MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1
sahilmgandhi 18:6a4db94011d3 2 /****************************************************************************************************//**
sahilmgandhi 18:6a4db94011d3 3 * @file nrf51.h
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
sahilmgandhi 18:6a4db94011d3 6 * nrf51 from Nordic Semiconductor.
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @version V522
sahilmgandhi 18:6a4db94011d3 9 * @date 23. February 2016
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * @note Generated with SVDConv V2.81d
sahilmgandhi 18:6a4db94011d3 12 * from CMSIS SVD File 'nrf51.svd' Version 522,
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * @par Copyright (c) 2013, Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 15 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 18 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * * Redistributions of source code must retain the above copyright notice, this
sahilmgandhi 18:6a4db94011d3 21 * list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * * Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 24 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 25 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
sahilmgandhi 18:6a4db94011d3 28 * contributors may be used to endorse or promote products derived from
sahilmgandhi 18:6a4db94011d3 29 * this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 41 *
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 *******************************************************************************************************/
sahilmgandhi 18:6a4db94011d3 44
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 /** @addtogroup Nordic Semiconductor
sahilmgandhi 18:6a4db94011d3 48 * @{
sahilmgandhi 18:6a4db94011d3 49 */
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /** @addtogroup nrf51
sahilmgandhi 18:6a4db94011d3 52 * @{
sahilmgandhi 18:6a4db94011d3 53 */
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #ifndef NRF51_H
sahilmgandhi 18:6a4db94011d3 56 #define NRF51_H
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 59 extern "C" {
sahilmgandhi 18:6a4db94011d3 60 #endif
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /* ------------------------- Interrupt Number Definition ------------------------ */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 typedef enum {
sahilmgandhi 18:6a4db94011d3 66 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
sahilmgandhi 18:6a4db94011d3 67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
sahilmgandhi 18:6a4db94011d3 69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 70 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
sahilmgandhi 18:6a4db94011d3 71 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
sahilmgandhi 18:6a4db94011d3 72 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
sahilmgandhi 18:6a4db94011d3 73 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
sahilmgandhi 18:6a4db94011d3 74 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
sahilmgandhi 18:6a4db94011d3 75 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
sahilmgandhi 18:6a4db94011d3 76 RADIO_IRQn = 1, /*!< 1 RADIO */
sahilmgandhi 18:6a4db94011d3 77 UART0_IRQn = 2, /*!< 2 UART0 */
sahilmgandhi 18:6a4db94011d3 78 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
sahilmgandhi 18:6a4db94011d3 79 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
sahilmgandhi 18:6a4db94011d3 80 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
sahilmgandhi 18:6a4db94011d3 81 ADC_IRQn = 7, /*!< 7 ADC */
sahilmgandhi 18:6a4db94011d3 82 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
sahilmgandhi 18:6a4db94011d3 83 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
sahilmgandhi 18:6a4db94011d3 84 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
sahilmgandhi 18:6a4db94011d3 85 RTC0_IRQn = 11, /*!< 11 RTC0 */
sahilmgandhi 18:6a4db94011d3 86 TEMP_IRQn = 12, /*!< 12 TEMP */
sahilmgandhi 18:6a4db94011d3 87 RNG_IRQn = 13, /*!< 13 RNG */
sahilmgandhi 18:6a4db94011d3 88 ECB_IRQn = 14, /*!< 14 ECB */
sahilmgandhi 18:6a4db94011d3 89 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
sahilmgandhi 18:6a4db94011d3 90 WDT_IRQn = 16, /*!< 16 WDT */
sahilmgandhi 18:6a4db94011d3 91 RTC1_IRQn = 17, /*!< 17 RTC1 */
sahilmgandhi 18:6a4db94011d3 92 QDEC_IRQn = 18, /*!< 18 QDEC */
sahilmgandhi 18:6a4db94011d3 93 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
sahilmgandhi 18:6a4db94011d3 94 SWI0_IRQn = 20, /*!< 20 SWI0 */
sahilmgandhi 18:6a4db94011d3 95 SWI1_IRQn = 21, /*!< 21 SWI1 */
sahilmgandhi 18:6a4db94011d3 96 SWI2_IRQn = 22, /*!< 22 SWI2 */
sahilmgandhi 18:6a4db94011d3 97 SWI3_IRQn = 23, /*!< 23 SWI3 */
sahilmgandhi 18:6a4db94011d3 98 SWI4_IRQn = 24, /*!< 24 SWI4 */
sahilmgandhi 18:6a4db94011d3 99 SWI5_IRQn = 25 /*!< 25 SWI5 */
sahilmgandhi 18:6a4db94011d3 100 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 /** @addtogroup Configuration_of_CMSIS
sahilmgandhi 18:6a4db94011d3 104 * @{
sahilmgandhi 18:6a4db94011d3 105 */
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 109 /* ================ Processor and Core Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 110 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
sahilmgandhi 18:6a4db94011d3 113 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
sahilmgandhi 18:6a4db94011d3 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
sahilmgandhi 18:6a4db94011d3 115 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 117 /** @} */ /* End of group Configuration_of_CMSIS */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 120 #include "system_nrf51.h" /*!< nrf51 System */
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 124 /* ================ Device Specific Peripheral Section ================ */
sahilmgandhi 18:6a4db94011d3 125 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /** @addtogroup Device_Peripheral_Registers
sahilmgandhi 18:6a4db94011d3 129 * @{
sahilmgandhi 18:6a4db94011d3 130 */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /* ------------------- Start of section using anonymous unions ------------------ */
sahilmgandhi 18:6a4db94011d3 134 #if defined(__CC_ARM)
sahilmgandhi 18:6a4db94011d3 135 #pragma push
sahilmgandhi 18:6a4db94011d3 136 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 137 #elif defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 138 #pragma language=extended
sahilmgandhi 18:6a4db94011d3 139 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 140 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 141 #elif defined(__TMS470__)
sahilmgandhi 18:6a4db94011d3 142 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 143 #elif defined(__TASKING__)
sahilmgandhi 18:6a4db94011d3 144 #pragma warning 586
sahilmgandhi 18:6a4db94011d3 145 #else
sahilmgandhi 18:6a4db94011d3 146 #warning Not supported compiler type
sahilmgandhi 18:6a4db94011d3 147 #endif
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 typedef struct {
sahilmgandhi 18:6a4db94011d3 151 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
sahilmgandhi 18:6a4db94011d3 152 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
sahilmgandhi 18:6a4db94011d3 153 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
sahilmgandhi 18:6a4db94011d3 154 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
sahilmgandhi 18:6a4db94011d3 155 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
sahilmgandhi 18:6a4db94011d3 156 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
sahilmgandhi 18:6a4db94011d3 157 } AMLI_RAMPRI_Type;
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 typedef struct {
sahilmgandhi 18:6a4db94011d3 160 __IO uint32_t SCK; /*!< Pin select for SCK. */
sahilmgandhi 18:6a4db94011d3 161 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
sahilmgandhi 18:6a4db94011d3 162 __IO uint32_t MISO; /*!< Pin select for MISO. */
sahilmgandhi 18:6a4db94011d3 163 } SPIM_PSEL_Type;
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 typedef struct {
sahilmgandhi 18:6a4db94011d3 166 __IO uint32_t PTR; /*!< Data pointer. */
sahilmgandhi 18:6a4db94011d3 167 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
sahilmgandhi 18:6a4db94011d3 168 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
sahilmgandhi 18:6a4db94011d3 169 } SPIM_RXD_Type;
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 typedef struct {
sahilmgandhi 18:6a4db94011d3 172 __IO uint32_t PTR; /*!< Data pointer. */
sahilmgandhi 18:6a4db94011d3 173 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
sahilmgandhi 18:6a4db94011d3 174 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
sahilmgandhi 18:6a4db94011d3 175 } SPIM_TXD_Type;
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 typedef struct {
sahilmgandhi 18:6a4db94011d3 178 __O uint32_t EN; /*!< Enable channel group. */
sahilmgandhi 18:6a4db94011d3 179 __O uint32_t DIS; /*!< Disable channel group. */
sahilmgandhi 18:6a4db94011d3 180 } PPI_TASKS_CHG_Type;
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 typedef struct {
sahilmgandhi 18:6a4db94011d3 183 __IO uint32_t EEP; /*!< Channel event end-point. */
sahilmgandhi 18:6a4db94011d3 184 __IO uint32_t TEP; /*!< Channel task end-point. */
sahilmgandhi 18:6a4db94011d3 185 } PPI_CH_Type;
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 189 /* ================ POWER ================ */
sahilmgandhi 18:6a4db94011d3 190 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /**
sahilmgandhi 18:6a4db94011d3 194 * @brief Power Control. (POWER)
sahilmgandhi 18:6a4db94011d3 195 */
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 typedef struct { /*!< POWER Structure */
sahilmgandhi 18:6a4db94011d3 198 __I uint32_t RESERVED0[30];
sahilmgandhi 18:6a4db94011d3 199 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
sahilmgandhi 18:6a4db94011d3 200 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
sahilmgandhi 18:6a4db94011d3 201 __I uint32_t RESERVED1[34];
sahilmgandhi 18:6a4db94011d3 202 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
sahilmgandhi 18:6a4db94011d3 203 __I uint32_t RESERVED2[126];
sahilmgandhi 18:6a4db94011d3 204 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 205 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 206 __I uint32_t RESERVED3[61];
sahilmgandhi 18:6a4db94011d3 207 __IO uint32_t RESETREAS; /*!< Reset reason. */
sahilmgandhi 18:6a4db94011d3 208 __I uint32_t RESERVED4[9];
sahilmgandhi 18:6a4db94011d3 209 __I uint32_t RAMSTATUS; /*!< Ram status register. */
sahilmgandhi 18:6a4db94011d3 210 __I uint32_t RESERVED5[53];
sahilmgandhi 18:6a4db94011d3 211 __O uint32_t SYSTEMOFF; /*!< System off register. */
sahilmgandhi 18:6a4db94011d3 212 __I uint32_t RESERVED6[3];
sahilmgandhi 18:6a4db94011d3 213 __IO uint32_t POFCON; /*!< Power failure configuration. */
sahilmgandhi 18:6a4db94011d3 214 __I uint32_t RESERVED7[2];
sahilmgandhi 18:6a4db94011d3 215 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
sahilmgandhi 18:6a4db94011d3 216 register. */
sahilmgandhi 18:6a4db94011d3 217 __I uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 218 __IO uint32_t RAMON; /*!< Ram on/off. */
sahilmgandhi 18:6a4db94011d3 219 __I uint32_t RESERVED9[7];
sahilmgandhi 18:6a4db94011d3 220 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
sahilmgandhi 18:6a4db94011d3 221 is a retained register. */
sahilmgandhi 18:6a4db94011d3 222 __I uint32_t RESERVED10[3];
sahilmgandhi 18:6a4db94011d3 223 __IO uint32_t RAMONB; /*!< Ram on/off. */
sahilmgandhi 18:6a4db94011d3 224 __I uint32_t RESERVED11[8];
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
sahilmgandhi 18:6a4db94011d3 226 __I uint32_t RESERVED12[291];
sahilmgandhi 18:6a4db94011d3 227 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
sahilmgandhi 18:6a4db94011d3 228 } NRF_POWER_Type;
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 232 /* ================ CLOCK ================ */
sahilmgandhi 18:6a4db94011d3 233 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 /**
sahilmgandhi 18:6a4db94011d3 237 * @brief Clock control. (CLOCK)
sahilmgandhi 18:6a4db94011d3 238 */
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 typedef struct { /*!< CLOCK Structure */
sahilmgandhi 18:6a4db94011d3 241 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
sahilmgandhi 18:6a4db94011d3 242 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
sahilmgandhi 18:6a4db94011d3 243 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
sahilmgandhi 18:6a4db94011d3 244 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
sahilmgandhi 18:6a4db94011d3 245 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
sahilmgandhi 18:6a4db94011d3 246 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
sahilmgandhi 18:6a4db94011d3 247 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
sahilmgandhi 18:6a4db94011d3 248 __I uint32_t RESERVED0[57];
sahilmgandhi 18:6a4db94011d3 249 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
sahilmgandhi 18:6a4db94011d3 250 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
sahilmgandhi 18:6a4db94011d3 251 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 252 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
sahilmgandhi 18:6a4db94011d3 253 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
sahilmgandhi 18:6a4db94011d3 254 __I uint32_t RESERVED2[124];
sahilmgandhi 18:6a4db94011d3 255 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 256 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 257 __I uint32_t RESERVED3[63];
sahilmgandhi 18:6a4db94011d3 258 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
sahilmgandhi 18:6a4db94011d3 259 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
sahilmgandhi 18:6a4db94011d3 260 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 261 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
sahilmgandhi 18:6a4db94011d3 262 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
sahilmgandhi 18:6a4db94011d3 263 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
sahilmgandhi 18:6a4db94011d3 264 triggered. */
sahilmgandhi 18:6a4db94011d3 265 __I uint32_t RESERVED5[62];
sahilmgandhi 18:6a4db94011d3 266 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
sahilmgandhi 18:6a4db94011d3 267 __I uint32_t RESERVED6[7];
sahilmgandhi 18:6a4db94011d3 268 __IO uint32_t CTIV; /*!< Calibration timer interval. */
sahilmgandhi 18:6a4db94011d3 269 __I uint32_t RESERVED7[5];
sahilmgandhi 18:6a4db94011d3 270 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
sahilmgandhi 18:6a4db94011d3 271 } NRF_CLOCK_Type;
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 275 /* ================ MPU ================ */
sahilmgandhi 18:6a4db94011d3 276 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /**
sahilmgandhi 18:6a4db94011d3 280 * @brief Memory Protection Unit. (MPU)
sahilmgandhi 18:6a4db94011d3 281 */
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 typedef struct { /*!< MPU Structure */
sahilmgandhi 18:6a4db94011d3 284 __I uint32_t RESERVED0[330];
sahilmgandhi 18:6a4db94011d3 285 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
sahilmgandhi 18:6a4db94011d3 286 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
sahilmgandhi 18:6a4db94011d3 287 __I uint32_t RESERVED1[52];
sahilmgandhi 18:6a4db94011d3 288 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
sahilmgandhi 18:6a4db94011d3 289 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
sahilmgandhi 18:6a4db94011d3 290 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
sahilmgandhi 18:6a4db94011d3 291 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
sahilmgandhi 18:6a4db94011d3 292 } NRF_MPU_Type;
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 296 /* ================ AMLI ================ */
sahilmgandhi 18:6a4db94011d3 297 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 /**
sahilmgandhi 18:6a4db94011d3 301 * @brief AHB Multi-Layer Interface. (AMLI)
sahilmgandhi 18:6a4db94011d3 302 */
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 typedef struct { /*!< AMLI Structure */
sahilmgandhi 18:6a4db94011d3 305 __I uint32_t RESERVED0[896];
sahilmgandhi 18:6a4db94011d3 306 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
sahilmgandhi 18:6a4db94011d3 307 } NRF_AMLI_Type;
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 311 /* ================ RADIO ================ */
sahilmgandhi 18:6a4db94011d3 312 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 /**
sahilmgandhi 18:6a4db94011d3 316 * @brief The radio. (RADIO)
sahilmgandhi 18:6a4db94011d3 317 */
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 typedef struct { /*!< RADIO Structure */
sahilmgandhi 18:6a4db94011d3 320 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
sahilmgandhi 18:6a4db94011d3 321 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
sahilmgandhi 18:6a4db94011d3 322 __O uint32_t TASKS_START; /*!< Start radio. */
sahilmgandhi 18:6a4db94011d3 323 __O uint32_t TASKS_STOP; /*!< Stop radio. */
sahilmgandhi 18:6a4db94011d3 324 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
sahilmgandhi 18:6a4db94011d3 325 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
sahilmgandhi 18:6a4db94011d3 326 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
sahilmgandhi 18:6a4db94011d3 327 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
sahilmgandhi 18:6a4db94011d3 328 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
sahilmgandhi 18:6a4db94011d3 329 __I uint32_t RESERVED0[55];
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t EVENTS_READY; /*!< Ready event. */
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
sahilmgandhi 18:6a4db94011d3 332 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
sahilmgandhi 18:6a4db94011d3 333 __IO uint32_t EVENTS_END; /*!< End event. */
sahilmgandhi 18:6a4db94011d3 334 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
sahilmgandhi 18:6a4db94011d3 335 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
sahilmgandhi 18:6a4db94011d3 336 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
sahilmgandhi 18:6a4db94011d3 337 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
sahilmgandhi 18:6a4db94011d3 338 sample is ready for readout at the RSSISAMPLE register. */
sahilmgandhi 18:6a4db94011d3 339 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 340 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
sahilmgandhi 18:6a4db94011d3 341 __I uint32_t RESERVED2[53];
sahilmgandhi 18:6a4db94011d3 342 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
sahilmgandhi 18:6a4db94011d3 343 __I uint32_t RESERVED3[64];
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 346 __I uint32_t RESERVED4[61];
sahilmgandhi 18:6a4db94011d3 347 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
sahilmgandhi 18:6a4db94011d3 348 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 349 __I uint32_t RXMATCH; /*!< Received address. */
sahilmgandhi 18:6a4db94011d3 350 __I uint32_t RXCRC; /*!< Received CRC. */
sahilmgandhi 18:6a4db94011d3 351 __I uint32_t DAI; /*!< Device address match index. */
sahilmgandhi 18:6a4db94011d3 352 __I uint32_t RESERVED6[60];
sahilmgandhi 18:6a4db94011d3 353 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 354 __IO uint32_t FREQUENCY; /*!< Frequency. */
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t TXPOWER; /*!< Output power. */
sahilmgandhi 18:6a4db94011d3 356 __IO uint32_t MODE; /*!< Data rate and modulation. */
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t CRCCNF; /*!< CRC configuration. */
sahilmgandhi 18:6a4db94011d3 366 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
sahilmgandhi 18:6a4db94011d3 367 __IO uint32_t CRCINIT; /*!< CRC initial value. */
sahilmgandhi 18:6a4db94011d3 368 __IO uint32_t TEST; /*!< Test features enable register. */
sahilmgandhi 18:6a4db94011d3 369 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
sahilmgandhi 18:6a4db94011d3 370 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
sahilmgandhi 18:6a4db94011d3 371 __I uint32_t RESERVED7;
sahilmgandhi 18:6a4db94011d3 372 __I uint32_t STATE; /*!< Current radio state. */
sahilmgandhi 18:6a4db94011d3 373 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
sahilmgandhi 18:6a4db94011d3 374 __I uint32_t RESERVED8[2];
sahilmgandhi 18:6a4db94011d3 375 __IO uint32_t BCC; /*!< Bit counter compare. */
sahilmgandhi 18:6a4db94011d3 376 __I uint32_t RESERVED9[39];
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t DAB[8]; /*!< Device address base segment. */
sahilmgandhi 18:6a4db94011d3 378 __IO uint32_t DAP[8]; /*!< Device address prefix. */
sahilmgandhi 18:6a4db94011d3 379 __IO uint32_t DACNF; /*!< Device address match configuration. */
sahilmgandhi 18:6a4db94011d3 380 __I uint32_t RESERVED10[56];
sahilmgandhi 18:6a4db94011d3 381 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
sahilmgandhi 18:6a4db94011d3 382 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
sahilmgandhi 18:6a4db94011d3 383 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
sahilmgandhi 18:6a4db94011d3 384 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
sahilmgandhi 18:6a4db94011d3 385 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
sahilmgandhi 18:6a4db94011d3 386 __I uint32_t RESERVED11[561];
sahilmgandhi 18:6a4db94011d3 387 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 388 } NRF_RADIO_Type;
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 392 /* ================ UART ================ */
sahilmgandhi 18:6a4db94011d3 393 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 /**
sahilmgandhi 18:6a4db94011d3 397 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
sahilmgandhi 18:6a4db94011d3 398 */
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 typedef struct { /*!< UART Structure */
sahilmgandhi 18:6a4db94011d3 401 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
sahilmgandhi 18:6a4db94011d3 402 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
sahilmgandhi 18:6a4db94011d3 403 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
sahilmgandhi 18:6a4db94011d3 404 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
sahilmgandhi 18:6a4db94011d3 405 __I uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 406 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
sahilmgandhi 18:6a4db94011d3 407 __I uint32_t RESERVED1[56];
sahilmgandhi 18:6a4db94011d3 408 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
sahilmgandhi 18:6a4db94011d3 409 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
sahilmgandhi 18:6a4db94011d3 410 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
sahilmgandhi 18:6a4db94011d3 411 __I uint32_t RESERVED2[4];
sahilmgandhi 18:6a4db94011d3 412 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
sahilmgandhi 18:6a4db94011d3 413 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 414 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
sahilmgandhi 18:6a4db94011d3 415 __I uint32_t RESERVED4[7];
sahilmgandhi 18:6a4db94011d3 416 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
sahilmgandhi 18:6a4db94011d3 417 __I uint32_t RESERVED5[46];
sahilmgandhi 18:6a4db94011d3 418 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
sahilmgandhi 18:6a4db94011d3 419 __I uint32_t RESERVED6[64];
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 421 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 422 __I uint32_t RESERVED7[93];
sahilmgandhi 18:6a4db94011d3 423 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
sahilmgandhi 18:6a4db94011d3 424 __I uint32_t RESERVED8[31];
sahilmgandhi 18:6a4db94011d3 425 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
sahilmgandhi 18:6a4db94011d3 426 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 427 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
sahilmgandhi 18:6a4db94011d3 428 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
sahilmgandhi 18:6a4db94011d3 429 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
sahilmgandhi 18:6a4db94011d3 430 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
sahilmgandhi 18:6a4db94011d3 431 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
sahilmgandhi 18:6a4db94011d3 432 Once read the character is consumed. If read when no character
sahilmgandhi 18:6a4db94011d3 433 available, the UART will stop working. */
sahilmgandhi 18:6a4db94011d3 434 __O uint32_t TXD; /*!< TXD register. */
sahilmgandhi 18:6a4db94011d3 435 __I uint32_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 436 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
sahilmgandhi 18:6a4db94011d3 437 __I uint32_t RESERVED11[17];
sahilmgandhi 18:6a4db94011d3 438 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
sahilmgandhi 18:6a4db94011d3 439 __I uint32_t RESERVED12[675];
sahilmgandhi 18:6a4db94011d3 440 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 441 } NRF_UART_Type;
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 445 /* ================ SPI ================ */
sahilmgandhi 18:6a4db94011d3 446 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /**
sahilmgandhi 18:6a4db94011d3 450 * @brief SPI master 0. (SPI)
sahilmgandhi 18:6a4db94011d3 451 */
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 typedef struct { /*!< SPI Structure */
sahilmgandhi 18:6a4db94011d3 454 __I uint32_t RESERVED0[66];
sahilmgandhi 18:6a4db94011d3 455 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
sahilmgandhi 18:6a4db94011d3 456 __I uint32_t RESERVED1[126];
sahilmgandhi 18:6a4db94011d3 457 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 458 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 459 __I uint32_t RESERVED2[125];
sahilmgandhi 18:6a4db94011d3 460 __IO uint32_t ENABLE; /*!< Enable SPI. */
sahilmgandhi 18:6a4db94011d3 461 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 462 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
sahilmgandhi 18:6a4db94011d3 463 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
sahilmgandhi 18:6a4db94011d3 464 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
sahilmgandhi 18:6a4db94011d3 465 __I uint32_t RESERVED4;
sahilmgandhi 18:6a4db94011d3 466 __I uint32_t RXD; /*!< RX data. */
sahilmgandhi 18:6a4db94011d3 467 __IO uint32_t TXD; /*!< TX data. */
sahilmgandhi 18:6a4db94011d3 468 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 469 __IO uint32_t FREQUENCY; /*!< SPI frequency */
sahilmgandhi 18:6a4db94011d3 470 __I uint32_t RESERVED6[11];
sahilmgandhi 18:6a4db94011d3 471 __IO uint32_t CONFIG; /*!< Configuration register. */
sahilmgandhi 18:6a4db94011d3 472 __I uint32_t RESERVED7[681];
sahilmgandhi 18:6a4db94011d3 473 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 474 } NRF_SPI_Type;
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 478 /* ================ TWI ================ */
sahilmgandhi 18:6a4db94011d3 479 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481
sahilmgandhi 18:6a4db94011d3 482 /**
sahilmgandhi 18:6a4db94011d3 483 * @brief Two-wire interface master 0. (TWI)
sahilmgandhi 18:6a4db94011d3 484 */
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 typedef struct { /*!< TWI Structure */
sahilmgandhi 18:6a4db94011d3 487 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
sahilmgandhi 18:6a4db94011d3 488 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 489 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
sahilmgandhi 18:6a4db94011d3 490 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 491 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
sahilmgandhi 18:6a4db94011d3 492 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 493 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
sahilmgandhi 18:6a4db94011d3 494 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
sahilmgandhi 18:6a4db94011d3 495 __I uint32_t RESERVED3[56];
sahilmgandhi 18:6a4db94011d3 496 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
sahilmgandhi 18:6a4db94011d3 497 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
sahilmgandhi 18:6a4db94011d3 498 __I uint32_t RESERVED4[4];
sahilmgandhi 18:6a4db94011d3 499 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
sahilmgandhi 18:6a4db94011d3 500 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 501 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
sahilmgandhi 18:6a4db94011d3 502 __I uint32_t RESERVED6[4];
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
sahilmgandhi 18:6a4db94011d3 504 __I uint32_t RESERVED7[3];
sahilmgandhi 18:6a4db94011d3 505 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
sahilmgandhi 18:6a4db94011d3 506 __I uint32_t RESERVED8[45];
sahilmgandhi 18:6a4db94011d3 507 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
sahilmgandhi 18:6a4db94011d3 508 __I uint32_t RESERVED9[64];
sahilmgandhi 18:6a4db94011d3 509 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 510 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 511 __I uint32_t RESERVED10[110];
sahilmgandhi 18:6a4db94011d3 512 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
sahilmgandhi 18:6a4db94011d3 513 __I uint32_t RESERVED11[14];
sahilmgandhi 18:6a4db94011d3 514 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
sahilmgandhi 18:6a4db94011d3 515 __I uint32_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 516 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
sahilmgandhi 18:6a4db94011d3 517 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
sahilmgandhi 18:6a4db94011d3 518 __I uint32_t RESERVED13[2];
sahilmgandhi 18:6a4db94011d3 519 __I uint32_t RXD; /*!< RX data register. */
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t TXD; /*!< TX data register. */
sahilmgandhi 18:6a4db94011d3 521 __I uint32_t RESERVED14;
sahilmgandhi 18:6a4db94011d3 522 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
sahilmgandhi 18:6a4db94011d3 523 __I uint32_t RESERVED15[24];
sahilmgandhi 18:6a4db94011d3 524 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
sahilmgandhi 18:6a4db94011d3 525 __I uint32_t RESERVED16[668];
sahilmgandhi 18:6a4db94011d3 526 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 527 } NRF_TWI_Type;
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 531 /* ================ SPIS ================ */
sahilmgandhi 18:6a4db94011d3 532 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535 /**
sahilmgandhi 18:6a4db94011d3 536 * @brief SPI slave 1. (SPIS)
sahilmgandhi 18:6a4db94011d3 537 */
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 typedef struct { /*!< SPIS Structure */
sahilmgandhi 18:6a4db94011d3 540 __I uint32_t RESERVED0[9];
sahilmgandhi 18:6a4db94011d3 541 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
sahilmgandhi 18:6a4db94011d3 542 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
sahilmgandhi 18:6a4db94011d3 543 __I uint32_t RESERVED1[54];
sahilmgandhi 18:6a4db94011d3 544 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
sahilmgandhi 18:6a4db94011d3 545 __I uint32_t RESERVED2[2];
sahilmgandhi 18:6a4db94011d3 546 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
sahilmgandhi 18:6a4db94011d3 547 __I uint32_t RESERVED3[5];
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
sahilmgandhi 18:6a4db94011d3 549 __I uint32_t RESERVED4[53];
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
sahilmgandhi 18:6a4db94011d3 551 __I uint32_t RESERVED5[64];
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 554 __I uint32_t RESERVED6[61];
sahilmgandhi 18:6a4db94011d3 555 __I uint32_t SEMSTAT; /*!< Semaphore status. */
sahilmgandhi 18:6a4db94011d3 556 __I uint32_t RESERVED7[15];
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t STATUS; /*!< Status from last transaction. */
sahilmgandhi 18:6a4db94011d3 558 __I uint32_t RESERVED8[47];
sahilmgandhi 18:6a4db94011d3 559 __IO uint32_t ENABLE; /*!< Enable SPIS. */
sahilmgandhi 18:6a4db94011d3 560 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 561 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
sahilmgandhi 18:6a4db94011d3 562 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
sahilmgandhi 18:6a4db94011d3 563 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
sahilmgandhi 18:6a4db94011d3 564 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
sahilmgandhi 18:6a4db94011d3 565 __I uint32_t RESERVED10[7];
sahilmgandhi 18:6a4db94011d3 566 __IO uint32_t RXDPTR; /*!< RX data pointer. */
sahilmgandhi 18:6a4db94011d3 567 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
sahilmgandhi 18:6a4db94011d3 568 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
sahilmgandhi 18:6a4db94011d3 569 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 570 __IO uint32_t TXDPTR; /*!< TX data pointer. */
sahilmgandhi 18:6a4db94011d3 571 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
sahilmgandhi 18:6a4db94011d3 572 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
sahilmgandhi 18:6a4db94011d3 573 __I uint32_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 574 __IO uint32_t CONFIG; /*!< Configuration register. */
sahilmgandhi 18:6a4db94011d3 575 __I uint32_t RESERVED13;
sahilmgandhi 18:6a4db94011d3 576 __IO uint32_t DEF; /*!< Default character. */
sahilmgandhi 18:6a4db94011d3 577 __I uint32_t RESERVED14[24];
sahilmgandhi 18:6a4db94011d3 578 __IO uint32_t ORC; /*!< Over-read character. */
sahilmgandhi 18:6a4db94011d3 579 __I uint32_t RESERVED15[654];
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 581 } NRF_SPIS_Type;
sahilmgandhi 18:6a4db94011d3 582
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 585 /* ================ SPIM ================ */
sahilmgandhi 18:6a4db94011d3 586 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 587
sahilmgandhi 18:6a4db94011d3 588
sahilmgandhi 18:6a4db94011d3 589 /**
sahilmgandhi 18:6a4db94011d3 590 * @brief SPI master with easyDMA 1. (SPIM)
sahilmgandhi 18:6a4db94011d3 591 */
sahilmgandhi 18:6a4db94011d3 592
sahilmgandhi 18:6a4db94011d3 593 typedef struct { /*!< SPIM Structure */
sahilmgandhi 18:6a4db94011d3 594 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 595 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
sahilmgandhi 18:6a4db94011d3 596 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
sahilmgandhi 18:6a4db94011d3 597 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 598 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
sahilmgandhi 18:6a4db94011d3 599 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
sahilmgandhi 18:6a4db94011d3 600 __I uint32_t RESERVED2[56];
sahilmgandhi 18:6a4db94011d3 601 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
sahilmgandhi 18:6a4db94011d3 602 __I uint32_t RESERVED3[2];
sahilmgandhi 18:6a4db94011d3 603 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
sahilmgandhi 18:6a4db94011d3 604 __I uint32_t RESERVED4[3];
sahilmgandhi 18:6a4db94011d3 605 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
sahilmgandhi 18:6a4db94011d3 606 __I uint32_t RESERVED5[10];
sahilmgandhi 18:6a4db94011d3 607 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
sahilmgandhi 18:6a4db94011d3 608 __I uint32_t RESERVED6[109];
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 610 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 611 __I uint32_t RESERVED7[125];
sahilmgandhi 18:6a4db94011d3 612 __IO uint32_t ENABLE; /*!< Enable SPIM. */
sahilmgandhi 18:6a4db94011d3 613 __I uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 614 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
sahilmgandhi 18:6a4db94011d3 615 __I uint32_t RESERVED9[4];
sahilmgandhi 18:6a4db94011d3 616 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
sahilmgandhi 18:6a4db94011d3 617 __I uint32_t RESERVED10[3];
sahilmgandhi 18:6a4db94011d3 618 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
sahilmgandhi 18:6a4db94011d3 619 __I uint32_t RESERVED11;
sahilmgandhi 18:6a4db94011d3 620 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
sahilmgandhi 18:6a4db94011d3 621 __I uint32_t RESERVED12;
sahilmgandhi 18:6a4db94011d3 622 __IO uint32_t CONFIG; /*!< Configuration register. */
sahilmgandhi 18:6a4db94011d3 623 __I uint32_t RESERVED13[26];
sahilmgandhi 18:6a4db94011d3 624 __IO uint32_t ORC; /*!< Over-read character. */
sahilmgandhi 18:6a4db94011d3 625 __I uint32_t RESERVED14[654];
sahilmgandhi 18:6a4db94011d3 626 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 627 } NRF_SPIM_Type;
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629
sahilmgandhi 18:6a4db94011d3 630 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 631 /* ================ GPIOTE ================ */
sahilmgandhi 18:6a4db94011d3 632 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 633
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 /**
sahilmgandhi 18:6a4db94011d3 636 * @brief GPIO tasks and events. (GPIOTE)
sahilmgandhi 18:6a4db94011d3 637 */
sahilmgandhi 18:6a4db94011d3 638
sahilmgandhi 18:6a4db94011d3 639 typedef struct { /*!< GPIOTE Structure */
sahilmgandhi 18:6a4db94011d3 640 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
sahilmgandhi 18:6a4db94011d3 641 __I uint32_t RESERVED0[60];
sahilmgandhi 18:6a4db94011d3 642 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
sahilmgandhi 18:6a4db94011d3 643 __I uint32_t RESERVED1[27];
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
sahilmgandhi 18:6a4db94011d3 645 __I uint32_t RESERVED2[97];
sahilmgandhi 18:6a4db94011d3 646 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 647 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 648 __I uint32_t RESERVED3[129];
sahilmgandhi 18:6a4db94011d3 649 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
sahilmgandhi 18:6a4db94011d3 650 __I uint32_t RESERVED4[695];
sahilmgandhi 18:6a4db94011d3 651 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 652 } NRF_GPIOTE_Type;
sahilmgandhi 18:6a4db94011d3 653
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 656 /* ================ ADC ================ */
sahilmgandhi 18:6a4db94011d3 657 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659
sahilmgandhi 18:6a4db94011d3 660 /**
sahilmgandhi 18:6a4db94011d3 661 * @brief Analog to digital converter. (ADC)
sahilmgandhi 18:6a4db94011d3 662 */
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 typedef struct { /*!< ADC Structure */
sahilmgandhi 18:6a4db94011d3 665 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
sahilmgandhi 18:6a4db94011d3 666 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
sahilmgandhi 18:6a4db94011d3 667 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 668 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
sahilmgandhi 18:6a4db94011d3 669 __I uint32_t RESERVED1[128];
sahilmgandhi 18:6a4db94011d3 670 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 671 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 672 __I uint32_t RESERVED2[61];
sahilmgandhi 18:6a4db94011d3 673 __I uint32_t BUSY; /*!< ADC busy register. */
sahilmgandhi 18:6a4db94011d3 674 __I uint32_t RESERVED3[63];
sahilmgandhi 18:6a4db94011d3 675 __IO uint32_t ENABLE; /*!< ADC enable. */
sahilmgandhi 18:6a4db94011d3 676 __IO uint32_t CONFIG; /*!< ADC configuration register. */
sahilmgandhi 18:6a4db94011d3 677 __I uint32_t RESULT; /*!< Result of ADC conversion. */
sahilmgandhi 18:6a4db94011d3 678 __I uint32_t RESERVED4[700];
sahilmgandhi 18:6a4db94011d3 679 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 680 } NRF_ADC_Type;
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682
sahilmgandhi 18:6a4db94011d3 683 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 684 /* ================ TIMER ================ */
sahilmgandhi 18:6a4db94011d3 685 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 686
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 /**
sahilmgandhi 18:6a4db94011d3 689 * @brief Timer 0. (TIMER)
sahilmgandhi 18:6a4db94011d3 690 */
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692 typedef struct { /*!< TIMER Structure */
sahilmgandhi 18:6a4db94011d3 693 __O uint32_t TASKS_START; /*!< Start Timer. */
sahilmgandhi 18:6a4db94011d3 694 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
sahilmgandhi 18:6a4db94011d3 695 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
sahilmgandhi 18:6a4db94011d3 696 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
sahilmgandhi 18:6a4db94011d3 697 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
sahilmgandhi 18:6a4db94011d3 698 __I uint32_t RESERVED0[11];
sahilmgandhi 18:6a4db94011d3 699 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
sahilmgandhi 18:6a4db94011d3 700 __I uint32_t RESERVED1[60];
sahilmgandhi 18:6a4db94011d3 701 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
sahilmgandhi 18:6a4db94011d3 702 __I uint32_t RESERVED2[44];
sahilmgandhi 18:6a4db94011d3 703 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
sahilmgandhi 18:6a4db94011d3 704 __I uint32_t RESERVED3[64];
sahilmgandhi 18:6a4db94011d3 705 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 706 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 707 __I uint32_t RESERVED4[126];
sahilmgandhi 18:6a4db94011d3 708 __IO uint32_t MODE; /*!< Timer Mode selection. */
sahilmgandhi 18:6a4db94011d3 709 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
sahilmgandhi 18:6a4db94011d3 710 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 711 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
sahilmgandhi 18:6a4db94011d3 712 clock frequency is divided by 2^SCALE. */
sahilmgandhi 18:6a4db94011d3 713 __I uint32_t RESERVED6[11];
sahilmgandhi 18:6a4db94011d3 714 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
sahilmgandhi 18:6a4db94011d3 715 __I uint32_t RESERVED7[683];
sahilmgandhi 18:6a4db94011d3 716 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 717 } NRF_TIMER_Type;
sahilmgandhi 18:6a4db94011d3 718
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 721 /* ================ RTC ================ */
sahilmgandhi 18:6a4db94011d3 722 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724
sahilmgandhi 18:6a4db94011d3 725 /**
sahilmgandhi 18:6a4db94011d3 726 * @brief Real time counter 0. (RTC)
sahilmgandhi 18:6a4db94011d3 727 */
sahilmgandhi 18:6a4db94011d3 728
sahilmgandhi 18:6a4db94011d3 729 typedef struct { /*!< RTC Structure */
sahilmgandhi 18:6a4db94011d3 730 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
sahilmgandhi 18:6a4db94011d3 731 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
sahilmgandhi 18:6a4db94011d3 732 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
sahilmgandhi 18:6a4db94011d3 733 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
sahilmgandhi 18:6a4db94011d3 734 __I uint32_t RESERVED0[60];
sahilmgandhi 18:6a4db94011d3 735 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
sahilmgandhi 18:6a4db94011d3 736 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
sahilmgandhi 18:6a4db94011d3 737 __I uint32_t RESERVED1[14];
sahilmgandhi 18:6a4db94011d3 738 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
sahilmgandhi 18:6a4db94011d3 739 __I uint32_t RESERVED2[109];
sahilmgandhi 18:6a4db94011d3 740 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 741 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 742 __I uint32_t RESERVED3[13];
sahilmgandhi 18:6a4db94011d3 743 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
sahilmgandhi 18:6a4db94011d3 744 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
sahilmgandhi 18:6a4db94011d3 745 the value of EVTEN. */
sahilmgandhi 18:6a4db94011d3 746 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
sahilmgandhi 18:6a4db94011d3 747 gives the value of EVTEN. */
sahilmgandhi 18:6a4db94011d3 748 __I uint32_t RESERVED4[110];
sahilmgandhi 18:6a4db94011d3 749 __I uint32_t COUNTER; /*!< Current COUNTER value. */
sahilmgandhi 18:6a4db94011d3 750 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
sahilmgandhi 18:6a4db94011d3 751 Must be written when RTC is STOPed. */
sahilmgandhi 18:6a4db94011d3 752 __I uint32_t RESERVED5[13];
sahilmgandhi 18:6a4db94011d3 753 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
sahilmgandhi 18:6a4db94011d3 754 __I uint32_t RESERVED6[683];
sahilmgandhi 18:6a4db94011d3 755 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 756 } NRF_RTC_Type;
sahilmgandhi 18:6a4db94011d3 757
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 760 /* ================ TEMP ================ */
sahilmgandhi 18:6a4db94011d3 761 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763
sahilmgandhi 18:6a4db94011d3 764 /**
sahilmgandhi 18:6a4db94011d3 765 * @brief Temperature Sensor. (TEMP)
sahilmgandhi 18:6a4db94011d3 766 */
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 typedef struct { /*!< TEMP Structure */
sahilmgandhi 18:6a4db94011d3 769 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
sahilmgandhi 18:6a4db94011d3 770 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
sahilmgandhi 18:6a4db94011d3 771 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 772 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
sahilmgandhi 18:6a4db94011d3 773 __I uint32_t RESERVED1[128];
sahilmgandhi 18:6a4db94011d3 774 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 775 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 776 __I uint32_t RESERVED2[127];
sahilmgandhi 18:6a4db94011d3 777 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
sahilmgandhi 18:6a4db94011d3 778 __I uint32_t RESERVED3[700];
sahilmgandhi 18:6a4db94011d3 779 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 780 } NRF_TEMP_Type;
sahilmgandhi 18:6a4db94011d3 781
sahilmgandhi 18:6a4db94011d3 782
sahilmgandhi 18:6a4db94011d3 783 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 784 /* ================ RNG ================ */
sahilmgandhi 18:6a4db94011d3 785 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 786
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 /**
sahilmgandhi 18:6a4db94011d3 789 * @brief Random Number Generator. (RNG)
sahilmgandhi 18:6a4db94011d3 790 */
sahilmgandhi 18:6a4db94011d3 791
sahilmgandhi 18:6a4db94011d3 792 typedef struct { /*!< RNG Structure */
sahilmgandhi 18:6a4db94011d3 793 __O uint32_t TASKS_START; /*!< Start the random number generator. */
sahilmgandhi 18:6a4db94011d3 794 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
sahilmgandhi 18:6a4db94011d3 795 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 796 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
sahilmgandhi 18:6a4db94011d3 797 __I uint32_t RESERVED1[63];
sahilmgandhi 18:6a4db94011d3 798 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
sahilmgandhi 18:6a4db94011d3 799 __I uint32_t RESERVED2[64];
sahilmgandhi 18:6a4db94011d3 800 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
sahilmgandhi 18:6a4db94011d3 801 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
sahilmgandhi 18:6a4db94011d3 802 __I uint32_t RESERVED3[126];
sahilmgandhi 18:6a4db94011d3 803 __IO uint32_t CONFIG; /*!< Configuration register. */
sahilmgandhi 18:6a4db94011d3 804 __I uint32_t VALUE; /*!< RNG random number. */
sahilmgandhi 18:6a4db94011d3 805 __I uint32_t RESERVED4[700];
sahilmgandhi 18:6a4db94011d3 806 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 807 } NRF_RNG_Type;
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809
sahilmgandhi 18:6a4db94011d3 810 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 811 /* ================ ECB ================ */
sahilmgandhi 18:6a4db94011d3 812 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814
sahilmgandhi 18:6a4db94011d3 815 /**
sahilmgandhi 18:6a4db94011d3 816 * @brief AES ECB Mode Encryption. (ECB)
sahilmgandhi 18:6a4db94011d3 817 */
sahilmgandhi 18:6a4db94011d3 818
sahilmgandhi 18:6a4db94011d3 819 typedef struct { /*!< ECB Structure */
sahilmgandhi 18:6a4db94011d3 820 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
sahilmgandhi 18:6a4db94011d3 821 will not initiate a new encryption and the ERRORECB event will
sahilmgandhi 18:6a4db94011d3 822 be triggered. */
sahilmgandhi 18:6a4db94011d3 823 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
sahilmgandhi 18:6a4db94011d3 824 this will will trigger the ERRORECB event. */
sahilmgandhi 18:6a4db94011d3 825 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 826 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
sahilmgandhi 18:6a4db94011d3 827 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
sahilmgandhi 18:6a4db94011d3 828 error. */
sahilmgandhi 18:6a4db94011d3 829 __I uint32_t RESERVED1[127];
sahilmgandhi 18:6a4db94011d3 830 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 831 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 832 __I uint32_t RESERVED2[126];
sahilmgandhi 18:6a4db94011d3 833 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
sahilmgandhi 18:6a4db94011d3 834 __I uint32_t RESERVED3[701];
sahilmgandhi 18:6a4db94011d3 835 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 836 } NRF_ECB_Type;
sahilmgandhi 18:6a4db94011d3 837
sahilmgandhi 18:6a4db94011d3 838
sahilmgandhi 18:6a4db94011d3 839 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 840 /* ================ AAR ================ */
sahilmgandhi 18:6a4db94011d3 841 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843
sahilmgandhi 18:6a4db94011d3 844 /**
sahilmgandhi 18:6a4db94011d3 845 * @brief Accelerated Address Resolver. (AAR)
sahilmgandhi 18:6a4db94011d3 846 */
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 typedef struct { /*!< AAR Structure */
sahilmgandhi 18:6a4db94011d3 849 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
sahilmgandhi 18:6a4db94011d3 850 data structure. */
sahilmgandhi 18:6a4db94011d3 851 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 852 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
sahilmgandhi 18:6a4db94011d3 853 __I uint32_t RESERVED1[61];
sahilmgandhi 18:6a4db94011d3 854 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
sahilmgandhi 18:6a4db94011d3 855 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
sahilmgandhi 18:6a4db94011d3 856 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
sahilmgandhi 18:6a4db94011d3 857 __I uint32_t RESERVED2[126];
sahilmgandhi 18:6a4db94011d3 858 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 859 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 860 __I uint32_t RESERVED3[61];
sahilmgandhi 18:6a4db94011d3 861 __I uint32_t STATUS; /*!< Resolution status. */
sahilmgandhi 18:6a4db94011d3 862 __I uint32_t RESERVED4[63];
sahilmgandhi 18:6a4db94011d3 863 __IO uint32_t ENABLE; /*!< Enable AAR. */
sahilmgandhi 18:6a4db94011d3 864 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
sahilmgandhi 18:6a4db94011d3 865 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
sahilmgandhi 18:6a4db94011d3 866 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 867 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
sahilmgandhi 18:6a4db94011d3 868 __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
sahilmgandhi 18:6a4db94011d3 869 resolution. A minimum of 3 bytes must be reserved. */
sahilmgandhi 18:6a4db94011d3 870 __I uint32_t RESERVED6[697];
sahilmgandhi 18:6a4db94011d3 871 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 872 } NRF_AAR_Type;
sahilmgandhi 18:6a4db94011d3 873
sahilmgandhi 18:6a4db94011d3 874
sahilmgandhi 18:6a4db94011d3 875 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 876 /* ================ CCM ================ */
sahilmgandhi 18:6a4db94011d3 877 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 878
sahilmgandhi 18:6a4db94011d3 879
sahilmgandhi 18:6a4db94011d3 880 /**
sahilmgandhi 18:6a4db94011d3 881 * @brief AES CCM Mode Encryption. (CCM)
sahilmgandhi 18:6a4db94011d3 882 */
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 typedef struct { /*!< CCM Structure */
sahilmgandhi 18:6a4db94011d3 885 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
sahilmgandhi 18:6a4db94011d3 886 itself when completed. */
sahilmgandhi 18:6a4db94011d3 887 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
sahilmgandhi 18:6a4db94011d3 888 completed. */
sahilmgandhi 18:6a4db94011d3 889 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
sahilmgandhi 18:6a4db94011d3 890 __I uint32_t RESERVED0[61];
sahilmgandhi 18:6a4db94011d3 891 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
sahilmgandhi 18:6a4db94011d3 892 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
sahilmgandhi 18:6a4db94011d3 893 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
sahilmgandhi 18:6a4db94011d3 894 __I uint32_t RESERVED1[61];
sahilmgandhi 18:6a4db94011d3 895 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
sahilmgandhi 18:6a4db94011d3 896 __I uint32_t RESERVED2[64];
sahilmgandhi 18:6a4db94011d3 897 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 898 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 899 __I uint32_t RESERVED3[61];
sahilmgandhi 18:6a4db94011d3 900 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
sahilmgandhi 18:6a4db94011d3 901 __I uint32_t RESERVED4[63];
sahilmgandhi 18:6a4db94011d3 902 __IO uint32_t ENABLE; /*!< CCM enable. */
sahilmgandhi 18:6a4db94011d3 903 __IO uint32_t MODE; /*!< Operation mode. */
sahilmgandhi 18:6a4db94011d3 904 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
sahilmgandhi 18:6a4db94011d3 905 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
sahilmgandhi 18:6a4db94011d3 906 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
sahilmgandhi 18:6a4db94011d3 907 __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
sahilmgandhi 18:6a4db94011d3 908 resolution. A minimum of 43 bytes must be reserved. */
sahilmgandhi 18:6a4db94011d3 909 __I uint32_t RESERVED5[697];
sahilmgandhi 18:6a4db94011d3 910 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 911 } NRF_CCM_Type;
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 915 /* ================ WDT ================ */
sahilmgandhi 18:6a4db94011d3 916 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 917
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 /**
sahilmgandhi 18:6a4db94011d3 920 * @brief Watchdog Timer. (WDT)
sahilmgandhi 18:6a4db94011d3 921 */
sahilmgandhi 18:6a4db94011d3 922
sahilmgandhi 18:6a4db94011d3 923 typedef struct { /*!< WDT Structure */
sahilmgandhi 18:6a4db94011d3 924 __O uint32_t TASKS_START; /*!< Start the watchdog. */
sahilmgandhi 18:6a4db94011d3 925 __I uint32_t RESERVED0[63];
sahilmgandhi 18:6a4db94011d3 926 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
sahilmgandhi 18:6a4db94011d3 927 __I uint32_t RESERVED1[128];
sahilmgandhi 18:6a4db94011d3 928 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 929 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 930 __I uint32_t RESERVED2[61];
sahilmgandhi 18:6a4db94011d3 931 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
sahilmgandhi 18:6a4db94011d3 932 __I uint32_t REQSTATUS; /*!< Request status. */
sahilmgandhi 18:6a4db94011d3 933 __I uint32_t RESERVED3[63];
sahilmgandhi 18:6a4db94011d3 934 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
sahilmgandhi 18:6a4db94011d3 935 __IO uint32_t RREN; /*!< Reload request enable. */
sahilmgandhi 18:6a4db94011d3 936 __IO uint32_t CONFIG; /*!< Configuration register. */
sahilmgandhi 18:6a4db94011d3 937 __I uint32_t RESERVED4[60];
sahilmgandhi 18:6a4db94011d3 938 __O uint32_t RR[8]; /*!< Reload requests registers. */
sahilmgandhi 18:6a4db94011d3 939 __I uint32_t RESERVED5[631];
sahilmgandhi 18:6a4db94011d3 940 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 941 } NRF_WDT_Type;
sahilmgandhi 18:6a4db94011d3 942
sahilmgandhi 18:6a4db94011d3 943
sahilmgandhi 18:6a4db94011d3 944 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 945 /* ================ QDEC ================ */
sahilmgandhi 18:6a4db94011d3 946 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 947
sahilmgandhi 18:6a4db94011d3 948
sahilmgandhi 18:6a4db94011d3 949 /**
sahilmgandhi 18:6a4db94011d3 950 * @brief Rotary decoder. (QDEC)
sahilmgandhi 18:6a4db94011d3 951 */
sahilmgandhi 18:6a4db94011d3 952
sahilmgandhi 18:6a4db94011d3 953 typedef struct { /*!< QDEC Structure */
sahilmgandhi 18:6a4db94011d3 954 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
sahilmgandhi 18:6a4db94011d3 955 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
sahilmgandhi 18:6a4db94011d3 956 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
sahilmgandhi 18:6a4db94011d3 957 and clears the ACC registers. */
sahilmgandhi 18:6a4db94011d3 958 __I uint32_t RESERVED0[61];
sahilmgandhi 18:6a4db94011d3 959 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
sahilmgandhi 18:6a4db94011d3 960 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
sahilmgandhi 18:6a4db94011d3 961 ACC register different than zero. */
sahilmgandhi 18:6a4db94011d3 962 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
sahilmgandhi 18:6a4db94011d3 963 __I uint32_t RESERVED1[61];
sahilmgandhi 18:6a4db94011d3 964 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
sahilmgandhi 18:6a4db94011d3 965 __I uint32_t RESERVED2[64];
sahilmgandhi 18:6a4db94011d3 966 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 967 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 968 __I uint32_t RESERVED3[125];
sahilmgandhi 18:6a4db94011d3 969 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
sahilmgandhi 18:6a4db94011d3 970 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
sahilmgandhi 18:6a4db94011d3 971 __IO uint32_t SAMPLEPER; /*!< Sample period. */
sahilmgandhi 18:6a4db94011d3 972 __I int32_t SAMPLE; /*!< Motion sample value. */
sahilmgandhi 18:6a4db94011d3 973 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
sahilmgandhi 18:6a4db94011d3 974 __I int32_t ACC; /*!< Accumulated valid transitions register. */
sahilmgandhi 18:6a4db94011d3 975 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
sahilmgandhi 18:6a4db94011d3 976 task. */
sahilmgandhi 18:6a4db94011d3 977 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
sahilmgandhi 18:6a4db94011d3 978 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
sahilmgandhi 18:6a4db94011d3 979 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
sahilmgandhi 18:6a4db94011d3 980 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
sahilmgandhi 18:6a4db94011d3 981 __I uint32_t RESERVED4[5];
sahilmgandhi 18:6a4db94011d3 982 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
sahilmgandhi 18:6a4db94011d3 983 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
sahilmgandhi 18:6a4db94011d3 984 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
sahilmgandhi 18:6a4db94011d3 985 task. */
sahilmgandhi 18:6a4db94011d3 986 __I uint32_t RESERVED5[684];
sahilmgandhi 18:6a4db94011d3 987 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 988 } NRF_QDEC_Type;
sahilmgandhi 18:6a4db94011d3 989
sahilmgandhi 18:6a4db94011d3 990
sahilmgandhi 18:6a4db94011d3 991 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 992 /* ================ LPCOMP ================ */
sahilmgandhi 18:6a4db94011d3 993 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 994
sahilmgandhi 18:6a4db94011d3 995
sahilmgandhi 18:6a4db94011d3 996 /**
sahilmgandhi 18:6a4db94011d3 997 * @brief Low power comparator. (LPCOMP)
sahilmgandhi 18:6a4db94011d3 998 */
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 typedef struct { /*!< LPCOMP Structure */
sahilmgandhi 18:6a4db94011d3 1001 __O uint32_t TASKS_START; /*!< Start the comparator. */
sahilmgandhi 18:6a4db94011d3 1002 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
sahilmgandhi 18:6a4db94011d3 1003 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
sahilmgandhi 18:6a4db94011d3 1004 __I uint32_t RESERVED0[61];
sahilmgandhi 18:6a4db94011d3 1005 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
sahilmgandhi 18:6a4db94011d3 1006 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
sahilmgandhi 18:6a4db94011d3 1007 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
sahilmgandhi 18:6a4db94011d3 1008 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
sahilmgandhi 18:6a4db94011d3 1009 __I uint32_t RESERVED1[60];
sahilmgandhi 18:6a4db94011d3 1010 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
sahilmgandhi 18:6a4db94011d3 1011 __I uint32_t RESERVED2[64];
sahilmgandhi 18:6a4db94011d3 1012 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
sahilmgandhi 18:6a4db94011d3 1013 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
sahilmgandhi 18:6a4db94011d3 1014 __I uint32_t RESERVED3[61];
sahilmgandhi 18:6a4db94011d3 1015 __I uint32_t RESULT; /*!< Result of last compare. */
sahilmgandhi 18:6a4db94011d3 1016 __I uint32_t RESERVED4[63];
sahilmgandhi 18:6a4db94011d3 1017 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
sahilmgandhi 18:6a4db94011d3 1018 __IO uint32_t PSEL; /*!< Input pin select. */
sahilmgandhi 18:6a4db94011d3 1019 __IO uint32_t REFSEL; /*!< Reference select. */
sahilmgandhi 18:6a4db94011d3 1020 __IO uint32_t EXTREFSEL; /*!< External reference select. */
sahilmgandhi 18:6a4db94011d3 1021 __I uint32_t RESERVED5[4];
sahilmgandhi 18:6a4db94011d3 1022 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
sahilmgandhi 18:6a4db94011d3 1023 __I uint32_t RESERVED6[694];
sahilmgandhi 18:6a4db94011d3 1024 __IO uint32_t POWER; /*!< Peripheral power control. */
sahilmgandhi 18:6a4db94011d3 1025 } NRF_LPCOMP_Type;
sahilmgandhi 18:6a4db94011d3 1026
sahilmgandhi 18:6a4db94011d3 1027
sahilmgandhi 18:6a4db94011d3 1028 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1029 /* ================ SWI ================ */
sahilmgandhi 18:6a4db94011d3 1030 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1031
sahilmgandhi 18:6a4db94011d3 1032
sahilmgandhi 18:6a4db94011d3 1033 /**
sahilmgandhi 18:6a4db94011d3 1034 * @brief SW Interrupts. (SWI)
sahilmgandhi 18:6a4db94011d3 1035 */
sahilmgandhi 18:6a4db94011d3 1036
sahilmgandhi 18:6a4db94011d3 1037 typedef struct { /*!< SWI Structure */
sahilmgandhi 18:6a4db94011d3 1038 __I uint32_t UNUSED; /*!< Unused. */
sahilmgandhi 18:6a4db94011d3 1039 } NRF_SWI_Type;
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041
sahilmgandhi 18:6a4db94011d3 1042 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1043 /* ================ NVMC ================ */
sahilmgandhi 18:6a4db94011d3 1044 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1045
sahilmgandhi 18:6a4db94011d3 1046
sahilmgandhi 18:6a4db94011d3 1047 /**
sahilmgandhi 18:6a4db94011d3 1048 * @brief Non Volatile Memory Controller. (NVMC)
sahilmgandhi 18:6a4db94011d3 1049 */
sahilmgandhi 18:6a4db94011d3 1050
sahilmgandhi 18:6a4db94011d3 1051 typedef struct { /*!< NVMC Structure */
sahilmgandhi 18:6a4db94011d3 1052 __I uint32_t RESERVED0[256];
sahilmgandhi 18:6a4db94011d3 1053 __I uint32_t READY; /*!< Ready flag. */
sahilmgandhi 18:6a4db94011d3 1054 __I uint32_t RESERVED1[64];
sahilmgandhi 18:6a4db94011d3 1055 __IO uint32_t CONFIG; /*!< Configuration register. */
sahilmgandhi 18:6a4db94011d3 1056
sahilmgandhi 18:6a4db94011d3 1057 union {
sahilmgandhi 18:6a4db94011d3 1058 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
sahilmgandhi 18:6a4db94011d3 1059 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
sahilmgandhi 18:6a4db94011d3 1060 };
sahilmgandhi 18:6a4db94011d3 1061 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
sahilmgandhi 18:6a4db94011d3 1062 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
sahilmgandhi 18:6a4db94011d3 1063 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
sahilmgandhi 18:6a4db94011d3 1064 } NRF_NVMC_Type;
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066
sahilmgandhi 18:6a4db94011d3 1067 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1068 /* ================ PPI ================ */
sahilmgandhi 18:6a4db94011d3 1069 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1070
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 /**
sahilmgandhi 18:6a4db94011d3 1073 * @brief PPI controller. (PPI)
sahilmgandhi 18:6a4db94011d3 1074 */
sahilmgandhi 18:6a4db94011d3 1075
sahilmgandhi 18:6a4db94011d3 1076 typedef struct { /*!< PPI Structure */
sahilmgandhi 18:6a4db94011d3 1077 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
sahilmgandhi 18:6a4db94011d3 1078 __I uint32_t RESERVED0[312];
sahilmgandhi 18:6a4db94011d3 1079 __IO uint32_t CHEN; /*!< Channel enable. */
sahilmgandhi 18:6a4db94011d3 1080 __IO uint32_t CHENSET; /*!< Channel enable set. */
sahilmgandhi 18:6a4db94011d3 1081 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
sahilmgandhi 18:6a4db94011d3 1082 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 1083 PPI_CH_Type CH[16]; /*!< PPI Channel. */
sahilmgandhi 18:6a4db94011d3 1084 __I uint32_t RESERVED2[156];
sahilmgandhi 18:6a4db94011d3 1085 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
sahilmgandhi 18:6a4db94011d3 1086 } NRF_PPI_Type;
sahilmgandhi 18:6a4db94011d3 1087
sahilmgandhi 18:6a4db94011d3 1088
sahilmgandhi 18:6a4db94011d3 1089 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1090 /* ================ FICR ================ */
sahilmgandhi 18:6a4db94011d3 1091 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1092
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094 /**
sahilmgandhi 18:6a4db94011d3 1095 * @brief Factory Information Configuration. (FICR)
sahilmgandhi 18:6a4db94011d3 1096 */
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 typedef struct { /*!< FICR Structure */
sahilmgandhi 18:6a4db94011d3 1099 __I uint32_t RESERVED0[4];
sahilmgandhi 18:6a4db94011d3 1100 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
sahilmgandhi 18:6a4db94011d3 1101 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
sahilmgandhi 18:6a4db94011d3 1102 __I uint32_t RESERVED1[4];
sahilmgandhi 18:6a4db94011d3 1103 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
sahilmgandhi 18:6a4db94011d3 1104 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
sahilmgandhi 18:6a4db94011d3 1105 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 1106 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
sahilmgandhi 18:6a4db94011d3 1107
sahilmgandhi 18:6a4db94011d3 1108 union {
sahilmgandhi 18:6a4db94011d3 1109 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
sahilmgandhi 18:6a4db94011d3 1110 kept for backward compatinility purposes. Use SIZERAMBLOCKS
sahilmgandhi 18:6a4db94011d3 1111 instead. */
sahilmgandhi 18:6a4db94011d3 1112 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
sahilmgandhi 18:6a4db94011d3 1113 };
sahilmgandhi 18:6a4db94011d3 1114 __I uint32_t RESERVED3[5];
sahilmgandhi 18:6a4db94011d3 1115 __I uint32_t CONFIGID; /*!< Configuration identifier. */
sahilmgandhi 18:6a4db94011d3 1116 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
sahilmgandhi 18:6a4db94011d3 1117 __I uint32_t RESERVED4[6];
sahilmgandhi 18:6a4db94011d3 1118 __I uint32_t ER[4]; /*!< Encryption root. */
sahilmgandhi 18:6a4db94011d3 1119 __I uint32_t IR[4]; /*!< Identity root. */
sahilmgandhi 18:6a4db94011d3 1120 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
sahilmgandhi 18:6a4db94011d3 1121 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
sahilmgandhi 18:6a4db94011d3 1122 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
sahilmgandhi 18:6a4db94011d3 1123 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
sahilmgandhi 18:6a4db94011d3 1124 mode. */
sahilmgandhi 18:6a4db94011d3 1125 __I uint32_t RESERVED5[10];
sahilmgandhi 18:6a4db94011d3 1126 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
sahilmgandhi 18:6a4db94011d3 1127 mode. */
sahilmgandhi 18:6a4db94011d3 1128 } NRF_FICR_Type;
sahilmgandhi 18:6a4db94011d3 1129
sahilmgandhi 18:6a4db94011d3 1130
sahilmgandhi 18:6a4db94011d3 1131 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1132 /* ================ UICR ================ */
sahilmgandhi 18:6a4db94011d3 1133 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1134
sahilmgandhi 18:6a4db94011d3 1135
sahilmgandhi 18:6a4db94011d3 1136 /**
sahilmgandhi 18:6a4db94011d3 1137 * @brief User Information Configuration. (UICR)
sahilmgandhi 18:6a4db94011d3 1138 */
sahilmgandhi 18:6a4db94011d3 1139
sahilmgandhi 18:6a4db94011d3 1140 typedef struct { /*!< UICR Structure */
sahilmgandhi 18:6a4db94011d3 1141 __IO uint32_t CLENR0; /*!< Length of code region 0. */
sahilmgandhi 18:6a4db94011d3 1142 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
sahilmgandhi 18:6a4db94011d3 1143 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
sahilmgandhi 18:6a4db94011d3 1144 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1145 __I uint32_t FWID; /*!< Firmware ID. */
sahilmgandhi 18:6a4db94011d3 1146
sahilmgandhi 18:6a4db94011d3 1147 union {
sahilmgandhi 18:6a4db94011d3 1148 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
sahilmgandhi 18:6a4db94011d3 1149 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
sahilmgandhi 18:6a4db94011d3 1150 };
sahilmgandhi 18:6a4db94011d3 1151 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
sahilmgandhi 18:6a4db94011d3 1152 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
sahilmgandhi 18:6a4db94011d3 1153 } NRF_UICR_Type;
sahilmgandhi 18:6a4db94011d3 1154
sahilmgandhi 18:6a4db94011d3 1155
sahilmgandhi 18:6a4db94011d3 1156 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1157 /* ================ GPIO ================ */
sahilmgandhi 18:6a4db94011d3 1158 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1159
sahilmgandhi 18:6a4db94011d3 1160
sahilmgandhi 18:6a4db94011d3 1161 /**
sahilmgandhi 18:6a4db94011d3 1162 * @brief General purpose input and output. (GPIO)
sahilmgandhi 18:6a4db94011d3 1163 */
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 typedef struct { /*!< GPIO Structure */
sahilmgandhi 18:6a4db94011d3 1166 __I uint32_t RESERVED0[321];
sahilmgandhi 18:6a4db94011d3 1167 __IO uint32_t OUT; /*!< Write GPIO port. */
sahilmgandhi 18:6a4db94011d3 1168 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
sahilmgandhi 18:6a4db94011d3 1169 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
sahilmgandhi 18:6a4db94011d3 1170 __I uint32_t IN; /*!< Read GPIO port. */
sahilmgandhi 18:6a4db94011d3 1171 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
sahilmgandhi 18:6a4db94011d3 1172 __IO uint32_t DIRSET; /*!< DIR set register. */
sahilmgandhi 18:6a4db94011d3 1173 __IO uint32_t DIRCLR; /*!< DIR clear register. */
sahilmgandhi 18:6a4db94011d3 1174 __I uint32_t RESERVED1[120];
sahilmgandhi 18:6a4db94011d3 1175 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
sahilmgandhi 18:6a4db94011d3 1176 } NRF_GPIO_Type;
sahilmgandhi 18:6a4db94011d3 1177
sahilmgandhi 18:6a4db94011d3 1178
sahilmgandhi 18:6a4db94011d3 1179 /* -------------------- End of section using anonymous unions ------------------- */
sahilmgandhi 18:6a4db94011d3 1180 #if defined(__CC_ARM)
sahilmgandhi 18:6a4db94011d3 1181 #pragma pop
sahilmgandhi 18:6a4db94011d3 1182 #elif defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 1183 /* leave anonymous unions enabled */
sahilmgandhi 18:6a4db94011d3 1184 #elif defined(__GNUC__)
sahilmgandhi 18:6a4db94011d3 1185 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 1186 #elif defined(__TMS470__)
sahilmgandhi 18:6a4db94011d3 1187 /* anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 1188 #elif defined(__TASKING__)
sahilmgandhi 18:6a4db94011d3 1189 #pragma warning restore
sahilmgandhi 18:6a4db94011d3 1190 #else
sahilmgandhi 18:6a4db94011d3 1191 #warning Not supported compiler type
sahilmgandhi 18:6a4db94011d3 1192 #endif
sahilmgandhi 18:6a4db94011d3 1193
sahilmgandhi 18:6a4db94011d3 1194
sahilmgandhi 18:6a4db94011d3 1195
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1198 /* ================ Peripheral memory map ================ */
sahilmgandhi 18:6a4db94011d3 1199 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1200
sahilmgandhi 18:6a4db94011d3 1201 #define NRF_POWER_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1202 #define NRF_CLOCK_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1203 #define NRF_MPU_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1204 #define NRF_AMLI_BASE 0x40000000UL
sahilmgandhi 18:6a4db94011d3 1205 #define NRF_RADIO_BASE 0x40001000UL
sahilmgandhi 18:6a4db94011d3 1206 #define NRF_UART0_BASE 0x40002000UL
sahilmgandhi 18:6a4db94011d3 1207 #define NRF_SPI0_BASE 0x40003000UL
sahilmgandhi 18:6a4db94011d3 1208 #define NRF_TWI0_BASE 0x40003000UL
sahilmgandhi 18:6a4db94011d3 1209 #define NRF_SPI1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1210 #define NRF_TWI1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1211 #define NRF_SPIS1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1212 #define NRF_SPIM1_BASE 0x40004000UL
sahilmgandhi 18:6a4db94011d3 1213 #define NRF_GPIOTE_BASE 0x40006000UL
sahilmgandhi 18:6a4db94011d3 1214 #define NRF_ADC_BASE 0x40007000UL
sahilmgandhi 18:6a4db94011d3 1215 #define NRF_TIMER0_BASE 0x40008000UL
sahilmgandhi 18:6a4db94011d3 1216 #define NRF_TIMER1_BASE 0x40009000UL
sahilmgandhi 18:6a4db94011d3 1217 #define NRF_TIMER2_BASE 0x4000A000UL
sahilmgandhi 18:6a4db94011d3 1218 #define NRF_RTC0_BASE 0x4000B000UL
sahilmgandhi 18:6a4db94011d3 1219 #define NRF_TEMP_BASE 0x4000C000UL
sahilmgandhi 18:6a4db94011d3 1220 #define NRF_RNG_BASE 0x4000D000UL
sahilmgandhi 18:6a4db94011d3 1221 #define NRF_ECB_BASE 0x4000E000UL
sahilmgandhi 18:6a4db94011d3 1222 #define NRF_AAR_BASE 0x4000F000UL
sahilmgandhi 18:6a4db94011d3 1223 #define NRF_CCM_BASE 0x4000F000UL
sahilmgandhi 18:6a4db94011d3 1224 #define NRF_WDT_BASE 0x40010000UL
sahilmgandhi 18:6a4db94011d3 1225 #define NRF_RTC1_BASE 0x40011000UL
sahilmgandhi 18:6a4db94011d3 1226 #define NRF_QDEC_BASE 0x40012000UL
sahilmgandhi 18:6a4db94011d3 1227 #define NRF_LPCOMP_BASE 0x40013000UL
sahilmgandhi 18:6a4db94011d3 1228 #define NRF_SWI_BASE 0x40014000UL
sahilmgandhi 18:6a4db94011d3 1229 #define NRF_NVMC_BASE 0x4001E000UL
sahilmgandhi 18:6a4db94011d3 1230 #define NRF_PPI_BASE 0x4001F000UL
sahilmgandhi 18:6a4db94011d3 1231 #define NRF_FICR_BASE 0x10000000UL
sahilmgandhi 18:6a4db94011d3 1232 #define NRF_UICR_BASE 0x10001000UL
sahilmgandhi 18:6a4db94011d3 1233 #define NRF_GPIO_BASE 0x50000000UL
sahilmgandhi 18:6a4db94011d3 1234
sahilmgandhi 18:6a4db94011d3 1235
sahilmgandhi 18:6a4db94011d3 1236 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1237 /* ================ Peripheral declaration ================ */
sahilmgandhi 18:6a4db94011d3 1238 /* ================================================================================ */
sahilmgandhi 18:6a4db94011d3 1239
sahilmgandhi 18:6a4db94011d3 1240 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
sahilmgandhi 18:6a4db94011d3 1241 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
sahilmgandhi 18:6a4db94011d3 1242 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
sahilmgandhi 18:6a4db94011d3 1243 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
sahilmgandhi 18:6a4db94011d3 1244 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
sahilmgandhi 18:6a4db94011d3 1245 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
sahilmgandhi 18:6a4db94011d3 1246 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
sahilmgandhi 18:6a4db94011d3 1247 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
sahilmgandhi 18:6a4db94011d3 1248 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 1249 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
sahilmgandhi 18:6a4db94011d3 1250 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
sahilmgandhi 18:6a4db94011d3 1251 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
sahilmgandhi 18:6a4db94011d3 1252 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
sahilmgandhi 18:6a4db94011d3 1253 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
sahilmgandhi 18:6a4db94011d3 1254 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
sahilmgandhi 18:6a4db94011d3 1255 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
sahilmgandhi 18:6a4db94011d3 1256 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
sahilmgandhi 18:6a4db94011d3 1257 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
sahilmgandhi 18:6a4db94011d3 1258 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
sahilmgandhi 18:6a4db94011d3 1259 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
sahilmgandhi 18:6a4db94011d3 1260 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
sahilmgandhi 18:6a4db94011d3 1261 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
sahilmgandhi 18:6a4db94011d3 1262 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
sahilmgandhi 18:6a4db94011d3 1263 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
sahilmgandhi 18:6a4db94011d3 1264 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
sahilmgandhi 18:6a4db94011d3 1265 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
sahilmgandhi 18:6a4db94011d3 1266 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
sahilmgandhi 18:6a4db94011d3 1267 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
sahilmgandhi 18:6a4db94011d3 1268 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
sahilmgandhi 18:6a4db94011d3 1269 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
sahilmgandhi 18:6a4db94011d3 1270 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
sahilmgandhi 18:6a4db94011d3 1271 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
sahilmgandhi 18:6a4db94011d3 1272 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
sahilmgandhi 18:6a4db94011d3 1273
sahilmgandhi 18:6a4db94011d3 1274
sahilmgandhi 18:6a4db94011d3 1275 /** @} */ /* End of group Device_Peripheral_Registers */
sahilmgandhi 18:6a4db94011d3 1276 /** @} */ /* End of group nrf51 */
sahilmgandhi 18:6a4db94011d3 1277 /** @} */ /* End of group Nordic Semiconductor */
sahilmgandhi 18:6a4db94011d3 1278
sahilmgandhi 18:6a4db94011d3 1279 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1280 }
sahilmgandhi 18:6a4db94011d3 1281 #endif
sahilmgandhi 18:6a4db94011d3 1282
sahilmgandhi 18:6a4db94011d3 1283
sahilmgandhi 18:6a4db94011d3 1284 #endif /* nrf51_H */
sahilmgandhi 18:6a4db94011d3 1285