Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/us_ticker.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2006-2015 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | #include <stddef.h> |
sahilmgandhi | 18:6a4db94011d3 | 17 | #include "us_ticker_api.h" |
sahilmgandhi | 18:6a4db94011d3 | 18 | #include "cmsis.h" |
sahilmgandhi | 18:6a4db94011d3 | 19 | #include "mbed_assert.h" |
sahilmgandhi | 18:6a4db94011d3 | 20 | #include "compiler.h" |
sahilmgandhi | 18:6a4db94011d3 | 21 | #include "sysclk.h" |
sahilmgandhi | 18:6a4db94011d3 | 22 | #include "tc.h" |
sahilmgandhi | 18:6a4db94011d3 | 23 | |
sahilmgandhi | 18:6a4db94011d3 | 24 | uint8_t us_ticker_inited = 0; |
sahilmgandhi | 18:6a4db94011d3 | 25 | extern uint8_t g_sys_init; |
sahilmgandhi | 18:6a4db94011d3 | 26 | volatile uint16_t us_ticker_16bit_counter; |
sahilmgandhi | 18:6a4db94011d3 | 27 | volatile uint16_t us_ticker_interrupt_counter; |
sahilmgandhi | 18:6a4db94011d3 | 28 | volatile uint16_t us_ticker_interrupt_offset; |
sahilmgandhi | 18:6a4db94011d3 | 29 | volatile uint32_t overflow32bitcounter = 0; |
sahilmgandhi | 18:6a4db94011d3 | 30 | |
sahilmgandhi | 18:6a4db94011d3 | 31 | #define TICKER_COUNTER_uS TC1 |
sahilmgandhi | 18:6a4db94011d3 | 32 | |
sahilmgandhi | 18:6a4db94011d3 | 33 | #define TICKER_COUNTER_CLK0 ID_TC3 |
sahilmgandhi | 18:6a4db94011d3 | 34 | #define TICKER_COUNTER_CLK1 ID_TC4 |
sahilmgandhi | 18:6a4db94011d3 | 35 | |
sahilmgandhi | 18:6a4db94011d3 | 36 | #define TICKER_COUNTER_CHANNEL0 0 |
sahilmgandhi | 18:6a4db94011d3 | 37 | #define TICKER_COUNTER_IRQn0 TC3_IRQn |
sahilmgandhi | 18:6a4db94011d3 | 38 | #define TICKER_COUNTER_Handlr0 TC3_Handler |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | #define TICKER_COUNTER_CHANNEL1 1 |
sahilmgandhi | 18:6a4db94011d3 | 41 | #define TICKER_COUNTER_IRQn1 TC4_IRQn |
sahilmgandhi | 18:6a4db94011d3 | 42 | #define TICKER_COUNTER_Handlr1 TC4_Handler |
sahilmgandhi | 18:6a4db94011d3 | 43 | |
sahilmgandhi | 18:6a4db94011d3 | 44 | #define OVERFLOW_16bit_VALUE 0xFFFF |
sahilmgandhi | 18:6a4db94011d3 | 45 | |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | void TICKER_COUNTER_Handlr1(void) |
sahilmgandhi | 18:6a4db94011d3 | 48 | { |
sahilmgandhi | 18:6a4db94011d3 | 49 | uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); |
sahilmgandhi | 18:6a4db94011d3 | 50 | uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | if (((status & interrupmask) & TC_IER_CPCS)) { |
sahilmgandhi | 18:6a4db94011d3 | 53 | if(us_ticker_interrupt_counter) { |
sahilmgandhi | 18:6a4db94011d3 | 54 | us_ticker_interrupt_counter--; |
sahilmgandhi | 18:6a4db94011d3 | 55 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 56 | if(us_ticker_interrupt_offset) { |
sahilmgandhi | 18:6a4db94011d3 | 57 | us_ticker_interrupt_offset=0; |
sahilmgandhi | 18:6a4db94011d3 | 58 | tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); |
sahilmgandhi | 18:6a4db94011d3 | 59 | tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)us_ticker_interrupt_offset); |
sahilmgandhi | 18:6a4db94011d3 | 60 | tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); |
sahilmgandhi | 18:6a4db94011d3 | 61 | } else |
sahilmgandhi | 18:6a4db94011d3 | 62 | us_ticker_irq_handler(); |
sahilmgandhi | 18:6a4db94011d3 | 63 | } |
sahilmgandhi | 18:6a4db94011d3 | 64 | } |
sahilmgandhi | 18:6a4db94011d3 | 65 | } |
sahilmgandhi | 18:6a4db94011d3 | 66 | |
sahilmgandhi | 18:6a4db94011d3 | 67 | void TICKER_COUNTER_Handlr0(void) |
sahilmgandhi | 18:6a4db94011d3 | 68 | { |
sahilmgandhi | 18:6a4db94011d3 | 69 | uint32_t status=tc_get_status(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0); |
sahilmgandhi | 18:6a4db94011d3 | 70 | uint32_t interrupmask=tc_get_interrupt_mask(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0); |
sahilmgandhi | 18:6a4db94011d3 | 71 | |
sahilmgandhi | 18:6a4db94011d3 | 72 | if (((status & interrupmask) & TC_IER_COVFS)) { |
sahilmgandhi | 18:6a4db94011d3 | 73 | us_ticker_16bit_counter++; |
sahilmgandhi | 18:6a4db94011d3 | 74 | if(us_ticker_16bit_counter == 0xFFFF) |
sahilmgandhi | 18:6a4db94011d3 | 75 | overflow32bitcounter++; |
sahilmgandhi | 18:6a4db94011d3 | 76 | } |
sahilmgandhi | 18:6a4db94011d3 | 77 | } |
sahilmgandhi | 18:6a4db94011d3 | 78 | |
sahilmgandhi | 18:6a4db94011d3 | 79 | void us_ticker_init(void) |
sahilmgandhi | 18:6a4db94011d3 | 80 | { |
sahilmgandhi | 18:6a4db94011d3 | 81 | if (us_ticker_inited) return; |
sahilmgandhi | 18:6a4db94011d3 | 82 | us_ticker_inited = 1; |
sahilmgandhi | 18:6a4db94011d3 | 83 | |
sahilmgandhi | 18:6a4db94011d3 | 84 | us_ticker_16bit_counter=0; |
sahilmgandhi | 18:6a4db94011d3 | 85 | us_ticker_interrupt_counter=0; |
sahilmgandhi | 18:6a4db94011d3 | 86 | us_ticker_interrupt_offset=0; |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | if (g_sys_init == 0) { |
sahilmgandhi | 18:6a4db94011d3 | 89 | sysclk_init(); |
sahilmgandhi | 18:6a4db94011d3 | 90 | system_board_init(); |
sahilmgandhi | 18:6a4db94011d3 | 91 | g_sys_init = 1; |
sahilmgandhi | 18:6a4db94011d3 | 92 | } |
sahilmgandhi | 18:6a4db94011d3 | 93 | |
sahilmgandhi | 18:6a4db94011d3 | 94 | /* Configure the PMC to enable the TC module. */ |
sahilmgandhi | 18:6a4db94011d3 | 95 | sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK0); |
sahilmgandhi | 18:6a4db94011d3 | 96 | sysclk_enable_peripheral_clock(TICKER_COUNTER_CLK1); |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | #if SAMG55 |
sahilmgandhi | 18:6a4db94011d3 | 99 | /* Enable PCK output */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | pmc_disable_pck(PMC_PCK_3); |
sahilmgandhi | 18:6a4db94011d3 | 101 | pmc_switch_pck_to_mck(PMC_PCK_3, PMC_PCK_PRES_CLK_1); |
sahilmgandhi | 18:6a4db94011d3 | 102 | pmc_enable_pck(PMC_PCK_3); |
sahilmgandhi | 18:6a4db94011d3 | 103 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 104 | |
sahilmgandhi | 18:6a4db94011d3 | 105 | /* Init TC to Counter mode. */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_CMR_TCCLKS_TIMER_CLOCK4); |
sahilmgandhi | 18:6a4db94011d3 | 107 | tc_init(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_CMR_TCCLKS_TIMER_CLOCK4); |
sahilmgandhi | 18:6a4db94011d3 | 108 | |
sahilmgandhi | 18:6a4db94011d3 | 109 | |
sahilmgandhi | 18:6a4db94011d3 | 110 | NVIC_DisableIRQ(TICKER_COUNTER_IRQn0); |
sahilmgandhi | 18:6a4db94011d3 | 111 | |
sahilmgandhi | 18:6a4db94011d3 | 112 | NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn0); |
sahilmgandhi | 18:6a4db94011d3 | 113 | NVIC_SetPriority(TICKER_COUNTER_IRQn0, 0); |
sahilmgandhi | 18:6a4db94011d3 | 114 | NVIC_EnableIRQ(TICKER_COUNTER_IRQn0); |
sahilmgandhi | 18:6a4db94011d3 | 115 | tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0, TC_IER_COVFS); |
sahilmgandhi | 18:6a4db94011d3 | 116 | |
sahilmgandhi | 18:6a4db94011d3 | 117 | tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0); |
sahilmgandhi | 18:6a4db94011d3 | 118 | } |
sahilmgandhi | 18:6a4db94011d3 | 119 | |
sahilmgandhi | 18:6a4db94011d3 | 120 | |
sahilmgandhi | 18:6a4db94011d3 | 121 | uint32_t us_ticker_read() |
sahilmgandhi | 18:6a4db94011d3 | 122 | { |
sahilmgandhi | 18:6a4db94011d3 | 123 | if (!us_ticker_inited) |
sahilmgandhi | 18:6a4db94011d3 | 124 | us_ticker_init(); |
sahilmgandhi | 18:6a4db94011d3 | 125 | |
sahilmgandhi | 18:6a4db94011d3 | 126 | uint32_t counter_value=0; |
sahilmgandhi | 18:6a4db94011d3 | 127 | uint16_t tickerbefore=0; |
sahilmgandhi | 18:6a4db94011d3 | 128 | do { |
sahilmgandhi | 18:6a4db94011d3 | 129 | tickerbefore=us_ticker_16bit_counter; |
sahilmgandhi | 18:6a4db94011d3 | 130 | counter_value=tc_read_cv(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL0); |
sahilmgandhi | 18:6a4db94011d3 | 131 | } while(tickerbefore!=us_ticker_16bit_counter); |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | return counter_value+(OVERFLOW_16bit_VALUE*us_ticker_16bit_counter); |
sahilmgandhi | 18:6a4db94011d3 | 134 | } |
sahilmgandhi | 18:6a4db94011d3 | 135 | |
sahilmgandhi | 18:6a4db94011d3 | 136 | void us_ticker_set_interrupt(timestamp_t timestamp) |
sahilmgandhi | 18:6a4db94011d3 | 137 | { |
sahilmgandhi | 18:6a4db94011d3 | 138 | uint32_t cur_time; |
sahilmgandhi | 18:6a4db94011d3 | 139 | int32_t delta; |
sahilmgandhi | 18:6a4db94011d3 | 140 | |
sahilmgandhi | 18:6a4db94011d3 | 141 | cur_time = us_ticker_read(); |
sahilmgandhi | 18:6a4db94011d3 | 142 | delta = (int32_t)((uint32_t)timestamp - cur_time); |
sahilmgandhi | 18:6a4db94011d3 | 143 | if (delta < 0) { |
sahilmgandhi | 18:6a4db94011d3 | 144 | /* Event already occurred in past */ |
sahilmgandhi | 18:6a4db94011d3 | 145 | us_ticker_irq_handler(); |
sahilmgandhi | 18:6a4db94011d3 | 146 | return; |
sahilmgandhi | 18:6a4db94011d3 | 147 | } |
sahilmgandhi | 18:6a4db94011d3 | 148 | |
sahilmgandhi | 18:6a4db94011d3 | 149 | uint16_t interruptat=0; |
sahilmgandhi | 18:6a4db94011d3 | 150 | |
sahilmgandhi | 18:6a4db94011d3 | 151 | if(delta > OVERFLOW_16bit_VALUE) { |
sahilmgandhi | 18:6a4db94011d3 | 152 | us_ticker_interrupt_counter= (delta/OVERFLOW_16bit_VALUE) -1; |
sahilmgandhi | 18:6a4db94011d3 | 153 | us_ticker_interrupt_offset=delta%OVERFLOW_16bit_VALUE; |
sahilmgandhi | 18:6a4db94011d3 | 154 | interruptat=OVERFLOW_16bit_VALUE; |
sahilmgandhi | 18:6a4db94011d3 | 155 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 156 | us_ticker_interrupt_counter=0; |
sahilmgandhi | 18:6a4db94011d3 | 157 | us_ticker_interrupt_offset=0; |
sahilmgandhi | 18:6a4db94011d3 | 158 | interruptat=delta; |
sahilmgandhi | 18:6a4db94011d3 | 159 | } |
sahilmgandhi | 18:6a4db94011d3 | 160 | |
sahilmgandhi | 18:6a4db94011d3 | 161 | NVIC_DisableIRQ(TICKER_COUNTER_IRQn1); |
sahilmgandhi | 18:6a4db94011d3 | 162 | |
sahilmgandhi | 18:6a4db94011d3 | 163 | tc_write_rc(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, (uint32_t)interruptat); |
sahilmgandhi | 18:6a4db94011d3 | 164 | |
sahilmgandhi | 18:6a4db94011d3 | 165 | NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1); |
sahilmgandhi | 18:6a4db94011d3 | 166 | NVIC_SetPriority(TICKER_COUNTER_IRQn1, 0); |
sahilmgandhi | 18:6a4db94011d3 | 167 | NVIC_EnableIRQ(TICKER_COUNTER_IRQn1); |
sahilmgandhi | 18:6a4db94011d3 | 168 | tc_enable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS ); |
sahilmgandhi | 18:6a4db94011d3 | 169 | |
sahilmgandhi | 18:6a4db94011d3 | 170 | tc_start(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); |
sahilmgandhi | 18:6a4db94011d3 | 171 | } |
sahilmgandhi | 18:6a4db94011d3 | 172 | |
sahilmgandhi | 18:6a4db94011d3 | 173 | void us_ticker_disable_interrupt(void) |
sahilmgandhi | 18:6a4db94011d3 | 174 | { |
sahilmgandhi | 18:6a4db94011d3 | 175 | tc_stop(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1); |
sahilmgandhi | 18:6a4db94011d3 | 176 | tc_disable_interrupt(TICKER_COUNTER_uS, TICKER_COUNTER_CHANNEL1, TC_IDR_CPCS); |
sahilmgandhi | 18:6a4db94011d3 | 177 | NVIC_DisableIRQ(TICKER_COUNTER_IRQn1); |
sahilmgandhi | 18:6a4db94011d3 | 178 | } |
sahilmgandhi | 18:6a4db94011d3 | 179 | |
sahilmgandhi | 18:6a4db94011d3 | 180 | void us_ticker_clear_interrupt(void) |
sahilmgandhi | 18:6a4db94011d3 | 181 | { |
sahilmgandhi | 18:6a4db94011d3 | 182 | NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn1); |
sahilmgandhi | 18:6a4db94011d3 | 183 | } |