Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/services/ioport/sam/ioport_gpio.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief SAM architecture specific IOPORT service implementation header file. |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | #ifndef IOPORT_SAM_H |
sahilmgandhi | 18:6a4db94011d3 | 47 | #define IOPORT_SAM_H |
sahilmgandhi | 18:6a4db94011d3 | 48 | |
sahilmgandhi | 18:6a4db94011d3 | 49 | #include <sysclk.h> |
sahilmgandhi | 18:6a4db94011d3 | 50 | |
sahilmgandhi | 18:6a4db94011d3 | 51 | #define IOPORT_CREATE_PIN(port, pin) ((port) * 32 + (pin)) |
sahilmgandhi | 18:6a4db94011d3 | 52 | |
sahilmgandhi | 18:6a4db94011d3 | 53 | // Aliases |
sahilmgandhi | 18:6a4db94011d3 | 54 | #define IOPORT_GPIOA 0 |
sahilmgandhi | 18:6a4db94011d3 | 55 | #define IOPORT_GPIOB 1 |
sahilmgandhi | 18:6a4db94011d3 | 56 | #define IOPORT_GPIOC 2 |
sahilmgandhi | 18:6a4db94011d3 | 57 | #define IOPORT_GPIOD 3 |
sahilmgandhi | 18:6a4db94011d3 | 58 | #define IOPORT_GPIOE 4 |
sahilmgandhi | 18:6a4db94011d3 | 59 | #define IOPORT_GPIOF 5 |
sahilmgandhi | 18:6a4db94011d3 | 60 | |
sahilmgandhi | 18:6a4db94011d3 | 61 | /** |
sahilmgandhi | 18:6a4db94011d3 | 62 | * \weakgroup ioport_group |
sahilmgandhi | 18:6a4db94011d3 | 63 | * \section ioport_modes IOPORT Modes |
sahilmgandhi | 18:6a4db94011d3 | 64 | * |
sahilmgandhi | 18:6a4db94011d3 | 65 | * For details on these please see the device datasheet. |
sahilmgandhi | 18:6a4db94011d3 | 66 | * |
sahilmgandhi | 18:6a4db94011d3 | 67 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 68 | */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | |
sahilmgandhi | 18:6a4db94011d3 | 70 | /** \name IOPORT Mode bit definitions */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | /** @{ */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | #define IOPORT_MODE_MUX_MASK (7 << 0) /*!< MUX bits mask */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | #define IOPORT_MODE_MUX_BIT0 (1 << 0) /*!< MUX BIT0 mask */ |
sahilmgandhi | 18:6a4db94011d3 | 74 | #define IOPORT_MODE_MUX_BIT1 (1 << 1) /*!< MUX BIT1 mask */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | #define IOPORT_MODE_MUX_A (0 << 0) /*!< MUX function A */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | #define IOPORT_MODE_MUX_B (1 << 0) /*!< MUX function B */ |
sahilmgandhi | 18:6a4db94011d3 | 77 | #define IOPORT_MODE_MUX_C (2 << 0) /*!< MUX function C */ |
sahilmgandhi | 18:6a4db94011d3 | 78 | #define IOPORT_MODE_MUX_D (3 << 0) /*!< MUX function D */ |
sahilmgandhi | 18:6a4db94011d3 | 79 | |
sahilmgandhi | 18:6a4db94011d3 | 80 | #define IOPORT_MODE_MUX_BIT2 (1 << 2) /*!< MUX BIT2 mask */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | #define IOPORT_MODE_MUX_E (4 << 0) /*!< MUX function E */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | #define IOPORT_MODE_MUX_F (5 << 0) /*!< MUX function F */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | #define IOPORT_MODE_MUX_G (6 << 0) /*!< MUX function G */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | #define IOPORT_MODE_MUX_H (7 << 0) /*!< MUX function H */ |
sahilmgandhi | 18:6a4db94011d3 | 85 | |
sahilmgandhi | 18:6a4db94011d3 | 86 | #define IOPORT_MODE_PULLUP (1 << 3) /*!< Pull-up */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | #define IOPORT_MODE_PULLDOWN (1 << 4) /*!< Pull-down */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | #define IOPORT_MODE_GLITCH_FILTER (1 << 6) /*!< Glitch filter */ |
sahilmgandhi | 18:6a4db94011d3 | 89 | #define IOPORT_MODE_DRIVE_STRENGTH (1 << 7) /*!< Extra drive strength */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | |
sahilmgandhi | 18:6a4db94011d3 | 94 | typedef uint32_t ioport_mode_t; |
sahilmgandhi | 18:6a4db94011d3 | 95 | typedef uint32_t ioport_pin_t; |
sahilmgandhi | 18:6a4db94011d3 | 96 | typedef uint32_t ioport_port_t; |
sahilmgandhi | 18:6a4db94011d3 | 97 | typedef uint32_t ioport_port_mask_t; |
sahilmgandhi | 18:6a4db94011d3 | 98 | |
sahilmgandhi | 18:6a4db94011d3 | 99 | __always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin) |
sahilmgandhi | 18:6a4db94011d3 | 100 | { |
sahilmgandhi | 18:6a4db94011d3 | 101 | return pin >> 5; |
sahilmgandhi | 18:6a4db94011d3 | 102 | } |
sahilmgandhi | 18:6a4db94011d3 | 103 | |
sahilmgandhi | 18:6a4db94011d3 | 104 | __always_inline static volatile GpioPort *arch_ioport_port_to_base( |
sahilmgandhi | 18:6a4db94011d3 | 105 | ioport_port_t port) |
sahilmgandhi | 18:6a4db94011d3 | 106 | { |
sahilmgandhi | 18:6a4db94011d3 | 107 | return (volatile GpioPort *)(GPIO_ADDR |
sahilmgandhi | 18:6a4db94011d3 | 108 | + port * sizeof(GpioPort)); |
sahilmgandhi | 18:6a4db94011d3 | 109 | } |
sahilmgandhi | 18:6a4db94011d3 | 110 | |
sahilmgandhi | 18:6a4db94011d3 | 111 | __always_inline static volatile GpioPort *arch_ioport_pin_to_base(ioport_pin_t pin) |
sahilmgandhi | 18:6a4db94011d3 | 112 | { |
sahilmgandhi | 18:6a4db94011d3 | 113 | return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin)); |
sahilmgandhi | 18:6a4db94011d3 | 114 | } |
sahilmgandhi | 18:6a4db94011d3 | 115 | |
sahilmgandhi | 18:6a4db94011d3 | 116 | __always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin) |
sahilmgandhi | 18:6a4db94011d3 | 117 | { |
sahilmgandhi | 18:6a4db94011d3 | 118 | return 1U << (pin & 0x1F); |
sahilmgandhi | 18:6a4db94011d3 | 119 | } |
sahilmgandhi | 18:6a4db94011d3 | 120 | |
sahilmgandhi | 18:6a4db94011d3 | 121 | __always_inline static void arch_ioport_init(void) |
sahilmgandhi | 18:6a4db94011d3 | 122 | { |
sahilmgandhi | 18:6a4db94011d3 | 123 | sysclk_enable_peripheral_clock(GPIO); |
sahilmgandhi | 18:6a4db94011d3 | 124 | } |
sahilmgandhi | 18:6a4db94011d3 | 125 | |
sahilmgandhi | 18:6a4db94011d3 | 126 | __always_inline static void arch_ioport_enable_port(ioport_port_t port, |
sahilmgandhi | 18:6a4db94011d3 | 127 | ioport_port_mask_t mask) |
sahilmgandhi | 18:6a4db94011d3 | 128 | { |
sahilmgandhi | 18:6a4db94011d3 | 129 | arch_ioport_port_to_base(port)->GPIO_GPERS = mask; |
sahilmgandhi | 18:6a4db94011d3 | 130 | } |
sahilmgandhi | 18:6a4db94011d3 | 131 | |
sahilmgandhi | 18:6a4db94011d3 | 132 | __always_inline static void arch_ioport_disable_port(ioport_port_t port, |
sahilmgandhi | 18:6a4db94011d3 | 133 | ioport_port_mask_t mask) |
sahilmgandhi | 18:6a4db94011d3 | 134 | { |
sahilmgandhi | 18:6a4db94011d3 | 135 | arch_ioport_port_to_base(port)->GPIO_GPERC = mask; |
sahilmgandhi | 18:6a4db94011d3 | 136 | } |
sahilmgandhi | 18:6a4db94011d3 | 137 | |
sahilmgandhi | 18:6a4db94011d3 | 138 | __always_inline static void arch_ioport_enable_pin(ioport_pin_t pin) |
sahilmgandhi | 18:6a4db94011d3 | 139 | { |
sahilmgandhi | 18:6a4db94011d3 | 140 | arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin), |
sahilmgandhi | 18:6a4db94011d3 | 141 | arch_ioport_pin_to_mask(pin)); |
sahilmgandhi | 18:6a4db94011d3 | 142 | } |
sahilmgandhi | 18:6a4db94011d3 | 143 | |
sahilmgandhi | 18:6a4db94011d3 | 144 | __always_inline static void arch_ioport_disable_pin(ioport_pin_t pin) |
sahilmgandhi | 18:6a4db94011d3 | 145 | { |
sahilmgandhi | 18:6a4db94011d3 | 146 | arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin), |
sahilmgandhi | 18:6a4db94011d3 | 147 | arch_ioport_pin_to_mask(pin)); |
sahilmgandhi | 18:6a4db94011d3 | 148 | } |
sahilmgandhi | 18:6a4db94011d3 | 149 | |
sahilmgandhi | 18:6a4db94011d3 | 150 | __always_inline static void arch_ioport_set_port_mode(ioport_port_t port, |
sahilmgandhi | 18:6a4db94011d3 | 151 | ioport_port_mask_t mask, ioport_mode_t mode) |
sahilmgandhi | 18:6a4db94011d3 | 152 | { |
sahilmgandhi | 18:6a4db94011d3 | 153 | volatile GpioPort *base = arch_ioport_port_to_base(port); |
sahilmgandhi | 18:6a4db94011d3 | 154 | |
sahilmgandhi | 18:6a4db94011d3 | 155 | if (mode & IOPORT_MODE_PULLUP) { |
sahilmgandhi | 18:6a4db94011d3 | 156 | base->GPIO_PUERS = mask; |
sahilmgandhi | 18:6a4db94011d3 | 157 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 158 | base->GPIO_PUERC = mask; |
sahilmgandhi | 18:6a4db94011d3 | 159 | } |
sahilmgandhi | 18:6a4db94011d3 | 160 | |
sahilmgandhi | 18:6a4db94011d3 | 161 | #ifdef IOPORT_MODE_PULLDOWN |
sahilmgandhi | 18:6a4db94011d3 | 162 | if (mode & IOPORT_MODE_PULLDOWN) { |
sahilmgandhi | 18:6a4db94011d3 | 163 | base->GPIO_PDERS = mask; |
sahilmgandhi | 18:6a4db94011d3 | 164 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 165 | base->GPIO_PDERC = mask; |
sahilmgandhi | 18:6a4db94011d3 | 166 | } |
sahilmgandhi | 18:6a4db94011d3 | 167 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 168 | |
sahilmgandhi | 18:6a4db94011d3 | 169 | if (mode & IOPORT_MODE_GLITCH_FILTER) { |
sahilmgandhi | 18:6a4db94011d3 | 170 | base->GPIO_GFERS = mask; |
sahilmgandhi | 18:6a4db94011d3 | 171 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 172 | base->GPIO_GFERC = mask; |
sahilmgandhi | 18:6a4db94011d3 | 173 | } |
sahilmgandhi | 18:6a4db94011d3 | 174 | |
sahilmgandhi | 18:6a4db94011d3 | 175 | #ifdef IOPORT_MODE_DRIVE_STRENGTH |
sahilmgandhi | 18:6a4db94011d3 | 176 | if (mode & IOPORT_MODE_DRIVE_STRENGTH) { |
sahilmgandhi | 18:6a4db94011d3 | 177 | base->GPIO_ODCR0S = mask; |
sahilmgandhi | 18:6a4db94011d3 | 178 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 179 | base->GPIO_ODCR0C = mask; |
sahilmgandhi | 18:6a4db94011d3 | 180 | } |
sahilmgandhi | 18:6a4db94011d3 | 181 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 182 | |
sahilmgandhi | 18:6a4db94011d3 | 183 | if (mode & IOPORT_MODE_MUX_BIT0) { |
sahilmgandhi | 18:6a4db94011d3 | 184 | base->GPIO_PMR0S = mask; |
sahilmgandhi | 18:6a4db94011d3 | 185 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 186 | base->GPIO_PMR0C = mask; |
sahilmgandhi | 18:6a4db94011d3 | 187 | } |
sahilmgandhi | 18:6a4db94011d3 | 188 | |
sahilmgandhi | 18:6a4db94011d3 | 189 | if (mode & IOPORT_MODE_MUX_BIT1) { |
sahilmgandhi | 18:6a4db94011d3 | 190 | base->GPIO_PMR1S = mask; |
sahilmgandhi | 18:6a4db94011d3 | 191 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 192 | base->GPIO_PMR1C = mask; |
sahilmgandhi | 18:6a4db94011d3 | 193 | } |
sahilmgandhi | 18:6a4db94011d3 | 194 | |
sahilmgandhi | 18:6a4db94011d3 | 195 | #ifdef IOPORT_MODE_MUX_BIT2 |
sahilmgandhi | 18:6a4db94011d3 | 196 | if (mode & IOPORT_MODE_MUX_BIT2) { |
sahilmgandhi | 18:6a4db94011d3 | 197 | base->GPIO_PMR2S = mask; |
sahilmgandhi | 18:6a4db94011d3 | 198 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 199 | base->GPIO_PMR2C = mask; |
sahilmgandhi | 18:6a4db94011d3 | 200 | } |
sahilmgandhi | 18:6a4db94011d3 | 201 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 202 | } |
sahilmgandhi | 18:6a4db94011d3 | 203 | |
sahilmgandhi | 18:6a4db94011d3 | 204 | __always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin, |
sahilmgandhi | 18:6a4db94011d3 | 205 | ioport_mode_t mode) |
sahilmgandhi | 18:6a4db94011d3 | 206 | { |
sahilmgandhi | 18:6a4db94011d3 | 207 | arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin), |
sahilmgandhi | 18:6a4db94011d3 | 208 | arch_ioport_pin_to_mask(pin), mode); |
sahilmgandhi | 18:6a4db94011d3 | 209 | } |
sahilmgandhi | 18:6a4db94011d3 | 210 | |
sahilmgandhi | 18:6a4db94011d3 | 211 | __always_inline static void arch_ioport_set_port_dir(ioport_port_t port, |
sahilmgandhi | 18:6a4db94011d3 | 212 | ioport_port_mask_t mask, unsigned char group_direction) |
sahilmgandhi | 18:6a4db94011d3 | 213 | { |
sahilmgandhi | 18:6a4db94011d3 | 214 | if (group_direction == IOPORT_DIR_OUTPUT) { |
sahilmgandhi | 18:6a4db94011d3 | 215 | arch_ioport_port_to_base(port)->GPIO_ODERS = mask; |
sahilmgandhi | 18:6a4db94011d3 | 216 | // Always disable the Schmitt trigger for output pins. |
sahilmgandhi | 18:6a4db94011d3 | 217 | arch_ioport_port_to_base(port)->GPIO_STERC = mask; |
sahilmgandhi | 18:6a4db94011d3 | 218 | } else if (group_direction == IOPORT_DIR_INPUT) { |
sahilmgandhi | 18:6a4db94011d3 | 219 | arch_ioport_port_to_base(port)->GPIO_ODERC = mask; |
sahilmgandhi | 18:6a4db94011d3 | 220 | // Always enable the Schmitt trigger for input pins. |
sahilmgandhi | 18:6a4db94011d3 | 221 | arch_ioport_port_to_base(port)->GPIO_STERS = mask; |
sahilmgandhi | 18:6a4db94011d3 | 222 | } |
sahilmgandhi | 18:6a4db94011d3 | 223 | } |
sahilmgandhi | 18:6a4db94011d3 | 224 | |
sahilmgandhi | 18:6a4db94011d3 | 225 | __always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin, |
sahilmgandhi | 18:6a4db94011d3 | 226 | enum ioport_direction dir) |
sahilmgandhi | 18:6a4db94011d3 | 227 | { |
sahilmgandhi | 18:6a4db94011d3 | 228 | if (dir == IOPORT_DIR_OUTPUT) { |
sahilmgandhi | 18:6a4db94011d3 | 229 | arch_ioport_pin_to_base(pin)->GPIO_ODERS = arch_ioport_pin_to_mask(pin); |
sahilmgandhi | 18:6a4db94011d3 | 230 | // Always disable the Schmitt trigger for output pins. |
sahilmgandhi | 18:6a4db94011d3 | 231 | arch_ioport_pin_to_base(pin)->GPIO_STERC = arch_ioport_pin_to_mask(pin); |
sahilmgandhi | 18:6a4db94011d3 | 232 | } else if (dir == IOPORT_DIR_INPUT) { |
sahilmgandhi | 18:6a4db94011d3 | 233 | arch_ioport_pin_to_base(pin)->GPIO_ODERC = arch_ioport_pin_to_mask(pin); |
sahilmgandhi | 18:6a4db94011d3 | 234 | // Always enable the Schmitt trigger for input pins. |
sahilmgandhi | 18:6a4db94011d3 | 235 | arch_ioport_pin_to_base(pin)->GPIO_STERS = arch_ioport_pin_to_mask(pin); |
sahilmgandhi | 18:6a4db94011d3 | 236 | } |
sahilmgandhi | 18:6a4db94011d3 | 237 | } |
sahilmgandhi | 18:6a4db94011d3 | 238 | |
sahilmgandhi | 18:6a4db94011d3 | 239 | __always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin, |
sahilmgandhi | 18:6a4db94011d3 | 240 | bool level) |
sahilmgandhi | 18:6a4db94011d3 | 241 | { |
sahilmgandhi | 18:6a4db94011d3 | 242 | if (level) { |
sahilmgandhi | 18:6a4db94011d3 | 243 | arch_ioport_pin_to_base(pin)->GPIO_OVRS = arch_ioport_pin_to_mask(pin); |
sahilmgandhi | 18:6a4db94011d3 | 244 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 245 | arch_ioport_pin_to_base(pin)->GPIO_OVRC = arch_ioport_pin_to_mask(pin); |
sahilmgandhi | 18:6a4db94011d3 | 246 | } |
sahilmgandhi | 18:6a4db94011d3 | 247 | } |
sahilmgandhi | 18:6a4db94011d3 | 248 | |
sahilmgandhi | 18:6a4db94011d3 | 249 | __always_inline static void arch_ioport_set_port_level(ioport_port_t port, |
sahilmgandhi | 18:6a4db94011d3 | 250 | ioport_port_mask_t mask, ioport_port_mask_t level) |
sahilmgandhi | 18:6a4db94011d3 | 251 | { |
sahilmgandhi | 18:6a4db94011d3 | 252 | volatile GpioPort *base = arch_ioport_port_to_base(port); |
sahilmgandhi | 18:6a4db94011d3 | 253 | if (level) { |
sahilmgandhi | 18:6a4db94011d3 | 254 | base->GPIO_OVRS = mask; |
sahilmgandhi | 18:6a4db94011d3 | 255 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 256 | base->GPIO_OVRC = mask; |
sahilmgandhi | 18:6a4db94011d3 | 257 | } |
sahilmgandhi | 18:6a4db94011d3 | 258 | } |
sahilmgandhi | 18:6a4db94011d3 | 259 | |
sahilmgandhi | 18:6a4db94011d3 | 260 | __always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin) |
sahilmgandhi | 18:6a4db94011d3 | 261 | { |
sahilmgandhi | 18:6a4db94011d3 | 262 | return arch_ioport_pin_to_base(pin)->GPIO_PVR & arch_ioport_pin_to_mask(pin); |
sahilmgandhi | 18:6a4db94011d3 | 263 | } |
sahilmgandhi | 18:6a4db94011d3 | 264 | |
sahilmgandhi | 18:6a4db94011d3 | 265 | __always_inline static ioport_port_mask_t arch_ioport_get_port_level( |
sahilmgandhi | 18:6a4db94011d3 | 266 | ioport_port_t port, ioport_port_mask_t mask) |
sahilmgandhi | 18:6a4db94011d3 | 267 | { |
sahilmgandhi | 18:6a4db94011d3 | 268 | return arch_ioport_port_to_base(port)->GPIO_PVR & mask; |
sahilmgandhi | 18:6a4db94011d3 | 269 | } |
sahilmgandhi | 18:6a4db94011d3 | 270 | |
sahilmgandhi | 18:6a4db94011d3 | 271 | __always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin) |
sahilmgandhi | 18:6a4db94011d3 | 272 | { |
sahilmgandhi | 18:6a4db94011d3 | 273 | arch_ioport_pin_to_base(pin)->GPIO_OVRT = arch_ioport_pin_to_mask(pin); |
sahilmgandhi | 18:6a4db94011d3 | 274 | } |
sahilmgandhi | 18:6a4db94011d3 | 275 | |
sahilmgandhi | 18:6a4db94011d3 | 276 | __always_inline static void arch_ioport_toggle_port_level(ioport_port_t port, |
sahilmgandhi | 18:6a4db94011d3 | 277 | ioport_port_mask_t mask) |
sahilmgandhi | 18:6a4db94011d3 | 278 | { |
sahilmgandhi | 18:6a4db94011d3 | 279 | arch_ioport_port_to_base(port)->GPIO_OVRT = mask; |
sahilmgandhi | 18:6a4db94011d3 | 280 | } |
sahilmgandhi | 18:6a4db94011d3 | 281 | |
sahilmgandhi | 18:6a4db94011d3 | 282 | __always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port, |
sahilmgandhi | 18:6a4db94011d3 | 283 | ioport_port_mask_t mask, enum ioport_sense pin_sense) |
sahilmgandhi | 18:6a4db94011d3 | 284 | { |
sahilmgandhi | 18:6a4db94011d3 | 285 | volatile GpioPort *base = arch_ioport_port_to_base(port); |
sahilmgandhi | 18:6a4db94011d3 | 286 | |
sahilmgandhi | 18:6a4db94011d3 | 287 | if (pin_sense & 0x01) { |
sahilmgandhi | 18:6a4db94011d3 | 288 | base->GPIO_IMR0S = mask; |
sahilmgandhi | 18:6a4db94011d3 | 289 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 290 | base->GPIO_IMR0C = mask; |
sahilmgandhi | 18:6a4db94011d3 | 291 | } |
sahilmgandhi | 18:6a4db94011d3 | 292 | |
sahilmgandhi | 18:6a4db94011d3 | 293 | if (pin_sense & 0x02) { |
sahilmgandhi | 18:6a4db94011d3 | 294 | base->GPIO_IMR1S = mask; |
sahilmgandhi | 18:6a4db94011d3 | 295 | } else { |
sahilmgandhi | 18:6a4db94011d3 | 296 | base->GPIO_IMR1C = mask; |
sahilmgandhi | 18:6a4db94011d3 | 297 | } |
sahilmgandhi | 18:6a4db94011d3 | 298 | } |
sahilmgandhi | 18:6a4db94011d3 | 299 | |
sahilmgandhi | 18:6a4db94011d3 | 300 | __always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin, |
sahilmgandhi | 18:6a4db94011d3 | 301 | enum ioport_sense pin_sense) |
sahilmgandhi | 18:6a4db94011d3 | 302 | { |
sahilmgandhi | 18:6a4db94011d3 | 303 | arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin), |
sahilmgandhi | 18:6a4db94011d3 | 304 | arch_ioport_pin_to_mask(pin), pin_sense); |
sahilmgandhi | 18:6a4db94011d3 | 305 | } |
sahilmgandhi | 18:6a4db94011d3 | 306 | |
sahilmgandhi | 18:6a4db94011d3 | 307 | #endif /* IOPORT_SAM_H */ |