Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pio/pio_handler.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief Parallel Input/Output (PIO) interrupt handler for SAM. |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | #include "pio.h" |
sahilmgandhi | 18:6a4db94011d3 | 48 | #include "pio_handler.h" |
sahilmgandhi | 18:6a4db94011d3 | 49 | |
sahilmgandhi | 18:6a4db94011d3 | 50 | /** |
sahilmgandhi | 18:6a4db94011d3 | 51 | * Maximum number of interrupt sources that can be defined. This |
sahilmgandhi | 18:6a4db94011d3 | 52 | * constant can be increased, but the current value is the smallest possible one |
sahilmgandhi | 18:6a4db94011d3 | 53 | * that will be compatible with all existing projects. |
sahilmgandhi | 18:6a4db94011d3 | 54 | */ |
sahilmgandhi | 18:6a4db94011d3 | 55 | #define MAX_INTERRUPT_SOURCES 7 |
sahilmgandhi | 18:6a4db94011d3 | 56 | |
sahilmgandhi | 18:6a4db94011d3 | 57 | /** |
sahilmgandhi | 18:6a4db94011d3 | 58 | * Describes a PIO interrupt source, including the PIO instance triggering the |
sahilmgandhi | 18:6a4db94011d3 | 59 | * interrupt and the associated interrupt handler. |
sahilmgandhi | 18:6a4db94011d3 | 60 | */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | struct s_interrupt_source { |
sahilmgandhi | 18:6a4db94011d3 | 62 | uint32_t id; |
sahilmgandhi | 18:6a4db94011d3 | 63 | uint32_t mask; |
sahilmgandhi | 18:6a4db94011d3 | 64 | uint32_t attr; |
sahilmgandhi | 18:6a4db94011d3 | 65 | |
sahilmgandhi | 18:6a4db94011d3 | 66 | /* Interrupt handler. */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | void (*handler) (const uint32_t, const uint32_t); |
sahilmgandhi | 18:6a4db94011d3 | 68 | }; |
sahilmgandhi | 18:6a4db94011d3 | 69 | |
sahilmgandhi | 18:6a4db94011d3 | 70 | |
sahilmgandhi | 18:6a4db94011d3 | 71 | /* List of interrupt sources. */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES]; |
sahilmgandhi | 18:6a4db94011d3 | 73 | |
sahilmgandhi | 18:6a4db94011d3 | 74 | /* Number of currently defined interrupt sources. */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | static uint32_t gs_ul_nb_sources = 0; |
sahilmgandhi | 18:6a4db94011d3 | 76 | |
sahilmgandhi | 18:6a4db94011d3 | 77 | #if (SAM3S || SAM4S || SAM4E) |
sahilmgandhi | 18:6a4db94011d3 | 78 | /* PIO Capture handler */ |
sahilmgandhi | 18:6a4db94011d3 | 79 | static void (*pio_capture_handler)(Pio *) = NULL; |
sahilmgandhi | 18:6a4db94011d3 | 80 | extern uint32_t pio_capture_enable_flag; |
sahilmgandhi | 18:6a4db94011d3 | 81 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 82 | |
sahilmgandhi | 18:6a4db94011d3 | 83 | /** |
sahilmgandhi | 18:6a4db94011d3 | 84 | * \brief Process an interrupt request on the given PIO controller. |
sahilmgandhi | 18:6a4db94011d3 | 85 | * |
sahilmgandhi | 18:6a4db94011d3 | 86 | * \param p_pio PIO controller base address. |
sahilmgandhi | 18:6a4db94011d3 | 87 | * \param ul_id PIO controller ID. |
sahilmgandhi | 18:6a4db94011d3 | 88 | */ |
sahilmgandhi | 18:6a4db94011d3 | 89 | void pio_handler_process(Pio *p_pio, uint32_t ul_id) |
sahilmgandhi | 18:6a4db94011d3 | 90 | { |
sahilmgandhi | 18:6a4db94011d3 | 91 | uint32_t status; |
sahilmgandhi | 18:6a4db94011d3 | 92 | uint32_t i; |
sahilmgandhi | 18:6a4db94011d3 | 93 | |
sahilmgandhi | 18:6a4db94011d3 | 94 | /* Read PIO controller status */ |
sahilmgandhi | 18:6a4db94011d3 | 95 | status = pio_get_interrupt_status(p_pio); |
sahilmgandhi | 18:6a4db94011d3 | 96 | status &= pio_get_interrupt_mask(p_pio); |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | /* Check pending events */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | if (status != 0) { |
sahilmgandhi | 18:6a4db94011d3 | 100 | /* Find triggering source */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | i = 0; |
sahilmgandhi | 18:6a4db94011d3 | 102 | while (status != 0) { |
sahilmgandhi | 18:6a4db94011d3 | 103 | /* Source is configured on the same controller */ |
sahilmgandhi | 18:6a4db94011d3 | 104 | if (gs_interrupt_sources[i].id == ul_id) { |
sahilmgandhi | 18:6a4db94011d3 | 105 | /* Source has PIOs whose statuses have changed */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | if ((status & gs_interrupt_sources[i].mask) != 0) { |
sahilmgandhi | 18:6a4db94011d3 | 107 | gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, |
sahilmgandhi | 18:6a4db94011d3 | 108 | gs_interrupt_sources[i].mask); |
sahilmgandhi | 18:6a4db94011d3 | 109 | status &= ~(gs_interrupt_sources[i].mask); |
sahilmgandhi | 18:6a4db94011d3 | 110 | } |
sahilmgandhi | 18:6a4db94011d3 | 111 | } |
sahilmgandhi | 18:6a4db94011d3 | 112 | i++; |
sahilmgandhi | 18:6a4db94011d3 | 113 | if (i >= MAX_INTERRUPT_SOURCES) { |
sahilmgandhi | 18:6a4db94011d3 | 114 | break; |
sahilmgandhi | 18:6a4db94011d3 | 115 | } |
sahilmgandhi | 18:6a4db94011d3 | 116 | } |
sahilmgandhi | 18:6a4db94011d3 | 117 | } |
sahilmgandhi | 18:6a4db94011d3 | 118 | |
sahilmgandhi | 18:6a4db94011d3 | 119 | /* Check capture events */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | #if (SAM3S || SAM4S || SAM4E) |
sahilmgandhi | 18:6a4db94011d3 | 121 | if (pio_capture_enable_flag) { |
sahilmgandhi | 18:6a4db94011d3 | 122 | if (pio_capture_handler) { |
sahilmgandhi | 18:6a4db94011d3 | 123 | pio_capture_handler(p_pio); |
sahilmgandhi | 18:6a4db94011d3 | 124 | } |
sahilmgandhi | 18:6a4db94011d3 | 125 | } |
sahilmgandhi | 18:6a4db94011d3 | 126 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 127 | } |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | /** |
sahilmgandhi | 18:6a4db94011d3 | 130 | * \brief Set an interrupt handler for the provided pins. |
sahilmgandhi | 18:6a4db94011d3 | 131 | * The provided handler will be called with the triggering pin as its parameter |
sahilmgandhi | 18:6a4db94011d3 | 132 | * as soon as an interrupt is detected. |
sahilmgandhi | 18:6a4db94011d3 | 133 | * |
sahilmgandhi | 18:6a4db94011d3 | 134 | * \param p_pio PIO controller base address. |
sahilmgandhi | 18:6a4db94011d3 | 135 | * \param ul_id PIO ID. |
sahilmgandhi | 18:6a4db94011d3 | 136 | * \param ul_mask Pins (bit mask) to configure. |
sahilmgandhi | 18:6a4db94011d3 | 137 | * \param ul_attr Pins attribute to configure. |
sahilmgandhi | 18:6a4db94011d3 | 138 | * \param p_handler Interrupt handler function pointer. |
sahilmgandhi | 18:6a4db94011d3 | 139 | * |
sahilmgandhi | 18:6a4db94011d3 | 140 | * \return 0 if successful, 1 if the maximum number of sources has been defined. |
sahilmgandhi | 18:6a4db94011d3 | 141 | */ |
sahilmgandhi | 18:6a4db94011d3 | 142 | uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, |
sahilmgandhi | 18:6a4db94011d3 | 143 | uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)) |
sahilmgandhi | 18:6a4db94011d3 | 144 | { |
sahilmgandhi | 18:6a4db94011d3 | 145 | struct s_interrupt_source *pSource; |
sahilmgandhi | 18:6a4db94011d3 | 146 | |
sahilmgandhi | 18:6a4db94011d3 | 147 | if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES) |
sahilmgandhi | 18:6a4db94011d3 | 148 | return 1; |
sahilmgandhi | 18:6a4db94011d3 | 149 | |
sahilmgandhi | 18:6a4db94011d3 | 150 | /* Define new source */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | pSource = &(gs_interrupt_sources[gs_ul_nb_sources]); |
sahilmgandhi | 18:6a4db94011d3 | 152 | pSource->id = ul_id; |
sahilmgandhi | 18:6a4db94011d3 | 153 | pSource->mask = ul_mask; |
sahilmgandhi | 18:6a4db94011d3 | 154 | pSource->attr = ul_attr; |
sahilmgandhi | 18:6a4db94011d3 | 155 | pSource->handler = p_handler; |
sahilmgandhi | 18:6a4db94011d3 | 156 | gs_ul_nb_sources++; |
sahilmgandhi | 18:6a4db94011d3 | 157 | |
sahilmgandhi | 18:6a4db94011d3 | 158 | /* Configure interrupt mode */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | pio_configure_interrupt(p_pio, ul_mask, ul_attr); |
sahilmgandhi | 18:6a4db94011d3 | 160 | |
sahilmgandhi | 18:6a4db94011d3 | 161 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 162 | } |
sahilmgandhi | 18:6a4db94011d3 | 163 | |
sahilmgandhi | 18:6a4db94011d3 | 164 | #if (SAM3S || SAM4S || SAM4E) |
sahilmgandhi | 18:6a4db94011d3 | 165 | /** |
sahilmgandhi | 18:6a4db94011d3 | 166 | * \brief Set a capture interrupt handler for all PIO. |
sahilmgandhi | 18:6a4db94011d3 | 167 | * |
sahilmgandhi | 18:6a4db94011d3 | 168 | * The handler will be called with the triggering PIO as its parameter |
sahilmgandhi | 18:6a4db94011d3 | 169 | * as soon as an interrupt is detected. |
sahilmgandhi | 18:6a4db94011d3 | 170 | * |
sahilmgandhi | 18:6a4db94011d3 | 171 | * \param p_handler Interrupt handler function pointer. |
sahilmgandhi | 18:6a4db94011d3 | 172 | * |
sahilmgandhi | 18:6a4db94011d3 | 173 | */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | void pio_capture_handler_set(void (*p_handler)(Pio *)) |
sahilmgandhi | 18:6a4db94011d3 | 175 | { |
sahilmgandhi | 18:6a4db94011d3 | 176 | pio_capture_handler = p_handler; |
sahilmgandhi | 18:6a4db94011d3 | 177 | } |
sahilmgandhi | 18:6a4db94011d3 | 178 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 179 | |
sahilmgandhi | 18:6a4db94011d3 | 180 | #ifdef ID_PIOA |
sahilmgandhi | 18:6a4db94011d3 | 181 | /** |
sahilmgandhi | 18:6a4db94011d3 | 182 | * \brief Set an interrupt handler for the specified pin. |
sahilmgandhi | 18:6a4db94011d3 | 183 | * The provided handler will be called with the triggering pin as its parameter |
sahilmgandhi | 18:6a4db94011d3 | 184 | * as soon as an interrupt is detected. |
sahilmgandhi | 18:6a4db94011d3 | 185 | * |
sahilmgandhi | 18:6a4db94011d3 | 186 | * \param ul_pin Pin index to configure. |
sahilmgandhi | 18:6a4db94011d3 | 187 | * \param ul_flag Pin flag. |
sahilmgandhi | 18:6a4db94011d3 | 188 | * \param p_handler Interrupt handler function pointer. |
sahilmgandhi | 18:6a4db94011d3 | 189 | * |
sahilmgandhi | 18:6a4db94011d3 | 190 | * \return 0 if successful, 1 if the maximum number of sources has been defined. |
sahilmgandhi | 18:6a4db94011d3 | 191 | */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, |
sahilmgandhi | 18:6a4db94011d3 | 193 | void (*p_handler) (uint32_t, uint32_t)) |
sahilmgandhi | 18:6a4db94011d3 | 194 | { |
sahilmgandhi | 18:6a4db94011d3 | 195 | Pio *p_pio = pio_get_pin_group(ul_pin); |
sahilmgandhi | 18:6a4db94011d3 | 196 | uint32_t group_id = pio_get_pin_group_id(ul_pin); |
sahilmgandhi | 18:6a4db94011d3 | 197 | uint32_t group_mask = pio_get_pin_group_mask(ul_pin); |
sahilmgandhi | 18:6a4db94011d3 | 198 | |
sahilmgandhi | 18:6a4db94011d3 | 199 | return pio_handler_set(p_pio, group_id, group_mask, ul_flag, p_handler); |
sahilmgandhi | 18:6a4db94011d3 | 200 | } |
sahilmgandhi | 18:6a4db94011d3 | 201 | |
sahilmgandhi | 18:6a4db94011d3 | 202 | /** |
sahilmgandhi | 18:6a4db94011d3 | 203 | * \brief Parallel IO Controller A interrupt handler. |
sahilmgandhi | 18:6a4db94011d3 | 204 | * Redefined PIOA interrupt handler for NVIC interrupt table. |
sahilmgandhi | 18:6a4db94011d3 | 205 | */ |
sahilmgandhi | 18:6a4db94011d3 | 206 | void PIOA_Handler(void) |
sahilmgandhi | 18:6a4db94011d3 | 207 | { |
sahilmgandhi | 18:6a4db94011d3 | 208 | pio_handler_process(PIOA, ID_PIOA); |
sahilmgandhi | 18:6a4db94011d3 | 209 | } |
sahilmgandhi | 18:6a4db94011d3 | 210 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 211 | |
sahilmgandhi | 18:6a4db94011d3 | 212 | #ifdef ID_PIOB |
sahilmgandhi | 18:6a4db94011d3 | 213 | /** |
sahilmgandhi | 18:6a4db94011d3 | 214 | * \brief Parallel IO Controller B interrupt handler |
sahilmgandhi | 18:6a4db94011d3 | 215 | * Redefined PIOB interrupt handler for NVIC interrupt table. |
sahilmgandhi | 18:6a4db94011d3 | 216 | */ |
sahilmgandhi | 18:6a4db94011d3 | 217 | void PIOB_Handler(void) |
sahilmgandhi | 18:6a4db94011d3 | 218 | { |
sahilmgandhi | 18:6a4db94011d3 | 219 | pio_handler_process(PIOB, ID_PIOB); |
sahilmgandhi | 18:6a4db94011d3 | 220 | } |
sahilmgandhi | 18:6a4db94011d3 | 221 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 222 | |
sahilmgandhi | 18:6a4db94011d3 | 223 | #ifdef ID_PIOC |
sahilmgandhi | 18:6a4db94011d3 | 224 | /** |
sahilmgandhi | 18:6a4db94011d3 | 225 | * \brief Parallel IO Controller C interrupt handler. |
sahilmgandhi | 18:6a4db94011d3 | 226 | * Redefined PIOC interrupt handler for NVIC interrupt table. |
sahilmgandhi | 18:6a4db94011d3 | 227 | */ |
sahilmgandhi | 18:6a4db94011d3 | 228 | void PIOC_Handler(void) |
sahilmgandhi | 18:6a4db94011d3 | 229 | { |
sahilmgandhi | 18:6a4db94011d3 | 230 | pio_handler_process(PIOC, ID_PIOC); |
sahilmgandhi | 18:6a4db94011d3 | 231 | } |
sahilmgandhi | 18:6a4db94011d3 | 232 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 233 | |
sahilmgandhi | 18:6a4db94011d3 | 234 | #ifdef ID_PIOD |
sahilmgandhi | 18:6a4db94011d3 | 235 | /** |
sahilmgandhi | 18:6a4db94011d3 | 236 | * \brief Parallel IO Controller D interrupt handler. |
sahilmgandhi | 18:6a4db94011d3 | 237 | * Redefined PIOD interrupt handler for NVIC interrupt table. |
sahilmgandhi | 18:6a4db94011d3 | 238 | */ |
sahilmgandhi | 18:6a4db94011d3 | 239 | void PIOD_Handler(void) |
sahilmgandhi | 18:6a4db94011d3 | 240 | { |
sahilmgandhi | 18:6a4db94011d3 | 241 | pio_handler_process(PIOD, ID_PIOD); |
sahilmgandhi | 18:6a4db94011d3 | 242 | } |
sahilmgandhi | 18:6a4db94011d3 | 243 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 244 | |
sahilmgandhi | 18:6a4db94011d3 | 245 | #ifdef ID_PIOE |
sahilmgandhi | 18:6a4db94011d3 | 246 | /** |
sahilmgandhi | 18:6a4db94011d3 | 247 | * \brief Parallel IO Controller E interrupt handler. |
sahilmgandhi | 18:6a4db94011d3 | 248 | * Redefined PIOE interrupt handler for NVIC interrupt table. |
sahilmgandhi | 18:6a4db94011d3 | 249 | */ |
sahilmgandhi | 18:6a4db94011d3 | 250 | void PIOE_Handler(void) |
sahilmgandhi | 18:6a4db94011d3 | 251 | { |
sahilmgandhi | 18:6a4db94011d3 | 252 | pio_handler_process(PIOE, ID_PIOE); |
sahilmgandhi | 18:6a4db94011d3 | 253 | } |
sahilmgandhi | 18:6a4db94011d3 | 254 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 255 | |
sahilmgandhi | 18:6a4db94011d3 | 256 | #ifdef ID_PIOF |
sahilmgandhi | 18:6a4db94011d3 | 257 | /** |
sahilmgandhi | 18:6a4db94011d3 | 258 | * \brief Parallel IO Controller F interrupt handler. |
sahilmgandhi | 18:6a4db94011d3 | 259 | * Redefined PIOF interrupt handler for NVIC interrupt table. |
sahilmgandhi | 18:6a4db94011d3 | 260 | */ |
sahilmgandhi | 18:6a4db94011d3 | 261 | void PIOF_Handler(void) |
sahilmgandhi | 18:6a4db94011d3 | 262 | { |
sahilmgandhi | 18:6a4db94011d3 | 263 | pio_handler_process(PIOF, ID_PIOF); |
sahilmgandhi | 18:6a4db94011d3 | 264 | } |
sahilmgandhi | 18:6a4db94011d3 | 265 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 266 | |
sahilmgandhi | 18:6a4db94011d3 | 267 | /** |
sahilmgandhi | 18:6a4db94011d3 | 268 | * \brief Initialize PIO interrupt management logic. |
sahilmgandhi | 18:6a4db94011d3 | 269 | * |
sahilmgandhi | 18:6a4db94011d3 | 270 | * \param p_pio PIO controller base address. |
sahilmgandhi | 18:6a4db94011d3 | 271 | * \param ul_irqn NVIC line number. |
sahilmgandhi | 18:6a4db94011d3 | 272 | * \param ul_priority PIO controller interrupts priority. |
sahilmgandhi | 18:6a4db94011d3 | 273 | */ |
sahilmgandhi | 18:6a4db94011d3 | 274 | void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority) |
sahilmgandhi | 18:6a4db94011d3 | 275 | { |
sahilmgandhi | 18:6a4db94011d3 | 276 | uint32_t bitmask = 0; |
sahilmgandhi | 18:6a4db94011d3 | 277 | |
sahilmgandhi | 18:6a4db94011d3 | 278 | bitmask = pio_get_interrupt_mask(p_pio); |
sahilmgandhi | 18:6a4db94011d3 | 279 | pio_disable_interrupt(p_pio, 0xFFFFFFFF); |
sahilmgandhi | 18:6a4db94011d3 | 280 | pio_get_interrupt_status(p_pio); |
sahilmgandhi | 18:6a4db94011d3 | 281 | NVIC_DisableIRQ(ul_irqn); |
sahilmgandhi | 18:6a4db94011d3 | 282 | NVIC_ClearPendingIRQ(ul_irqn); |
sahilmgandhi | 18:6a4db94011d3 | 283 | NVIC_SetPriority(ul_irqn, ul_priority); |
sahilmgandhi | 18:6a4db94011d3 | 284 | NVIC_EnableIRQ(ul_irqn); |
sahilmgandhi | 18:6a4db94011d3 | 285 | pio_enable_interrupt(p_pio, bitmask); |
sahilmgandhi | 18:6a4db94011d3 | 286 | } |