MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ARM_SSG/TARGET_IOTSS/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2015 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 17 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 18 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 19 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 20
sahilmgandhi 18:6a4db94011d3 21 #define CHANNEL_NUM 32
sahilmgandhi 18:6a4db94011d3 22 #define CMSDK_GPIO_0 CMSDK_GPIO0
sahilmgandhi 18:6a4db94011d3 23 #define CMSDK_GPIO_1 CMSDK_GPIO1
sahilmgandhi 18:6a4db94011d3 24 #define PININT_IRQ 0
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sahilmgandhi 18:6a4db94011d3 27 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 static inline void handle_interrupt_in(uint32_t channel) {
sahilmgandhi 18:6a4db94011d3 30 uint32_t ch_bit = (1 << channel);
sahilmgandhi 18:6a4db94011d3 31 // Return immediately if:
sahilmgandhi 18:6a4db94011d3 32 // * The interrupt was already served
sahilmgandhi 18:6a4db94011d3 33 // * There is no user handler
sahilmgandhi 18:6a4db94011d3 34 // * It is a level interrupt, not an edge interrupt
sahilmgandhi 18:6a4db94011d3 35 if (ch_bit <16){
sahilmgandhi 18:6a4db94011d3 36 if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return;
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
sahilmgandhi 18:6a4db94011d3 39 irq_handler(channel_ids[channel], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 40 CMSDK_GPIO_0->INTPOLSET = ch_bit;
sahilmgandhi 18:6a4db94011d3 41 }
sahilmgandhi 18:6a4db94011d3 42 if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
sahilmgandhi 18:6a4db94011d3 43 irq_handler(channel_ids[channel], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 44 }
sahilmgandhi 18:6a4db94011d3 45 CMSDK_GPIO_0->INTCLEAR = ch_bit;
sahilmgandhi 18:6a4db94011d3 46 }
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 if (ch_bit>=16) {
sahilmgandhi 18:6a4db94011d3 49 if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return;
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
sahilmgandhi 18:6a4db94011d3 52 irq_handler(channel_ids[channel], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 53 CMSDK_GPIO_1->INTPOLSET = ch_bit;
sahilmgandhi 18:6a4db94011d3 54 }
sahilmgandhi 18:6a4db94011d3 55 if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
sahilmgandhi 18:6a4db94011d3 56 irq_handler(channel_ids[channel], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 57 }
sahilmgandhi 18:6a4db94011d3 58 CMSDK_GPIO_1->INTCLEAR = ch_bit;
sahilmgandhi 18:6a4db94011d3 59 }
sahilmgandhi 18:6a4db94011d3 60 }
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 void gpio0_irq0(void) {handle_interrupt_in(0);}
sahilmgandhi 18:6a4db94011d3 63 void gpio0_irq1(void) {handle_interrupt_in(1);}
sahilmgandhi 18:6a4db94011d3 64 void gpio0_irq2(void) {handle_interrupt_in(2);}
sahilmgandhi 18:6a4db94011d3 65 void gpio0_irq3(void) {handle_interrupt_in(3);}
sahilmgandhi 18:6a4db94011d3 66 void gpio0_irq4(void) {handle_interrupt_in(4);}
sahilmgandhi 18:6a4db94011d3 67 void gpio0_irq5(void) {handle_interrupt_in(5);}
sahilmgandhi 18:6a4db94011d3 68 void gpio0_irq6(void) {handle_interrupt_in(6);}
sahilmgandhi 18:6a4db94011d3 69 void gpio0_irq7(void) {handle_interrupt_in(7);}
sahilmgandhi 18:6a4db94011d3 70 void gpio0_irq8(void) {handle_interrupt_in(8);}
sahilmgandhi 18:6a4db94011d3 71 void gpio0_irq9(void) {handle_interrupt_in(9);}
sahilmgandhi 18:6a4db94011d3 72 void gpio0_irq10(void) {handle_interrupt_in(10);}
sahilmgandhi 18:6a4db94011d3 73 void gpio0_irq11(void) {handle_interrupt_in(11);}
sahilmgandhi 18:6a4db94011d3 74 void gpio0_irq12(void) {handle_interrupt_in(12);}
sahilmgandhi 18:6a4db94011d3 75 void gpio0_irq13(void) {handle_interrupt_in(13);}
sahilmgandhi 18:6a4db94011d3 76 void gpio0_irq14(void) {handle_interrupt_in(14);}
sahilmgandhi 18:6a4db94011d3 77 void gpio0_irq15(void) {handle_interrupt_in(15);}
sahilmgandhi 18:6a4db94011d3 78 void gpio1_irq0(void) {handle_interrupt_in(16);}
sahilmgandhi 18:6a4db94011d3 79 void gpio1_irq1(void) {handle_interrupt_in(17);}
sahilmgandhi 18:6a4db94011d3 80 void gpio1_irq2(void) {handle_interrupt_in(18);}
sahilmgandhi 18:6a4db94011d3 81 void gpio1_irq3(void) {handle_interrupt_in(19);}
sahilmgandhi 18:6a4db94011d3 82 void gpio1_irq4(void) {handle_interrupt_in(20);}
sahilmgandhi 18:6a4db94011d3 83 void gpio1_irq5(void) {handle_interrupt_in(21);}
sahilmgandhi 18:6a4db94011d3 84 void gpio1_irq6(void) {handle_interrupt_in(22);}
sahilmgandhi 18:6a4db94011d3 85 void gpio1_irq7(void) {handle_interrupt_in(23);}
sahilmgandhi 18:6a4db94011d3 86 void gpio1_irq8(void) {handle_interrupt_in(24);}
sahilmgandhi 18:6a4db94011d3 87 void gpio1_irq9(void) {handle_interrupt_in(25);}
sahilmgandhi 18:6a4db94011d3 88 void gpio1_irq10(void) {handle_interrupt_in(26);}
sahilmgandhi 18:6a4db94011d3 89 void gpio1_irq11(void) {handle_interrupt_in(27);}
sahilmgandhi 18:6a4db94011d3 90 void gpio1_irq12(void) {handle_interrupt_in(28);}
sahilmgandhi 18:6a4db94011d3 91 void gpio1_irq13(void) {handle_interrupt_in(29);}
sahilmgandhi 18:6a4db94011d3 92 void gpio1_irq14(void) {handle_interrupt_in(30);}
sahilmgandhi 18:6a4db94011d3 93 void gpio1_irq15(void) {handle_interrupt_in(31);}
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sahilmgandhi 18:6a4db94011d3 97 if (pin == NC) {return -1;}
sahilmgandhi 18:6a4db94011d3 98 else {
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 int found_free_channel = 0;
sahilmgandhi 18:6a4db94011d3 103 int i = 0;
sahilmgandhi 18:6a4db94011d3 104 for (i=0; i<CHANNEL_NUM; i++) {
sahilmgandhi 18:6a4db94011d3 105 if (channel_ids[i] == 0) {
sahilmgandhi 18:6a4db94011d3 106 channel_ids[i] = id;
sahilmgandhi 18:6a4db94011d3 107 obj->ch = i;
sahilmgandhi 18:6a4db94011d3 108 found_free_channel = 1;
sahilmgandhi 18:6a4db94011d3 109 break;
sahilmgandhi 18:6a4db94011d3 110 }
sahilmgandhi 18:6a4db94011d3 111 }
sahilmgandhi 18:6a4db94011d3 112 if (!found_free_channel) return -1;
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /* To select a pin for any of the eight pin interrupts, write the pin number
sahilmgandhi 18:6a4db94011d3 116 * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
sahilmgandhi 18:6a4db94011d3 117 * @see: mbed_capi/PinNames.h
sahilmgandhi 18:6a4db94011d3 118 */
sahilmgandhi 18:6a4db94011d3 119 if (pin <16)
sahilmgandhi 18:6a4db94011d3 120 {
sahilmgandhi 18:6a4db94011d3 121 CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
sahilmgandhi 18:6a4db94011d3 122 }
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 if (pin >= 16)
sahilmgandhi 18:6a4db94011d3 125 {
sahilmgandhi 18:6a4db94011d3 126 CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
sahilmgandhi 18:6a4db94011d3 127 }
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 void (*channels_irq)(void) = NULL;
sahilmgandhi 18:6a4db94011d3 130 switch (obj->ch) {
sahilmgandhi 18:6a4db94011d3 131 case 0: channels_irq = &gpio0_irq0; break;
sahilmgandhi 18:6a4db94011d3 132 case 1: channels_irq = &gpio0_irq1; break;
sahilmgandhi 18:6a4db94011d3 133 case 2: channels_irq = &gpio0_irq2; break;
sahilmgandhi 18:6a4db94011d3 134 case 3: channels_irq = &gpio0_irq3; break;
sahilmgandhi 18:6a4db94011d3 135 case 4: channels_irq = &gpio0_irq4; break;
sahilmgandhi 18:6a4db94011d3 136 case 5: channels_irq = &gpio0_irq5; break;
sahilmgandhi 18:6a4db94011d3 137 case 6: channels_irq = &gpio0_irq6; break;
sahilmgandhi 18:6a4db94011d3 138 case 7: channels_irq = &gpio0_irq7; break;
sahilmgandhi 18:6a4db94011d3 139 case 8: channels_irq = &gpio0_irq8; break;
sahilmgandhi 18:6a4db94011d3 140 case 9: channels_irq = &gpio0_irq9; break;
sahilmgandhi 18:6a4db94011d3 141 case 10: channels_irq = &gpio0_irq10; break;
sahilmgandhi 18:6a4db94011d3 142 case 11: channels_irq = &gpio0_irq11; break;
sahilmgandhi 18:6a4db94011d3 143 case 12: channels_irq = &gpio0_irq12; break;
sahilmgandhi 18:6a4db94011d3 144 case 13: channels_irq = &gpio0_irq13; break;
sahilmgandhi 18:6a4db94011d3 145 case 14: channels_irq = &gpio0_irq14; break;
sahilmgandhi 18:6a4db94011d3 146 case 15: channels_irq = &gpio0_irq15; break;
sahilmgandhi 18:6a4db94011d3 147 case 16: channels_irq = &gpio1_irq0; break;
sahilmgandhi 18:6a4db94011d3 148 case 17: channels_irq = &gpio1_irq1; break;
sahilmgandhi 18:6a4db94011d3 149 case 18: channels_irq = &gpio1_irq2; break;
sahilmgandhi 18:6a4db94011d3 150 case 19: channels_irq = &gpio1_irq3; break;
sahilmgandhi 18:6a4db94011d3 151 case 20: channels_irq = &gpio1_irq4; break;
sahilmgandhi 18:6a4db94011d3 152 case 21: channels_irq = &gpio1_irq5; break;
sahilmgandhi 18:6a4db94011d3 153 case 22: channels_irq = &gpio1_irq6; break;
sahilmgandhi 18:6a4db94011d3 154 case 23: channels_irq = &gpio1_irq7; break;
sahilmgandhi 18:6a4db94011d3 155 case 24: channels_irq = &gpio1_irq8; break;
sahilmgandhi 18:6a4db94011d3 156 case 25: channels_irq = &gpio1_irq9; break;
sahilmgandhi 18:6a4db94011d3 157 case 26: channels_irq = &gpio1_irq10; break;
sahilmgandhi 18:6a4db94011d3 158 case 27: channels_irq = &gpio1_irq11; break;
sahilmgandhi 18:6a4db94011d3 159 case 28: channels_irq = &gpio1_irq12; break;
sahilmgandhi 18:6a4db94011d3 160 case 29: channels_irq = &gpio1_irq13; break;
sahilmgandhi 18:6a4db94011d3 161 case 30: channels_irq = &gpio1_irq14; break;
sahilmgandhi 18:6a4db94011d3 162 case 31: channels_irq = &gpio1_irq15; break;
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165 NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
sahilmgandhi 18:6a4db94011d3 166 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 return 0;
sahilmgandhi 18:6a4db94011d3 169 }
sahilmgandhi 18:6a4db94011d3 170 }
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 void gpio_irq_free(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 173 }
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sahilmgandhi 18:6a4db94011d3 176 unsigned int ch_bit = (1 << obj->ch);
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 // Clear interrupt
sahilmgandhi 18:6a4db94011d3 179 if (obj->ch <16)
sahilmgandhi 18:6a4db94011d3 180 {
sahilmgandhi 18:6a4db94011d3 181 if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit))
sahilmgandhi 18:6a4db94011d3 182 {
sahilmgandhi 18:6a4db94011d3 183 CMSDK_GPIO_0->INTCLEAR = ch_bit;
sahilmgandhi 18:6a4db94011d3 184 }
sahilmgandhi 18:6a4db94011d3 185 }
sahilmgandhi 18:6a4db94011d3 186 if (obj->ch >= 16)
sahilmgandhi 18:6a4db94011d3 187 {
sahilmgandhi 18:6a4db94011d3 188 if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit))
sahilmgandhi 18:6a4db94011d3 189 {
sahilmgandhi 18:6a4db94011d3 190 CMSDK_GPIO_1->INTCLEAR = ch_bit;
sahilmgandhi 18:6a4db94011d3 191 }
sahilmgandhi 18:6a4db94011d3 192 }
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 // Edge trigger
sahilmgandhi 18:6a4db94011d3 195 if (obj->ch <16)
sahilmgandhi 18:6a4db94011d3 196 {
sahilmgandhi 18:6a4db94011d3 197 CMSDK_GPIO_0->INTTYPESET &= ch_bit;
sahilmgandhi 18:6a4db94011d3 198 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 199 CMSDK_GPIO_0->INTPOLSET |= ch_bit;
sahilmgandhi 18:6a4db94011d3 200 if (enable) {
sahilmgandhi 18:6a4db94011d3 201 CMSDK_GPIO_0->INTENSET |= ch_bit;
sahilmgandhi 18:6a4db94011d3 202 } else {
sahilmgandhi 18:6a4db94011d3 203 CMSDK_GPIO_0->INTENCLR |= ch_bit;
sahilmgandhi 18:6a4db94011d3 204 }
sahilmgandhi 18:6a4db94011d3 205 } else {
sahilmgandhi 18:6a4db94011d3 206 CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
sahilmgandhi 18:6a4db94011d3 207 if (enable) {
sahilmgandhi 18:6a4db94011d3 208 CMSDK_GPIO_0->INTENSET |= ch_bit;
sahilmgandhi 18:6a4db94011d3 209 } else {
sahilmgandhi 18:6a4db94011d3 210 CMSDK_GPIO_0->INTENCLR |= ch_bit;
sahilmgandhi 18:6a4db94011d3 211 }
sahilmgandhi 18:6a4db94011d3 212 }
sahilmgandhi 18:6a4db94011d3 213 }
sahilmgandhi 18:6a4db94011d3 214 if (obj->ch >= 16)
sahilmgandhi 18:6a4db94011d3 215 {
sahilmgandhi 18:6a4db94011d3 216 CMSDK_GPIO_1->INTTYPESET &= ch_bit;
sahilmgandhi 18:6a4db94011d3 217 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 218 CMSDK_GPIO_1->INTPOLSET |= ch_bit;
sahilmgandhi 18:6a4db94011d3 219 if (enable) {
sahilmgandhi 18:6a4db94011d3 220 CMSDK_GPIO_1->INTENSET |= ch_bit;
sahilmgandhi 18:6a4db94011d3 221 } else {
sahilmgandhi 18:6a4db94011d3 222 CMSDK_GPIO_1->INTENCLR |= ch_bit;
sahilmgandhi 18:6a4db94011d3 223 }
sahilmgandhi 18:6a4db94011d3 224 } else {
sahilmgandhi 18:6a4db94011d3 225 CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
sahilmgandhi 18:6a4db94011d3 226 if (enable) {
sahilmgandhi 18:6a4db94011d3 227 CMSDK_GPIO_1->INTENSET |= ch_bit;
sahilmgandhi 18:6a4db94011d3 228 } else {
sahilmgandhi 18:6a4db94011d3 229 CMSDK_GPIO_1->INTENCLR |= ch_bit;
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231 }
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233 }
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 void gpio_irq_enable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 236 NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 void gpio_irq_disable(gpio_irq_t *obj) {
sahilmgandhi 18:6a4db94011d3 240 NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
sahilmgandhi 18:6a4db94011d3 241 }