MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_ublox/TARGET_HI2110/pinmap.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2016 u-blox
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16
sahilmgandhi 18:6a4db94011d3 17 /* As well as claiming and setting pins, the functions here also need
sahilmgandhi 18:6a4db94011d3 18 * to take into account the way the pins are powered. On the Boudica
sahilmgandhi 18:6a4db94011d3 19 * chip they are arranged in three banks, PIO 0:5, PIO 6:10 and
sahilmgandhi 18:6a4db94011d3 20 * PIO 11:19.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * The arrangement for which PIO bank is powered is determined by the module
sahilmgandhi 18:6a4db94011d3 23 * in which the HI2110 chip is mounted, hence the use of conditional
sahilmgandhi 18:6a4db94011d3 24 * compilation below.
sahilmgandhi 18:6a4db94011d3 25 */
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 #include "stdbool.h"
sahilmgandhi 18:6a4db94011d3 28 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 29 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 30 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 /* ----------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 33 * MACROS
sahilmgandhi 18:6a4db94011d3 34 * ----------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 #define HAL_PIO_MASK_FUNC (0xFF)
sahilmgandhi 18:6a4db94011d3 37 #define HAL_PIO_MODULO_4_MASK (0x3)
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /* ----------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 40 * GLOBAL VARIABLES
sahilmgandhi 18:6a4db94011d3 41 * ----------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 /* ----------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 44 * FUNCTION PROTOTYPES
sahilmgandhi 18:6a4db94011d3 45 * ----------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 46
sahilmgandhi 18:6a4db94011d3 47 static inline uint32_t clr_mask (PinName pin);
sahilmgandhi 18:6a4db94011d3 48 static inline uint32_t set_mask (PinName pin, int function);
sahilmgandhi 18:6a4db94011d3 49 static inline volatile uint32_t * func_reg (PinName pin);
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /* ----------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 52 * NON-API FUNCTIONS
sahilmgandhi 18:6a4db94011d3 53 * ----------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 // Return the clear mask for a pin
sahilmgandhi 18:6a4db94011d3 56 static inline uint32_t clr_mask (PinName pin)
sahilmgandhi 18:6a4db94011d3 57 {
sahilmgandhi 18:6a4db94011d3 58 return HAL_PIO_MASK_FUNC << ((pin & HAL_PIO_MODULO_4_MASK) << 3);
sahilmgandhi 18:6a4db94011d3 59 }
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 // Return the set mask for a pin and a given function
sahilmgandhi 18:6a4db94011d3 62 static inline uint32_t set_mask (PinName pin, int function)
sahilmgandhi 18:6a4db94011d3 63 {
sahilmgandhi 18:6a4db94011d3 64 return function << ((pin & HAL_PIO_MODULO_4_MASK) << 3);
sahilmgandhi 18:6a4db94011d3 65 }
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 // Return the function register for a pin
sahilmgandhi 18:6a4db94011d3 68 static inline volatile uint32_t * func_reg (PinName pin)
sahilmgandhi 18:6a4db94011d3 69 {
sahilmgandhi 18:6a4db94011d3 70 return &PIO_FUNC0 + (pin >> 2);
sahilmgandhi 18:6a4db94011d3 71 }
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 // Return the owner of a pin
sahilmgandhi 18:6a4db94011d3 74 // 0: None
sahilmgandhi 18:6a4db94011d3 75 // 1: security core
sahilmgandhi 18:6a4db94011d3 76 // 2: protocol core
sahilmgandhi 18:6a4db94011d3 77 // 3: apps core
sahilmgandhi 18:6a4db94011d3 78 static inline uint8_t get_owner(PinName pin)
sahilmgandhi 18:6a4db94011d3 79 {
sahilmgandhi 18:6a4db94011d3 80 uint8_t pio_owner_shift = (pin & 0x0F) << 1;
sahilmgandhi 18:6a4db94011d3 81 volatile uint32_t * pio_owner_reg = (&PIO_OWNER0 + (pin >> 4));
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 return 0x03 & (*pio_owner_reg >> pio_owner_shift);
sahilmgandhi 18:6a4db94011d3 84 }
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 /* ----------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 87 * MBED "INTERNAL" API CALLS
sahilmgandhi 18:6a4db94011d3 88 * ----------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 void pin_function(PinName pin, int function)
sahilmgandhi 18:6a4db94011d3 91 {
sahilmgandhi 18:6a4db94011d3 92 volatile uint32_t *pio_func_reg;
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /* Set the function for the given pin */
sahilmgandhi 18:6a4db94011d3 95 pio_func_reg = func_reg (pin);
sahilmgandhi 18:6a4db94011d3 96 *pio_func_reg = (*pio_func_reg & ~(clr_mask(pin))) | set_mask(pin, function);
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /* Power the pin */
sahilmgandhi 18:6a4db94011d3 99 #ifdef TARGET_SARA_NBIOT
sahilmgandhi 18:6a4db94011d3 100 /* On Sara NBIoT, GPIO pin 19 has to be high to power GPIO pins 0 to 10 */
sahilmgandhi 18:6a4db94011d3 101 if ((pin >= p0) && (pin <= p10)) {
sahilmgandhi 18:6a4db94011d3 102 /* Grab pin 19 as a GPIO if we don't have it already */
sahilmgandhi 18:6a4db94011d3 103 if (get_owner(p19) != 0x03) {
sahilmgandhi 18:6a4db94011d3 104 pio_func_reg = func_reg (p19);
sahilmgandhi 18:6a4db94011d3 105 *pio_func_reg = (*pio_func_reg & ~(clr_mask(p19))) | set_mask(p19, 1); /* 1 == PIN_FUNCTION_GPIO */
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 MBED_ASSERT (get_owner(p19) == 0x03);
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /* Set pin 19 to be an output and to be high */
sahilmgandhi 18:6a4db94011d3 111 GPIO_DIR |= (1ul << p19);
sahilmgandhi 18:6a4db94011d3 112 GPIO_OUT_BITSET = (1ul << p19);
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /* Note: the level on pins 6 to 10 is controlled by the protocol
sahilmgandhi 18:6a4db94011d3 115 * processor to be the VCC level required by the SIM. The
sahilmgandhi 18:6a4db94011d3 116 * application has no control over this. */
sahilmgandhi 18:6a4db94011d3 117 }
sahilmgandhi 18:6a4db94011d3 118 /* The power to GPIOs 11 to 19 is fed directly from pin 51 of the module */
sahilmgandhi 18:6a4db94011d3 119 #endif
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 void pin_mode(PinName pin, PinMode mode)
sahilmgandhi 18:6a4db94011d3 123 {
sahilmgandhi 18:6a4db94011d3 124 MBED_ASSERT(pin != (PinName)NC);
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 switch (mode) {
sahilmgandhi 18:6a4db94011d3 127 case PullUp:
sahilmgandhi 18:6a4db94011d3 128 {
sahilmgandhi 18:6a4db94011d3 129 MBED_ASSERT(false); /* Not currently supported on HI2100 */
sahilmgandhi 18:6a4db94011d3 130 }
sahilmgandhi 18:6a4db94011d3 131 break;
sahilmgandhi 18:6a4db94011d3 132 case PullDown:
sahilmgandhi 18:6a4db94011d3 133 {
sahilmgandhi 18:6a4db94011d3 134 GPIO_PULLEN_BITSET = 1U << pin;
sahilmgandhi 18:6a4db94011d3 135 }
sahilmgandhi 18:6a4db94011d3 136 break;
sahilmgandhi 18:6a4db94011d3 137 case PullNone:
sahilmgandhi 18:6a4db94011d3 138 {
sahilmgandhi 18:6a4db94011d3 139 GPIO_PULLEN_BITCLR = 1U << pin;
sahilmgandhi 18:6a4db94011d3 140 }
sahilmgandhi 18:6a4db94011d3 141 break;
sahilmgandhi 18:6a4db94011d3 142 default:
sahilmgandhi 18:6a4db94011d3 143 break;
sahilmgandhi 18:6a4db94011d3 144 }
sahilmgandhi 18:6a4db94011d3 145 }