Mouse code for the MacroRat
mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @file efr32mg1p_usart.h |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @brief EFR32MG1P_USART register and bit field definitions |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @version 5.1.2 |
sahilmgandhi | 18:6a4db94011d3 | 5 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @section License |
sahilmgandhi | 18:6a4db94011d3 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
sahilmgandhi | 18:6a4db94011d3 | 8 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Permission is granted to anyone to use this software for any purpose, |
sahilmgandhi | 18:6a4db94011d3 | 11 | * including commercial applications, and to alter it and redistribute it |
sahilmgandhi | 18:6a4db94011d3 | 12 | * freely, subject to the following restrictions: |
sahilmgandhi | 18:6a4db94011d3 | 13 | * |
sahilmgandhi | 18:6a4db94011d3 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
sahilmgandhi | 18:6a4db94011d3 | 15 | * claim that you wrote the original software.@n |
sahilmgandhi | 18:6a4db94011d3 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
sahilmgandhi | 18:6a4db94011d3 | 17 | * misrepresented as being the original software.@n |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
sahilmgandhi | 18:6a4db94011d3 | 19 | * |
sahilmgandhi | 18:6a4db94011d3 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
sahilmgandhi | 18:6a4db94011d3 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
sahilmgandhi | 18:6a4db94011d3 | 23 | * kind, including, but not limited to, any implied warranties of |
sahilmgandhi | 18:6a4db94011d3 | 24 | * merchantability or fitness for any particular purpose or warranties against |
sahilmgandhi | 18:6a4db94011d3 | 25 | * infringement of any proprietary rights of a third party. |
sahilmgandhi | 18:6a4db94011d3 | 26 | * |
sahilmgandhi | 18:6a4db94011d3 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
sahilmgandhi | 18:6a4db94011d3 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
sahilmgandhi | 18:6a4db94011d3 | 29 | * any third party, arising from your use of this Software. |
sahilmgandhi | 18:6a4db94011d3 | 30 | * |
sahilmgandhi | 18:6a4db94011d3 | 31 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 32 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 33 | * @addtogroup Parts |
sahilmgandhi | 18:6a4db94011d3 | 34 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 35 | ******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 36 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 37 | * @defgroup EFR32MG1P_USART |
sahilmgandhi | 18:6a4db94011d3 | 38 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 39 | * @brief EFR32MG1P_USART Register Declaration |
sahilmgandhi | 18:6a4db94011d3 | 40 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 41 | typedef struct |
sahilmgandhi | 18:6a4db94011d3 | 42 | { |
sahilmgandhi | 18:6a4db94011d3 | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 44 | __IOM uint32_t FRAME; /**< USART Frame Format Register */ |
sahilmgandhi | 18:6a4db94011d3 | 45 | __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | __IOM uint32_t CMD; /**< Command Register */ |
sahilmgandhi | 18:6a4db94011d3 | 47 | __IM uint32_t STATUS; /**< USART Status Register */ |
sahilmgandhi | 18:6a4db94011d3 | 48 | __IOM uint32_t CLKDIV; /**< Clock Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 49 | __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ |
sahilmgandhi | 18:6a4db94011d3 | 50 | __IM uint32_t RXDATA; /**< RX Buffer Data Register */ |
sahilmgandhi | 18:6a4db94011d3 | 51 | __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ |
sahilmgandhi | 18:6a4db94011d3 | 52 | __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ |
sahilmgandhi | 18:6a4db94011d3 | 53 | __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ |
sahilmgandhi | 18:6a4db94011d3 | 54 | __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ |
sahilmgandhi | 18:6a4db94011d3 | 55 | __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ |
sahilmgandhi | 18:6a4db94011d3 | 56 | __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ |
sahilmgandhi | 18:6a4db94011d3 | 57 | __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ |
sahilmgandhi | 18:6a4db94011d3 | 58 | __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ |
sahilmgandhi | 18:6a4db94011d3 | 59 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
sahilmgandhi | 18:6a4db94011d3 | 62 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
sahilmgandhi | 18:6a4db94011d3 | 63 | __IOM uint32_t IRCTRL; /**< IrDA Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 64 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
sahilmgandhi | 18:6a4db94011d3 | 65 | __IOM uint32_t INPUT; /**< USART Input Register */ |
sahilmgandhi | 18:6a4db94011d3 | 66 | __IOM uint32_t I2SCTRL; /**< I2S Control Register */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | __IOM uint32_t TIMING; /**< Timing Register */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | __IOM uint32_t CTRLX; /**< Control Register Extended */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | __IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */ |
sahilmgandhi | 18:6a4db94011d3 | 70 | __IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | __IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */ |
sahilmgandhi | 18:6a4db94011d3 | 74 | __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | } USART_TypeDef; /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | |
sahilmgandhi | 18:6a4db94011d3 | 77 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 78 | * @defgroup EFR32MG1P_USART_BitFields |
sahilmgandhi | 18:6a4db94011d3 | 79 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 80 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 81 | |
sahilmgandhi | 18:6a4db94011d3 | 82 | /* Bit fields for USART CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | #define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 85 | #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 86 | #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 89 | #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 94 | #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 95 | #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 96 | #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ |
sahilmgandhi | 18:6a4db94011d3 | 97 | #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ |
sahilmgandhi | 18:6a4db94011d3 | 98 | #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ |
sahilmgandhi | 18:6a4db94011d3 | 102 | #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 104 | #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ |
sahilmgandhi | 18:6a4db94011d3 | 106 | #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ |
sahilmgandhi | 18:6a4db94011d3 | 107 | #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ |
sahilmgandhi | 18:6a4db94011d3 | 108 | #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 110 | #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ |
sahilmgandhi | 18:6a4db94011d3 | 111 | #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ |
sahilmgandhi | 18:6a4db94011d3 | 112 | #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 113 | #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 114 | #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 115 | #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 118 | #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 119 | #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 121 | #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 122 | #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ |
sahilmgandhi | 18:6a4db94011d3 | 123 | #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ |
sahilmgandhi | 18:6a4db94011d3 | 124 | #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ |
sahilmgandhi | 18:6a4db94011d3 | 125 | #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 126 | #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 127 | #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 128 | #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 129 | #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 130 | #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 131 | #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ |
sahilmgandhi | 18:6a4db94011d3 | 133 | #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ |
sahilmgandhi | 18:6a4db94011d3 | 134 | #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 135 | #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 136 | #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 137 | #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 138 | #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 139 | #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ |
sahilmgandhi | 18:6a4db94011d3 | 141 | #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ |
sahilmgandhi | 18:6a4db94011d3 | 142 | #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ |
sahilmgandhi | 18:6a4db94011d3 | 143 | #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 144 | #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 145 | #define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ |
sahilmgandhi | 18:6a4db94011d3 | 147 | #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 149 | #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 150 | #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 152 | #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 153 | #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 154 | #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ |
sahilmgandhi | 18:6a4db94011d3 | 155 | #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ |
sahilmgandhi | 18:6a4db94011d3 | 156 | #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ |
sahilmgandhi | 18:6a4db94011d3 | 157 | #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 158 | #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 160 | #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 161 | #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 162 | #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ |
sahilmgandhi | 18:6a4db94011d3 | 164 | #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ |
sahilmgandhi | 18:6a4db94011d3 | 165 | #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ |
sahilmgandhi | 18:6a4db94011d3 | 166 | #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 167 | #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 168 | #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ |
sahilmgandhi | 18:6a4db94011d3 | 170 | #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ |
sahilmgandhi | 18:6a4db94011d3 | 171 | #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 172 | #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 173 | #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ |
sahilmgandhi | 18:6a4db94011d3 | 175 | #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ |
sahilmgandhi | 18:6a4db94011d3 | 176 | #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 177 | #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ |
sahilmgandhi | 18:6a4db94011d3 | 179 | #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ |
sahilmgandhi | 18:6a4db94011d3 | 180 | #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ |
sahilmgandhi | 18:6a4db94011d3 | 181 | #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 182 | #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 183 | #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ |
sahilmgandhi | 18:6a4db94011d3 | 185 | #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ |
sahilmgandhi | 18:6a4db94011d3 | 186 | #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 187 | #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 188 | #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ |
sahilmgandhi | 18:6a4db94011d3 | 190 | #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ |
sahilmgandhi | 18:6a4db94011d3 | 191 | #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 193 | #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ |
sahilmgandhi | 18:6a4db94011d3 | 194 | #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ |
sahilmgandhi | 18:6a4db94011d3 | 195 | #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ |
sahilmgandhi | 18:6a4db94011d3 | 196 | #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 197 | #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 198 | #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ |
sahilmgandhi | 18:6a4db94011d3 | 199 | #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ |
sahilmgandhi | 18:6a4db94011d3 | 200 | #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ |
sahilmgandhi | 18:6a4db94011d3 | 201 | #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 202 | #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 203 | #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ |
sahilmgandhi | 18:6a4db94011d3 | 205 | #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ |
sahilmgandhi | 18:6a4db94011d3 | 206 | #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 208 | #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ |
sahilmgandhi | 18:6a4db94011d3 | 209 | #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ |
sahilmgandhi | 18:6a4db94011d3 | 210 | #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ |
sahilmgandhi | 18:6a4db94011d3 | 211 | #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 212 | #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 213 | #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ |
sahilmgandhi | 18:6a4db94011d3 | 214 | #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ |
sahilmgandhi | 18:6a4db94011d3 | 215 | #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ |
sahilmgandhi | 18:6a4db94011d3 | 216 | #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 217 | #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 218 | #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ |
sahilmgandhi | 18:6a4db94011d3 | 219 | #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ |
sahilmgandhi | 18:6a4db94011d3 | 221 | #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 222 | #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 223 | #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ |
sahilmgandhi | 18:6a4db94011d3 | 224 | #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ |
sahilmgandhi | 18:6a4db94011d3 | 225 | #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ |
sahilmgandhi | 18:6a4db94011d3 | 226 | #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 227 | #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 228 | #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ |
sahilmgandhi | 18:6a4db94011d3 | 229 | #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ |
sahilmgandhi | 18:6a4db94011d3 | 230 | #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ |
sahilmgandhi | 18:6a4db94011d3 | 231 | #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 232 | #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 233 | #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ |
sahilmgandhi | 18:6a4db94011d3 | 234 | #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ |
sahilmgandhi | 18:6a4db94011d3 | 235 | #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ |
sahilmgandhi | 18:6a4db94011d3 | 236 | #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 237 | #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 238 | #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ |
sahilmgandhi | 18:6a4db94011d3 | 239 | #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 240 | #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 241 | #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 242 | #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 243 | #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ |
sahilmgandhi | 18:6a4db94011d3 | 244 | #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ |
sahilmgandhi | 18:6a4db94011d3 | 245 | #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ |
sahilmgandhi | 18:6a4db94011d3 | 246 | #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 247 | #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 248 | |
sahilmgandhi | 18:6a4db94011d3 | 249 | /* Bit fields for USART FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 250 | #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 251 | #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 252 | #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ |
sahilmgandhi | 18:6a4db94011d3 | 253 | #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ |
sahilmgandhi | 18:6a4db94011d3 | 254 | #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 255 | #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 256 | #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 257 | #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 258 | #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 259 | #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 261 | #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 262 | #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 263 | #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 264 | #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 265 | #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 266 | #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 267 | #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 268 | #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 269 | #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 270 | #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 271 | #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 272 | #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 273 | #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 274 | #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 275 | #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 276 | #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 277 | #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 278 | #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 279 | #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 280 | #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 281 | #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 282 | #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ |
sahilmgandhi | 18:6a4db94011d3 | 283 | #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ |
sahilmgandhi | 18:6a4db94011d3 | 284 | #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 285 | #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 286 | #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 287 | #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 288 | #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 289 | #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 290 | #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 291 | #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 292 | #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ |
sahilmgandhi | 18:6a4db94011d3 | 293 | #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ |
sahilmgandhi | 18:6a4db94011d3 | 294 | #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 295 | #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 296 | #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 297 | #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 298 | #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 299 | #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 300 | #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 301 | #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 302 | #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 303 | #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ |
sahilmgandhi | 18:6a4db94011d3 | 304 | |
sahilmgandhi | 18:6a4db94011d3 | 305 | /* Bit fields for USART TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 306 | #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 307 | #define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 308 | #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 309 | #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 310 | #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 311 | #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 312 | #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 313 | #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 314 | #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 315 | #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 316 | #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 317 | #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 318 | #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 319 | #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 320 | #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 321 | #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 322 | #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | #define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */ |
sahilmgandhi | 18:6a4db94011d3 | 324 | #define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ |
sahilmgandhi | 18:6a4db94011d3 | 325 | #define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ |
sahilmgandhi | 18:6a4db94011d3 | 326 | #define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 327 | #define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 328 | #define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */ |
sahilmgandhi | 18:6a4db94011d3 | 329 | #define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ |
sahilmgandhi | 18:6a4db94011d3 | 330 | #define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ |
sahilmgandhi | 18:6a4db94011d3 | 331 | #define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 332 | #define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 333 | #define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */ |
sahilmgandhi | 18:6a4db94011d3 | 334 | #define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ |
sahilmgandhi | 18:6a4db94011d3 | 335 | #define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ |
sahilmgandhi | 18:6a4db94011d3 | 336 | #define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 337 | #define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 338 | #define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */ |
sahilmgandhi | 18:6a4db94011d3 | 339 | #define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ |
sahilmgandhi | 18:6a4db94011d3 | 340 | #define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ |
sahilmgandhi | 18:6a4db94011d3 | 341 | #define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 342 | #define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 343 | #define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */ |
sahilmgandhi | 18:6a4db94011d3 | 344 | #define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ |
sahilmgandhi | 18:6a4db94011d3 | 345 | #define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ |
sahilmgandhi | 18:6a4db94011d3 | 346 | #define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 347 | #define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 348 | #define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */ |
sahilmgandhi | 18:6a4db94011d3 | 349 | #define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ |
sahilmgandhi | 18:6a4db94011d3 | 350 | #define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ |
sahilmgandhi | 18:6a4db94011d3 | 351 | #define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 352 | #define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 353 | #define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */ |
sahilmgandhi | 18:6a4db94011d3 | 354 | #define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */ |
sahilmgandhi | 18:6a4db94011d3 | 355 | #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 356 | #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 357 | #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 358 | #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 359 | #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 360 | #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 361 | #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 362 | #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 363 | #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 364 | #define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 365 | #define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 366 | #define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 367 | #define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 368 | #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 369 | #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 370 | #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 371 | #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 372 | #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 373 | #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 374 | #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 375 | #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 376 | #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 377 | #define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 378 | #define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 379 | #define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 380 | #define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 381 | |
sahilmgandhi | 18:6a4db94011d3 | 382 | /* Bit fields for USART CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 383 | #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 384 | #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 385 | #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 386 | #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ |
sahilmgandhi | 18:6a4db94011d3 | 387 | #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ |
sahilmgandhi | 18:6a4db94011d3 | 388 | #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 389 | #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 390 | #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ |
sahilmgandhi | 18:6a4db94011d3 | 391 | #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 392 | #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 393 | #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 394 | #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 395 | #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 396 | #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ |
sahilmgandhi | 18:6a4db94011d3 | 397 | #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ |
sahilmgandhi | 18:6a4db94011d3 | 398 | #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 399 | #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 400 | #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ |
sahilmgandhi | 18:6a4db94011d3 | 401 | #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 402 | #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 403 | #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 404 | #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 405 | #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 406 | #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ |
sahilmgandhi | 18:6a4db94011d3 | 407 | #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ |
sahilmgandhi | 18:6a4db94011d3 | 408 | #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 409 | #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 410 | #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ |
sahilmgandhi | 18:6a4db94011d3 | 411 | #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 412 | #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 413 | #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 414 | #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 415 | #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 416 | #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ |
sahilmgandhi | 18:6a4db94011d3 | 417 | #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ |
sahilmgandhi | 18:6a4db94011d3 | 418 | #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 419 | #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 420 | #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ |
sahilmgandhi | 18:6a4db94011d3 | 421 | #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 422 | #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 423 | #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 424 | #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 425 | #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 426 | #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ |
sahilmgandhi | 18:6a4db94011d3 | 427 | #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ |
sahilmgandhi | 18:6a4db94011d3 | 428 | #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 429 | #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 430 | #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ |
sahilmgandhi | 18:6a4db94011d3 | 431 | #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 432 | #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ |
sahilmgandhi | 18:6a4db94011d3 | 433 | #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 434 | #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 435 | #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ |
sahilmgandhi | 18:6a4db94011d3 | 436 | #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ |
sahilmgandhi | 18:6a4db94011d3 | 437 | #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ |
sahilmgandhi | 18:6a4db94011d3 | 438 | #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 439 | #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 440 | #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ |
sahilmgandhi | 18:6a4db94011d3 | 441 | #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ |
sahilmgandhi | 18:6a4db94011d3 | 442 | #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ |
sahilmgandhi | 18:6a4db94011d3 | 443 | #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 444 | #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ |
sahilmgandhi | 18:6a4db94011d3 | 445 | |
sahilmgandhi | 18:6a4db94011d3 | 446 | /* Bit fields for USART STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 447 | #define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 448 | #define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 449 | #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ |
sahilmgandhi | 18:6a4db94011d3 | 450 | #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ |
sahilmgandhi | 18:6a4db94011d3 | 451 | #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ |
sahilmgandhi | 18:6a4db94011d3 | 452 | #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 453 | #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 454 | #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ |
sahilmgandhi | 18:6a4db94011d3 | 455 | #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ |
sahilmgandhi | 18:6a4db94011d3 | 456 | #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ |
sahilmgandhi | 18:6a4db94011d3 | 457 | #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 458 | #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 459 | #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 460 | #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ |
sahilmgandhi | 18:6a4db94011d3 | 461 | #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ |
sahilmgandhi | 18:6a4db94011d3 | 462 | #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 463 | #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 464 | #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ |
sahilmgandhi | 18:6a4db94011d3 | 465 | #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ |
sahilmgandhi | 18:6a4db94011d3 | 466 | #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ |
sahilmgandhi | 18:6a4db94011d3 | 467 | #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 468 | #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 469 | #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ |
sahilmgandhi | 18:6a4db94011d3 | 470 | #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ |
sahilmgandhi | 18:6a4db94011d3 | 471 | #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ |
sahilmgandhi | 18:6a4db94011d3 | 472 | #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 473 | #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 474 | #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ |
sahilmgandhi | 18:6a4db94011d3 | 475 | #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 476 | #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 477 | #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 478 | #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 479 | #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ |
sahilmgandhi | 18:6a4db94011d3 | 480 | #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ |
sahilmgandhi | 18:6a4db94011d3 | 481 | #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ |
sahilmgandhi | 18:6a4db94011d3 | 482 | #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 483 | #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 484 | #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ |
sahilmgandhi | 18:6a4db94011d3 | 485 | #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ |
sahilmgandhi | 18:6a4db94011d3 | 486 | #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ |
sahilmgandhi | 18:6a4db94011d3 | 487 | #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 488 | #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 489 | #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ |
sahilmgandhi | 18:6a4db94011d3 | 490 | #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 491 | #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 492 | #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 493 | #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 494 | #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ |
sahilmgandhi | 18:6a4db94011d3 | 495 | #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ |
sahilmgandhi | 18:6a4db94011d3 | 496 | #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ |
sahilmgandhi | 18:6a4db94011d3 | 497 | #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 498 | #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 499 | #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ |
sahilmgandhi | 18:6a4db94011d3 | 500 | #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ |
sahilmgandhi | 18:6a4db94011d3 | 501 | #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ |
sahilmgandhi | 18:6a4db94011d3 | 502 | #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 503 | #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 504 | #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ |
sahilmgandhi | 18:6a4db94011d3 | 505 | #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ |
sahilmgandhi | 18:6a4db94011d3 | 506 | #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ |
sahilmgandhi | 18:6a4db94011d3 | 507 | #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 508 | #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 509 | #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ |
sahilmgandhi | 18:6a4db94011d3 | 510 | #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ |
sahilmgandhi | 18:6a4db94011d3 | 511 | #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ |
sahilmgandhi | 18:6a4db94011d3 | 512 | #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 513 | #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 514 | #define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ |
sahilmgandhi | 18:6a4db94011d3 | 515 | #define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 516 | #define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 517 | #define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 518 | #define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 519 | #define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ |
sahilmgandhi | 18:6a4db94011d3 | 520 | #define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ |
sahilmgandhi | 18:6a4db94011d3 | 521 | #define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ |
sahilmgandhi | 18:6a4db94011d3 | 522 | #define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 523 | #define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 524 | #define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ |
sahilmgandhi | 18:6a4db94011d3 | 525 | #define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ |
sahilmgandhi | 18:6a4db94011d3 | 526 | #define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 527 | #define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ |
sahilmgandhi | 18:6a4db94011d3 | 528 | |
sahilmgandhi | 18:6a4db94011d3 | 529 | /* Bit fields for USART CLKDIV */ |
sahilmgandhi | 18:6a4db94011d3 | 530 | #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ |
sahilmgandhi | 18:6a4db94011d3 | 531 | #define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ |
sahilmgandhi | 18:6a4db94011d3 | 532 | #define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ |
sahilmgandhi | 18:6a4db94011d3 | 533 | #define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ |
sahilmgandhi | 18:6a4db94011d3 | 534 | #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ |
sahilmgandhi | 18:6a4db94011d3 | 535 | #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ |
sahilmgandhi | 18:6a4db94011d3 | 536 | #define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ |
sahilmgandhi | 18:6a4db94011d3 | 537 | #define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ |
sahilmgandhi | 18:6a4db94011d3 | 538 | #define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ |
sahilmgandhi | 18:6a4db94011d3 | 539 | #define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ |
sahilmgandhi | 18:6a4db94011d3 | 540 | #define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ |
sahilmgandhi | 18:6a4db94011d3 | 541 | |
sahilmgandhi | 18:6a4db94011d3 | 542 | /* Bit fields for USART RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 543 | #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 544 | #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 545 | #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 546 | #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 547 | #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 548 | #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 549 | #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ |
sahilmgandhi | 18:6a4db94011d3 | 550 | #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 551 | #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 552 | #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 553 | #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 554 | #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ |
sahilmgandhi | 18:6a4db94011d3 | 555 | #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 556 | #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 557 | #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 558 | #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 559 | |
sahilmgandhi | 18:6a4db94011d3 | 560 | /* Bit fields for USART RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 561 | #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 562 | #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 563 | #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 564 | #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 565 | #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 566 | #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 567 | |
sahilmgandhi | 18:6a4db94011d3 | 568 | /* Bit fields for USART RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 569 | #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 570 | #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 571 | #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ |
sahilmgandhi | 18:6a4db94011d3 | 572 | #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ |
sahilmgandhi | 18:6a4db94011d3 | 573 | #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 574 | #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 575 | #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 576 | #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ |
sahilmgandhi | 18:6a4db94011d3 | 577 | #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ |
sahilmgandhi | 18:6a4db94011d3 | 578 | #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 579 | #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 580 | #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 581 | #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ |
sahilmgandhi | 18:6a4db94011d3 | 582 | #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ |
sahilmgandhi | 18:6a4db94011d3 | 583 | #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 584 | #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 585 | #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ |
sahilmgandhi | 18:6a4db94011d3 | 586 | #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ |
sahilmgandhi | 18:6a4db94011d3 | 587 | #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 588 | #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 589 | #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 590 | #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ |
sahilmgandhi | 18:6a4db94011d3 | 591 | #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ |
sahilmgandhi | 18:6a4db94011d3 | 592 | #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 593 | #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 594 | #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 595 | #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ |
sahilmgandhi | 18:6a4db94011d3 | 596 | #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ |
sahilmgandhi | 18:6a4db94011d3 | 597 | #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 598 | #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 599 | |
sahilmgandhi | 18:6a4db94011d3 | 600 | /* Bit fields for USART RXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 601 | #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 602 | #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 603 | #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ |
sahilmgandhi | 18:6a4db94011d3 | 604 | #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ |
sahilmgandhi | 18:6a4db94011d3 | 605 | #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 606 | #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 607 | #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ |
sahilmgandhi | 18:6a4db94011d3 | 608 | #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ |
sahilmgandhi | 18:6a4db94011d3 | 609 | #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 610 | #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 611 | |
sahilmgandhi | 18:6a4db94011d3 | 612 | /* Bit fields for USART RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 613 | #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 614 | #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 615 | #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ |
sahilmgandhi | 18:6a4db94011d3 | 616 | #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ |
sahilmgandhi | 18:6a4db94011d3 | 617 | #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 618 | #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 619 | #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ |
sahilmgandhi | 18:6a4db94011d3 | 620 | #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ |
sahilmgandhi | 18:6a4db94011d3 | 621 | #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ |
sahilmgandhi | 18:6a4db94011d3 | 622 | #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 623 | #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 624 | #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ |
sahilmgandhi | 18:6a4db94011d3 | 625 | #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ |
sahilmgandhi | 18:6a4db94011d3 | 626 | #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ |
sahilmgandhi | 18:6a4db94011d3 | 627 | #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 628 | #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ |
sahilmgandhi | 18:6a4db94011d3 | 629 | |
sahilmgandhi | 18:6a4db94011d3 | 630 | /* Bit fields for USART RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 631 | #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 632 | #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 633 | #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 634 | #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 635 | #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 636 | #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 637 | #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ |
sahilmgandhi | 18:6a4db94011d3 | 638 | #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 639 | #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 640 | #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 641 | #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 642 | #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ |
sahilmgandhi | 18:6a4db94011d3 | 643 | #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 644 | #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 645 | #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 646 | #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 647 | #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 648 | #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 649 | #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 650 | #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 651 | #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ |
sahilmgandhi | 18:6a4db94011d3 | 652 | #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 653 | #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 654 | #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 655 | #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 656 | #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ |
sahilmgandhi | 18:6a4db94011d3 | 657 | #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 658 | #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 659 | #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 660 | #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
sahilmgandhi | 18:6a4db94011d3 | 661 | |
sahilmgandhi | 18:6a4db94011d3 | 662 | /* Bit fields for USART TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 663 | #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 664 | #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 665 | #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 666 | #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 667 | #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 668 | #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 669 | #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 670 | #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ |
sahilmgandhi | 18:6a4db94011d3 | 671 | #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ |
sahilmgandhi | 18:6a4db94011d3 | 672 | #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 673 | #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 674 | #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 675 | #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ |
sahilmgandhi | 18:6a4db94011d3 | 676 | #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ |
sahilmgandhi | 18:6a4db94011d3 | 677 | #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 678 | #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 679 | #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ |
sahilmgandhi | 18:6a4db94011d3 | 680 | #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ |
sahilmgandhi | 18:6a4db94011d3 | 681 | #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ |
sahilmgandhi | 18:6a4db94011d3 | 682 | #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 683 | #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 684 | #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 685 | #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ |
sahilmgandhi | 18:6a4db94011d3 | 686 | #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ |
sahilmgandhi | 18:6a4db94011d3 | 687 | #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 688 | #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 689 | #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 690 | #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ |
sahilmgandhi | 18:6a4db94011d3 | 691 | #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ |
sahilmgandhi | 18:6a4db94011d3 | 692 | #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 693 | #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
sahilmgandhi | 18:6a4db94011d3 | 694 | |
sahilmgandhi | 18:6a4db94011d3 | 695 | /* Bit fields for USART TXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 696 | #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 697 | #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 698 | #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 699 | #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 700 | #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 701 | #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ |
sahilmgandhi | 18:6a4db94011d3 | 702 | |
sahilmgandhi | 18:6a4db94011d3 | 703 | /* Bit fields for USART TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 704 | #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 705 | #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 706 | #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ |
sahilmgandhi | 18:6a4db94011d3 | 707 | #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ |
sahilmgandhi | 18:6a4db94011d3 | 708 | #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 709 | #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 710 | #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 711 | #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 712 | #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 713 | #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 714 | #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 715 | #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 716 | #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 717 | #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 718 | #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 719 | #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 720 | #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ |
sahilmgandhi | 18:6a4db94011d3 | 721 | #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 722 | #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 723 | #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 724 | #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 725 | #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 726 | #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 727 | #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 728 | #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 729 | #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 730 | #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 731 | #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 732 | #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ |
sahilmgandhi | 18:6a4db94011d3 | 733 | #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 734 | #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 735 | #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ |
sahilmgandhi | 18:6a4db94011d3 | 736 | #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ |
sahilmgandhi | 18:6a4db94011d3 | 737 | #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 738 | #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 739 | #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 740 | #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 741 | #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 742 | #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 743 | #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 744 | #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 745 | #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 746 | #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 747 | #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 748 | #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 749 | #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ |
sahilmgandhi | 18:6a4db94011d3 | 750 | #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ |
sahilmgandhi | 18:6a4db94011d3 | 751 | #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ |
sahilmgandhi | 18:6a4db94011d3 | 752 | #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 753 | #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 754 | #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 755 | #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 756 | #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 757 | #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 758 | #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 759 | #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ |
sahilmgandhi | 18:6a4db94011d3 | 760 | #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 761 | #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ |
sahilmgandhi | 18:6a4db94011d3 | 762 | #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 763 | #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
sahilmgandhi | 18:6a4db94011d3 | 764 | |
sahilmgandhi | 18:6a4db94011d3 | 765 | /* Bit fields for USART TXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 766 | #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 767 | #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 768 | #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ |
sahilmgandhi | 18:6a4db94011d3 | 769 | #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ |
sahilmgandhi | 18:6a4db94011d3 | 770 | #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 771 | #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 772 | #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ |
sahilmgandhi | 18:6a4db94011d3 | 773 | #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ |
sahilmgandhi | 18:6a4db94011d3 | 774 | #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 775 | #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ |
sahilmgandhi | 18:6a4db94011d3 | 776 | |
sahilmgandhi | 18:6a4db94011d3 | 777 | /* Bit fields for USART IF */ |
sahilmgandhi | 18:6a4db94011d3 | 778 | #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 779 | #define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 780 | #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 781 | #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 782 | #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 783 | #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 784 | #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 785 | #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 786 | #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ |
sahilmgandhi | 18:6a4db94011d3 | 787 | #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ |
sahilmgandhi | 18:6a4db94011d3 | 788 | #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 789 | #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 790 | #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 791 | #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ |
sahilmgandhi | 18:6a4db94011d3 | 792 | #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ |
sahilmgandhi | 18:6a4db94011d3 | 793 | #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 794 | #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 795 | #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 796 | #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 797 | #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 798 | #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 799 | #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 800 | #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 801 | #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 802 | #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 803 | #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 804 | #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 805 | #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 806 | #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 807 | #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 808 | #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 809 | #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 810 | #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 811 | #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 812 | #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 813 | #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 814 | #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 815 | #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 816 | #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 817 | #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 818 | #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 819 | #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 820 | #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 821 | #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 822 | #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 823 | #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 824 | #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 825 | #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 826 | #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 827 | #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 828 | #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 829 | #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 830 | #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 831 | #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ |
sahilmgandhi | 18:6a4db94011d3 | 832 | #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ |
sahilmgandhi | 18:6a4db94011d3 | 833 | #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 834 | #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 835 | #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 836 | #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ |
sahilmgandhi | 18:6a4db94011d3 | 837 | #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ |
sahilmgandhi | 18:6a4db94011d3 | 838 | #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 839 | #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 840 | #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 841 | #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ |
sahilmgandhi | 18:6a4db94011d3 | 842 | #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ |
sahilmgandhi | 18:6a4db94011d3 | 843 | #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 844 | #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 845 | #define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 846 | #define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 847 | #define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 848 | #define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 849 | #define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 850 | #define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 851 | #define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 852 | #define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 853 | #define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 854 | #define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 855 | #define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 856 | #define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 857 | #define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 858 | #define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 859 | #define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 860 | #define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 861 | #define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 862 | #define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 863 | #define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 864 | #define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ |
sahilmgandhi | 18:6a4db94011d3 | 865 | |
sahilmgandhi | 18:6a4db94011d3 | 866 | /* Bit fields for USART IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 867 | #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 868 | #define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 869 | #define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 870 | #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 871 | #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 872 | #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 873 | #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 874 | #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 875 | #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 876 | #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 877 | #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 878 | #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 879 | #define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 880 | #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 881 | #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 882 | #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 883 | #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 884 | #define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 885 | #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 886 | #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 887 | #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 888 | #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 889 | #define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 890 | #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 891 | #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 892 | #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 893 | #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 894 | #define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 895 | #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 896 | #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 897 | #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 898 | #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 899 | #define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 900 | #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 901 | #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 902 | #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 903 | #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 904 | #define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 905 | #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 906 | #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 907 | #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 908 | #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 909 | #define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 910 | #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ |
sahilmgandhi | 18:6a4db94011d3 | 911 | #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ |
sahilmgandhi | 18:6a4db94011d3 | 912 | #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 913 | #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 914 | #define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 915 | #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ |
sahilmgandhi | 18:6a4db94011d3 | 916 | #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ |
sahilmgandhi | 18:6a4db94011d3 | 917 | #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 918 | #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 919 | #define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 920 | #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ |
sahilmgandhi | 18:6a4db94011d3 | 921 | #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ |
sahilmgandhi | 18:6a4db94011d3 | 922 | #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 923 | #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 924 | #define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 925 | #define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 926 | #define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 927 | #define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 928 | #define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 929 | #define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 930 | #define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 931 | #define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 932 | #define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 933 | #define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 934 | #define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 935 | #define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 936 | #define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 937 | #define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 938 | #define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 939 | #define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 940 | #define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 941 | #define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 942 | #define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 943 | #define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */ |
sahilmgandhi | 18:6a4db94011d3 | 944 | |
sahilmgandhi | 18:6a4db94011d3 | 945 | /* Bit fields for USART IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 946 | #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 947 | #define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 948 | #define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 949 | #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 950 | #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 951 | #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 952 | #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 953 | #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 954 | #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 955 | #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 956 | #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 957 | #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 958 | #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 959 | #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 960 | #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 961 | #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 962 | #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 963 | #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 964 | #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 965 | #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 966 | #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 967 | #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 968 | #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 969 | #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 970 | #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 971 | #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 972 | #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 973 | #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 974 | #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 975 | #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 976 | #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 977 | #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 978 | #define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 979 | #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 980 | #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 981 | #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 982 | #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 983 | #define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 984 | #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 985 | #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 986 | #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 987 | #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 988 | #define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 989 | #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ |
sahilmgandhi | 18:6a4db94011d3 | 990 | #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ |
sahilmgandhi | 18:6a4db94011d3 | 991 | #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 992 | #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 993 | #define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 994 | #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ |
sahilmgandhi | 18:6a4db94011d3 | 995 | #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ |
sahilmgandhi | 18:6a4db94011d3 | 996 | #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 997 | #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 998 | #define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 999 | #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ |
sahilmgandhi | 18:6a4db94011d3 | 1000 | #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ |
sahilmgandhi | 18:6a4db94011d3 | 1001 | #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1002 | #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1003 | #define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1004 | #define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 1005 | #define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 1006 | #define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1007 | #define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1008 | #define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1009 | #define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1010 | #define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1011 | #define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1012 | #define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1013 | #define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1014 | #define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1015 | #define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1016 | #define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1017 | #define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1018 | #define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1019 | #define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1020 | #define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1021 | #define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1022 | #define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */ |
sahilmgandhi | 18:6a4db94011d3 | 1023 | |
sahilmgandhi | 18:6a4db94011d3 | 1024 | /* Bit fields for USART IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1025 | #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1026 | #define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1027 | #define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1028 | #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 1029 | #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ |
sahilmgandhi | 18:6a4db94011d3 | 1030 | #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1031 | #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1032 | #define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1033 | #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ |
sahilmgandhi | 18:6a4db94011d3 | 1034 | #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ |
sahilmgandhi | 18:6a4db94011d3 | 1035 | #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1036 | #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1037 | #define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1038 | #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ |
sahilmgandhi | 18:6a4db94011d3 | 1039 | #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ |
sahilmgandhi | 18:6a4db94011d3 | 1040 | #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1041 | #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1042 | #define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1043 | #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 1044 | #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ |
sahilmgandhi | 18:6a4db94011d3 | 1045 | #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1046 | #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1047 | #define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1048 | #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 1049 | #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 1050 | #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1051 | #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1052 | #define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1053 | #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 1054 | #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 1055 | #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1056 | #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1057 | #define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1058 | #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 1059 | #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ |
sahilmgandhi | 18:6a4db94011d3 | 1060 | #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1061 | #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1062 | #define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1063 | #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 1064 | #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ |
sahilmgandhi | 18:6a4db94011d3 | 1065 | #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1066 | #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1067 | #define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1068 | #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 1069 | #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ |
sahilmgandhi | 18:6a4db94011d3 | 1070 | #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1071 | #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1072 | #define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1073 | #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 1074 | #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ |
sahilmgandhi | 18:6a4db94011d3 | 1075 | #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1076 | #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1077 | #define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1078 | #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ |
sahilmgandhi | 18:6a4db94011d3 | 1079 | #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ |
sahilmgandhi | 18:6a4db94011d3 | 1080 | #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1081 | #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1082 | #define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1083 | #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ |
sahilmgandhi | 18:6a4db94011d3 | 1084 | #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ |
sahilmgandhi | 18:6a4db94011d3 | 1085 | #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1086 | #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1087 | #define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1088 | #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ |
sahilmgandhi | 18:6a4db94011d3 | 1089 | #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ |
sahilmgandhi | 18:6a4db94011d3 | 1090 | #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1091 | #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1092 | #define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1093 | #define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 1094 | #define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ |
sahilmgandhi | 18:6a4db94011d3 | 1095 | #define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1096 | #define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1097 | #define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1098 | #define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1099 | #define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1100 | #define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1101 | #define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1102 | #define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1103 | #define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1104 | #define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1105 | #define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1106 | #define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1107 | #define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1108 | #define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1109 | #define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1110 | #define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1111 | #define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1112 | |
sahilmgandhi | 18:6a4db94011d3 | 1113 | /* Bit fields for USART IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1114 | #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1115 | #define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1116 | #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ |
sahilmgandhi | 18:6a4db94011d3 | 1117 | #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ |
sahilmgandhi | 18:6a4db94011d3 | 1118 | #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ |
sahilmgandhi | 18:6a4db94011d3 | 1119 | #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1120 | #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1121 | #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ |
sahilmgandhi | 18:6a4db94011d3 | 1122 | #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ |
sahilmgandhi | 18:6a4db94011d3 | 1123 | #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1124 | #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1125 | #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1126 | #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1127 | #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1128 | #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1129 | #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1130 | #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1131 | #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1132 | #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1133 | #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ |
sahilmgandhi | 18:6a4db94011d3 | 1134 | #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ |
sahilmgandhi | 18:6a4db94011d3 | 1135 | #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ |
sahilmgandhi | 18:6a4db94011d3 | 1136 | #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1137 | #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1138 | #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1139 | #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1140 | #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1141 | #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1142 | #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1143 | #define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */ |
sahilmgandhi | 18:6a4db94011d3 | 1144 | #define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */ |
sahilmgandhi | 18:6a4db94011d3 | 1145 | #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1146 | #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1147 | #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1148 | #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1149 | #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1150 | #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1151 | #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1152 | #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1153 | #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1154 | #define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1155 | #define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1156 | #define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1157 | #define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1158 | #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1159 | #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1160 | #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1161 | #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1162 | #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1163 | #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1164 | #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1165 | #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1166 | #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1167 | #define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1168 | #define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1169 | #define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1170 | #define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1171 | |
sahilmgandhi | 18:6a4db94011d3 | 1172 | /* Bit fields for USART INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1173 | #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1174 | #define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1175 | #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ |
sahilmgandhi | 18:6a4db94011d3 | 1176 | #define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */ |
sahilmgandhi | 18:6a4db94011d3 | 1177 | #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1178 | #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1179 | #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1180 | #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1181 | #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1182 | #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1183 | #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1184 | #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1185 | #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1186 | #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1187 | #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1188 | #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1189 | #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1190 | #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1191 | #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1192 | #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1193 | #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1194 | #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1195 | #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1196 | #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1197 | #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1198 | #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1199 | #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1200 | #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1201 | #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1202 | #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1203 | #define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1204 | #define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */ |
sahilmgandhi | 18:6a4db94011d3 | 1205 | #define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */ |
sahilmgandhi | 18:6a4db94011d3 | 1206 | #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1207 | #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1208 | #define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */ |
sahilmgandhi | 18:6a4db94011d3 | 1209 | #define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */ |
sahilmgandhi | 18:6a4db94011d3 | 1210 | #define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1211 | #define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1212 | #define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1213 | #define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1214 | #define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1215 | #define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1216 | #define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1217 | #define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1218 | #define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1219 | #define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1220 | #define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1221 | #define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1222 | #define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1223 | #define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1224 | #define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1225 | #define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1226 | #define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1227 | #define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1228 | #define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1229 | #define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1230 | #define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1231 | #define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1232 | #define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1233 | #define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1234 | #define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1235 | #define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1236 | #define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1237 | #define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */ |
sahilmgandhi | 18:6a4db94011d3 | 1238 | #define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */ |
sahilmgandhi | 18:6a4db94011d3 | 1239 | #define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1240 | #define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */ |
sahilmgandhi | 18:6a4db94011d3 | 1241 | |
sahilmgandhi | 18:6a4db94011d3 | 1242 | /* Bit fields for USART I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1243 | #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1244 | #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1245 | #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ |
sahilmgandhi | 18:6a4db94011d3 | 1246 | #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ |
sahilmgandhi | 18:6a4db94011d3 | 1247 | #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ |
sahilmgandhi | 18:6a4db94011d3 | 1248 | #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1249 | #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1250 | #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ |
sahilmgandhi | 18:6a4db94011d3 | 1251 | #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ |
sahilmgandhi | 18:6a4db94011d3 | 1252 | #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ |
sahilmgandhi | 18:6a4db94011d3 | 1253 | #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1254 | #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1255 | #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ |
sahilmgandhi | 18:6a4db94011d3 | 1256 | #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ |
sahilmgandhi | 18:6a4db94011d3 | 1257 | #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ |
sahilmgandhi | 18:6a4db94011d3 | 1258 | #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1259 | #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1260 | #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1261 | #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1262 | #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1263 | #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1264 | #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ |
sahilmgandhi | 18:6a4db94011d3 | 1265 | #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ |
sahilmgandhi | 18:6a4db94011d3 | 1266 | #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ |
sahilmgandhi | 18:6a4db94011d3 | 1267 | #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1268 | #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1269 | #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ |
sahilmgandhi | 18:6a4db94011d3 | 1270 | #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ |
sahilmgandhi | 18:6a4db94011d3 | 1271 | #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ |
sahilmgandhi | 18:6a4db94011d3 | 1272 | #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1273 | #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1274 | #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ |
sahilmgandhi | 18:6a4db94011d3 | 1275 | #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ |
sahilmgandhi | 18:6a4db94011d3 | 1276 | #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1277 | #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1278 | #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1279 | #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1280 | #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1281 | #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1282 | #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1283 | #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1284 | #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1285 | #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1286 | #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1287 | #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1288 | #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1289 | #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1290 | #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1291 | #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1292 | #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1293 | #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ |
sahilmgandhi | 18:6a4db94011d3 | 1294 | |
sahilmgandhi | 18:6a4db94011d3 | 1295 | /* Bit fields for USART TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1296 | #define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1297 | #define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1298 | #define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ |
sahilmgandhi | 18:6a4db94011d3 | 1299 | #define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ |
sahilmgandhi | 18:6a4db94011d3 | 1300 | #define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1301 | #define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1302 | #define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1303 | #define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1304 | #define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1305 | #define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1306 | #define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1307 | #define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1308 | #define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1309 | #define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1310 | #define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1311 | #define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1312 | #define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1313 | #define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1314 | #define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1315 | #define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1316 | #define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1317 | #define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1318 | #define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ |
sahilmgandhi | 18:6a4db94011d3 | 1319 | #define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ |
sahilmgandhi | 18:6a4db94011d3 | 1320 | #define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1321 | #define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1322 | #define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1323 | #define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1324 | #define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1325 | #define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1326 | #define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1327 | #define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1328 | #define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1329 | #define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1330 | #define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1331 | #define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1332 | #define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1333 | #define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1334 | #define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1335 | #define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1336 | #define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1337 | #define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1338 | #define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ |
sahilmgandhi | 18:6a4db94011d3 | 1339 | #define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ |
sahilmgandhi | 18:6a4db94011d3 | 1340 | #define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1341 | #define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1342 | #define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1343 | #define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1344 | #define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1345 | #define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1346 | #define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1347 | #define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1348 | #define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1349 | #define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1350 | #define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1351 | #define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1352 | #define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1353 | #define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1354 | #define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1355 | #define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1356 | #define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1357 | #define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1358 | #define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ |
sahilmgandhi | 18:6a4db94011d3 | 1359 | #define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ |
sahilmgandhi | 18:6a4db94011d3 | 1360 | #define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1361 | #define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1362 | #define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1363 | #define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1364 | #define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1365 | #define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1366 | #define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1367 | #define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1368 | #define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1369 | #define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1370 | #define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1371 | #define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1372 | #define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1373 | #define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1374 | #define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1375 | #define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1376 | #define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1377 | #define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ |
sahilmgandhi | 18:6a4db94011d3 | 1378 | |
sahilmgandhi | 18:6a4db94011d3 | 1379 | /* Bit fields for USART CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1380 | #define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1381 | #define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1382 | #define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ |
sahilmgandhi | 18:6a4db94011d3 | 1383 | #define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ |
sahilmgandhi | 18:6a4db94011d3 | 1384 | #define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ |
sahilmgandhi | 18:6a4db94011d3 | 1385 | #define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1386 | #define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1387 | #define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ |
sahilmgandhi | 18:6a4db94011d3 | 1388 | #define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ |
sahilmgandhi | 18:6a4db94011d3 | 1389 | #define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ |
sahilmgandhi | 18:6a4db94011d3 | 1390 | #define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1391 | #define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1392 | #define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ |
sahilmgandhi | 18:6a4db94011d3 | 1393 | #define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1394 | #define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1395 | #define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1396 | #define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1397 | #define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ |
sahilmgandhi | 18:6a4db94011d3 | 1398 | #define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ |
sahilmgandhi | 18:6a4db94011d3 | 1399 | #define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ |
sahilmgandhi | 18:6a4db94011d3 | 1400 | #define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1401 | #define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ |
sahilmgandhi | 18:6a4db94011d3 | 1402 | |
sahilmgandhi | 18:6a4db94011d3 | 1403 | /* Bit fields for USART TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1404 | #define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1405 | #define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1406 | #define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ |
sahilmgandhi | 18:6a4db94011d3 | 1407 | #define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ |
sahilmgandhi | 18:6a4db94011d3 | 1408 | #define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1409 | #define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1410 | #define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ |
sahilmgandhi | 18:6a4db94011d3 | 1411 | #define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ |
sahilmgandhi | 18:6a4db94011d3 | 1412 | #define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1413 | #define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1414 | #define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1415 | #define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1416 | #define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1417 | #define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1418 | #define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1419 | #define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1420 | #define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1421 | #define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1422 | #define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1423 | #define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1424 | #define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ |
sahilmgandhi | 18:6a4db94011d3 | 1425 | #define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ |
sahilmgandhi | 18:6a4db94011d3 | 1426 | #define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1427 | #define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1428 | #define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1429 | #define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1430 | #define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1431 | #define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1432 | #define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1433 | #define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1434 | #define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1435 | #define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1436 | #define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1437 | #define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1438 | #define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1439 | #define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1440 | #define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1441 | |
sahilmgandhi | 18:6a4db94011d3 | 1442 | /* Bit fields for USART TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1443 | #define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1444 | #define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1445 | #define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ |
sahilmgandhi | 18:6a4db94011d3 | 1446 | #define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ |
sahilmgandhi | 18:6a4db94011d3 | 1447 | #define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1448 | #define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1449 | #define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ |
sahilmgandhi | 18:6a4db94011d3 | 1450 | #define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ |
sahilmgandhi | 18:6a4db94011d3 | 1451 | #define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1452 | #define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1453 | #define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1454 | #define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1455 | #define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1456 | #define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1457 | #define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1458 | #define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1459 | #define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1460 | #define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1461 | #define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1462 | #define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1463 | #define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ |
sahilmgandhi | 18:6a4db94011d3 | 1464 | #define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ |
sahilmgandhi | 18:6a4db94011d3 | 1465 | #define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1466 | #define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1467 | #define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1468 | #define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1469 | #define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1470 | #define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1471 | #define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1472 | #define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1473 | #define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1474 | #define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1475 | #define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1476 | #define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1477 | #define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1478 | #define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1479 | #define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1480 | |
sahilmgandhi | 18:6a4db94011d3 | 1481 | /* Bit fields for USART TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1482 | #define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1483 | #define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1484 | #define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ |
sahilmgandhi | 18:6a4db94011d3 | 1485 | #define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ |
sahilmgandhi | 18:6a4db94011d3 | 1486 | #define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1487 | #define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1488 | #define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ |
sahilmgandhi | 18:6a4db94011d3 | 1489 | #define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ |
sahilmgandhi | 18:6a4db94011d3 | 1490 | #define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1491 | #define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1492 | #define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1493 | #define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1494 | #define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1495 | #define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1496 | #define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1497 | #define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1498 | #define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1499 | #define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1500 | #define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1501 | #define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1502 | #define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ |
sahilmgandhi | 18:6a4db94011d3 | 1503 | #define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ |
sahilmgandhi | 18:6a4db94011d3 | 1504 | #define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1505 | #define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1506 | #define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1507 | #define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1508 | #define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1509 | #define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1510 | #define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1511 | #define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1512 | #define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1513 | #define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1514 | #define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1515 | #define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1516 | #define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1517 | #define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1518 | #define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ |
sahilmgandhi | 18:6a4db94011d3 | 1519 | |
sahilmgandhi | 18:6a4db94011d3 | 1520 | /* Bit fields for USART ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1521 | #define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1522 | #define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1523 | #define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1524 | #define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1525 | #define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1526 | #define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1527 | #define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1528 | #define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1529 | #define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1530 | #define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1531 | #define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1532 | #define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1533 | #define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1534 | #define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1535 | #define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1536 | #define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1537 | #define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1538 | #define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1539 | #define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1540 | #define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1541 | #define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1542 | #define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1543 | #define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1544 | #define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1545 | #define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1546 | #define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1547 | #define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1548 | #define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */ |
sahilmgandhi | 18:6a4db94011d3 | 1549 | #define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1550 | #define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1551 | #define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1552 | #define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */ |
sahilmgandhi | 18:6a4db94011d3 | 1553 | |
sahilmgandhi | 18:6a4db94011d3 | 1554 | /* Bit fields for USART ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1555 | #define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1556 | #define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1557 | #define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1558 | #define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1559 | #define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1560 | #define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1561 | #define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1562 | #define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1563 | #define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1564 | #define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1565 | #define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1566 | #define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1567 | #define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1568 | #define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1569 | #define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1570 | #define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1571 | #define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1572 | #define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1573 | #define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1574 | #define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1575 | #define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1576 | #define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1577 | #define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1578 | #define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1579 | #define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1580 | #define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1581 | #define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1582 | #define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1583 | #define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1584 | #define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1585 | #define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1586 | #define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1587 | #define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1588 | #define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1589 | #define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1590 | #define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1591 | #define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1592 | #define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1593 | #define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1594 | #define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1595 | #define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1596 | #define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1597 | #define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1598 | #define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1599 | #define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1600 | #define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1601 | #define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1602 | #define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1603 | #define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1604 | #define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1605 | #define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1606 | #define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1607 | #define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1608 | #define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1609 | #define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1610 | #define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1611 | #define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1612 | #define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1613 | #define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1614 | #define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1615 | #define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1616 | #define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1617 | #define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1618 | #define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1619 | #define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1620 | #define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1621 | #define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1622 | #define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1623 | #define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1624 | #define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1625 | #define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1626 | #define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1627 | #define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1628 | #define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1629 | #define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1630 | #define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1631 | #define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1632 | #define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1633 | #define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1634 | #define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1635 | #define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1636 | #define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1637 | #define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1638 | #define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1639 | #define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1640 | #define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1641 | #define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1642 | #define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1643 | #define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1644 | #define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1645 | #define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1646 | #define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1647 | #define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1648 | #define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1649 | #define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1650 | #define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1651 | #define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1652 | #define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1653 | #define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1654 | #define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1655 | #define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1656 | #define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1657 | #define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1658 | #define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1659 | #define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1660 | #define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1661 | #define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1662 | #define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1663 | #define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1664 | #define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1665 | #define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1666 | #define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1667 | #define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1668 | #define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1669 | #define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1670 | #define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1671 | #define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1672 | #define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1673 | #define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1674 | #define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1675 | #define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1676 | #define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1677 | #define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1678 | #define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1679 | #define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1680 | #define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1681 | #define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1682 | #define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1683 | #define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1684 | #define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1685 | #define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1686 | #define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1687 | #define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1688 | #define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1689 | #define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1690 | #define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1691 | #define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1692 | #define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1693 | #define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1694 | #define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1695 | #define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1696 | #define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1697 | #define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1698 | #define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1699 | #define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1700 | #define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1701 | #define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1702 | #define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1703 | #define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1704 | #define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1705 | #define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1706 | #define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1707 | #define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1708 | #define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1709 | #define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1710 | #define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1711 | #define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1712 | #define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1713 | #define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1714 | #define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1715 | #define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1716 | #define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1717 | #define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1718 | #define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1719 | #define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1720 | #define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1721 | #define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1722 | #define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1723 | #define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1724 | #define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1725 | #define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1726 | #define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1727 | #define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1728 | #define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1729 | #define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1730 | #define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1731 | #define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1732 | #define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1733 | #define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1734 | #define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1735 | #define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1736 | #define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1737 | #define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1738 | #define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1739 | #define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1740 | #define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1741 | #define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1742 | #define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1743 | #define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1744 | #define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1745 | #define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1746 | #define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1747 | #define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1748 | #define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1749 | #define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1750 | #define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1751 | #define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1752 | #define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1753 | #define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1754 | #define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1755 | #define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1756 | #define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1757 | #define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1758 | #define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1759 | #define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1760 | #define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1761 | #define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1762 | #define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1763 | #define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1764 | #define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1765 | #define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1766 | #define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1767 | #define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1768 | #define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1769 | #define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1770 | #define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1771 | #define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1772 | #define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1773 | #define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1774 | #define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1775 | #define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1776 | #define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1777 | #define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1778 | #define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1779 | #define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1780 | #define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1781 | #define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1782 | #define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1783 | #define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1784 | #define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1785 | #define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1786 | #define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1787 | #define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1788 | #define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1789 | #define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1790 | #define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1791 | #define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1792 | #define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1793 | #define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1794 | #define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1795 | #define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1796 | #define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1797 | #define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1798 | #define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1799 | #define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1800 | #define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1801 | #define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1802 | #define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1803 | #define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1804 | #define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1805 | #define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1806 | #define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1807 | #define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1808 | #define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1809 | #define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1810 | #define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1811 | #define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1812 | #define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1813 | #define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1814 | #define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1815 | #define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1816 | #define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1817 | #define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1818 | #define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1819 | #define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1820 | #define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1821 | #define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1822 | #define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1823 | #define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1824 | #define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1825 | #define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1826 | #define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1827 | #define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1828 | #define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */ |
sahilmgandhi | 18:6a4db94011d3 | 1829 | |
sahilmgandhi | 18:6a4db94011d3 | 1830 | /* Bit fields for USART ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1831 | #define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1832 | #define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1833 | #define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1834 | #define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1835 | #define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1836 | #define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1837 | #define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1838 | #define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1839 | #define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1840 | #define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1841 | #define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1842 | #define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1843 | #define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1844 | #define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1845 | #define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1846 | #define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1847 | #define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1848 | #define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1849 | #define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1850 | #define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1851 | #define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1852 | #define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1853 | #define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1854 | #define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1855 | #define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1856 | #define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1857 | #define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1858 | #define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1859 | #define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1860 | #define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1861 | #define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1862 | #define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1863 | #define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1864 | #define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1865 | #define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1866 | #define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1867 | #define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1868 | #define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1869 | #define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1870 | #define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1871 | #define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1872 | #define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1873 | #define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1874 | #define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1875 | #define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1876 | #define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1877 | #define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1878 | #define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1879 | #define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1880 | #define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1881 | #define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1882 | #define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1883 | #define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1884 | #define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1885 | #define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1886 | #define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1887 | #define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1888 | #define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1889 | #define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1890 | #define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1891 | #define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1892 | #define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1893 | #define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1894 | #define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1895 | #define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1896 | #define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1897 | #define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1898 | #define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1899 | #define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1900 | #define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1901 | #define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1902 | #define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */ |
sahilmgandhi | 18:6a4db94011d3 | 1903 | #define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1904 | #define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1905 | #define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1906 | #define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1907 | #define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1908 | #define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1909 | #define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1910 | #define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1911 | #define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1912 | #define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1913 | #define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1914 | #define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1915 | #define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1916 | #define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1917 | #define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1918 | #define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1919 | #define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1920 | #define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1921 | #define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1922 | #define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1923 | #define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1924 | #define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1925 | #define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1926 | #define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1927 | #define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1928 | #define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1929 | #define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1930 | #define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1931 | #define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1932 | #define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1933 | #define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1934 | #define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1935 | #define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1936 | #define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1937 | #define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1938 | #define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1939 | #define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1940 | #define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1941 | #define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1942 | #define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1943 | #define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1944 | #define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1945 | #define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1946 | #define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1947 | #define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1948 | #define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1949 | #define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1950 | #define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1951 | #define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1952 | #define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1953 | #define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1954 | #define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1955 | #define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1956 | #define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1957 | #define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1958 | #define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1959 | #define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1960 | #define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1961 | #define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1962 | #define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1963 | #define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1964 | #define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1965 | #define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1966 | #define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1967 | #define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1968 | #define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */ |
sahilmgandhi | 18:6a4db94011d3 | 1969 | |
sahilmgandhi | 18:6a4db94011d3 | 1970 | /** @} End of group EFR32MG1P_USART */ |
sahilmgandhi | 18:6a4db94011d3 | 1971 | /** @} End of group Parts */ |
sahilmgandhi | 18:6a4db94011d3 | 1972 |