Mouse code for the MacroRat
mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p132f256gm48.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @file efr32mg1p132f256gm48.h |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @brief CMSIS Cortex-M Peripheral Access Layer Header File |
sahilmgandhi | 18:6a4db94011d3 | 4 | * for EFR32MG1P132F256GM48 |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @version 5.1.2 |
sahilmgandhi | 18:6a4db94011d3 | 6 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @section License |
sahilmgandhi | 18:6a4db94011d3 | 8 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
sahilmgandhi | 18:6a4db94011d3 | 9 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 10 | * |
sahilmgandhi | 18:6a4db94011d3 | 11 | * Permission is granted to anyone to use this software for any purpose, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * including commercial applications, and to alter it and redistribute it |
sahilmgandhi | 18:6a4db94011d3 | 13 | * freely, subject to the following restrictions: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. The origin of this software must not be misrepresented; you must not |
sahilmgandhi | 18:6a4db94011d3 | 16 | * claim that you wrote the original software.@n |
sahilmgandhi | 18:6a4db94011d3 | 17 | * 2. Altered source versions must be plainly marked as such, and must not be |
sahilmgandhi | 18:6a4db94011d3 | 18 | * misrepresented as being the original software.@n |
sahilmgandhi | 18:6a4db94011d3 | 19 | * 3. This notice may not be removed or altered from any source distribution. |
sahilmgandhi | 18:6a4db94011d3 | 20 | * |
sahilmgandhi | 18:6a4db94011d3 | 21 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
sahilmgandhi | 18:6a4db94011d3 | 22 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
sahilmgandhi | 18:6a4db94011d3 | 23 | * providing the Software "AS IS", with no express or implied warranties of any |
sahilmgandhi | 18:6a4db94011d3 | 24 | * kind, including, but not limited to, any implied warranties of |
sahilmgandhi | 18:6a4db94011d3 | 25 | * merchantability or fitness for any particular purpose or warranties against |
sahilmgandhi | 18:6a4db94011d3 | 26 | * infringement of any proprietary rights of a third party. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
sahilmgandhi | 18:6a4db94011d3 | 29 | * incidental, or special damages, or any other relief, or for any claim by |
sahilmgandhi | 18:6a4db94011d3 | 30 | * any third party, arising from your use of this Software. |
sahilmgandhi | 18:6a4db94011d3 | 31 | * |
sahilmgandhi | 18:6a4db94011d3 | 32 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 33 | |
sahilmgandhi | 18:6a4db94011d3 | 34 | #ifndef EFR32MG1P132F256GM48_H |
sahilmgandhi | 18:6a4db94011d3 | 35 | #define EFR32MG1P132F256GM48_H |
sahilmgandhi | 18:6a4db94011d3 | 36 | |
sahilmgandhi | 18:6a4db94011d3 | 37 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 38 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 39 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 40 | |
sahilmgandhi | 18:6a4db94011d3 | 41 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 42 | * @addtogroup Parts |
sahilmgandhi | 18:6a4db94011d3 | 43 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 44 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 45 | |
sahilmgandhi | 18:6a4db94011d3 | 46 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 47 | * @defgroup EFR32MG1P132F256GM48 EFR32MG1P132F256GM48 |
sahilmgandhi | 18:6a4db94011d3 | 48 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 49 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 50 | |
sahilmgandhi | 18:6a4db94011d3 | 51 | /** Interrupt Number Definition */ |
sahilmgandhi | 18:6a4db94011d3 | 52 | typedef enum IRQn |
sahilmgandhi | 18:6a4db94011d3 | 53 | { |
sahilmgandhi | 18:6a4db94011d3 | 54 | /****** Cortex-M4 Processor Exceptions Numbers ********************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 55 | NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 56 | HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 57 | MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 58 | BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 59 | UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 62 | PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 63 | SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 64 | |
sahilmgandhi | 18:6a4db94011d3 | 65 | /****** EFR32MG1P Peripheral Interrupt Numbers ********************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 66 | |
sahilmgandhi | 18:6a4db94011d3 | 67 | EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | LDMA_IRQn = 8, /*!< 8 EFR32 LDMA Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 70 | GPIO_EVEN_IRQn = 9, /*!< 9 EFR32 GPIO_EVEN Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | USART0_RX_IRQn = 11, /*!< 11 EFR32 USART0_RX Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | USART0_TX_IRQn = 12, /*!< 12 EFR32 USART0_TX Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 74 | ACMP0_IRQn = 13, /*!< 13 EFR32 ACMP0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | ADC0_IRQn = 14, /*!< 14 EFR32 ADC0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | IDAC0_IRQn = 15, /*!< 15 EFR32 IDAC0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 77 | I2C0_IRQn = 16, /*!< 16 EFR32 I2C0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 78 | GPIO_ODD_IRQn = 17, /*!< 17 EFR32 GPIO_ODD Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 79 | TIMER1_IRQn = 18, /*!< 18 EFR32 TIMER1 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | USART1_RX_IRQn = 19, /*!< 19 EFR32 USART1_RX Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | USART1_TX_IRQn = 20, /*!< 20 EFR32 USART1_TX Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | LEUART0_IRQn = 21, /*!< 21 EFR32 LEUART0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | PCNT0_IRQn = 22, /*!< 22 EFR32 PCNT0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | CMU_IRQn = 23, /*!< 23 EFR32 CMU Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 85 | MSC_IRQn = 24, /*!< 24 EFR32 MSC Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 86 | CRYPTO_IRQn = 25, /*!< 25 EFR32 CRYPTO Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | LETIMER0_IRQn = 26, /*!< 26 EFR32 LETIMER0 Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | RTCC_IRQn = 29, /*!< 29 EFR32 RTCC Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 89 | CRYOTIMER_IRQn = 31, /*!< 31 EFR32 CRYOTIMER Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | FPUEH_IRQn = 33, /*!< 33 EFR32 FPUEH Interrupt */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | } IRQn_Type; |
sahilmgandhi | 18:6a4db94011d3 | 92 | |
sahilmgandhi | 18:6a4db94011d3 | 93 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 94 | * @defgroup EFR32MG1P132F256GM48_Core EFR32MG1P132F256GM48 Core |
sahilmgandhi | 18:6a4db94011d3 | 95 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 96 | * @brief Processor and Core Peripheral Section |
sahilmgandhi | 18:6a4db94011d3 | 97 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 98 | #define __MPU_PRESENT 1 /**< Presence of MPU */ |
sahilmgandhi | 18:6a4db94011d3 | 99 | #define __FPU_PRESENT 1 /**< Presence of FPU */ |
sahilmgandhi | 18:6a4db94011d3 | 100 | #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */ |
sahilmgandhi | 18:6a4db94011d3 | 102 | #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | |
sahilmgandhi | 18:6a4db94011d3 | 104 | /** @} End of group EFR32MG1P132F256GM48_Core */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | |
sahilmgandhi | 18:6a4db94011d3 | 106 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 107 | * @defgroup EFR32MG1P132F256GM48_Part EFR32MG1P132F256GM48 Part |
sahilmgandhi | 18:6a4db94011d3 | 108 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 109 | ******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 110 | |
sahilmgandhi | 18:6a4db94011d3 | 111 | /** Part family */ |
sahilmgandhi | 18:6a4db94011d3 | 112 | #define _EFR32_MIGHTY_FAMILY 1 /**< MIGHTY Gecko RF SoC Family */ |
sahilmgandhi | 18:6a4db94011d3 | 113 | #define _EFR_DEVICE /**< Silicon Labs EFR-type RF SoC */ |
sahilmgandhi | 18:6a4db94011d3 | 114 | #define _SILICON_LABS_32B_SERIES_1 /**< Silicon Labs series number */ |
sahilmgandhi | 18:6a4db94011d3 | 115 | #define _SILICON_LABS_32B_SERIES 1 /**< Silicon Labs series number */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | #define _SILICON_LABS_32B_SERIES_1_CONFIG_1 /**< Series 1, Configuration 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | #define _SILICON_LABS_32B_SERIES_1_CONFIG 1 /**< Series 1, Configuration 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 118 | #define _SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */ |
sahilmgandhi | 18:6a4db94011d3 | 119 | #define _SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | #define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 |
sahilmgandhi | 18:6a4db94011d3 | 121 | #define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 |
sahilmgandhi | 18:6a4db94011d3 | 122 | #define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 |
sahilmgandhi | 18:6a4db94011d3 | 123 | #define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ |
sahilmgandhi | 18:6a4db94011d3 | 124 | #define _SILICON_LABS_32B_PLATFORM_2 /**< @deprecated Silicon Labs platform name */ |
sahilmgandhi | 18:6a4db94011d3 | 125 | #define _SILICON_LABS_32B_PLATFORM 2 /**< @deprecated Silicon Labs platform name */ |
sahilmgandhi | 18:6a4db94011d3 | 126 | #define _SILICON_LABS_32B_PLATFORM_2_GEN_1 /**< @deprecated Platform 2, generation 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 127 | #define _SILICON_LABS_32B_PLATFORM_2_GEN 1 /**< @deprecated Platform 2, generation 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | /* If part number is not defined as compiler option, define it */ |
sahilmgandhi | 18:6a4db94011d3 | 130 | #if !defined(EFR32MG1P132F256GM48) |
sahilmgandhi | 18:6a4db94011d3 | 131 | #define EFR32MG1P132F256GM48 1 /**< MIGHTY Gecko Part */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 133 | |
sahilmgandhi | 18:6a4db94011d3 | 134 | /** Configure part number */ |
sahilmgandhi | 18:6a4db94011d3 | 135 | #define PART_NUMBER "EFR32MG1P132F256GM48" /**< Part Number */ |
sahilmgandhi | 18:6a4db94011d3 | 136 | |
sahilmgandhi | 18:6a4db94011d3 | 137 | /** Memory Base addresses and limits */ |
sahilmgandhi | 18:6a4db94011d3 | 138 | #define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ |
sahilmgandhi | 18:6a4db94011d3 | 139 | #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | #define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ |
sahilmgandhi | 18:6a4db94011d3 | 141 | #define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 142 | #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ |
sahilmgandhi | 18:6a4db94011d3 | 143 | #define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 144 | #define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ |
sahilmgandhi | 18:6a4db94011d3 | 145 | #define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | #define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ |
sahilmgandhi | 18:6a4db94011d3 | 147 | #define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | #define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ |
sahilmgandhi | 18:6a4db94011d3 | 149 | #define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 150 | #define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | #define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 152 | #define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ |
sahilmgandhi | 18:6a4db94011d3 | 153 | #define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 154 | #define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ |
sahilmgandhi | 18:6a4db94011d3 | 155 | #define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 156 | #define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ |
sahilmgandhi | 18:6a4db94011d3 | 157 | #define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 158 | #define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | #define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 160 | #define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ |
sahilmgandhi | 18:6a4db94011d3 | 161 | #define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 162 | #define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | #define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 164 | #define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ |
sahilmgandhi | 18:6a4db94011d3 | 165 | #define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 166 | #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ |
sahilmgandhi | 18:6a4db94011d3 | 167 | #define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 168 | #define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | #define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 170 | #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ |
sahilmgandhi | 18:6a4db94011d3 | 171 | #define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ |
sahilmgandhi | 18:6a4db94011d3 | 172 | #define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ |
sahilmgandhi | 18:6a4db94011d3 | 173 | #define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | |
sahilmgandhi | 18:6a4db94011d3 | 175 | /** Bit banding area */ |
sahilmgandhi | 18:6a4db94011d3 | 176 | #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ |
sahilmgandhi | 18:6a4db94011d3 | 177 | #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | |
sahilmgandhi | 18:6a4db94011d3 | 179 | /** Flash and SRAM limits for EFR32MG1P132F256GM48 */ |
sahilmgandhi | 18:6a4db94011d3 | 180 | #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ |
sahilmgandhi | 18:6a4db94011d3 | 181 | #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */ |
sahilmgandhi | 18:6a4db94011d3 | 182 | #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */ |
sahilmgandhi | 18:6a4db94011d3 | 183 | #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | #define SRAM_SIZE (0x00007C00UL) /**< Available SRAM Memory */ |
sahilmgandhi | 18:6a4db94011d3 | 185 | #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */ |
sahilmgandhi | 18:6a4db94011d3 | 186 | #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */ |
sahilmgandhi | 18:6a4db94011d3 | 187 | #define DMA_CHAN_COUNT 8 /**< Number of DMA channels */ |
sahilmgandhi | 18:6a4db94011d3 | 188 | #define EXT_IRQ_COUNT 34 /**< Number of External (NVIC) interrupts */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | |
sahilmgandhi | 18:6a4db94011d3 | 190 | /** AF channels connect the different on-chip peripherals with the af-mux */ |
sahilmgandhi | 18:6a4db94011d3 | 191 | #define AFCHAN_MAX 72 |
sahilmgandhi | 18:6a4db94011d3 | 192 | #define AFCHANLOC_MAX 32 |
sahilmgandhi | 18:6a4db94011d3 | 193 | /** Analog AF channels */ |
sahilmgandhi | 18:6a4db94011d3 | 194 | #define AFACHAN_MAX 61 |
sahilmgandhi | 18:6a4db94011d3 | 195 | |
sahilmgandhi | 18:6a4db94011d3 | 196 | /* Part number capabilities */ |
sahilmgandhi | 18:6a4db94011d3 | 197 | |
sahilmgandhi | 18:6a4db94011d3 | 198 | #define TIMER_PRESENT /**< TIMER is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 199 | #define TIMER_COUNT 2 /**< 2 TIMERs available */ |
sahilmgandhi | 18:6a4db94011d3 | 200 | #define USART_PRESENT /**< USART is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 201 | #define USART_COUNT 2 /**< 2 USARTs available */ |
sahilmgandhi | 18:6a4db94011d3 | 202 | #define LEUART_PRESENT /**< LEUART is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 203 | #define LEUART_COUNT 1 /**< 1 LEUARTs available */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | #define LETIMER_PRESENT /**< LETIMER is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 205 | #define LETIMER_COUNT 1 /**< 1 LETIMERs available */ |
sahilmgandhi | 18:6a4db94011d3 | 206 | #define PCNT_PRESENT /**< PCNT is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | #define PCNT_COUNT 1 /**< 1 PCNTs available */ |
sahilmgandhi | 18:6a4db94011d3 | 208 | #define I2C_PRESENT /**< I2C is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 209 | #define I2C_COUNT 1 /**< 1 I2Cs available */ |
sahilmgandhi | 18:6a4db94011d3 | 210 | #define ADC_PRESENT /**< ADC is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 211 | #define ADC_COUNT 1 /**< 1 ADCs available */ |
sahilmgandhi | 18:6a4db94011d3 | 212 | #define ACMP_PRESENT /**< ACMP is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 213 | #define ACMP_COUNT 2 /**< 2 ACMPs available */ |
sahilmgandhi | 18:6a4db94011d3 | 214 | #define IDAC_PRESENT /**< IDAC is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 215 | #define IDAC_COUNT 1 /**< 1 IDACs available */ |
sahilmgandhi | 18:6a4db94011d3 | 216 | #define WDOG_PRESENT /**< WDOG is available in this part */ |
sahilmgandhi | 18:6a4db94011d3 | 217 | #define WDOG_COUNT 1 /**< 1 WDOGs available */ |
sahilmgandhi | 18:6a4db94011d3 | 218 | #define MSC_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 219 | #define MSC_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 220 | #define EMU_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 221 | #define EMU_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 222 | #define RMU_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 223 | #define RMU_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 224 | #define CMU_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 225 | #define CMU_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 226 | #define CRYPTO_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 227 | #define CRYPTO_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 228 | #define GPIO_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 229 | #define GPIO_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 230 | #define PRS_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 231 | #define PRS_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 232 | #define LDMA_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 233 | #define LDMA_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 234 | #define FPUEH_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 235 | #define FPUEH_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 236 | #define GPCRC_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 237 | #define GPCRC_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 238 | #define CRYOTIMER_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 239 | #define CRYOTIMER_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 240 | #define RTCC_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 241 | #define RTCC_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 242 | #define BOOTLOADER_PRESENT |
sahilmgandhi | 18:6a4db94011d3 | 243 | #define BOOTLOADER_COUNT 1 |
sahilmgandhi | 18:6a4db94011d3 | 244 | |
sahilmgandhi | 18:6a4db94011d3 | 245 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
sahilmgandhi | 18:6a4db94011d3 | 246 | #include "system_efr32mg1p.h" /* System Header File */ |
sahilmgandhi | 18:6a4db94011d3 | 247 | |
sahilmgandhi | 18:6a4db94011d3 | 248 | /** @} End of group EFR32MG1P132F256GM48_Part */ |
sahilmgandhi | 18:6a4db94011d3 | 249 | |
sahilmgandhi | 18:6a4db94011d3 | 250 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 251 | * @defgroup EFR32MG1P132F256GM48_Peripheral_TypeDefs EFR32MG1P132F256GM48 Peripheral TypeDefs |
sahilmgandhi | 18:6a4db94011d3 | 252 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 253 | * @brief Device Specific Peripheral Register Structures |
sahilmgandhi | 18:6a4db94011d3 | 254 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 255 | |
sahilmgandhi | 18:6a4db94011d3 | 256 | #include "efr32mg1p_msc.h" |
sahilmgandhi | 18:6a4db94011d3 | 257 | #include "efr32mg1p_emu.h" |
sahilmgandhi | 18:6a4db94011d3 | 258 | #include "efr32mg1p_rmu.h" |
sahilmgandhi | 18:6a4db94011d3 | 259 | #include "efr32mg1p_cmu.h" |
sahilmgandhi | 18:6a4db94011d3 | 260 | #include "efr32mg1p_crypto.h" |
sahilmgandhi | 18:6a4db94011d3 | 261 | #include "efr32mg1p_gpio_p.h" |
sahilmgandhi | 18:6a4db94011d3 | 262 | #include "efr32mg1p_gpio.h" |
sahilmgandhi | 18:6a4db94011d3 | 263 | #include "efr32mg1p_prs_ch.h" |
sahilmgandhi | 18:6a4db94011d3 | 264 | #include "efr32mg1p_prs.h" |
sahilmgandhi | 18:6a4db94011d3 | 265 | #include "efr32mg1p_ldma_ch.h" |
sahilmgandhi | 18:6a4db94011d3 | 266 | #include "efr32mg1p_ldma.h" |
sahilmgandhi | 18:6a4db94011d3 | 267 | #include "efr32mg1p_fpueh.h" |
sahilmgandhi | 18:6a4db94011d3 | 268 | #include "efr32mg1p_gpcrc.h" |
sahilmgandhi | 18:6a4db94011d3 | 269 | #include "efr32mg1p_timer_cc.h" |
sahilmgandhi | 18:6a4db94011d3 | 270 | #include "efr32mg1p_timer.h" |
sahilmgandhi | 18:6a4db94011d3 | 271 | #include "efr32mg1p_usart.h" |
sahilmgandhi | 18:6a4db94011d3 | 272 | #include "efr32mg1p_leuart.h" |
sahilmgandhi | 18:6a4db94011d3 | 273 | #include "efr32mg1p_letimer.h" |
sahilmgandhi | 18:6a4db94011d3 | 274 | #include "efr32mg1p_cryotimer.h" |
sahilmgandhi | 18:6a4db94011d3 | 275 | #include "efr32mg1p_pcnt.h" |
sahilmgandhi | 18:6a4db94011d3 | 276 | #include "efr32mg1p_i2c.h" |
sahilmgandhi | 18:6a4db94011d3 | 277 | #include "efr32mg1p_adc.h" |
sahilmgandhi | 18:6a4db94011d3 | 278 | #include "efr32mg1p_acmp.h" |
sahilmgandhi | 18:6a4db94011d3 | 279 | #include "efr32mg1p_idac.h" |
sahilmgandhi | 18:6a4db94011d3 | 280 | #include "efr32mg1p_rtcc_cc.h" |
sahilmgandhi | 18:6a4db94011d3 | 281 | #include "efr32mg1p_rtcc_ret.h" |
sahilmgandhi | 18:6a4db94011d3 | 282 | #include "efr32mg1p_rtcc.h" |
sahilmgandhi | 18:6a4db94011d3 | 283 | #include "efr32mg1p_wdog_pch.h" |
sahilmgandhi | 18:6a4db94011d3 | 284 | #include "efr32mg1p_wdog.h" |
sahilmgandhi | 18:6a4db94011d3 | 285 | #include "efr32mg1p_dma_descriptor.h" |
sahilmgandhi | 18:6a4db94011d3 | 286 | #include "efr32mg1p_devinfo.h" |
sahilmgandhi | 18:6a4db94011d3 | 287 | #include "efr32mg1p_romtable.h" |
sahilmgandhi | 18:6a4db94011d3 | 288 | |
sahilmgandhi | 18:6a4db94011d3 | 289 | /** @} End of group EFR32MG1P132F256GM48_Peripheral_TypeDefs */ |
sahilmgandhi | 18:6a4db94011d3 | 290 | |
sahilmgandhi | 18:6a4db94011d3 | 291 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 292 | * @defgroup EFR32MG1P132F256GM48_Peripheral_Base EFR32MG1P132F256GM48 Peripheral Memory Map |
sahilmgandhi | 18:6a4db94011d3 | 293 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 294 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 295 | |
sahilmgandhi | 18:6a4db94011d3 | 296 | #define MSC_BASE (0x400E0000UL) /**< MSC base address */ |
sahilmgandhi | 18:6a4db94011d3 | 297 | #define EMU_BASE (0x400E3000UL) /**< EMU base address */ |
sahilmgandhi | 18:6a4db94011d3 | 298 | #define RMU_BASE (0x400E5000UL) /**< RMU base address */ |
sahilmgandhi | 18:6a4db94011d3 | 299 | #define CMU_BASE (0x400E4000UL) /**< CMU base address */ |
sahilmgandhi | 18:6a4db94011d3 | 300 | #define CRYPTO_BASE (0x400F0000UL) /**< CRYPTO base address */ |
sahilmgandhi | 18:6a4db94011d3 | 301 | #define GPIO_BASE (0x4000A000UL) /**< GPIO base address */ |
sahilmgandhi | 18:6a4db94011d3 | 302 | #define PRS_BASE (0x400E6000UL) /**< PRS base address */ |
sahilmgandhi | 18:6a4db94011d3 | 303 | #define LDMA_BASE (0x400E2000UL) /**< LDMA base address */ |
sahilmgandhi | 18:6a4db94011d3 | 304 | #define FPUEH_BASE (0x400E1000UL) /**< FPUEH base address */ |
sahilmgandhi | 18:6a4db94011d3 | 305 | #define GPCRC_BASE (0x4001C000UL) /**< GPCRC base address */ |
sahilmgandhi | 18:6a4db94011d3 | 306 | #define TIMER0_BASE (0x40018000UL) /**< TIMER0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 307 | #define TIMER1_BASE (0x40018400UL) /**< TIMER1 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 308 | #define USART0_BASE (0x40010000UL) /**< USART0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 309 | #define USART1_BASE (0x40010400UL) /**< USART1 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 310 | #define LEUART0_BASE (0x4004A000UL) /**< LEUART0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 311 | #define LETIMER0_BASE (0x40046000UL) /**< LETIMER0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 312 | #define CRYOTIMER_BASE (0x4001E000UL) /**< CRYOTIMER base address */ |
sahilmgandhi | 18:6a4db94011d3 | 313 | #define PCNT0_BASE (0x4004E000UL) /**< PCNT0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 314 | #define I2C0_BASE (0x4000C000UL) /**< I2C0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 315 | #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 316 | #define ACMP0_BASE (0x40000000UL) /**< ACMP0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 317 | #define ACMP1_BASE (0x40000400UL) /**< ACMP1 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 318 | #define IDAC0_BASE (0x40006000UL) /**< IDAC0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 319 | #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ |
sahilmgandhi | 18:6a4db94011d3 | 320 | #define WDOG0_BASE (0x40052000UL) /**< WDOG0 base address */ |
sahilmgandhi | 18:6a4db94011d3 | 321 | #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */ |
sahilmgandhi | 18:6a4db94011d3 | 322 | #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */ |
sahilmgandhi | 18:6a4db94011d3 | 324 | #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */ |
sahilmgandhi | 18:6a4db94011d3 | 325 | |
sahilmgandhi | 18:6a4db94011d3 | 326 | /** @} End of group EFR32MG1P132F256GM48_Peripheral_Base */ |
sahilmgandhi | 18:6a4db94011d3 | 327 | |
sahilmgandhi | 18:6a4db94011d3 | 328 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 329 | * @defgroup EFR32MG1P132F256GM48_Peripheral_Declaration EFR32MG1P132F256GM48 Peripheral Declarations |
sahilmgandhi | 18:6a4db94011d3 | 330 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 331 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 332 | |
sahilmgandhi | 18:6a4db94011d3 | 333 | #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 334 | #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 335 | #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 336 | #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 337 | #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) /**< CRYPTO base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 338 | #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 339 | #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 340 | #define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 341 | #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 342 | #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 343 | #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 344 | #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 345 | #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 346 | #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 347 | #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 348 | #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 349 | #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) /**< CRYOTIMER base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 350 | #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 351 | #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 352 | #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 353 | #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 354 | #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 355 | #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 356 | #define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 357 | #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 358 | #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 359 | #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */ |
sahilmgandhi | 18:6a4db94011d3 | 360 | |
sahilmgandhi | 18:6a4db94011d3 | 361 | /** @} End of group EFR32MG1P132F256GM48_Peripheral_Declaration */ |
sahilmgandhi | 18:6a4db94011d3 | 362 | |
sahilmgandhi | 18:6a4db94011d3 | 363 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 364 | * @defgroup EFR32MG1P132F256GM48_Peripheral_Offsets EFR32MG1P132F256GM48 Peripheral Offsets |
sahilmgandhi | 18:6a4db94011d3 | 365 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 366 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 367 | |
sahilmgandhi | 18:6a4db94011d3 | 368 | #define TIMER_OFFSET 0x400 /**< Offset in bytes between TIMER instances */ |
sahilmgandhi | 18:6a4db94011d3 | 369 | #define USART_OFFSET 0x400 /**< Offset in bytes between USART instances */ |
sahilmgandhi | 18:6a4db94011d3 | 370 | #define LEUART_OFFSET 0x400 /**< Offset in bytes between LEUART instances */ |
sahilmgandhi | 18:6a4db94011d3 | 371 | #define LETIMER_OFFSET 0x400 /**< Offset in bytes between LETIMER instances */ |
sahilmgandhi | 18:6a4db94011d3 | 372 | #define PCNT_OFFSET 0x400 /**< Offset in bytes between PCNT instances */ |
sahilmgandhi | 18:6a4db94011d3 | 373 | #define I2C_OFFSET 0x400 /**< Offset in bytes between I2C instances */ |
sahilmgandhi | 18:6a4db94011d3 | 374 | #define ADC_OFFSET 0x400 /**< Offset in bytes between ADC instances */ |
sahilmgandhi | 18:6a4db94011d3 | 375 | #define ACMP_OFFSET 0x400 /**< Offset in bytes between ACMP instances */ |
sahilmgandhi | 18:6a4db94011d3 | 376 | #define IDAC_OFFSET 0x400 /**< Offset in bytes between IDAC instances */ |
sahilmgandhi | 18:6a4db94011d3 | 377 | #define WDOG_OFFSET 0x400 /**< Offset in bytes between WDOG instances */ |
sahilmgandhi | 18:6a4db94011d3 | 378 | |
sahilmgandhi | 18:6a4db94011d3 | 379 | /** @} End of group EFR32MG1P132F256GM48_Peripheral_Offsets */ |
sahilmgandhi | 18:6a4db94011d3 | 380 | |
sahilmgandhi | 18:6a4db94011d3 | 381 | |
sahilmgandhi | 18:6a4db94011d3 | 382 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 383 | * @defgroup EFR32MG1P132F256GM48_BitFields EFR32MG1P132F256GM48 Bit Fields |
sahilmgandhi | 18:6a4db94011d3 | 384 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 385 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 386 | |
sahilmgandhi | 18:6a4db94011d3 | 387 | #include "efr32mg1p_prs_signals.h" |
sahilmgandhi | 18:6a4db94011d3 | 388 | #include "efr32mg1p_dmareq.h" |
sahilmgandhi | 18:6a4db94011d3 | 389 | |
sahilmgandhi | 18:6a4db94011d3 | 390 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 391 | * @defgroup EFR32MG1P132F256GM48_UNLOCK EFR32MG1P132F256GM48 Unlock Codes |
sahilmgandhi | 18:6a4db94011d3 | 392 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 393 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 394 | #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */ |
sahilmgandhi | 18:6a4db94011d3 | 395 | #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */ |
sahilmgandhi | 18:6a4db94011d3 | 396 | #define RMU_UNLOCK_CODE 0xE084 /**< RMU unlock code */ |
sahilmgandhi | 18:6a4db94011d3 | 397 | #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */ |
sahilmgandhi | 18:6a4db94011d3 | 398 | #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */ |
sahilmgandhi | 18:6a4db94011d3 | 399 | #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */ |
sahilmgandhi | 18:6a4db94011d3 | 400 | #define RTCC_UNLOCK_CODE 0xAEE8 /**< RTCC unlock code */ |
sahilmgandhi | 18:6a4db94011d3 | 401 | |
sahilmgandhi | 18:6a4db94011d3 | 402 | /** @} End of group EFR32MG1P132F256GM48_UNLOCK */ |
sahilmgandhi | 18:6a4db94011d3 | 403 | |
sahilmgandhi | 18:6a4db94011d3 | 404 | /** @} End of group EFR32MG1P132F256GM48_BitFields */ |
sahilmgandhi | 18:6a4db94011d3 | 405 | |
sahilmgandhi | 18:6a4db94011d3 | 406 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 407 | * @defgroup EFR32MG1P132F256GM48_Alternate_Function EFR32MG1P132F256GM48 Alternate Function |
sahilmgandhi | 18:6a4db94011d3 | 408 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 409 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 410 | |
sahilmgandhi | 18:6a4db94011d3 | 411 | #include "efr32mg1p_af_ports.h" |
sahilmgandhi | 18:6a4db94011d3 | 412 | #include "efr32mg1p_af_pins.h" |
sahilmgandhi | 18:6a4db94011d3 | 413 | |
sahilmgandhi | 18:6a4db94011d3 | 414 | /** @} End of group EFR32MG1P132F256GM48_Alternate_Function */ |
sahilmgandhi | 18:6a4db94011d3 | 415 | |
sahilmgandhi | 18:6a4db94011d3 | 416 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 417 | * @brief Set the value of a bit field within a register. |
sahilmgandhi | 18:6a4db94011d3 | 418 | * |
sahilmgandhi | 18:6a4db94011d3 | 419 | * @param REG |
sahilmgandhi | 18:6a4db94011d3 | 420 | * The register to update |
sahilmgandhi | 18:6a4db94011d3 | 421 | * @param MASK |
sahilmgandhi | 18:6a4db94011d3 | 422 | * The mask for the bit field to update |
sahilmgandhi | 18:6a4db94011d3 | 423 | * @param VALUE |
sahilmgandhi | 18:6a4db94011d3 | 424 | * The value to write to the bit field |
sahilmgandhi | 18:6a4db94011d3 | 425 | * @param OFFSET |
sahilmgandhi | 18:6a4db94011d3 | 426 | * The number of bits that the field is offset within the register. |
sahilmgandhi | 18:6a4db94011d3 | 427 | * 0 (zero) means LSB. |
sahilmgandhi | 18:6a4db94011d3 | 428 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 429 | #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ |
sahilmgandhi | 18:6a4db94011d3 | 430 | REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
sahilmgandhi | 18:6a4db94011d3 | 431 | |
sahilmgandhi | 18:6a4db94011d3 | 432 | /** @} End of group EFR32MG1P132F256GM48 */ |
sahilmgandhi | 18:6a4db94011d3 | 433 | |
sahilmgandhi | 18:6a4db94011d3 | 434 | /** @} End of group Parts */ |
sahilmgandhi | 18:6a4db94011d3 | 435 | |
sahilmgandhi | 18:6a4db94011d3 | 436 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 437 | } |
sahilmgandhi | 18:6a4db94011d3 | 438 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 439 | #endif /* EFR32MG1P132F256GM48_H */ |