Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file stm32f4xx_ll_fmc.c |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @author MCD Application Team |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V1.5.0 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 06-May-2016 |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @brief FMC Low Layer HAL module driver. |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | * This file provides firmware functions to manage the following |
sahilmgandhi | 18:6a4db94011d3 | 10 | * functionalities of the Flexible Memory Controller (FMC) peripheral memories: |
sahilmgandhi | 18:6a4db94011d3 | 11 | * + Initialization/de-initialization functions |
sahilmgandhi | 18:6a4db94011d3 | 12 | * + Peripheral Control functions |
sahilmgandhi | 18:6a4db94011d3 | 13 | * + Peripheral State functions |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 16 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 17 | ##### FMC peripheral features ##### |
sahilmgandhi | 18:6a4db94011d3 | 18 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 19 | [..] The Flexible memory controller (FMC) includes three memory controllers: |
sahilmgandhi | 18:6a4db94011d3 | 20 | (+) The NOR/PSRAM memory controller |
sahilmgandhi | 18:6a4db94011d3 | 21 | (+) The NAND/PC Card memory controller |
sahilmgandhi | 18:6a4db94011d3 | 22 | (+) The Synchronous DRAM (SDRAM) controller |
sahilmgandhi | 18:6a4db94011d3 | 23 | |
sahilmgandhi | 18:6a4db94011d3 | 24 | [..] The FMC functional block makes the interface with synchronous and asynchronous static |
sahilmgandhi | 18:6a4db94011d3 | 25 | memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: |
sahilmgandhi | 18:6a4db94011d3 | 26 | (+) to translate AHB transactions into the appropriate external device protocol |
sahilmgandhi | 18:6a4db94011d3 | 27 | (+) to meet the access time requirements of the external memory devices |
sahilmgandhi | 18:6a4db94011d3 | 28 | |
sahilmgandhi | 18:6a4db94011d3 | 29 | [..] All external memories share the addresses, data and control signals with the controller. |
sahilmgandhi | 18:6a4db94011d3 | 30 | Each external device is accessed by means of a unique Chip Select. The FMC performs |
sahilmgandhi | 18:6a4db94011d3 | 31 | only one access at a time to an external device. |
sahilmgandhi | 18:6a4db94011d3 | 32 | The main features of the FMC controller are the following: |
sahilmgandhi | 18:6a4db94011d3 | 33 | (+) Interface with static-memory mapped devices including: |
sahilmgandhi | 18:6a4db94011d3 | 34 | (++) Static random access memory (SRAM) |
sahilmgandhi | 18:6a4db94011d3 | 35 | (++) Read-only memory (ROM) |
sahilmgandhi | 18:6a4db94011d3 | 36 | (++) NOR Flash memory/OneNAND Flash memory |
sahilmgandhi | 18:6a4db94011d3 | 37 | (++) PSRAM (4 memory banks) |
sahilmgandhi | 18:6a4db94011d3 | 38 | (++) 16-bit PC Card compatible devices |
sahilmgandhi | 18:6a4db94011d3 | 39 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
sahilmgandhi | 18:6a4db94011d3 | 40 | data |
sahilmgandhi | 18:6a4db94011d3 | 41 | (+) Interface with synchronous DRAM (SDRAM) memories |
sahilmgandhi | 18:6a4db94011d3 | 42 | (+) Independent Chip Select control for each memory bank |
sahilmgandhi | 18:6a4db94011d3 | 43 | (+) Independent configuration for each memory bank |
sahilmgandhi | 18:6a4db94011d3 | 44 | |
sahilmgandhi | 18:6a4db94011d3 | 45 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 46 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 47 | * @attention |
sahilmgandhi | 18:6a4db94011d3 | 48 | * |
sahilmgandhi | 18:6a4db94011d3 | 49 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
sahilmgandhi | 18:6a4db94011d3 | 50 | * |
sahilmgandhi | 18:6a4db94011d3 | 51 | * Redistribution and use in source and binary forms, with or without modification, |
sahilmgandhi | 18:6a4db94011d3 | 52 | * are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 53 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 54 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 55 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 56 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 57 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 58 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 59 | * may be used to endorse or promote products derived from this software |
sahilmgandhi | 18:6a4db94011d3 | 60 | * without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 61 | * |
sahilmgandhi | 18:6a4db94011d3 | 62 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 63 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 64 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
sahilmgandhi | 18:6a4db94011d3 | 65 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
sahilmgandhi | 18:6a4db94011d3 | 66 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 67 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
sahilmgandhi | 18:6a4db94011d3 | 68 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
sahilmgandhi | 18:6a4db94011d3 | 69 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
sahilmgandhi | 18:6a4db94011d3 | 70 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
sahilmgandhi | 18:6a4db94011d3 | 71 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 72 | * |
sahilmgandhi | 18:6a4db94011d3 | 73 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 74 | */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | |
sahilmgandhi | 18:6a4db94011d3 | 76 | /* Includes ------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 77 | #include "stm32f4xx_hal.h" |
sahilmgandhi | 18:6a4db94011d3 | 78 | |
sahilmgandhi | 18:6a4db94011d3 | 79 | /** @addtogroup STM32F4xx_HAL_Driver |
sahilmgandhi | 18:6a4db94011d3 | 80 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 81 | */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | |
sahilmgandhi | 18:6a4db94011d3 | 83 | /** @defgroup FMC_LL FMC Low Layer |
sahilmgandhi | 18:6a4db94011d3 | 84 | * @brief FMC driver modules |
sahilmgandhi | 18:6a4db94011d3 | 85 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 86 | */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) |
sahilmgandhi | 18:6a4db94011d3 | 89 | |
sahilmgandhi | 18:6a4db94011d3 | 90 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | /* Private typedef -----------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 93 | /* Private define ------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 94 | /* Private macro -------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 95 | /* Private variables ---------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 96 | /* Private function prototypes -----------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 97 | /* Private functions ---------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 98 | /** @addtogroup FMC_LL_Private_Functions |
sahilmgandhi | 18:6a4db94011d3 | 99 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 100 | */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | |
sahilmgandhi | 18:6a4db94011d3 | 102 | /** @addtogroup FMC_LL_NORSRAM |
sahilmgandhi | 18:6a4db94011d3 | 103 | * @brief NORSRAM Controller functions |
sahilmgandhi | 18:6a4db94011d3 | 104 | * |
sahilmgandhi | 18:6a4db94011d3 | 105 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 106 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 107 | ##### How to use NORSRAM device driver ##### |
sahilmgandhi | 18:6a4db94011d3 | 108 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 109 | |
sahilmgandhi | 18:6a4db94011d3 | 110 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 111 | This driver contains a set of APIs to interface with the FMC NORSRAM banks in order |
sahilmgandhi | 18:6a4db94011d3 | 112 | to run the NORSRAM external devices. |
sahilmgandhi | 18:6a4db94011d3 | 113 | |
sahilmgandhi | 18:6a4db94011d3 | 114 | (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() |
sahilmgandhi | 18:6a4db94011d3 | 115 | (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() |
sahilmgandhi | 18:6a4db94011d3 | 116 | (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 117 | (+) FMC NORSRAM bank extended timing configuration using the function |
sahilmgandhi | 18:6a4db94011d3 | 118 | FMC_NORSRAM_Extended_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 119 | (+) FMC NORSRAM bank enable/disable write operation using the functions |
sahilmgandhi | 18:6a4db94011d3 | 120 | FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() |
sahilmgandhi | 18:6a4db94011d3 | 121 | |
sahilmgandhi | 18:6a4db94011d3 | 122 | |
sahilmgandhi | 18:6a4db94011d3 | 123 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 124 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 125 | */ |
sahilmgandhi | 18:6a4db94011d3 | 126 | |
sahilmgandhi | 18:6a4db94011d3 | 127 | /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1 |
sahilmgandhi | 18:6a4db94011d3 | 128 | * @brief Initialization and Configuration functions |
sahilmgandhi | 18:6a4db94011d3 | 129 | * |
sahilmgandhi | 18:6a4db94011d3 | 130 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 131 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 132 | ##### Initialization and de_initialization functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 133 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 134 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 135 | This section provides functions allowing to: |
sahilmgandhi | 18:6a4db94011d3 | 136 | (+) Initialize and configure the FMC NORSRAM interface |
sahilmgandhi | 18:6a4db94011d3 | 137 | (+) De-initialize the FMC NORSRAM interface |
sahilmgandhi | 18:6a4db94011d3 | 138 | (+) Configure the FMC clock and associated GPIOs |
sahilmgandhi | 18:6a4db94011d3 | 139 | |
sahilmgandhi | 18:6a4db94011d3 | 140 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 141 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 142 | */ |
sahilmgandhi | 18:6a4db94011d3 | 143 | |
sahilmgandhi | 18:6a4db94011d3 | 144 | /** |
sahilmgandhi | 18:6a4db94011d3 | 145 | * @brief Initialize the FMC_NORSRAM device according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 146 | * control parameters in the FMC_NORSRAM_InitTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 147 | * @param Device: Pointer to NORSRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 148 | * @param Init: Pointer to NORSRAM Initialization structure |
sahilmgandhi | 18:6a4db94011d3 | 149 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 150 | */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) |
sahilmgandhi | 18:6a4db94011d3 | 152 | { |
sahilmgandhi | 18:6a4db94011d3 | 153 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 154 | |
sahilmgandhi | 18:6a4db94011d3 | 155 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 156 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 157 | assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); |
sahilmgandhi | 18:6a4db94011d3 | 158 | assert_param(IS_FMC_MUX(Init->DataAddressMux)); |
sahilmgandhi | 18:6a4db94011d3 | 159 | assert_param(IS_FMC_MEMORY(Init->MemoryType)); |
sahilmgandhi | 18:6a4db94011d3 | 160 | assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
sahilmgandhi | 18:6a4db94011d3 | 161 | assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); |
sahilmgandhi | 18:6a4db94011d3 | 162 | assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
sahilmgandhi | 18:6a4db94011d3 | 163 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
sahilmgandhi | 18:6a4db94011d3 | 164 | assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); |
sahilmgandhi | 18:6a4db94011d3 | 165 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
sahilmgandhi | 18:6a4db94011d3 | 166 | assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
sahilmgandhi | 18:6a4db94011d3 | 167 | assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); |
sahilmgandhi | 18:6a4db94011d3 | 168 | assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); |
sahilmgandhi | 18:6a4db94011d3 | 169 | assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); |
sahilmgandhi | 18:6a4db94011d3 | 170 | assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); |
sahilmgandhi | 18:6a4db94011d3 | 171 | assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); |
sahilmgandhi | 18:6a4db94011d3 | 172 | assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); |
sahilmgandhi | 18:6a4db94011d3 | 173 | assert_param(IS_FMC_PAGESIZE(Init->PageSize)); |
sahilmgandhi | 18:6a4db94011d3 | 174 | #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
sahilmgandhi | 18:6a4db94011d3 | 175 | assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); |
sahilmgandhi | 18:6a4db94011d3 | 176 | #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ |
sahilmgandhi | 18:6a4db94011d3 | 177 | |
sahilmgandhi | 18:6a4db94011d3 | 178 | /* Get the BTCR register value */ |
sahilmgandhi | 18:6a4db94011d3 | 179 | tmpr = Device->BTCR[Init->NSBank]; |
sahilmgandhi | 18:6a4db94011d3 | 180 | |
sahilmgandhi | 18:6a4db94011d3 | 181 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
sahilmgandhi | 18:6a4db94011d3 | 182 | /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, |
sahilmgandhi | 18:6a4db94011d3 | 183 | WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ |
sahilmgandhi | 18:6a4db94011d3 | 185 | FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ |
sahilmgandhi | 18:6a4db94011d3 | 186 | FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \ |
sahilmgandhi | 18:6a4db94011d3 | 187 | FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ |
sahilmgandhi | 18:6a4db94011d3 | 188 | FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \ |
sahilmgandhi | 18:6a4db94011d3 | 189 | FMC_BCR1_CCLKEN)); |
sahilmgandhi | 18:6a4db94011d3 | 190 | |
sahilmgandhi | 18:6a4db94011d3 | 191 | /* Set NORSRAM device control parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | tmpr |= (uint32_t)(Init->DataAddressMux |\ |
sahilmgandhi | 18:6a4db94011d3 | 193 | Init->MemoryType |\ |
sahilmgandhi | 18:6a4db94011d3 | 194 | Init->MemoryDataWidth |\ |
sahilmgandhi | 18:6a4db94011d3 | 195 | Init->BurstAccessMode |\ |
sahilmgandhi | 18:6a4db94011d3 | 196 | Init->WaitSignalPolarity |\ |
sahilmgandhi | 18:6a4db94011d3 | 197 | Init->WrapMode |\ |
sahilmgandhi | 18:6a4db94011d3 | 198 | Init->WaitSignalActive |\ |
sahilmgandhi | 18:6a4db94011d3 | 199 | Init->WriteOperation |\ |
sahilmgandhi | 18:6a4db94011d3 | 200 | Init->WaitSignal |\ |
sahilmgandhi | 18:6a4db94011d3 | 201 | Init->ExtendedMode |\ |
sahilmgandhi | 18:6a4db94011d3 | 202 | Init->AsynchronousWait |\ |
sahilmgandhi | 18:6a4db94011d3 | 203 | Init->PageSize |\ |
sahilmgandhi | 18:6a4db94011d3 | 204 | Init->WriteBurst |\ |
sahilmgandhi | 18:6a4db94011d3 | 205 | Init->ContinuousClock); |
sahilmgandhi | 18:6a4db94011d3 | 206 | #else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN, |
sahilmgandhi | 18:6a4db94011d3 | 208 | WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */ |
sahilmgandhi | 18:6a4db94011d3 | 209 | tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ |
sahilmgandhi | 18:6a4db94011d3 | 210 | FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ |
sahilmgandhi | 18:6a4db94011d3 | 211 | FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \ |
sahilmgandhi | 18:6a4db94011d3 | 212 | FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ |
sahilmgandhi | 18:6a4db94011d3 | 213 | FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \ |
sahilmgandhi | 18:6a4db94011d3 | 214 | FMC_BCR1_WFDIS)); |
sahilmgandhi | 18:6a4db94011d3 | 215 | |
sahilmgandhi | 18:6a4db94011d3 | 216 | /* Set NORSRAM device control parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 217 | tmpr |= (uint32_t)(Init->DataAddressMux |\ |
sahilmgandhi | 18:6a4db94011d3 | 218 | Init->MemoryType |\ |
sahilmgandhi | 18:6a4db94011d3 | 219 | Init->MemoryDataWidth |\ |
sahilmgandhi | 18:6a4db94011d3 | 220 | Init->BurstAccessMode |\ |
sahilmgandhi | 18:6a4db94011d3 | 221 | Init->WaitSignalPolarity |\ |
sahilmgandhi | 18:6a4db94011d3 | 222 | Init->WaitSignalActive |\ |
sahilmgandhi | 18:6a4db94011d3 | 223 | Init->WriteOperation |\ |
sahilmgandhi | 18:6a4db94011d3 | 224 | Init->WaitSignal |\ |
sahilmgandhi | 18:6a4db94011d3 | 225 | Init->ExtendedMode |\ |
sahilmgandhi | 18:6a4db94011d3 | 226 | Init->AsynchronousWait |\ |
sahilmgandhi | 18:6a4db94011d3 | 227 | Init->WriteBurst |\ |
sahilmgandhi | 18:6a4db94011d3 | 228 | Init->ContinuousClock |\ |
sahilmgandhi | 18:6a4db94011d3 | 229 | Init->PageSize |\ |
sahilmgandhi | 18:6a4db94011d3 | 230 | Init->WriteFifo); |
sahilmgandhi | 18:6a4db94011d3 | 231 | #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ |
sahilmgandhi | 18:6a4db94011d3 | 232 | |
sahilmgandhi | 18:6a4db94011d3 | 233 | if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) |
sahilmgandhi | 18:6a4db94011d3 | 234 | { |
sahilmgandhi | 18:6a4db94011d3 | 235 | tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 236 | } |
sahilmgandhi | 18:6a4db94011d3 | 237 | |
sahilmgandhi | 18:6a4db94011d3 | 238 | Device->BTCR[Init->NSBank] = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 239 | |
sahilmgandhi | 18:6a4db94011d3 | 240 | /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ |
sahilmgandhi | 18:6a4db94011d3 | 241 | if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) |
sahilmgandhi | 18:6a4db94011d3 | 242 | { |
sahilmgandhi | 18:6a4db94011d3 | 243 | Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); |
sahilmgandhi | 18:6a4db94011d3 | 244 | } |
sahilmgandhi | 18:6a4db94011d3 | 245 | |
sahilmgandhi | 18:6a4db94011d3 | 246 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
sahilmgandhi | 18:6a4db94011d3 | 247 | if(Init->NSBank != FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 248 | { |
sahilmgandhi | 18:6a4db94011d3 | 249 | Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); |
sahilmgandhi | 18:6a4db94011d3 | 250 | } |
sahilmgandhi | 18:6a4db94011d3 | 251 | #endif /* STM32F446xx || STM32F469xx || STM32F479xx */ |
sahilmgandhi | 18:6a4db94011d3 | 252 | |
sahilmgandhi | 18:6a4db94011d3 | 253 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 254 | } |
sahilmgandhi | 18:6a4db94011d3 | 255 | |
sahilmgandhi | 18:6a4db94011d3 | 256 | /** |
sahilmgandhi | 18:6a4db94011d3 | 257 | * @brief DeInitialize the FMC_NORSRAM peripheral |
sahilmgandhi | 18:6a4db94011d3 | 258 | * @param Device: Pointer to NORSRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 259 | * @param ExDevice: Pointer to NORSRAM extended mode device instance |
sahilmgandhi | 18:6a4db94011d3 | 260 | * @param Bank: NORSRAM bank number |
sahilmgandhi | 18:6a4db94011d3 | 261 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 262 | */ |
sahilmgandhi | 18:6a4db94011d3 | 263 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 264 | { |
sahilmgandhi | 18:6a4db94011d3 | 265 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 266 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 267 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
sahilmgandhi | 18:6a4db94011d3 | 268 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 269 | |
sahilmgandhi | 18:6a4db94011d3 | 270 | /* Disable the FMC_NORSRAM device */ |
sahilmgandhi | 18:6a4db94011d3 | 271 | __FMC_NORSRAM_DISABLE(Device, Bank); |
sahilmgandhi | 18:6a4db94011d3 | 272 | |
sahilmgandhi | 18:6a4db94011d3 | 273 | /* De-initialize the FMC_NORSRAM device */ |
sahilmgandhi | 18:6a4db94011d3 | 274 | /* FMC_NORSRAM_BANK1 */ |
sahilmgandhi | 18:6a4db94011d3 | 275 | if(Bank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 276 | { |
sahilmgandhi | 18:6a4db94011d3 | 277 | Device->BTCR[Bank] = 0x000030DBU; |
sahilmgandhi | 18:6a4db94011d3 | 278 | } |
sahilmgandhi | 18:6a4db94011d3 | 279 | /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 280 | else |
sahilmgandhi | 18:6a4db94011d3 | 281 | { |
sahilmgandhi | 18:6a4db94011d3 | 282 | Device->BTCR[Bank] = 0x000030D2U; |
sahilmgandhi | 18:6a4db94011d3 | 283 | } |
sahilmgandhi | 18:6a4db94011d3 | 284 | |
sahilmgandhi | 18:6a4db94011d3 | 285 | Device->BTCR[Bank + 1] = 0x0FFFFFFFU; |
sahilmgandhi | 18:6a4db94011d3 | 286 | ExDevice->BWTR[Bank] = 0x0FFFFFFFU; |
sahilmgandhi | 18:6a4db94011d3 | 287 | |
sahilmgandhi | 18:6a4db94011d3 | 288 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 289 | } |
sahilmgandhi | 18:6a4db94011d3 | 290 | |
sahilmgandhi | 18:6a4db94011d3 | 291 | /** |
sahilmgandhi | 18:6a4db94011d3 | 292 | * @brief Initialize the FMC_NORSRAM Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 293 | * parameters in the FMC_NORSRAM_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 294 | * @param Device: Pointer to NORSRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 295 | * @param Timing: Pointer to NORSRAM Timing structure |
sahilmgandhi | 18:6a4db94011d3 | 296 | * @param Bank: NORSRAM bank number |
sahilmgandhi | 18:6a4db94011d3 | 297 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 298 | */ |
sahilmgandhi | 18:6a4db94011d3 | 299 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 300 | { |
sahilmgandhi | 18:6a4db94011d3 | 301 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 302 | |
sahilmgandhi | 18:6a4db94011d3 | 303 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 304 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 305 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 306 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
sahilmgandhi | 18:6a4db94011d3 | 307 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 308 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
sahilmgandhi | 18:6a4db94011d3 | 309 | assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
sahilmgandhi | 18:6a4db94011d3 | 310 | assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
sahilmgandhi | 18:6a4db94011d3 | 311 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
sahilmgandhi | 18:6a4db94011d3 | 312 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 313 | |
sahilmgandhi | 18:6a4db94011d3 | 314 | /* Get the BTCR register value */ |
sahilmgandhi | 18:6a4db94011d3 | 315 | tmpr = Device->BTCR[Bank + 1U]; |
sahilmgandhi | 18:6a4db94011d3 | 316 | |
sahilmgandhi | 18:6a4db94011d3 | 317 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ |
sahilmgandhi | 18:6a4db94011d3 | 318 | tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ |
sahilmgandhi | 18:6a4db94011d3 | 319 | FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ |
sahilmgandhi | 18:6a4db94011d3 | 320 | FMC_BTR1_ACCMOD)); |
sahilmgandhi | 18:6a4db94011d3 | 321 | |
sahilmgandhi | 18:6a4db94011d3 | 322 | /* Set FMC_NORSRAM device timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 324 | ((Timing->AddressHoldTime) << 4U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 325 | ((Timing->DataSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 326 | ((Timing->BusTurnAroundDuration) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 327 | (((Timing->CLKDivision) - 1U) << 20U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 328 | (((Timing->DataLatency) - 2U) << 24U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 329 | (Timing->AccessMode)); |
sahilmgandhi | 18:6a4db94011d3 | 330 | |
sahilmgandhi | 18:6a4db94011d3 | 331 | Device->BTCR[Bank + 1U] = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 332 | |
sahilmgandhi | 18:6a4db94011d3 | 333 | /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ |
sahilmgandhi | 18:6a4db94011d3 | 334 | if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) |
sahilmgandhi | 18:6a4db94011d3 | 335 | { |
sahilmgandhi | 18:6a4db94011d3 | 336 | tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0FU) << 20U)); |
sahilmgandhi | 18:6a4db94011d3 | 337 | tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U); |
sahilmgandhi | 18:6a4db94011d3 | 338 | Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 339 | } |
sahilmgandhi | 18:6a4db94011d3 | 340 | |
sahilmgandhi | 18:6a4db94011d3 | 341 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 342 | } |
sahilmgandhi | 18:6a4db94011d3 | 343 | |
sahilmgandhi | 18:6a4db94011d3 | 344 | /** |
sahilmgandhi | 18:6a4db94011d3 | 345 | * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 346 | * parameters in the FMC_NORSRAM_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 347 | * @param Device: Pointer to NORSRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 348 | * @param Timing: Pointer to NORSRAM Timing structure |
sahilmgandhi | 18:6a4db94011d3 | 349 | * @param Bank: NORSRAM bank number |
sahilmgandhi | 18:6a4db94011d3 | 350 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 351 | */ |
sahilmgandhi | 18:6a4db94011d3 | 352 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
sahilmgandhi | 18:6a4db94011d3 | 353 | { |
sahilmgandhi | 18:6a4db94011d3 | 354 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 355 | |
sahilmgandhi | 18:6a4db94011d3 | 356 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 357 | assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); |
sahilmgandhi | 18:6a4db94011d3 | 358 | |
sahilmgandhi | 18:6a4db94011d3 | 359 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
sahilmgandhi | 18:6a4db94011d3 | 360 | if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) |
sahilmgandhi | 18:6a4db94011d3 | 361 | { |
sahilmgandhi | 18:6a4db94011d3 | 362 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 363 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 364 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 365 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
sahilmgandhi | 18:6a4db94011d3 | 366 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 367 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
sahilmgandhi | 18:6a4db94011d3 | 368 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
sahilmgandhi | 18:6a4db94011d3 | 369 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 370 | |
sahilmgandhi | 18:6a4db94011d3 | 371 | /* Get the BWTR register value */ |
sahilmgandhi | 18:6a4db94011d3 | 372 | tmpr = Device->BWTR[Bank]; |
sahilmgandhi | 18:6a4db94011d3 | 373 | |
sahilmgandhi | 18:6a4db94011d3 | 374 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ |
sahilmgandhi | 18:6a4db94011d3 | 375 | tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ |
sahilmgandhi | 18:6a4db94011d3 | 376 | FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); |
sahilmgandhi | 18:6a4db94011d3 | 377 | |
sahilmgandhi | 18:6a4db94011d3 | 378 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 379 | ((Timing->AddressHoldTime) << 4U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 380 | ((Timing->DataSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 381 | ((Timing->BusTurnAroundDuration) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 382 | (Timing->AccessMode)); |
sahilmgandhi | 18:6a4db94011d3 | 383 | |
sahilmgandhi | 18:6a4db94011d3 | 384 | Device->BWTR[Bank] = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 385 | } |
sahilmgandhi | 18:6a4db94011d3 | 386 | else |
sahilmgandhi | 18:6a4db94011d3 | 387 | { |
sahilmgandhi | 18:6a4db94011d3 | 388 | Device->BWTR[Bank] = 0x0FFFFFFFU; |
sahilmgandhi | 18:6a4db94011d3 | 389 | } |
sahilmgandhi | 18:6a4db94011d3 | 390 | |
sahilmgandhi | 18:6a4db94011d3 | 391 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 392 | } |
sahilmgandhi | 18:6a4db94011d3 | 393 | /** |
sahilmgandhi | 18:6a4db94011d3 | 394 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 395 | */ |
sahilmgandhi | 18:6a4db94011d3 | 396 | |
sahilmgandhi | 18:6a4db94011d3 | 397 | /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 |
sahilmgandhi | 18:6a4db94011d3 | 398 | * @brief management functions |
sahilmgandhi | 18:6a4db94011d3 | 399 | * |
sahilmgandhi | 18:6a4db94011d3 | 400 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 401 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 402 | ##### FMC_NORSRAM Control functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 403 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 404 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 405 | This subsection provides a set of functions allowing to control dynamically |
sahilmgandhi | 18:6a4db94011d3 | 406 | the FMC NORSRAM interface. |
sahilmgandhi | 18:6a4db94011d3 | 407 | |
sahilmgandhi | 18:6a4db94011d3 | 408 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 409 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 410 | */ |
sahilmgandhi | 18:6a4db94011d3 | 411 | /** |
sahilmgandhi | 18:6a4db94011d3 | 412 | * @brief Enables dynamically FMC_NORSRAM write operation. |
sahilmgandhi | 18:6a4db94011d3 | 413 | * @param Device: Pointer to NORSRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 414 | * @param Bank: NORSRAM bank number |
sahilmgandhi | 18:6a4db94011d3 | 415 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 416 | */ |
sahilmgandhi | 18:6a4db94011d3 | 417 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 418 | { |
sahilmgandhi | 18:6a4db94011d3 | 419 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 420 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 421 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 422 | |
sahilmgandhi | 18:6a4db94011d3 | 423 | /* Enable write operation */ |
sahilmgandhi | 18:6a4db94011d3 | 424 | Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 425 | |
sahilmgandhi | 18:6a4db94011d3 | 426 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 427 | } |
sahilmgandhi | 18:6a4db94011d3 | 428 | |
sahilmgandhi | 18:6a4db94011d3 | 429 | /** |
sahilmgandhi | 18:6a4db94011d3 | 430 | * @brief Disables dynamically FMC_NORSRAM write operation. |
sahilmgandhi | 18:6a4db94011d3 | 431 | * @param Device: Pointer to NORSRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 432 | * @param Bank: NORSRAM bank number |
sahilmgandhi | 18:6a4db94011d3 | 433 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 434 | */ |
sahilmgandhi | 18:6a4db94011d3 | 435 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 436 | { |
sahilmgandhi | 18:6a4db94011d3 | 437 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 438 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 439 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 440 | |
sahilmgandhi | 18:6a4db94011d3 | 441 | /* Disable write operation */ |
sahilmgandhi | 18:6a4db94011d3 | 442 | Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 443 | |
sahilmgandhi | 18:6a4db94011d3 | 444 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 445 | } |
sahilmgandhi | 18:6a4db94011d3 | 446 | |
sahilmgandhi | 18:6a4db94011d3 | 447 | /** |
sahilmgandhi | 18:6a4db94011d3 | 448 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 449 | */ |
sahilmgandhi | 18:6a4db94011d3 | 450 | |
sahilmgandhi | 18:6a4db94011d3 | 451 | /** |
sahilmgandhi | 18:6a4db94011d3 | 452 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 453 | */ |
sahilmgandhi | 18:6a4db94011d3 | 454 | |
sahilmgandhi | 18:6a4db94011d3 | 455 | /** @addtogroup FMC_LL_NAND |
sahilmgandhi | 18:6a4db94011d3 | 456 | * @brief NAND Controller functions |
sahilmgandhi | 18:6a4db94011d3 | 457 | * |
sahilmgandhi | 18:6a4db94011d3 | 458 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 459 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 460 | ##### How to use NAND device driver ##### |
sahilmgandhi | 18:6a4db94011d3 | 461 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 462 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 463 | This driver contains a set of APIs to interface with the FMC NAND banks in order |
sahilmgandhi | 18:6a4db94011d3 | 464 | to run the NAND external devices. |
sahilmgandhi | 18:6a4db94011d3 | 465 | |
sahilmgandhi | 18:6a4db94011d3 | 466 | (+) FMC NAND bank reset using the function FMC_NAND_DeInit() |
sahilmgandhi | 18:6a4db94011d3 | 467 | (+) FMC NAND bank control configuration using the function FMC_NAND_Init() |
sahilmgandhi | 18:6a4db94011d3 | 468 | (+) FMC NAND bank common space timing configuration using the function |
sahilmgandhi | 18:6a4db94011d3 | 469 | FMC_NAND_CommonSpace_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 470 | (+) FMC NAND bank attribute space timing configuration using the function |
sahilmgandhi | 18:6a4db94011d3 | 471 | FMC_NAND_AttributeSpace_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 472 | (+) FMC NAND bank enable/disable ECC correction feature using the functions |
sahilmgandhi | 18:6a4db94011d3 | 473 | FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() |
sahilmgandhi | 18:6a4db94011d3 | 474 | (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() |
sahilmgandhi | 18:6a4db94011d3 | 475 | |
sahilmgandhi | 18:6a4db94011d3 | 476 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 477 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 478 | */ |
sahilmgandhi | 18:6a4db94011d3 | 479 | |
sahilmgandhi | 18:6a4db94011d3 | 480 | #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
sahilmgandhi | 18:6a4db94011d3 | 481 | /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions |
sahilmgandhi | 18:6a4db94011d3 | 482 | * @brief Initialization and Configuration functions |
sahilmgandhi | 18:6a4db94011d3 | 483 | * |
sahilmgandhi | 18:6a4db94011d3 | 484 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 485 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 486 | ##### Initialization and de_initialization functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 487 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 488 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 489 | This section provides functions allowing to: |
sahilmgandhi | 18:6a4db94011d3 | 490 | (+) Initialize and configure the FMC NAND interface |
sahilmgandhi | 18:6a4db94011d3 | 491 | (+) De-initialize the FMC NAND interface |
sahilmgandhi | 18:6a4db94011d3 | 492 | (+) Configure the FMC clock and associated GPIOs |
sahilmgandhi | 18:6a4db94011d3 | 493 | |
sahilmgandhi | 18:6a4db94011d3 | 494 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 495 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 496 | */ |
sahilmgandhi | 18:6a4db94011d3 | 497 | |
sahilmgandhi | 18:6a4db94011d3 | 498 | /** |
sahilmgandhi | 18:6a4db94011d3 | 499 | * @brief Initializes the FMC_NAND device according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 500 | * control parameters in the FMC_NAND_HandleTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 501 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 502 | * @param Init: Pointer to NAND Initialization structure |
sahilmgandhi | 18:6a4db94011d3 | 503 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 504 | */ |
sahilmgandhi | 18:6a4db94011d3 | 505 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
sahilmgandhi | 18:6a4db94011d3 | 506 | { |
sahilmgandhi | 18:6a4db94011d3 | 507 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 508 | |
sahilmgandhi | 18:6a4db94011d3 | 509 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 510 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 511 | assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
sahilmgandhi | 18:6a4db94011d3 | 512 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
sahilmgandhi | 18:6a4db94011d3 | 513 | assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
sahilmgandhi | 18:6a4db94011d3 | 514 | assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
sahilmgandhi | 18:6a4db94011d3 | 515 | assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
sahilmgandhi | 18:6a4db94011d3 | 516 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 517 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 518 | |
sahilmgandhi | 18:6a4db94011d3 | 519 | /* Get the NAND bank register value */ |
sahilmgandhi | 18:6a4db94011d3 | 520 | tmpr = Device->PCR; |
sahilmgandhi | 18:6a4db94011d3 | 521 | |
sahilmgandhi | 18:6a4db94011d3 | 522 | /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ |
sahilmgandhi | 18:6a4db94011d3 | 523 | tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ |
sahilmgandhi | 18:6a4db94011d3 | 524 | FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ |
sahilmgandhi | 18:6a4db94011d3 | 525 | FMC_PCR_TAR | FMC_PCR_ECCPS)); |
sahilmgandhi | 18:6a4db94011d3 | 526 | |
sahilmgandhi | 18:6a4db94011d3 | 527 | /* Set NAND device control parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 528 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
sahilmgandhi | 18:6a4db94011d3 | 529 | FMC_PCR_MEMORY_TYPE_NAND |\ |
sahilmgandhi | 18:6a4db94011d3 | 530 | Init->MemoryDataWidth |\ |
sahilmgandhi | 18:6a4db94011d3 | 531 | Init->EccComputation |\ |
sahilmgandhi | 18:6a4db94011d3 | 532 | Init->ECCPageSize |\ |
sahilmgandhi | 18:6a4db94011d3 | 533 | ((Init->TCLRSetupTime) << 9U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 534 | ((Init->TARSetupTime) << 13U)); |
sahilmgandhi | 18:6a4db94011d3 | 535 | |
sahilmgandhi | 18:6a4db94011d3 | 536 | /* NAND bank registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 537 | Device->PCR = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 538 | |
sahilmgandhi | 18:6a4db94011d3 | 539 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 540 | } |
sahilmgandhi | 18:6a4db94011d3 | 541 | |
sahilmgandhi | 18:6a4db94011d3 | 542 | /** |
sahilmgandhi | 18:6a4db94011d3 | 543 | * @brief Initializes the FMC_NAND Common space Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 544 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 545 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 546 | * @param Timing: Pointer to NAND timing structure |
sahilmgandhi | 18:6a4db94011d3 | 547 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 548 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 549 | */ |
sahilmgandhi | 18:6a4db94011d3 | 550 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 551 | { |
sahilmgandhi | 18:6a4db94011d3 | 552 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 553 | |
sahilmgandhi | 18:6a4db94011d3 | 554 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 555 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 556 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 557 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 558 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 559 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 560 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 561 | |
sahilmgandhi | 18:6a4db94011d3 | 562 | /* Get the NAND bank 2 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 563 | tmpr = Device->PMEM; |
sahilmgandhi | 18:6a4db94011d3 | 564 | |
sahilmgandhi | 18:6a4db94011d3 | 565 | |
sahilmgandhi | 18:6a4db94011d3 | 566 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
sahilmgandhi | 18:6a4db94011d3 | 567 | tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \ |
sahilmgandhi | 18:6a4db94011d3 | 568 | FMC_PMEM_MEMHIZ2)); |
sahilmgandhi | 18:6a4db94011d3 | 569 | |
sahilmgandhi | 18:6a4db94011d3 | 570 | /* Set FMC_NAND device timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 571 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 572 | ((Timing->WaitSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 573 | ((Timing->HoldSetupTime) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 574 | ((Timing->HiZSetupTime) << 24U) |
sahilmgandhi | 18:6a4db94011d3 | 575 | ); |
sahilmgandhi | 18:6a4db94011d3 | 576 | |
sahilmgandhi | 18:6a4db94011d3 | 577 | /* NAND bank registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 578 | Device->PMEM = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 579 | |
sahilmgandhi | 18:6a4db94011d3 | 580 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 581 | } |
sahilmgandhi | 18:6a4db94011d3 | 582 | |
sahilmgandhi | 18:6a4db94011d3 | 583 | /** |
sahilmgandhi | 18:6a4db94011d3 | 584 | * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 585 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 586 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 587 | * @param Timing: Pointer to NAND timing structure |
sahilmgandhi | 18:6a4db94011d3 | 588 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 589 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 590 | */ |
sahilmgandhi | 18:6a4db94011d3 | 591 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 592 | { |
sahilmgandhi | 18:6a4db94011d3 | 593 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 594 | |
sahilmgandhi | 18:6a4db94011d3 | 595 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 596 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 597 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 598 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 599 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 600 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 601 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 602 | |
sahilmgandhi | 18:6a4db94011d3 | 603 | /* Get the NAND bank register value */ |
sahilmgandhi | 18:6a4db94011d3 | 604 | tmpr = Device->PATT; |
sahilmgandhi | 18:6a4db94011d3 | 605 | |
sahilmgandhi | 18:6a4db94011d3 | 606 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
sahilmgandhi | 18:6a4db94011d3 | 607 | tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \ |
sahilmgandhi | 18:6a4db94011d3 | 608 | FMC_PATT_ATTHIZ2)); |
sahilmgandhi | 18:6a4db94011d3 | 609 | |
sahilmgandhi | 18:6a4db94011d3 | 610 | /* Set FMC_NAND device timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 611 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 612 | ((Timing->WaitSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 613 | ((Timing->HoldSetupTime) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 614 | ((Timing->HiZSetupTime) << 24U)); |
sahilmgandhi | 18:6a4db94011d3 | 615 | |
sahilmgandhi | 18:6a4db94011d3 | 616 | /* NAND bank registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 617 | Device->PATT = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 618 | |
sahilmgandhi | 18:6a4db94011d3 | 619 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 620 | } |
sahilmgandhi | 18:6a4db94011d3 | 621 | |
sahilmgandhi | 18:6a4db94011d3 | 622 | |
sahilmgandhi | 18:6a4db94011d3 | 623 | /** |
sahilmgandhi | 18:6a4db94011d3 | 624 | * @brief DeInitializes the FMC_NAND device |
sahilmgandhi | 18:6a4db94011d3 | 625 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 626 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 627 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 628 | */ |
sahilmgandhi | 18:6a4db94011d3 | 629 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 630 | { |
sahilmgandhi | 18:6a4db94011d3 | 631 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 632 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 633 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 634 | |
sahilmgandhi | 18:6a4db94011d3 | 635 | /* Disable the NAND Bank */ |
sahilmgandhi | 18:6a4db94011d3 | 636 | __FMC_NAND_DISABLE(Device, Bank); |
sahilmgandhi | 18:6a4db94011d3 | 637 | |
sahilmgandhi | 18:6a4db94011d3 | 638 | /* De-initialize the NAND Bank */ |
sahilmgandhi | 18:6a4db94011d3 | 639 | /* Set the FMC_NAND_BANK registers to their reset values */ |
sahilmgandhi | 18:6a4db94011d3 | 640 | Device->PCR = 0x00000018U; |
sahilmgandhi | 18:6a4db94011d3 | 641 | Device->SR = 0x00000040U; |
sahilmgandhi | 18:6a4db94011d3 | 642 | Device->PMEM = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 643 | Device->PATT = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 644 | |
sahilmgandhi | 18:6a4db94011d3 | 645 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 646 | } |
sahilmgandhi | 18:6a4db94011d3 | 647 | |
sahilmgandhi | 18:6a4db94011d3 | 648 | /** |
sahilmgandhi | 18:6a4db94011d3 | 649 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 650 | */ |
sahilmgandhi | 18:6a4db94011d3 | 651 | |
sahilmgandhi | 18:6a4db94011d3 | 652 | |
sahilmgandhi | 18:6a4db94011d3 | 653 | /** @defgroup HAL_FMC_NAND_Group2 Control functions |
sahilmgandhi | 18:6a4db94011d3 | 654 | * @brief management functions |
sahilmgandhi | 18:6a4db94011d3 | 655 | * |
sahilmgandhi | 18:6a4db94011d3 | 656 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 657 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 658 | ##### FMC_NAND Control functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 659 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 660 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 661 | This subsection provides a set of functions allowing to control dynamically |
sahilmgandhi | 18:6a4db94011d3 | 662 | the FMC NAND interface. |
sahilmgandhi | 18:6a4db94011d3 | 663 | |
sahilmgandhi | 18:6a4db94011d3 | 664 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 665 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 666 | */ |
sahilmgandhi | 18:6a4db94011d3 | 667 | |
sahilmgandhi | 18:6a4db94011d3 | 668 | |
sahilmgandhi | 18:6a4db94011d3 | 669 | /** |
sahilmgandhi | 18:6a4db94011d3 | 670 | * @brief Enables dynamically FMC_NAND ECC feature. |
sahilmgandhi | 18:6a4db94011d3 | 671 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 672 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 673 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 674 | */ |
sahilmgandhi | 18:6a4db94011d3 | 675 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 676 | { |
sahilmgandhi | 18:6a4db94011d3 | 677 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 678 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 679 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 680 | |
sahilmgandhi | 18:6a4db94011d3 | 681 | /* Enable ECC feature */ |
sahilmgandhi | 18:6a4db94011d3 | 682 | Device->PCR |= FMC_PCR_ECCEN; |
sahilmgandhi | 18:6a4db94011d3 | 683 | |
sahilmgandhi | 18:6a4db94011d3 | 684 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 685 | } |
sahilmgandhi | 18:6a4db94011d3 | 686 | |
sahilmgandhi | 18:6a4db94011d3 | 687 | |
sahilmgandhi | 18:6a4db94011d3 | 688 | /** |
sahilmgandhi | 18:6a4db94011d3 | 689 | * @brief Disables dynamically FMC_NAND ECC feature. |
sahilmgandhi | 18:6a4db94011d3 | 690 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 691 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 692 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 693 | */ |
sahilmgandhi | 18:6a4db94011d3 | 694 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 695 | { |
sahilmgandhi | 18:6a4db94011d3 | 696 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 697 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 698 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 699 | |
sahilmgandhi | 18:6a4db94011d3 | 700 | /* Disable ECC feature */ |
sahilmgandhi | 18:6a4db94011d3 | 701 | Device->PCR &= ~FMC_PCR_ECCEN; |
sahilmgandhi | 18:6a4db94011d3 | 702 | |
sahilmgandhi | 18:6a4db94011d3 | 703 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 704 | } |
sahilmgandhi | 18:6a4db94011d3 | 705 | |
sahilmgandhi | 18:6a4db94011d3 | 706 | /** |
sahilmgandhi | 18:6a4db94011d3 | 707 | * @brief Disables dynamically FMC_NAND ECC feature. |
sahilmgandhi | 18:6a4db94011d3 | 708 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 709 | * @param ECCval: Pointer to ECC value |
sahilmgandhi | 18:6a4db94011d3 | 710 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 711 | * @param Timeout: Timeout wait value |
sahilmgandhi | 18:6a4db94011d3 | 712 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 713 | */ |
sahilmgandhi | 18:6a4db94011d3 | 714 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
sahilmgandhi | 18:6a4db94011d3 | 715 | { |
sahilmgandhi | 18:6a4db94011d3 | 716 | uint32_t tickstart = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 717 | |
sahilmgandhi | 18:6a4db94011d3 | 718 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 719 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 720 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 721 | |
sahilmgandhi | 18:6a4db94011d3 | 722 | /* Get tick */ |
sahilmgandhi | 18:6a4db94011d3 | 723 | tickstart = HAL_GetTick(); |
sahilmgandhi | 18:6a4db94011d3 | 724 | |
sahilmgandhi | 18:6a4db94011d3 | 725 | /* Wait until FIFO is empty */ |
sahilmgandhi | 18:6a4db94011d3 | 726 | while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 727 | { |
sahilmgandhi | 18:6a4db94011d3 | 728 | /* Check for the Timeout */ |
sahilmgandhi | 18:6a4db94011d3 | 729 | if(Timeout != HAL_MAX_DELAY) |
sahilmgandhi | 18:6a4db94011d3 | 730 | { |
sahilmgandhi | 18:6a4db94011d3 | 731 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
sahilmgandhi | 18:6a4db94011d3 | 732 | { |
sahilmgandhi | 18:6a4db94011d3 | 733 | return HAL_TIMEOUT; |
sahilmgandhi | 18:6a4db94011d3 | 734 | } |
sahilmgandhi | 18:6a4db94011d3 | 735 | } |
sahilmgandhi | 18:6a4db94011d3 | 736 | } |
sahilmgandhi | 18:6a4db94011d3 | 737 | |
sahilmgandhi | 18:6a4db94011d3 | 738 | /* Get the ECCR register value */ |
sahilmgandhi | 18:6a4db94011d3 | 739 | *ECCval = (uint32_t)Device->ECCR; |
sahilmgandhi | 18:6a4db94011d3 | 740 | |
sahilmgandhi | 18:6a4db94011d3 | 741 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 742 | } |
sahilmgandhi | 18:6a4db94011d3 | 743 | |
sahilmgandhi | 18:6a4db94011d3 | 744 | /** |
sahilmgandhi | 18:6a4db94011d3 | 745 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 746 | */ |
sahilmgandhi | 18:6a4db94011d3 | 747 | |
sahilmgandhi | 18:6a4db94011d3 | 748 | #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ |
sahilmgandhi | 18:6a4db94011d3 | 749 | /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions |
sahilmgandhi | 18:6a4db94011d3 | 750 | * @brief Initialization and Configuration functions |
sahilmgandhi | 18:6a4db94011d3 | 751 | * |
sahilmgandhi | 18:6a4db94011d3 | 752 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 753 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 754 | ##### Initialization and de_initialization functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 755 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 756 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 757 | This section provides functions allowing to: |
sahilmgandhi | 18:6a4db94011d3 | 758 | (+) Initialize and configure the FMC NAND interface |
sahilmgandhi | 18:6a4db94011d3 | 759 | (+) De-initialize the FMC NAND interface |
sahilmgandhi | 18:6a4db94011d3 | 760 | (+) Configure the FMC clock and associated GPIOs |
sahilmgandhi | 18:6a4db94011d3 | 761 | |
sahilmgandhi | 18:6a4db94011d3 | 762 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 763 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 764 | */ |
sahilmgandhi | 18:6a4db94011d3 | 765 | /** |
sahilmgandhi | 18:6a4db94011d3 | 766 | * @brief Initializes the FMC_NAND device according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 767 | * control parameters in the FMC_NAND_HandleTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 768 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 769 | * @param Init: Pointer to NAND Initialization structure |
sahilmgandhi | 18:6a4db94011d3 | 770 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 771 | */ |
sahilmgandhi | 18:6a4db94011d3 | 772 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
sahilmgandhi | 18:6a4db94011d3 | 773 | { |
sahilmgandhi | 18:6a4db94011d3 | 774 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 775 | |
sahilmgandhi | 18:6a4db94011d3 | 776 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 777 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 778 | assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
sahilmgandhi | 18:6a4db94011d3 | 779 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
sahilmgandhi | 18:6a4db94011d3 | 780 | assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
sahilmgandhi | 18:6a4db94011d3 | 781 | assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
sahilmgandhi | 18:6a4db94011d3 | 782 | assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
sahilmgandhi | 18:6a4db94011d3 | 783 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 784 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 785 | |
sahilmgandhi | 18:6a4db94011d3 | 786 | if(Init->NandBank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 787 | { |
sahilmgandhi | 18:6a4db94011d3 | 788 | /* Get the NAND bank 2 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 789 | tmpr = Device->PCR2; |
sahilmgandhi | 18:6a4db94011d3 | 790 | } |
sahilmgandhi | 18:6a4db94011d3 | 791 | else |
sahilmgandhi | 18:6a4db94011d3 | 792 | { |
sahilmgandhi | 18:6a4db94011d3 | 793 | /* Get the NAND bank 3 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 794 | tmpr = Device->PCR3; |
sahilmgandhi | 18:6a4db94011d3 | 795 | } |
sahilmgandhi | 18:6a4db94011d3 | 796 | |
sahilmgandhi | 18:6a4db94011d3 | 797 | /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ |
sahilmgandhi | 18:6a4db94011d3 | 798 | tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \ |
sahilmgandhi | 18:6a4db94011d3 | 799 | FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ |
sahilmgandhi | 18:6a4db94011d3 | 800 | FMC_PCR2_TAR | FMC_PCR2_ECCPS)); |
sahilmgandhi | 18:6a4db94011d3 | 801 | |
sahilmgandhi | 18:6a4db94011d3 | 802 | /* Set NAND device control parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 803 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
sahilmgandhi | 18:6a4db94011d3 | 804 | FMC_PCR_MEMORY_TYPE_NAND |\ |
sahilmgandhi | 18:6a4db94011d3 | 805 | Init->MemoryDataWidth |\ |
sahilmgandhi | 18:6a4db94011d3 | 806 | Init->EccComputation |\ |
sahilmgandhi | 18:6a4db94011d3 | 807 | Init->ECCPageSize |\ |
sahilmgandhi | 18:6a4db94011d3 | 808 | ((Init->TCLRSetupTime) << 9U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 809 | ((Init->TARSetupTime) << 13U)); |
sahilmgandhi | 18:6a4db94011d3 | 810 | |
sahilmgandhi | 18:6a4db94011d3 | 811 | if(Init->NandBank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 812 | { |
sahilmgandhi | 18:6a4db94011d3 | 813 | /* NAND bank 2 registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 814 | Device->PCR2 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 815 | } |
sahilmgandhi | 18:6a4db94011d3 | 816 | else |
sahilmgandhi | 18:6a4db94011d3 | 817 | { |
sahilmgandhi | 18:6a4db94011d3 | 818 | /* NAND bank 3 registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 819 | Device->PCR3 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 820 | } |
sahilmgandhi | 18:6a4db94011d3 | 821 | |
sahilmgandhi | 18:6a4db94011d3 | 822 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 823 | |
sahilmgandhi | 18:6a4db94011d3 | 824 | } |
sahilmgandhi | 18:6a4db94011d3 | 825 | |
sahilmgandhi | 18:6a4db94011d3 | 826 | /** |
sahilmgandhi | 18:6a4db94011d3 | 827 | * @brief Initializes the FMC_NAND Common space Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 828 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 829 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 830 | * @param Timing: Pointer to NAND timing structure |
sahilmgandhi | 18:6a4db94011d3 | 831 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 832 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 833 | */ |
sahilmgandhi | 18:6a4db94011d3 | 834 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 835 | { |
sahilmgandhi | 18:6a4db94011d3 | 836 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 837 | |
sahilmgandhi | 18:6a4db94011d3 | 838 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 839 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 840 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 841 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 842 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 843 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 844 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 845 | |
sahilmgandhi | 18:6a4db94011d3 | 846 | if(Bank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 847 | { |
sahilmgandhi | 18:6a4db94011d3 | 848 | /* Get the NAND bank 2 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 849 | tmpr = Device->PMEM2; |
sahilmgandhi | 18:6a4db94011d3 | 850 | } |
sahilmgandhi | 18:6a4db94011d3 | 851 | else |
sahilmgandhi | 18:6a4db94011d3 | 852 | { |
sahilmgandhi | 18:6a4db94011d3 | 853 | /* Get the NAND bank 3 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 854 | tmpr = Device->PMEM3; |
sahilmgandhi | 18:6a4db94011d3 | 855 | } |
sahilmgandhi | 18:6a4db94011d3 | 856 | |
sahilmgandhi | 18:6a4db94011d3 | 857 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
sahilmgandhi | 18:6a4db94011d3 | 858 | tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \ |
sahilmgandhi | 18:6a4db94011d3 | 859 | FMC_PMEM2_MEMHIZ2)); |
sahilmgandhi | 18:6a4db94011d3 | 860 | |
sahilmgandhi | 18:6a4db94011d3 | 861 | /* Set FMC_NAND device timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 862 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 863 | ((Timing->WaitSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 864 | ((Timing->HoldSetupTime) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 865 | ((Timing->HiZSetupTime) << 24U) |
sahilmgandhi | 18:6a4db94011d3 | 866 | ); |
sahilmgandhi | 18:6a4db94011d3 | 867 | |
sahilmgandhi | 18:6a4db94011d3 | 868 | if(Bank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 869 | { |
sahilmgandhi | 18:6a4db94011d3 | 870 | /* NAND bank 2 registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 871 | Device->PMEM2 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 872 | } |
sahilmgandhi | 18:6a4db94011d3 | 873 | else |
sahilmgandhi | 18:6a4db94011d3 | 874 | { |
sahilmgandhi | 18:6a4db94011d3 | 875 | /* NAND bank 3 registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 876 | Device->PMEM3 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 877 | } |
sahilmgandhi | 18:6a4db94011d3 | 878 | |
sahilmgandhi | 18:6a4db94011d3 | 879 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 880 | } |
sahilmgandhi | 18:6a4db94011d3 | 881 | |
sahilmgandhi | 18:6a4db94011d3 | 882 | /** |
sahilmgandhi | 18:6a4db94011d3 | 883 | * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 884 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 885 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 886 | * @param Timing: Pointer to NAND timing structure |
sahilmgandhi | 18:6a4db94011d3 | 887 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 888 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 889 | */ |
sahilmgandhi | 18:6a4db94011d3 | 890 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 891 | { |
sahilmgandhi | 18:6a4db94011d3 | 892 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 893 | |
sahilmgandhi | 18:6a4db94011d3 | 894 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 895 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 896 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 897 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 898 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 899 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 900 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 901 | |
sahilmgandhi | 18:6a4db94011d3 | 902 | if(Bank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 903 | { |
sahilmgandhi | 18:6a4db94011d3 | 904 | /* Get the NAND bank 2 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 905 | tmpr = Device->PATT2; |
sahilmgandhi | 18:6a4db94011d3 | 906 | } |
sahilmgandhi | 18:6a4db94011d3 | 907 | else |
sahilmgandhi | 18:6a4db94011d3 | 908 | { |
sahilmgandhi | 18:6a4db94011d3 | 909 | /* Get the NAND bank 3 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 910 | tmpr = Device->PATT3; |
sahilmgandhi | 18:6a4db94011d3 | 911 | } |
sahilmgandhi | 18:6a4db94011d3 | 912 | |
sahilmgandhi | 18:6a4db94011d3 | 913 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
sahilmgandhi | 18:6a4db94011d3 | 914 | tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \ |
sahilmgandhi | 18:6a4db94011d3 | 915 | FMC_PATT2_ATTHIZ2)); |
sahilmgandhi | 18:6a4db94011d3 | 916 | |
sahilmgandhi | 18:6a4db94011d3 | 917 | /* Set FMC_NAND device timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 918 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 919 | ((Timing->WaitSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 920 | ((Timing->HoldSetupTime) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 921 | ((Timing->HiZSetupTime) << 24U)); |
sahilmgandhi | 18:6a4db94011d3 | 922 | |
sahilmgandhi | 18:6a4db94011d3 | 923 | if(Bank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 924 | { |
sahilmgandhi | 18:6a4db94011d3 | 925 | /* NAND bank 2 registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 926 | Device->PATT2 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 927 | } |
sahilmgandhi | 18:6a4db94011d3 | 928 | else |
sahilmgandhi | 18:6a4db94011d3 | 929 | { |
sahilmgandhi | 18:6a4db94011d3 | 930 | /* NAND bank 3 registers configuration */ |
sahilmgandhi | 18:6a4db94011d3 | 931 | Device->PATT3 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 932 | } |
sahilmgandhi | 18:6a4db94011d3 | 933 | |
sahilmgandhi | 18:6a4db94011d3 | 934 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 935 | } |
sahilmgandhi | 18:6a4db94011d3 | 936 | |
sahilmgandhi | 18:6a4db94011d3 | 937 | /** |
sahilmgandhi | 18:6a4db94011d3 | 938 | * @brief DeInitializes the FMC_NAND device |
sahilmgandhi | 18:6a4db94011d3 | 939 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 940 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 941 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 942 | */ |
sahilmgandhi | 18:6a4db94011d3 | 943 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 944 | { |
sahilmgandhi | 18:6a4db94011d3 | 945 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 946 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 947 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 948 | |
sahilmgandhi | 18:6a4db94011d3 | 949 | /* Disable the NAND Bank */ |
sahilmgandhi | 18:6a4db94011d3 | 950 | __FMC_NAND_DISABLE(Device, Bank); |
sahilmgandhi | 18:6a4db94011d3 | 951 | |
sahilmgandhi | 18:6a4db94011d3 | 952 | /* De-initialize the NAND Bank */ |
sahilmgandhi | 18:6a4db94011d3 | 953 | if(Bank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 954 | { |
sahilmgandhi | 18:6a4db94011d3 | 955 | /* Set the FMC_NAND_BANK2 registers to their reset values */ |
sahilmgandhi | 18:6a4db94011d3 | 956 | Device->PCR2 = 0x00000018U; |
sahilmgandhi | 18:6a4db94011d3 | 957 | Device->SR2 = 0x00000040U; |
sahilmgandhi | 18:6a4db94011d3 | 958 | Device->PMEM2 = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 959 | Device->PATT2 = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 960 | } |
sahilmgandhi | 18:6a4db94011d3 | 961 | /* FMC_Bank3_NAND */ |
sahilmgandhi | 18:6a4db94011d3 | 962 | else |
sahilmgandhi | 18:6a4db94011d3 | 963 | { |
sahilmgandhi | 18:6a4db94011d3 | 964 | /* Set the FMC_NAND_BANK3 registers to their reset values */ |
sahilmgandhi | 18:6a4db94011d3 | 965 | Device->PCR3 = 0x00000018U; |
sahilmgandhi | 18:6a4db94011d3 | 966 | Device->SR3 = 0x00000040U; |
sahilmgandhi | 18:6a4db94011d3 | 967 | Device->PMEM3 = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 968 | Device->PATT3 = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 969 | } |
sahilmgandhi | 18:6a4db94011d3 | 970 | |
sahilmgandhi | 18:6a4db94011d3 | 971 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 972 | } |
sahilmgandhi | 18:6a4db94011d3 | 973 | |
sahilmgandhi | 18:6a4db94011d3 | 974 | /** |
sahilmgandhi | 18:6a4db94011d3 | 975 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 976 | */ |
sahilmgandhi | 18:6a4db94011d3 | 977 | |
sahilmgandhi | 18:6a4db94011d3 | 978 | /** @addtogroup FMC_LL_NAND_Private_Functions_Group2 |
sahilmgandhi | 18:6a4db94011d3 | 979 | * @brief management functions |
sahilmgandhi | 18:6a4db94011d3 | 980 | * |
sahilmgandhi | 18:6a4db94011d3 | 981 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 982 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 983 | ##### FMC_NAND Control functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 984 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 985 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 986 | This subsection provides a set of functions allowing to control dynamically |
sahilmgandhi | 18:6a4db94011d3 | 987 | the FMC NAND interface. |
sahilmgandhi | 18:6a4db94011d3 | 988 | |
sahilmgandhi | 18:6a4db94011d3 | 989 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 990 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 991 | */ |
sahilmgandhi | 18:6a4db94011d3 | 992 | /** |
sahilmgandhi | 18:6a4db94011d3 | 993 | * @brief Enables dynamically FMC_NAND ECC feature. |
sahilmgandhi | 18:6a4db94011d3 | 994 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 995 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 996 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 997 | */ |
sahilmgandhi | 18:6a4db94011d3 | 998 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 999 | { |
sahilmgandhi | 18:6a4db94011d3 | 1000 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1001 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1002 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 1003 | |
sahilmgandhi | 18:6a4db94011d3 | 1004 | /* Enable ECC feature */ |
sahilmgandhi | 18:6a4db94011d3 | 1005 | if(Bank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 1006 | { |
sahilmgandhi | 18:6a4db94011d3 | 1007 | Device->PCR2 |= FMC_PCR2_ECCEN; |
sahilmgandhi | 18:6a4db94011d3 | 1008 | } |
sahilmgandhi | 18:6a4db94011d3 | 1009 | else |
sahilmgandhi | 18:6a4db94011d3 | 1010 | { |
sahilmgandhi | 18:6a4db94011d3 | 1011 | Device->PCR3 |= FMC_PCR3_ECCEN; |
sahilmgandhi | 18:6a4db94011d3 | 1012 | } |
sahilmgandhi | 18:6a4db94011d3 | 1013 | |
sahilmgandhi | 18:6a4db94011d3 | 1014 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1015 | } |
sahilmgandhi | 18:6a4db94011d3 | 1016 | |
sahilmgandhi | 18:6a4db94011d3 | 1017 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1018 | * @brief Disables dynamically FMC_NAND ECC feature. |
sahilmgandhi | 18:6a4db94011d3 | 1019 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 1020 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 1021 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1022 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1023 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 1024 | { |
sahilmgandhi | 18:6a4db94011d3 | 1025 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1026 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1027 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 1028 | |
sahilmgandhi | 18:6a4db94011d3 | 1029 | /* Disable ECC feature */ |
sahilmgandhi | 18:6a4db94011d3 | 1030 | if(Bank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 1031 | { |
sahilmgandhi | 18:6a4db94011d3 | 1032 | Device->PCR2 &= ~FMC_PCR2_ECCEN; |
sahilmgandhi | 18:6a4db94011d3 | 1033 | } |
sahilmgandhi | 18:6a4db94011d3 | 1034 | else |
sahilmgandhi | 18:6a4db94011d3 | 1035 | { |
sahilmgandhi | 18:6a4db94011d3 | 1036 | Device->PCR3 &= ~FMC_PCR3_ECCEN; |
sahilmgandhi | 18:6a4db94011d3 | 1037 | } |
sahilmgandhi | 18:6a4db94011d3 | 1038 | |
sahilmgandhi | 18:6a4db94011d3 | 1039 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1040 | } |
sahilmgandhi | 18:6a4db94011d3 | 1041 | |
sahilmgandhi | 18:6a4db94011d3 | 1042 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1043 | * @brief Disables dynamically FMC_NAND ECC feature. |
sahilmgandhi | 18:6a4db94011d3 | 1044 | * @param Device: Pointer to NAND device instance |
sahilmgandhi | 18:6a4db94011d3 | 1045 | * @param ECCval: Pointer to ECC value |
sahilmgandhi | 18:6a4db94011d3 | 1046 | * @param Bank: NAND bank number |
sahilmgandhi | 18:6a4db94011d3 | 1047 | * @param Timeout: Timeout wait value |
sahilmgandhi | 18:6a4db94011d3 | 1048 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1049 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1050 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
sahilmgandhi | 18:6a4db94011d3 | 1051 | { |
sahilmgandhi | 18:6a4db94011d3 | 1052 | uint32_t tickstart = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1053 | |
sahilmgandhi | 18:6a4db94011d3 | 1054 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1055 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1056 | assert_param(IS_FMC_NAND_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 1057 | |
sahilmgandhi | 18:6a4db94011d3 | 1058 | /* Get tick */ |
sahilmgandhi | 18:6a4db94011d3 | 1059 | tickstart = HAL_GetTick(); |
sahilmgandhi | 18:6a4db94011d3 | 1060 | |
sahilmgandhi | 18:6a4db94011d3 | 1061 | /* Wait until FIFO is empty */ |
sahilmgandhi | 18:6a4db94011d3 | 1062 | while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
sahilmgandhi | 18:6a4db94011d3 | 1063 | { |
sahilmgandhi | 18:6a4db94011d3 | 1064 | /* Check for the Timeout */ |
sahilmgandhi | 18:6a4db94011d3 | 1065 | if(Timeout != HAL_MAX_DELAY) |
sahilmgandhi | 18:6a4db94011d3 | 1066 | { |
sahilmgandhi | 18:6a4db94011d3 | 1067 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
sahilmgandhi | 18:6a4db94011d3 | 1068 | { |
sahilmgandhi | 18:6a4db94011d3 | 1069 | return HAL_TIMEOUT; |
sahilmgandhi | 18:6a4db94011d3 | 1070 | } |
sahilmgandhi | 18:6a4db94011d3 | 1071 | } |
sahilmgandhi | 18:6a4db94011d3 | 1072 | } |
sahilmgandhi | 18:6a4db94011d3 | 1073 | |
sahilmgandhi | 18:6a4db94011d3 | 1074 | if(Bank == FMC_NAND_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 1075 | { |
sahilmgandhi | 18:6a4db94011d3 | 1076 | /* Get the ECCR2 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 1077 | *ECCval = (uint32_t)Device->ECCR2; |
sahilmgandhi | 18:6a4db94011d3 | 1078 | } |
sahilmgandhi | 18:6a4db94011d3 | 1079 | else |
sahilmgandhi | 18:6a4db94011d3 | 1080 | { |
sahilmgandhi | 18:6a4db94011d3 | 1081 | /* Get the ECCR3 register value */ |
sahilmgandhi | 18:6a4db94011d3 | 1082 | *ECCval = (uint32_t)Device->ECCR3; |
sahilmgandhi | 18:6a4db94011d3 | 1083 | } |
sahilmgandhi | 18:6a4db94011d3 | 1084 | |
sahilmgandhi | 18:6a4db94011d3 | 1085 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1086 | } |
sahilmgandhi | 18:6a4db94011d3 | 1087 | |
sahilmgandhi | 18:6a4db94011d3 | 1088 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1089 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1090 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1091 | |
sahilmgandhi | 18:6a4db94011d3 | 1092 | #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ |
sahilmgandhi | 18:6a4db94011d3 | 1093 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1094 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1095 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1096 | |
sahilmgandhi | 18:6a4db94011d3 | 1097 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
sahilmgandhi | 18:6a4db94011d3 | 1098 | /** @addtogroup FMC_LL_PCCARD |
sahilmgandhi | 18:6a4db94011d3 | 1099 | * @brief PCCARD Controller functions |
sahilmgandhi | 18:6a4db94011d3 | 1100 | * |
sahilmgandhi | 18:6a4db94011d3 | 1101 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 1102 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1103 | ##### How to use PCCARD device driver ##### |
sahilmgandhi | 18:6a4db94011d3 | 1104 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1105 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 1106 | This driver contains a set of APIs to interface with the FMC PCCARD bank in order |
sahilmgandhi | 18:6a4db94011d3 | 1107 | to run the PCCARD/compact flash external devices. |
sahilmgandhi | 18:6a4db94011d3 | 1108 | |
sahilmgandhi | 18:6a4db94011d3 | 1109 | (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit() |
sahilmgandhi | 18:6a4db94011d3 | 1110 | (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init() |
sahilmgandhi | 18:6a4db94011d3 | 1111 | (+) FMC PCCARD bank common space timing configuration using the function |
sahilmgandhi | 18:6a4db94011d3 | 1112 | FMC_PCCARD_CommonSpace_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 1113 | (+) FMC PCCARD bank attribute space timing configuration using the function |
sahilmgandhi | 18:6a4db94011d3 | 1114 | FMC_PCCARD_AttributeSpace_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 1115 | (+) FMC PCCARD bank IO space timing configuration using the function |
sahilmgandhi | 18:6a4db94011d3 | 1116 | FMC_PCCARD_IOSpace_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 1117 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 1118 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1119 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1120 | |
sahilmgandhi | 18:6a4db94011d3 | 1121 | /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1 |
sahilmgandhi | 18:6a4db94011d3 | 1122 | * @brief Initialization and Configuration functions |
sahilmgandhi | 18:6a4db94011d3 | 1123 | * |
sahilmgandhi | 18:6a4db94011d3 | 1124 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 1125 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1126 | ##### Initialization and de_initialization functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 1127 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1128 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 1129 | This section provides functions allowing to: |
sahilmgandhi | 18:6a4db94011d3 | 1130 | (+) Initialize and configure the FMC PCCARD interface |
sahilmgandhi | 18:6a4db94011d3 | 1131 | (+) De-initialize the FMC PCCARD interface |
sahilmgandhi | 18:6a4db94011d3 | 1132 | (+) Configure the FMC clock and associated GPIOs |
sahilmgandhi | 18:6a4db94011d3 | 1133 | |
sahilmgandhi | 18:6a4db94011d3 | 1134 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 1135 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1136 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1137 | |
sahilmgandhi | 18:6a4db94011d3 | 1138 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1139 | * @brief Initializes the FMC_PCCARD device according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 1140 | * control parameters in the FMC_PCCARD_HandleTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 1141 | * @param Device: Pointer to PCCARD device instance |
sahilmgandhi | 18:6a4db94011d3 | 1142 | * @param Init: Pointer to PCCARD Initialization structure |
sahilmgandhi | 18:6a4db94011d3 | 1143 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1144 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1145 | HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) |
sahilmgandhi | 18:6a4db94011d3 | 1146 | { |
sahilmgandhi | 18:6a4db94011d3 | 1147 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1148 | |
sahilmgandhi | 18:6a4db94011d3 | 1149 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1150 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1151 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
sahilmgandhi | 18:6a4db94011d3 | 1152 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1153 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1154 | |
sahilmgandhi | 18:6a4db94011d3 | 1155 | /* Get PCCARD control register value */ |
sahilmgandhi | 18:6a4db94011d3 | 1156 | tmpr = Device->PCR4; |
sahilmgandhi | 18:6a4db94011d3 | 1157 | |
sahilmgandhi | 18:6a4db94011d3 | 1158 | /* Clear TAR, TCLR, PWAITEN and PWID bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1159 | tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ |
sahilmgandhi | 18:6a4db94011d3 | 1160 | FMC_PCR4_PWID)); |
sahilmgandhi | 18:6a4db94011d3 | 1161 | |
sahilmgandhi | 18:6a4db94011d3 | 1162 | /* Set FMC_PCCARD device control parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1163 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
sahilmgandhi | 18:6a4db94011d3 | 1164 | FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ |
sahilmgandhi | 18:6a4db94011d3 | 1165 | (Init->TCLRSetupTime << 9U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1166 | (Init->TARSetupTime << 13U)); |
sahilmgandhi | 18:6a4db94011d3 | 1167 | |
sahilmgandhi | 18:6a4db94011d3 | 1168 | Device->PCR4 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 1169 | |
sahilmgandhi | 18:6a4db94011d3 | 1170 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1171 | } |
sahilmgandhi | 18:6a4db94011d3 | 1172 | |
sahilmgandhi | 18:6a4db94011d3 | 1173 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1174 | * @brief Initializes the FMC_PCCARD Common space Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 1175 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 1176 | * @param Device: Pointer to PCCARD device instance |
sahilmgandhi | 18:6a4db94011d3 | 1177 | * @param Timing: Pointer to PCCARD timing structure |
sahilmgandhi | 18:6a4db94011d3 | 1178 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1179 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1180 | HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
sahilmgandhi | 18:6a4db94011d3 | 1181 | { |
sahilmgandhi | 18:6a4db94011d3 | 1182 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1183 | |
sahilmgandhi | 18:6a4db94011d3 | 1184 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1185 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1186 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1187 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1188 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1189 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1190 | |
sahilmgandhi | 18:6a4db94011d3 | 1191 | /* Get PCCARD common space timing register value */ |
sahilmgandhi | 18:6a4db94011d3 | 1192 | tmpr = Device->PMEM4; |
sahilmgandhi | 18:6a4db94011d3 | 1193 | |
sahilmgandhi | 18:6a4db94011d3 | 1194 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1195 | tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \ |
sahilmgandhi | 18:6a4db94011d3 | 1196 | FMC_PMEM4_MEMHIZ4)); |
sahilmgandhi | 18:6a4db94011d3 | 1197 | /* Set PCCARD timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1198 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 1199 | ((Timing->WaitSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1200 | ((Timing->HoldSetupTime) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1201 | ((Timing->HiZSetupTime) << 24U)); |
sahilmgandhi | 18:6a4db94011d3 | 1202 | |
sahilmgandhi | 18:6a4db94011d3 | 1203 | Device->PMEM4 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 1204 | |
sahilmgandhi | 18:6a4db94011d3 | 1205 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1206 | } |
sahilmgandhi | 18:6a4db94011d3 | 1207 | |
sahilmgandhi | 18:6a4db94011d3 | 1208 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1209 | * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 1210 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 1211 | * @param Device: Pointer to PCCARD device instance |
sahilmgandhi | 18:6a4db94011d3 | 1212 | * @param Timing: Pointer to PCCARD timing structure |
sahilmgandhi | 18:6a4db94011d3 | 1213 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1214 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1215 | HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
sahilmgandhi | 18:6a4db94011d3 | 1216 | { |
sahilmgandhi | 18:6a4db94011d3 | 1217 | uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1218 | |
sahilmgandhi | 18:6a4db94011d3 | 1219 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1220 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1221 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1222 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1223 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1224 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1225 | |
sahilmgandhi | 18:6a4db94011d3 | 1226 | /* Get PCCARD timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1227 | tmpr = Device->PATT4; |
sahilmgandhi | 18:6a4db94011d3 | 1228 | |
sahilmgandhi | 18:6a4db94011d3 | 1229 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1230 | tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \ |
sahilmgandhi | 18:6a4db94011d3 | 1231 | FMC_PATT4_ATTHIZ4)); |
sahilmgandhi | 18:6a4db94011d3 | 1232 | |
sahilmgandhi | 18:6a4db94011d3 | 1233 | /* Set PCCARD timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1234 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 1235 | ((Timing->WaitSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1236 | ((Timing->HoldSetupTime) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1237 | ((Timing->HiZSetupTime) << 24U)); |
sahilmgandhi | 18:6a4db94011d3 | 1238 | Device->PATT4 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 1239 | |
sahilmgandhi | 18:6a4db94011d3 | 1240 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1241 | } |
sahilmgandhi | 18:6a4db94011d3 | 1242 | |
sahilmgandhi | 18:6a4db94011d3 | 1243 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1244 | * @brief Initializes the FMC_PCCARD IO space Timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 1245 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 1246 | * @param Device: Pointer to PCCARD device instance |
sahilmgandhi | 18:6a4db94011d3 | 1247 | * @param Timing: Pointer to PCCARD timing structure |
sahilmgandhi | 18:6a4db94011d3 | 1248 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1249 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1250 | HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
sahilmgandhi | 18:6a4db94011d3 | 1251 | { |
sahilmgandhi | 18:6a4db94011d3 | 1252 | uint32_t tmpr = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1253 | |
sahilmgandhi | 18:6a4db94011d3 | 1254 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1255 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1256 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1257 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1258 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1259 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1260 | |
sahilmgandhi | 18:6a4db94011d3 | 1261 | /* Get FMC_PCCARD device timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1262 | tmpr = Device->PIO4; |
sahilmgandhi | 18:6a4db94011d3 | 1263 | |
sahilmgandhi | 18:6a4db94011d3 | 1264 | /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1265 | tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \ |
sahilmgandhi | 18:6a4db94011d3 | 1266 | FMC_PIO4_IOHIZ4)); |
sahilmgandhi | 18:6a4db94011d3 | 1267 | |
sahilmgandhi | 18:6a4db94011d3 | 1268 | /* Set FMC_PCCARD device timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1269 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
sahilmgandhi | 18:6a4db94011d3 | 1270 | ((Timing->WaitSetupTime) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1271 | ((Timing->HoldSetupTime) << 16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1272 | ((Timing->HiZSetupTime) << 24U)); |
sahilmgandhi | 18:6a4db94011d3 | 1273 | |
sahilmgandhi | 18:6a4db94011d3 | 1274 | Device->PIO4 = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 1275 | |
sahilmgandhi | 18:6a4db94011d3 | 1276 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1277 | } |
sahilmgandhi | 18:6a4db94011d3 | 1278 | |
sahilmgandhi | 18:6a4db94011d3 | 1279 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1280 | * @brief DeInitializes the FMC_PCCARD device |
sahilmgandhi | 18:6a4db94011d3 | 1281 | * @param Device: Pointer to PCCARD device instance |
sahilmgandhi | 18:6a4db94011d3 | 1282 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1283 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1284 | HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) |
sahilmgandhi | 18:6a4db94011d3 | 1285 | { |
sahilmgandhi | 18:6a4db94011d3 | 1286 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1287 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1288 | |
sahilmgandhi | 18:6a4db94011d3 | 1289 | /* Disable the FMC_PCCARD device */ |
sahilmgandhi | 18:6a4db94011d3 | 1290 | __FMC_PCCARD_DISABLE(Device); |
sahilmgandhi | 18:6a4db94011d3 | 1291 | |
sahilmgandhi | 18:6a4db94011d3 | 1292 | /* De-initialize the FMC_PCCARD device */ |
sahilmgandhi | 18:6a4db94011d3 | 1293 | Device->PCR4 = 0x00000018U; |
sahilmgandhi | 18:6a4db94011d3 | 1294 | Device->SR4 = 0x00000000U; |
sahilmgandhi | 18:6a4db94011d3 | 1295 | Device->PMEM4 = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 1296 | Device->PATT4 = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 1297 | Device->PIO4 = 0xFCFCFCFCU; |
sahilmgandhi | 18:6a4db94011d3 | 1298 | |
sahilmgandhi | 18:6a4db94011d3 | 1299 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1300 | } |
sahilmgandhi | 18:6a4db94011d3 | 1301 | |
sahilmgandhi | 18:6a4db94011d3 | 1302 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1303 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1304 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1305 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
sahilmgandhi | 18:6a4db94011d3 | 1306 | |
sahilmgandhi | 18:6a4db94011d3 | 1307 | |
sahilmgandhi | 18:6a4db94011d3 | 1308 | /** @addtogroup FMC_LL_SDRAM |
sahilmgandhi | 18:6a4db94011d3 | 1309 | * @brief SDRAM Controller functions |
sahilmgandhi | 18:6a4db94011d3 | 1310 | * |
sahilmgandhi | 18:6a4db94011d3 | 1311 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 1312 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1313 | ##### How to use SDRAM device driver ##### |
sahilmgandhi | 18:6a4db94011d3 | 1314 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1315 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 1316 | This driver contains a set of APIs to interface with the FMC SDRAM banks in order |
sahilmgandhi | 18:6a4db94011d3 | 1317 | to run the SDRAM external devices. |
sahilmgandhi | 18:6a4db94011d3 | 1318 | |
sahilmgandhi | 18:6a4db94011d3 | 1319 | (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() |
sahilmgandhi | 18:6a4db94011d3 | 1320 | (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() |
sahilmgandhi | 18:6a4db94011d3 | 1321 | (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() |
sahilmgandhi | 18:6a4db94011d3 | 1322 | (+) FMC SDRAM bank enable/disable write operation using the functions |
sahilmgandhi | 18:6a4db94011d3 | 1323 | FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() |
sahilmgandhi | 18:6a4db94011d3 | 1324 | (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() |
sahilmgandhi | 18:6a4db94011d3 | 1325 | |
sahilmgandhi | 18:6a4db94011d3 | 1326 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 1327 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1328 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1329 | |
sahilmgandhi | 18:6a4db94011d3 | 1330 | /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 |
sahilmgandhi | 18:6a4db94011d3 | 1331 | * @brief Initialization and Configuration functions |
sahilmgandhi | 18:6a4db94011d3 | 1332 | * |
sahilmgandhi | 18:6a4db94011d3 | 1333 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 1334 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1335 | ##### Initialization and de_initialization functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 1336 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1337 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 1338 | This section provides functions allowing to: |
sahilmgandhi | 18:6a4db94011d3 | 1339 | (+) Initialize and configure the FMC SDRAM interface |
sahilmgandhi | 18:6a4db94011d3 | 1340 | (+) De-initialize the FMC SDRAM interface |
sahilmgandhi | 18:6a4db94011d3 | 1341 | (+) Configure the FMC clock and associated GPIOs |
sahilmgandhi | 18:6a4db94011d3 | 1342 | |
sahilmgandhi | 18:6a4db94011d3 | 1343 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 1344 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1345 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1346 | |
sahilmgandhi | 18:6a4db94011d3 | 1347 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1348 | * @brief Initializes the FMC_SDRAM device according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 1349 | * control parameters in the FMC_SDRAM_InitTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 1350 | * @param Device: Pointer to SDRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 1351 | * @param Init: Pointer to SDRAM Initialization structure |
sahilmgandhi | 18:6a4db94011d3 | 1352 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1353 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1354 | HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) |
sahilmgandhi | 18:6a4db94011d3 | 1355 | { |
sahilmgandhi | 18:6a4db94011d3 | 1356 | uint32_t tmpr1 = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1357 | uint32_t tmpr2 = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1358 | |
sahilmgandhi | 18:6a4db94011d3 | 1359 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1360 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1361 | assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); |
sahilmgandhi | 18:6a4db94011d3 | 1362 | assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); |
sahilmgandhi | 18:6a4db94011d3 | 1363 | assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); |
sahilmgandhi | 18:6a4db94011d3 | 1364 | assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); |
sahilmgandhi | 18:6a4db94011d3 | 1365 | assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); |
sahilmgandhi | 18:6a4db94011d3 | 1366 | assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); |
sahilmgandhi | 18:6a4db94011d3 | 1367 | assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); |
sahilmgandhi | 18:6a4db94011d3 | 1368 | assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); |
sahilmgandhi | 18:6a4db94011d3 | 1369 | assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); |
sahilmgandhi | 18:6a4db94011d3 | 1370 | assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); |
sahilmgandhi | 18:6a4db94011d3 | 1371 | |
sahilmgandhi | 18:6a4db94011d3 | 1372 | /* Set SDRAM bank configuration parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1373 | if (Init->SDBank != FMC_SDRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 1374 | { |
sahilmgandhi | 18:6a4db94011d3 | 1375 | tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; |
sahilmgandhi | 18:6a4db94011d3 | 1376 | |
sahilmgandhi | 18:6a4db94011d3 | 1377 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1378 | tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
sahilmgandhi | 18:6a4db94011d3 | 1379 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
sahilmgandhi | 18:6a4db94011d3 | 1380 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
sahilmgandhi | 18:6a4db94011d3 | 1381 | |
sahilmgandhi | 18:6a4db94011d3 | 1382 | |
sahilmgandhi | 18:6a4db94011d3 | 1383 | tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ |
sahilmgandhi | 18:6a4db94011d3 | 1384 | Init->RowBitsNumber |\ |
sahilmgandhi | 18:6a4db94011d3 | 1385 | Init->MemoryDataWidth |\ |
sahilmgandhi | 18:6a4db94011d3 | 1386 | Init->InternalBankNumber |\ |
sahilmgandhi | 18:6a4db94011d3 | 1387 | Init->CASLatency |\ |
sahilmgandhi | 18:6a4db94011d3 | 1388 | Init->WriteProtection |\ |
sahilmgandhi | 18:6a4db94011d3 | 1389 | Init->SDClockPeriod |\ |
sahilmgandhi | 18:6a4db94011d3 | 1390 | Init->ReadBurst |\ |
sahilmgandhi | 18:6a4db94011d3 | 1391 | Init->ReadPipeDelay |
sahilmgandhi | 18:6a4db94011d3 | 1392 | ); |
sahilmgandhi | 18:6a4db94011d3 | 1393 | Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; |
sahilmgandhi | 18:6a4db94011d3 | 1394 | } |
sahilmgandhi | 18:6a4db94011d3 | 1395 | else /* FMC_Bank2_SDRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 1396 | { |
sahilmgandhi | 18:6a4db94011d3 | 1397 | tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; |
sahilmgandhi | 18:6a4db94011d3 | 1398 | |
sahilmgandhi | 18:6a4db94011d3 | 1399 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1400 | tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
sahilmgandhi | 18:6a4db94011d3 | 1401 | |
sahilmgandhi | 18:6a4db94011d3 | 1402 | tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ |
sahilmgandhi | 18:6a4db94011d3 | 1403 | Init->ReadBurst |\ |
sahilmgandhi | 18:6a4db94011d3 | 1404 | Init->ReadPipeDelay); |
sahilmgandhi | 18:6a4db94011d3 | 1405 | |
sahilmgandhi | 18:6a4db94011d3 | 1406 | tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; |
sahilmgandhi | 18:6a4db94011d3 | 1407 | |
sahilmgandhi | 18:6a4db94011d3 | 1408 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1409 | tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
sahilmgandhi | 18:6a4db94011d3 | 1410 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
sahilmgandhi | 18:6a4db94011d3 | 1411 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
sahilmgandhi | 18:6a4db94011d3 | 1412 | |
sahilmgandhi | 18:6a4db94011d3 | 1413 | tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ |
sahilmgandhi | 18:6a4db94011d3 | 1414 | Init->RowBitsNumber |\ |
sahilmgandhi | 18:6a4db94011d3 | 1415 | Init->MemoryDataWidth |\ |
sahilmgandhi | 18:6a4db94011d3 | 1416 | Init->InternalBankNumber |\ |
sahilmgandhi | 18:6a4db94011d3 | 1417 | Init->CASLatency |\ |
sahilmgandhi | 18:6a4db94011d3 | 1418 | Init->WriteProtection); |
sahilmgandhi | 18:6a4db94011d3 | 1419 | |
sahilmgandhi | 18:6a4db94011d3 | 1420 | Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; |
sahilmgandhi | 18:6a4db94011d3 | 1421 | Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; |
sahilmgandhi | 18:6a4db94011d3 | 1422 | } |
sahilmgandhi | 18:6a4db94011d3 | 1423 | |
sahilmgandhi | 18:6a4db94011d3 | 1424 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1425 | } |
sahilmgandhi | 18:6a4db94011d3 | 1426 | |
sahilmgandhi | 18:6a4db94011d3 | 1427 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1428 | * @brief Initializes the FMC_SDRAM device timing according to the specified |
sahilmgandhi | 18:6a4db94011d3 | 1429 | * parameters in the FMC_SDRAM_TimingTypeDef |
sahilmgandhi | 18:6a4db94011d3 | 1430 | * @param Device: Pointer to SDRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 1431 | * @param Timing: Pointer to SDRAM Timing structure |
sahilmgandhi | 18:6a4db94011d3 | 1432 | * @param Bank: SDRAM bank number |
sahilmgandhi | 18:6a4db94011d3 | 1433 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1434 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1435 | HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 1436 | { |
sahilmgandhi | 18:6a4db94011d3 | 1437 | uint32_t tmpr1 = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1438 | uint32_t tmpr2 = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1439 | |
sahilmgandhi | 18:6a4db94011d3 | 1440 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1441 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1442 | assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); |
sahilmgandhi | 18:6a4db94011d3 | 1443 | assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); |
sahilmgandhi | 18:6a4db94011d3 | 1444 | assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1445 | assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); |
sahilmgandhi | 18:6a4db94011d3 | 1446 | assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); |
sahilmgandhi | 18:6a4db94011d3 | 1447 | assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); |
sahilmgandhi | 18:6a4db94011d3 | 1448 | assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); |
sahilmgandhi | 18:6a4db94011d3 | 1449 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 1450 | |
sahilmgandhi | 18:6a4db94011d3 | 1451 | /* Set SDRAM device timing parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1452 | if (Bank != FMC_SDRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 1453 | { |
sahilmgandhi | 18:6a4db94011d3 | 1454 | tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; |
sahilmgandhi | 18:6a4db94011d3 | 1455 | |
sahilmgandhi | 18:6a4db94011d3 | 1456 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1457 | tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
sahilmgandhi | 18:6a4db94011d3 | 1458 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
sahilmgandhi | 18:6a4db94011d3 | 1459 | FMC_SDTR1_TRCD)); |
sahilmgandhi | 18:6a4db94011d3 | 1460 | |
sahilmgandhi | 18:6a4db94011d3 | 1461 | tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1462 | (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1463 | (((Timing->SelfRefreshTime)-1U) << 8U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1464 | (((Timing->RowCycleDelay)-1U) << 12U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1465 | (((Timing->WriteRecoveryTime)-1U) <<16U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1466 | (((Timing->RPDelay)-1U) << 20U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1467 | (((Timing->RCDDelay)-1U) << 24U)); |
sahilmgandhi | 18:6a4db94011d3 | 1468 | Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; |
sahilmgandhi | 18:6a4db94011d3 | 1469 | } |
sahilmgandhi | 18:6a4db94011d3 | 1470 | else /* FMC_Bank2_SDRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 1471 | { |
sahilmgandhi | 18:6a4db94011d3 | 1472 | tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; |
sahilmgandhi | 18:6a4db94011d3 | 1473 | |
sahilmgandhi | 18:6a4db94011d3 | 1474 | /* Clear TRC and TRP bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1475 | tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP)); |
sahilmgandhi | 18:6a4db94011d3 | 1476 | |
sahilmgandhi | 18:6a4db94011d3 | 1477 | tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1478 | (((Timing->RPDelay)-1) << 20)); |
sahilmgandhi | 18:6a4db94011d3 | 1479 | |
sahilmgandhi | 18:6a4db94011d3 | 1480 | tmpr2 = Device->SDTR[FMC_SDRAM_BANK2]; |
sahilmgandhi | 18:6a4db94011d3 | 1481 | |
sahilmgandhi | 18:6a4db94011d3 | 1482 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
sahilmgandhi | 18:6a4db94011d3 | 1483 | tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
sahilmgandhi | 18:6a4db94011d3 | 1484 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
sahilmgandhi | 18:6a4db94011d3 | 1485 | FMC_SDTR1_TRCD)); |
sahilmgandhi | 18:6a4db94011d3 | 1486 | |
sahilmgandhi | 18:6a4db94011d3 | 1487 | tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1488 | (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1489 | (((Timing->SelfRefreshTime)-1) << 8) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1490 | (((Timing->WriteRecoveryTime)-1) <<16) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1491 | (((Timing->RCDDelay)-1) << 24))); |
sahilmgandhi | 18:6a4db94011d3 | 1492 | |
sahilmgandhi | 18:6a4db94011d3 | 1493 | Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; |
sahilmgandhi | 18:6a4db94011d3 | 1494 | Device->SDTR[FMC_SDRAM_BANK2] = tmpr2; |
sahilmgandhi | 18:6a4db94011d3 | 1495 | } |
sahilmgandhi | 18:6a4db94011d3 | 1496 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1497 | } |
sahilmgandhi | 18:6a4db94011d3 | 1498 | |
sahilmgandhi | 18:6a4db94011d3 | 1499 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1500 | * @brief DeInitializes the FMC_SDRAM peripheral |
sahilmgandhi | 18:6a4db94011d3 | 1501 | * @param Device: Pointer to SDRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 1502 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1503 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1504 | HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 1505 | { |
sahilmgandhi | 18:6a4db94011d3 | 1506 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1507 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1508 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 1509 | |
sahilmgandhi | 18:6a4db94011d3 | 1510 | /* De-initialize the SDRAM device */ |
sahilmgandhi | 18:6a4db94011d3 | 1511 | Device->SDCR[Bank] = 0x000002D0U; |
sahilmgandhi | 18:6a4db94011d3 | 1512 | Device->SDTR[Bank] = 0x0FFFFFFFU; |
sahilmgandhi | 18:6a4db94011d3 | 1513 | Device->SDCMR = 0x00000000U; |
sahilmgandhi | 18:6a4db94011d3 | 1514 | Device->SDRTR = 0x00000000U; |
sahilmgandhi | 18:6a4db94011d3 | 1515 | Device->SDSR = 0x00000000U; |
sahilmgandhi | 18:6a4db94011d3 | 1516 | |
sahilmgandhi | 18:6a4db94011d3 | 1517 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1518 | } |
sahilmgandhi | 18:6a4db94011d3 | 1519 | |
sahilmgandhi | 18:6a4db94011d3 | 1520 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1521 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1522 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1523 | |
sahilmgandhi | 18:6a4db94011d3 | 1524 | /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 |
sahilmgandhi | 18:6a4db94011d3 | 1525 | * @brief management functions |
sahilmgandhi | 18:6a4db94011d3 | 1526 | * |
sahilmgandhi | 18:6a4db94011d3 | 1527 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 1528 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1529 | ##### FMC_SDRAM Control functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 1530 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 1531 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 1532 | This subsection provides a set of functions allowing to control dynamically |
sahilmgandhi | 18:6a4db94011d3 | 1533 | the FMC SDRAM interface. |
sahilmgandhi | 18:6a4db94011d3 | 1534 | |
sahilmgandhi | 18:6a4db94011d3 | 1535 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 1536 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1537 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1538 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1539 | * @brief Enables dynamically FMC_SDRAM write protection. |
sahilmgandhi | 18:6a4db94011d3 | 1540 | * @param Device: Pointer to SDRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 1541 | * @param Bank: SDRAM bank number |
sahilmgandhi | 18:6a4db94011d3 | 1542 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1543 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1544 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 1545 | { |
sahilmgandhi | 18:6a4db94011d3 | 1546 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1547 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1548 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 1549 | |
sahilmgandhi | 18:6a4db94011d3 | 1550 | /* Enable write protection */ |
sahilmgandhi | 18:6a4db94011d3 | 1551 | Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 1552 | |
sahilmgandhi | 18:6a4db94011d3 | 1553 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1554 | } |
sahilmgandhi | 18:6a4db94011d3 | 1555 | |
sahilmgandhi | 18:6a4db94011d3 | 1556 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1557 | * @brief Disables dynamically FMC_SDRAM write protection. |
sahilmgandhi | 18:6a4db94011d3 | 1558 | * @param hsdram: FMC_SDRAM handle |
sahilmgandhi | 18:6a4db94011d3 | 1559 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 1560 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1561 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 1562 | { |
sahilmgandhi | 18:6a4db94011d3 | 1563 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1564 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1565 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 1566 | |
sahilmgandhi | 18:6a4db94011d3 | 1567 | /* Disable write protection */ |
sahilmgandhi | 18:6a4db94011d3 | 1568 | Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 1569 | |
sahilmgandhi | 18:6a4db94011d3 | 1570 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1571 | } |
sahilmgandhi | 18:6a4db94011d3 | 1572 | |
sahilmgandhi | 18:6a4db94011d3 | 1573 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1574 | * @brief Send Command to the FMC SDRAM bank |
sahilmgandhi | 18:6a4db94011d3 | 1575 | * @param Device: Pointer to SDRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 1576 | * @param Command: Pointer to SDRAM command structure |
sahilmgandhi | 18:6a4db94011d3 | 1577 | * @param Timing: Pointer to SDRAM Timing structure |
sahilmgandhi | 18:6a4db94011d3 | 1578 | * @param Timeout: Timeout wait value |
sahilmgandhi | 18:6a4db94011d3 | 1579 | * @retval HAL state |
sahilmgandhi | 18:6a4db94011d3 | 1580 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1581 | HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) |
sahilmgandhi | 18:6a4db94011d3 | 1582 | { |
sahilmgandhi | 18:6a4db94011d3 | 1583 | __IO uint32_t tmpr = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1584 | uint32_t tickstart = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1585 | |
sahilmgandhi | 18:6a4db94011d3 | 1586 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1587 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1588 | assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); |
sahilmgandhi | 18:6a4db94011d3 | 1589 | assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); |
sahilmgandhi | 18:6a4db94011d3 | 1590 | assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); |
sahilmgandhi | 18:6a4db94011d3 | 1591 | assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); |
sahilmgandhi | 18:6a4db94011d3 | 1592 | |
sahilmgandhi | 18:6a4db94011d3 | 1593 | /* Set command register */ |
sahilmgandhi | 18:6a4db94011d3 | 1594 | tmpr = (uint32_t)((Command->CommandMode) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1595 | (Command->CommandTarget) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1596 | (((Command->AutoRefreshNumber)-1U) << 5U) |\ |
sahilmgandhi | 18:6a4db94011d3 | 1597 | ((Command->ModeRegisterDefinition) << 9U) |
sahilmgandhi | 18:6a4db94011d3 | 1598 | ); |
sahilmgandhi | 18:6a4db94011d3 | 1599 | |
sahilmgandhi | 18:6a4db94011d3 | 1600 | Device->SDCMR = tmpr; |
sahilmgandhi | 18:6a4db94011d3 | 1601 | |
sahilmgandhi | 18:6a4db94011d3 | 1602 | /* Get tick */ |
sahilmgandhi | 18:6a4db94011d3 | 1603 | tickstart = HAL_GetTick(); |
sahilmgandhi | 18:6a4db94011d3 | 1604 | |
sahilmgandhi | 18:6a4db94011d3 | 1605 | /* Wait until command is send */ |
sahilmgandhi | 18:6a4db94011d3 | 1606 | while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) |
sahilmgandhi | 18:6a4db94011d3 | 1607 | { |
sahilmgandhi | 18:6a4db94011d3 | 1608 | /* Check for the Timeout */ |
sahilmgandhi | 18:6a4db94011d3 | 1609 | if(Timeout != HAL_MAX_DELAY) |
sahilmgandhi | 18:6a4db94011d3 | 1610 | { |
sahilmgandhi | 18:6a4db94011d3 | 1611 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
sahilmgandhi | 18:6a4db94011d3 | 1612 | { |
sahilmgandhi | 18:6a4db94011d3 | 1613 | return HAL_TIMEOUT; |
sahilmgandhi | 18:6a4db94011d3 | 1614 | } |
sahilmgandhi | 18:6a4db94011d3 | 1615 | } |
sahilmgandhi | 18:6a4db94011d3 | 1616 | } |
sahilmgandhi | 18:6a4db94011d3 | 1617 | |
sahilmgandhi | 18:6a4db94011d3 | 1618 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1619 | } |
sahilmgandhi | 18:6a4db94011d3 | 1620 | |
sahilmgandhi | 18:6a4db94011d3 | 1621 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1622 | * @brief Program the SDRAM Memory Refresh rate. |
sahilmgandhi | 18:6a4db94011d3 | 1623 | * @param Device: Pointer to SDRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 1624 | * @param RefreshRate: The SDRAM refresh rate value. |
sahilmgandhi | 18:6a4db94011d3 | 1625 | * @retval HAL state |
sahilmgandhi | 18:6a4db94011d3 | 1626 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1627 | HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) |
sahilmgandhi | 18:6a4db94011d3 | 1628 | { |
sahilmgandhi | 18:6a4db94011d3 | 1629 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1630 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1631 | assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); |
sahilmgandhi | 18:6a4db94011d3 | 1632 | |
sahilmgandhi | 18:6a4db94011d3 | 1633 | /* Set the refresh rate in command register */ |
sahilmgandhi | 18:6a4db94011d3 | 1634 | Device->SDRTR |= (RefreshRate<<1U); |
sahilmgandhi | 18:6a4db94011d3 | 1635 | |
sahilmgandhi | 18:6a4db94011d3 | 1636 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1637 | } |
sahilmgandhi | 18:6a4db94011d3 | 1638 | |
sahilmgandhi | 18:6a4db94011d3 | 1639 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1640 | * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. |
sahilmgandhi | 18:6a4db94011d3 | 1641 | * @param Device: Pointer to SDRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 1642 | * @param AutoRefreshNumber: Specifies the auto Refresh number. |
sahilmgandhi | 18:6a4db94011d3 | 1643 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 1644 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1645 | HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) |
sahilmgandhi | 18:6a4db94011d3 | 1646 | { |
sahilmgandhi | 18:6a4db94011d3 | 1647 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1648 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1649 | assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); |
sahilmgandhi | 18:6a4db94011d3 | 1650 | |
sahilmgandhi | 18:6a4db94011d3 | 1651 | /* Set the Auto-refresh number in command register */ |
sahilmgandhi | 18:6a4db94011d3 | 1652 | Device->SDCMR |= (AutoRefreshNumber << 5U); |
sahilmgandhi | 18:6a4db94011d3 | 1653 | |
sahilmgandhi | 18:6a4db94011d3 | 1654 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 1655 | } |
sahilmgandhi | 18:6a4db94011d3 | 1656 | |
sahilmgandhi | 18:6a4db94011d3 | 1657 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1658 | * @brief Returns the indicated FMC SDRAM bank mode status. |
sahilmgandhi | 18:6a4db94011d3 | 1659 | * @param Device: Pointer to SDRAM device instance |
sahilmgandhi | 18:6a4db94011d3 | 1660 | * @param Bank: Defines the FMC SDRAM bank. This parameter can be |
sahilmgandhi | 18:6a4db94011d3 | 1661 | * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. |
sahilmgandhi | 18:6a4db94011d3 | 1662 | * @retval The FMC SDRAM bank mode status, could be on of the following values: |
sahilmgandhi | 18:6a4db94011d3 | 1663 | * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or |
sahilmgandhi | 18:6a4db94011d3 | 1664 | * FMC_SDRAM_POWER_DOWN_MODE. |
sahilmgandhi | 18:6a4db94011d3 | 1665 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1666 | uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
sahilmgandhi | 18:6a4db94011d3 | 1667 | { |
sahilmgandhi | 18:6a4db94011d3 | 1668 | uint32_t tmpreg = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 1669 | |
sahilmgandhi | 18:6a4db94011d3 | 1670 | /* Check the parameters */ |
sahilmgandhi | 18:6a4db94011d3 | 1671 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
sahilmgandhi | 18:6a4db94011d3 | 1672 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
sahilmgandhi | 18:6a4db94011d3 | 1673 | |
sahilmgandhi | 18:6a4db94011d3 | 1674 | /* Get the corresponding bank mode */ |
sahilmgandhi | 18:6a4db94011d3 | 1675 | if(Bank == FMC_SDRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 1676 | { |
sahilmgandhi | 18:6a4db94011d3 | 1677 | tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); |
sahilmgandhi | 18:6a4db94011d3 | 1678 | } |
sahilmgandhi | 18:6a4db94011d3 | 1679 | else |
sahilmgandhi | 18:6a4db94011d3 | 1680 | { |
sahilmgandhi | 18:6a4db94011d3 | 1681 | tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); |
sahilmgandhi | 18:6a4db94011d3 | 1682 | } |
sahilmgandhi | 18:6a4db94011d3 | 1683 | |
sahilmgandhi | 18:6a4db94011d3 | 1684 | /* Return the mode status */ |
sahilmgandhi | 18:6a4db94011d3 | 1685 | return tmpreg; |
sahilmgandhi | 18:6a4db94011d3 | 1686 | } |
sahilmgandhi | 18:6a4db94011d3 | 1687 | |
sahilmgandhi | 18:6a4db94011d3 | 1688 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1689 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1690 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1691 | |
sahilmgandhi | 18:6a4db94011d3 | 1692 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1693 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1694 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1695 | |
sahilmgandhi | 18:6a4db94011d3 | 1696 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1697 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1698 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1699 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
sahilmgandhi | 18:6a4db94011d3 | 1700 | #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ |
sahilmgandhi | 18:6a4db94011d3 | 1701 | |
sahilmgandhi | 18:6a4db94011d3 | 1702 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1703 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1704 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1705 | |
sahilmgandhi | 18:6a4db94011d3 | 1706 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1707 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1708 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1709 | |
sahilmgandhi | 18:6a4db94011d3 | 1710 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |