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Mouse code for the MacroRat

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mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_rcc.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of RCC HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_HAL_RCC_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_HAL_RCC_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f4xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /* Include RCC HAL Extended module */
sahilmgandhi 18:6a4db94011d3 50 /* (include on top of file since RCC structures are defined in extended file) */
sahilmgandhi 18:6a4db94011d3 51 #include "stm32f4xx_hal_rcc_ex.h"
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /** @addtogroup RCC
sahilmgandhi 18:6a4db94011d3 58 * @{
sahilmgandhi 18:6a4db94011d3 59 */
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 62 /** @defgroup RCC_Exported_Types RCC Exported Types
sahilmgandhi 18:6a4db94011d3 63 * @{
sahilmgandhi 18:6a4db94011d3 64 */
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 /**
sahilmgandhi 18:6a4db94011d3 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69 typedef struct
sahilmgandhi 18:6a4db94011d3 70 {
sahilmgandhi 18:6a4db94011d3 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
sahilmgandhi 18:6a4db94011d3 72 This parameter can be a value of @ref RCC_Oscillator_Type */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 uint32_t HSEState; /*!< The new state of the HSE.
sahilmgandhi 18:6a4db94011d3 75 This parameter can be a value of @ref RCC_HSE_Config */
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 uint32_t LSEState; /*!< The new state of the LSE.
sahilmgandhi 18:6a4db94011d3 78 This parameter can be a value of @ref RCC_LSE_Config */
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 uint32_t HSIState; /*!< The new state of the HSI.
sahilmgandhi 18:6a4db94011d3 81 This parameter can be a value of @ref RCC_HSI_Config */
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
sahilmgandhi 18:6a4db94011d3 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 uint32_t LSIState; /*!< The new state of the LSI.
sahilmgandhi 18:6a4db94011d3 87 This parameter can be a value of @ref RCC_LSI_Config */
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
sahilmgandhi 18:6a4db94011d3 90 }RCC_OscInitTypeDef;
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /**
sahilmgandhi 18:6a4db94011d3 93 * @brief RCC System, AHB and APB busses clock configuration structure definition
sahilmgandhi 18:6a4db94011d3 94 */
sahilmgandhi 18:6a4db94011d3 95 typedef struct
sahilmgandhi 18:6a4db94011d3 96 {
sahilmgandhi 18:6a4db94011d3 97 uint32_t ClockType; /*!< The clock to be configured.
sahilmgandhi 18:6a4db94011d3 98 This parameter can be a value of @ref RCC_System_Clock_Type */
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
sahilmgandhi 18:6a4db94011d3 101 This parameter can be a value of @ref RCC_System_Clock_Source */
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
sahilmgandhi 18:6a4db94011d3 104 This parameter can be a value of @ref RCC_AHB_Clock_Source */
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
sahilmgandhi 18:6a4db94011d3 107 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
sahilmgandhi 18:6a4db94011d3 110 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 }RCC_ClkInitTypeDef;
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /**
sahilmgandhi 18:6a4db94011d3 115 * @}
sahilmgandhi 18:6a4db94011d3 116 */
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 119 /** @defgroup RCC_Exported_Constants RCC Exported Constants
sahilmgandhi 18:6a4db94011d3 120 * @{
sahilmgandhi 18:6a4db94011d3 121 */
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /** @defgroup RCC_Oscillator_Type Oscillator Type
sahilmgandhi 18:6a4db94011d3 124 * @{
sahilmgandhi 18:6a4db94011d3 125 */
sahilmgandhi 18:6a4db94011d3 126 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 127 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
sahilmgandhi 18:6a4db94011d3 128 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 129 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 130 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 131 /**
sahilmgandhi 18:6a4db94011d3 132 * @}
sahilmgandhi 18:6a4db94011d3 133 */
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 /** @defgroup RCC_HSE_Config HSE Config
sahilmgandhi 18:6a4db94011d3 136 * @{
sahilmgandhi 18:6a4db94011d3 137 */
sahilmgandhi 18:6a4db94011d3 138 #define RCC_HSE_OFF ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 139 #define RCC_HSE_ON ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 140 #define RCC_HSE_BYPASS ((uint8_t)0x05U)
sahilmgandhi 18:6a4db94011d3 141 /**
sahilmgandhi 18:6a4db94011d3 142 * @}
sahilmgandhi 18:6a4db94011d3 143 */
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 /** @defgroup RCC_LSE_Config LSE Config
sahilmgandhi 18:6a4db94011d3 146 * @{
sahilmgandhi 18:6a4db94011d3 147 */
sahilmgandhi 18:6a4db94011d3 148 #define RCC_LSE_OFF ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 149 #define RCC_LSE_ON ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 150 #define RCC_LSE_BYPASS ((uint8_t)0x05U)
sahilmgandhi 18:6a4db94011d3 151 /**
sahilmgandhi 18:6a4db94011d3 152 * @}
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /** @defgroup RCC_HSI_Config HSI Config
sahilmgandhi 18:6a4db94011d3 156 * @{
sahilmgandhi 18:6a4db94011d3 157 */
sahilmgandhi 18:6a4db94011d3 158 #define RCC_HSI_OFF ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 159 #define RCC_HSI_ON ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
sahilmgandhi 18:6a4db94011d3 162 /**
sahilmgandhi 18:6a4db94011d3 163 * @}
sahilmgandhi 18:6a4db94011d3 164 */
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /** @defgroup RCC_LSI_Config LSI Config
sahilmgandhi 18:6a4db94011d3 167 * @{
sahilmgandhi 18:6a4db94011d3 168 */
sahilmgandhi 18:6a4db94011d3 169 #define RCC_LSI_OFF ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 170 #define RCC_LSI_ON ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 171 /**
sahilmgandhi 18:6a4db94011d3 172 * @}
sahilmgandhi 18:6a4db94011d3 173 */
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /** @defgroup RCC_PLL_Config PLL Config
sahilmgandhi 18:6a4db94011d3 176 * @{
sahilmgandhi 18:6a4db94011d3 177 */
sahilmgandhi 18:6a4db94011d3 178 #define RCC_PLL_NONE ((uint8_t)0x00U)
sahilmgandhi 18:6a4db94011d3 179 #define RCC_PLL_OFF ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 180 #define RCC_PLL_ON ((uint8_t)0x02U)
sahilmgandhi 18:6a4db94011d3 181 /**
sahilmgandhi 18:6a4db94011d3 182 * @}
sahilmgandhi 18:6a4db94011d3 183 */
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
sahilmgandhi 18:6a4db94011d3 186 * @{
sahilmgandhi 18:6a4db94011d3 187 */
sahilmgandhi 18:6a4db94011d3 188 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 189 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 190 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
sahilmgandhi 18:6a4db94011d3 191 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 192 /**
sahilmgandhi 18:6a4db94011d3 193 * @}
sahilmgandhi 18:6a4db94011d3 194 */
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
sahilmgandhi 18:6a4db94011d3 197 * @{
sahilmgandhi 18:6a4db94011d3 198 */
sahilmgandhi 18:6a4db94011d3 199 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
sahilmgandhi 18:6a4db94011d3 200 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
sahilmgandhi 18:6a4db94011d3 201 /**
sahilmgandhi 18:6a4db94011d3 202 * @}
sahilmgandhi 18:6a4db94011d3 203 */
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 /** @defgroup RCC_System_Clock_Type System Clock Type
sahilmgandhi 18:6a4db94011d3 206 * @{
sahilmgandhi 18:6a4db94011d3 207 */
sahilmgandhi 18:6a4db94011d3 208 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
sahilmgandhi 18:6a4db94011d3 209 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
sahilmgandhi 18:6a4db94011d3 210 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
sahilmgandhi 18:6a4db94011d3 211 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
sahilmgandhi 18:6a4db94011d3 212 /**
sahilmgandhi 18:6a4db94011d3 213 * @}
sahilmgandhi 18:6a4db94011d3 214 */
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 /** @defgroup RCC_System_Clock_Source System Clock Source
sahilmgandhi 18:6a4db94011d3 217 * @{
sahilmgandhi 18:6a4db94011d3 218 */
sahilmgandhi 18:6a4db94011d3 219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
sahilmgandhi 18:6a4db94011d3 220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
sahilmgandhi 18:6a4db94011d3 221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
sahilmgandhi 18:6a4db94011d3 222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
sahilmgandhi 18:6a4db94011d3 223 /**
sahilmgandhi 18:6a4db94011d3 224 * @}
sahilmgandhi 18:6a4db94011d3 225 */
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
sahilmgandhi 18:6a4db94011d3 228 * @{
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
sahilmgandhi 18:6a4db94011d3 231 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
sahilmgandhi 18:6a4db94011d3 232 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
sahilmgandhi 18:6a4db94011d3 233 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
sahilmgandhi 18:6a4db94011d3 234 /**
sahilmgandhi 18:6a4db94011d3 235 * @}
sahilmgandhi 18:6a4db94011d3 236 */
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
sahilmgandhi 18:6a4db94011d3 239 * @{
sahilmgandhi 18:6a4db94011d3 240 */
sahilmgandhi 18:6a4db94011d3 241 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
sahilmgandhi 18:6a4db94011d3 242 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
sahilmgandhi 18:6a4db94011d3 243 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
sahilmgandhi 18:6a4db94011d3 244 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
sahilmgandhi 18:6a4db94011d3 245 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
sahilmgandhi 18:6a4db94011d3 246 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
sahilmgandhi 18:6a4db94011d3 247 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
sahilmgandhi 18:6a4db94011d3 248 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
sahilmgandhi 18:6a4db94011d3 249 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
sahilmgandhi 18:6a4db94011d3 250 /**
sahilmgandhi 18:6a4db94011d3 251 * @}
sahilmgandhi 18:6a4db94011d3 252 */
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
sahilmgandhi 18:6a4db94011d3 255 * @{
sahilmgandhi 18:6a4db94011d3 256 */
sahilmgandhi 18:6a4db94011d3 257 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
sahilmgandhi 18:6a4db94011d3 258 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
sahilmgandhi 18:6a4db94011d3 259 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
sahilmgandhi 18:6a4db94011d3 260 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
sahilmgandhi 18:6a4db94011d3 261 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
sahilmgandhi 18:6a4db94011d3 262 /**
sahilmgandhi 18:6a4db94011d3 263 * @}
sahilmgandhi 18:6a4db94011d3 264 */
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
sahilmgandhi 18:6a4db94011d3 267 * @{
sahilmgandhi 18:6a4db94011d3 268 */
sahilmgandhi 18:6a4db94011d3 269 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
sahilmgandhi 18:6a4db94011d3 270 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
sahilmgandhi 18:6a4db94011d3 271 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
sahilmgandhi 18:6a4db94011d3 272 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
sahilmgandhi 18:6a4db94011d3 273 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
sahilmgandhi 18:6a4db94011d3 274 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
sahilmgandhi 18:6a4db94011d3 275 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
sahilmgandhi 18:6a4db94011d3 276 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
sahilmgandhi 18:6a4db94011d3 277 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
sahilmgandhi 18:6a4db94011d3 278 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
sahilmgandhi 18:6a4db94011d3 279 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
sahilmgandhi 18:6a4db94011d3 280 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
sahilmgandhi 18:6a4db94011d3 281 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
sahilmgandhi 18:6a4db94011d3 282 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
sahilmgandhi 18:6a4db94011d3 283 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
sahilmgandhi 18:6a4db94011d3 284 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
sahilmgandhi 18:6a4db94011d3 285 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
sahilmgandhi 18:6a4db94011d3 286 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
sahilmgandhi 18:6a4db94011d3 287 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
sahilmgandhi 18:6a4db94011d3 288 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
sahilmgandhi 18:6a4db94011d3 289 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
sahilmgandhi 18:6a4db94011d3 290 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
sahilmgandhi 18:6a4db94011d3 291 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
sahilmgandhi 18:6a4db94011d3 292 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
sahilmgandhi 18:6a4db94011d3 293 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
sahilmgandhi 18:6a4db94011d3 294 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
sahilmgandhi 18:6a4db94011d3 295 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
sahilmgandhi 18:6a4db94011d3 296 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
sahilmgandhi 18:6a4db94011d3 297 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
sahilmgandhi 18:6a4db94011d3 298 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
sahilmgandhi 18:6a4db94011d3 299 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
sahilmgandhi 18:6a4db94011d3 300 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
sahilmgandhi 18:6a4db94011d3 301 /**
sahilmgandhi 18:6a4db94011d3 302 * @}
sahilmgandhi 18:6a4db94011d3 303 */
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /** @defgroup RCC_MCO_Index MCO Index
sahilmgandhi 18:6a4db94011d3 306 * @{
sahilmgandhi 18:6a4db94011d3 307 */
sahilmgandhi 18:6a4db94011d3 308 #define RCC_MCO1 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 309 #define RCC_MCO2 ((uint32_t)0x00000001U)
sahilmgandhi 18:6a4db94011d3 310 /**
sahilmgandhi 18:6a4db94011d3 311 * @}
sahilmgandhi 18:6a4db94011d3 312 */
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
sahilmgandhi 18:6a4db94011d3 315 * @{
sahilmgandhi 18:6a4db94011d3 316 */
sahilmgandhi 18:6a4db94011d3 317 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 318 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
sahilmgandhi 18:6a4db94011d3 319 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
sahilmgandhi 18:6a4db94011d3 320 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
sahilmgandhi 18:6a4db94011d3 321 /**
sahilmgandhi 18:6a4db94011d3 322 * @}
sahilmgandhi 18:6a4db94011d3 323 */
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
sahilmgandhi 18:6a4db94011d3 326 * @{
sahilmgandhi 18:6a4db94011d3 327 */
sahilmgandhi 18:6a4db94011d3 328 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 329 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
sahilmgandhi 18:6a4db94011d3 330 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
sahilmgandhi 18:6a4db94011d3 331 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
sahilmgandhi 18:6a4db94011d3 332 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
sahilmgandhi 18:6a4db94011d3 333 /**
sahilmgandhi 18:6a4db94011d3 334 * @}
sahilmgandhi 18:6a4db94011d3 335 */
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 /** @defgroup RCC_Interrupt Interrupts
sahilmgandhi 18:6a4db94011d3 338 * @{
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 341 #define RCC_IT_LSERDY ((uint8_t)0x02U)
sahilmgandhi 18:6a4db94011d3 342 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
sahilmgandhi 18:6a4db94011d3 343 #define RCC_IT_HSERDY ((uint8_t)0x08U)
sahilmgandhi 18:6a4db94011d3 344 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
sahilmgandhi 18:6a4db94011d3 345 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
sahilmgandhi 18:6a4db94011d3 346 #define RCC_IT_CSS ((uint8_t)0x80U)
sahilmgandhi 18:6a4db94011d3 347 /**
sahilmgandhi 18:6a4db94011d3 348 * @}
sahilmgandhi 18:6a4db94011d3 349 */
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 /** @defgroup RCC_Flag Flags
sahilmgandhi 18:6a4db94011d3 352 * Elements values convention: 0XXYYYYYb
sahilmgandhi 18:6a4db94011d3 353 * - YYYYY : Flag position in the register
sahilmgandhi 18:6a4db94011d3 354 * - 0XX : Register index
sahilmgandhi 18:6a4db94011d3 355 * - 01: CR register
sahilmgandhi 18:6a4db94011d3 356 * - 10: BDCR register
sahilmgandhi 18:6a4db94011d3 357 * - 11: CSR register
sahilmgandhi 18:6a4db94011d3 358 * @{
sahilmgandhi 18:6a4db94011d3 359 */
sahilmgandhi 18:6a4db94011d3 360 /* Flags in the CR register */
sahilmgandhi 18:6a4db94011d3 361 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
sahilmgandhi 18:6a4db94011d3 362 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
sahilmgandhi 18:6a4db94011d3 363 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
sahilmgandhi 18:6a4db94011d3 364 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /* Flags in the BDCR register */
sahilmgandhi 18:6a4db94011d3 367 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 /* Flags in the CSR register */
sahilmgandhi 18:6a4db94011d3 370 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
sahilmgandhi 18:6a4db94011d3 371 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
sahilmgandhi 18:6a4db94011d3 372 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
sahilmgandhi 18:6a4db94011d3 373 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
sahilmgandhi 18:6a4db94011d3 374 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
sahilmgandhi 18:6a4db94011d3 375 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
sahilmgandhi 18:6a4db94011d3 376 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
sahilmgandhi 18:6a4db94011d3 377 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
sahilmgandhi 18:6a4db94011d3 378 /**
sahilmgandhi 18:6a4db94011d3 379 * @}
sahilmgandhi 18:6a4db94011d3 380 */
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 /**
sahilmgandhi 18:6a4db94011d3 383 * @}
sahilmgandhi 18:6a4db94011d3 384 */
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 387 /** @defgroup RCC_Exported_Macros RCC Exported Macros
sahilmgandhi 18:6a4db94011d3 388 * @{
sahilmgandhi 18:6a4db94011d3 389 */
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi 18:6a4db94011d3 392 * @brief Enable or disable the AHB1 peripheral clock.
sahilmgandhi 18:6a4db94011d3 393 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 394 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 395 * using it.
sahilmgandhi 18:6a4db94011d3 396 * @{
sahilmgandhi 18:6a4db94011d3 397 */
sahilmgandhi 18:6a4db94011d3 398 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 399 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 400 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
sahilmgandhi 18:6a4db94011d3 401 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 402 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
sahilmgandhi 18:6a4db94011d3 403 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 404 } while(0)
sahilmgandhi 18:6a4db94011d3 405 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 406 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 407 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
sahilmgandhi 18:6a4db94011d3 408 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 409 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
sahilmgandhi 18:6a4db94011d3 410 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 411 } while(0)
sahilmgandhi 18:6a4db94011d3 412 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
sahilmgandhi 18:6a4db94011d3 415 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
sahilmgandhi 18:6a4db94011d3 417 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 418 } while(0)
sahilmgandhi 18:6a4db94011d3 419 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 420 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 421 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
sahilmgandhi 18:6a4db94011d3 422 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 423 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
sahilmgandhi 18:6a4db94011d3 424 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 425 } while(0)
sahilmgandhi 18:6a4db94011d3 426 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 427 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 428 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
sahilmgandhi 18:6a4db94011d3 429 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 430 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
sahilmgandhi 18:6a4db94011d3 431 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 432 } while(0)
sahilmgandhi 18:6a4db94011d3 433 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 434 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 435 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
sahilmgandhi 18:6a4db94011d3 436 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 437 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
sahilmgandhi 18:6a4db94011d3 438 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 439 } while(0)
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
sahilmgandhi 18:6a4db94011d3 442 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
sahilmgandhi 18:6a4db94011d3 443 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
sahilmgandhi 18:6a4db94011d3 444 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
sahilmgandhi 18:6a4db94011d3 445 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
sahilmgandhi 18:6a4db94011d3 446 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
sahilmgandhi 18:6a4db94011d3 447 /**
sahilmgandhi 18:6a4db94011d3 448 * @}
sahilmgandhi 18:6a4db94011d3 449 */
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi 18:6a4db94011d3 452 * @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi 18:6a4db94011d3 453 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 454 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 455 * using it.
sahilmgandhi 18:6a4db94011d3 456 * @{
sahilmgandhi 18:6a4db94011d3 457 */
sahilmgandhi 18:6a4db94011d3 458 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
sahilmgandhi 18:6a4db94011d3 459 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
sahilmgandhi 18:6a4db94011d3 460 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
sahilmgandhi 18:6a4db94011d3 461 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
sahilmgandhi 18:6a4db94011d3 462 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 463 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
sahilmgandhi 18:6a4db94011d3 466 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
sahilmgandhi 18:6a4db94011d3 467 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
sahilmgandhi 18:6a4db94011d3 468 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
sahilmgandhi 18:6a4db94011d3 469 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 470 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 471 /**
sahilmgandhi 18:6a4db94011d3 472 * @}
sahilmgandhi 18:6a4db94011d3 473 */
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
sahilmgandhi 18:6a4db94011d3 476 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
sahilmgandhi 18:6a4db94011d3 477 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 478 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 479 * using it.
sahilmgandhi 18:6a4db94011d3 480 * @{
sahilmgandhi 18:6a4db94011d3 481 */
sahilmgandhi 18:6a4db94011d3 482 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
sahilmgandhi 18:6a4db94011d3 485 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
sahilmgandhi 18:6a4db94011d3 487 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 488 } while(0)
sahilmgandhi 18:6a4db94011d3 489 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 490 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 491 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
sahilmgandhi 18:6a4db94011d3 492 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 493 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
sahilmgandhi 18:6a4db94011d3 494 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 495 } while(0)
sahilmgandhi 18:6a4db94011d3 496 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 497 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 498 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
sahilmgandhi 18:6a4db94011d3 499 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 500 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
sahilmgandhi 18:6a4db94011d3 501 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 502 } while(0)
sahilmgandhi 18:6a4db94011d3 503 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 505 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
sahilmgandhi 18:6a4db94011d3 506 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 507 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
sahilmgandhi 18:6a4db94011d3 508 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 509 } while(0)
sahilmgandhi 18:6a4db94011d3 510 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 511 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 512 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
sahilmgandhi 18:6a4db94011d3 513 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 514 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
sahilmgandhi 18:6a4db94011d3 515 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 516 } while(0)
sahilmgandhi 18:6a4db94011d3 517 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 518 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 519 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
sahilmgandhi 18:6a4db94011d3 520 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 521 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
sahilmgandhi 18:6a4db94011d3 522 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 523 } while(0)
sahilmgandhi 18:6a4db94011d3 524 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 525 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 526 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
sahilmgandhi 18:6a4db94011d3 527 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 528 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
sahilmgandhi 18:6a4db94011d3 529 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 530 } while(0)
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
sahilmgandhi 18:6a4db94011d3 533 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
sahilmgandhi 18:6a4db94011d3 534 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
sahilmgandhi 18:6a4db94011d3 535 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
sahilmgandhi 18:6a4db94011d3 536 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
sahilmgandhi 18:6a4db94011d3 537 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
sahilmgandhi 18:6a4db94011d3 538 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
sahilmgandhi 18:6a4db94011d3 539 /**
sahilmgandhi 18:6a4db94011d3 540 * @}
sahilmgandhi 18:6a4db94011d3 541 */
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
sahilmgandhi 18:6a4db94011d3 544 * @brief Get the enable or disable status of the APB1 peripheral clock.
sahilmgandhi 18:6a4db94011d3 545 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 546 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 547 * using it.
sahilmgandhi 18:6a4db94011d3 548 * @{
sahilmgandhi 18:6a4db94011d3 549 */
sahilmgandhi 18:6a4db94011d3 550 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 551 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
sahilmgandhi 18:6a4db94011d3 552 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 553 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 554 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 555 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 556 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 559 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
sahilmgandhi 18:6a4db94011d3 560 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 561 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 562 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 563 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 564 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
sahilmgandhi 18:6a4db94011d3 565 /**
sahilmgandhi 18:6a4db94011d3 566 * @}
sahilmgandhi 18:6a4db94011d3 567 */
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
sahilmgandhi 18:6a4db94011d3 570 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
sahilmgandhi 18:6a4db94011d3 571 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 572 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 573 * using it.
sahilmgandhi 18:6a4db94011d3 574 * @{
sahilmgandhi 18:6a4db94011d3 575 */
sahilmgandhi 18:6a4db94011d3 576 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 577 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 578 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
sahilmgandhi 18:6a4db94011d3 579 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 580 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
sahilmgandhi 18:6a4db94011d3 581 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 582 } while(0)
sahilmgandhi 18:6a4db94011d3 583 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 585 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
sahilmgandhi 18:6a4db94011d3 586 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 587 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
sahilmgandhi 18:6a4db94011d3 588 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 589 } while(0)
sahilmgandhi 18:6a4db94011d3 590 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 591 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 592 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
sahilmgandhi 18:6a4db94011d3 593 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 594 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
sahilmgandhi 18:6a4db94011d3 595 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 596 } while(0)
sahilmgandhi 18:6a4db94011d3 597 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 598 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 599 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
sahilmgandhi 18:6a4db94011d3 600 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 601 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
sahilmgandhi 18:6a4db94011d3 602 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 603 } while(0)
sahilmgandhi 18:6a4db94011d3 604 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 605 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 606 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
sahilmgandhi 18:6a4db94011d3 607 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 608 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
sahilmgandhi 18:6a4db94011d3 609 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 610 } while(0)
sahilmgandhi 18:6a4db94011d3 611 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 612 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 613 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
sahilmgandhi 18:6a4db94011d3 614 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 615 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
sahilmgandhi 18:6a4db94011d3 616 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 617 } while(0)
sahilmgandhi 18:6a4db94011d3 618 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 620 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
sahilmgandhi 18:6a4db94011d3 621 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 622 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
sahilmgandhi 18:6a4db94011d3 623 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 624 } while(0)
sahilmgandhi 18:6a4db94011d3 625 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
sahilmgandhi 18:6a4db94011d3 626 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 627 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
sahilmgandhi 18:6a4db94011d3 628 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 629 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
sahilmgandhi 18:6a4db94011d3 630 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 631 } while(0)
sahilmgandhi 18:6a4db94011d3 632
sahilmgandhi 18:6a4db94011d3 633 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
sahilmgandhi 18:6a4db94011d3 634 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
sahilmgandhi 18:6a4db94011d3 635 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
sahilmgandhi 18:6a4db94011d3 636 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
sahilmgandhi 18:6a4db94011d3 637 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
sahilmgandhi 18:6a4db94011d3 638 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
sahilmgandhi 18:6a4db94011d3 639 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
sahilmgandhi 18:6a4db94011d3 640 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
sahilmgandhi 18:6a4db94011d3 641 /**
sahilmgandhi 18:6a4db94011d3 642 * @}
sahilmgandhi 18:6a4db94011d3 643 */
sahilmgandhi 18:6a4db94011d3 644
sahilmgandhi 18:6a4db94011d3 645 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
sahilmgandhi 18:6a4db94011d3 646 * @brief Get the enable or disable status of the APB2 peripheral clock.
sahilmgandhi 18:6a4db94011d3 647 * @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi 18:6a4db94011d3 648 * is disabled and the application software has to enable this clock before
sahilmgandhi 18:6a4db94011d3 649 * using it.
sahilmgandhi 18:6a4db94011d3 650 * @{
sahilmgandhi 18:6a4db94011d3 651 */
sahilmgandhi 18:6a4db94011d3 652 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 653 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 654 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 655 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 656 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 657 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
sahilmgandhi 18:6a4db94011d3 658 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 659 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 662 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 663 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 664 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 665 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 666 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
sahilmgandhi 18:6a4db94011d3 667 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 668 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
sahilmgandhi 18:6a4db94011d3 669 /**
sahilmgandhi 18:6a4db94011d3 670 * @}
sahilmgandhi 18:6a4db94011d3 671 */
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi 18:6a4db94011d3 674 * @brief Force or release AHB1 peripheral reset.
sahilmgandhi 18:6a4db94011d3 675 * @{
sahilmgandhi 18:6a4db94011d3 676 */
sahilmgandhi 18:6a4db94011d3 677 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
sahilmgandhi 18:6a4db94011d3 678 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
sahilmgandhi 18:6a4db94011d3 679 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
sahilmgandhi 18:6a4db94011d3 680 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
sahilmgandhi 18:6a4db94011d3 681 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
sahilmgandhi 18:6a4db94011d3 682 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
sahilmgandhi 18:6a4db94011d3 683 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
sahilmgandhi 18:6a4db94011d3 686 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
sahilmgandhi 18:6a4db94011d3 687 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
sahilmgandhi 18:6a4db94011d3 688 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
sahilmgandhi 18:6a4db94011d3 689 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
sahilmgandhi 18:6a4db94011d3 690 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
sahilmgandhi 18:6a4db94011d3 691 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
sahilmgandhi 18:6a4db94011d3 692 /**
sahilmgandhi 18:6a4db94011d3 693 * @}
sahilmgandhi 18:6a4db94011d3 694 */
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
sahilmgandhi 18:6a4db94011d3 697 * @brief Force or release APB1 peripheral reset.
sahilmgandhi 18:6a4db94011d3 698 * @{
sahilmgandhi 18:6a4db94011d3 699 */
sahilmgandhi 18:6a4db94011d3 700 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
sahilmgandhi 18:6a4db94011d3 701 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
sahilmgandhi 18:6a4db94011d3 702 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
sahilmgandhi 18:6a4db94011d3 703 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
sahilmgandhi 18:6a4db94011d3 704 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
sahilmgandhi 18:6a4db94011d3 705 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
sahilmgandhi 18:6a4db94011d3 706 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
sahilmgandhi 18:6a4db94011d3 707 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
sahilmgandhi 18:6a4db94011d3 708
sahilmgandhi 18:6a4db94011d3 709 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
sahilmgandhi 18:6a4db94011d3 710 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
sahilmgandhi 18:6a4db94011d3 711 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
sahilmgandhi 18:6a4db94011d3 712 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
sahilmgandhi 18:6a4db94011d3 713 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
sahilmgandhi 18:6a4db94011d3 714 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
sahilmgandhi 18:6a4db94011d3 715 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
sahilmgandhi 18:6a4db94011d3 716 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
sahilmgandhi 18:6a4db94011d3 717 /**
sahilmgandhi 18:6a4db94011d3 718 * @}
sahilmgandhi 18:6a4db94011d3 719 */
sahilmgandhi 18:6a4db94011d3 720
sahilmgandhi 18:6a4db94011d3 721 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
sahilmgandhi 18:6a4db94011d3 722 * @brief Force or release APB2 peripheral reset.
sahilmgandhi 18:6a4db94011d3 723 * @{
sahilmgandhi 18:6a4db94011d3 724 */
sahilmgandhi 18:6a4db94011d3 725 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
sahilmgandhi 18:6a4db94011d3 726 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
sahilmgandhi 18:6a4db94011d3 727 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
sahilmgandhi 18:6a4db94011d3 728 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
sahilmgandhi 18:6a4db94011d3 729 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
sahilmgandhi 18:6a4db94011d3 730 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
sahilmgandhi 18:6a4db94011d3 731 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
sahilmgandhi 18:6a4db94011d3 732 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
sahilmgandhi 18:6a4db94011d3 733 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
sahilmgandhi 18:6a4db94011d3 736 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
sahilmgandhi 18:6a4db94011d3 737 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
sahilmgandhi 18:6a4db94011d3 738 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
sahilmgandhi 18:6a4db94011d3 739 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
sahilmgandhi 18:6a4db94011d3 740 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
sahilmgandhi 18:6a4db94011d3 741 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
sahilmgandhi 18:6a4db94011d3 742 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
sahilmgandhi 18:6a4db94011d3 743 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
sahilmgandhi 18:6a4db94011d3 744 /**
sahilmgandhi 18:6a4db94011d3 745 * @}
sahilmgandhi 18:6a4db94011d3 746 */
sahilmgandhi 18:6a4db94011d3 747
sahilmgandhi 18:6a4db94011d3 748 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi 18:6a4db94011d3 749 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi 18:6a4db94011d3 750 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi 18:6a4db94011d3 751 * power consumption.
sahilmgandhi 18:6a4db94011d3 752 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi 18:6a4db94011d3 753 * @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi 18:6a4db94011d3 754 * @{
sahilmgandhi 18:6a4db94011d3 755 */
sahilmgandhi 18:6a4db94011d3 756 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
sahilmgandhi 18:6a4db94011d3 757 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
sahilmgandhi 18:6a4db94011d3 758 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
sahilmgandhi 18:6a4db94011d3 759 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
sahilmgandhi 18:6a4db94011d3 760 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
sahilmgandhi 18:6a4db94011d3 761 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
sahilmgandhi 18:6a4db94011d3 764 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
sahilmgandhi 18:6a4db94011d3 765 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
sahilmgandhi 18:6a4db94011d3 766 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
sahilmgandhi 18:6a4db94011d3 767 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
sahilmgandhi 18:6a4db94011d3 768 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
sahilmgandhi 18:6a4db94011d3 769 /**
sahilmgandhi 18:6a4db94011d3 770 * @}
sahilmgandhi 18:6a4db94011d3 771 */
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
sahilmgandhi 18:6a4db94011d3 774 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi 18:6a4db94011d3 775 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi 18:6a4db94011d3 776 * power consumption.
sahilmgandhi 18:6a4db94011d3 777 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi 18:6a4db94011d3 778 * @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi 18:6a4db94011d3 779 * @{
sahilmgandhi 18:6a4db94011d3 780 */
sahilmgandhi 18:6a4db94011d3 781 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
sahilmgandhi 18:6a4db94011d3 782 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
sahilmgandhi 18:6a4db94011d3 783 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
sahilmgandhi 18:6a4db94011d3 784 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
sahilmgandhi 18:6a4db94011d3 785 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
sahilmgandhi 18:6a4db94011d3 786 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
sahilmgandhi 18:6a4db94011d3 787 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
sahilmgandhi 18:6a4db94011d3 788
sahilmgandhi 18:6a4db94011d3 789 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
sahilmgandhi 18:6a4db94011d3 790 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
sahilmgandhi 18:6a4db94011d3 791 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
sahilmgandhi 18:6a4db94011d3 792 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
sahilmgandhi 18:6a4db94011d3 793 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
sahilmgandhi 18:6a4db94011d3 794 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
sahilmgandhi 18:6a4db94011d3 795 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
sahilmgandhi 18:6a4db94011d3 796 /**
sahilmgandhi 18:6a4db94011d3 797 * @}
sahilmgandhi 18:6a4db94011d3 798 */
sahilmgandhi 18:6a4db94011d3 799
sahilmgandhi 18:6a4db94011d3 800 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
sahilmgandhi 18:6a4db94011d3 801 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi 18:6a4db94011d3 802 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi 18:6a4db94011d3 803 * power consumption.
sahilmgandhi 18:6a4db94011d3 804 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi 18:6a4db94011d3 805 * @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi 18:6a4db94011d3 806 * @{
sahilmgandhi 18:6a4db94011d3 807 */
sahilmgandhi 18:6a4db94011d3 808 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
sahilmgandhi 18:6a4db94011d3 809 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
sahilmgandhi 18:6a4db94011d3 810 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
sahilmgandhi 18:6a4db94011d3 811 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
sahilmgandhi 18:6a4db94011d3 812 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
sahilmgandhi 18:6a4db94011d3 813 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
sahilmgandhi 18:6a4db94011d3 814 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
sahilmgandhi 18:6a4db94011d3 815 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
sahilmgandhi 18:6a4db94011d3 816
sahilmgandhi 18:6a4db94011d3 817 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
sahilmgandhi 18:6a4db94011d3 818 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
sahilmgandhi 18:6a4db94011d3 819 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
sahilmgandhi 18:6a4db94011d3 820 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
sahilmgandhi 18:6a4db94011d3 821 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
sahilmgandhi 18:6a4db94011d3 822 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
sahilmgandhi 18:6a4db94011d3 823 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
sahilmgandhi 18:6a4db94011d3 824 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
sahilmgandhi 18:6a4db94011d3 825 /**
sahilmgandhi 18:6a4db94011d3 826 * @}
sahilmgandhi 18:6a4db94011d3 827 */
sahilmgandhi 18:6a4db94011d3 828
sahilmgandhi 18:6a4db94011d3 829 /** @defgroup RCC_HSI_Configuration HSI Configuration
sahilmgandhi 18:6a4db94011d3 830 * @{
sahilmgandhi 18:6a4db94011d3 831 */
sahilmgandhi 18:6a4db94011d3 832
sahilmgandhi 18:6a4db94011d3 833 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
sahilmgandhi 18:6a4db94011d3 834 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
sahilmgandhi 18:6a4db94011d3 835 * It is used (enabled by hardware) as system clock source after startup
sahilmgandhi 18:6a4db94011d3 836 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
sahilmgandhi 18:6a4db94011d3 837 * of the HSE used directly or indirectly as system clock (if the Clock
sahilmgandhi 18:6a4db94011d3 838 * Security System CSS is enabled).
sahilmgandhi 18:6a4db94011d3 839 * @note HSI can not be stopped if it is used as system clock source. In this case,
sahilmgandhi 18:6a4db94011d3 840 * you have to select another source of the system clock then stop the HSI.
sahilmgandhi 18:6a4db94011d3 841 * @note After enabling the HSI, the application software should wait on HSIRDY
sahilmgandhi 18:6a4db94011d3 842 * flag to be set indicating that HSI clock is stable and can be used as
sahilmgandhi 18:6a4db94011d3 843 * system clock source.
sahilmgandhi 18:6a4db94011d3 844 * This parameter can be: ENABLE or DISABLE.
sahilmgandhi 18:6a4db94011d3 845 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
sahilmgandhi 18:6a4db94011d3 846 * clock cycles.
sahilmgandhi 18:6a4db94011d3 847 */
sahilmgandhi 18:6a4db94011d3 848 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
sahilmgandhi 18:6a4db94011d3 849 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
sahilmgandhi 18:6a4db94011d3 850
sahilmgandhi 18:6a4db94011d3 851 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
sahilmgandhi 18:6a4db94011d3 852 * @note The calibration is used to compensate for the variations in voltage
sahilmgandhi 18:6a4db94011d3 853 * and temperature that influence the frequency of the internal HSI RC.
sahilmgandhi 18:6a4db94011d3 854 * @param __HSICalibrationValue__: specifies the calibration trimming value.
sahilmgandhi 18:6a4db94011d3 855 * (default is RCC_HSICALIBRATION_DEFAULT).
sahilmgandhi 18:6a4db94011d3 856 * This parameter must be a number between 0 and 0x1F.
sahilmgandhi 18:6a4db94011d3 857 */
sahilmgandhi 18:6a4db94011d3 858 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
sahilmgandhi 18:6a4db94011d3 859 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
sahilmgandhi 18:6a4db94011d3 860 /**
sahilmgandhi 18:6a4db94011d3 861 * @}
sahilmgandhi 18:6a4db94011d3 862 */
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 /** @defgroup RCC_LSI_Configuration LSI Configuration
sahilmgandhi 18:6a4db94011d3 865 * @{
sahilmgandhi 18:6a4db94011d3 866 */
sahilmgandhi 18:6a4db94011d3 867
sahilmgandhi 18:6a4db94011d3 868 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
sahilmgandhi 18:6a4db94011d3 869 * @note After enabling the LSI, the application software should wait on
sahilmgandhi 18:6a4db94011d3 870 * LSIRDY flag to be set indicating that LSI clock is stable and can
sahilmgandhi 18:6a4db94011d3 871 * be used to clock the IWDG and/or the RTC.
sahilmgandhi 18:6a4db94011d3 872 * @note LSI can not be disabled if the IWDG is running.
sahilmgandhi 18:6a4db94011d3 873 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
sahilmgandhi 18:6a4db94011d3 874 * clock cycles.
sahilmgandhi 18:6a4db94011d3 875 */
sahilmgandhi 18:6a4db94011d3 876 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
sahilmgandhi 18:6a4db94011d3 877 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
sahilmgandhi 18:6a4db94011d3 878 /**
sahilmgandhi 18:6a4db94011d3 879 * @}
sahilmgandhi 18:6a4db94011d3 880 */
sahilmgandhi 18:6a4db94011d3 881
sahilmgandhi 18:6a4db94011d3 882 /** @defgroup RCC_HSE_Configuration HSE Configuration
sahilmgandhi 18:6a4db94011d3 883 * @{
sahilmgandhi 18:6a4db94011d3 884 */
sahilmgandhi 18:6a4db94011d3 885
sahilmgandhi 18:6a4db94011d3 886 /**
sahilmgandhi 18:6a4db94011d3 887 * @brief Macro to configure the External High Speed oscillator (HSE).
sahilmgandhi 18:6a4db94011d3 888 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
sahilmgandhi 18:6a4db94011d3 889 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
sahilmgandhi 18:6a4db94011d3 890 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
sahilmgandhi 18:6a4db94011d3 891 * software should wait on HSERDY flag to be set indicating that HSE clock
sahilmgandhi 18:6a4db94011d3 892 * is stable and can be used to clock the PLL and/or system clock.
sahilmgandhi 18:6a4db94011d3 893 * @note HSE state can not be changed if it is used directly or through the
sahilmgandhi 18:6a4db94011d3 894 * PLL as system clock. In this case, you have to select another source
sahilmgandhi 18:6a4db94011d3 895 * of the system clock then change the HSE state (ex. disable it).
sahilmgandhi 18:6a4db94011d3 896 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
sahilmgandhi 18:6a4db94011d3 897 * @note This function reset the CSSON bit, so if the clock security system(CSS)
sahilmgandhi 18:6a4db94011d3 898 * was previously enabled you have to enable it again after calling this
sahilmgandhi 18:6a4db94011d3 899 * function.
sahilmgandhi 18:6a4db94011d3 900 * @param __STATE__: specifies the new state of the HSE.
sahilmgandhi 18:6a4db94011d3 901 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 902 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
sahilmgandhi 18:6a4db94011d3 903 * 6 HSE oscillator clock cycles.
sahilmgandhi 18:6a4db94011d3 904 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
sahilmgandhi 18:6a4db94011d3 905 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
sahilmgandhi 18:6a4db94011d3 906 */
sahilmgandhi 18:6a4db94011d3 907 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
sahilmgandhi 18:6a4db94011d3 908 /**
sahilmgandhi 18:6a4db94011d3 909 * @}
sahilmgandhi 18:6a4db94011d3 910 */
sahilmgandhi 18:6a4db94011d3 911
sahilmgandhi 18:6a4db94011d3 912 /** @defgroup RCC_LSE_Configuration LSE Configuration
sahilmgandhi 18:6a4db94011d3 913 * @{
sahilmgandhi 18:6a4db94011d3 914 */
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 /**
sahilmgandhi 18:6a4db94011d3 917 * @brief Macro to configure the External Low Speed oscillator (LSE).
sahilmgandhi 18:6a4db94011d3 918 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
sahilmgandhi 18:6a4db94011d3 919 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
sahilmgandhi 18:6a4db94011d3 920 * @note As the LSE is in the Backup domain and write access is denied to
sahilmgandhi 18:6a4db94011d3 921 * this domain after reset, you have to enable write access using
sahilmgandhi 18:6a4db94011d3 922 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
sahilmgandhi 18:6a4db94011d3 923 * (to be done once after reset).
sahilmgandhi 18:6a4db94011d3 924 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
sahilmgandhi 18:6a4db94011d3 925 * software should wait on LSERDY flag to be set indicating that LSE clock
sahilmgandhi 18:6a4db94011d3 926 * is stable and can be used to clock the RTC.
sahilmgandhi 18:6a4db94011d3 927 * @param __STATE__: specifies the new state of the LSE.
sahilmgandhi 18:6a4db94011d3 928 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 929 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
sahilmgandhi 18:6a4db94011d3 930 * 6 LSE oscillator clock cycles.
sahilmgandhi 18:6a4db94011d3 931 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
sahilmgandhi 18:6a4db94011d3 932 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
sahilmgandhi 18:6a4db94011d3 933 */
sahilmgandhi 18:6a4db94011d3 934 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936 /**
sahilmgandhi 18:6a4db94011d3 937 * @}
sahilmgandhi 18:6a4db94011d3 938 */
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
sahilmgandhi 18:6a4db94011d3 941 * @{
sahilmgandhi 18:6a4db94011d3 942 */
sahilmgandhi 18:6a4db94011d3 943
sahilmgandhi 18:6a4db94011d3 944 /** @brief Macros to enable or disable the RTC clock.
sahilmgandhi 18:6a4db94011d3 945 * @note These macros must be used only after the RTC clock source was selected.
sahilmgandhi 18:6a4db94011d3 946 */
sahilmgandhi 18:6a4db94011d3 947 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
sahilmgandhi 18:6a4db94011d3 948 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
sahilmgandhi 18:6a4db94011d3 949
sahilmgandhi 18:6a4db94011d3 950 /** @brief Macros to configure the RTC clock (RTCCLK).
sahilmgandhi 18:6a4db94011d3 951 * @note As the RTC clock configuration bits are in the Backup domain and write
sahilmgandhi 18:6a4db94011d3 952 * access is denied to this domain after reset, you have to enable write
sahilmgandhi 18:6a4db94011d3 953 * access using the Power Backup Access macro before to configure
sahilmgandhi 18:6a4db94011d3 954 * the RTC clock source (to be done once after reset).
sahilmgandhi 18:6a4db94011d3 955 * @note Once the RTC clock is configured it can't be changed unless the
sahilmgandhi 18:6a4db94011d3 956 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
sahilmgandhi 18:6a4db94011d3 957 * a Power On Reset (POR).
sahilmgandhi 18:6a4db94011d3 958 * @param __RTCCLKSource__: specifies the RTC clock source.
sahilmgandhi 18:6a4db94011d3 959 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 960 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
sahilmgandhi 18:6a4db94011d3 961 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
sahilmgandhi 18:6a4db94011d3 962 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
sahilmgandhi 18:6a4db94011d3 963 * as RTC clock, where x:[2,31]
sahilmgandhi 18:6a4db94011d3 964 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
sahilmgandhi 18:6a4db94011d3 965 * work in STOP and STANDBY modes, and can be used as wake-up source.
sahilmgandhi 18:6a4db94011d3 966 * However, when the HSE clock is used as RTC clock source, the RTC
sahilmgandhi 18:6a4db94011d3 967 * cannot be used in STOP and STANDBY modes.
sahilmgandhi 18:6a4db94011d3 968 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
sahilmgandhi 18:6a4db94011d3 969 * RTC clock source).
sahilmgandhi 18:6a4db94011d3 970 */
sahilmgandhi 18:6a4db94011d3 971 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
sahilmgandhi 18:6a4db94011d3 972 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
sahilmgandhi 18:6a4db94011d3 973
sahilmgandhi 18:6a4db94011d3 974 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
sahilmgandhi 18:6a4db94011d3 975 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
sahilmgandhi 18:6a4db94011d3 976 } while (0)
sahilmgandhi 18:6a4db94011d3 977
sahilmgandhi 18:6a4db94011d3 978 /** @brief Macros to force or release the Backup domain reset.
sahilmgandhi 18:6a4db94011d3 979 * @note This function resets the RTC peripheral (including the backup registers)
sahilmgandhi 18:6a4db94011d3 980 * and the RTC clock source selection in RCC_CSR register.
sahilmgandhi 18:6a4db94011d3 981 * @note The BKPSRAM is not affected by this reset.
sahilmgandhi 18:6a4db94011d3 982 */
sahilmgandhi 18:6a4db94011d3 983 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
sahilmgandhi 18:6a4db94011d3 984 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
sahilmgandhi 18:6a4db94011d3 985 /**
sahilmgandhi 18:6a4db94011d3 986 * @}
sahilmgandhi 18:6a4db94011d3 987 */
sahilmgandhi 18:6a4db94011d3 988
sahilmgandhi 18:6a4db94011d3 989 /** @defgroup RCC_PLL_Configuration PLL Configuration
sahilmgandhi 18:6a4db94011d3 990 * @{
sahilmgandhi 18:6a4db94011d3 991 */
sahilmgandhi 18:6a4db94011d3 992
sahilmgandhi 18:6a4db94011d3 993 /** @brief Macros to enable or disable the main PLL.
sahilmgandhi 18:6a4db94011d3 994 * @note After enabling the main PLL, the application software should wait on
sahilmgandhi 18:6a4db94011d3 995 * PLLRDY flag to be set indicating that PLL clock is stable and can
sahilmgandhi 18:6a4db94011d3 996 * be used as system clock source.
sahilmgandhi 18:6a4db94011d3 997 * @note The main PLL can not be disabled if it is used as system clock source
sahilmgandhi 18:6a4db94011d3 998 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
sahilmgandhi 18:6a4db94011d3 999 */
sahilmgandhi 18:6a4db94011d3 1000 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
sahilmgandhi 18:6a4db94011d3 1001 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 /** @brief Macro to configure the PLL clock source.
sahilmgandhi 18:6a4db94011d3 1004 * @note This function must be used only when the main PLL is disabled.
sahilmgandhi 18:6a4db94011d3 1005 * @param __PLLSOURCE__: specifies the PLL entry clock source.
sahilmgandhi 18:6a4db94011d3 1006 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1007 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
sahilmgandhi 18:6a4db94011d3 1008 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
sahilmgandhi 18:6a4db94011d3 1009 *
sahilmgandhi 18:6a4db94011d3 1010 */
sahilmgandhi 18:6a4db94011d3 1011 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 /** @brief Macro to configure the PLL multiplication factor.
sahilmgandhi 18:6a4db94011d3 1014 * @note This function must be used only when the main PLL is disabled.
sahilmgandhi 18:6a4db94011d3 1015 * @param __PLLM__: specifies the division factor for PLL VCO input clock
sahilmgandhi 18:6a4db94011d3 1016 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
sahilmgandhi 18:6a4db94011d3 1017 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
sahilmgandhi 18:6a4db94011d3 1018 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
sahilmgandhi 18:6a4db94011d3 1019 * of 2 MHz to limit PLL jitter.
sahilmgandhi 18:6a4db94011d3 1020 *
sahilmgandhi 18:6a4db94011d3 1021 */
sahilmgandhi 18:6a4db94011d3 1022 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
sahilmgandhi 18:6a4db94011d3 1023 /**
sahilmgandhi 18:6a4db94011d3 1024 * @}
sahilmgandhi 18:6a4db94011d3 1025 */
sahilmgandhi 18:6a4db94011d3 1026
sahilmgandhi 18:6a4db94011d3 1027 /** @defgroup RCC_Get_Clock_source Get Clock source
sahilmgandhi 18:6a4db94011d3 1028 * @{
sahilmgandhi 18:6a4db94011d3 1029 */
sahilmgandhi 18:6a4db94011d3 1030 /**
sahilmgandhi 18:6a4db94011d3 1031 * @brief Macro to configure the system clock source.
sahilmgandhi 18:6a4db94011d3 1032 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
sahilmgandhi 18:6a4db94011d3 1033 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1034 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
sahilmgandhi 18:6a4db94011d3 1035 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
sahilmgandhi 18:6a4db94011d3 1036 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
sahilmgandhi 18:6a4db94011d3 1037 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
sahilmgandhi 18:6a4db94011d3 1038 */
sahilmgandhi 18:6a4db94011d3 1039 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041 /** @brief Macro to get the clock source used as system clock.
sahilmgandhi 18:6a4db94011d3 1042 * @retval The clock source used as system clock. The returned value can be one
sahilmgandhi 18:6a4db94011d3 1043 * of the following:
sahilmgandhi 18:6a4db94011d3 1044 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
sahilmgandhi 18:6a4db94011d3 1045 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
sahilmgandhi 18:6a4db94011d3 1046 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
sahilmgandhi 18:6a4db94011d3 1047 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
sahilmgandhi 18:6a4db94011d3 1048 */
sahilmgandhi 18:6a4db94011d3 1049 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
sahilmgandhi 18:6a4db94011d3 1050
sahilmgandhi 18:6a4db94011d3 1051 /** @brief Macro to get the oscillator used as PLL clock source.
sahilmgandhi 18:6a4db94011d3 1052 * @retval The oscillator used as PLL clock source. The returned value can be one
sahilmgandhi 18:6a4db94011d3 1053 * of the following:
sahilmgandhi 18:6a4db94011d3 1054 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
sahilmgandhi 18:6a4db94011d3 1055 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
sahilmgandhi 18:6a4db94011d3 1056 */
sahilmgandhi 18:6a4db94011d3 1057 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
sahilmgandhi 18:6a4db94011d3 1058 /**
sahilmgandhi 18:6a4db94011d3 1059 * @}
sahilmgandhi 18:6a4db94011d3 1060 */
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
sahilmgandhi 18:6a4db94011d3 1063 * @{
sahilmgandhi 18:6a4db94011d3 1064 */
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 /** @brief Macro to configure the MCO1 clock.
sahilmgandhi 18:6a4db94011d3 1067 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
sahilmgandhi 18:6a4db94011d3 1068 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1069 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 1070 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 1071 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 1072 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 1073 * @param __MCODIV__ specifies the MCO clock prescaler.
sahilmgandhi 18:6a4db94011d3 1074 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1075 * @arg RCC_MCODIV_1: no division applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1076 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1077 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1078 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1079 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1080 */
sahilmgandhi 18:6a4db94011d3 1081 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
sahilmgandhi 18:6a4db94011d3 1082 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
sahilmgandhi 18:6a4db94011d3 1083
sahilmgandhi 18:6a4db94011d3 1084 /** @brief Macro to configure the MCO2 clock.
sahilmgandhi 18:6a4db94011d3 1085 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
sahilmgandhi 18:6a4db94011d3 1086 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1087 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 1088 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
sahilmgandhi 18:6a4db94011d3 1089 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
sahilmgandhi 18:6a4db94011d3 1090 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 1091 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 1092 * @param __MCODIV__ specifies the MCO clock prescaler.
sahilmgandhi 18:6a4db94011d3 1093 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1094 * @arg RCC_MCODIV_1: no division applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1095 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1096 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1097 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1098 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 1099 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
sahilmgandhi 18:6a4db94011d3 1100 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
sahilmgandhi 18:6a4db94011d3 1101 */
sahilmgandhi 18:6a4db94011d3 1102 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
sahilmgandhi 18:6a4db94011d3 1103 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
sahilmgandhi 18:6a4db94011d3 1104 /**
sahilmgandhi 18:6a4db94011d3 1105 * @}
sahilmgandhi 18:6a4db94011d3 1106 */
sahilmgandhi 18:6a4db94011d3 1107
sahilmgandhi 18:6a4db94011d3 1108 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
sahilmgandhi 18:6a4db94011d3 1109 * @brief macros to manage the specified RCC Flags and interrupts.
sahilmgandhi 18:6a4db94011d3 1110 * @{
sahilmgandhi 18:6a4db94011d3 1111 */
sahilmgandhi 18:6a4db94011d3 1112
sahilmgandhi 18:6a4db94011d3 1113 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
sahilmgandhi 18:6a4db94011d3 1114 * the selected interrupts).
sahilmgandhi 18:6a4db94011d3 1115 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
sahilmgandhi 18:6a4db94011d3 1116 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1117 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
sahilmgandhi 18:6a4db94011d3 1118 * @arg RCC_IT_LSERDY: LSE ready interrupt.
sahilmgandhi 18:6a4db94011d3 1119 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
sahilmgandhi 18:6a4db94011d3 1120 * @arg RCC_IT_HSERDY: HSE ready interrupt.
sahilmgandhi 18:6a4db94011d3 1121 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
sahilmgandhi 18:6a4db94011d3 1122 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
sahilmgandhi 18:6a4db94011d3 1123 */
sahilmgandhi 18:6a4db94011d3 1124 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 1125
sahilmgandhi 18:6a4db94011d3 1126 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
sahilmgandhi 18:6a4db94011d3 1127 * the selected interrupts).
sahilmgandhi 18:6a4db94011d3 1128 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
sahilmgandhi 18:6a4db94011d3 1129 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1130 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
sahilmgandhi 18:6a4db94011d3 1131 * @arg RCC_IT_LSERDY: LSE ready interrupt.
sahilmgandhi 18:6a4db94011d3 1132 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
sahilmgandhi 18:6a4db94011d3 1133 * @arg RCC_IT_HSERDY: HSE ready interrupt.
sahilmgandhi 18:6a4db94011d3 1134 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
sahilmgandhi 18:6a4db94011d3 1135 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
sahilmgandhi 18:6a4db94011d3 1136 */
sahilmgandhi 18:6a4db94011d3 1137 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 1138
sahilmgandhi 18:6a4db94011d3 1139 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
sahilmgandhi 18:6a4db94011d3 1140 * bits to clear the selected interrupt pending bits.
sahilmgandhi 18:6a4db94011d3 1141 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
sahilmgandhi 18:6a4db94011d3 1142 * This parameter can be any combination of the following values:
sahilmgandhi 18:6a4db94011d3 1143 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
sahilmgandhi 18:6a4db94011d3 1144 * @arg RCC_IT_LSERDY: LSE ready interrupt.
sahilmgandhi 18:6a4db94011d3 1145 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
sahilmgandhi 18:6a4db94011d3 1146 * @arg RCC_IT_HSERDY: HSE ready interrupt.
sahilmgandhi 18:6a4db94011d3 1147 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
sahilmgandhi 18:6a4db94011d3 1148 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
sahilmgandhi 18:6a4db94011d3 1149 * @arg RCC_IT_CSS: Clock Security System interrupt
sahilmgandhi 18:6a4db94011d3 1150 */
sahilmgandhi 18:6a4db94011d3 1151 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 1152
sahilmgandhi 18:6a4db94011d3 1153 /** @brief Check the RCC's interrupt has occurred or not.
sahilmgandhi 18:6a4db94011d3 1154 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
sahilmgandhi 18:6a4db94011d3 1155 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1156 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
sahilmgandhi 18:6a4db94011d3 1157 * @arg RCC_IT_LSERDY: LSE ready interrupt.
sahilmgandhi 18:6a4db94011d3 1158 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
sahilmgandhi 18:6a4db94011d3 1159 * @arg RCC_IT_HSERDY: HSE ready interrupt.
sahilmgandhi 18:6a4db94011d3 1160 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
sahilmgandhi 18:6a4db94011d3 1161 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
sahilmgandhi 18:6a4db94011d3 1162 * @arg RCC_IT_CSS: Clock Security System interrupt
sahilmgandhi 18:6a4db94011d3 1163 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
sahilmgandhi 18:6a4db94011d3 1164 */
sahilmgandhi 18:6a4db94011d3 1165 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
sahilmgandhi 18:6a4db94011d3 1166
sahilmgandhi 18:6a4db94011d3 1167 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
sahilmgandhi 18:6a4db94011d3 1168 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
sahilmgandhi 18:6a4db94011d3 1169 */
sahilmgandhi 18:6a4db94011d3 1170 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
sahilmgandhi 18:6a4db94011d3 1171
sahilmgandhi 18:6a4db94011d3 1172 /** @brief Check RCC flag is set or not.
sahilmgandhi 18:6a4db94011d3 1173 * @param __FLAG__: specifies the flag to check.
sahilmgandhi 18:6a4db94011d3 1174 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1175 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
sahilmgandhi 18:6a4db94011d3 1176 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
sahilmgandhi 18:6a4db94011d3 1177 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
sahilmgandhi 18:6a4db94011d3 1178 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
sahilmgandhi 18:6a4db94011d3 1179 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
sahilmgandhi 18:6a4db94011d3 1180 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
sahilmgandhi 18:6a4db94011d3 1181 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
sahilmgandhi 18:6a4db94011d3 1182 * @arg RCC_FLAG_PINRST: Pin reset.
sahilmgandhi 18:6a4db94011d3 1183 * @arg RCC_FLAG_PORRST: POR/PDR reset.
sahilmgandhi 18:6a4db94011d3 1184 * @arg RCC_FLAG_SFTRST: Software reset.
sahilmgandhi 18:6a4db94011d3 1185 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
sahilmgandhi 18:6a4db94011d3 1186 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
sahilmgandhi 18:6a4db94011d3 1187 * @arg RCC_FLAG_LPWRRST: Low Power reset.
sahilmgandhi 18:6a4db94011d3 1188 * @retval The new state of __FLAG__ (TRUE or FALSE).
sahilmgandhi 18:6a4db94011d3 1189 */
sahilmgandhi 18:6a4db94011d3 1190 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
sahilmgandhi 18:6a4db94011d3 1191 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
sahilmgandhi 18:6a4db94011d3 1192
sahilmgandhi 18:6a4db94011d3 1193 /**
sahilmgandhi 18:6a4db94011d3 1194 * @}
sahilmgandhi 18:6a4db94011d3 1195 */
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 /**
sahilmgandhi 18:6a4db94011d3 1198 * @}
sahilmgandhi 18:6a4db94011d3 1199 */
sahilmgandhi 18:6a4db94011d3 1200
sahilmgandhi 18:6a4db94011d3 1201 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1202 /** @addtogroup RCC_Exported_Functions
sahilmgandhi 18:6a4db94011d3 1203 * @{
sahilmgandhi 18:6a4db94011d3 1204 */
sahilmgandhi 18:6a4db94011d3 1205
sahilmgandhi 18:6a4db94011d3 1206 /** @addtogroup RCC_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 1207 * @{
sahilmgandhi 18:6a4db94011d3 1208 */
sahilmgandhi 18:6a4db94011d3 1209 /* Initialization and de-initialization functions ******************************/
sahilmgandhi 18:6a4db94011d3 1210 void HAL_RCC_DeInit(void);
sahilmgandhi 18:6a4db94011d3 1211 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
sahilmgandhi 18:6a4db94011d3 1212 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
sahilmgandhi 18:6a4db94011d3 1213 /**
sahilmgandhi 18:6a4db94011d3 1214 * @}
sahilmgandhi 18:6a4db94011d3 1215 */
sahilmgandhi 18:6a4db94011d3 1216
sahilmgandhi 18:6a4db94011d3 1217 /** @addtogroup RCC_Exported_Functions_Group2
sahilmgandhi 18:6a4db94011d3 1218 * @{
sahilmgandhi 18:6a4db94011d3 1219 */
sahilmgandhi 18:6a4db94011d3 1220 /* Peripheral Control functions ************************************************/
sahilmgandhi 18:6a4db94011d3 1221 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
sahilmgandhi 18:6a4db94011d3 1222 void HAL_RCC_EnableCSS(void);
sahilmgandhi 18:6a4db94011d3 1223 void HAL_RCC_DisableCSS(void);
sahilmgandhi 18:6a4db94011d3 1224 uint32_t HAL_RCC_GetSysClockFreq(void);
sahilmgandhi 18:6a4db94011d3 1225 uint32_t HAL_RCC_GetHCLKFreq(void);
sahilmgandhi 18:6a4db94011d3 1226 uint32_t HAL_RCC_GetPCLK1Freq(void);
sahilmgandhi 18:6a4db94011d3 1227 uint32_t HAL_RCC_GetPCLK2Freq(void);
sahilmgandhi 18:6a4db94011d3 1228 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
sahilmgandhi 18:6a4db94011d3 1229 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
sahilmgandhi 18:6a4db94011d3 1230
sahilmgandhi 18:6a4db94011d3 1231 /* CSS NMI IRQ handler */
sahilmgandhi 18:6a4db94011d3 1232 void HAL_RCC_NMI_IRQHandler(void);
sahilmgandhi 18:6a4db94011d3 1233
sahilmgandhi 18:6a4db94011d3 1234 /* User Callbacks in non blocking mode (IT mode) */
sahilmgandhi 18:6a4db94011d3 1235 void HAL_RCC_CSSCallback(void);
sahilmgandhi 18:6a4db94011d3 1236
sahilmgandhi 18:6a4db94011d3 1237 /**
sahilmgandhi 18:6a4db94011d3 1238 * @}
sahilmgandhi 18:6a4db94011d3 1239 */
sahilmgandhi 18:6a4db94011d3 1240
sahilmgandhi 18:6a4db94011d3 1241 /**
sahilmgandhi 18:6a4db94011d3 1242 * @}
sahilmgandhi 18:6a4db94011d3 1243 */
sahilmgandhi 18:6a4db94011d3 1244
sahilmgandhi 18:6a4db94011d3 1245 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1246 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1247 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1248 /** @defgroup RCC_Private_Constants RCC Private Constants
sahilmgandhi 18:6a4db94011d3 1249 * @{
sahilmgandhi 18:6a4db94011d3 1250 */
sahilmgandhi 18:6a4db94011d3 1251
sahilmgandhi 18:6a4db94011d3 1252 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
sahilmgandhi 18:6a4db94011d3 1253 * @brief RCC registers bit address in the alias region
sahilmgandhi 18:6a4db94011d3 1254 * @{
sahilmgandhi 18:6a4db94011d3 1255 */
sahilmgandhi 18:6a4db94011d3 1256 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
sahilmgandhi 18:6a4db94011d3 1257 /* --- CR Register ---*/
sahilmgandhi 18:6a4db94011d3 1258 /* Alias word address of HSION bit */
sahilmgandhi 18:6a4db94011d3 1259 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
sahilmgandhi 18:6a4db94011d3 1260 #define RCC_HSION_BIT_NUMBER 0x00U
sahilmgandhi 18:6a4db94011d3 1261 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 1262 /* Alias word address of CSSON bit */
sahilmgandhi 18:6a4db94011d3 1263 #define RCC_CSSON_BIT_NUMBER 0x13U
sahilmgandhi 18:6a4db94011d3 1264 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 1265 /* Alias word address of PLLON bit */
sahilmgandhi 18:6a4db94011d3 1266 #define RCC_PLLON_BIT_NUMBER 0x18U
sahilmgandhi 18:6a4db94011d3 1267 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 1268
sahilmgandhi 18:6a4db94011d3 1269 /* --- BDCR Register ---*/
sahilmgandhi 18:6a4db94011d3 1270 /* Alias word address of RTCEN bit */
sahilmgandhi 18:6a4db94011d3 1271 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
sahilmgandhi 18:6a4db94011d3 1272 #define RCC_RTCEN_BIT_NUMBER 0x0FU
sahilmgandhi 18:6a4db94011d3 1273 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 1274 /* Alias word address of BDRST bit */
sahilmgandhi 18:6a4db94011d3 1275 #define RCC_BDRST_BIT_NUMBER 0x10U
sahilmgandhi 18:6a4db94011d3 1276 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 1277
sahilmgandhi 18:6a4db94011d3 1278 /* --- CSR Register ---*/
sahilmgandhi 18:6a4db94011d3 1279 /* Alias word address of LSION bit */
sahilmgandhi 18:6a4db94011d3 1280 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
sahilmgandhi 18:6a4db94011d3 1281 #define RCC_LSION_BIT_NUMBER 0x00U
sahilmgandhi 18:6a4db94011d3 1282 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 1283
sahilmgandhi 18:6a4db94011d3 1284 /* CR register byte 3 (Bits[23:16]) base address */
sahilmgandhi 18:6a4db94011d3 1285 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
sahilmgandhi 18:6a4db94011d3 1286
sahilmgandhi 18:6a4db94011d3 1287 /* CIR register byte 2 (Bits[15:8]) base address */
sahilmgandhi 18:6a4db94011d3 1288 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
sahilmgandhi 18:6a4db94011d3 1289
sahilmgandhi 18:6a4db94011d3 1290 /* CIR register byte 3 (Bits[23:16]) base address */
sahilmgandhi 18:6a4db94011d3 1291 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
sahilmgandhi 18:6a4db94011d3 1292
sahilmgandhi 18:6a4db94011d3 1293 /* BDCR register base address */
sahilmgandhi 18:6a4db94011d3 1294 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
sahilmgandhi 18:6a4db94011d3 1295
sahilmgandhi 18:6a4db94011d3 1296 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
sahilmgandhi 18:6a4db94011d3 1297 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
sahilmgandhi 18:6a4db94011d3 1298
sahilmgandhi 18:6a4db94011d3 1299 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
sahilmgandhi 18:6a4db94011d3 1300 #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
sahilmgandhi 18:6a4db94011d3 1301 #define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
sahilmgandhi 18:6a4db94011d3 1302
sahilmgandhi 18:6a4db94011d3 1303 /**
sahilmgandhi 18:6a4db94011d3 1304 * @}
sahilmgandhi 18:6a4db94011d3 1305 */
sahilmgandhi 18:6a4db94011d3 1306
sahilmgandhi 18:6a4db94011d3 1307 /**
sahilmgandhi 18:6a4db94011d3 1308 * @}
sahilmgandhi 18:6a4db94011d3 1309 */
sahilmgandhi 18:6a4db94011d3 1310
sahilmgandhi 18:6a4db94011d3 1311 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1312 /** @defgroup RCC_Private_Macros RCC Private Macros
sahilmgandhi 18:6a4db94011d3 1313 * @{
sahilmgandhi 18:6a4db94011d3 1314 */
sahilmgandhi 18:6a4db94011d3 1315
sahilmgandhi 18:6a4db94011d3 1316 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
sahilmgandhi 18:6a4db94011d3 1317 * @{
sahilmgandhi 18:6a4db94011d3 1318 */
sahilmgandhi 18:6a4db94011d3 1319 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
sahilmgandhi 18:6a4db94011d3 1320
sahilmgandhi 18:6a4db94011d3 1321 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
sahilmgandhi 18:6a4db94011d3 1322 ((HSE) == RCC_HSE_BYPASS))
sahilmgandhi 18:6a4db94011d3 1323
sahilmgandhi 18:6a4db94011d3 1324 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
sahilmgandhi 18:6a4db94011d3 1325 ((LSE) == RCC_LSE_BYPASS))
sahilmgandhi 18:6a4db94011d3 1326
sahilmgandhi 18:6a4db94011d3 1327 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
sahilmgandhi 18:6a4db94011d3 1328
sahilmgandhi 18:6a4db94011d3 1329 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
sahilmgandhi 18:6a4db94011d3 1330
sahilmgandhi 18:6a4db94011d3 1331 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
sahilmgandhi 18:6a4db94011d3 1332
sahilmgandhi 18:6a4db94011d3 1333 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
sahilmgandhi 18:6a4db94011d3 1334 ((SOURCE) == RCC_PLLSOURCE_HSE))
sahilmgandhi 18:6a4db94011d3 1335
sahilmgandhi 18:6a4db94011d3 1336 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
sahilmgandhi 18:6a4db94011d3 1337 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
sahilmgandhi 18:6a4db94011d3 1338 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
sahilmgandhi 18:6a4db94011d3 1339 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
sahilmgandhi 18:6a4db94011d3 1340
sahilmgandhi 18:6a4db94011d3 1341 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
sahilmgandhi 18:6a4db94011d3 1342 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
sahilmgandhi 18:6a4db94011d3 1343 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
sahilmgandhi 18:6a4db94011d3 1344 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
sahilmgandhi 18:6a4db94011d3 1345 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
sahilmgandhi 18:6a4db94011d3 1346 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
sahilmgandhi 18:6a4db94011d3 1347 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
sahilmgandhi 18:6a4db94011d3 1348 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
sahilmgandhi 18:6a4db94011d3 1349 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
sahilmgandhi 18:6a4db94011d3 1350 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
sahilmgandhi 18:6a4db94011d3 1351 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
sahilmgandhi 18:6a4db94011d3 1352 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
sahilmgandhi 18:6a4db94011d3 1353 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
sahilmgandhi 18:6a4db94011d3 1354 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
sahilmgandhi 18:6a4db94011d3 1355 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
sahilmgandhi 18:6a4db94011d3 1356 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
sahilmgandhi 18:6a4db94011d3 1357 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
sahilmgandhi 18:6a4db94011d3 1358 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
sahilmgandhi 18:6a4db94011d3 1359 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
sahilmgandhi 18:6a4db94011d3 1360 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
sahilmgandhi 18:6a4db94011d3 1361 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
sahilmgandhi 18:6a4db94011d3 1362 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
sahilmgandhi 18:6a4db94011d3 1363 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
sahilmgandhi 18:6a4db94011d3 1364 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
sahilmgandhi 18:6a4db94011d3 1365 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
sahilmgandhi 18:6a4db94011d3 1366 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
sahilmgandhi 18:6a4db94011d3 1367 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
sahilmgandhi 18:6a4db94011d3 1368 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
sahilmgandhi 18:6a4db94011d3 1369 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
sahilmgandhi 18:6a4db94011d3 1370 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
sahilmgandhi 18:6a4db94011d3 1371 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
sahilmgandhi 18:6a4db94011d3 1372 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
sahilmgandhi 18:6a4db94011d3 1373
sahilmgandhi 18:6a4db94011d3 1374 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
sahilmgandhi 18:6a4db94011d3 1375
sahilmgandhi 18:6a4db94011d3 1376 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
sahilmgandhi 18:6a4db94011d3 1377
sahilmgandhi 18:6a4db94011d3 1378 #define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
sahilmgandhi 18:6a4db94011d3 1379
sahilmgandhi 18:6a4db94011d3 1380 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
sahilmgandhi 18:6a4db94011d3 1381 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
sahilmgandhi 18:6a4db94011d3 1382 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
sahilmgandhi 18:6a4db94011d3 1383 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
sahilmgandhi 18:6a4db94011d3 1384 ((HCLK) == RCC_SYSCLK_DIV512))
sahilmgandhi 18:6a4db94011d3 1385
sahilmgandhi 18:6a4db94011d3 1386 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
sahilmgandhi 18:6a4db94011d3 1387
sahilmgandhi 18:6a4db94011d3 1388 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
sahilmgandhi 18:6a4db94011d3 1389 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
sahilmgandhi 18:6a4db94011d3 1390 ((PCLK) == RCC_HCLK_DIV16))
sahilmgandhi 18:6a4db94011d3 1391
sahilmgandhi 18:6a4db94011d3 1392 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
sahilmgandhi 18:6a4db94011d3 1393
sahilmgandhi 18:6a4db94011d3 1394 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
sahilmgandhi 18:6a4db94011d3 1395 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
sahilmgandhi 18:6a4db94011d3 1396
sahilmgandhi 18:6a4db94011d3 1397 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
sahilmgandhi 18:6a4db94011d3 1398 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
sahilmgandhi 18:6a4db94011d3 1399 ((DIV) == RCC_MCODIV_5))
sahilmgandhi 18:6a4db94011d3 1400 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
sahilmgandhi 18:6a4db94011d3 1401
sahilmgandhi 18:6a4db94011d3 1402 /**
sahilmgandhi 18:6a4db94011d3 1403 * @}
sahilmgandhi 18:6a4db94011d3 1404 */
sahilmgandhi 18:6a4db94011d3 1405
sahilmgandhi 18:6a4db94011d3 1406 /**
sahilmgandhi 18:6a4db94011d3 1407 * @}
sahilmgandhi 18:6a4db94011d3 1408 */
sahilmgandhi 18:6a4db94011d3 1409
sahilmgandhi 18:6a4db94011d3 1410 /**
sahilmgandhi 18:6a4db94011d3 1411 * @}
sahilmgandhi 18:6a4db94011d3 1412 */
sahilmgandhi 18:6a4db94011d3 1413
sahilmgandhi 18:6a4db94011d3 1414 /**
sahilmgandhi 18:6a4db94011d3 1415 * @}
sahilmgandhi 18:6a4db94011d3 1416 */
sahilmgandhi 18:6a4db94011d3 1417
sahilmgandhi 18:6a4db94011d3 1418 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1419 }
sahilmgandhi 18:6a4db94011d3 1420 #endif
sahilmgandhi 18:6a4db94011d3 1421
sahilmgandhi 18:6a4db94011d3 1422 #endif /* __STM32F4xx_HAL_RCC_H */
sahilmgandhi 18:6a4db94011d3 1423
sahilmgandhi 18:6a4db94011d3 1424 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/