MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

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sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f437xx.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V2.6.0
sahilmgandhi 18:6a4db94011d3 6 * @date 04-November-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file contains:
sahilmgandhi 18:6a4db94011d3 10 * - Data structures and the address mapping for all peripherals
sahilmgandhi 18:6a4db94011d3 11 * - peripherals registers declarations and bits definition
sahilmgandhi 18:6a4db94011d3 12 * - Macros to access peripheral’s registers hardware
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 15 * @attention
sahilmgandhi 18:6a4db94011d3 16 *
sahilmgandhi 18:6a4db94011d3 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 20 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 21 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 22 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 24 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 25 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 27 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 28 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 29 *
sahilmgandhi 18:6a4db94011d3 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 40 *
sahilmgandhi 18:6a4db94011d3 41 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 42 */
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 /** @addtogroup CMSIS_Device
sahilmgandhi 18:6a4db94011d3 45 * @{
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 /** @addtogroup stm32f437xx
sahilmgandhi 18:6a4db94011d3 49 * @{
sahilmgandhi 18:6a4db94011d3 50 */
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 #ifndef __STM32F437xx_H
sahilmgandhi 18:6a4db94011d3 53 #define __STM32F437xx_H
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 56 extern "C" {
sahilmgandhi 18:6a4db94011d3 57 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /** @addtogroup Configuration_section_for_CMSIS
sahilmgandhi 18:6a4db94011d3 60 * @{
sahilmgandhi 18:6a4db94011d3 61 */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /**
sahilmgandhi 18:6a4db94011d3 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
sahilmgandhi 18:6a4db94011d3 65 */
sahilmgandhi 18:6a4db94011d3 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
sahilmgandhi 18:6a4db94011d3 67 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
sahilmgandhi 18:6a4db94011d3 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
sahilmgandhi 18:6a4db94011d3 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 70 #ifndef __FPU_PRESENT
sahilmgandhi 18:6a4db94011d3 71 #define __FPU_PRESENT 1U /*!< FPU present */
sahilmgandhi 18:6a4db94011d3 72 #endif /* __FPU_PRESENT */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /**
sahilmgandhi 18:6a4db94011d3 75 * @}
sahilmgandhi 18:6a4db94011d3 76 */
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 /** @addtogroup Peripheral_interrupt_number_definition
sahilmgandhi 18:6a4db94011d3 79 * @{
sahilmgandhi 18:6a4db94011d3 80 */
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 /**
sahilmgandhi 18:6a4db94011d3 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
sahilmgandhi 18:6a4db94011d3 84 * in @ref Library_configuration_section
sahilmgandhi 18:6a4db94011d3 85 */
sahilmgandhi 18:6a4db94011d3 86 typedef enum
sahilmgandhi 18:6a4db94011d3 87 {
sahilmgandhi 18:6a4db94011d3 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
sahilmgandhi 18:6a4db94011d3 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
sahilmgandhi 18:6a4db94011d3 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
sahilmgandhi 18:6a4db94011d3 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
sahilmgandhi 18:6a4db94011d3 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
sahilmgandhi 18:6a4db94011d3 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
sahilmgandhi 18:6a4db94011d3 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
sahilmgandhi 18:6a4db94011d3 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
sahilmgandhi 18:6a4db94011d3 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
sahilmgandhi 18:6a4db94011d3 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
sahilmgandhi 18:6a4db94011d3 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
sahilmgandhi 18:6a4db94011d3 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
sahilmgandhi 18:6a4db94011d3 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
sahilmgandhi 18:6a4db94011d3 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
sahilmgandhi 18:6a4db94011d3 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
sahilmgandhi 18:6a4db94011d3 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
sahilmgandhi 18:6a4db94011d3 117 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
sahilmgandhi 18:6a4db94011d3 118 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
sahilmgandhi 18:6a4db94011d3 119 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
sahilmgandhi 18:6a4db94011d3 120 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
sahilmgandhi 18:6a4db94011d3 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
sahilmgandhi 18:6a4db94011d3 122 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
sahilmgandhi 18:6a4db94011d3 123 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
sahilmgandhi 18:6a4db94011d3 124 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
sahilmgandhi 18:6a4db94011d3 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
sahilmgandhi 18:6a4db94011d3 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
sahilmgandhi 18:6a4db94011d3 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
sahilmgandhi 18:6a4db94011d3 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
sahilmgandhi 18:6a4db94011d3 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
sahilmgandhi 18:6a4db94011d3 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 135 USART1_IRQn = 37, /*!< USART1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 136 USART2_IRQn = 38, /*!< USART2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 137 USART3_IRQn = 39, /*!< USART3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
sahilmgandhi 18:6a4db94011d3 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
sahilmgandhi 18:6a4db94011d3 140 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
sahilmgandhi 18:6a4db94011d3 141 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
sahilmgandhi 18:6a4db94011d3 142 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
sahilmgandhi 18:6a4db94011d3 143 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
sahilmgandhi 18:6a4db94011d3 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
sahilmgandhi 18:6a4db94011d3 145 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
sahilmgandhi 18:6a4db94011d3 146 FMC_IRQn = 48, /*!< FMC global Interrupt */
sahilmgandhi 18:6a4db94011d3 147 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
sahilmgandhi 18:6a4db94011d3 148 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 149 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 150 UART4_IRQn = 52, /*!< UART4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 151 UART5_IRQn = 53, /*!< UART5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 152 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
sahilmgandhi 18:6a4db94011d3 153 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
sahilmgandhi 18:6a4db94011d3 154 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
sahilmgandhi 18:6a4db94011d3 155 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 156 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
sahilmgandhi 18:6a4db94011d3 157 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
sahilmgandhi 18:6a4db94011d3 158 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 159 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
sahilmgandhi 18:6a4db94011d3 160 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
sahilmgandhi 18:6a4db94011d3 161 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
sahilmgandhi 18:6a4db94011d3 162 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
sahilmgandhi 18:6a4db94011d3 163 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
sahilmgandhi 18:6a4db94011d3 164 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
sahilmgandhi 18:6a4db94011d3 165 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
sahilmgandhi 18:6a4db94011d3 166 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
sahilmgandhi 18:6a4db94011d3 167 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
sahilmgandhi 18:6a4db94011d3 168 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
sahilmgandhi 18:6a4db94011d3 169 USART6_IRQn = 71, /*!< USART6 global interrupt */
sahilmgandhi 18:6a4db94011d3 170 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
sahilmgandhi 18:6a4db94011d3 171 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
sahilmgandhi 18:6a4db94011d3 172 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
sahilmgandhi 18:6a4db94011d3 173 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
sahilmgandhi 18:6a4db94011d3 174 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
sahilmgandhi 18:6a4db94011d3 175 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
sahilmgandhi 18:6a4db94011d3 176 DCMI_IRQn = 78, /*!< DCMI global interrupt */
sahilmgandhi 18:6a4db94011d3 177 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
sahilmgandhi 18:6a4db94011d3 178 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
sahilmgandhi 18:6a4db94011d3 179 FPU_IRQn = 81, /*!< FPU global interrupt */
sahilmgandhi 18:6a4db94011d3 180 UART7_IRQn = 82, /*!< UART7 global interrupt */
sahilmgandhi 18:6a4db94011d3 181 UART8_IRQn = 83, /*!< UART8 global interrupt */
sahilmgandhi 18:6a4db94011d3 182 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
sahilmgandhi 18:6a4db94011d3 183 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
sahilmgandhi 18:6a4db94011d3 184 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
sahilmgandhi 18:6a4db94011d3 185 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
sahilmgandhi 18:6a4db94011d3 186 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
sahilmgandhi 18:6a4db94011d3 187 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 /**
sahilmgandhi 18:6a4db94011d3 190 * @}
sahilmgandhi 18:6a4db94011d3 191 */
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 194 #include "system_stm32f4xx.h"
sahilmgandhi 18:6a4db94011d3 195 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 /** @addtogroup Peripheral_registers_structures
sahilmgandhi 18:6a4db94011d3 198 * @{
sahilmgandhi 18:6a4db94011d3 199 */
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 /**
sahilmgandhi 18:6a4db94011d3 202 * @brief Analog to Digital Converter
sahilmgandhi 18:6a4db94011d3 203 */
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 typedef struct
sahilmgandhi 18:6a4db94011d3 206 {
sahilmgandhi 18:6a4db94011d3 207 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 208 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 209 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 210 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 211 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 212 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 213 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 214 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 215 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 216 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 217 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 218 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 219 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 220 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 221 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
sahilmgandhi 18:6a4db94011d3 222 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 223 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 224 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 225 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 226 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 227 } ADC_TypeDef;
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 typedef struct
sahilmgandhi 18:6a4db94011d3 230 {
sahilmgandhi 18:6a4db94011d3 231 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
sahilmgandhi 18:6a4db94011d3 232 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
sahilmgandhi 18:6a4db94011d3 233 __IO uint32_t CDR; /*!< ADC common regular data register for dual
sahilmgandhi 18:6a4db94011d3 234 AND triple modes, Address offset: ADC1 base address + 0x308 */
sahilmgandhi 18:6a4db94011d3 235 } ADC_Common_TypeDef;
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /**
sahilmgandhi 18:6a4db94011d3 239 * @brief Controller Area Network TxMailBox
sahilmgandhi 18:6a4db94011d3 240 */
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 typedef struct
sahilmgandhi 18:6a4db94011d3 243 {
sahilmgandhi 18:6a4db94011d3 244 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
sahilmgandhi 18:6a4db94011d3 245 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
sahilmgandhi 18:6a4db94011d3 246 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
sahilmgandhi 18:6a4db94011d3 247 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
sahilmgandhi 18:6a4db94011d3 248 } CAN_TxMailBox_TypeDef;
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 /**
sahilmgandhi 18:6a4db94011d3 251 * @brief Controller Area Network FIFOMailBox
sahilmgandhi 18:6a4db94011d3 252 */
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 typedef struct
sahilmgandhi 18:6a4db94011d3 255 {
sahilmgandhi 18:6a4db94011d3 256 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
sahilmgandhi 18:6a4db94011d3 257 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
sahilmgandhi 18:6a4db94011d3 258 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
sahilmgandhi 18:6a4db94011d3 259 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
sahilmgandhi 18:6a4db94011d3 260 } CAN_FIFOMailBox_TypeDef;
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /**
sahilmgandhi 18:6a4db94011d3 263 * @brief Controller Area Network FilterRegister
sahilmgandhi 18:6a4db94011d3 264 */
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 typedef struct
sahilmgandhi 18:6a4db94011d3 267 {
sahilmgandhi 18:6a4db94011d3 268 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
sahilmgandhi 18:6a4db94011d3 269 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
sahilmgandhi 18:6a4db94011d3 270 } CAN_FilterRegister_TypeDef;
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /**
sahilmgandhi 18:6a4db94011d3 273 * @brief Controller Area Network
sahilmgandhi 18:6a4db94011d3 274 */
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 typedef struct
sahilmgandhi 18:6a4db94011d3 277 {
sahilmgandhi 18:6a4db94011d3 278 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 279 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 280 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 281 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 282 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 283 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 284 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 285 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 286 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
sahilmgandhi 18:6a4db94011d3 287 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
sahilmgandhi 18:6a4db94011d3 288 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
sahilmgandhi 18:6a4db94011d3 289 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
sahilmgandhi 18:6a4db94011d3 290 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
sahilmgandhi 18:6a4db94011d3 291 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
sahilmgandhi 18:6a4db94011d3 292 uint32_t RESERVED2; /*!< Reserved, 0x208 */
sahilmgandhi 18:6a4db94011d3 293 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
sahilmgandhi 18:6a4db94011d3 294 uint32_t RESERVED3; /*!< Reserved, 0x210 */
sahilmgandhi 18:6a4db94011d3 295 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
sahilmgandhi 18:6a4db94011d3 296 uint32_t RESERVED4; /*!< Reserved, 0x218 */
sahilmgandhi 18:6a4db94011d3 297 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
sahilmgandhi 18:6a4db94011d3 298 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
sahilmgandhi 18:6a4db94011d3 299 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
sahilmgandhi 18:6a4db94011d3 300 } CAN_TypeDef;
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /**
sahilmgandhi 18:6a4db94011d3 303 * @brief CRC calculation unit
sahilmgandhi 18:6a4db94011d3 304 */
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 typedef struct
sahilmgandhi 18:6a4db94011d3 307 {
sahilmgandhi 18:6a4db94011d3 308 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 309 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 310 uint8_t RESERVED0; /*!< Reserved, 0x05 */
sahilmgandhi 18:6a4db94011d3 311 uint16_t RESERVED1; /*!< Reserved, 0x06 */
sahilmgandhi 18:6a4db94011d3 312 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 313 } CRC_TypeDef;
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 /**
sahilmgandhi 18:6a4db94011d3 316 * @brief Digital to Analog Converter
sahilmgandhi 18:6a4db94011d3 317 */
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 typedef struct
sahilmgandhi 18:6a4db94011d3 320 {
sahilmgandhi 18:6a4db94011d3 321 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 322 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 323 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 324 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 325 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 326 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 327 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 328 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 329 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 330 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 331 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 332 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 333 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 334 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 335 } DAC_TypeDef;
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 /**
sahilmgandhi 18:6a4db94011d3 338 * @brief Debug MCU
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 typedef struct
sahilmgandhi 18:6a4db94011d3 342 {
sahilmgandhi 18:6a4db94011d3 343 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 345 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 346 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 347 }DBGMCU_TypeDef;
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /**
sahilmgandhi 18:6a4db94011d3 350 * @brief DCMI
sahilmgandhi 18:6a4db94011d3 351 */
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 typedef struct
sahilmgandhi 18:6a4db94011d3 354 {
sahilmgandhi 18:6a4db94011d3 355 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 356 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 362 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 366 } DCMI_TypeDef;
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 /**
sahilmgandhi 18:6a4db94011d3 369 * @brief DMA Controller
sahilmgandhi 18:6a4db94011d3 370 */
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 typedef struct
sahilmgandhi 18:6a4db94011d3 373 {
sahilmgandhi 18:6a4db94011d3 374 __IO uint32_t CR; /*!< DMA stream x configuration register */
sahilmgandhi 18:6a4db94011d3 375 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
sahilmgandhi 18:6a4db94011d3 376 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
sahilmgandhi 18:6a4db94011d3 377 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
sahilmgandhi 18:6a4db94011d3 378 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
sahilmgandhi 18:6a4db94011d3 379 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
sahilmgandhi 18:6a4db94011d3 380 } DMA_Stream_TypeDef;
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 typedef struct
sahilmgandhi 18:6a4db94011d3 383 {
sahilmgandhi 18:6a4db94011d3 384 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 385 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 386 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 387 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 388 } DMA_TypeDef;
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 /**
sahilmgandhi 18:6a4db94011d3 391 * @brief DMA2D Controller
sahilmgandhi 18:6a4db94011d3 392 */
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 typedef struct
sahilmgandhi 18:6a4db94011d3 395 {
sahilmgandhi 18:6a4db94011d3 396 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 397 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 398 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 399 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 400 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 401 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 402 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 403 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 404 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 405 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 406 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 407 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 408 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 409 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 410 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 411 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 412 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 413 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 414 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 415 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 416 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
sahilmgandhi 18:6a4db94011d3 417 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
sahilmgandhi 18:6a4db94011d3 418 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
sahilmgandhi 18:6a4db94011d3 419 } DMA2D_TypeDef;
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 /**
sahilmgandhi 18:6a4db94011d3 422 * @brief Ethernet MAC
sahilmgandhi 18:6a4db94011d3 423 */
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 typedef struct
sahilmgandhi 18:6a4db94011d3 426 {
sahilmgandhi 18:6a4db94011d3 427 __IO uint32_t MACCR;
sahilmgandhi 18:6a4db94011d3 428 __IO uint32_t MACFFR;
sahilmgandhi 18:6a4db94011d3 429 __IO uint32_t MACHTHR;
sahilmgandhi 18:6a4db94011d3 430 __IO uint32_t MACHTLR;
sahilmgandhi 18:6a4db94011d3 431 __IO uint32_t MACMIIAR;
sahilmgandhi 18:6a4db94011d3 432 __IO uint32_t MACMIIDR;
sahilmgandhi 18:6a4db94011d3 433 __IO uint32_t MACFCR;
sahilmgandhi 18:6a4db94011d3 434 __IO uint32_t MACVLANTR; /* 8 */
sahilmgandhi 18:6a4db94011d3 435 uint32_t RESERVED0[2];
sahilmgandhi 18:6a4db94011d3 436 __IO uint32_t MACRWUFFR; /* 11 */
sahilmgandhi 18:6a4db94011d3 437 __IO uint32_t MACPMTCSR;
sahilmgandhi 18:6a4db94011d3 438 uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 439 __IO uint32_t MACDBGR;
sahilmgandhi 18:6a4db94011d3 440 __IO uint32_t MACSR; /* 15 */
sahilmgandhi 18:6a4db94011d3 441 __IO uint32_t MACIMR;
sahilmgandhi 18:6a4db94011d3 442 __IO uint32_t MACA0HR;
sahilmgandhi 18:6a4db94011d3 443 __IO uint32_t MACA0LR;
sahilmgandhi 18:6a4db94011d3 444 __IO uint32_t MACA1HR;
sahilmgandhi 18:6a4db94011d3 445 __IO uint32_t MACA1LR;
sahilmgandhi 18:6a4db94011d3 446 __IO uint32_t MACA2HR;
sahilmgandhi 18:6a4db94011d3 447 __IO uint32_t MACA2LR;
sahilmgandhi 18:6a4db94011d3 448 __IO uint32_t MACA3HR;
sahilmgandhi 18:6a4db94011d3 449 __IO uint32_t MACA3LR; /* 24 */
sahilmgandhi 18:6a4db94011d3 450 uint32_t RESERVED2[40];
sahilmgandhi 18:6a4db94011d3 451 __IO uint32_t MMCCR; /* 65 */
sahilmgandhi 18:6a4db94011d3 452 __IO uint32_t MMCRIR;
sahilmgandhi 18:6a4db94011d3 453 __IO uint32_t MMCTIR;
sahilmgandhi 18:6a4db94011d3 454 __IO uint32_t MMCRIMR;
sahilmgandhi 18:6a4db94011d3 455 __IO uint32_t MMCTIMR; /* 69 */
sahilmgandhi 18:6a4db94011d3 456 uint32_t RESERVED3[14];
sahilmgandhi 18:6a4db94011d3 457 __IO uint32_t MMCTGFSCCR; /* 84 */
sahilmgandhi 18:6a4db94011d3 458 __IO uint32_t MMCTGFMSCCR;
sahilmgandhi 18:6a4db94011d3 459 uint32_t RESERVED4[5];
sahilmgandhi 18:6a4db94011d3 460 __IO uint32_t MMCTGFCR;
sahilmgandhi 18:6a4db94011d3 461 uint32_t RESERVED5[10];
sahilmgandhi 18:6a4db94011d3 462 __IO uint32_t MMCRFCECR;
sahilmgandhi 18:6a4db94011d3 463 __IO uint32_t MMCRFAECR;
sahilmgandhi 18:6a4db94011d3 464 uint32_t RESERVED6[10];
sahilmgandhi 18:6a4db94011d3 465 __IO uint32_t MMCRGUFCR;
sahilmgandhi 18:6a4db94011d3 466 uint32_t RESERVED7[334];
sahilmgandhi 18:6a4db94011d3 467 __IO uint32_t PTPTSCR;
sahilmgandhi 18:6a4db94011d3 468 __IO uint32_t PTPSSIR;
sahilmgandhi 18:6a4db94011d3 469 __IO uint32_t PTPTSHR;
sahilmgandhi 18:6a4db94011d3 470 __IO uint32_t PTPTSLR;
sahilmgandhi 18:6a4db94011d3 471 __IO uint32_t PTPTSHUR;
sahilmgandhi 18:6a4db94011d3 472 __IO uint32_t PTPTSLUR;
sahilmgandhi 18:6a4db94011d3 473 __IO uint32_t PTPTSAR;
sahilmgandhi 18:6a4db94011d3 474 __IO uint32_t PTPTTHR;
sahilmgandhi 18:6a4db94011d3 475 __IO uint32_t PTPTTLR;
sahilmgandhi 18:6a4db94011d3 476 __IO uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 477 __IO uint32_t PTPTSSR;
sahilmgandhi 18:6a4db94011d3 478 uint32_t RESERVED9[565];
sahilmgandhi 18:6a4db94011d3 479 __IO uint32_t DMABMR;
sahilmgandhi 18:6a4db94011d3 480 __IO uint32_t DMATPDR;
sahilmgandhi 18:6a4db94011d3 481 __IO uint32_t DMARPDR;
sahilmgandhi 18:6a4db94011d3 482 __IO uint32_t DMARDLAR;
sahilmgandhi 18:6a4db94011d3 483 __IO uint32_t DMATDLAR;
sahilmgandhi 18:6a4db94011d3 484 __IO uint32_t DMASR;
sahilmgandhi 18:6a4db94011d3 485 __IO uint32_t DMAOMR;
sahilmgandhi 18:6a4db94011d3 486 __IO uint32_t DMAIER;
sahilmgandhi 18:6a4db94011d3 487 __IO uint32_t DMAMFBOCR;
sahilmgandhi 18:6a4db94011d3 488 __IO uint32_t DMARSWTR;
sahilmgandhi 18:6a4db94011d3 489 uint32_t RESERVED10[8];
sahilmgandhi 18:6a4db94011d3 490 __IO uint32_t DMACHTDR;
sahilmgandhi 18:6a4db94011d3 491 __IO uint32_t DMACHRDR;
sahilmgandhi 18:6a4db94011d3 492 __IO uint32_t DMACHTBAR;
sahilmgandhi 18:6a4db94011d3 493 __IO uint32_t DMACHRBAR;
sahilmgandhi 18:6a4db94011d3 494 } ETH_TypeDef;
sahilmgandhi 18:6a4db94011d3 495
sahilmgandhi 18:6a4db94011d3 496 /**
sahilmgandhi 18:6a4db94011d3 497 * @brief External Interrupt/Event Controller
sahilmgandhi 18:6a4db94011d3 498 */
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 typedef struct
sahilmgandhi 18:6a4db94011d3 501 {
sahilmgandhi 18:6a4db94011d3 502 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 503 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 504 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 505 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 506 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 507 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 508 } EXTI_TypeDef;
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 /**
sahilmgandhi 18:6a4db94011d3 511 * @brief FLASH Registers
sahilmgandhi 18:6a4db94011d3 512 */
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 typedef struct
sahilmgandhi 18:6a4db94011d3 515 {
sahilmgandhi 18:6a4db94011d3 516 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 517 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 518 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 520 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 521 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 522 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 523 } FLASH_TypeDef;
sahilmgandhi 18:6a4db94011d3 524
sahilmgandhi 18:6a4db94011d3 525 /**
sahilmgandhi 18:6a4db94011d3 526 * @brief Flexible Memory Controller
sahilmgandhi 18:6a4db94011d3 527 */
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 typedef struct
sahilmgandhi 18:6a4db94011d3 530 {
sahilmgandhi 18:6a4db94011d3 531 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
sahilmgandhi 18:6a4db94011d3 532 } FMC_Bank1_TypeDef;
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 /**
sahilmgandhi 18:6a4db94011d3 535 * @brief Flexible Memory Controller Bank1E
sahilmgandhi 18:6a4db94011d3 536 */
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 typedef struct
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
sahilmgandhi 18:6a4db94011d3 541 } FMC_Bank1E_TypeDef;
sahilmgandhi 18:6a4db94011d3 542 /**
sahilmgandhi 18:6a4db94011d3 543 * @brief Flexible Memory Controller Bank2
sahilmgandhi 18:6a4db94011d3 544 */
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 typedef struct
sahilmgandhi 18:6a4db94011d3 547 {
sahilmgandhi 18:6a4db94011d3 548 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 549 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 552 uint32_t RESERVED0; /*!< Reserved, 0x70 */
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 554 uint32_t RESERVED1; /*!< Reserved, 0x78 */
sahilmgandhi 18:6a4db94011d3 555 uint32_t RESERVED2; /*!< Reserved, 0x7C */
sahilmgandhi 18:6a4db94011d3 556 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 558 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 559 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 560 uint32_t RESERVED3; /*!< Reserved, 0x90 */
sahilmgandhi 18:6a4db94011d3 561 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 562 } FMC_Bank2_3_TypeDef;
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564 /**
sahilmgandhi 18:6a4db94011d3 565 * @brief Flexible Memory Controller Bank4
sahilmgandhi 18:6a4db94011d3 566 */
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 typedef struct
sahilmgandhi 18:6a4db94011d3 569 {
sahilmgandhi 18:6a4db94011d3 570 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
sahilmgandhi 18:6a4db94011d3 571 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
sahilmgandhi 18:6a4db94011d3 572 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
sahilmgandhi 18:6a4db94011d3 573 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
sahilmgandhi 18:6a4db94011d3 574 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
sahilmgandhi 18:6a4db94011d3 575 } FMC_Bank4_TypeDef;
sahilmgandhi 18:6a4db94011d3 576
sahilmgandhi 18:6a4db94011d3 577 /**
sahilmgandhi 18:6a4db94011d3 578 * @brief Flexible Memory Controller Bank5_6
sahilmgandhi 18:6a4db94011d3 579 */
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 typedef struct
sahilmgandhi 18:6a4db94011d3 582 {
sahilmgandhi 18:6a4db94011d3 583 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
sahilmgandhi 18:6a4db94011d3 585 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
sahilmgandhi 18:6a4db94011d3 587 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
sahilmgandhi 18:6a4db94011d3 588 } FMC_Bank5_6_TypeDef;
sahilmgandhi 18:6a4db94011d3 589
sahilmgandhi 18:6a4db94011d3 590 /**
sahilmgandhi 18:6a4db94011d3 591 * @brief General Purpose I/O
sahilmgandhi 18:6a4db94011d3 592 */
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 typedef struct
sahilmgandhi 18:6a4db94011d3 595 {
sahilmgandhi 18:6a4db94011d3 596 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 597 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 598 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 599 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 600 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 601 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 602 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 603 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 604 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
sahilmgandhi 18:6a4db94011d3 605 } GPIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 /**
sahilmgandhi 18:6a4db94011d3 608 * @brief System configuration controller
sahilmgandhi 18:6a4db94011d3 609 */
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 typedef struct
sahilmgandhi 18:6a4db94011d3 612 {
sahilmgandhi 18:6a4db94011d3 613 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 614 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 615 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
sahilmgandhi 18:6a4db94011d3 616 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
sahilmgandhi 18:6a4db94011d3 617 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 618 } SYSCFG_TypeDef;
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 /**
sahilmgandhi 18:6a4db94011d3 621 * @brief Inter-integrated Circuit Interface
sahilmgandhi 18:6a4db94011d3 622 */
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 typedef struct
sahilmgandhi 18:6a4db94011d3 625 {
sahilmgandhi 18:6a4db94011d3 626 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 627 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 628 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 629 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 630 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 631 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 632 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 633 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 634 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 635 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 636 } I2C_TypeDef;
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /**
sahilmgandhi 18:6a4db94011d3 639 * @brief Independent WATCHDOG
sahilmgandhi 18:6a4db94011d3 640 */
sahilmgandhi 18:6a4db94011d3 641
sahilmgandhi 18:6a4db94011d3 642 typedef struct
sahilmgandhi 18:6a4db94011d3 643 {
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 645 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 646 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 647 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 648 } IWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 649
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651 /**
sahilmgandhi 18:6a4db94011d3 652 * @brief Power Control
sahilmgandhi 18:6a4db94011d3 653 */
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 typedef struct
sahilmgandhi 18:6a4db94011d3 656 {
sahilmgandhi 18:6a4db94011d3 657 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 658 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 659 } PWR_TypeDef;
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 /**
sahilmgandhi 18:6a4db94011d3 662 * @brief Reset and Clock Control
sahilmgandhi 18:6a4db94011d3 663 */
sahilmgandhi 18:6a4db94011d3 664
sahilmgandhi 18:6a4db94011d3 665 typedef struct
sahilmgandhi 18:6a4db94011d3 666 {
sahilmgandhi 18:6a4db94011d3 667 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 668 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 669 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 670 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 671 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 672 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 673 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 674 uint32_t RESERVED0; /*!< Reserved, 0x1C */
sahilmgandhi 18:6a4db94011d3 675 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 676 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 677 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
sahilmgandhi 18:6a4db94011d3 678 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 679 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 680 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 681 uint32_t RESERVED2; /*!< Reserved, 0x3C */
sahilmgandhi 18:6a4db94011d3 682 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 683 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 684 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
sahilmgandhi 18:6a4db94011d3 685 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 686 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 687 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 688 uint32_t RESERVED4; /*!< Reserved, 0x5C */
sahilmgandhi 18:6a4db94011d3 689 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 690 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 691 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
sahilmgandhi 18:6a4db94011d3 692 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
sahilmgandhi 18:6a4db94011d3 693 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 694 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
sahilmgandhi 18:6a4db94011d3 695 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 696 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 697 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 698 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 699 } RCC_TypeDef;
sahilmgandhi 18:6a4db94011d3 700
sahilmgandhi 18:6a4db94011d3 701 /**
sahilmgandhi 18:6a4db94011d3 702 * @brief Real-Time Clock
sahilmgandhi 18:6a4db94011d3 703 */
sahilmgandhi 18:6a4db94011d3 704
sahilmgandhi 18:6a4db94011d3 705 typedef struct
sahilmgandhi 18:6a4db94011d3 706 {
sahilmgandhi 18:6a4db94011d3 707 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 708 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 709 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 710 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 711 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 712 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 713 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 714 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 715 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 716 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 717 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 718 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 719 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 720 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 721 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 722 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 723 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 724 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 725 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 726 uint32_t RESERVED7; /*!< Reserved, 0x4C */
sahilmgandhi 18:6a4db94011d3 727 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 728 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 729 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 730 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 731 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 732 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 733 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 734 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 735 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
sahilmgandhi 18:6a4db94011d3 736 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 737 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
sahilmgandhi 18:6a4db94011d3 738 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
sahilmgandhi 18:6a4db94011d3 739 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 740 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 741 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 742 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 743 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
sahilmgandhi 18:6a4db94011d3 744 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
sahilmgandhi 18:6a4db94011d3 745 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
sahilmgandhi 18:6a4db94011d3 746 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
sahilmgandhi 18:6a4db94011d3 747 } RTC_TypeDef;
sahilmgandhi 18:6a4db94011d3 748
sahilmgandhi 18:6a4db94011d3 749 /**
sahilmgandhi 18:6a4db94011d3 750 * @brief Serial Audio Interface
sahilmgandhi 18:6a4db94011d3 751 */
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 typedef struct
sahilmgandhi 18:6a4db94011d3 754 {
sahilmgandhi 18:6a4db94011d3 755 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 756 } SAI_TypeDef;
sahilmgandhi 18:6a4db94011d3 757
sahilmgandhi 18:6a4db94011d3 758 typedef struct
sahilmgandhi 18:6a4db94011d3 759 {
sahilmgandhi 18:6a4db94011d3 760 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 761 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 762 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 763 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 764 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 765 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 766 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 767 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 768 } SAI_Block_TypeDef;
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 /**
sahilmgandhi 18:6a4db94011d3 771 * @brief SD host Interface
sahilmgandhi 18:6a4db94011d3 772 */
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 typedef struct
sahilmgandhi 18:6a4db94011d3 775 {
sahilmgandhi 18:6a4db94011d3 776 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 777 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 778 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 779 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 780 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 781 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 782 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 783 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 784 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 785 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 786 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 787 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 788 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 789 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 790 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 791 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 792 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
sahilmgandhi 18:6a4db94011d3 793 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 794 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
sahilmgandhi 18:6a4db94011d3 795 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 796 } SDIO_TypeDef;
sahilmgandhi 18:6a4db94011d3 797
sahilmgandhi 18:6a4db94011d3 798 /**
sahilmgandhi 18:6a4db94011d3 799 * @brief Serial Peripheral Interface
sahilmgandhi 18:6a4db94011d3 800 */
sahilmgandhi 18:6a4db94011d3 801
sahilmgandhi 18:6a4db94011d3 802 typedef struct
sahilmgandhi 18:6a4db94011d3 803 {
sahilmgandhi 18:6a4db94011d3 804 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 805 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 806 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 807 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 808 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 809 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 810 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 811 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 812 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 813 } SPI_TypeDef;
sahilmgandhi 18:6a4db94011d3 814
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 /**
sahilmgandhi 18:6a4db94011d3 817 * @brief TIM
sahilmgandhi 18:6a4db94011d3 818 */
sahilmgandhi 18:6a4db94011d3 819
sahilmgandhi 18:6a4db94011d3 820 typedef struct
sahilmgandhi 18:6a4db94011d3 821 {
sahilmgandhi 18:6a4db94011d3 822 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 823 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 824 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 825 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 826 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 827 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 828 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 829 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 830 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 831 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 832 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 833 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 834 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 835 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 836 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 837 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 838 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 839 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 840 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 841 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 842 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 843 } TIM_TypeDef;
sahilmgandhi 18:6a4db94011d3 844
sahilmgandhi 18:6a4db94011d3 845 /**
sahilmgandhi 18:6a4db94011d3 846 * @brief Universal Synchronous Asynchronous Receiver Transmitter
sahilmgandhi 18:6a4db94011d3 847 */
sahilmgandhi 18:6a4db94011d3 848
sahilmgandhi 18:6a4db94011d3 849 typedef struct
sahilmgandhi 18:6a4db94011d3 850 {
sahilmgandhi 18:6a4db94011d3 851 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 852 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 853 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 854 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 855 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 856 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 857 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 858 } USART_TypeDef;
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860 /**
sahilmgandhi 18:6a4db94011d3 861 * @brief Window WATCHDOG
sahilmgandhi 18:6a4db94011d3 862 */
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 typedef struct
sahilmgandhi 18:6a4db94011d3 865 {
sahilmgandhi 18:6a4db94011d3 866 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 867 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 868 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 869 } WWDG_TypeDef;
sahilmgandhi 18:6a4db94011d3 870
sahilmgandhi 18:6a4db94011d3 871 /**
sahilmgandhi 18:6a4db94011d3 872 * @brief Crypto Processor
sahilmgandhi 18:6a4db94011d3 873 */
sahilmgandhi 18:6a4db94011d3 874
sahilmgandhi 18:6a4db94011d3 875 typedef struct
sahilmgandhi 18:6a4db94011d3 876 {
sahilmgandhi 18:6a4db94011d3 877 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 878 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 879 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 880 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
sahilmgandhi 18:6a4db94011d3 881 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
sahilmgandhi 18:6a4db94011d3 882 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
sahilmgandhi 18:6a4db94011d3 883 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
sahilmgandhi 18:6a4db94011d3 884 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
sahilmgandhi 18:6a4db94011d3 885 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 886 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 887 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
sahilmgandhi 18:6a4db94011d3 888 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
sahilmgandhi 18:6a4db94011d3 889 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
sahilmgandhi 18:6a4db94011d3 890 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
sahilmgandhi 18:6a4db94011d3 891 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
sahilmgandhi 18:6a4db94011d3 892 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
sahilmgandhi 18:6a4db94011d3 893 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
sahilmgandhi 18:6a4db94011d3 894 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
sahilmgandhi 18:6a4db94011d3 895 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
sahilmgandhi 18:6a4db94011d3 896 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
sahilmgandhi 18:6a4db94011d3 897 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
sahilmgandhi 18:6a4db94011d3 898 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
sahilmgandhi 18:6a4db94011d3 899 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
sahilmgandhi 18:6a4db94011d3 900 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
sahilmgandhi 18:6a4db94011d3 901 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
sahilmgandhi 18:6a4db94011d3 902 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
sahilmgandhi 18:6a4db94011d3 903 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
sahilmgandhi 18:6a4db94011d3 904 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
sahilmgandhi 18:6a4db94011d3 905 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
sahilmgandhi 18:6a4db94011d3 906 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
sahilmgandhi 18:6a4db94011d3 907 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
sahilmgandhi 18:6a4db94011d3 908 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
sahilmgandhi 18:6a4db94011d3 909 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
sahilmgandhi 18:6a4db94011d3 910 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
sahilmgandhi 18:6a4db94011d3 911 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
sahilmgandhi 18:6a4db94011d3 912 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
sahilmgandhi 18:6a4db94011d3 913 } CRYP_TypeDef;
sahilmgandhi 18:6a4db94011d3 914
sahilmgandhi 18:6a4db94011d3 915 /**
sahilmgandhi 18:6a4db94011d3 916 * @brief HASH
sahilmgandhi 18:6a4db94011d3 917 */
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 typedef struct
sahilmgandhi 18:6a4db94011d3 920 {
sahilmgandhi 18:6a4db94011d3 921 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 922 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 923 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 924 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
sahilmgandhi 18:6a4db94011d3 925 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
sahilmgandhi 18:6a4db94011d3 926 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
sahilmgandhi 18:6a4db94011d3 927 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
sahilmgandhi 18:6a4db94011d3 928 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
sahilmgandhi 18:6a4db94011d3 929 } HASH_TypeDef;
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931 /**
sahilmgandhi 18:6a4db94011d3 932 * @brief HASH_DIGEST
sahilmgandhi 18:6a4db94011d3 933 */
sahilmgandhi 18:6a4db94011d3 934
sahilmgandhi 18:6a4db94011d3 935 typedef struct
sahilmgandhi 18:6a4db94011d3 936 {
sahilmgandhi 18:6a4db94011d3 937 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
sahilmgandhi 18:6a4db94011d3 938 } HASH_DIGEST_TypeDef;
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 /**
sahilmgandhi 18:6a4db94011d3 941 * @brief RNG
sahilmgandhi 18:6a4db94011d3 942 */
sahilmgandhi 18:6a4db94011d3 943
sahilmgandhi 18:6a4db94011d3 944 typedef struct
sahilmgandhi 18:6a4db94011d3 945 {
sahilmgandhi 18:6a4db94011d3 946 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
sahilmgandhi 18:6a4db94011d3 947 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
sahilmgandhi 18:6a4db94011d3 948 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
sahilmgandhi 18:6a4db94011d3 949 } RNG_TypeDef;
sahilmgandhi 18:6a4db94011d3 950
sahilmgandhi 18:6a4db94011d3 951 /**
sahilmgandhi 18:6a4db94011d3 952 * @brief USB_OTG_Core_Registers
sahilmgandhi 18:6a4db94011d3 953 */
sahilmgandhi 18:6a4db94011d3 954 typedef struct
sahilmgandhi 18:6a4db94011d3 955 {
sahilmgandhi 18:6a4db94011d3 956 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
sahilmgandhi 18:6a4db94011d3 957 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
sahilmgandhi 18:6a4db94011d3 958 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
sahilmgandhi 18:6a4db94011d3 959 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
sahilmgandhi 18:6a4db94011d3 960 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
sahilmgandhi 18:6a4db94011d3 961 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
sahilmgandhi 18:6a4db94011d3 962 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
sahilmgandhi 18:6a4db94011d3 963 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
sahilmgandhi 18:6a4db94011d3 964 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
sahilmgandhi 18:6a4db94011d3 965 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
sahilmgandhi 18:6a4db94011d3 966 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
sahilmgandhi 18:6a4db94011d3 967 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
sahilmgandhi 18:6a4db94011d3 968 uint32_t Reserved30[2]; /*!< Reserved 030h */
sahilmgandhi 18:6a4db94011d3 969 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
sahilmgandhi 18:6a4db94011d3 970 __IO uint32_t CID; /*!< User ID Register 03Ch */
sahilmgandhi 18:6a4db94011d3 971 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
sahilmgandhi 18:6a4db94011d3 972 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
sahilmgandhi 18:6a4db94011d3 973 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
sahilmgandhi 18:6a4db94011d3 974 } USB_OTG_GlobalTypeDef;
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 /**
sahilmgandhi 18:6a4db94011d3 977 * @brief USB_OTG_device_Registers
sahilmgandhi 18:6a4db94011d3 978 */
sahilmgandhi 18:6a4db94011d3 979 typedef struct
sahilmgandhi 18:6a4db94011d3 980 {
sahilmgandhi 18:6a4db94011d3 981 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
sahilmgandhi 18:6a4db94011d3 982 __IO uint32_t DCTL; /*!< dev Control Register 804h */
sahilmgandhi 18:6a4db94011d3 983 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
sahilmgandhi 18:6a4db94011d3 984 uint32_t Reserved0C; /*!< Reserved 80Ch */
sahilmgandhi 18:6a4db94011d3 985 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
sahilmgandhi 18:6a4db94011d3 986 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
sahilmgandhi 18:6a4db94011d3 987 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
sahilmgandhi 18:6a4db94011d3 988 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
sahilmgandhi 18:6a4db94011d3 989 uint32_t Reserved20; /*!< Reserved 820h */
sahilmgandhi 18:6a4db94011d3 990 uint32_t Reserved9; /*!< Reserved 824h */
sahilmgandhi 18:6a4db94011d3 991 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
sahilmgandhi 18:6a4db94011d3 992 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
sahilmgandhi 18:6a4db94011d3 993 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
sahilmgandhi 18:6a4db94011d3 994 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
sahilmgandhi 18:6a4db94011d3 995 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
sahilmgandhi 18:6a4db94011d3 996 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
sahilmgandhi 18:6a4db94011d3 997 uint32_t Reserved40; /*!< dedicated EP mask 840h */
sahilmgandhi 18:6a4db94011d3 998 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
sahilmgandhi 18:6a4db94011d3 999 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
sahilmgandhi 18:6a4db94011d3 1000 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
sahilmgandhi 18:6a4db94011d3 1001 } USB_OTG_DeviceTypeDef;
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 /**
sahilmgandhi 18:6a4db94011d3 1004 * @brief USB_OTG_IN_Endpoint-Specific_Register
sahilmgandhi 18:6a4db94011d3 1005 */
sahilmgandhi 18:6a4db94011d3 1006 typedef struct
sahilmgandhi 18:6a4db94011d3 1007 {
sahilmgandhi 18:6a4db94011d3 1008 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
sahilmgandhi 18:6a4db94011d3 1009 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
sahilmgandhi 18:6a4db94011d3 1010 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
sahilmgandhi 18:6a4db94011d3 1011 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
sahilmgandhi 18:6a4db94011d3 1012 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
sahilmgandhi 18:6a4db94011d3 1013 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
sahilmgandhi 18:6a4db94011d3 1014 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
sahilmgandhi 18:6a4db94011d3 1015 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
sahilmgandhi 18:6a4db94011d3 1016 } USB_OTG_INEndpointTypeDef;
sahilmgandhi 18:6a4db94011d3 1017
sahilmgandhi 18:6a4db94011d3 1018 /**
sahilmgandhi 18:6a4db94011d3 1019 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
sahilmgandhi 18:6a4db94011d3 1020 */
sahilmgandhi 18:6a4db94011d3 1021 typedef struct
sahilmgandhi 18:6a4db94011d3 1022 {
sahilmgandhi 18:6a4db94011d3 1023 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
sahilmgandhi 18:6a4db94011d3 1024 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
sahilmgandhi 18:6a4db94011d3 1025 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
sahilmgandhi 18:6a4db94011d3 1026 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
sahilmgandhi 18:6a4db94011d3 1027 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
sahilmgandhi 18:6a4db94011d3 1028 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
sahilmgandhi 18:6a4db94011d3 1029 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
sahilmgandhi 18:6a4db94011d3 1030 } USB_OTG_OUTEndpointTypeDef;
sahilmgandhi 18:6a4db94011d3 1031
sahilmgandhi 18:6a4db94011d3 1032 /**
sahilmgandhi 18:6a4db94011d3 1033 * @brief USB_OTG_Host_Mode_Register_Structures
sahilmgandhi 18:6a4db94011d3 1034 */
sahilmgandhi 18:6a4db94011d3 1035 typedef struct
sahilmgandhi 18:6a4db94011d3 1036 {
sahilmgandhi 18:6a4db94011d3 1037 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
sahilmgandhi 18:6a4db94011d3 1038 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
sahilmgandhi 18:6a4db94011d3 1039 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
sahilmgandhi 18:6a4db94011d3 1040 uint32_t Reserved40C; /*!< Reserved 40Ch */
sahilmgandhi 18:6a4db94011d3 1041 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
sahilmgandhi 18:6a4db94011d3 1042 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
sahilmgandhi 18:6a4db94011d3 1043 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
sahilmgandhi 18:6a4db94011d3 1044 } USB_OTG_HostTypeDef;
sahilmgandhi 18:6a4db94011d3 1045
sahilmgandhi 18:6a4db94011d3 1046 /**
sahilmgandhi 18:6a4db94011d3 1047 * @brief USB_OTG_Host_Channel_Specific_Registers
sahilmgandhi 18:6a4db94011d3 1048 */
sahilmgandhi 18:6a4db94011d3 1049 typedef struct
sahilmgandhi 18:6a4db94011d3 1050 {
sahilmgandhi 18:6a4db94011d3 1051 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
sahilmgandhi 18:6a4db94011d3 1052 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
sahilmgandhi 18:6a4db94011d3 1053 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
sahilmgandhi 18:6a4db94011d3 1054 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
sahilmgandhi 18:6a4db94011d3 1055 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
sahilmgandhi 18:6a4db94011d3 1056 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
sahilmgandhi 18:6a4db94011d3 1057 uint32_t Reserved[2]; /*!< Reserved */
sahilmgandhi 18:6a4db94011d3 1058 } USB_OTG_HostChannelTypeDef;
sahilmgandhi 18:6a4db94011d3 1059
sahilmgandhi 18:6a4db94011d3 1060 /**
sahilmgandhi 18:6a4db94011d3 1061 * @}
sahilmgandhi 18:6a4db94011d3 1062 */
sahilmgandhi 18:6a4db94011d3 1063
sahilmgandhi 18:6a4db94011d3 1064 /** @addtogroup Peripheral_memory_map
sahilmgandhi 18:6a4db94011d3 1065 * @{
sahilmgandhi 18:6a4db94011d3 1066 */
sahilmgandhi 18:6a4db94011d3 1067 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 1068 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 1069 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 1070 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 1071 #define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 1072 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
sahilmgandhi 18:6a4db94011d3 1073 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
sahilmgandhi 18:6a4db94011d3 1074 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
sahilmgandhi 18:6a4db94011d3 1075 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 1076 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 1077 #define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 1078 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 1079 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
sahilmgandhi 18:6a4db94011d3 1080 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
sahilmgandhi 18:6a4db94011d3 1081 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
sahilmgandhi 18:6a4db94011d3 1082
sahilmgandhi 18:6a4db94011d3 1083 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 1084 #define SRAM_BASE SRAM1_BASE
sahilmgandhi 18:6a4db94011d3 1085 #define SRAM_BB_BASE SRAM1_BB_BASE
sahilmgandhi 18:6a4db94011d3 1086
sahilmgandhi 18:6a4db94011d3 1087
sahilmgandhi 18:6a4db94011d3 1088 /*!< Peripheral memory map */
sahilmgandhi 18:6a4db94011d3 1089 #define APB1PERIPH_BASE PERIPH_BASE
sahilmgandhi 18:6a4db94011d3 1090 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
sahilmgandhi 18:6a4db94011d3 1091 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
sahilmgandhi 18:6a4db94011d3 1092 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094 /*!< APB1 peripherals */
sahilmgandhi 18:6a4db94011d3 1095 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 1096 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
sahilmgandhi 18:6a4db94011d3 1097 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
sahilmgandhi 18:6a4db94011d3 1098 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
sahilmgandhi 18:6a4db94011d3 1099 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 1100 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
sahilmgandhi 18:6a4db94011d3 1101 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
sahilmgandhi 18:6a4db94011d3 1102 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
sahilmgandhi 18:6a4db94011d3 1103 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
sahilmgandhi 18:6a4db94011d3 1104 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
sahilmgandhi 18:6a4db94011d3 1105 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
sahilmgandhi 18:6a4db94011d3 1106 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 1107 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
sahilmgandhi 18:6a4db94011d3 1108 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 1109 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 1110 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
sahilmgandhi 18:6a4db94011d3 1111 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
sahilmgandhi 18:6a4db94011d3 1112 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
sahilmgandhi 18:6a4db94011d3 1113 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
sahilmgandhi 18:6a4db94011d3 1114 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
sahilmgandhi 18:6a4db94011d3 1115 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
sahilmgandhi 18:6a4db94011d3 1116 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
sahilmgandhi 18:6a4db94011d3 1117 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
sahilmgandhi 18:6a4db94011d3 1118 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
sahilmgandhi 18:6a4db94011d3 1119 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
sahilmgandhi 18:6a4db94011d3 1120 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
sahilmgandhi 18:6a4db94011d3 1121 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
sahilmgandhi 18:6a4db94011d3 1122 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
sahilmgandhi 18:6a4db94011d3 1123 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
sahilmgandhi 18:6a4db94011d3 1124
sahilmgandhi 18:6a4db94011d3 1125 /*!< APB2 peripherals */
sahilmgandhi 18:6a4db94011d3 1126 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 1127 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
sahilmgandhi 18:6a4db94011d3 1128 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 1129 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
sahilmgandhi 18:6a4db94011d3 1130 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
sahilmgandhi 18:6a4db94011d3 1131 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
sahilmgandhi 18:6a4db94011d3 1132 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
sahilmgandhi 18:6a4db94011d3 1133 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
sahilmgandhi 18:6a4db94011d3 1134 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
sahilmgandhi 18:6a4db94011d3 1135 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 1136 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
sahilmgandhi 18:6a4db94011d3 1137 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 1138 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 1139 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
sahilmgandhi 18:6a4db94011d3 1140 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
sahilmgandhi 18:6a4db94011d3 1141 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
sahilmgandhi 18:6a4db94011d3 1142 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
sahilmgandhi 18:6a4db94011d3 1143 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
sahilmgandhi 18:6a4db94011d3 1144 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
sahilmgandhi 18:6a4db94011d3 1145 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
sahilmgandhi 18:6a4db94011d3 1146 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
sahilmgandhi 18:6a4db94011d3 1147
sahilmgandhi 18:6a4db94011d3 1148 /*!< AHB1 peripherals */
sahilmgandhi 18:6a4db94011d3 1149 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 1150 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
sahilmgandhi 18:6a4db94011d3 1151 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
sahilmgandhi 18:6a4db94011d3 1152 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
sahilmgandhi 18:6a4db94011d3 1153 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 1154 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
sahilmgandhi 18:6a4db94011d3 1155 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
sahilmgandhi 18:6a4db94011d3 1156 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
sahilmgandhi 18:6a4db94011d3 1157 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
sahilmgandhi 18:6a4db94011d3 1158 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
sahilmgandhi 18:6a4db94011d3 1159 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
sahilmgandhi 18:6a4db94011d3 1160 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
sahilmgandhi 18:6a4db94011d3 1161 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
sahilmgandhi 18:6a4db94011d3 1162 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
sahilmgandhi 18:6a4db94011d3 1163 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
sahilmgandhi 18:6a4db94011d3 1164 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
sahilmgandhi 18:6a4db94011d3 1165 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
sahilmgandhi 18:6a4db94011d3 1166 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
sahilmgandhi 18:6a4db94011d3 1167 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
sahilmgandhi 18:6a4db94011d3 1168 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
sahilmgandhi 18:6a4db94011d3 1169 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
sahilmgandhi 18:6a4db94011d3 1170 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
sahilmgandhi 18:6a4db94011d3 1171 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
sahilmgandhi 18:6a4db94011d3 1172 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
sahilmgandhi 18:6a4db94011d3 1173 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
sahilmgandhi 18:6a4db94011d3 1174 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
sahilmgandhi 18:6a4db94011d3 1175 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
sahilmgandhi 18:6a4db94011d3 1176 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
sahilmgandhi 18:6a4db94011d3 1177 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
sahilmgandhi 18:6a4db94011d3 1178 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
sahilmgandhi 18:6a4db94011d3 1179 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
sahilmgandhi 18:6a4db94011d3 1180 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
sahilmgandhi 18:6a4db94011d3 1181 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
sahilmgandhi 18:6a4db94011d3 1182 #define ETH_MAC_BASE (ETH_BASE)
sahilmgandhi 18:6a4db94011d3 1183 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
sahilmgandhi 18:6a4db94011d3 1184 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
sahilmgandhi 18:6a4db94011d3 1185 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
sahilmgandhi 18:6a4db94011d3 1186 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
sahilmgandhi 18:6a4db94011d3 1187
sahilmgandhi 18:6a4db94011d3 1188 /*!< AHB2 peripherals */
sahilmgandhi 18:6a4db94011d3 1189 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
sahilmgandhi 18:6a4db94011d3 1190 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
sahilmgandhi 18:6a4db94011d3 1191 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
sahilmgandhi 18:6a4db94011d3 1192 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
sahilmgandhi 18:6a4db94011d3 1193 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
sahilmgandhi 18:6a4db94011d3 1194
sahilmgandhi 18:6a4db94011d3 1195 /*!< FMC Bankx registers base address */
sahilmgandhi 18:6a4db94011d3 1196 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
sahilmgandhi 18:6a4db94011d3 1197 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
sahilmgandhi 18:6a4db94011d3 1198 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
sahilmgandhi 18:6a4db94011d3 1199 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
sahilmgandhi 18:6a4db94011d3 1200 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
sahilmgandhi 18:6a4db94011d3 1201
sahilmgandhi 18:6a4db94011d3 1202
sahilmgandhi 18:6a4db94011d3 1203 /*!< Debug MCU registers base address */
sahilmgandhi 18:6a4db94011d3 1204 #define DBGMCU_BASE 0xE0042000U
sahilmgandhi 18:6a4db94011d3 1205 /*!< USB registers base address */
sahilmgandhi 18:6a4db94011d3 1206 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
sahilmgandhi 18:6a4db94011d3 1207 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
sahilmgandhi 18:6a4db94011d3 1208
sahilmgandhi 18:6a4db94011d3 1209 #define USB_OTG_GLOBAL_BASE 0x000U
sahilmgandhi 18:6a4db94011d3 1210 #define USB_OTG_DEVICE_BASE 0x800U
sahilmgandhi 18:6a4db94011d3 1211 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
sahilmgandhi 18:6a4db94011d3 1212 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
sahilmgandhi 18:6a4db94011d3 1213 #define USB_OTG_EP_REG_SIZE 0x20U
sahilmgandhi 18:6a4db94011d3 1214 #define USB_OTG_HOST_BASE 0x400U
sahilmgandhi 18:6a4db94011d3 1215 #define USB_OTG_HOST_PORT_BASE 0x440U
sahilmgandhi 18:6a4db94011d3 1216 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
sahilmgandhi 18:6a4db94011d3 1217 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
sahilmgandhi 18:6a4db94011d3 1218 #define USB_OTG_PCGCCTL_BASE 0xE00U
sahilmgandhi 18:6a4db94011d3 1219 #define USB_OTG_FIFO_BASE 0x1000U
sahilmgandhi 18:6a4db94011d3 1220 #define USB_OTG_FIFO_SIZE 0x1000U
sahilmgandhi 18:6a4db94011d3 1221
sahilmgandhi 18:6a4db94011d3 1222 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
sahilmgandhi 18:6a4db94011d3 1223 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
sahilmgandhi 18:6a4db94011d3 1224 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
sahilmgandhi 18:6a4db94011d3 1225 /**
sahilmgandhi 18:6a4db94011d3 1226 * @}
sahilmgandhi 18:6a4db94011d3 1227 */
sahilmgandhi 18:6a4db94011d3 1228
sahilmgandhi 18:6a4db94011d3 1229 /** @addtogroup Peripheral_declaration
sahilmgandhi 18:6a4db94011d3 1230 * @{
sahilmgandhi 18:6a4db94011d3 1231 */
sahilmgandhi 18:6a4db94011d3 1232 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
sahilmgandhi 18:6a4db94011d3 1233 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
sahilmgandhi 18:6a4db94011d3 1234 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
sahilmgandhi 18:6a4db94011d3 1235 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
sahilmgandhi 18:6a4db94011d3 1236 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
sahilmgandhi 18:6a4db94011d3 1237 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
sahilmgandhi 18:6a4db94011d3 1238 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
sahilmgandhi 18:6a4db94011d3 1239 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
sahilmgandhi 18:6a4db94011d3 1240 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
sahilmgandhi 18:6a4db94011d3 1241 #define RTC ((RTC_TypeDef *) RTC_BASE)
sahilmgandhi 18:6a4db94011d3 1242 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
sahilmgandhi 18:6a4db94011d3 1243 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
sahilmgandhi 18:6a4db94011d3 1244 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
sahilmgandhi 18:6a4db94011d3 1245 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
sahilmgandhi 18:6a4db94011d3 1246 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
sahilmgandhi 18:6a4db94011d3 1247 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
sahilmgandhi 18:6a4db94011d3 1248 #define USART2 ((USART_TypeDef *) USART2_BASE)
sahilmgandhi 18:6a4db94011d3 1249 #define USART3 ((USART_TypeDef *) USART3_BASE)
sahilmgandhi 18:6a4db94011d3 1250 #define UART4 ((USART_TypeDef *) UART4_BASE)
sahilmgandhi 18:6a4db94011d3 1251 #define UART5 ((USART_TypeDef *) UART5_BASE)
sahilmgandhi 18:6a4db94011d3 1252 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 1253 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
sahilmgandhi 18:6a4db94011d3 1254 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
sahilmgandhi 18:6a4db94011d3 1255 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
sahilmgandhi 18:6a4db94011d3 1256 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
sahilmgandhi 18:6a4db94011d3 1257 #define PWR ((PWR_TypeDef *) PWR_BASE)
sahilmgandhi 18:6a4db94011d3 1258 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
sahilmgandhi 18:6a4db94011d3 1259 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
sahilmgandhi 18:6a4db94011d3 1260 #define UART7 ((USART_TypeDef *) UART7_BASE)
sahilmgandhi 18:6a4db94011d3 1261 #define UART8 ((USART_TypeDef *) UART8_BASE)
sahilmgandhi 18:6a4db94011d3 1262 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
sahilmgandhi 18:6a4db94011d3 1263 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
sahilmgandhi 18:6a4db94011d3 1264 #define USART1 ((USART_TypeDef *) USART1_BASE)
sahilmgandhi 18:6a4db94011d3 1265 #define USART6 ((USART_TypeDef *) USART6_BASE)
sahilmgandhi 18:6a4db94011d3 1266 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
sahilmgandhi 18:6a4db94011d3 1267 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
sahilmgandhi 18:6a4db94011d3 1268 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
sahilmgandhi 18:6a4db94011d3 1269 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
sahilmgandhi 18:6a4db94011d3 1270 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
sahilmgandhi 18:6a4db94011d3 1271 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
sahilmgandhi 18:6a4db94011d3 1272 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
sahilmgandhi 18:6a4db94011d3 1273 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
sahilmgandhi 18:6a4db94011d3 1274 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
sahilmgandhi 18:6a4db94011d3 1275 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
sahilmgandhi 18:6a4db94011d3 1276 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
sahilmgandhi 18:6a4db94011d3 1277 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
sahilmgandhi 18:6a4db94011d3 1278 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
sahilmgandhi 18:6a4db94011d3 1279 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
sahilmgandhi 18:6a4db94011d3 1280 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
sahilmgandhi 18:6a4db94011d3 1281 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
sahilmgandhi 18:6a4db94011d3 1282 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
sahilmgandhi 18:6a4db94011d3 1283 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
sahilmgandhi 18:6a4db94011d3 1284 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
sahilmgandhi 18:6a4db94011d3 1285 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
sahilmgandhi 18:6a4db94011d3 1286 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
sahilmgandhi 18:6a4db94011d3 1287 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
sahilmgandhi 18:6a4db94011d3 1288 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
sahilmgandhi 18:6a4db94011d3 1289 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
sahilmgandhi 18:6a4db94011d3 1290 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
sahilmgandhi 18:6a4db94011d3 1291 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
sahilmgandhi 18:6a4db94011d3 1292 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
sahilmgandhi 18:6a4db94011d3 1293 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
sahilmgandhi 18:6a4db94011d3 1294 #define CRC ((CRC_TypeDef *) CRC_BASE)
sahilmgandhi 18:6a4db94011d3 1295 #define RCC ((RCC_TypeDef *) RCC_BASE)
sahilmgandhi 18:6a4db94011d3 1296 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
sahilmgandhi 18:6a4db94011d3 1297 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
sahilmgandhi 18:6a4db94011d3 1298 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
sahilmgandhi 18:6a4db94011d3 1299 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
sahilmgandhi 18:6a4db94011d3 1300 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
sahilmgandhi 18:6a4db94011d3 1301 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
sahilmgandhi 18:6a4db94011d3 1302 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
sahilmgandhi 18:6a4db94011d3 1303 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
sahilmgandhi 18:6a4db94011d3 1304 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
sahilmgandhi 18:6a4db94011d3 1305 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
sahilmgandhi 18:6a4db94011d3 1306 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
sahilmgandhi 18:6a4db94011d3 1307 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
sahilmgandhi 18:6a4db94011d3 1308 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
sahilmgandhi 18:6a4db94011d3 1309 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
sahilmgandhi 18:6a4db94011d3 1310 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
sahilmgandhi 18:6a4db94011d3 1311 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
sahilmgandhi 18:6a4db94011d3 1312 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
sahilmgandhi 18:6a4db94011d3 1313 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
sahilmgandhi 18:6a4db94011d3 1314 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
sahilmgandhi 18:6a4db94011d3 1315 #define ETH ((ETH_TypeDef *) ETH_BASE)
sahilmgandhi 18:6a4db94011d3 1316 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
sahilmgandhi 18:6a4db94011d3 1317 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
sahilmgandhi 18:6a4db94011d3 1318 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
sahilmgandhi 18:6a4db94011d3 1319 #define HASH ((HASH_TypeDef *) HASH_BASE)
sahilmgandhi 18:6a4db94011d3 1320 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
sahilmgandhi 18:6a4db94011d3 1321 #define RNG ((RNG_TypeDef *) RNG_BASE)
sahilmgandhi 18:6a4db94011d3 1322 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
sahilmgandhi 18:6a4db94011d3 1323 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
sahilmgandhi 18:6a4db94011d3 1324 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
sahilmgandhi 18:6a4db94011d3 1325 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
sahilmgandhi 18:6a4db94011d3 1326 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
sahilmgandhi 18:6a4db94011d3 1327 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
sahilmgandhi 18:6a4db94011d3 1328 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
sahilmgandhi 18:6a4db94011d3 1329 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
sahilmgandhi 18:6a4db94011d3 1330
sahilmgandhi 18:6a4db94011d3 1331 /**
sahilmgandhi 18:6a4db94011d3 1332 * @}
sahilmgandhi 18:6a4db94011d3 1333 */
sahilmgandhi 18:6a4db94011d3 1334
sahilmgandhi 18:6a4db94011d3 1335 /** @addtogroup Exported_constants
sahilmgandhi 18:6a4db94011d3 1336 * @{
sahilmgandhi 18:6a4db94011d3 1337 */
sahilmgandhi 18:6a4db94011d3 1338
sahilmgandhi 18:6a4db94011d3 1339 /** @addtogroup Peripheral_Registers_Bits_Definition
sahilmgandhi 18:6a4db94011d3 1340 * @{
sahilmgandhi 18:6a4db94011d3 1341 */
sahilmgandhi 18:6a4db94011d3 1342
sahilmgandhi 18:6a4db94011d3 1343 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1344 /* Peripheral Registers_Bits_Definition */
sahilmgandhi 18:6a4db94011d3 1345 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1346
sahilmgandhi 18:6a4db94011d3 1347 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1348 /* */
sahilmgandhi 18:6a4db94011d3 1349 /* Analog to Digital Converter */
sahilmgandhi 18:6a4db94011d3 1350 /* */
sahilmgandhi 18:6a4db94011d3 1351 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1352 /******************** Bit definition for ADC_SR register ********************/
sahilmgandhi 18:6a4db94011d3 1353 #define ADC_SR_AWD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1354 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1355 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1356 #define ADC_SR_EOC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1357 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1358 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
sahilmgandhi 18:6a4db94011d3 1359 #define ADC_SR_JEOC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1360 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1361 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1362 #define ADC_SR_JSTRT_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1363 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1364 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1365 #define ADC_SR_STRT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1366 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1367 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1368 #define ADC_SR_OVR_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1369 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1370 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
sahilmgandhi 18:6a4db94011d3 1371
sahilmgandhi 18:6a4db94011d3 1372 /******************* Bit definition for ADC_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 1373 #define ADC_CR1_AWDCH_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1374 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 1375 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
sahilmgandhi 18:6a4db94011d3 1376 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1377 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1378 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1379 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1380 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1381 #define ADC_CR1_EOCIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1382 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1383 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
sahilmgandhi 18:6a4db94011d3 1384 #define ADC_CR1_AWDIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1385 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1386 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
sahilmgandhi 18:6a4db94011d3 1387 #define ADC_CR1_JEOCIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1388 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1389 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
sahilmgandhi 18:6a4db94011d3 1390 #define ADC_CR1_SCAN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1391 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1392 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
sahilmgandhi 18:6a4db94011d3 1393 #define ADC_CR1_AWDSGL_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1394 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1395 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
sahilmgandhi 18:6a4db94011d3 1396 #define ADC_CR1_JAUTO_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1397 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1398 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
sahilmgandhi 18:6a4db94011d3 1399 #define ADC_CR1_DISCEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1400 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1401 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
sahilmgandhi 18:6a4db94011d3 1402 #define ADC_CR1_JDISCEN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1403 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1404 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
sahilmgandhi 18:6a4db94011d3 1405 #define ADC_CR1_DISCNUM_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1406 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 1407 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
sahilmgandhi 18:6a4db94011d3 1408 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1409 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1410 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1411 #define ADC_CR1_JAWDEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1412 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1413 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
sahilmgandhi 18:6a4db94011d3 1414 #define ADC_CR1_AWDEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1415 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1416 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
sahilmgandhi 18:6a4db94011d3 1417 #define ADC_CR1_RES_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1418 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 1419 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
sahilmgandhi 18:6a4db94011d3 1420 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1421 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1422 #define ADC_CR1_OVRIE_Pos (26U)
sahilmgandhi 18:6a4db94011d3 1423 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1424 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
sahilmgandhi 18:6a4db94011d3 1425
sahilmgandhi 18:6a4db94011d3 1426 /******************* Bit definition for ADC_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 1427 #define ADC_CR2_ADON_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1428 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1429 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
sahilmgandhi 18:6a4db94011d3 1430 #define ADC_CR2_CONT_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1431 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1432 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
sahilmgandhi 18:6a4db94011d3 1433 #define ADC_CR2_DMA_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1434 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1435 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
sahilmgandhi 18:6a4db94011d3 1436 #define ADC_CR2_DDS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1437 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1438 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
sahilmgandhi 18:6a4db94011d3 1439 #define ADC_CR2_EOCS_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1440 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1441 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
sahilmgandhi 18:6a4db94011d3 1442 #define ADC_CR2_ALIGN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1443 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1444 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
sahilmgandhi 18:6a4db94011d3 1445 #define ADC_CR2_JEXTSEL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1446 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 1447 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
sahilmgandhi 18:6a4db94011d3 1448 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1449 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1450 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1451 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1452 #define ADC_CR2_JEXTEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1453 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 1454 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
sahilmgandhi 18:6a4db94011d3 1455 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1456 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1457 #define ADC_CR2_JSWSTART_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1458 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1459 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
sahilmgandhi 18:6a4db94011d3 1460 #define ADC_CR2_EXTSEL_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1461 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 1462 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
sahilmgandhi 18:6a4db94011d3 1463 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1464 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1465 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1466 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1467 #define ADC_CR2_EXTEN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 1468 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 1469 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
sahilmgandhi 18:6a4db94011d3 1470 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1471 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1472 #define ADC_CR2_SWSTART_Pos (30U)
sahilmgandhi 18:6a4db94011d3 1473 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 1474 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
sahilmgandhi 18:6a4db94011d3 1475
sahilmgandhi 18:6a4db94011d3 1476 /****************** Bit definition for ADC_SMPR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1477 #define ADC_SMPR1_SMP10_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1478 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 1479 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1480 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1481 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1482 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1483 #define ADC_SMPR1_SMP11_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1484 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 1485 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1486 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1487 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1488 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1489 #define ADC_SMPR1_SMP12_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1490 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
sahilmgandhi 18:6a4db94011d3 1491 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1492 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1493 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1494 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1495 #define ADC_SMPR1_SMP13_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1496 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
sahilmgandhi 18:6a4db94011d3 1497 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1498 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1499 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1500 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1501 #define ADC_SMPR1_SMP14_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1502 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 1503 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1504 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1505 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1506 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1507 #define ADC_SMPR1_SMP15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1508 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
sahilmgandhi 18:6a4db94011d3 1509 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1510 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1511 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1512 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1513 #define ADC_SMPR1_SMP16_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1514 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
sahilmgandhi 18:6a4db94011d3 1515 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1516 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1517 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1518 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1519 #define ADC_SMPR1_SMP17_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1520 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
sahilmgandhi 18:6a4db94011d3 1521 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1522 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1523 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1524 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1525 #define ADC_SMPR1_SMP18_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1526 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
sahilmgandhi 18:6a4db94011d3 1527 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1528 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1529 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1530 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1531
sahilmgandhi 18:6a4db94011d3 1532 /****************** Bit definition for ADC_SMPR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1533 #define ADC_SMPR2_SMP0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1534 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 1535 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1536 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1537 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1538 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1539 #define ADC_SMPR2_SMP1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1540 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 1541 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1542 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1543 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1544 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1545 #define ADC_SMPR2_SMP2_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1546 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
sahilmgandhi 18:6a4db94011d3 1547 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1548 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1549 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1550 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1551 #define ADC_SMPR2_SMP3_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1552 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
sahilmgandhi 18:6a4db94011d3 1553 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1554 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1555 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1556 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1557 #define ADC_SMPR2_SMP4_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1558 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 1559 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1560 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1561 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1562 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1563 #define ADC_SMPR2_SMP5_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1564 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
sahilmgandhi 18:6a4db94011d3 1565 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1566 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1567 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1568 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1569 #define ADC_SMPR2_SMP6_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1570 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
sahilmgandhi 18:6a4db94011d3 1571 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1572 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1573 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1574 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1575 #define ADC_SMPR2_SMP7_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1576 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
sahilmgandhi 18:6a4db94011d3 1577 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1578 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1579 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1580 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1581 #define ADC_SMPR2_SMP8_Pos (24U)
sahilmgandhi 18:6a4db94011d3 1582 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
sahilmgandhi 18:6a4db94011d3 1583 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1584 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1585 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1586 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1587 #define ADC_SMPR2_SMP9_Pos (27U)
sahilmgandhi 18:6a4db94011d3 1588 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
sahilmgandhi 18:6a4db94011d3 1589 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
sahilmgandhi 18:6a4db94011d3 1590 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1591 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1592 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1593
sahilmgandhi 18:6a4db94011d3 1594 /****************** Bit definition for ADC_JOFR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1595 #define ADC_JOFR1_JOFFSET1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1596 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1597 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
sahilmgandhi 18:6a4db94011d3 1598
sahilmgandhi 18:6a4db94011d3 1599 /****************** Bit definition for ADC_JOFR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1600 #define ADC_JOFR2_JOFFSET2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1601 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1602 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
sahilmgandhi 18:6a4db94011d3 1603
sahilmgandhi 18:6a4db94011d3 1604 /****************** Bit definition for ADC_JOFR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1605 #define ADC_JOFR3_JOFFSET3_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1606 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1607 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
sahilmgandhi 18:6a4db94011d3 1608
sahilmgandhi 18:6a4db94011d3 1609 /****************** Bit definition for ADC_JOFR4 register *******************/
sahilmgandhi 18:6a4db94011d3 1610 #define ADC_JOFR4_JOFFSET4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1611 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1612 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
sahilmgandhi 18:6a4db94011d3 1613
sahilmgandhi 18:6a4db94011d3 1614 /******************* Bit definition for ADC_HTR register ********************/
sahilmgandhi 18:6a4db94011d3 1615 #define ADC_HTR_HT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1616 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1617 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
sahilmgandhi 18:6a4db94011d3 1618
sahilmgandhi 18:6a4db94011d3 1619 /******************* Bit definition for ADC_LTR register ********************/
sahilmgandhi 18:6a4db94011d3 1620 #define ADC_LTR_LT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1621 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 1622 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
sahilmgandhi 18:6a4db94011d3 1623
sahilmgandhi 18:6a4db94011d3 1624 /******************* Bit definition for ADC_SQR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1625 #define ADC_SQR1_SQ13_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1626 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 1627 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1628 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1629 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1630 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1631 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1632 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1633 #define ADC_SQR1_SQ14_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1634 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
sahilmgandhi 18:6a4db94011d3 1635 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1636 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1637 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1638 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1639 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1640 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1641 #define ADC_SQR1_SQ15_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1642 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
sahilmgandhi 18:6a4db94011d3 1643 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1644 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1645 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1646 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1647 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1648 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1649 #define ADC_SQR1_SQ16_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1650 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
sahilmgandhi 18:6a4db94011d3 1651 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1652 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1653 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1654 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1655 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1656 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1657 #define ADC_SQR1_L_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1658 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 1659 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
sahilmgandhi 18:6a4db94011d3 1660 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1661 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1662 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1663 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1664
sahilmgandhi 18:6a4db94011d3 1665 /******************* Bit definition for ADC_SQR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1666 #define ADC_SQR2_SQ7_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1667 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 1668 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1669 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1670 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1671 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1672 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1673 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1674 #define ADC_SQR2_SQ8_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1675 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
sahilmgandhi 18:6a4db94011d3 1676 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1677 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1678 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1679 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1680 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1681 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1682 #define ADC_SQR2_SQ9_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1683 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
sahilmgandhi 18:6a4db94011d3 1684 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1685 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1686 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1687 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1688 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1689 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1690 #define ADC_SQR2_SQ10_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1691 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
sahilmgandhi 18:6a4db94011d3 1692 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1693 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1694 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1695 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1696 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1697 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1698 #define ADC_SQR2_SQ11_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1699 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
sahilmgandhi 18:6a4db94011d3 1700 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1701 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1702 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1703 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1704 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1705 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1706 #define ADC_SQR2_SQ12_Pos (25U)
sahilmgandhi 18:6a4db94011d3 1707 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
sahilmgandhi 18:6a4db94011d3 1708 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1709 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1710 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1711 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1712 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1713 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1714
sahilmgandhi 18:6a4db94011d3 1715 /******************* Bit definition for ADC_SQR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1716 #define ADC_SQR3_SQ1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1717 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 1718 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1719 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1720 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1721 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1722 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1723 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1724 #define ADC_SQR3_SQ2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1725 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
sahilmgandhi 18:6a4db94011d3 1726 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1727 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1728 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1729 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1730 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1731 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1732 #define ADC_SQR3_SQ3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1733 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
sahilmgandhi 18:6a4db94011d3 1734 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1735 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1736 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1737 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1738 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1739 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1740 #define ADC_SQR3_SQ4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1741 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
sahilmgandhi 18:6a4db94011d3 1742 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1743 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1744 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1745 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1746 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1747 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1748 #define ADC_SQR3_SQ5_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1749 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
sahilmgandhi 18:6a4db94011d3 1750 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1751 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1752 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1753 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1754 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1755 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 1756 #define ADC_SQR3_SQ6_Pos (25U)
sahilmgandhi 18:6a4db94011d3 1757 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
sahilmgandhi 18:6a4db94011d3 1758 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
sahilmgandhi 18:6a4db94011d3 1759 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 1760 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 1761 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 1762 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 1763 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 1764
sahilmgandhi 18:6a4db94011d3 1765 /******************* Bit definition for ADC_JSQR register *******************/
sahilmgandhi 18:6a4db94011d3 1766 #define ADC_JSQR_JSQ1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1767 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 1768 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1769 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1770 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1771 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1772 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1773 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1774 #define ADC_JSQR_JSQ2_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1775 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
sahilmgandhi 18:6a4db94011d3 1776 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1777 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1778 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1779 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1780 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1781 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1782 #define ADC_JSQR_JSQ3_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1783 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
sahilmgandhi 18:6a4db94011d3 1784 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1785 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1786 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1787 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1788 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1789 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1790 #define ADC_JSQR_JSQ4_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1791 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
sahilmgandhi 18:6a4db94011d3 1792 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
sahilmgandhi 18:6a4db94011d3 1793 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1794 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1795 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1796 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1797 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1798 #define ADC_JSQR_JL_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1799 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 1800 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
sahilmgandhi 18:6a4db94011d3 1801 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1802 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1803
sahilmgandhi 18:6a4db94011d3 1804 /******************* Bit definition for ADC_JDR1 register *******************/
sahilmgandhi 18:6a4db94011d3 1805 #define ADC_JDR1_JDATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1806 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1807 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1808
sahilmgandhi 18:6a4db94011d3 1809 /******************* Bit definition for ADC_JDR2 register *******************/
sahilmgandhi 18:6a4db94011d3 1810 #define ADC_JDR2_JDATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1811 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1812 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1813
sahilmgandhi 18:6a4db94011d3 1814 /******************* Bit definition for ADC_JDR3 register *******************/
sahilmgandhi 18:6a4db94011d3 1815 #define ADC_JDR3_JDATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1816 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1817 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1818
sahilmgandhi 18:6a4db94011d3 1819 /******************* Bit definition for ADC_JDR4 register *******************/
sahilmgandhi 18:6a4db94011d3 1820 #define ADC_JDR4_JDATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1821 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1822 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
sahilmgandhi 18:6a4db94011d3 1823
sahilmgandhi 18:6a4db94011d3 1824 /******************** Bit definition for ADC_DR register ********************/
sahilmgandhi 18:6a4db94011d3 1825 #define ADC_DR_DATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1826 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1827 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
sahilmgandhi 18:6a4db94011d3 1828 #define ADC_DR_ADC2DATA_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1829 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 1830 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
sahilmgandhi 18:6a4db94011d3 1831
sahilmgandhi 18:6a4db94011d3 1832 /******************* Bit definition for ADC_CSR register ********************/
sahilmgandhi 18:6a4db94011d3 1833 #define ADC_CSR_AWD1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1834 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1835 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1836 #define ADC_CSR_EOC1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1837 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1838 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
sahilmgandhi 18:6a4db94011d3 1839 #define ADC_CSR_JEOC1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1840 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1841 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1842 #define ADC_CSR_JSTRT1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1843 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1844 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1845 #define ADC_CSR_STRT1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1846 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1847 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1848 #define ADC_CSR_OVR1_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1849 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1850 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1851 #define ADC_CSR_AWD2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1852 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1853 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1854 #define ADC_CSR_EOC2_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1855 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1856 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
sahilmgandhi 18:6a4db94011d3 1857 #define ADC_CSR_JEOC2_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1858 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1859 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1860 #define ADC_CSR_JSTRT2_Pos (11U)
sahilmgandhi 18:6a4db94011d3 1861 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1862 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1863 #define ADC_CSR_STRT2_Pos (12U)
sahilmgandhi 18:6a4db94011d3 1864 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 1865 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1866 #define ADC_CSR_OVR2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1867 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1868 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1869 #define ADC_CSR_AWD3_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1870 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1871 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
sahilmgandhi 18:6a4db94011d3 1872 #define ADC_CSR_EOC3_Pos (17U)
sahilmgandhi 18:6a4db94011d3 1873 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1874 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
sahilmgandhi 18:6a4db94011d3 1875 #define ADC_CSR_JEOC3_Pos (18U)
sahilmgandhi 18:6a4db94011d3 1876 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 1877 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
sahilmgandhi 18:6a4db94011d3 1878 #define ADC_CSR_JSTRT3_Pos (19U)
sahilmgandhi 18:6a4db94011d3 1879 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 1880 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
sahilmgandhi 18:6a4db94011d3 1881 #define ADC_CSR_STRT3_Pos (20U)
sahilmgandhi 18:6a4db94011d3 1882 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 1883 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
sahilmgandhi 18:6a4db94011d3 1884 #define ADC_CSR_OVR3_Pos (21U)
sahilmgandhi 18:6a4db94011d3 1885 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 1886 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
sahilmgandhi 18:6a4db94011d3 1887
sahilmgandhi 18:6a4db94011d3 1888 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 1889 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
sahilmgandhi 18:6a4db94011d3 1890 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
sahilmgandhi 18:6a4db94011d3 1891 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
sahilmgandhi 18:6a4db94011d3 1892
sahilmgandhi 18:6a4db94011d3 1893 /******************* Bit definition for ADC_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 1894 #define ADC_CCR_MULTI_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1895 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 1896 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
sahilmgandhi 18:6a4db94011d3 1897 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1898 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1899 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1900 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1901 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1902 #define ADC_CCR_DELAY_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1903 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 1904 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
sahilmgandhi 18:6a4db94011d3 1905 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1906 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1907 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1908 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 1909 #define ADC_CCR_DDS_Pos (13U)
sahilmgandhi 18:6a4db94011d3 1910 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 1911 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
sahilmgandhi 18:6a4db94011d3 1912 #define ADC_CCR_DMA_Pos (14U)
sahilmgandhi 18:6a4db94011d3 1913 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 1914 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
sahilmgandhi 18:6a4db94011d3 1915 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 1916 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1917 #define ADC_CCR_ADCPRE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1918 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 1919 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
sahilmgandhi 18:6a4db94011d3 1920 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1921 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 1922 #define ADC_CCR_VBATE_Pos (22U)
sahilmgandhi 18:6a4db94011d3 1923 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 1924 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
sahilmgandhi 18:6a4db94011d3 1925 #define ADC_CCR_TSVREFE_Pos (23U)
sahilmgandhi 18:6a4db94011d3 1926 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 1927 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
sahilmgandhi 18:6a4db94011d3 1928
sahilmgandhi 18:6a4db94011d3 1929 /******************* Bit definition for ADC_CDR register ********************/
sahilmgandhi 18:6a4db94011d3 1930 #define ADC_CDR_DATA1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1931 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 1932 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
sahilmgandhi 18:6a4db94011d3 1933 #define ADC_CDR_DATA2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1934 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 1935 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
sahilmgandhi 18:6a4db94011d3 1936
sahilmgandhi 18:6a4db94011d3 1937 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1938 /* */
sahilmgandhi 18:6a4db94011d3 1939 /* Controller Area Network */
sahilmgandhi 18:6a4db94011d3 1940 /* */
sahilmgandhi 18:6a4db94011d3 1941 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 1942 /*!<CAN control and status registers */
sahilmgandhi 18:6a4db94011d3 1943 /******************* Bit definition for CAN_MCR register ********************/
sahilmgandhi 18:6a4db94011d3 1944 #define CAN_MCR_INRQ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1945 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1946 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
sahilmgandhi 18:6a4db94011d3 1947 #define CAN_MCR_SLEEP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1948 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1949 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
sahilmgandhi 18:6a4db94011d3 1950 #define CAN_MCR_TXFP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1951 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1952 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
sahilmgandhi 18:6a4db94011d3 1953 #define CAN_MCR_RFLM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1954 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1955 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
sahilmgandhi 18:6a4db94011d3 1956 #define CAN_MCR_NART_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1957 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1958 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
sahilmgandhi 18:6a4db94011d3 1959 #define CAN_MCR_AWUM_Pos (5U)
sahilmgandhi 18:6a4db94011d3 1960 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 1961 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
sahilmgandhi 18:6a4db94011d3 1962 #define CAN_MCR_ABOM_Pos (6U)
sahilmgandhi 18:6a4db94011d3 1963 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 1964 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
sahilmgandhi 18:6a4db94011d3 1965 #define CAN_MCR_TTCM_Pos (7U)
sahilmgandhi 18:6a4db94011d3 1966 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 1967 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
sahilmgandhi 18:6a4db94011d3 1968 #define CAN_MCR_RESET_Pos (15U)
sahilmgandhi 18:6a4db94011d3 1969 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 1970 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
sahilmgandhi 18:6a4db94011d3 1971 #define CAN_MCR_DBF_Pos (16U)
sahilmgandhi 18:6a4db94011d3 1972 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 1973 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
sahilmgandhi 18:6a4db94011d3 1974 /******************* Bit definition for CAN_MSR register ********************/
sahilmgandhi 18:6a4db94011d3 1975 #define CAN_MSR_INAK_Pos (0U)
sahilmgandhi 18:6a4db94011d3 1976 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 1977 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
sahilmgandhi 18:6a4db94011d3 1978 #define CAN_MSR_SLAK_Pos (1U)
sahilmgandhi 18:6a4db94011d3 1979 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 1980 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
sahilmgandhi 18:6a4db94011d3 1981 #define CAN_MSR_ERRI_Pos (2U)
sahilmgandhi 18:6a4db94011d3 1982 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 1983 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
sahilmgandhi 18:6a4db94011d3 1984 #define CAN_MSR_WKUI_Pos (3U)
sahilmgandhi 18:6a4db94011d3 1985 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 1986 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
sahilmgandhi 18:6a4db94011d3 1987 #define CAN_MSR_SLAKI_Pos (4U)
sahilmgandhi 18:6a4db94011d3 1988 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 1989 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
sahilmgandhi 18:6a4db94011d3 1990 #define CAN_MSR_TXM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 1991 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 1992 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
sahilmgandhi 18:6a4db94011d3 1993 #define CAN_MSR_RXM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 1994 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 1995 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
sahilmgandhi 18:6a4db94011d3 1996 #define CAN_MSR_SAMP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 1997 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 1998 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
sahilmgandhi 18:6a4db94011d3 1999 #define CAN_MSR_RX_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2000 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2001 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
sahilmgandhi 18:6a4db94011d3 2002
sahilmgandhi 18:6a4db94011d3 2003 /******************* Bit definition for CAN_TSR register ********************/
sahilmgandhi 18:6a4db94011d3 2004 #define CAN_TSR_RQCP0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2005 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2006 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
sahilmgandhi 18:6a4db94011d3 2007 #define CAN_TSR_TXOK0_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2008 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2009 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
sahilmgandhi 18:6a4db94011d3 2010 #define CAN_TSR_ALST0_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2011 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2012 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
sahilmgandhi 18:6a4db94011d3 2013 #define CAN_TSR_TERR0_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2014 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2015 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
sahilmgandhi 18:6a4db94011d3 2016 #define CAN_TSR_ABRQ0_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2017 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2018 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
sahilmgandhi 18:6a4db94011d3 2019 #define CAN_TSR_RQCP1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2020 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2021 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
sahilmgandhi 18:6a4db94011d3 2022 #define CAN_TSR_TXOK1_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2023 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2024 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
sahilmgandhi 18:6a4db94011d3 2025 #define CAN_TSR_ALST1_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2026 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2027 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
sahilmgandhi 18:6a4db94011d3 2028 #define CAN_TSR_TERR1_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2029 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2030 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
sahilmgandhi 18:6a4db94011d3 2031 #define CAN_TSR_ABRQ1_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2032 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2033 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
sahilmgandhi 18:6a4db94011d3 2034 #define CAN_TSR_RQCP2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2035 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2036 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
sahilmgandhi 18:6a4db94011d3 2037 #define CAN_TSR_TXOK2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2038 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2039 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
sahilmgandhi 18:6a4db94011d3 2040 #define CAN_TSR_ALST2_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2041 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2042 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
sahilmgandhi 18:6a4db94011d3 2043 #define CAN_TSR_TERR2_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2044 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2045 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
sahilmgandhi 18:6a4db94011d3 2046 #define CAN_TSR_ABRQ2_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2047 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2048 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
sahilmgandhi 18:6a4db94011d3 2049 #define CAN_TSR_CODE_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2050 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 2051 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
sahilmgandhi 18:6a4db94011d3 2052
sahilmgandhi 18:6a4db94011d3 2053 #define CAN_TSR_TME_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2054 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
sahilmgandhi 18:6a4db94011d3 2055 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
sahilmgandhi 18:6a4db94011d3 2056 #define CAN_TSR_TME0_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2057 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2058 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
sahilmgandhi 18:6a4db94011d3 2059 #define CAN_TSR_TME1_Pos (27U)
sahilmgandhi 18:6a4db94011d3 2060 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2061 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
sahilmgandhi 18:6a4db94011d3 2062 #define CAN_TSR_TME2_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2063 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2064 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
sahilmgandhi 18:6a4db94011d3 2065
sahilmgandhi 18:6a4db94011d3 2066 #define CAN_TSR_LOW_Pos (29U)
sahilmgandhi 18:6a4db94011d3 2067 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
sahilmgandhi 18:6a4db94011d3 2068 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
sahilmgandhi 18:6a4db94011d3 2069 #define CAN_TSR_LOW0_Pos (29U)
sahilmgandhi 18:6a4db94011d3 2070 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2071 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
sahilmgandhi 18:6a4db94011d3 2072 #define CAN_TSR_LOW1_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2073 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2074 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
sahilmgandhi 18:6a4db94011d3 2075 #define CAN_TSR_LOW2_Pos (31U)
sahilmgandhi 18:6a4db94011d3 2076 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2077 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
sahilmgandhi 18:6a4db94011d3 2078
sahilmgandhi 18:6a4db94011d3 2079 /******************* Bit definition for CAN_RF0R register *******************/
sahilmgandhi 18:6a4db94011d3 2080 #define CAN_RF0R_FMP0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2081 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 2082 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
sahilmgandhi 18:6a4db94011d3 2083 #define CAN_RF0R_FULL0_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2084 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2085 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
sahilmgandhi 18:6a4db94011d3 2086 #define CAN_RF0R_FOVR0_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2087 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2088 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
sahilmgandhi 18:6a4db94011d3 2089 #define CAN_RF0R_RFOM0_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2090 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2091 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
sahilmgandhi 18:6a4db94011d3 2092
sahilmgandhi 18:6a4db94011d3 2093 /******************* Bit definition for CAN_RF1R register *******************/
sahilmgandhi 18:6a4db94011d3 2094 #define CAN_RF1R_FMP1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2095 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 2096 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
sahilmgandhi 18:6a4db94011d3 2097 #define CAN_RF1R_FULL1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2098 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2099 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
sahilmgandhi 18:6a4db94011d3 2100 #define CAN_RF1R_FOVR1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2101 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2102 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
sahilmgandhi 18:6a4db94011d3 2103 #define CAN_RF1R_RFOM1_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2104 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2105 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
sahilmgandhi 18:6a4db94011d3 2106
sahilmgandhi 18:6a4db94011d3 2107 /******************** Bit definition for CAN_IER register *******************/
sahilmgandhi 18:6a4db94011d3 2108 #define CAN_IER_TMEIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2109 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2110 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2111 #define CAN_IER_FMPIE0_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2112 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2113 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2114 #define CAN_IER_FFIE0_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2115 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2116 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2117 #define CAN_IER_FOVIE0_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2118 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2119 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2120 #define CAN_IER_FMPIE1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2121 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2122 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2123 #define CAN_IER_FFIE1_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2124 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2125 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2126 #define CAN_IER_FOVIE1_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2127 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2128 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2129 #define CAN_IER_EWGIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2130 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2131 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2132 #define CAN_IER_EPVIE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2133 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2134 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2135 #define CAN_IER_BOFIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2136 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2137 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2138 #define CAN_IER_LECIE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2139 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2140 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2141 #define CAN_IER_ERRIE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2142 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2143 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2144 #define CAN_IER_WKUIE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2145 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2146 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2147 #define CAN_IER_SLKIE_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2148 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2149 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 2150 #define CAN_IER_EWGIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2151 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2152 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error warning interrupt enable */
sahilmgandhi 18:6a4db94011d3 2153 #define CAN_IER_EPVIE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2154 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2155 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error passive interrupt enable */
sahilmgandhi 18:6a4db94011d3 2156 #define CAN_IER_BOFIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2157 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2158 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-off interrupt enable */
sahilmgandhi 18:6a4db94011d3 2159 #define CAN_IER_LECIE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2160 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2161 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last error code interrupt enable */
sahilmgandhi 18:6a4db94011d3 2162 #define CAN_IER_ERRIE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2163 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2164 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error interrupt enable */
sahilmgandhi 18:6a4db94011d3 2165
sahilmgandhi 18:6a4db94011d3 2166
sahilmgandhi 18:6a4db94011d3 2167 /******************** Bit definition for CAN_ESR register *******************/
sahilmgandhi 18:6a4db94011d3 2168 #define CAN_ESR_EWGF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2169 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2170 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
sahilmgandhi 18:6a4db94011d3 2171 #define CAN_ESR_EPVF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2172 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2173 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
sahilmgandhi 18:6a4db94011d3 2174 #define CAN_ESR_BOFF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2175 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2176 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
sahilmgandhi 18:6a4db94011d3 2177
sahilmgandhi 18:6a4db94011d3 2178 #define CAN_ESR_LEC_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2179 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 2180 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
sahilmgandhi 18:6a4db94011d3 2181 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2182 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2183 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2184
sahilmgandhi 18:6a4db94011d3 2185 #define CAN_ESR_TEC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2186 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2187 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
sahilmgandhi 18:6a4db94011d3 2188 #define CAN_ESR_REC_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2189 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2190 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
sahilmgandhi 18:6a4db94011d3 2191
sahilmgandhi 18:6a4db94011d3 2192 /******************* Bit definition for CAN_BTR register ********************/
sahilmgandhi 18:6a4db94011d3 2193 #define CAN_BTR_BRP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2194 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
sahilmgandhi 18:6a4db94011d3 2195 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
sahilmgandhi 18:6a4db94011d3 2196 #define CAN_BTR_TS1_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2197 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 2198 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
sahilmgandhi 18:6a4db94011d3 2199 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2200 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2201 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2202 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2203 #define CAN_BTR_TS2_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2204 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
sahilmgandhi 18:6a4db94011d3 2205 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
sahilmgandhi 18:6a4db94011d3 2206 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2207 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2208 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2209 #define CAN_BTR_SJW_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2210 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 2211 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
sahilmgandhi 18:6a4db94011d3 2212 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2213 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2214 #define CAN_BTR_LBKM_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2215 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2216 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
sahilmgandhi 18:6a4db94011d3 2217 #define CAN_BTR_SILM_Pos (31U)
sahilmgandhi 18:6a4db94011d3 2218 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2219 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
sahilmgandhi 18:6a4db94011d3 2220
sahilmgandhi 18:6a4db94011d3 2221
sahilmgandhi 18:6a4db94011d3 2222 /*!<Mailbox registers */
sahilmgandhi 18:6a4db94011d3 2223 /****************** Bit definition for CAN_TI0R register ********************/
sahilmgandhi 18:6a4db94011d3 2224 #define CAN_TI0R_TXRQ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2225 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2226 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
sahilmgandhi 18:6a4db94011d3 2227 #define CAN_TI0R_RTR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2228 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2229 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 2230 #define CAN_TI0R_IDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2231 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2232 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 2233 #define CAN_TI0R_EXID_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2234 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
sahilmgandhi 18:6a4db94011d3 2235 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
sahilmgandhi 18:6a4db94011d3 2236 #define CAN_TI0R_STID_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2237 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
sahilmgandhi 18:6a4db94011d3 2238 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 2239
sahilmgandhi 18:6a4db94011d3 2240 /****************** Bit definition for CAN_TDT0R register *******************/
sahilmgandhi 18:6a4db94011d3 2241 #define CAN_TDT0R_DLC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2242 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 2243 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 2244 #define CAN_TDT0R_TGT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2245 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2246 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
sahilmgandhi 18:6a4db94011d3 2247 #define CAN_TDT0R_TIME_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2248 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 2249 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 2250
sahilmgandhi 18:6a4db94011d3 2251 /****************** Bit definition for CAN_TDL0R register *******************/
sahilmgandhi 18:6a4db94011d3 2252 #define CAN_TDL0R_DATA0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2253 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2254 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 2255 #define CAN_TDL0R_DATA1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2256 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2257 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 2258 #define CAN_TDL0R_DATA2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2259 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2260 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 2261 #define CAN_TDL0R_DATA3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2262 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2263 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 2264
sahilmgandhi 18:6a4db94011d3 2265 /****************** Bit definition for CAN_TDH0R register *******************/
sahilmgandhi 18:6a4db94011d3 2266 #define CAN_TDH0R_DATA4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2267 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2268 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 2269 #define CAN_TDH0R_DATA5_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2270 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2271 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 2272 #define CAN_TDH0R_DATA6_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2273 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2274 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 2275 #define CAN_TDH0R_DATA7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2276 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2277 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 2278
sahilmgandhi 18:6a4db94011d3 2279 /******************* Bit definition for CAN_TI1R register *******************/
sahilmgandhi 18:6a4db94011d3 2280 #define CAN_TI1R_TXRQ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2281 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2282 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
sahilmgandhi 18:6a4db94011d3 2283 #define CAN_TI1R_RTR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2284 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2285 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 2286 #define CAN_TI1R_IDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2287 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2288 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 2289 #define CAN_TI1R_EXID_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2290 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
sahilmgandhi 18:6a4db94011d3 2291 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
sahilmgandhi 18:6a4db94011d3 2292 #define CAN_TI1R_STID_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2293 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
sahilmgandhi 18:6a4db94011d3 2294 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 2295
sahilmgandhi 18:6a4db94011d3 2296 /******************* Bit definition for CAN_TDT1R register ******************/
sahilmgandhi 18:6a4db94011d3 2297 #define CAN_TDT1R_DLC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2298 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 2299 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 2300 #define CAN_TDT1R_TGT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2301 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2302 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
sahilmgandhi 18:6a4db94011d3 2303 #define CAN_TDT1R_TIME_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2304 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 2305 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 2306
sahilmgandhi 18:6a4db94011d3 2307 /******************* Bit definition for CAN_TDL1R register ******************/
sahilmgandhi 18:6a4db94011d3 2308 #define CAN_TDL1R_DATA0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2309 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2310 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 2311 #define CAN_TDL1R_DATA1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2312 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2313 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 2314 #define CAN_TDL1R_DATA2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2315 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2316 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 2317 #define CAN_TDL1R_DATA3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2318 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2319 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 2320
sahilmgandhi 18:6a4db94011d3 2321 /******************* Bit definition for CAN_TDH1R register ******************/
sahilmgandhi 18:6a4db94011d3 2322 #define CAN_TDH1R_DATA4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2323 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2324 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 2325 #define CAN_TDH1R_DATA5_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2326 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2327 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 2328 #define CAN_TDH1R_DATA6_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2329 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2330 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 2331 #define CAN_TDH1R_DATA7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2332 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2333 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 2334
sahilmgandhi 18:6a4db94011d3 2335 /******************* Bit definition for CAN_TI2R register *******************/
sahilmgandhi 18:6a4db94011d3 2336 #define CAN_TI2R_TXRQ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2337 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2338 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
sahilmgandhi 18:6a4db94011d3 2339 #define CAN_TI2R_RTR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2340 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2341 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 2342 #define CAN_TI2R_IDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2343 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2344 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 2345 #define CAN_TI2R_EXID_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2346 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
sahilmgandhi 18:6a4db94011d3 2347 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
sahilmgandhi 18:6a4db94011d3 2348 #define CAN_TI2R_STID_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2349 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
sahilmgandhi 18:6a4db94011d3 2350 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 2351
sahilmgandhi 18:6a4db94011d3 2352 /******************* Bit definition for CAN_TDT2R register ******************/
sahilmgandhi 18:6a4db94011d3 2353 #define CAN_TDT2R_DLC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2354 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 2355 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 2356 #define CAN_TDT2R_TGT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2357 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2358 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
sahilmgandhi 18:6a4db94011d3 2359 #define CAN_TDT2R_TIME_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2360 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 2361 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 2362
sahilmgandhi 18:6a4db94011d3 2363 /******************* Bit definition for CAN_TDL2R register ******************/
sahilmgandhi 18:6a4db94011d3 2364 #define CAN_TDL2R_DATA0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2365 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2366 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 2367 #define CAN_TDL2R_DATA1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2368 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2369 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 2370 #define CAN_TDL2R_DATA2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2371 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2372 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 2373 #define CAN_TDL2R_DATA3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2374 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2375 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 2376
sahilmgandhi 18:6a4db94011d3 2377 /******************* Bit definition for CAN_TDH2R register ******************/
sahilmgandhi 18:6a4db94011d3 2378 #define CAN_TDH2R_DATA4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2379 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2380 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 2381 #define CAN_TDH2R_DATA5_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2382 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2383 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 2384 #define CAN_TDH2R_DATA6_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2385 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2386 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 2387 #define CAN_TDH2R_DATA7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2388 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2389 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 2390
sahilmgandhi 18:6a4db94011d3 2391 /******************* Bit definition for CAN_RI0R register *******************/
sahilmgandhi 18:6a4db94011d3 2392 #define CAN_RI0R_RTR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2393 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2394 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 2395 #define CAN_RI0R_IDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2396 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2397 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 2398 #define CAN_RI0R_EXID_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2399 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
sahilmgandhi 18:6a4db94011d3 2400 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
sahilmgandhi 18:6a4db94011d3 2401 #define CAN_RI0R_STID_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2402 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
sahilmgandhi 18:6a4db94011d3 2403 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 2404
sahilmgandhi 18:6a4db94011d3 2405 /******************* Bit definition for CAN_RDT0R register ******************/
sahilmgandhi 18:6a4db94011d3 2406 #define CAN_RDT0R_DLC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2407 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 2408 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 2409 #define CAN_RDT0R_FMI_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2410 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2411 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
sahilmgandhi 18:6a4db94011d3 2412 #define CAN_RDT0R_TIME_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2413 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 2414 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 2415
sahilmgandhi 18:6a4db94011d3 2416 /******************* Bit definition for CAN_RDL0R register ******************/
sahilmgandhi 18:6a4db94011d3 2417 #define CAN_RDL0R_DATA0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2418 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2419 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 2420 #define CAN_RDL0R_DATA1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2421 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2422 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 2423 #define CAN_RDL0R_DATA2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2424 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2425 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 2426 #define CAN_RDL0R_DATA3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2427 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2428 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 2429
sahilmgandhi 18:6a4db94011d3 2430 /******************* Bit definition for CAN_RDH0R register ******************/
sahilmgandhi 18:6a4db94011d3 2431 #define CAN_RDH0R_DATA4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2432 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2433 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 2434 #define CAN_RDH0R_DATA5_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2435 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2436 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 2437 #define CAN_RDH0R_DATA6_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2438 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2439 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 2440 #define CAN_RDH0R_DATA7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2441 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2442 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 2443
sahilmgandhi 18:6a4db94011d3 2444 /******************* Bit definition for CAN_RI1R register *******************/
sahilmgandhi 18:6a4db94011d3 2445 #define CAN_RI1R_RTR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2446 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2447 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
sahilmgandhi 18:6a4db94011d3 2448 #define CAN_RI1R_IDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2449 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2450 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
sahilmgandhi 18:6a4db94011d3 2451 #define CAN_RI1R_EXID_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2452 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
sahilmgandhi 18:6a4db94011d3 2453 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
sahilmgandhi 18:6a4db94011d3 2454 #define CAN_RI1R_STID_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2455 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
sahilmgandhi 18:6a4db94011d3 2456 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
sahilmgandhi 18:6a4db94011d3 2457
sahilmgandhi 18:6a4db94011d3 2458 /******************* Bit definition for CAN_RDT1R register ******************/
sahilmgandhi 18:6a4db94011d3 2459 #define CAN_RDT1R_DLC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2460 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 2461 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
sahilmgandhi 18:6a4db94011d3 2462 #define CAN_RDT1R_FMI_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2463 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2464 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
sahilmgandhi 18:6a4db94011d3 2465 #define CAN_RDT1R_TIME_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2466 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 2467 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
sahilmgandhi 18:6a4db94011d3 2468
sahilmgandhi 18:6a4db94011d3 2469 /******************* Bit definition for CAN_RDL1R register ******************/
sahilmgandhi 18:6a4db94011d3 2470 #define CAN_RDL1R_DATA0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2471 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2472 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
sahilmgandhi 18:6a4db94011d3 2473 #define CAN_RDL1R_DATA1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2474 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2475 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
sahilmgandhi 18:6a4db94011d3 2476 #define CAN_RDL1R_DATA2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2477 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2478 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
sahilmgandhi 18:6a4db94011d3 2479 #define CAN_RDL1R_DATA3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2480 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2481 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
sahilmgandhi 18:6a4db94011d3 2482
sahilmgandhi 18:6a4db94011d3 2483 /******************* Bit definition for CAN_RDH1R register ******************/
sahilmgandhi 18:6a4db94011d3 2484 #define CAN_RDH1R_DATA4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2485 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 2486 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
sahilmgandhi 18:6a4db94011d3 2487 #define CAN_RDH1R_DATA5_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2488 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 2489 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
sahilmgandhi 18:6a4db94011d3 2490 #define CAN_RDH1R_DATA6_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2491 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 2492 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
sahilmgandhi 18:6a4db94011d3 2493 #define CAN_RDH1R_DATA7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2494 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 2495 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
sahilmgandhi 18:6a4db94011d3 2496
sahilmgandhi 18:6a4db94011d3 2497 /*!<CAN filter registers */
sahilmgandhi 18:6a4db94011d3 2498 /******************* Bit definition for CAN_FMR register ********************/
sahilmgandhi 18:6a4db94011d3 2499 #define CAN_FMR_FINIT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2500 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2501 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
sahilmgandhi 18:6a4db94011d3 2502 #define CAN_FMR_CAN2SB_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2503 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
sahilmgandhi 18:6a4db94011d3 2504 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
sahilmgandhi 18:6a4db94011d3 2505
sahilmgandhi 18:6a4db94011d3 2506 /******************* Bit definition for CAN_FM1R register *******************/
sahilmgandhi 18:6a4db94011d3 2507 #define CAN_FM1R_FBM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2508 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
sahilmgandhi 18:6a4db94011d3 2509 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
sahilmgandhi 18:6a4db94011d3 2510 #define CAN_FM1R_FBM0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2511 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2512 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
sahilmgandhi 18:6a4db94011d3 2513 #define CAN_FM1R_FBM1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2514 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2515 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
sahilmgandhi 18:6a4db94011d3 2516 #define CAN_FM1R_FBM2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2517 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2518 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
sahilmgandhi 18:6a4db94011d3 2519 #define CAN_FM1R_FBM3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2520 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2521 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
sahilmgandhi 18:6a4db94011d3 2522 #define CAN_FM1R_FBM4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2523 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2524 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
sahilmgandhi 18:6a4db94011d3 2525 #define CAN_FM1R_FBM5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2526 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2527 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
sahilmgandhi 18:6a4db94011d3 2528 #define CAN_FM1R_FBM6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2529 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2530 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
sahilmgandhi 18:6a4db94011d3 2531 #define CAN_FM1R_FBM7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2532 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2533 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
sahilmgandhi 18:6a4db94011d3 2534 #define CAN_FM1R_FBM8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2535 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2536 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
sahilmgandhi 18:6a4db94011d3 2537 #define CAN_FM1R_FBM9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2538 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2539 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
sahilmgandhi 18:6a4db94011d3 2540 #define CAN_FM1R_FBM10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2541 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2542 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
sahilmgandhi 18:6a4db94011d3 2543 #define CAN_FM1R_FBM11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2544 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2545 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
sahilmgandhi 18:6a4db94011d3 2546 #define CAN_FM1R_FBM12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2547 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2548 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
sahilmgandhi 18:6a4db94011d3 2549 #define CAN_FM1R_FBM13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2550 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2551 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
sahilmgandhi 18:6a4db94011d3 2552 #define CAN_FM1R_FBM14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2553 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2554 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
sahilmgandhi 18:6a4db94011d3 2555 #define CAN_FM1R_FBM15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2556 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2557 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
sahilmgandhi 18:6a4db94011d3 2558 #define CAN_FM1R_FBM16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2559 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2560 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
sahilmgandhi 18:6a4db94011d3 2561 #define CAN_FM1R_FBM17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2562 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2563 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
sahilmgandhi 18:6a4db94011d3 2564 #define CAN_FM1R_FBM18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2565 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2566 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
sahilmgandhi 18:6a4db94011d3 2567 #define CAN_FM1R_FBM19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2568 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2569 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
sahilmgandhi 18:6a4db94011d3 2570 #define CAN_FM1R_FBM20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2571 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2572 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
sahilmgandhi 18:6a4db94011d3 2573 #define CAN_FM1R_FBM21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2574 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2575 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
sahilmgandhi 18:6a4db94011d3 2576 #define CAN_FM1R_FBM22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2577 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2578 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
sahilmgandhi 18:6a4db94011d3 2579 #define CAN_FM1R_FBM23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2580 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2581 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
sahilmgandhi 18:6a4db94011d3 2582 #define CAN_FM1R_FBM24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2583 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2584 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
sahilmgandhi 18:6a4db94011d3 2585 #define CAN_FM1R_FBM25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 2586 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2587 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
sahilmgandhi 18:6a4db94011d3 2588 #define CAN_FM1R_FBM26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2589 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2590 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
sahilmgandhi 18:6a4db94011d3 2591 #define CAN_FM1R_FBM27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 2592 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2593 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
sahilmgandhi 18:6a4db94011d3 2594
sahilmgandhi 18:6a4db94011d3 2595 /******************* Bit definition for CAN_FS1R register *******************/
sahilmgandhi 18:6a4db94011d3 2596 #define CAN_FS1R_FSC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2597 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
sahilmgandhi 18:6a4db94011d3 2598 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
sahilmgandhi 18:6a4db94011d3 2599 #define CAN_FS1R_FSC0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2600 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2601 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
sahilmgandhi 18:6a4db94011d3 2602 #define CAN_FS1R_FSC1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2603 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2604 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
sahilmgandhi 18:6a4db94011d3 2605 #define CAN_FS1R_FSC2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2606 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2607 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
sahilmgandhi 18:6a4db94011d3 2608 #define CAN_FS1R_FSC3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2609 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2610 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
sahilmgandhi 18:6a4db94011d3 2611 #define CAN_FS1R_FSC4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2612 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2613 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
sahilmgandhi 18:6a4db94011d3 2614 #define CAN_FS1R_FSC5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2615 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2616 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
sahilmgandhi 18:6a4db94011d3 2617 #define CAN_FS1R_FSC6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2618 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2619 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
sahilmgandhi 18:6a4db94011d3 2620 #define CAN_FS1R_FSC7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2621 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2622 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
sahilmgandhi 18:6a4db94011d3 2623 #define CAN_FS1R_FSC8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2624 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2625 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
sahilmgandhi 18:6a4db94011d3 2626 #define CAN_FS1R_FSC9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2627 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2628 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
sahilmgandhi 18:6a4db94011d3 2629 #define CAN_FS1R_FSC10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2630 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2631 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
sahilmgandhi 18:6a4db94011d3 2632 #define CAN_FS1R_FSC11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2633 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2634 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
sahilmgandhi 18:6a4db94011d3 2635 #define CAN_FS1R_FSC12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2636 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2637 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
sahilmgandhi 18:6a4db94011d3 2638 #define CAN_FS1R_FSC13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2639 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2640 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
sahilmgandhi 18:6a4db94011d3 2641 #define CAN_FS1R_FSC14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2642 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2643 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
sahilmgandhi 18:6a4db94011d3 2644 #define CAN_FS1R_FSC15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2645 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2646 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
sahilmgandhi 18:6a4db94011d3 2647 #define CAN_FS1R_FSC16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2648 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2649 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
sahilmgandhi 18:6a4db94011d3 2650 #define CAN_FS1R_FSC17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2651 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2652 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
sahilmgandhi 18:6a4db94011d3 2653 #define CAN_FS1R_FSC18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2654 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2655 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
sahilmgandhi 18:6a4db94011d3 2656 #define CAN_FS1R_FSC19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2657 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2658 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
sahilmgandhi 18:6a4db94011d3 2659 #define CAN_FS1R_FSC20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2660 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2661 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
sahilmgandhi 18:6a4db94011d3 2662 #define CAN_FS1R_FSC21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2663 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2664 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
sahilmgandhi 18:6a4db94011d3 2665 #define CAN_FS1R_FSC22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2666 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2667 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
sahilmgandhi 18:6a4db94011d3 2668 #define CAN_FS1R_FSC23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2669 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2670 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
sahilmgandhi 18:6a4db94011d3 2671 #define CAN_FS1R_FSC24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2672 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2673 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
sahilmgandhi 18:6a4db94011d3 2674 #define CAN_FS1R_FSC25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 2675 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2676 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
sahilmgandhi 18:6a4db94011d3 2677 #define CAN_FS1R_FSC26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2678 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2679 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
sahilmgandhi 18:6a4db94011d3 2680 #define CAN_FS1R_FSC27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 2681 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2682 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
sahilmgandhi 18:6a4db94011d3 2683
sahilmgandhi 18:6a4db94011d3 2684 /****************** Bit definition for CAN_FFA1R register *******************/
sahilmgandhi 18:6a4db94011d3 2685 #define CAN_FFA1R_FFA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2686 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
sahilmgandhi 18:6a4db94011d3 2687 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
sahilmgandhi 18:6a4db94011d3 2688 #define CAN_FFA1R_FFA0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2689 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2690 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
sahilmgandhi 18:6a4db94011d3 2691 #define CAN_FFA1R_FFA1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2692 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2693 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
sahilmgandhi 18:6a4db94011d3 2694 #define CAN_FFA1R_FFA2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2695 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2696 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
sahilmgandhi 18:6a4db94011d3 2697 #define CAN_FFA1R_FFA3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2698 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2699 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
sahilmgandhi 18:6a4db94011d3 2700 #define CAN_FFA1R_FFA4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2701 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2702 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
sahilmgandhi 18:6a4db94011d3 2703 #define CAN_FFA1R_FFA5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2704 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2705 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
sahilmgandhi 18:6a4db94011d3 2706 #define CAN_FFA1R_FFA6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2707 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2708 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
sahilmgandhi 18:6a4db94011d3 2709 #define CAN_FFA1R_FFA7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2710 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2711 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
sahilmgandhi 18:6a4db94011d3 2712 #define CAN_FFA1R_FFA8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2713 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2714 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
sahilmgandhi 18:6a4db94011d3 2715 #define CAN_FFA1R_FFA9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2716 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2717 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
sahilmgandhi 18:6a4db94011d3 2718 #define CAN_FFA1R_FFA10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2719 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2720 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
sahilmgandhi 18:6a4db94011d3 2721 #define CAN_FFA1R_FFA11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2722 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2723 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
sahilmgandhi 18:6a4db94011d3 2724 #define CAN_FFA1R_FFA12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2725 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2726 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
sahilmgandhi 18:6a4db94011d3 2727 #define CAN_FFA1R_FFA13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2728 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2729 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
sahilmgandhi 18:6a4db94011d3 2730 #define CAN_FFA1R_FFA14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2731 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2732 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
sahilmgandhi 18:6a4db94011d3 2733 #define CAN_FFA1R_FFA15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2734 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2735 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
sahilmgandhi 18:6a4db94011d3 2736 #define CAN_FFA1R_FFA16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2737 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2738 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
sahilmgandhi 18:6a4db94011d3 2739 #define CAN_FFA1R_FFA17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2740 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2741 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
sahilmgandhi 18:6a4db94011d3 2742 #define CAN_FFA1R_FFA18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2743 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2744 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
sahilmgandhi 18:6a4db94011d3 2745 #define CAN_FFA1R_FFA19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2746 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2747 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
sahilmgandhi 18:6a4db94011d3 2748 #define CAN_FFA1R_FFA20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2749 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2750 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
sahilmgandhi 18:6a4db94011d3 2751 #define CAN_FFA1R_FFA21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2752 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2753 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
sahilmgandhi 18:6a4db94011d3 2754 #define CAN_FFA1R_FFA22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2755 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2756 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
sahilmgandhi 18:6a4db94011d3 2757 #define CAN_FFA1R_FFA23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2758 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2759 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
sahilmgandhi 18:6a4db94011d3 2760 #define CAN_FFA1R_FFA24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2761 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2762 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
sahilmgandhi 18:6a4db94011d3 2763 #define CAN_FFA1R_FFA25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 2764 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2765 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
sahilmgandhi 18:6a4db94011d3 2766 #define CAN_FFA1R_FFA26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2767 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2768 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
sahilmgandhi 18:6a4db94011d3 2769 #define CAN_FFA1R_FFA27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 2770 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2771 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
sahilmgandhi 18:6a4db94011d3 2772
sahilmgandhi 18:6a4db94011d3 2773 /******************* Bit definition for CAN_FA1R register *******************/
sahilmgandhi 18:6a4db94011d3 2774 #define CAN_FA1R_FACT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2775 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
sahilmgandhi 18:6a4db94011d3 2776 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
sahilmgandhi 18:6a4db94011d3 2777 #define CAN_FA1R_FACT0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2778 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2779 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
sahilmgandhi 18:6a4db94011d3 2780 #define CAN_FA1R_FACT1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2781 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2782 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
sahilmgandhi 18:6a4db94011d3 2783 #define CAN_FA1R_FACT2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2784 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2785 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
sahilmgandhi 18:6a4db94011d3 2786 #define CAN_FA1R_FACT3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2787 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2788 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
sahilmgandhi 18:6a4db94011d3 2789 #define CAN_FA1R_FACT4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2790 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2791 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
sahilmgandhi 18:6a4db94011d3 2792 #define CAN_FA1R_FACT5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2793 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2794 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
sahilmgandhi 18:6a4db94011d3 2795 #define CAN_FA1R_FACT6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2796 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2797 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
sahilmgandhi 18:6a4db94011d3 2798 #define CAN_FA1R_FACT7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2799 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2800 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
sahilmgandhi 18:6a4db94011d3 2801 #define CAN_FA1R_FACT8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2802 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2803 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
sahilmgandhi 18:6a4db94011d3 2804 #define CAN_FA1R_FACT9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2805 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2806 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
sahilmgandhi 18:6a4db94011d3 2807 #define CAN_FA1R_FACT10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2808 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2809 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
sahilmgandhi 18:6a4db94011d3 2810 #define CAN_FA1R_FACT11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2811 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2812 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
sahilmgandhi 18:6a4db94011d3 2813 #define CAN_FA1R_FACT12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2814 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2815 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
sahilmgandhi 18:6a4db94011d3 2816 #define CAN_FA1R_FACT13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2817 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2818 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
sahilmgandhi 18:6a4db94011d3 2819 #define CAN_FA1R_FACT14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2820 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2821 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
sahilmgandhi 18:6a4db94011d3 2822 #define CAN_FA1R_FACT15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2823 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2824 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
sahilmgandhi 18:6a4db94011d3 2825 #define CAN_FA1R_FACT16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2826 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2827 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
sahilmgandhi 18:6a4db94011d3 2828 #define CAN_FA1R_FACT17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2829 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2830 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
sahilmgandhi 18:6a4db94011d3 2831 #define CAN_FA1R_FACT18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2832 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2833 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
sahilmgandhi 18:6a4db94011d3 2834 #define CAN_FA1R_FACT19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2835 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2836 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
sahilmgandhi 18:6a4db94011d3 2837 #define CAN_FA1R_FACT20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2838 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2839 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
sahilmgandhi 18:6a4db94011d3 2840 #define CAN_FA1R_FACT21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2841 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2842 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
sahilmgandhi 18:6a4db94011d3 2843 #define CAN_FA1R_FACT22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2844 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2845 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
sahilmgandhi 18:6a4db94011d3 2846 #define CAN_FA1R_FACT23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2847 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2848 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
sahilmgandhi 18:6a4db94011d3 2849 #define CAN_FA1R_FACT24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2850 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2851 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
sahilmgandhi 18:6a4db94011d3 2852 #define CAN_FA1R_FACT25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 2853 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2854 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
sahilmgandhi 18:6a4db94011d3 2855 #define CAN_FA1R_FACT26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2856 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2857 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
sahilmgandhi 18:6a4db94011d3 2858 #define CAN_FA1R_FACT27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 2859 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2860 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
sahilmgandhi 18:6a4db94011d3 2861
sahilmgandhi 18:6a4db94011d3 2862
sahilmgandhi 18:6a4db94011d3 2863 /******************* Bit definition for CAN_F0R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2864 #define CAN_F0R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2865 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2866 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2867 #define CAN_F0R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2868 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2869 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2870 #define CAN_F0R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2871 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2872 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2873 #define CAN_F0R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2874 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2875 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2876 #define CAN_F0R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2877 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2878 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2879 #define CAN_F0R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2880 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2881 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2882 #define CAN_F0R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2883 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2884 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2885 #define CAN_F0R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2886 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2887 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2888 #define CAN_F0R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2889 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2890 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2891 #define CAN_F0R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2892 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2893 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2894 #define CAN_F0R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2895 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2896 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2897 #define CAN_F0R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2898 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2899 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2900 #define CAN_F0R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2901 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 2902 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 2903 #define CAN_F0R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 2904 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 2905 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 2906 #define CAN_F0R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 2907 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 2908 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 2909 #define CAN_F0R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 2910 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 2911 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 2912 #define CAN_F0R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 2913 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 2914 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 2915 #define CAN_F0R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 2916 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 2917 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 2918 #define CAN_F0R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 2919 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 2920 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 2921 #define CAN_F0R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 2922 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 2923 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 2924 #define CAN_F0R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 2925 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 2926 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 2927 #define CAN_F0R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 2928 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 2929 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 2930 #define CAN_F0R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 2931 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 2932 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 2933 #define CAN_F0R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 2934 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 2935 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 2936 #define CAN_F0R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 2937 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 2938 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 2939 #define CAN_F0R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 2940 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 2941 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 2942 #define CAN_F0R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 2943 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 2944 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 2945 #define CAN_F0R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 2946 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 2947 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 2948 #define CAN_F0R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 2949 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 2950 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 2951 #define CAN_F0R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 2952 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 2953 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 2954 #define CAN_F0R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 2955 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 2956 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 2957 #define CAN_F0R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 2958 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 2959 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 2960
sahilmgandhi 18:6a4db94011d3 2961 /******************* Bit definition for CAN_F1R1 register *******************/
sahilmgandhi 18:6a4db94011d3 2962 #define CAN_F1R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 2963 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 2964 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 2965 #define CAN_F1R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 2966 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 2967 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 2968 #define CAN_F1R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 2969 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 2970 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 2971 #define CAN_F1R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 2972 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 2973 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 2974 #define CAN_F1R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 2975 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 2976 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 2977 #define CAN_F1R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 2978 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 2979 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 2980 #define CAN_F1R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 2981 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 2982 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 2983 #define CAN_F1R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 2984 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 2985 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 2986 #define CAN_F1R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 2987 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 2988 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 2989 #define CAN_F1R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 2990 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 2991 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 2992 #define CAN_F1R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 2993 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 2994 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 2995 #define CAN_F1R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 2996 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 2997 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 2998 #define CAN_F1R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 2999 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3000 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3001 #define CAN_F1R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3002 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3003 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3004 #define CAN_F1R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3005 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3006 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3007 #define CAN_F1R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3008 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3009 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3010 #define CAN_F1R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3011 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3012 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3013 #define CAN_F1R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3014 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3015 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3016 #define CAN_F1R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3017 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3018 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3019 #define CAN_F1R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3020 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3021 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3022 #define CAN_F1R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3023 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3024 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3025 #define CAN_F1R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3026 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3027 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3028 #define CAN_F1R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3029 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3030 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3031 #define CAN_F1R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3032 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3033 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3034 #define CAN_F1R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3035 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3036 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3037 #define CAN_F1R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3038 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3039 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3040 #define CAN_F1R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3041 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3042 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3043 #define CAN_F1R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3044 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3045 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3046 #define CAN_F1R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3047 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3048 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3049 #define CAN_F1R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3050 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3051 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3052 #define CAN_F1R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3053 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3054 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3055 #define CAN_F1R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3056 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3057 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3058
sahilmgandhi 18:6a4db94011d3 3059 /******************* Bit definition for CAN_F2R1 register *******************/
sahilmgandhi 18:6a4db94011d3 3060 #define CAN_F2R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3061 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3062 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3063 #define CAN_F2R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3064 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3065 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3066 #define CAN_F2R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3067 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3068 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3069 #define CAN_F2R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3070 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3071 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3072 #define CAN_F2R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3073 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3074 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3075 #define CAN_F2R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3076 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3077 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3078 #define CAN_F2R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3079 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3080 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3081 #define CAN_F2R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3082 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3083 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3084 #define CAN_F2R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3085 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3086 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3087 #define CAN_F2R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3088 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3089 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3090 #define CAN_F2R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3091 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3092 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3093 #define CAN_F2R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3094 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3095 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3096 #define CAN_F2R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3097 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3098 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3099 #define CAN_F2R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3100 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3101 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3102 #define CAN_F2R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3103 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3104 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3105 #define CAN_F2R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3106 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3107 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3108 #define CAN_F2R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3109 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3110 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3111 #define CAN_F2R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3112 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3113 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3114 #define CAN_F2R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3115 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3116 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3117 #define CAN_F2R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3118 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3119 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3120 #define CAN_F2R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3121 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3122 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3123 #define CAN_F2R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3124 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3125 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3126 #define CAN_F2R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3127 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3128 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3129 #define CAN_F2R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3130 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3131 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3132 #define CAN_F2R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3133 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3134 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3135 #define CAN_F2R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3136 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3137 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3138 #define CAN_F2R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3139 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3140 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3141 #define CAN_F2R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3142 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3143 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3144 #define CAN_F2R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3145 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3146 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3147 #define CAN_F2R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3148 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3149 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3150 #define CAN_F2R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3151 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3152 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3153 #define CAN_F2R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3154 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3155 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3156
sahilmgandhi 18:6a4db94011d3 3157 /******************* Bit definition for CAN_F3R1 register *******************/
sahilmgandhi 18:6a4db94011d3 3158 #define CAN_F3R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3159 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3160 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3161 #define CAN_F3R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3162 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3163 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3164 #define CAN_F3R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3165 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3166 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3167 #define CAN_F3R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3168 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3169 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3170 #define CAN_F3R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3171 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3172 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3173 #define CAN_F3R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3174 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3175 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3176 #define CAN_F3R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3177 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3178 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3179 #define CAN_F3R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3180 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3181 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3182 #define CAN_F3R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3183 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3184 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3185 #define CAN_F3R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3186 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3187 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3188 #define CAN_F3R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3189 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3190 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3191 #define CAN_F3R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3192 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3193 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3194 #define CAN_F3R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3195 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3196 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3197 #define CAN_F3R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3198 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3199 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3200 #define CAN_F3R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3201 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3202 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3203 #define CAN_F3R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3204 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3205 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3206 #define CAN_F3R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3207 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3208 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3209 #define CAN_F3R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3210 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3211 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3212 #define CAN_F3R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3213 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3214 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3215 #define CAN_F3R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3216 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3217 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3218 #define CAN_F3R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3219 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3220 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3221 #define CAN_F3R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3222 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3223 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3224 #define CAN_F3R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3225 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3226 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3227 #define CAN_F3R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3228 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3229 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3230 #define CAN_F3R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3231 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3232 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3233 #define CAN_F3R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3234 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3235 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3236 #define CAN_F3R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3237 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3238 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3239 #define CAN_F3R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3240 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3241 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3242 #define CAN_F3R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3243 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3244 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3245 #define CAN_F3R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3246 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3247 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3248 #define CAN_F3R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3249 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3250 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3251 #define CAN_F3R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3252 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3253 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3254
sahilmgandhi 18:6a4db94011d3 3255 /******************* Bit definition for CAN_F4R1 register *******************/
sahilmgandhi 18:6a4db94011d3 3256 #define CAN_F4R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3257 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3258 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3259 #define CAN_F4R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3260 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3261 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3262 #define CAN_F4R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3263 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3264 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3265 #define CAN_F4R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3266 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3267 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3268 #define CAN_F4R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3269 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3270 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3271 #define CAN_F4R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3272 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3273 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3274 #define CAN_F4R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3275 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3276 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3277 #define CAN_F4R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3278 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3279 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3280 #define CAN_F4R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3281 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3282 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3283 #define CAN_F4R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3284 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3285 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3286 #define CAN_F4R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3287 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3288 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3289 #define CAN_F4R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3290 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3291 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3292 #define CAN_F4R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3293 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3294 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3295 #define CAN_F4R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3296 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3297 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3298 #define CAN_F4R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3299 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3300 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3301 #define CAN_F4R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3302 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3303 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3304 #define CAN_F4R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3305 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3306 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3307 #define CAN_F4R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3308 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3309 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3310 #define CAN_F4R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3311 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3312 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3313 #define CAN_F4R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3314 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3315 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3316 #define CAN_F4R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3317 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3318 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3319 #define CAN_F4R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3320 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3321 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3322 #define CAN_F4R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3323 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3324 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3325 #define CAN_F4R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3326 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3327 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3328 #define CAN_F4R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3329 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3330 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3331 #define CAN_F4R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3332 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3333 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3334 #define CAN_F4R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3335 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3336 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3337 #define CAN_F4R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3338 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3339 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3340 #define CAN_F4R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3341 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3342 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3343 #define CAN_F4R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3344 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3345 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3346 #define CAN_F4R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3347 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3348 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3349 #define CAN_F4R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3350 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3351 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3352
sahilmgandhi 18:6a4db94011d3 3353 /******************* Bit definition for CAN_F5R1 register *******************/
sahilmgandhi 18:6a4db94011d3 3354 #define CAN_F5R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3355 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3356 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3357 #define CAN_F5R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3358 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3359 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3360 #define CAN_F5R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3361 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3362 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3363 #define CAN_F5R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3364 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3365 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3366 #define CAN_F5R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3367 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3368 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3369 #define CAN_F5R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3370 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3371 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3372 #define CAN_F5R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3373 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3374 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3375 #define CAN_F5R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3376 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3377 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3378 #define CAN_F5R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3379 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3380 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3381 #define CAN_F5R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3382 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3383 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3384 #define CAN_F5R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3385 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3386 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3387 #define CAN_F5R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3388 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3389 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3390 #define CAN_F5R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3391 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3392 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3393 #define CAN_F5R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3394 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3395 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3396 #define CAN_F5R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3397 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3398 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3399 #define CAN_F5R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3400 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3401 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3402 #define CAN_F5R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3403 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3404 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3405 #define CAN_F5R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3406 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3407 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3408 #define CAN_F5R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3409 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3410 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3411 #define CAN_F5R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3412 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3413 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3414 #define CAN_F5R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3415 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3416 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3417 #define CAN_F5R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3418 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3419 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3420 #define CAN_F5R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3421 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3422 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3423 #define CAN_F5R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3424 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3425 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3426 #define CAN_F5R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3427 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3428 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3429 #define CAN_F5R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3430 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3431 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3432 #define CAN_F5R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3433 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3434 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3435 #define CAN_F5R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3436 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3437 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3438 #define CAN_F5R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3439 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3440 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3441 #define CAN_F5R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3442 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3443 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3444 #define CAN_F5R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3445 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3446 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3447 #define CAN_F5R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3448 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3449 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3450
sahilmgandhi 18:6a4db94011d3 3451 /******************* Bit definition for CAN_F6R1 register *******************/
sahilmgandhi 18:6a4db94011d3 3452 #define CAN_F6R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3453 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3454 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3455 #define CAN_F6R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3456 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3457 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3458 #define CAN_F6R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3459 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3460 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3461 #define CAN_F6R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3462 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3463 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3464 #define CAN_F6R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3465 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3466 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3467 #define CAN_F6R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3468 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3469 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3470 #define CAN_F6R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3471 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3472 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3473 #define CAN_F6R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3474 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3475 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3476 #define CAN_F6R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3477 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3478 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3479 #define CAN_F6R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3480 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3481 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3482 #define CAN_F6R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3483 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3484 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3485 #define CAN_F6R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3486 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3487 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3488 #define CAN_F6R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3489 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3490 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3491 #define CAN_F6R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3492 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3493 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3494 #define CAN_F6R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3495 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3496 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3497 #define CAN_F6R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3498 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3499 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3500 #define CAN_F6R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3501 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3502 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3503 #define CAN_F6R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3504 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3505 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3506 #define CAN_F6R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3507 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3508 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3509 #define CAN_F6R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3510 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3511 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3512 #define CAN_F6R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3513 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3514 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3515 #define CAN_F6R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3516 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3517 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3518 #define CAN_F6R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3519 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3520 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3521 #define CAN_F6R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3522 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3523 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3524 #define CAN_F6R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3525 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3526 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3527 #define CAN_F6R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3528 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3529 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3530 #define CAN_F6R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3531 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3532 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3533 #define CAN_F6R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3534 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3535 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3536 #define CAN_F6R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3537 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3538 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3539 #define CAN_F6R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3540 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3541 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3542 #define CAN_F6R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3543 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3544 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3545 #define CAN_F6R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3546 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3547 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3548
sahilmgandhi 18:6a4db94011d3 3549 /******************* Bit definition for CAN_F7R1 register *******************/
sahilmgandhi 18:6a4db94011d3 3550 #define CAN_F7R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3551 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3552 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3553 #define CAN_F7R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3554 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3555 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3556 #define CAN_F7R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3557 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3558 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3559 #define CAN_F7R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3560 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3561 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3562 #define CAN_F7R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3563 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3564 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3565 #define CAN_F7R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3566 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3567 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3568 #define CAN_F7R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3569 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3570 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3571 #define CAN_F7R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3572 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3573 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3574 #define CAN_F7R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3575 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3576 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3577 #define CAN_F7R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3578 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3579 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3580 #define CAN_F7R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3581 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3582 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3583 #define CAN_F7R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3584 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3585 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3586 #define CAN_F7R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3587 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3588 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3589 #define CAN_F7R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3590 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3591 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3592 #define CAN_F7R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3593 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3594 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3595 #define CAN_F7R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3596 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3597 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3598 #define CAN_F7R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3599 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3600 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3601 #define CAN_F7R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3602 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3603 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3604 #define CAN_F7R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3605 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3606 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3607 #define CAN_F7R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3608 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3609 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3610 #define CAN_F7R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3611 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3612 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3613 #define CAN_F7R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3614 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3615 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3616 #define CAN_F7R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3617 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3618 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3619 #define CAN_F7R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3620 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3621 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3622 #define CAN_F7R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3623 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3624 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3625 #define CAN_F7R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3626 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3627 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3628 #define CAN_F7R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3629 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3630 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3631 #define CAN_F7R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3632 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3633 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3634 #define CAN_F7R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3635 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3636 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3637 #define CAN_F7R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3638 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3639 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3640 #define CAN_F7R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3641 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3642 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3643 #define CAN_F7R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3644 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3645 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3646
sahilmgandhi 18:6a4db94011d3 3647 /******************* Bit definition for CAN_F8R1 register *******************/
sahilmgandhi 18:6a4db94011d3 3648 #define CAN_F8R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3649 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3650 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3651 #define CAN_F8R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3652 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3653 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3654 #define CAN_F8R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3655 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3656 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3657 #define CAN_F8R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3658 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3659 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3660 #define CAN_F8R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3661 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3662 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3663 #define CAN_F8R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3664 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3665 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3666 #define CAN_F8R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3667 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3668 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3669 #define CAN_F8R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3670 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3671 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3672 #define CAN_F8R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3673 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3674 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3675 #define CAN_F8R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3676 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3677 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3678 #define CAN_F8R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3679 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3680 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3681 #define CAN_F8R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3682 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3683 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3684 #define CAN_F8R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3685 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3686 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3687 #define CAN_F8R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3688 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3689 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3690 #define CAN_F8R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3691 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3692 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3693 #define CAN_F8R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3694 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3695 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3696 #define CAN_F8R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3697 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3698 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3699 #define CAN_F8R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3700 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3701 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3702 #define CAN_F8R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3703 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3704 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3705 #define CAN_F8R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3706 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3707 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3708 #define CAN_F8R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3709 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3710 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3711 #define CAN_F8R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3712 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3713 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3714 #define CAN_F8R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3715 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3716 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3717 #define CAN_F8R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3718 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3719 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3720 #define CAN_F8R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3721 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3722 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3723 #define CAN_F8R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3724 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3725 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3726 #define CAN_F8R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3727 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3728 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3729 #define CAN_F8R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3730 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3731 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3732 #define CAN_F8R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3733 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3734 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3735 #define CAN_F8R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3736 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3737 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3738 #define CAN_F8R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3739 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3740 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3741 #define CAN_F8R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3742 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3743 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3744
sahilmgandhi 18:6a4db94011d3 3745 /******************* Bit definition for CAN_F9R1 register *******************/
sahilmgandhi 18:6a4db94011d3 3746 #define CAN_F9R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3747 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3748 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3749 #define CAN_F9R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3750 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3751 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3752 #define CAN_F9R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3753 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3754 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3755 #define CAN_F9R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3756 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3757 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3758 #define CAN_F9R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3759 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3760 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3761 #define CAN_F9R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3762 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3763 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3764 #define CAN_F9R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3765 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3766 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3767 #define CAN_F9R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3768 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3769 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3770 #define CAN_F9R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3771 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3772 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3773 #define CAN_F9R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3774 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3775 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3776 #define CAN_F9R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3777 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3778 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3779 #define CAN_F9R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3780 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3781 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3782 #define CAN_F9R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3783 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3784 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3785 #define CAN_F9R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3786 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3787 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3788 #define CAN_F9R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3789 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3790 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3791 #define CAN_F9R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3792 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3793 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3794 #define CAN_F9R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3795 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3796 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3797 #define CAN_F9R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3798 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3799 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3800 #define CAN_F9R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3801 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3802 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3803 #define CAN_F9R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3804 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3805 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3806 #define CAN_F9R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3807 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3808 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3809 #define CAN_F9R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3810 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3811 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3812 #define CAN_F9R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3813 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3814 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3815 #define CAN_F9R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3816 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3817 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3818 #define CAN_F9R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3819 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3820 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3821 #define CAN_F9R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3822 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3823 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3824 #define CAN_F9R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3825 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3826 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3827 #define CAN_F9R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3828 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3829 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3830 #define CAN_F9R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3831 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3832 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3833 #define CAN_F9R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3834 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3835 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3836 #define CAN_F9R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3837 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3838 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3839 #define CAN_F9R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3840 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3841 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3842
sahilmgandhi 18:6a4db94011d3 3843 /******************* Bit definition for CAN_F10R1 register ******************/
sahilmgandhi 18:6a4db94011d3 3844 #define CAN_F10R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3845 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3846 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3847 #define CAN_F10R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3848 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3849 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3850 #define CAN_F10R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3851 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3852 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3853 #define CAN_F10R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3854 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3855 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3856 #define CAN_F10R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3857 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3858 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3859 #define CAN_F10R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3860 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3861 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3862 #define CAN_F10R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3863 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3864 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3865 #define CAN_F10R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3866 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3867 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3868 #define CAN_F10R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3869 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3870 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3871 #define CAN_F10R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3872 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3873 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3874 #define CAN_F10R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3875 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3876 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3877 #define CAN_F10R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3878 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3879 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3880 #define CAN_F10R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3881 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3882 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3883 #define CAN_F10R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3884 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3885 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3886 #define CAN_F10R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3887 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3888 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3889 #define CAN_F10R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3890 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3891 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3892 #define CAN_F10R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3893 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3894 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3895 #define CAN_F10R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3896 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3897 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3898 #define CAN_F10R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3899 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3900 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3901 #define CAN_F10R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 3902 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 3903 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 3904 #define CAN_F10R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 3905 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 3906 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 3907 #define CAN_F10R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 3908 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 3909 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 3910 #define CAN_F10R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 3911 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 3912 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 3913 #define CAN_F10R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 3914 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 3915 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 3916 #define CAN_F10R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 3917 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 3918 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 3919 #define CAN_F10R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 3920 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 3921 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 3922 #define CAN_F10R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 3923 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 3924 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 3925 #define CAN_F10R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 3926 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 3927 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 3928 #define CAN_F10R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 3929 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 3930 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 3931 #define CAN_F10R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 3932 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 3933 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 3934 #define CAN_F10R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 3935 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 3936 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 3937 #define CAN_F10R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 3938 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 3939 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 3940
sahilmgandhi 18:6a4db94011d3 3941 /******************* Bit definition for CAN_F11R1 register ******************/
sahilmgandhi 18:6a4db94011d3 3942 #define CAN_F11R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 3943 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 3944 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 3945 #define CAN_F11R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 3946 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 3947 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 3948 #define CAN_F11R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 3949 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 3950 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 3951 #define CAN_F11R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 3952 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 3953 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 3954 #define CAN_F11R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 3955 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 3956 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 3957 #define CAN_F11R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 3958 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 3959 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 3960 #define CAN_F11R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 3961 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 3962 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 3963 #define CAN_F11R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 3964 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 3965 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 3966 #define CAN_F11R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 3967 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 3968 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 3969 #define CAN_F11R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 3970 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 3971 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 3972 #define CAN_F11R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 3973 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 3974 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 3975 #define CAN_F11R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 3976 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 3977 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 3978 #define CAN_F11R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 3979 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 3980 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 3981 #define CAN_F11R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 3982 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 3983 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 3984 #define CAN_F11R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 3985 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 3986 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 3987 #define CAN_F11R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 3988 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 3989 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 3990 #define CAN_F11R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 3991 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 3992 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 3993 #define CAN_F11R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 3994 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 3995 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 3996 #define CAN_F11R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 3997 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 3998 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 3999 #define CAN_F11R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4000 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4001 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4002 #define CAN_F11R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4003 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4004 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4005 #define CAN_F11R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4006 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4007 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4008 #define CAN_F11R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4009 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4010 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4011 #define CAN_F11R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4012 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4013 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4014 #define CAN_F11R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4015 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4016 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4017 #define CAN_F11R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4018 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4019 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4020 #define CAN_F11R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4021 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4022 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4023 #define CAN_F11R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4024 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4025 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4026 #define CAN_F11R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4027 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4028 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4029 #define CAN_F11R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4030 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4031 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4032 #define CAN_F11R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4033 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4034 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4035 #define CAN_F11R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4036 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4037 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4038
sahilmgandhi 18:6a4db94011d3 4039 /******************* Bit definition for CAN_F12R1 register ******************/
sahilmgandhi 18:6a4db94011d3 4040 #define CAN_F12R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4041 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4042 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4043 #define CAN_F12R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4044 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4045 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4046 #define CAN_F12R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4047 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4048 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4049 #define CAN_F12R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4050 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4051 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4052 #define CAN_F12R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4053 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4054 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4055 #define CAN_F12R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4056 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4057 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4058 #define CAN_F12R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4059 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4060 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4061 #define CAN_F12R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4062 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4063 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4064 #define CAN_F12R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4065 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4066 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4067 #define CAN_F12R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4068 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4069 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4070 #define CAN_F12R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4071 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4072 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4073 #define CAN_F12R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4074 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4075 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4076 #define CAN_F12R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4077 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4078 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4079 #define CAN_F12R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4080 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4081 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4082 #define CAN_F12R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4083 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4084 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4085 #define CAN_F12R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4086 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4087 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4088 #define CAN_F12R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4089 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4090 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4091 #define CAN_F12R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4092 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4093 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4094 #define CAN_F12R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4095 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4096 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4097 #define CAN_F12R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4098 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4099 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4100 #define CAN_F12R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4101 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4102 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4103 #define CAN_F12R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4104 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4105 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4106 #define CAN_F12R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4107 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4108 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4109 #define CAN_F12R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4110 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4111 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4112 #define CAN_F12R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4113 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4114 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4115 #define CAN_F12R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4116 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4117 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4118 #define CAN_F12R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4119 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4120 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4121 #define CAN_F12R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4122 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4123 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4124 #define CAN_F12R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4125 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4126 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4127 #define CAN_F12R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4128 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4129 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4130 #define CAN_F12R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4131 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4132 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4133 #define CAN_F12R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4134 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4135 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4136
sahilmgandhi 18:6a4db94011d3 4137 /******************* Bit definition for CAN_F13R1 register ******************/
sahilmgandhi 18:6a4db94011d3 4138 #define CAN_F13R1_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4139 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4140 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4141 #define CAN_F13R1_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4142 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4143 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4144 #define CAN_F13R1_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4145 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4146 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4147 #define CAN_F13R1_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4148 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4149 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4150 #define CAN_F13R1_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4151 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4152 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4153 #define CAN_F13R1_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4154 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4155 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4156 #define CAN_F13R1_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4157 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4158 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4159 #define CAN_F13R1_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4160 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4161 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4162 #define CAN_F13R1_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4163 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4164 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4165 #define CAN_F13R1_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4166 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4167 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4168 #define CAN_F13R1_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4169 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4170 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4171 #define CAN_F13R1_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4172 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4173 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4174 #define CAN_F13R1_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4175 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4176 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4177 #define CAN_F13R1_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4178 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4179 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4180 #define CAN_F13R1_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4181 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4182 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4183 #define CAN_F13R1_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4184 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4185 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4186 #define CAN_F13R1_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4187 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4188 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4189 #define CAN_F13R1_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4190 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4191 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4192 #define CAN_F13R1_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4193 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4194 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4195 #define CAN_F13R1_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4196 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4197 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4198 #define CAN_F13R1_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4199 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4200 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4201 #define CAN_F13R1_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4202 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4203 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4204 #define CAN_F13R1_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4205 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4206 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4207 #define CAN_F13R1_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4208 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4209 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4210 #define CAN_F13R1_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4211 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4212 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4213 #define CAN_F13R1_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4214 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4215 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4216 #define CAN_F13R1_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4217 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4218 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4219 #define CAN_F13R1_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4220 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4221 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4222 #define CAN_F13R1_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4223 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4224 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4225 #define CAN_F13R1_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4226 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4227 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4228 #define CAN_F13R1_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4229 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4230 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4231 #define CAN_F13R1_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4232 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4233 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4234
sahilmgandhi 18:6a4db94011d3 4235 /******************* Bit definition for CAN_F0R2 register *******************/
sahilmgandhi 18:6a4db94011d3 4236 #define CAN_F0R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4237 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4238 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4239 #define CAN_F0R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4240 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4241 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4242 #define CAN_F0R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4243 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4244 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4245 #define CAN_F0R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4246 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4247 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4248 #define CAN_F0R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4249 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4250 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4251 #define CAN_F0R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4252 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4253 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4254 #define CAN_F0R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4255 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4256 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4257 #define CAN_F0R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4258 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4259 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4260 #define CAN_F0R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4261 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4262 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4263 #define CAN_F0R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4264 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4265 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4266 #define CAN_F0R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4267 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4268 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4269 #define CAN_F0R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4270 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4271 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4272 #define CAN_F0R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4273 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4274 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4275 #define CAN_F0R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4276 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4277 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4278 #define CAN_F0R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4279 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4280 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4281 #define CAN_F0R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4282 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4283 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4284 #define CAN_F0R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4285 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4286 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4287 #define CAN_F0R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4288 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4289 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4290 #define CAN_F0R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4291 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4292 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4293 #define CAN_F0R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4294 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4295 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4296 #define CAN_F0R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4297 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4298 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4299 #define CAN_F0R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4300 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4301 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4302 #define CAN_F0R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4303 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4304 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4305 #define CAN_F0R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4306 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4307 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4308 #define CAN_F0R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4309 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4310 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4311 #define CAN_F0R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4312 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4313 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4314 #define CAN_F0R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4315 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4316 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4317 #define CAN_F0R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4318 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4319 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4320 #define CAN_F0R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4321 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4322 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4323 #define CAN_F0R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4324 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4325 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4326 #define CAN_F0R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4327 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4328 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4329 #define CAN_F0R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4330 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4331 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4332
sahilmgandhi 18:6a4db94011d3 4333 /******************* Bit definition for CAN_F1R2 register *******************/
sahilmgandhi 18:6a4db94011d3 4334 #define CAN_F1R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4335 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4336 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4337 #define CAN_F1R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4338 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4339 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4340 #define CAN_F1R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4341 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4342 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4343 #define CAN_F1R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4344 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4345 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4346 #define CAN_F1R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4347 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4348 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4349 #define CAN_F1R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4350 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4351 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4352 #define CAN_F1R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4353 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4354 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4355 #define CAN_F1R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4356 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4357 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4358 #define CAN_F1R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4359 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4360 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4361 #define CAN_F1R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4362 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4363 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4364 #define CAN_F1R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4365 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4366 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4367 #define CAN_F1R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4368 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4369 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4370 #define CAN_F1R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4371 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4372 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4373 #define CAN_F1R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4374 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4375 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4376 #define CAN_F1R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4377 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4378 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4379 #define CAN_F1R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4380 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4381 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4382 #define CAN_F1R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4383 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4384 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4385 #define CAN_F1R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4386 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4387 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4388 #define CAN_F1R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4389 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4390 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4391 #define CAN_F1R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4392 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4393 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4394 #define CAN_F1R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4395 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4396 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4397 #define CAN_F1R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4398 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4399 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4400 #define CAN_F1R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4401 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4402 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4403 #define CAN_F1R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4404 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4405 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4406 #define CAN_F1R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4407 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4408 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4409 #define CAN_F1R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4410 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4411 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4412 #define CAN_F1R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4413 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4414 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4415 #define CAN_F1R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4416 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4417 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4418 #define CAN_F1R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4419 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4420 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4421 #define CAN_F1R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4422 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4423 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4424 #define CAN_F1R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4425 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4426 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4427 #define CAN_F1R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4428 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4429 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4430
sahilmgandhi 18:6a4db94011d3 4431 /******************* Bit definition for CAN_F2R2 register *******************/
sahilmgandhi 18:6a4db94011d3 4432 #define CAN_F2R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4433 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4434 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4435 #define CAN_F2R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4436 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4437 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4438 #define CAN_F2R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4439 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4440 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4441 #define CAN_F2R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4442 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4443 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4444 #define CAN_F2R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4445 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4446 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4447 #define CAN_F2R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4448 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4449 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4450 #define CAN_F2R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4451 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4452 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4453 #define CAN_F2R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4454 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4455 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4456 #define CAN_F2R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4457 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4458 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4459 #define CAN_F2R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4460 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4461 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4462 #define CAN_F2R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4463 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4464 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4465 #define CAN_F2R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4466 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4467 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4468 #define CAN_F2R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4469 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4470 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4471 #define CAN_F2R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4472 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4473 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4474 #define CAN_F2R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4475 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4476 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4477 #define CAN_F2R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4478 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4479 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4480 #define CAN_F2R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4481 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4482 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4483 #define CAN_F2R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4484 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4485 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4486 #define CAN_F2R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4487 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4488 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4489 #define CAN_F2R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4490 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4491 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4492 #define CAN_F2R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4493 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4494 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4495 #define CAN_F2R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4496 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4497 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4498 #define CAN_F2R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4499 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4500 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4501 #define CAN_F2R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4502 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4503 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4504 #define CAN_F2R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4505 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4506 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4507 #define CAN_F2R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4508 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4509 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4510 #define CAN_F2R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4511 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4512 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4513 #define CAN_F2R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4514 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4515 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4516 #define CAN_F2R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4517 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4518 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4519 #define CAN_F2R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4520 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4521 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4522 #define CAN_F2R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4523 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4524 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4525 #define CAN_F2R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4526 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4527 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4528
sahilmgandhi 18:6a4db94011d3 4529 /******************* Bit definition for CAN_F3R2 register *******************/
sahilmgandhi 18:6a4db94011d3 4530 #define CAN_F3R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4531 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4532 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4533 #define CAN_F3R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4534 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4535 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4536 #define CAN_F3R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4537 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4538 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4539 #define CAN_F3R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4540 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4541 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4542 #define CAN_F3R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4543 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4544 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4545 #define CAN_F3R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4546 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4547 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4548 #define CAN_F3R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4549 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4550 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4551 #define CAN_F3R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4552 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4553 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4554 #define CAN_F3R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4555 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4556 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4557 #define CAN_F3R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4558 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4559 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4560 #define CAN_F3R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4561 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4562 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4563 #define CAN_F3R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4564 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4565 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4566 #define CAN_F3R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4567 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4568 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4569 #define CAN_F3R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4570 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4571 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4572 #define CAN_F3R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4573 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4574 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4575 #define CAN_F3R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4576 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4577 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4578 #define CAN_F3R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4579 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4580 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4581 #define CAN_F3R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4582 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4583 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4584 #define CAN_F3R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4585 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4586 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4587 #define CAN_F3R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4588 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4589 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4590 #define CAN_F3R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4591 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4592 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4593 #define CAN_F3R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4594 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4595 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4596 #define CAN_F3R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4597 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4598 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4599 #define CAN_F3R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4600 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4601 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4602 #define CAN_F3R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4603 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4604 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4605 #define CAN_F3R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4606 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4607 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4608 #define CAN_F3R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4609 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4610 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4611 #define CAN_F3R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4612 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4613 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4614 #define CAN_F3R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4615 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4616 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4617 #define CAN_F3R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4618 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4619 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4620 #define CAN_F3R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4621 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4622 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4623 #define CAN_F3R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4624 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4625 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4626
sahilmgandhi 18:6a4db94011d3 4627 /******************* Bit definition for CAN_F4R2 register *******************/
sahilmgandhi 18:6a4db94011d3 4628 #define CAN_F4R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4629 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4630 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4631 #define CAN_F4R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4632 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4633 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4634 #define CAN_F4R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4635 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4636 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4637 #define CAN_F4R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4638 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4639 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4640 #define CAN_F4R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4641 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4642 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4643 #define CAN_F4R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4644 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4645 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4646 #define CAN_F4R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4647 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4648 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4649 #define CAN_F4R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4650 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4651 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4652 #define CAN_F4R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4653 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4654 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4655 #define CAN_F4R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4656 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4657 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4658 #define CAN_F4R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4659 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4660 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4661 #define CAN_F4R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4662 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4663 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4664 #define CAN_F4R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4665 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4666 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4667 #define CAN_F4R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4668 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4669 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4670 #define CAN_F4R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4671 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4672 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4673 #define CAN_F4R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4674 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4675 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4676 #define CAN_F4R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4677 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4678 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4679 #define CAN_F4R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4680 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4681 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4682 #define CAN_F4R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4683 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4684 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4685 #define CAN_F4R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4686 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4687 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4688 #define CAN_F4R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4689 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4690 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4691 #define CAN_F4R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4692 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4693 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4694 #define CAN_F4R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4695 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4696 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4697 #define CAN_F4R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4698 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4699 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4700 #define CAN_F4R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4701 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4702 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4703 #define CAN_F4R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4704 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4705 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4706 #define CAN_F4R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4707 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4708 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4709 #define CAN_F4R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4710 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4711 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4712 #define CAN_F4R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4713 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4714 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4715 #define CAN_F4R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4716 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4717 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4718 #define CAN_F4R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4719 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4720 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4721 #define CAN_F4R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4722 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4723 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4724
sahilmgandhi 18:6a4db94011d3 4725 /******************* Bit definition for CAN_F5R2 register *******************/
sahilmgandhi 18:6a4db94011d3 4726 #define CAN_F5R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4727 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4728 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4729 #define CAN_F5R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4730 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4731 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4732 #define CAN_F5R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4733 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4734 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4735 #define CAN_F5R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4736 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4737 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4738 #define CAN_F5R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4739 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4740 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4741 #define CAN_F5R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4742 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4743 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4744 #define CAN_F5R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4745 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4746 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4747 #define CAN_F5R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4748 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4749 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4750 #define CAN_F5R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4751 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4752 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4753 #define CAN_F5R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4754 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4755 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4756 #define CAN_F5R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4757 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4758 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4759 #define CAN_F5R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4760 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4761 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4762 #define CAN_F5R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4763 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4764 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4765 #define CAN_F5R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4766 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4767 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4768 #define CAN_F5R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4769 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4770 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4771 #define CAN_F5R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4772 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4773 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4774 #define CAN_F5R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4775 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4776 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4777 #define CAN_F5R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4778 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4779 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4780 #define CAN_F5R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4781 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4782 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4783 #define CAN_F5R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4784 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4785 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4786 #define CAN_F5R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4787 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4788 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4789 #define CAN_F5R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4790 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4791 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4792 #define CAN_F5R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4793 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4794 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4795 #define CAN_F5R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4796 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4797 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4798 #define CAN_F5R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4799 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4800 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4801 #define CAN_F5R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4802 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4803 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4804 #define CAN_F5R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4805 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4806 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4807 #define CAN_F5R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4808 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4809 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4810 #define CAN_F5R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4811 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4812 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4813 #define CAN_F5R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4814 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4815 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4816 #define CAN_F5R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4817 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4818 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4819 #define CAN_F5R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4820 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4821 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4822
sahilmgandhi 18:6a4db94011d3 4823 /******************* Bit definition for CAN_F6R2 register *******************/
sahilmgandhi 18:6a4db94011d3 4824 #define CAN_F6R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4825 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4826 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4827 #define CAN_F6R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4828 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4829 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4830 #define CAN_F6R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4831 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4832 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4833 #define CAN_F6R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4834 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4835 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4836 #define CAN_F6R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4837 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4838 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4839 #define CAN_F6R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4840 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4841 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4842 #define CAN_F6R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4843 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4844 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4845 #define CAN_F6R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4846 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4847 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4848 #define CAN_F6R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4849 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4850 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4851 #define CAN_F6R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4852 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4853 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4854 #define CAN_F6R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4855 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4856 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4857 #define CAN_F6R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4858 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4859 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4860 #define CAN_F6R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4861 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4862 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4863 #define CAN_F6R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4864 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4865 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4866 #define CAN_F6R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4867 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4868 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4869 #define CAN_F6R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4870 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4871 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4872 #define CAN_F6R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4873 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4874 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4875 #define CAN_F6R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4876 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4877 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4878 #define CAN_F6R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4879 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4880 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4881 #define CAN_F6R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4882 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4883 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4884 #define CAN_F6R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4885 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4886 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4887 #define CAN_F6R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4888 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4889 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4890 #define CAN_F6R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4891 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4892 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4893 #define CAN_F6R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4894 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4895 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4896 #define CAN_F6R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4897 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4898 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4899 #define CAN_F6R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4900 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4901 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 4902 #define CAN_F6R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 4903 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 4904 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 4905 #define CAN_F6R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 4906 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 4907 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 4908 #define CAN_F6R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 4909 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 4910 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 4911 #define CAN_F6R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 4912 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 4913 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 4914 #define CAN_F6R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 4915 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 4916 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 4917 #define CAN_F6R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 4918 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 4919 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 4920
sahilmgandhi 18:6a4db94011d3 4921 /******************* Bit definition for CAN_F7R2 register *******************/
sahilmgandhi 18:6a4db94011d3 4922 #define CAN_F7R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 4923 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 4924 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 4925 #define CAN_F7R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 4926 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 4927 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 4928 #define CAN_F7R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 4929 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 4930 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 4931 #define CAN_F7R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 4932 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 4933 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 4934 #define CAN_F7R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 4935 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 4936 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 4937 #define CAN_F7R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 4938 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 4939 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 4940 #define CAN_F7R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 4941 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 4942 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 4943 #define CAN_F7R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 4944 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 4945 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 4946 #define CAN_F7R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 4947 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 4948 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 4949 #define CAN_F7R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 4950 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 4951 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 4952 #define CAN_F7R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 4953 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 4954 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 4955 #define CAN_F7R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 4956 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 4957 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 4958 #define CAN_F7R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 4959 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 4960 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 4961 #define CAN_F7R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 4962 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 4963 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 4964 #define CAN_F7R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 4965 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 4966 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 4967 #define CAN_F7R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 4968 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 4969 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 4970 #define CAN_F7R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 4971 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 4972 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 4973 #define CAN_F7R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 4974 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 4975 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 4976 #define CAN_F7R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 4977 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 4978 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 4979 #define CAN_F7R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 4980 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 4981 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 4982 #define CAN_F7R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 4983 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 4984 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 4985 #define CAN_F7R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 4986 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 4987 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 4988 #define CAN_F7R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 4989 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 4990 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 4991 #define CAN_F7R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 4992 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 4993 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 4994 #define CAN_F7R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 4995 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 4996 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 4997 #define CAN_F7R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 4998 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 4999 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 5000 #define CAN_F7R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5001 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5002 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 5003 #define CAN_F7R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5004 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5005 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 5006 #define CAN_F7R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5007 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5008 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 5009 #define CAN_F7R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5010 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5011 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 5012 #define CAN_F7R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5013 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5014 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 5015 #define CAN_F7R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5016 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5017 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 5018
sahilmgandhi 18:6a4db94011d3 5019 /******************* Bit definition for CAN_F8R2 register *******************/
sahilmgandhi 18:6a4db94011d3 5020 #define CAN_F8R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5021 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5022 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 5023 #define CAN_F8R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5024 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5025 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 5026 #define CAN_F8R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5027 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5028 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 5029 #define CAN_F8R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5030 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5031 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 5032 #define CAN_F8R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5033 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5034 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 5035 #define CAN_F8R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5036 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5037 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 5038 #define CAN_F8R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5039 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5040 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 5041 #define CAN_F8R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5042 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5043 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 5044 #define CAN_F8R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5045 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5046 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 5047 #define CAN_F8R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5048 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5049 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 5050 #define CAN_F8R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5051 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5052 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 5053 #define CAN_F8R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5054 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5055 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 5056 #define CAN_F8R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5057 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5058 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 5059 #define CAN_F8R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5060 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5061 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 5062 #define CAN_F8R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5063 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5064 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 5065 #define CAN_F8R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5066 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5067 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 5068 #define CAN_F8R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5069 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5070 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 5071 #define CAN_F8R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5072 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5073 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 5074 #define CAN_F8R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5075 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5076 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 5077 #define CAN_F8R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5078 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5079 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 5080 #define CAN_F8R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5081 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5082 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 5083 #define CAN_F8R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5084 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5085 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 5086 #define CAN_F8R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5087 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5088 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 5089 #define CAN_F8R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5090 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5091 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 5092 #define CAN_F8R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5093 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5094 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 5095 #define CAN_F8R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5096 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5097 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 5098 #define CAN_F8R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5099 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5100 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 5101 #define CAN_F8R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5102 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5103 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 5104 #define CAN_F8R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5105 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5106 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 5107 #define CAN_F8R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5108 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5109 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 5110 #define CAN_F8R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5111 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5112 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 5113 #define CAN_F8R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5114 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5115 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 5116
sahilmgandhi 18:6a4db94011d3 5117 /******************* Bit definition for CAN_F9R2 register *******************/
sahilmgandhi 18:6a4db94011d3 5118 #define CAN_F9R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5119 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5120 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 5121 #define CAN_F9R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5122 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5123 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 5124 #define CAN_F9R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5125 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5126 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 5127 #define CAN_F9R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5128 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5129 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 5130 #define CAN_F9R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5131 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5132 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 5133 #define CAN_F9R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5134 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5135 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 5136 #define CAN_F9R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5137 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5138 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 5139 #define CAN_F9R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5140 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5141 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 5142 #define CAN_F9R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5143 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5144 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 5145 #define CAN_F9R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5146 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5147 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 5148 #define CAN_F9R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5149 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5150 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 5151 #define CAN_F9R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5152 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5153 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 5154 #define CAN_F9R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5155 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5156 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 5157 #define CAN_F9R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5158 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5159 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 5160 #define CAN_F9R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5161 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5162 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 5163 #define CAN_F9R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5164 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5165 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 5166 #define CAN_F9R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5167 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5168 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 5169 #define CAN_F9R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5170 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5171 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 5172 #define CAN_F9R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5173 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5174 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 5175 #define CAN_F9R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5176 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5177 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 5178 #define CAN_F9R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5179 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5180 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 5181 #define CAN_F9R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5182 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5183 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 5184 #define CAN_F9R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5185 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5186 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 5187 #define CAN_F9R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5188 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5189 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 5190 #define CAN_F9R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5191 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5192 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 5193 #define CAN_F9R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5194 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5195 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 5196 #define CAN_F9R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5197 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5198 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 5199 #define CAN_F9R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5200 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5201 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 5202 #define CAN_F9R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5203 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5204 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 5205 #define CAN_F9R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5206 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5207 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 5208 #define CAN_F9R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5209 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5210 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 5211 #define CAN_F9R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5212 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5213 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 5214
sahilmgandhi 18:6a4db94011d3 5215 /******************* Bit definition for CAN_F10R2 register ******************/
sahilmgandhi 18:6a4db94011d3 5216 #define CAN_F10R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5217 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5218 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 5219 #define CAN_F10R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5220 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5221 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 5222 #define CAN_F10R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5223 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5224 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 5225 #define CAN_F10R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5226 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5227 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 5228 #define CAN_F10R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5229 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5230 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 5231 #define CAN_F10R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5232 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5233 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 5234 #define CAN_F10R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5235 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5236 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 5237 #define CAN_F10R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5238 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5239 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 5240 #define CAN_F10R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5241 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5242 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 5243 #define CAN_F10R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5244 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5245 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 5246 #define CAN_F10R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5247 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5248 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 5249 #define CAN_F10R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5250 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5251 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 5252 #define CAN_F10R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5253 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5254 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 5255 #define CAN_F10R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5256 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5257 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 5258 #define CAN_F10R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5259 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5260 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 5261 #define CAN_F10R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5262 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5263 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 5264 #define CAN_F10R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5265 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5266 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 5267 #define CAN_F10R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5268 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5269 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 5270 #define CAN_F10R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5271 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5272 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 5273 #define CAN_F10R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5274 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5275 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 5276 #define CAN_F10R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5277 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5278 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 5279 #define CAN_F10R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5280 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5281 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 5282 #define CAN_F10R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5283 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5284 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 5285 #define CAN_F10R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5286 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5287 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 5288 #define CAN_F10R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5289 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5290 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 5291 #define CAN_F10R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5292 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5293 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 5294 #define CAN_F10R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5295 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5296 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 5297 #define CAN_F10R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5298 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5299 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 5300 #define CAN_F10R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5301 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5302 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 5303 #define CAN_F10R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5304 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5305 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 5306 #define CAN_F10R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5307 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5308 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 5309 #define CAN_F10R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5310 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5311 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 5312
sahilmgandhi 18:6a4db94011d3 5313 /******************* Bit definition for CAN_F11R2 register ******************/
sahilmgandhi 18:6a4db94011d3 5314 #define CAN_F11R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5315 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5316 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 5317 #define CAN_F11R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5318 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5319 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 5320 #define CAN_F11R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5321 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5322 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 5323 #define CAN_F11R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5324 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5325 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 5326 #define CAN_F11R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5327 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5328 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 5329 #define CAN_F11R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5330 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5331 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 5332 #define CAN_F11R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5333 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5334 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 5335 #define CAN_F11R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5336 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5337 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 5338 #define CAN_F11R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5339 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5340 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 5341 #define CAN_F11R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5342 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5343 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 5344 #define CAN_F11R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5345 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5346 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 5347 #define CAN_F11R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5348 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5349 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 5350 #define CAN_F11R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5351 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5352 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 5353 #define CAN_F11R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5354 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5355 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 5356 #define CAN_F11R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5357 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5358 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 5359 #define CAN_F11R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5360 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5361 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 5362 #define CAN_F11R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5363 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5364 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 5365 #define CAN_F11R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5366 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5367 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 5368 #define CAN_F11R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5369 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5370 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 5371 #define CAN_F11R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5372 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5373 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 5374 #define CAN_F11R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5375 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5376 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 5377 #define CAN_F11R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5378 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5379 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 5380 #define CAN_F11R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5381 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5382 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 5383 #define CAN_F11R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5384 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5385 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 5386 #define CAN_F11R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5387 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5388 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 5389 #define CAN_F11R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5390 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5391 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 5392 #define CAN_F11R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5393 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5394 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 5395 #define CAN_F11R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5396 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5397 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 5398 #define CAN_F11R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5399 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5400 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 5401 #define CAN_F11R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5402 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5403 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 5404 #define CAN_F11R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5405 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5406 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 5407 #define CAN_F11R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5408 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5409 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 5410
sahilmgandhi 18:6a4db94011d3 5411 /******************* Bit definition for CAN_F12R2 register ******************/
sahilmgandhi 18:6a4db94011d3 5412 #define CAN_F12R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5413 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5414 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 5415 #define CAN_F12R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5416 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5417 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 5418 #define CAN_F12R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5419 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5420 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 5421 #define CAN_F12R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5422 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5423 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 5424 #define CAN_F12R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5425 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5426 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 5427 #define CAN_F12R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5428 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5429 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 5430 #define CAN_F12R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5431 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5432 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 5433 #define CAN_F12R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5434 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5435 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 5436 #define CAN_F12R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5437 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5438 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 5439 #define CAN_F12R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5440 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5441 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 5442 #define CAN_F12R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5443 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5444 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 5445 #define CAN_F12R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5446 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5447 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 5448 #define CAN_F12R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5449 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5450 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 5451 #define CAN_F12R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5452 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5453 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 5454 #define CAN_F12R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5455 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5456 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 5457 #define CAN_F12R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5458 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5459 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 5460 #define CAN_F12R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5461 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5462 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 5463 #define CAN_F12R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5464 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5465 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 5466 #define CAN_F12R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5467 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5468 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 5469 #define CAN_F12R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5470 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5471 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 5472 #define CAN_F12R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5473 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5474 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 5475 #define CAN_F12R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5476 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5477 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 5478 #define CAN_F12R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5479 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5480 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 5481 #define CAN_F12R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5482 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5483 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 5484 #define CAN_F12R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5485 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5486 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 5487 #define CAN_F12R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5488 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5489 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 5490 #define CAN_F12R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5491 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5492 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 5493 #define CAN_F12R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5494 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5495 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 5496 #define CAN_F12R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5497 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5498 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 5499 #define CAN_F12R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5500 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5501 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 5502 #define CAN_F12R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5503 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5504 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 5505 #define CAN_F12R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5506 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5507 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 5508
sahilmgandhi 18:6a4db94011d3 5509 /******************* Bit definition for CAN_F13R2 register ******************/
sahilmgandhi 18:6a4db94011d3 5510 #define CAN_F13R2_FB0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5511 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5512 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
sahilmgandhi 18:6a4db94011d3 5513 #define CAN_F13R2_FB1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5514 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5515 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
sahilmgandhi 18:6a4db94011d3 5516 #define CAN_F13R2_FB2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5517 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5518 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
sahilmgandhi 18:6a4db94011d3 5519 #define CAN_F13R2_FB3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5520 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5521 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
sahilmgandhi 18:6a4db94011d3 5522 #define CAN_F13R2_FB4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5523 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5524 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
sahilmgandhi 18:6a4db94011d3 5525 #define CAN_F13R2_FB5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5526 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5527 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
sahilmgandhi 18:6a4db94011d3 5528 #define CAN_F13R2_FB6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5529 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5530 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
sahilmgandhi 18:6a4db94011d3 5531 #define CAN_F13R2_FB7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5532 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5533 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
sahilmgandhi 18:6a4db94011d3 5534 #define CAN_F13R2_FB8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5535 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5536 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
sahilmgandhi 18:6a4db94011d3 5537 #define CAN_F13R2_FB9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 5538 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5539 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
sahilmgandhi 18:6a4db94011d3 5540 #define CAN_F13R2_FB10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 5541 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5542 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
sahilmgandhi 18:6a4db94011d3 5543 #define CAN_F13R2_FB11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 5544 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5545 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
sahilmgandhi 18:6a4db94011d3 5546 #define CAN_F13R2_FB12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5547 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5548 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
sahilmgandhi 18:6a4db94011d3 5549 #define CAN_F13R2_FB13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5550 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5551 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
sahilmgandhi 18:6a4db94011d3 5552 #define CAN_F13R2_FB14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5553 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5554 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
sahilmgandhi 18:6a4db94011d3 5555 #define CAN_F13R2_FB15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5556 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5557 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
sahilmgandhi 18:6a4db94011d3 5558 #define CAN_F13R2_FB16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5559 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5560 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
sahilmgandhi 18:6a4db94011d3 5561 #define CAN_F13R2_FB17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5562 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5563 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
sahilmgandhi 18:6a4db94011d3 5564 #define CAN_F13R2_FB18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5565 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5566 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
sahilmgandhi 18:6a4db94011d3 5567 #define CAN_F13R2_FB19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5568 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5569 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
sahilmgandhi 18:6a4db94011d3 5570 #define CAN_F13R2_FB20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5571 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5572 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
sahilmgandhi 18:6a4db94011d3 5573 #define CAN_F13R2_FB21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 5574 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5575 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
sahilmgandhi 18:6a4db94011d3 5576 #define CAN_F13R2_FB22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5577 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5578 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
sahilmgandhi 18:6a4db94011d3 5579 #define CAN_F13R2_FB23_Pos (23U)
sahilmgandhi 18:6a4db94011d3 5580 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5581 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
sahilmgandhi 18:6a4db94011d3 5582 #define CAN_F13R2_FB24_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5583 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5584 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
sahilmgandhi 18:6a4db94011d3 5585 #define CAN_F13R2_FB25_Pos (25U)
sahilmgandhi 18:6a4db94011d3 5586 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5587 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
sahilmgandhi 18:6a4db94011d3 5588 #define CAN_F13R2_FB26_Pos (26U)
sahilmgandhi 18:6a4db94011d3 5589 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5590 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
sahilmgandhi 18:6a4db94011d3 5591 #define CAN_F13R2_FB27_Pos (27U)
sahilmgandhi 18:6a4db94011d3 5592 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5593 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
sahilmgandhi 18:6a4db94011d3 5594 #define CAN_F13R2_FB28_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5595 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5596 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
sahilmgandhi 18:6a4db94011d3 5597 #define CAN_F13R2_FB29_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5598 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5599 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
sahilmgandhi 18:6a4db94011d3 5600 #define CAN_F13R2_FB30_Pos (30U)
sahilmgandhi 18:6a4db94011d3 5601 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 5602 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
sahilmgandhi 18:6a4db94011d3 5603 #define CAN_F13R2_FB31_Pos (31U)
sahilmgandhi 18:6a4db94011d3 5604 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 5605 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
sahilmgandhi 18:6a4db94011d3 5606
sahilmgandhi 18:6a4db94011d3 5607 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5608 /* */
sahilmgandhi 18:6a4db94011d3 5609 /* CRC calculation unit */
sahilmgandhi 18:6a4db94011d3 5610 /* */
sahilmgandhi 18:6a4db94011d3 5611 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5612 /******************* Bit definition for CRC_DR register *********************/
sahilmgandhi 18:6a4db94011d3 5613 #define CRC_DR_DR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5614 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 5615 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
sahilmgandhi 18:6a4db94011d3 5616
sahilmgandhi 18:6a4db94011d3 5617
sahilmgandhi 18:6a4db94011d3 5618 /******************* Bit definition for CRC_IDR register ********************/
sahilmgandhi 18:6a4db94011d3 5619 #define CRC_IDR_IDR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5620 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 5621 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
sahilmgandhi 18:6a4db94011d3 5622
sahilmgandhi 18:6a4db94011d3 5623
sahilmgandhi 18:6a4db94011d3 5624 /******************** Bit definition for CRC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 5625 #define CRC_CR_RESET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5626 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5627 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
sahilmgandhi 18:6a4db94011d3 5628
sahilmgandhi 18:6a4db94011d3 5629 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5630 /* */
sahilmgandhi 18:6a4db94011d3 5631 /* Crypto Processor */
sahilmgandhi 18:6a4db94011d3 5632 /* */
sahilmgandhi 18:6a4db94011d3 5633 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5634 /******************* Bits definition for CRYP_CR register ********************/
sahilmgandhi 18:6a4db94011d3 5635 #define CRYP_CR_ALGODIR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5636 #define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5637 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
sahilmgandhi 18:6a4db94011d3 5638
sahilmgandhi 18:6a4db94011d3 5639 #define CRYP_CR_ALGOMODE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5640 #define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
sahilmgandhi 18:6a4db94011d3 5641 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
sahilmgandhi 18:6a4db94011d3 5642 #define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5643 #define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5644 #define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5645 #define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
sahilmgandhi 18:6a4db94011d3 5646 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5647 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5648 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
sahilmgandhi 18:6a4db94011d3 5649 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5650 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5651 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
sahilmgandhi 18:6a4db94011d3 5652 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5653 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 5654 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
sahilmgandhi 18:6a4db94011d3 5655 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5656 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5657 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
sahilmgandhi 18:6a4db94011d3 5658 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5659 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
sahilmgandhi 18:6a4db94011d3 5660 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
sahilmgandhi 18:6a4db94011d3 5661 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5662 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 5663 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
sahilmgandhi 18:6a4db94011d3 5664 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5665 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 5666 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
sahilmgandhi 18:6a4db94011d3 5667
sahilmgandhi 18:6a4db94011d3 5668 #define CRYP_CR_DATATYPE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5669 #define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 5670 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
sahilmgandhi 18:6a4db94011d3 5671 #define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5672 #define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5673 #define CRYP_CR_KEYSIZE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5674 #define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 5675 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
sahilmgandhi 18:6a4db94011d3 5676 #define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5677 #define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5678 #define CRYP_CR_FFLUSH_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5679 #define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5680 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
sahilmgandhi 18:6a4db94011d3 5681 #define CRYP_CR_CRYPEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 5682 #define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 5683 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
sahilmgandhi 18:6a4db94011d3 5684
sahilmgandhi 18:6a4db94011d3 5685 #define CRYP_CR_GCM_CCMPH_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5686 #define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 5687 #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
sahilmgandhi 18:6a4db94011d3 5688 #define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5689 #define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5690 #define CRYP_CR_ALGOMODE_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 5691
sahilmgandhi 18:6a4db94011d3 5692 /****************** Bits definition for CRYP_SR register *********************/
sahilmgandhi 18:6a4db94011d3 5693 #define CRYP_SR_IFEM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5694 #define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5695 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
sahilmgandhi 18:6a4db94011d3 5696 #define CRYP_SR_IFNF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5697 #define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5698 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
sahilmgandhi 18:6a4db94011d3 5699 #define CRYP_SR_OFNE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5700 #define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5701 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
sahilmgandhi 18:6a4db94011d3 5702 #define CRYP_SR_OFFU_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5703 #define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5704 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
sahilmgandhi 18:6a4db94011d3 5705 #define CRYP_SR_BUSY_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5706 #define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5707 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
sahilmgandhi 18:6a4db94011d3 5708 /****************** Bits definition for CRYP_DMACR register ******************/
sahilmgandhi 18:6a4db94011d3 5709 #define CRYP_DMACR_DIEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5710 #define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5711 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
sahilmgandhi 18:6a4db94011d3 5712 #define CRYP_DMACR_DOEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5713 #define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5714 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
sahilmgandhi 18:6a4db94011d3 5715 /***************** Bits definition for CRYP_IMSCR register ******************/
sahilmgandhi 18:6a4db94011d3 5716 #define CRYP_IMSCR_INIM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5717 #define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5718 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
sahilmgandhi 18:6a4db94011d3 5719 #define CRYP_IMSCR_OUTIM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5720 #define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5721 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
sahilmgandhi 18:6a4db94011d3 5722 /****************** Bits definition for CRYP_RISR register *******************/
sahilmgandhi 18:6a4db94011d3 5723 #define CRYP_RISR_OUTRIS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5724 #define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5725 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
sahilmgandhi 18:6a4db94011d3 5726 #define CRYP_RISR_INRIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5727 #define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5728 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
sahilmgandhi 18:6a4db94011d3 5729 /****************** Bits definition for CRYP_MISR register *******************/
sahilmgandhi 18:6a4db94011d3 5730 #define CRYP_MISR_INMIS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5731 #define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5732 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
sahilmgandhi 18:6a4db94011d3 5733 #define CRYP_MISR_OUTMIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5734 #define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5735 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
sahilmgandhi 18:6a4db94011d3 5736
sahilmgandhi 18:6a4db94011d3 5737 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5738 /* */
sahilmgandhi 18:6a4db94011d3 5739 /* Digital to Analog Converter */
sahilmgandhi 18:6a4db94011d3 5740 /* */
sahilmgandhi 18:6a4db94011d3 5741 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5742 /*
sahilmgandhi 18:6a4db94011d3 5743 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
sahilmgandhi 18:6a4db94011d3 5744 */
sahilmgandhi 18:6a4db94011d3 5745 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
sahilmgandhi 18:6a4db94011d3 5746 /******************** Bit definition for DAC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 5747 #define DAC_CR_EN1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5748 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5749 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
sahilmgandhi 18:6a4db94011d3 5750 #define DAC_CR_BOFF1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5751 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5752 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
sahilmgandhi 18:6a4db94011d3 5753 #define DAC_CR_TEN1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5754 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5755 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
sahilmgandhi 18:6a4db94011d3 5756
sahilmgandhi 18:6a4db94011d3 5757 #define DAC_CR_TSEL1_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5758 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 5759 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
sahilmgandhi 18:6a4db94011d3 5760 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5761 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5762 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5763
sahilmgandhi 18:6a4db94011d3 5764 #define DAC_CR_WAVE1_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5765 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 5766 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
sahilmgandhi 18:6a4db94011d3 5767 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5768 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5769
sahilmgandhi 18:6a4db94011d3 5770 #define DAC_CR_MAMP1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5771 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 5772 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
sahilmgandhi 18:6a4db94011d3 5773 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 5774 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 5775 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 5776 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 5777
sahilmgandhi 18:6a4db94011d3 5778 #define DAC_CR_DMAEN1_Pos (12U)
sahilmgandhi 18:6a4db94011d3 5779 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 5780 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
sahilmgandhi 18:6a4db94011d3 5781 #define DAC_CR_DMAUDRIE1_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5782 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5783 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
sahilmgandhi 18:6a4db94011d3 5784 #define DAC_CR_EN2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5785 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 5786 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
sahilmgandhi 18:6a4db94011d3 5787 #define DAC_CR_BOFF2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 5788 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 5789 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
sahilmgandhi 18:6a4db94011d3 5790 #define DAC_CR_TEN2_Pos (18U)
sahilmgandhi 18:6a4db94011d3 5791 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 5792 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
sahilmgandhi 18:6a4db94011d3 5793
sahilmgandhi 18:6a4db94011d3 5794 #define DAC_CR_TSEL2_Pos (19U)
sahilmgandhi 18:6a4db94011d3 5795 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
sahilmgandhi 18:6a4db94011d3 5796 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
sahilmgandhi 18:6a4db94011d3 5797 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 5798 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 5799 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 5800
sahilmgandhi 18:6a4db94011d3 5801 #define DAC_CR_WAVE2_Pos (22U)
sahilmgandhi 18:6a4db94011d3 5802 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 5803 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
sahilmgandhi 18:6a4db94011d3 5804 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 5805 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 5806
sahilmgandhi 18:6a4db94011d3 5807 #define DAC_CR_MAMP2_Pos (24U)
sahilmgandhi 18:6a4db94011d3 5808 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 5809 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
sahilmgandhi 18:6a4db94011d3 5810 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 5811 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 5812 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 5813 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 5814
sahilmgandhi 18:6a4db94011d3 5815 #define DAC_CR_DMAEN2_Pos (28U)
sahilmgandhi 18:6a4db94011d3 5816 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 5817 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
sahilmgandhi 18:6a4db94011d3 5818 #define DAC_CR_DMAUDRIE2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5819 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5820 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
sahilmgandhi 18:6a4db94011d3 5821
sahilmgandhi 18:6a4db94011d3 5822 /***************** Bit definition for DAC_SWTRIGR register ******************/
sahilmgandhi 18:6a4db94011d3 5823 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5824 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5825 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
sahilmgandhi 18:6a4db94011d3 5826 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5827 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5828 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
sahilmgandhi 18:6a4db94011d3 5829
sahilmgandhi 18:6a4db94011d3 5830 /***************** Bit definition for DAC_DHR12R1 register ******************/
sahilmgandhi 18:6a4db94011d3 5831 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5832 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 5833 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 5834
sahilmgandhi 18:6a4db94011d3 5835 /***************** Bit definition for DAC_DHR12L1 register ******************/
sahilmgandhi 18:6a4db94011d3 5836 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5837 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 5838 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 5839
sahilmgandhi 18:6a4db94011d3 5840 /****************** Bit definition for DAC_DHR8R1 register ******************/
sahilmgandhi 18:6a4db94011d3 5841 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5842 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 5843 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 5844
sahilmgandhi 18:6a4db94011d3 5845 /***************** Bit definition for DAC_DHR12R2 register ******************/
sahilmgandhi 18:6a4db94011d3 5846 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5847 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 5848 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 5849
sahilmgandhi 18:6a4db94011d3 5850 /***************** Bit definition for DAC_DHR12L2 register ******************/
sahilmgandhi 18:6a4db94011d3 5851 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5852 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 5853 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 5854
sahilmgandhi 18:6a4db94011d3 5855 /****************** Bit definition for DAC_DHR8R2 register ******************/
sahilmgandhi 18:6a4db94011d3 5856 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5857 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 5858 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 5859
sahilmgandhi 18:6a4db94011d3 5860 /***************** Bit definition for DAC_DHR12RD register ******************/
sahilmgandhi 18:6a4db94011d3 5861 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5862 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 5863 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 5864 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 5865 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
sahilmgandhi 18:6a4db94011d3 5866 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 5867
sahilmgandhi 18:6a4db94011d3 5868 /***************** Bit definition for DAC_DHR12LD register ******************/
sahilmgandhi 18:6a4db94011d3 5869 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5870 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 5871 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 5872 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
sahilmgandhi 18:6a4db94011d3 5873 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
sahilmgandhi 18:6a4db94011d3 5874 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
sahilmgandhi 18:6a4db94011d3 5875
sahilmgandhi 18:6a4db94011d3 5876 /****************** Bit definition for DAC_DHR8RD register ******************/
sahilmgandhi 18:6a4db94011d3 5877 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5878 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 5879 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 5880 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 5881 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 5882 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
sahilmgandhi 18:6a4db94011d3 5883
sahilmgandhi 18:6a4db94011d3 5884 /******************* Bit definition for DAC_DOR1 register *******************/
sahilmgandhi 18:6a4db94011d3 5885 #define DAC_DOR1_DACC1DOR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5886 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 5887 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
sahilmgandhi 18:6a4db94011d3 5888
sahilmgandhi 18:6a4db94011d3 5889 /******************* Bit definition for DAC_DOR2 register *******************/
sahilmgandhi 18:6a4db94011d3 5890 #define DAC_DOR2_DACC2DOR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5891 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 5892 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
sahilmgandhi 18:6a4db94011d3 5893
sahilmgandhi 18:6a4db94011d3 5894 /******************** Bit definition for DAC_SR register ********************/
sahilmgandhi 18:6a4db94011d3 5895 #define DAC_SR_DMAUDR1_Pos (13U)
sahilmgandhi 18:6a4db94011d3 5896 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 5897 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
sahilmgandhi 18:6a4db94011d3 5898 #define DAC_SR_DMAUDR2_Pos (29U)
sahilmgandhi 18:6a4db94011d3 5899 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 5900 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
sahilmgandhi 18:6a4db94011d3 5901
sahilmgandhi 18:6a4db94011d3 5902 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5903 /* */
sahilmgandhi 18:6a4db94011d3 5904 /* DCMI */
sahilmgandhi 18:6a4db94011d3 5905 /* */
sahilmgandhi 18:6a4db94011d3 5906 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 5907 /******************** Bits definition for DCMI_CR register ******************/
sahilmgandhi 18:6a4db94011d3 5908 #define DCMI_CR_CAPTURE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5909 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5910 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
sahilmgandhi 18:6a4db94011d3 5911 #define DCMI_CR_CM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5912 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5913 #define DCMI_CR_CM DCMI_CR_CM_Msk
sahilmgandhi 18:6a4db94011d3 5914 #define DCMI_CR_CROP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5915 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5916 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
sahilmgandhi 18:6a4db94011d3 5917 #define DCMI_CR_JPEG_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5918 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5919 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
sahilmgandhi 18:6a4db94011d3 5920 #define DCMI_CR_ESS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5921 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5922 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
sahilmgandhi 18:6a4db94011d3 5923 #define DCMI_CR_PCKPOL_Pos (5U)
sahilmgandhi 18:6a4db94011d3 5924 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 5925 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
sahilmgandhi 18:6a4db94011d3 5926 #define DCMI_CR_HSPOL_Pos (6U)
sahilmgandhi 18:6a4db94011d3 5927 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 5928 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
sahilmgandhi 18:6a4db94011d3 5929 #define DCMI_CR_VSPOL_Pos (7U)
sahilmgandhi 18:6a4db94011d3 5930 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 5931 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
sahilmgandhi 18:6a4db94011d3 5932 #define DCMI_CR_FCRC_0 0x00000100U
sahilmgandhi 18:6a4db94011d3 5933 #define DCMI_CR_FCRC_1 0x00000200U
sahilmgandhi 18:6a4db94011d3 5934 #define DCMI_CR_EDM_0 0x00000400U
sahilmgandhi 18:6a4db94011d3 5935 #define DCMI_CR_EDM_1 0x00000800U
sahilmgandhi 18:6a4db94011d3 5936 #define DCMI_CR_ENABLE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 5937 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 5938 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
sahilmgandhi 18:6a4db94011d3 5939
sahilmgandhi 18:6a4db94011d3 5940 /******************** Bits definition for DCMI_SR register ******************/
sahilmgandhi 18:6a4db94011d3 5941 #define DCMI_SR_HSYNC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5942 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5943 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
sahilmgandhi 18:6a4db94011d3 5944 #define DCMI_SR_VSYNC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5945 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5946 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
sahilmgandhi 18:6a4db94011d3 5947 #define DCMI_SR_FNE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5948 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5949 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
sahilmgandhi 18:6a4db94011d3 5950
sahilmgandhi 18:6a4db94011d3 5951 /******************** Bits definition for DCMI_RIS register *****************/
sahilmgandhi 18:6a4db94011d3 5952 #define DCMI_RIS_FRAME_RIS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5953 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5954 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
sahilmgandhi 18:6a4db94011d3 5955 #define DCMI_RIS_OVR_RIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5956 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5957 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
sahilmgandhi 18:6a4db94011d3 5958 #define DCMI_RIS_ERR_RIS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5959 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5960 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
sahilmgandhi 18:6a4db94011d3 5961 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5962 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5963 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
sahilmgandhi 18:6a4db94011d3 5964 #define DCMI_RIS_LINE_RIS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5965 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5966 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
sahilmgandhi 18:6a4db94011d3 5967 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 5968 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
sahilmgandhi 18:6a4db94011d3 5969 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
sahilmgandhi 18:6a4db94011d3 5970 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
sahilmgandhi 18:6a4db94011d3 5971 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
sahilmgandhi 18:6a4db94011d3 5972 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
sahilmgandhi 18:6a4db94011d3 5973 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
sahilmgandhi 18:6a4db94011d3 5974
sahilmgandhi 18:6a4db94011d3 5975 /******************** Bits definition for DCMI_IER register *****************/
sahilmgandhi 18:6a4db94011d3 5976 #define DCMI_IER_FRAME_IE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5977 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5978 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
sahilmgandhi 18:6a4db94011d3 5979 #define DCMI_IER_OVR_IE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5980 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 5981 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
sahilmgandhi 18:6a4db94011d3 5982 #define DCMI_IER_ERR_IE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 5983 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 5984 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
sahilmgandhi 18:6a4db94011d3 5985 #define DCMI_IER_VSYNC_IE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 5986 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 5987 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
sahilmgandhi 18:6a4db94011d3 5988 #define DCMI_IER_LINE_IE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 5989 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 5990 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
sahilmgandhi 18:6a4db94011d3 5991 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 5992 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
sahilmgandhi 18:6a4db94011d3 5993
sahilmgandhi 18:6a4db94011d3 5994 /******************** Bits definition for DCMI_MIS register *****************/
sahilmgandhi 18:6a4db94011d3 5995 #define DCMI_MIS_FRAME_MIS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 5996 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 5997 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
sahilmgandhi 18:6a4db94011d3 5998 #define DCMI_MIS_OVR_MIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 5999 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6000 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
sahilmgandhi 18:6a4db94011d3 6001 #define DCMI_MIS_ERR_MIS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6002 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6003 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
sahilmgandhi 18:6a4db94011d3 6004 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6005 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6006 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
sahilmgandhi 18:6a4db94011d3 6007 #define DCMI_MIS_LINE_MIS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6008 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6009 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
sahilmgandhi 18:6a4db94011d3 6010
sahilmgandhi 18:6a4db94011d3 6011 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6012 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
sahilmgandhi 18:6a4db94011d3 6013 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
sahilmgandhi 18:6a4db94011d3 6014 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
sahilmgandhi 18:6a4db94011d3 6015 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
sahilmgandhi 18:6a4db94011d3 6016 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
sahilmgandhi 18:6a4db94011d3 6017
sahilmgandhi 18:6a4db94011d3 6018 /******************** Bits definition for DCMI_ICR register *****************/
sahilmgandhi 18:6a4db94011d3 6019 #define DCMI_ICR_FRAME_ISC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6020 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6021 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
sahilmgandhi 18:6a4db94011d3 6022 #define DCMI_ICR_OVR_ISC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6023 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6024 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
sahilmgandhi 18:6a4db94011d3 6025 #define DCMI_ICR_ERR_ISC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6026 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6027 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
sahilmgandhi 18:6a4db94011d3 6028 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6029 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6030 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
sahilmgandhi 18:6a4db94011d3 6031 #define DCMI_ICR_LINE_ISC_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6032 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6033 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
sahilmgandhi 18:6a4db94011d3 6034
sahilmgandhi 18:6a4db94011d3 6035 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6036 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
sahilmgandhi 18:6a4db94011d3 6037
sahilmgandhi 18:6a4db94011d3 6038 /******************** Bits definition for DCMI_ESCR register ******************/
sahilmgandhi 18:6a4db94011d3 6039 #define DCMI_ESCR_FSC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6040 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 6041 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
sahilmgandhi 18:6a4db94011d3 6042 #define DCMI_ESCR_LSC_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6043 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6044 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
sahilmgandhi 18:6a4db94011d3 6045 #define DCMI_ESCR_LEC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6046 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 6047 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
sahilmgandhi 18:6a4db94011d3 6048 #define DCMI_ESCR_FEC_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6049 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 6050 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
sahilmgandhi 18:6a4db94011d3 6051
sahilmgandhi 18:6a4db94011d3 6052 /******************** Bits definition for DCMI_ESUR register ******************/
sahilmgandhi 18:6a4db94011d3 6053 #define DCMI_ESUR_FSU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6054 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 6055 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
sahilmgandhi 18:6a4db94011d3 6056 #define DCMI_ESUR_LSU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6057 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6058 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
sahilmgandhi 18:6a4db94011d3 6059 #define DCMI_ESUR_LEU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6060 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 6061 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
sahilmgandhi 18:6a4db94011d3 6062 #define DCMI_ESUR_FEU_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6063 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 6064 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
sahilmgandhi 18:6a4db94011d3 6065
sahilmgandhi 18:6a4db94011d3 6066 /******************** Bits definition for DCMI_CWSTRT register ******************/
sahilmgandhi 18:6a4db94011d3 6067 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6068 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
sahilmgandhi 18:6a4db94011d3 6069 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
sahilmgandhi 18:6a4db94011d3 6070 #define DCMI_CWSTRT_VST_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6071 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
sahilmgandhi 18:6a4db94011d3 6072 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
sahilmgandhi 18:6a4db94011d3 6073
sahilmgandhi 18:6a4db94011d3 6074 /******************** Bits definition for DCMI_CWSIZE register ******************/
sahilmgandhi 18:6a4db94011d3 6075 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6076 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
sahilmgandhi 18:6a4db94011d3 6077 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
sahilmgandhi 18:6a4db94011d3 6078 #define DCMI_CWSIZE_VLINE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6079 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
sahilmgandhi 18:6a4db94011d3 6080 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
sahilmgandhi 18:6a4db94011d3 6081
sahilmgandhi 18:6a4db94011d3 6082 /******************** Bits definition for DCMI_DR register *********************/
sahilmgandhi 18:6a4db94011d3 6083 #define DCMI_DR_BYTE0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6084 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 6085 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
sahilmgandhi 18:6a4db94011d3 6086 #define DCMI_DR_BYTE1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6087 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6088 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
sahilmgandhi 18:6a4db94011d3 6089 #define DCMI_DR_BYTE2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6090 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 6091 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
sahilmgandhi 18:6a4db94011d3 6092 #define DCMI_DR_BYTE3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6093 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 6094 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
sahilmgandhi 18:6a4db94011d3 6095
sahilmgandhi 18:6a4db94011d3 6096 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6097 /* */
sahilmgandhi 18:6a4db94011d3 6098 /* DMA Controller */
sahilmgandhi 18:6a4db94011d3 6099 /* */
sahilmgandhi 18:6a4db94011d3 6100 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6101 /******************** Bits definition for DMA_SxCR register *****************/
sahilmgandhi 18:6a4db94011d3 6102 #define DMA_SxCR_CHSEL_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6103 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
sahilmgandhi 18:6a4db94011d3 6104 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
sahilmgandhi 18:6a4db94011d3 6105 #define DMA_SxCR_CHSEL_0 0x02000000U
sahilmgandhi 18:6a4db94011d3 6106 #define DMA_SxCR_CHSEL_1 0x04000000U
sahilmgandhi 18:6a4db94011d3 6107 #define DMA_SxCR_CHSEL_2 0x08000000U
sahilmgandhi 18:6a4db94011d3 6108 #define DMA_SxCR_MBURST_Pos (23U)
sahilmgandhi 18:6a4db94011d3 6109 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
sahilmgandhi 18:6a4db94011d3 6110 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
sahilmgandhi 18:6a4db94011d3 6111 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 6112 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6113 #define DMA_SxCR_PBURST_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6114 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
sahilmgandhi 18:6a4db94011d3 6115 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
sahilmgandhi 18:6a4db94011d3 6116 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6117 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6118 #define DMA_SxCR_CT_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6119 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6120 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
sahilmgandhi 18:6a4db94011d3 6121 #define DMA_SxCR_DBM_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6122 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6123 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
sahilmgandhi 18:6a4db94011d3 6124 #define DMA_SxCR_PL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6125 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 6126 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
sahilmgandhi 18:6a4db94011d3 6127 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6128 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6129 #define DMA_SxCR_PINCOS_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6130 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6131 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
sahilmgandhi 18:6a4db94011d3 6132 #define DMA_SxCR_MSIZE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6133 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
sahilmgandhi 18:6a4db94011d3 6134 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
sahilmgandhi 18:6a4db94011d3 6135 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6136 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6137 #define DMA_SxCR_PSIZE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6138 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 6139 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
sahilmgandhi 18:6a4db94011d3 6140 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6141 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6142 #define DMA_SxCR_MINC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6143 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6144 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
sahilmgandhi 18:6a4db94011d3 6145 #define DMA_SxCR_PINC_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6146 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6147 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
sahilmgandhi 18:6a4db94011d3 6148 #define DMA_SxCR_CIRC_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6149 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6150 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
sahilmgandhi 18:6a4db94011d3 6151 #define DMA_SxCR_DIR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6152 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 6153 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
sahilmgandhi 18:6a4db94011d3 6154 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6155 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6156 #define DMA_SxCR_PFCTRL_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6157 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6158 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
sahilmgandhi 18:6a4db94011d3 6159 #define DMA_SxCR_TCIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6160 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6161 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
sahilmgandhi 18:6a4db94011d3 6162 #define DMA_SxCR_HTIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6163 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6164 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
sahilmgandhi 18:6a4db94011d3 6165 #define DMA_SxCR_TEIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6166 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6167 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
sahilmgandhi 18:6a4db94011d3 6168 #define DMA_SxCR_DMEIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6169 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6170 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
sahilmgandhi 18:6a4db94011d3 6171 #define DMA_SxCR_EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6172 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6173 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
sahilmgandhi 18:6a4db94011d3 6174
sahilmgandhi 18:6a4db94011d3 6175 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6176 #define DMA_SxCR_ACK_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6177 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6178 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
sahilmgandhi 18:6a4db94011d3 6179
sahilmgandhi 18:6a4db94011d3 6180 /******************** Bits definition for DMA_SxCNDTR register **************/
sahilmgandhi 18:6a4db94011d3 6181 #define DMA_SxNDT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6182 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6183 #define DMA_SxNDT DMA_SxNDT_Msk
sahilmgandhi 18:6a4db94011d3 6184 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6185 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6186 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6187 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6188 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6189 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6190 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6191 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6192 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6193 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6194 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6195 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6196 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6197 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6198 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6199 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6200
sahilmgandhi 18:6a4db94011d3 6201 /******************** Bits definition for DMA_SxFCR register ****************/
sahilmgandhi 18:6a4db94011d3 6202 #define DMA_SxFCR_FEIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6203 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6204 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
sahilmgandhi 18:6a4db94011d3 6205 #define DMA_SxFCR_FS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6206 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 6207 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
sahilmgandhi 18:6a4db94011d3 6208 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6209 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6210 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6211 #define DMA_SxFCR_DMDIS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6212 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6213 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
sahilmgandhi 18:6a4db94011d3 6214 #define DMA_SxFCR_FTH_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6215 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 6216 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
sahilmgandhi 18:6a4db94011d3 6217 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6218 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6219
sahilmgandhi 18:6a4db94011d3 6220 /******************** Bits definition for DMA_LISR register *****************/
sahilmgandhi 18:6a4db94011d3 6221 #define DMA_LISR_TCIF3_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6222 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6223 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
sahilmgandhi 18:6a4db94011d3 6224 #define DMA_LISR_HTIF3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 6225 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6226 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
sahilmgandhi 18:6a4db94011d3 6227 #define DMA_LISR_TEIF3_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6228 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6229 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
sahilmgandhi 18:6a4db94011d3 6230 #define DMA_LISR_DMEIF3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6231 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6232 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
sahilmgandhi 18:6a4db94011d3 6233 #define DMA_LISR_FEIF3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6234 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6235 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
sahilmgandhi 18:6a4db94011d3 6236 #define DMA_LISR_TCIF2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6237 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6238 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
sahilmgandhi 18:6a4db94011d3 6239 #define DMA_LISR_HTIF2_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6240 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6241 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
sahilmgandhi 18:6a4db94011d3 6242 #define DMA_LISR_TEIF2_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6243 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6244 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
sahilmgandhi 18:6a4db94011d3 6245 #define DMA_LISR_DMEIF2_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6246 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6247 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
sahilmgandhi 18:6a4db94011d3 6248 #define DMA_LISR_FEIF2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6249 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6250 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
sahilmgandhi 18:6a4db94011d3 6251 #define DMA_LISR_TCIF1_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6252 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6253 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
sahilmgandhi 18:6a4db94011d3 6254 #define DMA_LISR_HTIF1_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6255 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6256 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
sahilmgandhi 18:6a4db94011d3 6257 #define DMA_LISR_TEIF1_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6258 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6259 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
sahilmgandhi 18:6a4db94011d3 6260 #define DMA_LISR_DMEIF1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6261 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6262 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
sahilmgandhi 18:6a4db94011d3 6263 #define DMA_LISR_FEIF1_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6264 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6265 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
sahilmgandhi 18:6a4db94011d3 6266 #define DMA_LISR_TCIF0_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6267 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6268 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
sahilmgandhi 18:6a4db94011d3 6269 #define DMA_LISR_HTIF0_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6270 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6271 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
sahilmgandhi 18:6a4db94011d3 6272 #define DMA_LISR_TEIF0_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6273 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6274 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
sahilmgandhi 18:6a4db94011d3 6275 #define DMA_LISR_DMEIF0_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6276 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6277 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
sahilmgandhi 18:6a4db94011d3 6278 #define DMA_LISR_FEIF0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6279 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6280 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
sahilmgandhi 18:6a4db94011d3 6281
sahilmgandhi 18:6a4db94011d3 6282 /******************** Bits definition for DMA_HISR register *****************/
sahilmgandhi 18:6a4db94011d3 6283 #define DMA_HISR_TCIF7_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6284 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6285 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
sahilmgandhi 18:6a4db94011d3 6286 #define DMA_HISR_HTIF7_Pos (26U)
sahilmgandhi 18:6a4db94011d3 6287 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6288 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
sahilmgandhi 18:6a4db94011d3 6289 #define DMA_HISR_TEIF7_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6290 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6291 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
sahilmgandhi 18:6a4db94011d3 6292 #define DMA_HISR_DMEIF7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6293 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6294 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
sahilmgandhi 18:6a4db94011d3 6295 #define DMA_HISR_FEIF7_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6296 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6297 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
sahilmgandhi 18:6a4db94011d3 6298 #define DMA_HISR_TCIF6_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6299 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6300 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
sahilmgandhi 18:6a4db94011d3 6301 #define DMA_HISR_HTIF6_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6302 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6303 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
sahilmgandhi 18:6a4db94011d3 6304 #define DMA_HISR_TEIF6_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6305 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6306 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
sahilmgandhi 18:6a4db94011d3 6307 #define DMA_HISR_DMEIF6_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6308 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6309 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
sahilmgandhi 18:6a4db94011d3 6310 #define DMA_HISR_FEIF6_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6311 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6312 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
sahilmgandhi 18:6a4db94011d3 6313 #define DMA_HISR_TCIF5_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6314 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6315 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
sahilmgandhi 18:6a4db94011d3 6316 #define DMA_HISR_HTIF5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6317 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6318 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
sahilmgandhi 18:6a4db94011d3 6319 #define DMA_HISR_TEIF5_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6320 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6321 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
sahilmgandhi 18:6a4db94011d3 6322 #define DMA_HISR_DMEIF5_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6323 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6324 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
sahilmgandhi 18:6a4db94011d3 6325 #define DMA_HISR_FEIF5_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6326 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6327 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
sahilmgandhi 18:6a4db94011d3 6328 #define DMA_HISR_TCIF4_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6329 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6330 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
sahilmgandhi 18:6a4db94011d3 6331 #define DMA_HISR_HTIF4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6332 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6333 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
sahilmgandhi 18:6a4db94011d3 6334 #define DMA_HISR_TEIF4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6335 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6336 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
sahilmgandhi 18:6a4db94011d3 6337 #define DMA_HISR_DMEIF4_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6338 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6339 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
sahilmgandhi 18:6a4db94011d3 6340 #define DMA_HISR_FEIF4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6341 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6342 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
sahilmgandhi 18:6a4db94011d3 6343
sahilmgandhi 18:6a4db94011d3 6344 /******************** Bits definition for DMA_LIFCR register ****************/
sahilmgandhi 18:6a4db94011d3 6345 #define DMA_LIFCR_CTCIF3_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6346 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6347 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
sahilmgandhi 18:6a4db94011d3 6348 #define DMA_LIFCR_CHTIF3_Pos (26U)
sahilmgandhi 18:6a4db94011d3 6349 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6350 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
sahilmgandhi 18:6a4db94011d3 6351 #define DMA_LIFCR_CTEIF3_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6352 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6353 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
sahilmgandhi 18:6a4db94011d3 6354 #define DMA_LIFCR_CDMEIF3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6355 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6356 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
sahilmgandhi 18:6a4db94011d3 6357 #define DMA_LIFCR_CFEIF3_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6358 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6359 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
sahilmgandhi 18:6a4db94011d3 6360 #define DMA_LIFCR_CTCIF2_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6361 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6362 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
sahilmgandhi 18:6a4db94011d3 6363 #define DMA_LIFCR_CHTIF2_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6364 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6365 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
sahilmgandhi 18:6a4db94011d3 6366 #define DMA_LIFCR_CTEIF2_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6367 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6368 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
sahilmgandhi 18:6a4db94011d3 6369 #define DMA_LIFCR_CDMEIF2_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6370 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6371 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
sahilmgandhi 18:6a4db94011d3 6372 #define DMA_LIFCR_CFEIF2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6373 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6374 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
sahilmgandhi 18:6a4db94011d3 6375 #define DMA_LIFCR_CTCIF1_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6376 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6377 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
sahilmgandhi 18:6a4db94011d3 6378 #define DMA_LIFCR_CHTIF1_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6379 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6380 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
sahilmgandhi 18:6a4db94011d3 6381 #define DMA_LIFCR_CTEIF1_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6382 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6383 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
sahilmgandhi 18:6a4db94011d3 6384 #define DMA_LIFCR_CDMEIF1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6385 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6386 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
sahilmgandhi 18:6a4db94011d3 6387 #define DMA_LIFCR_CFEIF1_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6388 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6389 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
sahilmgandhi 18:6a4db94011d3 6390 #define DMA_LIFCR_CTCIF0_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6391 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6392 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
sahilmgandhi 18:6a4db94011d3 6393 #define DMA_LIFCR_CHTIF0_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6394 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6395 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
sahilmgandhi 18:6a4db94011d3 6396 #define DMA_LIFCR_CTEIF0_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6397 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6398 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
sahilmgandhi 18:6a4db94011d3 6399 #define DMA_LIFCR_CDMEIF0_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6400 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6401 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
sahilmgandhi 18:6a4db94011d3 6402 #define DMA_LIFCR_CFEIF0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6403 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6404 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
sahilmgandhi 18:6a4db94011d3 6405
sahilmgandhi 18:6a4db94011d3 6406 /******************** Bits definition for DMA_HIFCR register ****************/
sahilmgandhi 18:6a4db94011d3 6407 #define DMA_HIFCR_CTCIF7_Pos (27U)
sahilmgandhi 18:6a4db94011d3 6408 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 6409 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
sahilmgandhi 18:6a4db94011d3 6410 #define DMA_HIFCR_CHTIF7_Pos (26U)
sahilmgandhi 18:6a4db94011d3 6411 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 6412 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
sahilmgandhi 18:6a4db94011d3 6413 #define DMA_HIFCR_CTEIF7_Pos (25U)
sahilmgandhi 18:6a4db94011d3 6414 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 6415 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
sahilmgandhi 18:6a4db94011d3 6416 #define DMA_HIFCR_CDMEIF7_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6417 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 6418 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
sahilmgandhi 18:6a4db94011d3 6419 #define DMA_HIFCR_CFEIF7_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6420 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6421 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
sahilmgandhi 18:6a4db94011d3 6422 #define DMA_HIFCR_CTCIF6_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6423 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6424 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
sahilmgandhi 18:6a4db94011d3 6425 #define DMA_HIFCR_CHTIF6_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6426 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6427 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
sahilmgandhi 18:6a4db94011d3 6428 #define DMA_HIFCR_CTEIF6_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6429 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6430 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
sahilmgandhi 18:6a4db94011d3 6431 #define DMA_HIFCR_CDMEIF6_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6432 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6433 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
sahilmgandhi 18:6a4db94011d3 6434 #define DMA_HIFCR_CFEIF6_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6435 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6436 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
sahilmgandhi 18:6a4db94011d3 6437 #define DMA_HIFCR_CTCIF5_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6438 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6439 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
sahilmgandhi 18:6a4db94011d3 6440 #define DMA_HIFCR_CHTIF5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6441 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6442 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
sahilmgandhi 18:6a4db94011d3 6443 #define DMA_HIFCR_CTEIF5_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6444 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6445 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
sahilmgandhi 18:6a4db94011d3 6446 #define DMA_HIFCR_CDMEIF5_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6447 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6448 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
sahilmgandhi 18:6a4db94011d3 6449 #define DMA_HIFCR_CFEIF5_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6450 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6451 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
sahilmgandhi 18:6a4db94011d3 6452 #define DMA_HIFCR_CTCIF4_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6453 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6454 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
sahilmgandhi 18:6a4db94011d3 6455 #define DMA_HIFCR_CHTIF4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6456 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6457 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
sahilmgandhi 18:6a4db94011d3 6458 #define DMA_HIFCR_CTEIF4_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6459 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6460 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
sahilmgandhi 18:6a4db94011d3 6461 #define DMA_HIFCR_CDMEIF4_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6462 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6463 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
sahilmgandhi 18:6a4db94011d3 6464 #define DMA_HIFCR_CFEIF4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6465 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6466 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
sahilmgandhi 18:6a4db94011d3 6467
sahilmgandhi 18:6a4db94011d3 6468 /****************** Bit definition for DMA_SxPAR register ********************/
sahilmgandhi 18:6a4db94011d3 6469 #define DMA_SxPAR_PA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6470 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 6471 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
sahilmgandhi 18:6a4db94011d3 6472
sahilmgandhi 18:6a4db94011d3 6473 /****************** Bit definition for DMA_SxM0AR register ********************/
sahilmgandhi 18:6a4db94011d3 6474 #define DMA_SxM0AR_M0A_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6475 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 6476 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 6477
sahilmgandhi 18:6a4db94011d3 6478 /****************** Bit definition for DMA_SxM1AR register ********************/
sahilmgandhi 18:6a4db94011d3 6479 #define DMA_SxM1AR_M1A_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6480 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 6481 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 6482
sahilmgandhi 18:6a4db94011d3 6483
sahilmgandhi 18:6a4db94011d3 6484 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6485 /* */
sahilmgandhi 18:6a4db94011d3 6486 /* AHB Master DMA2D Controller (DMA2D) */
sahilmgandhi 18:6a4db94011d3 6487 /* */
sahilmgandhi 18:6a4db94011d3 6488 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6489
sahilmgandhi 18:6a4db94011d3 6490 /******************** Bit definition for DMA2D_CR register ******************/
sahilmgandhi 18:6a4db94011d3 6491
sahilmgandhi 18:6a4db94011d3 6492 #define DMA2D_CR_START_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6493 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6494 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
sahilmgandhi 18:6a4db94011d3 6495 #define DMA2D_CR_SUSP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6496 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6497 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
sahilmgandhi 18:6a4db94011d3 6498 #define DMA2D_CR_ABORT_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6499 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6500 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
sahilmgandhi 18:6a4db94011d3 6501 #define DMA2D_CR_TEIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6502 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6503 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6504 #define DMA2D_CR_TCIE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6505 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6506 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6507 #define DMA2D_CR_TWIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6508 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6509 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6510 #define DMA2D_CR_CAEIE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6511 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6512 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6513 #define DMA2D_CR_CTCIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6514 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6515 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6516 #define DMA2D_CR_CEIE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6517 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6518 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 6519 #define DMA2D_CR_MODE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6520 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 6521 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
sahilmgandhi 18:6a4db94011d3 6522 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6523 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6524
sahilmgandhi 18:6a4db94011d3 6525 /******************** Bit definition for DMA2D_ISR register *****************/
sahilmgandhi 18:6a4db94011d3 6526
sahilmgandhi 18:6a4db94011d3 6527 #define DMA2D_ISR_TEIF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6528 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6529 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6530 #define DMA2D_ISR_TCIF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6531 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6532 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6533 #define DMA2D_ISR_TWIF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6534 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6535 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6536 #define DMA2D_ISR_CAEIF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6537 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6538 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6539 #define DMA2D_ISR_CTCIF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6540 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6541 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6542 #define DMA2D_ISR_CEIF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6543 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6544 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6545
sahilmgandhi 18:6a4db94011d3 6546 /******************** Bit definition for DMA2D_IFCR register ****************/
sahilmgandhi 18:6a4db94011d3 6547
sahilmgandhi 18:6a4db94011d3 6548 #define DMA2D_IFCR_CTEIF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6549 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6550 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6551 #define DMA2D_IFCR_CTCIF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6552 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6553 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6554 #define DMA2D_IFCR_CTWIF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6555 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6556 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6557 #define DMA2D_IFCR_CAECIF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6558 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6559 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6560 #define DMA2D_IFCR_CCTCIF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6561 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6562 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6563 #define DMA2D_IFCR_CCEIF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6564 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6565 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6566
sahilmgandhi 18:6a4db94011d3 6567 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 6568 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6569 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6570 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6571 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6572 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6573 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 6574
sahilmgandhi 18:6a4db94011d3 6575 /******************** Bit definition for DMA2D_FGMAR register ***************/
sahilmgandhi 18:6a4db94011d3 6576
sahilmgandhi 18:6a4db94011d3 6577 #define DMA2D_FGMAR_MA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6578 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 6579 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 6580
sahilmgandhi 18:6a4db94011d3 6581 /******************** Bit definition for DMA2D_FGOR register ****************/
sahilmgandhi 18:6a4db94011d3 6582
sahilmgandhi 18:6a4db94011d3 6583 #define DMA2D_FGOR_LO_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6584 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
sahilmgandhi 18:6a4db94011d3 6585 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
sahilmgandhi 18:6a4db94011d3 6586
sahilmgandhi 18:6a4db94011d3 6587 /******************** Bit definition for DMA2D_BGMAR register ***************/
sahilmgandhi 18:6a4db94011d3 6588
sahilmgandhi 18:6a4db94011d3 6589 #define DMA2D_BGMAR_MA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6590 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 6591 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 6592
sahilmgandhi 18:6a4db94011d3 6593 /******************** Bit definition for DMA2D_BGOR register ****************/
sahilmgandhi 18:6a4db94011d3 6594
sahilmgandhi 18:6a4db94011d3 6595 #define DMA2D_BGOR_LO_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6596 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
sahilmgandhi 18:6a4db94011d3 6597 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
sahilmgandhi 18:6a4db94011d3 6598
sahilmgandhi 18:6a4db94011d3 6599 /******************** Bit definition for DMA2D_FGPFCCR register *************/
sahilmgandhi 18:6a4db94011d3 6600
sahilmgandhi 18:6a4db94011d3 6601 #define DMA2D_FGPFCCR_CM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6602 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 6603 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
sahilmgandhi 18:6a4db94011d3 6604 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6605 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6606 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6607 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6608 #define DMA2D_FGPFCCR_CCM_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6609 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6610 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
sahilmgandhi 18:6a4db94011d3 6611 #define DMA2D_FGPFCCR_START_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6612 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6613 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
sahilmgandhi 18:6a4db94011d3 6614 #define DMA2D_FGPFCCR_CS_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6615 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6616 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
sahilmgandhi 18:6a4db94011d3 6617 #define DMA2D_FGPFCCR_AM_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6618 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 6619 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
sahilmgandhi 18:6a4db94011d3 6620 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6621 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6622 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6623 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 6624 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
sahilmgandhi 18:6a4db94011d3 6625
sahilmgandhi 18:6a4db94011d3 6626 /******************** Bit definition for DMA2D_FGCOLR register **************/
sahilmgandhi 18:6a4db94011d3 6627
sahilmgandhi 18:6a4db94011d3 6628 #define DMA2D_FGCOLR_BLUE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6629 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 6630 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
sahilmgandhi 18:6a4db94011d3 6631 #define DMA2D_FGCOLR_GREEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6632 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6633 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
sahilmgandhi 18:6a4db94011d3 6634 #define DMA2D_FGCOLR_RED_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6635 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 6636 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
sahilmgandhi 18:6a4db94011d3 6637
sahilmgandhi 18:6a4db94011d3 6638 /******************** Bit definition for DMA2D_BGPFCCR register *************/
sahilmgandhi 18:6a4db94011d3 6639
sahilmgandhi 18:6a4db94011d3 6640 #define DMA2D_BGPFCCR_CM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6641 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 6642 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
sahilmgandhi 18:6a4db94011d3 6643 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6644 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6645 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6646 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
sahilmgandhi 18:6a4db94011d3 6647 #define DMA2D_BGPFCCR_CCM_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6648 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6649 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
sahilmgandhi 18:6a4db94011d3 6650 #define DMA2D_BGPFCCR_START_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6651 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6652 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
sahilmgandhi 18:6a4db94011d3 6653 #define DMA2D_BGPFCCR_CS_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6654 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6655 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
sahilmgandhi 18:6a4db94011d3 6656 #define DMA2D_BGPFCCR_AM_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6657 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 6658 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
sahilmgandhi 18:6a4db94011d3 6659 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6660 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6661 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
sahilmgandhi 18:6a4db94011d3 6662 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 6663 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
sahilmgandhi 18:6a4db94011d3 6664
sahilmgandhi 18:6a4db94011d3 6665 /******************** Bit definition for DMA2D_BGCOLR register **************/
sahilmgandhi 18:6a4db94011d3 6666
sahilmgandhi 18:6a4db94011d3 6667 #define DMA2D_BGCOLR_BLUE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6668 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 6669 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
sahilmgandhi 18:6a4db94011d3 6670 #define DMA2D_BGCOLR_GREEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6671 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6672 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
sahilmgandhi 18:6a4db94011d3 6673 #define DMA2D_BGCOLR_RED_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6674 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 6675 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
sahilmgandhi 18:6a4db94011d3 6676
sahilmgandhi 18:6a4db94011d3 6677 /******************** Bit definition for DMA2D_FGCMAR register **************/
sahilmgandhi 18:6a4db94011d3 6678
sahilmgandhi 18:6a4db94011d3 6679 #define DMA2D_FGCMAR_MA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6680 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 6681 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 6682
sahilmgandhi 18:6a4db94011d3 6683 /******************** Bit definition for DMA2D_BGCMAR register **************/
sahilmgandhi 18:6a4db94011d3 6684
sahilmgandhi 18:6a4db94011d3 6685 #define DMA2D_BGCMAR_MA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6686 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 6687 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 6688
sahilmgandhi 18:6a4db94011d3 6689 /******************** Bit definition for DMA2D_OPFCCR register **************/
sahilmgandhi 18:6a4db94011d3 6690
sahilmgandhi 18:6a4db94011d3 6691 #define DMA2D_OPFCCR_CM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6692 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 6693 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
sahilmgandhi 18:6a4db94011d3 6694 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6695 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6696 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6697
sahilmgandhi 18:6a4db94011d3 6698 /******************** Bit definition for DMA2D_OCOLR register ***************/
sahilmgandhi 18:6a4db94011d3 6699
sahilmgandhi 18:6a4db94011d3 6700 /*!<Mode_ARGB8888/RGB888 */
sahilmgandhi 18:6a4db94011d3 6701
sahilmgandhi 18:6a4db94011d3 6702 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
sahilmgandhi 18:6a4db94011d3 6703 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
sahilmgandhi 18:6a4db94011d3 6704 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
sahilmgandhi 18:6a4db94011d3 6705 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
sahilmgandhi 18:6a4db94011d3 6706
sahilmgandhi 18:6a4db94011d3 6707 /*!<Mode_RGB565 */
sahilmgandhi 18:6a4db94011d3 6708 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
sahilmgandhi 18:6a4db94011d3 6709 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
sahilmgandhi 18:6a4db94011d3 6710 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
sahilmgandhi 18:6a4db94011d3 6711
sahilmgandhi 18:6a4db94011d3 6712 /*!<Mode_ARGB1555 */
sahilmgandhi 18:6a4db94011d3 6713 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
sahilmgandhi 18:6a4db94011d3 6714 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
sahilmgandhi 18:6a4db94011d3 6715 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
sahilmgandhi 18:6a4db94011d3 6716 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
sahilmgandhi 18:6a4db94011d3 6717
sahilmgandhi 18:6a4db94011d3 6718 /*!<Mode_ARGB4444 */
sahilmgandhi 18:6a4db94011d3 6719 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
sahilmgandhi 18:6a4db94011d3 6720 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
sahilmgandhi 18:6a4db94011d3 6721 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
sahilmgandhi 18:6a4db94011d3 6722 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
sahilmgandhi 18:6a4db94011d3 6723
sahilmgandhi 18:6a4db94011d3 6724 /******************** Bit definition for DMA2D_OMAR register ****************/
sahilmgandhi 18:6a4db94011d3 6725
sahilmgandhi 18:6a4db94011d3 6726 #define DMA2D_OMAR_MA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6727 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 6728 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
sahilmgandhi 18:6a4db94011d3 6729
sahilmgandhi 18:6a4db94011d3 6730 /******************** Bit definition for DMA2D_OOR register *****************/
sahilmgandhi 18:6a4db94011d3 6731
sahilmgandhi 18:6a4db94011d3 6732 #define DMA2D_OOR_LO_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6733 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
sahilmgandhi 18:6a4db94011d3 6734 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
sahilmgandhi 18:6a4db94011d3 6735
sahilmgandhi 18:6a4db94011d3 6736 /******************** Bit definition for DMA2D_NLR register *****************/
sahilmgandhi 18:6a4db94011d3 6737
sahilmgandhi 18:6a4db94011d3 6738 #define DMA2D_NLR_NL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6739 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6740 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
sahilmgandhi 18:6a4db94011d3 6741 #define DMA2D_NLR_PL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6742 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
sahilmgandhi 18:6a4db94011d3 6743 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
sahilmgandhi 18:6a4db94011d3 6744
sahilmgandhi 18:6a4db94011d3 6745 /******************** Bit definition for DMA2D_LWR register *****************/
sahilmgandhi 18:6a4db94011d3 6746
sahilmgandhi 18:6a4db94011d3 6747 #define DMA2D_LWR_LW_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6748 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 6749 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
sahilmgandhi 18:6a4db94011d3 6750
sahilmgandhi 18:6a4db94011d3 6751 /******************** Bit definition for DMA2D_AMTCR register ***************/
sahilmgandhi 18:6a4db94011d3 6752
sahilmgandhi 18:6a4db94011d3 6753 #define DMA2D_AMTCR_EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6754 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6755 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
sahilmgandhi 18:6a4db94011d3 6756 #define DMA2D_AMTCR_DT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6757 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 6758 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
sahilmgandhi 18:6a4db94011d3 6759
sahilmgandhi 18:6a4db94011d3 6760 /******************** Bit definition for DMA2D_FGCLUT register **************/
sahilmgandhi 18:6a4db94011d3 6761
sahilmgandhi 18:6a4db94011d3 6762 /******************** Bit definition for DMA2D_BGCLUT register **************/
sahilmgandhi 18:6a4db94011d3 6763
sahilmgandhi 18:6a4db94011d3 6764
sahilmgandhi 18:6a4db94011d3 6765 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6766 /* */
sahilmgandhi 18:6a4db94011d3 6767 /* External Interrupt/Event Controller */
sahilmgandhi 18:6a4db94011d3 6768 /* */
sahilmgandhi 18:6a4db94011d3 6769 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 6770 /******************* Bit definition for EXTI_IMR register *******************/
sahilmgandhi 18:6a4db94011d3 6771 #define EXTI_IMR_MR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6772 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6773 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 6774 #define EXTI_IMR_MR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6775 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6776 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 6777 #define EXTI_IMR_MR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6778 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6779 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 6780 #define EXTI_IMR_MR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6781 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6782 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 6783 #define EXTI_IMR_MR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6784 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6785 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 6786 #define EXTI_IMR_MR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6787 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6788 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 6789 #define EXTI_IMR_MR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6790 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6791 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 6792 #define EXTI_IMR_MR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6793 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6794 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 6795 #define EXTI_IMR_MR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6796 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6797 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 6798 #define EXTI_IMR_MR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6799 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6800 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 6801 #define EXTI_IMR_MR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6802 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6803 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 6804 #define EXTI_IMR_MR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6805 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6806 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 6807 #define EXTI_IMR_MR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6808 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6809 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 6810 #define EXTI_IMR_MR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6811 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6812 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 6813 #define EXTI_IMR_MR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6814 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6815 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 6816 #define EXTI_IMR_MR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6817 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6818 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 6819 #define EXTI_IMR_MR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6820 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6821 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 6822 #define EXTI_IMR_MR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6823 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6824 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 6825 #define EXTI_IMR_MR18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6826 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6827 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 6828 #define EXTI_IMR_MR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6829 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6830 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 6831 #define EXTI_IMR_MR20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6832 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6833 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
sahilmgandhi 18:6a4db94011d3 6834 #define EXTI_IMR_MR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6835 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6836 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 6837 #define EXTI_IMR_MR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6838 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6839 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 6840
sahilmgandhi 18:6a4db94011d3 6841 /* Reference Defines */
sahilmgandhi 18:6a4db94011d3 6842 #define EXTI_IMR_IM0 EXTI_IMR_MR0
sahilmgandhi 18:6a4db94011d3 6843 #define EXTI_IMR_IM1 EXTI_IMR_MR1
sahilmgandhi 18:6a4db94011d3 6844 #define EXTI_IMR_IM2 EXTI_IMR_MR2
sahilmgandhi 18:6a4db94011d3 6845 #define EXTI_IMR_IM3 EXTI_IMR_MR3
sahilmgandhi 18:6a4db94011d3 6846 #define EXTI_IMR_IM4 EXTI_IMR_MR4
sahilmgandhi 18:6a4db94011d3 6847 #define EXTI_IMR_IM5 EXTI_IMR_MR5
sahilmgandhi 18:6a4db94011d3 6848 #define EXTI_IMR_IM6 EXTI_IMR_MR6
sahilmgandhi 18:6a4db94011d3 6849 #define EXTI_IMR_IM7 EXTI_IMR_MR7
sahilmgandhi 18:6a4db94011d3 6850 #define EXTI_IMR_IM8 EXTI_IMR_MR8
sahilmgandhi 18:6a4db94011d3 6851 #define EXTI_IMR_IM9 EXTI_IMR_MR9
sahilmgandhi 18:6a4db94011d3 6852 #define EXTI_IMR_IM10 EXTI_IMR_MR10
sahilmgandhi 18:6a4db94011d3 6853 #define EXTI_IMR_IM11 EXTI_IMR_MR11
sahilmgandhi 18:6a4db94011d3 6854 #define EXTI_IMR_IM12 EXTI_IMR_MR12
sahilmgandhi 18:6a4db94011d3 6855 #define EXTI_IMR_IM13 EXTI_IMR_MR13
sahilmgandhi 18:6a4db94011d3 6856 #define EXTI_IMR_IM14 EXTI_IMR_MR14
sahilmgandhi 18:6a4db94011d3 6857 #define EXTI_IMR_IM15 EXTI_IMR_MR15
sahilmgandhi 18:6a4db94011d3 6858 #define EXTI_IMR_IM16 EXTI_IMR_MR16
sahilmgandhi 18:6a4db94011d3 6859 #define EXTI_IMR_IM17 EXTI_IMR_MR17
sahilmgandhi 18:6a4db94011d3 6860 #define EXTI_IMR_IM18 EXTI_IMR_MR18
sahilmgandhi 18:6a4db94011d3 6861 #define EXTI_IMR_IM19 EXTI_IMR_MR19
sahilmgandhi 18:6a4db94011d3 6862 #define EXTI_IMR_IM20 EXTI_IMR_MR20
sahilmgandhi 18:6a4db94011d3 6863 #define EXTI_IMR_IM21 EXTI_IMR_MR21
sahilmgandhi 18:6a4db94011d3 6864 #define EXTI_IMR_IM22 EXTI_IMR_MR22
sahilmgandhi 18:6a4db94011d3 6865 #define EXTI_IMR_IM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6866 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
sahilmgandhi 18:6a4db94011d3 6867 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
sahilmgandhi 18:6a4db94011d3 6868
sahilmgandhi 18:6a4db94011d3 6869 /******************* Bit definition for EXTI_EMR register *******************/
sahilmgandhi 18:6a4db94011d3 6870 #define EXTI_EMR_MR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6871 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6872 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
sahilmgandhi 18:6a4db94011d3 6873 #define EXTI_EMR_MR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6874 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6875 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
sahilmgandhi 18:6a4db94011d3 6876 #define EXTI_EMR_MR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6877 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6878 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
sahilmgandhi 18:6a4db94011d3 6879 #define EXTI_EMR_MR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6880 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6881 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
sahilmgandhi 18:6a4db94011d3 6882 #define EXTI_EMR_MR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6883 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6884 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
sahilmgandhi 18:6a4db94011d3 6885 #define EXTI_EMR_MR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6886 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6887 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
sahilmgandhi 18:6a4db94011d3 6888 #define EXTI_EMR_MR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6889 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6890 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
sahilmgandhi 18:6a4db94011d3 6891 #define EXTI_EMR_MR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6892 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6893 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
sahilmgandhi 18:6a4db94011d3 6894 #define EXTI_EMR_MR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6895 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6896 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
sahilmgandhi 18:6a4db94011d3 6897 #define EXTI_EMR_MR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6898 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6899 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
sahilmgandhi 18:6a4db94011d3 6900 #define EXTI_EMR_MR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6901 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6902 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
sahilmgandhi 18:6a4db94011d3 6903 #define EXTI_EMR_MR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 6904 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 6905 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
sahilmgandhi 18:6a4db94011d3 6906 #define EXTI_EMR_MR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 6907 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 6908 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
sahilmgandhi 18:6a4db94011d3 6909 #define EXTI_EMR_MR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 6910 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 6911 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
sahilmgandhi 18:6a4db94011d3 6912 #define EXTI_EMR_MR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 6913 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 6914 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
sahilmgandhi 18:6a4db94011d3 6915 #define EXTI_EMR_MR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 6916 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 6917 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
sahilmgandhi 18:6a4db94011d3 6918 #define EXTI_EMR_MR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 6919 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 6920 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
sahilmgandhi 18:6a4db94011d3 6921 #define EXTI_EMR_MR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 6922 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 6923 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
sahilmgandhi 18:6a4db94011d3 6924 #define EXTI_EMR_MR18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 6925 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 6926 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
sahilmgandhi 18:6a4db94011d3 6927 #define EXTI_EMR_MR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 6928 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 6929 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
sahilmgandhi 18:6a4db94011d3 6930 #define EXTI_EMR_MR20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 6931 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 6932 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
sahilmgandhi 18:6a4db94011d3 6933 #define EXTI_EMR_MR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 6934 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 6935 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
sahilmgandhi 18:6a4db94011d3 6936 #define EXTI_EMR_MR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 6937 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 6938 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
sahilmgandhi 18:6a4db94011d3 6939
sahilmgandhi 18:6a4db94011d3 6940 /* Reference Defines */
sahilmgandhi 18:6a4db94011d3 6941 #define EXTI_EMR_EM0 EXTI_EMR_MR0
sahilmgandhi 18:6a4db94011d3 6942 #define EXTI_EMR_EM1 EXTI_EMR_MR1
sahilmgandhi 18:6a4db94011d3 6943 #define EXTI_EMR_EM2 EXTI_EMR_MR2
sahilmgandhi 18:6a4db94011d3 6944 #define EXTI_EMR_EM3 EXTI_EMR_MR3
sahilmgandhi 18:6a4db94011d3 6945 #define EXTI_EMR_EM4 EXTI_EMR_MR4
sahilmgandhi 18:6a4db94011d3 6946 #define EXTI_EMR_EM5 EXTI_EMR_MR5
sahilmgandhi 18:6a4db94011d3 6947 #define EXTI_EMR_EM6 EXTI_EMR_MR6
sahilmgandhi 18:6a4db94011d3 6948 #define EXTI_EMR_EM7 EXTI_EMR_MR7
sahilmgandhi 18:6a4db94011d3 6949 #define EXTI_EMR_EM8 EXTI_EMR_MR8
sahilmgandhi 18:6a4db94011d3 6950 #define EXTI_EMR_EM9 EXTI_EMR_MR9
sahilmgandhi 18:6a4db94011d3 6951 #define EXTI_EMR_EM10 EXTI_EMR_MR10
sahilmgandhi 18:6a4db94011d3 6952 #define EXTI_EMR_EM11 EXTI_EMR_MR11
sahilmgandhi 18:6a4db94011d3 6953 #define EXTI_EMR_EM12 EXTI_EMR_MR12
sahilmgandhi 18:6a4db94011d3 6954 #define EXTI_EMR_EM13 EXTI_EMR_MR13
sahilmgandhi 18:6a4db94011d3 6955 #define EXTI_EMR_EM14 EXTI_EMR_MR14
sahilmgandhi 18:6a4db94011d3 6956 #define EXTI_EMR_EM15 EXTI_EMR_MR15
sahilmgandhi 18:6a4db94011d3 6957 #define EXTI_EMR_EM16 EXTI_EMR_MR16
sahilmgandhi 18:6a4db94011d3 6958 #define EXTI_EMR_EM17 EXTI_EMR_MR17
sahilmgandhi 18:6a4db94011d3 6959 #define EXTI_EMR_EM18 EXTI_EMR_MR18
sahilmgandhi 18:6a4db94011d3 6960 #define EXTI_EMR_EM19 EXTI_EMR_MR19
sahilmgandhi 18:6a4db94011d3 6961 #define EXTI_EMR_EM20 EXTI_EMR_MR20
sahilmgandhi 18:6a4db94011d3 6962 #define EXTI_EMR_EM21 EXTI_EMR_MR21
sahilmgandhi 18:6a4db94011d3 6963 #define EXTI_EMR_EM22 EXTI_EMR_MR22
sahilmgandhi 18:6a4db94011d3 6964
sahilmgandhi 18:6a4db94011d3 6965 /****************** Bit definition for EXTI_RTSR register *******************/
sahilmgandhi 18:6a4db94011d3 6966 #define EXTI_RTSR_TR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 6967 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 6968 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 6969 #define EXTI_RTSR_TR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 6970 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 6971 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 6972 #define EXTI_RTSR_TR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 6973 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 6974 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 6975 #define EXTI_RTSR_TR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 6976 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 6977 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 6978 #define EXTI_RTSR_TR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 6979 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 6980 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 6981 #define EXTI_RTSR_TR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 6982 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 6983 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 6984 #define EXTI_RTSR_TR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 6985 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 6986 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 6987 #define EXTI_RTSR_TR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 6988 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 6989 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 6990 #define EXTI_RTSR_TR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 6991 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 6992 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 6993 #define EXTI_RTSR_TR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 6994 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 6995 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 6996 #define EXTI_RTSR_TR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 6997 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 6998 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 6999 #define EXTI_RTSR_TR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7000 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7001 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 7002 #define EXTI_RTSR_TR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7003 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7004 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 7005 #define EXTI_RTSR_TR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7006 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7007 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 7008 #define EXTI_RTSR_TR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7009 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7010 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 7011 #define EXTI_RTSR_TR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7012 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7013 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 7014 #define EXTI_RTSR_TR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7015 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7016 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 7017 #define EXTI_RTSR_TR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 7018 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7019 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 7020 #define EXTI_RTSR_TR18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 7021 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7022 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
sahilmgandhi 18:6a4db94011d3 7023 #define EXTI_RTSR_TR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7024 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7025 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 7026 #define EXTI_RTSR_TR20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7027 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7028 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
sahilmgandhi 18:6a4db94011d3 7029 #define EXTI_RTSR_TR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 7030 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7031 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 7032 #define EXTI_RTSR_TR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 7033 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7034 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 7035
sahilmgandhi 18:6a4db94011d3 7036 /****************** Bit definition for EXTI_FTSR register *******************/
sahilmgandhi 18:6a4db94011d3 7037 #define EXTI_FTSR_TR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7038 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7039 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
sahilmgandhi 18:6a4db94011d3 7040 #define EXTI_FTSR_TR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7041 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7042 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
sahilmgandhi 18:6a4db94011d3 7043 #define EXTI_FTSR_TR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7044 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7045 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
sahilmgandhi 18:6a4db94011d3 7046 #define EXTI_FTSR_TR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 7047 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7048 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
sahilmgandhi 18:6a4db94011d3 7049 #define EXTI_FTSR_TR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7050 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7051 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
sahilmgandhi 18:6a4db94011d3 7052 #define EXTI_FTSR_TR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 7053 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7054 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
sahilmgandhi 18:6a4db94011d3 7055 #define EXTI_FTSR_TR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7056 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7057 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
sahilmgandhi 18:6a4db94011d3 7058 #define EXTI_FTSR_TR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7059 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7060 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
sahilmgandhi 18:6a4db94011d3 7061 #define EXTI_FTSR_TR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7062 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7063 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
sahilmgandhi 18:6a4db94011d3 7064 #define EXTI_FTSR_TR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7065 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7066 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
sahilmgandhi 18:6a4db94011d3 7067 #define EXTI_FTSR_TR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7068 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7069 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
sahilmgandhi 18:6a4db94011d3 7070 #define EXTI_FTSR_TR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7071 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7072 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
sahilmgandhi 18:6a4db94011d3 7073 #define EXTI_FTSR_TR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7074 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7075 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
sahilmgandhi 18:6a4db94011d3 7076 #define EXTI_FTSR_TR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7077 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7078 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
sahilmgandhi 18:6a4db94011d3 7079 #define EXTI_FTSR_TR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7080 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7081 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
sahilmgandhi 18:6a4db94011d3 7082 #define EXTI_FTSR_TR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7083 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7084 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
sahilmgandhi 18:6a4db94011d3 7085 #define EXTI_FTSR_TR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7086 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7087 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
sahilmgandhi 18:6a4db94011d3 7088 #define EXTI_FTSR_TR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 7089 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7090 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
sahilmgandhi 18:6a4db94011d3 7091 #define EXTI_FTSR_TR18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 7092 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7093 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
sahilmgandhi 18:6a4db94011d3 7094 #define EXTI_FTSR_TR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7095 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7096 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
sahilmgandhi 18:6a4db94011d3 7097 #define EXTI_FTSR_TR20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7098 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7099 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
sahilmgandhi 18:6a4db94011d3 7100 #define EXTI_FTSR_TR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 7101 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7102 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
sahilmgandhi 18:6a4db94011d3 7103 #define EXTI_FTSR_TR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 7104 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7105 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
sahilmgandhi 18:6a4db94011d3 7106
sahilmgandhi 18:6a4db94011d3 7107 /****************** Bit definition for EXTI_SWIER register ******************/
sahilmgandhi 18:6a4db94011d3 7108 #define EXTI_SWIER_SWIER0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7109 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7110 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
sahilmgandhi 18:6a4db94011d3 7111 #define EXTI_SWIER_SWIER1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7112 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7113 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
sahilmgandhi 18:6a4db94011d3 7114 #define EXTI_SWIER_SWIER2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7115 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7116 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
sahilmgandhi 18:6a4db94011d3 7117 #define EXTI_SWIER_SWIER3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 7118 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7119 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
sahilmgandhi 18:6a4db94011d3 7120 #define EXTI_SWIER_SWIER4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7121 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7122 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
sahilmgandhi 18:6a4db94011d3 7123 #define EXTI_SWIER_SWIER5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 7124 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7125 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
sahilmgandhi 18:6a4db94011d3 7126 #define EXTI_SWIER_SWIER6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7127 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7128 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
sahilmgandhi 18:6a4db94011d3 7129 #define EXTI_SWIER_SWIER7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7130 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7131 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
sahilmgandhi 18:6a4db94011d3 7132 #define EXTI_SWIER_SWIER8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7133 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7134 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
sahilmgandhi 18:6a4db94011d3 7135 #define EXTI_SWIER_SWIER9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7136 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7137 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
sahilmgandhi 18:6a4db94011d3 7138 #define EXTI_SWIER_SWIER10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7139 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7140 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
sahilmgandhi 18:6a4db94011d3 7141 #define EXTI_SWIER_SWIER11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7142 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7143 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
sahilmgandhi 18:6a4db94011d3 7144 #define EXTI_SWIER_SWIER12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7145 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7146 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
sahilmgandhi 18:6a4db94011d3 7147 #define EXTI_SWIER_SWIER13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7148 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7149 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
sahilmgandhi 18:6a4db94011d3 7150 #define EXTI_SWIER_SWIER14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7151 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7152 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
sahilmgandhi 18:6a4db94011d3 7153 #define EXTI_SWIER_SWIER15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7154 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7155 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
sahilmgandhi 18:6a4db94011d3 7156 #define EXTI_SWIER_SWIER16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7157 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7158 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
sahilmgandhi 18:6a4db94011d3 7159 #define EXTI_SWIER_SWIER17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 7160 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7161 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
sahilmgandhi 18:6a4db94011d3 7162 #define EXTI_SWIER_SWIER18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 7163 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7164 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
sahilmgandhi 18:6a4db94011d3 7165 #define EXTI_SWIER_SWIER19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7166 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7167 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
sahilmgandhi 18:6a4db94011d3 7168 #define EXTI_SWIER_SWIER20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7169 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7170 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
sahilmgandhi 18:6a4db94011d3 7171 #define EXTI_SWIER_SWIER21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 7172 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7173 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
sahilmgandhi 18:6a4db94011d3 7174 #define EXTI_SWIER_SWIER22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 7175 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7176 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
sahilmgandhi 18:6a4db94011d3 7177
sahilmgandhi 18:6a4db94011d3 7178 /******************* Bit definition for EXTI_PR register ********************/
sahilmgandhi 18:6a4db94011d3 7179 #define EXTI_PR_PR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7180 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7181 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
sahilmgandhi 18:6a4db94011d3 7182 #define EXTI_PR_PR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7183 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7184 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
sahilmgandhi 18:6a4db94011d3 7185 #define EXTI_PR_PR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7186 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7187 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
sahilmgandhi 18:6a4db94011d3 7188 #define EXTI_PR_PR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 7189 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7190 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
sahilmgandhi 18:6a4db94011d3 7191 #define EXTI_PR_PR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7192 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7193 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
sahilmgandhi 18:6a4db94011d3 7194 #define EXTI_PR_PR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 7195 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7196 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
sahilmgandhi 18:6a4db94011d3 7197 #define EXTI_PR_PR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7198 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7199 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
sahilmgandhi 18:6a4db94011d3 7200 #define EXTI_PR_PR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7201 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7202 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
sahilmgandhi 18:6a4db94011d3 7203 #define EXTI_PR_PR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7204 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7205 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
sahilmgandhi 18:6a4db94011d3 7206 #define EXTI_PR_PR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7207 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7208 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
sahilmgandhi 18:6a4db94011d3 7209 #define EXTI_PR_PR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7210 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7211 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
sahilmgandhi 18:6a4db94011d3 7212 #define EXTI_PR_PR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7213 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7214 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
sahilmgandhi 18:6a4db94011d3 7215 #define EXTI_PR_PR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7216 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7217 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
sahilmgandhi 18:6a4db94011d3 7218 #define EXTI_PR_PR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7219 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7220 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
sahilmgandhi 18:6a4db94011d3 7221 #define EXTI_PR_PR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7222 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7223 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
sahilmgandhi 18:6a4db94011d3 7224 #define EXTI_PR_PR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7225 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7226 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
sahilmgandhi 18:6a4db94011d3 7227 #define EXTI_PR_PR16_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7228 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7229 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
sahilmgandhi 18:6a4db94011d3 7230 #define EXTI_PR_PR17_Pos (17U)
sahilmgandhi 18:6a4db94011d3 7231 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7232 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
sahilmgandhi 18:6a4db94011d3 7233 #define EXTI_PR_PR18_Pos (18U)
sahilmgandhi 18:6a4db94011d3 7234 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7235 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
sahilmgandhi 18:6a4db94011d3 7236 #define EXTI_PR_PR19_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7237 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7238 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
sahilmgandhi 18:6a4db94011d3 7239 #define EXTI_PR_PR20_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7240 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7241 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
sahilmgandhi 18:6a4db94011d3 7242 #define EXTI_PR_PR21_Pos (21U)
sahilmgandhi 18:6a4db94011d3 7243 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7244 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
sahilmgandhi 18:6a4db94011d3 7245 #define EXTI_PR_PR22_Pos (22U)
sahilmgandhi 18:6a4db94011d3 7246 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7247 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
sahilmgandhi 18:6a4db94011d3 7248
sahilmgandhi 18:6a4db94011d3 7249 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7250 /* */
sahilmgandhi 18:6a4db94011d3 7251 /* FLASH */
sahilmgandhi 18:6a4db94011d3 7252 /* */
sahilmgandhi 18:6a4db94011d3 7253 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7254 /******************* Bits definition for FLASH_ACR register *****************/
sahilmgandhi 18:6a4db94011d3 7255 #define FLASH_ACR_LATENCY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7256 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7257 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
sahilmgandhi 18:6a4db94011d3 7258 #define FLASH_ACR_LATENCY_0WS 0x00000000U
sahilmgandhi 18:6a4db94011d3 7259 #define FLASH_ACR_LATENCY_1WS 0x00000001U
sahilmgandhi 18:6a4db94011d3 7260 #define FLASH_ACR_LATENCY_2WS 0x00000002U
sahilmgandhi 18:6a4db94011d3 7261 #define FLASH_ACR_LATENCY_3WS 0x00000003U
sahilmgandhi 18:6a4db94011d3 7262 #define FLASH_ACR_LATENCY_4WS 0x00000004U
sahilmgandhi 18:6a4db94011d3 7263 #define FLASH_ACR_LATENCY_5WS 0x00000005U
sahilmgandhi 18:6a4db94011d3 7264 #define FLASH_ACR_LATENCY_6WS 0x00000006U
sahilmgandhi 18:6a4db94011d3 7265 #define FLASH_ACR_LATENCY_7WS 0x00000007U
sahilmgandhi 18:6a4db94011d3 7266
sahilmgandhi 18:6a4db94011d3 7267 #define FLASH_ACR_LATENCY_8WS 0x00000008U
sahilmgandhi 18:6a4db94011d3 7268 #define FLASH_ACR_LATENCY_9WS 0x00000009U
sahilmgandhi 18:6a4db94011d3 7269 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
sahilmgandhi 18:6a4db94011d3 7270 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
sahilmgandhi 18:6a4db94011d3 7271 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
sahilmgandhi 18:6a4db94011d3 7272 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
sahilmgandhi 18:6a4db94011d3 7273 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
sahilmgandhi 18:6a4db94011d3 7274 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
sahilmgandhi 18:6a4db94011d3 7275 #define FLASH_ACR_PRFTEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7276 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7277 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
sahilmgandhi 18:6a4db94011d3 7278 #define FLASH_ACR_ICEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7279 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7280 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
sahilmgandhi 18:6a4db94011d3 7281 #define FLASH_ACR_DCEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7282 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7283 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
sahilmgandhi 18:6a4db94011d3 7284 #define FLASH_ACR_ICRST_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7285 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7286 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
sahilmgandhi 18:6a4db94011d3 7287 #define FLASH_ACR_DCRST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7288 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7289 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
sahilmgandhi 18:6a4db94011d3 7290 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7291 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
sahilmgandhi 18:6a4db94011d3 7292 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
sahilmgandhi 18:6a4db94011d3 7293 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7294 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
sahilmgandhi 18:6a4db94011d3 7295 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
sahilmgandhi 18:6a4db94011d3 7296
sahilmgandhi 18:6a4db94011d3 7297 /******************* Bits definition for FLASH_SR register ******************/
sahilmgandhi 18:6a4db94011d3 7298 #define FLASH_SR_EOP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7299 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7300 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
sahilmgandhi 18:6a4db94011d3 7301 #define FLASH_SR_SOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7302 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7303 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
sahilmgandhi 18:6a4db94011d3 7304 #define FLASH_SR_WRPERR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7305 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7306 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
sahilmgandhi 18:6a4db94011d3 7307 #define FLASH_SR_PGAERR_Pos (5U)
sahilmgandhi 18:6a4db94011d3 7308 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7309 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
sahilmgandhi 18:6a4db94011d3 7310 #define FLASH_SR_PGPERR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7311 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7312 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
sahilmgandhi 18:6a4db94011d3 7313 #define FLASH_SR_PGSERR_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7314 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7315 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
sahilmgandhi 18:6a4db94011d3 7316 #define FLASH_SR_BSY_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7317 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7318 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
sahilmgandhi 18:6a4db94011d3 7319
sahilmgandhi 18:6a4db94011d3 7320 /******************* Bits definition for FLASH_CR register ******************/
sahilmgandhi 18:6a4db94011d3 7321 #define FLASH_CR_PG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7322 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7323 #define FLASH_CR_PG FLASH_CR_PG_Msk
sahilmgandhi 18:6a4db94011d3 7324 #define FLASH_CR_SER_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7325 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7326 #define FLASH_CR_SER FLASH_CR_SER_Msk
sahilmgandhi 18:6a4db94011d3 7327 #define FLASH_CR_MER_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7328 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7329 #define FLASH_CR_MER FLASH_CR_MER_Msk
sahilmgandhi 18:6a4db94011d3 7330 #define FLASH_CR_MER1 FLASH_CR_MER
sahilmgandhi 18:6a4db94011d3 7331 #define FLASH_CR_SNB_Pos (3U)
sahilmgandhi 18:6a4db94011d3 7332 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
sahilmgandhi 18:6a4db94011d3 7333 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
sahilmgandhi 18:6a4db94011d3 7334 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7335 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7336 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7337 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7338 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7339 #define FLASH_CR_PSIZE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7340 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 7341 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
sahilmgandhi 18:6a4db94011d3 7342 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7343 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7344 #define FLASH_CR_MER2_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7345 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7346 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
sahilmgandhi 18:6a4db94011d3 7347 #define FLASH_CR_STRT_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7348 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7349 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
sahilmgandhi 18:6a4db94011d3 7350 #define FLASH_CR_EOPIE_Pos (24U)
sahilmgandhi 18:6a4db94011d3 7351 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 7352 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
sahilmgandhi 18:6a4db94011d3 7353 #define FLASH_CR_LOCK_Pos (31U)
sahilmgandhi 18:6a4db94011d3 7354 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 7355 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
sahilmgandhi 18:6a4db94011d3 7356
sahilmgandhi 18:6a4db94011d3 7357 /******************* Bits definition for FLASH_OPTCR register ***************/
sahilmgandhi 18:6a4db94011d3 7358 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7359 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7360 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
sahilmgandhi 18:6a4db94011d3 7361 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7362 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7363 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
sahilmgandhi 18:6a4db94011d3 7364
sahilmgandhi 18:6a4db94011d3 7365 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
sahilmgandhi 18:6a4db94011d3 7366 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
sahilmgandhi 18:6a4db94011d3 7367 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7368 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 7369 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
sahilmgandhi 18:6a4db94011d3 7370 #define FLASH_OPTCR_BFB2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7371 #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7372 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
sahilmgandhi 18:6a4db94011d3 7373 #define FLASH_OPTCR_WDG_SW_Pos (5U)
sahilmgandhi 18:6a4db94011d3 7374 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7375 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
sahilmgandhi 18:6a4db94011d3 7376 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7377 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7378 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
sahilmgandhi 18:6a4db94011d3 7379 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
sahilmgandhi 18:6a4db94011d3 7380 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7381 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
sahilmgandhi 18:6a4db94011d3 7382 #define FLASH_OPTCR_RDP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7383 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 7384 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
sahilmgandhi 18:6a4db94011d3 7385 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7386 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7387 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7388 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7389 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7390 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7391 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7392 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7393 #define FLASH_OPTCR_nWRP_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7394 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
sahilmgandhi 18:6a4db94011d3 7395 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
sahilmgandhi 18:6a4db94011d3 7396 #define FLASH_OPTCR_nWRP_0 0x00010000U
sahilmgandhi 18:6a4db94011d3 7397 #define FLASH_OPTCR_nWRP_1 0x00020000U
sahilmgandhi 18:6a4db94011d3 7398 #define FLASH_OPTCR_nWRP_2 0x00040000U
sahilmgandhi 18:6a4db94011d3 7399 #define FLASH_OPTCR_nWRP_3 0x00080000U
sahilmgandhi 18:6a4db94011d3 7400 #define FLASH_OPTCR_nWRP_4 0x00100000U
sahilmgandhi 18:6a4db94011d3 7401 #define FLASH_OPTCR_nWRP_5 0x00200000U
sahilmgandhi 18:6a4db94011d3 7402 #define FLASH_OPTCR_nWRP_6 0x00400000U
sahilmgandhi 18:6a4db94011d3 7403 #define FLASH_OPTCR_nWRP_7 0x00800000U
sahilmgandhi 18:6a4db94011d3 7404 #define FLASH_OPTCR_nWRP_8 0x01000000U
sahilmgandhi 18:6a4db94011d3 7405 #define FLASH_OPTCR_nWRP_9 0x02000000U
sahilmgandhi 18:6a4db94011d3 7406 #define FLASH_OPTCR_nWRP_10 0x04000000U
sahilmgandhi 18:6a4db94011d3 7407 #define FLASH_OPTCR_nWRP_11 0x08000000U
sahilmgandhi 18:6a4db94011d3 7408 #define FLASH_OPTCR_DB1M_Pos (30U)
sahilmgandhi 18:6a4db94011d3 7409 #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 7410 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
sahilmgandhi 18:6a4db94011d3 7411 #define FLASH_OPTCR_SPRMOD_Pos (31U)
sahilmgandhi 18:6a4db94011d3 7412 #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 7413 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
sahilmgandhi 18:6a4db94011d3 7414
sahilmgandhi 18:6a4db94011d3 7415 /****************** Bits definition for FLASH_OPTCR1 register ***************/
sahilmgandhi 18:6a4db94011d3 7416 #define FLASH_OPTCR1_nWRP_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7417 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
sahilmgandhi 18:6a4db94011d3 7418 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
sahilmgandhi 18:6a4db94011d3 7419 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7420 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7421 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7422 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7423 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7424 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7425 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7426 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 7427 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 7428 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 7429 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 7430 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 7431
sahilmgandhi 18:6a4db94011d3 7432 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7433 /* */
sahilmgandhi 18:6a4db94011d3 7434 /* Flexible Memory Controller */
sahilmgandhi 18:6a4db94011d3 7435 /* */
sahilmgandhi 18:6a4db94011d3 7436 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 7437 /****************** Bit definition for FMC_BCR1 register *******************/
sahilmgandhi 18:6a4db94011d3 7438 #define FMC_BCR1_MBKEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7439 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7440 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 7441 #define FMC_BCR1_MUXEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7442 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7443 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
sahilmgandhi 18:6a4db94011d3 7444
sahilmgandhi 18:6a4db94011d3 7445 #define FMC_BCR1_MTYP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7446 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 7447 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
sahilmgandhi 18:6a4db94011d3 7448 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7449 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7450
sahilmgandhi 18:6a4db94011d3 7451 #define FMC_BCR1_MWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7452 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 7453 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
sahilmgandhi 18:6a4db94011d3 7454 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7455 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7456
sahilmgandhi 18:6a4db94011d3 7457 #define FMC_BCR1_FACCEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7458 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7459 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
sahilmgandhi 18:6a4db94011d3 7460 #define FMC_BCR1_BURSTEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7461 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7462 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
sahilmgandhi 18:6a4db94011d3 7463 #define FMC_BCR1_WAITPOL_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7464 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7465 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
sahilmgandhi 18:6a4db94011d3 7466 #define FMC_BCR1_WRAPMOD_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7467 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7468 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
sahilmgandhi 18:6a4db94011d3 7469 #define FMC_BCR1_WAITCFG_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7470 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7471 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
sahilmgandhi 18:6a4db94011d3 7472 #define FMC_BCR1_WREN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7473 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7474 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
sahilmgandhi 18:6a4db94011d3 7475 #define FMC_BCR1_WAITEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7476 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7477 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
sahilmgandhi 18:6a4db94011d3 7478 #define FMC_BCR1_EXTMOD_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7479 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7480 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
sahilmgandhi 18:6a4db94011d3 7481 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7482 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7483 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
sahilmgandhi 18:6a4db94011d3 7484 #define FMC_BCR1_CPSIZE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7485 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
sahilmgandhi 18:6a4db94011d3 7486 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
sahilmgandhi 18:6a4db94011d3 7487 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7488 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7489 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7490 #define FMC_BCR1_CBURSTRW_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7491 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7492 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
sahilmgandhi 18:6a4db94011d3 7493 #define FMC_BCR1_CCLKEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7494 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7495 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
sahilmgandhi 18:6a4db94011d3 7496
sahilmgandhi 18:6a4db94011d3 7497 /****************** Bit definition for FMC_BCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 7498 #define FMC_BCR2_MBKEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7499 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7500 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 7501 #define FMC_BCR2_MUXEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7502 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7503 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
sahilmgandhi 18:6a4db94011d3 7504
sahilmgandhi 18:6a4db94011d3 7505 #define FMC_BCR2_MTYP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7506 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 7507 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
sahilmgandhi 18:6a4db94011d3 7508 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7509 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7510
sahilmgandhi 18:6a4db94011d3 7511 #define FMC_BCR2_MWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7512 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 7513 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
sahilmgandhi 18:6a4db94011d3 7514 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7515 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7516
sahilmgandhi 18:6a4db94011d3 7517 #define FMC_BCR2_FACCEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7518 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7519 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
sahilmgandhi 18:6a4db94011d3 7520 #define FMC_BCR2_BURSTEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7521 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7522 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
sahilmgandhi 18:6a4db94011d3 7523 #define FMC_BCR2_WAITPOL_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7524 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7525 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
sahilmgandhi 18:6a4db94011d3 7526 #define FMC_BCR2_WRAPMOD_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7527 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7528 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
sahilmgandhi 18:6a4db94011d3 7529 #define FMC_BCR2_WAITCFG_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7530 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7531 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
sahilmgandhi 18:6a4db94011d3 7532 #define FMC_BCR2_WREN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7533 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7534 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
sahilmgandhi 18:6a4db94011d3 7535 #define FMC_BCR2_WAITEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7536 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7537 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
sahilmgandhi 18:6a4db94011d3 7538 #define FMC_BCR2_EXTMOD_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7539 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7540 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
sahilmgandhi 18:6a4db94011d3 7541 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7542 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7543 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
sahilmgandhi 18:6a4db94011d3 7544 #define FMC_BCR2_CPSIZE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7545 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
sahilmgandhi 18:6a4db94011d3 7546 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
sahilmgandhi 18:6a4db94011d3 7547 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7548 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7549 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7550 #define FMC_BCR2_CBURSTRW_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7551 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7552 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
sahilmgandhi 18:6a4db94011d3 7553
sahilmgandhi 18:6a4db94011d3 7554 /****************** Bit definition for FMC_BCR3 register *******************/
sahilmgandhi 18:6a4db94011d3 7555 #define FMC_BCR3_MBKEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7556 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7557 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 7558 #define FMC_BCR3_MUXEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7559 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7560 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
sahilmgandhi 18:6a4db94011d3 7561
sahilmgandhi 18:6a4db94011d3 7562 #define FMC_BCR3_MTYP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7563 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 7564 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
sahilmgandhi 18:6a4db94011d3 7565 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7566 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7567
sahilmgandhi 18:6a4db94011d3 7568 #define FMC_BCR3_MWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7569 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 7570 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
sahilmgandhi 18:6a4db94011d3 7571 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7572 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7573
sahilmgandhi 18:6a4db94011d3 7574 #define FMC_BCR3_FACCEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7575 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7576 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
sahilmgandhi 18:6a4db94011d3 7577 #define FMC_BCR3_BURSTEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7578 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7579 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
sahilmgandhi 18:6a4db94011d3 7580 #define FMC_BCR3_WAITPOL_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7581 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7582 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
sahilmgandhi 18:6a4db94011d3 7583 #define FMC_BCR3_WRAPMOD_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7584 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7585 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
sahilmgandhi 18:6a4db94011d3 7586 #define FMC_BCR3_WAITCFG_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7587 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7588 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
sahilmgandhi 18:6a4db94011d3 7589 #define FMC_BCR3_WREN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7590 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7591 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
sahilmgandhi 18:6a4db94011d3 7592 #define FMC_BCR3_WAITEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7593 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7594 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
sahilmgandhi 18:6a4db94011d3 7595 #define FMC_BCR3_EXTMOD_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7596 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7597 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
sahilmgandhi 18:6a4db94011d3 7598 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7599 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7600 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
sahilmgandhi 18:6a4db94011d3 7601 #define FMC_BCR3_CPSIZE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7602 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
sahilmgandhi 18:6a4db94011d3 7603 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
sahilmgandhi 18:6a4db94011d3 7604 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7605 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7606 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7607 #define FMC_BCR3_CBURSTRW_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7608 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7609 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
sahilmgandhi 18:6a4db94011d3 7610
sahilmgandhi 18:6a4db94011d3 7611 /****************** Bit definition for FMC_BCR4 register *******************/
sahilmgandhi 18:6a4db94011d3 7612 #define FMC_BCR4_MBKEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7613 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7614 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 7615 #define FMC_BCR4_MUXEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 7616 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7617 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
sahilmgandhi 18:6a4db94011d3 7618
sahilmgandhi 18:6a4db94011d3 7619 #define FMC_BCR4_MTYP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 7620 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 7621 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
sahilmgandhi 18:6a4db94011d3 7622 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7623 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7624
sahilmgandhi 18:6a4db94011d3 7625 #define FMC_BCR4_MWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7626 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 7627 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
sahilmgandhi 18:6a4db94011d3 7628 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7629 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7630
sahilmgandhi 18:6a4db94011d3 7631 #define FMC_BCR4_FACCEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 7632 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7633 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
sahilmgandhi 18:6a4db94011d3 7634 #define FMC_BCR4_BURSTEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7635 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7636 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
sahilmgandhi 18:6a4db94011d3 7637 #define FMC_BCR4_WAITPOL_Pos (9U)
sahilmgandhi 18:6a4db94011d3 7638 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7639 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
sahilmgandhi 18:6a4db94011d3 7640 #define FMC_BCR4_WRAPMOD_Pos (10U)
sahilmgandhi 18:6a4db94011d3 7641 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7642 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
sahilmgandhi 18:6a4db94011d3 7643 #define FMC_BCR4_WAITCFG_Pos (11U)
sahilmgandhi 18:6a4db94011d3 7644 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7645 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
sahilmgandhi 18:6a4db94011d3 7646 #define FMC_BCR4_WREN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 7647 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7648 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
sahilmgandhi 18:6a4db94011d3 7649 #define FMC_BCR4_WAITEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 7650 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7651 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
sahilmgandhi 18:6a4db94011d3 7652 #define FMC_BCR4_EXTMOD_Pos (14U)
sahilmgandhi 18:6a4db94011d3 7653 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7654 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
sahilmgandhi 18:6a4db94011d3 7655 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
sahilmgandhi 18:6a4db94011d3 7656 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7657 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
sahilmgandhi 18:6a4db94011d3 7658 #define FMC_BCR4_CPSIZE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7659 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
sahilmgandhi 18:6a4db94011d3 7660 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
sahilmgandhi 18:6a4db94011d3 7661 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7662 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7663 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7664 #define FMC_BCR4_CBURSTRW_Pos (19U)
sahilmgandhi 18:6a4db94011d3 7665 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7666 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
sahilmgandhi 18:6a4db94011d3 7667
sahilmgandhi 18:6a4db94011d3 7668 /****************** Bit definition for FMC_BTR1 register ******************/
sahilmgandhi 18:6a4db94011d3 7669 #define FMC_BTR1_ADDSET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7670 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7671 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 7672 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7673 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7674 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7675 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7676
sahilmgandhi 18:6a4db94011d3 7677 #define FMC_BTR1_ADDHLD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7678 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 7679 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 7680 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7681 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7682 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7683 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7684
sahilmgandhi 18:6a4db94011d3 7685 #define FMC_BTR1_DATAST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7686 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 7687 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 7688 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7689 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7690 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7691 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7692 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7693 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7694 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7695 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7696
sahilmgandhi 18:6a4db94011d3 7697 #define FMC_BTR1_BUSTURN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7698 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 7699 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
sahilmgandhi 18:6a4db94011d3 7700 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7701 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7702 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7703 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7704
sahilmgandhi 18:6a4db94011d3 7705 #define FMC_BTR1_CLKDIV_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7706 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 7707 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
sahilmgandhi 18:6a4db94011d3 7708 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7709 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7710 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7711 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 7712
sahilmgandhi 18:6a4db94011d3 7713 #define FMC_BTR1_DATLAT_Pos (24U)
sahilmgandhi 18:6a4db94011d3 7714 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 7715 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
sahilmgandhi 18:6a4db94011d3 7716 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 7717 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 7718 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 7719 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 7720
sahilmgandhi 18:6a4db94011d3 7721 #define FMC_BTR1_ACCMOD_Pos (28U)
sahilmgandhi 18:6a4db94011d3 7722 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 7723 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 7724 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 7725 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 7726
sahilmgandhi 18:6a4db94011d3 7727 /****************** Bit definition for FMC_BTR2 register *******************/
sahilmgandhi 18:6a4db94011d3 7728 #define FMC_BTR2_ADDSET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7729 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7730 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 7731 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7732 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7733 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7734 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7735
sahilmgandhi 18:6a4db94011d3 7736 #define FMC_BTR2_ADDHLD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7737 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 7738 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 7739 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7740 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7741 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7742 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7743
sahilmgandhi 18:6a4db94011d3 7744 #define FMC_BTR2_DATAST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7745 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 7746 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 7747 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7748 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7749 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7750 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7751 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7752 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7753 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7754 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7755
sahilmgandhi 18:6a4db94011d3 7756 #define FMC_BTR2_BUSTURN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7757 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 7758 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
sahilmgandhi 18:6a4db94011d3 7759 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7760 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7761 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7762 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7763
sahilmgandhi 18:6a4db94011d3 7764 #define FMC_BTR2_CLKDIV_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7765 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 7766 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
sahilmgandhi 18:6a4db94011d3 7767 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7768 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7769 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7770 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 7771
sahilmgandhi 18:6a4db94011d3 7772 #define FMC_BTR2_DATLAT_Pos (24U)
sahilmgandhi 18:6a4db94011d3 7773 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 7774 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
sahilmgandhi 18:6a4db94011d3 7775 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 7776 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 7777 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 7778 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 7779
sahilmgandhi 18:6a4db94011d3 7780 #define FMC_BTR2_ACCMOD_Pos (28U)
sahilmgandhi 18:6a4db94011d3 7781 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 7782 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 7783 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 7784 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 7785
sahilmgandhi 18:6a4db94011d3 7786 /******************* Bit definition for FMC_BTR3 register *******************/
sahilmgandhi 18:6a4db94011d3 7787 #define FMC_BTR3_ADDSET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7788 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7789 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 7790 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7791 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7792 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7793 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7794
sahilmgandhi 18:6a4db94011d3 7795 #define FMC_BTR3_ADDHLD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7796 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 7797 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 7798 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7799 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7800 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7801 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7802
sahilmgandhi 18:6a4db94011d3 7803 #define FMC_BTR3_DATAST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7804 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 7805 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 7806 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7807 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7808 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7809 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7810 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7811 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7812 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7813 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7814
sahilmgandhi 18:6a4db94011d3 7815 #define FMC_BTR3_BUSTURN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7816 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 7817 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
sahilmgandhi 18:6a4db94011d3 7818 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7819 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7820 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7821 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7822
sahilmgandhi 18:6a4db94011d3 7823 #define FMC_BTR3_CLKDIV_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7824 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 7825 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
sahilmgandhi 18:6a4db94011d3 7826 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7827 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7828 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7829 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 7830
sahilmgandhi 18:6a4db94011d3 7831 #define FMC_BTR3_DATLAT_Pos (24U)
sahilmgandhi 18:6a4db94011d3 7832 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 7833 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
sahilmgandhi 18:6a4db94011d3 7834 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 7835 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 7836 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 7837 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 7838
sahilmgandhi 18:6a4db94011d3 7839 #define FMC_BTR3_ACCMOD_Pos (28U)
sahilmgandhi 18:6a4db94011d3 7840 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 7841 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 7842 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 7843 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 7844
sahilmgandhi 18:6a4db94011d3 7845 /****************** Bit definition for FMC_BTR4 register *******************/
sahilmgandhi 18:6a4db94011d3 7846 #define FMC_BTR4_ADDSET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7847 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7848 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 7849 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7850 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7851 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7852 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7853
sahilmgandhi 18:6a4db94011d3 7854 #define FMC_BTR4_ADDHLD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7855 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 7856 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 7857 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7858 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7859 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7860 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7861
sahilmgandhi 18:6a4db94011d3 7862 #define FMC_BTR4_DATAST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7863 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 7864 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 7865 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7866 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7867 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7868 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7869 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7870 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7871 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7872 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7873
sahilmgandhi 18:6a4db94011d3 7874 #define FMC_BTR4_BUSTURN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7875 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 7876 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
sahilmgandhi 18:6a4db94011d3 7877 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7878 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7879 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7880 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7881
sahilmgandhi 18:6a4db94011d3 7882 #define FMC_BTR4_CLKDIV_Pos (20U)
sahilmgandhi 18:6a4db94011d3 7883 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 7884 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
sahilmgandhi 18:6a4db94011d3 7885 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 7886 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 7887 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 7888 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 7889
sahilmgandhi 18:6a4db94011d3 7890 #define FMC_BTR4_DATLAT_Pos (24U)
sahilmgandhi 18:6a4db94011d3 7891 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 7892 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
sahilmgandhi 18:6a4db94011d3 7893 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 7894 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 7895 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 7896 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 7897
sahilmgandhi 18:6a4db94011d3 7898 #define FMC_BTR4_ACCMOD_Pos (28U)
sahilmgandhi 18:6a4db94011d3 7899 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 7900 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 7901 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 7902 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 7903
sahilmgandhi 18:6a4db94011d3 7904 /****************** Bit definition for FMC_BWTR1 register ******************/
sahilmgandhi 18:6a4db94011d3 7905 #define FMC_BWTR1_ADDSET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7906 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7907 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 7908 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7909 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7910 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7911 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7912
sahilmgandhi 18:6a4db94011d3 7913 #define FMC_BWTR1_ADDHLD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7914 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 7915 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 7916 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7917 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7918 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7919 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7920
sahilmgandhi 18:6a4db94011d3 7921 #define FMC_BWTR1_DATAST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7922 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 7923 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 7924 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7925 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7926 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7927 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7928 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7929 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7930 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7931 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7932
sahilmgandhi 18:6a4db94011d3 7933 #define FMC_BWTR1_BUSTURN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7934 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 7935 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
sahilmgandhi 18:6a4db94011d3 7936 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7937 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7938 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7939 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7940
sahilmgandhi 18:6a4db94011d3 7941 #define FMC_BWTR1_ACCMOD_Pos (28U)
sahilmgandhi 18:6a4db94011d3 7942 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 7943 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 7944 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 7945 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 7946
sahilmgandhi 18:6a4db94011d3 7947 /****************** Bit definition for FMC_BWTR2 register ******************/
sahilmgandhi 18:6a4db94011d3 7948 #define FMC_BWTR2_ADDSET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7949 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7950 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 7951 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7952 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7953 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7954 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7955
sahilmgandhi 18:6a4db94011d3 7956 #define FMC_BWTR2_ADDHLD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 7957 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 7958 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 7959 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 7960 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 7961 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 7962 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 7963
sahilmgandhi 18:6a4db94011d3 7964 #define FMC_BWTR2_DATAST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 7965 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 7966 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 7967 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 7968 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 7969 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 7970 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 7971 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 7972 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 7973 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 7974 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 7975
sahilmgandhi 18:6a4db94011d3 7976 #define FMC_BWTR2_BUSTURN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 7977 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 7978 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
sahilmgandhi 18:6a4db94011d3 7979 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 7980 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 7981 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 7982 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 7983
sahilmgandhi 18:6a4db94011d3 7984 #define FMC_BWTR2_ACCMOD_Pos (28U)
sahilmgandhi 18:6a4db94011d3 7985 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 7986 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 7987 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 7988 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 7989
sahilmgandhi 18:6a4db94011d3 7990 /****************** Bit definition for FMC_BWTR3 register ******************/
sahilmgandhi 18:6a4db94011d3 7991 #define FMC_BWTR3_ADDSET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 7992 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 7993 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 7994 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 7995 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 7996 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 7997 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 7998
sahilmgandhi 18:6a4db94011d3 7999 #define FMC_BWTR3_ADDHLD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8000 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 8001 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 8002 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8003 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8004 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8005 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8006
sahilmgandhi 18:6a4db94011d3 8007 #define FMC_BWTR3_DATAST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8008 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8009 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 8010 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8011 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8012 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8013 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8014 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8015 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8016 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8017 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8018
sahilmgandhi 18:6a4db94011d3 8019 #define FMC_BWTR3_BUSTURN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8020 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 8021 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
sahilmgandhi 18:6a4db94011d3 8022 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8023 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8024 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8025 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8026
sahilmgandhi 18:6a4db94011d3 8027 #define FMC_BWTR3_ACCMOD_Pos (28U)
sahilmgandhi 18:6a4db94011d3 8028 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 8029 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 8030 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8031 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8032
sahilmgandhi 18:6a4db94011d3 8033 /****************** Bit definition for FMC_BWTR4 register ******************/
sahilmgandhi 18:6a4db94011d3 8034 #define FMC_BWTR4_ADDSET_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8035 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 8036 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
sahilmgandhi 18:6a4db94011d3 8037 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8038 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8039 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8040 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8041
sahilmgandhi 18:6a4db94011d3 8042 #define FMC_BWTR4_ADDHLD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8043 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 8044 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
sahilmgandhi 18:6a4db94011d3 8045 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8046 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8047 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8048 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8049
sahilmgandhi 18:6a4db94011d3 8050 #define FMC_BWTR4_DATAST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8051 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8052 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
sahilmgandhi 18:6a4db94011d3 8053 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8054 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8055 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8056 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8057 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8058 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8059 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8060 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8061
sahilmgandhi 18:6a4db94011d3 8062 #define FMC_BWTR4_BUSTURN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8063 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 8064 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
sahilmgandhi 18:6a4db94011d3 8065 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8066 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8067 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8068 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8069
sahilmgandhi 18:6a4db94011d3 8070 #define FMC_BWTR4_ACCMOD_Pos (28U)
sahilmgandhi 18:6a4db94011d3 8071 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 8072 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
sahilmgandhi 18:6a4db94011d3 8073 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8074 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8075
sahilmgandhi 18:6a4db94011d3 8076 /****************** Bit definition for FMC_PCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 8077
sahilmgandhi 18:6a4db94011d3 8078 #define FMC_PCR2_PWAITEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 8079 #define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8080 #define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
sahilmgandhi 18:6a4db94011d3 8081 #define FMC_PCR2_PBKEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8082 #define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8083 #define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 8084 #define FMC_PCR2_PTYP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 8085 #define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8086 #define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
sahilmgandhi 18:6a4db94011d3 8087
sahilmgandhi 18:6a4db94011d3 8088 #define FMC_PCR2_PWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8089 #define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 8090 #define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
sahilmgandhi 18:6a4db94011d3 8091 #define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8092 #define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8093
sahilmgandhi 18:6a4db94011d3 8094 #define FMC_PCR2_ECCEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8095 #define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8096 #define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
sahilmgandhi 18:6a4db94011d3 8097
sahilmgandhi 18:6a4db94011d3 8098 #define FMC_PCR2_TCLR_Pos (9U)
sahilmgandhi 18:6a4db94011d3 8099 #define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
sahilmgandhi 18:6a4db94011d3 8100 #define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
sahilmgandhi 18:6a4db94011d3 8101 #define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8102 #define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8103 #define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8104 #define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8105
sahilmgandhi 18:6a4db94011d3 8106 #define FMC_PCR2_TAR_Pos (13U)
sahilmgandhi 18:6a4db94011d3 8107 #define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
sahilmgandhi 18:6a4db94011d3 8108 #define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
sahilmgandhi 18:6a4db94011d3 8109 #define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8110 #define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8111 #define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8112 #define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8113
sahilmgandhi 18:6a4db94011d3 8114 #define FMC_PCR2_ECCPS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 8115 #define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
sahilmgandhi 18:6a4db94011d3 8116 #define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
sahilmgandhi 18:6a4db94011d3 8117 #define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8118 #define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8119 #define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8120
sahilmgandhi 18:6a4db94011d3 8121 /****************** Bit definition for FMC_PCR3 register *******************/
sahilmgandhi 18:6a4db94011d3 8122 #define FMC_PCR3_PWAITEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 8123 #define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8124 #define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
sahilmgandhi 18:6a4db94011d3 8125 #define FMC_PCR3_PBKEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8126 #define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8127 #define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 8128 #define FMC_PCR3_PTYP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 8129 #define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8130 #define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
sahilmgandhi 18:6a4db94011d3 8131
sahilmgandhi 18:6a4db94011d3 8132 #define FMC_PCR3_PWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8133 #define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 8134 #define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
sahilmgandhi 18:6a4db94011d3 8135 #define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8136 #define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8137
sahilmgandhi 18:6a4db94011d3 8138 #define FMC_PCR3_ECCEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8139 #define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8140 #define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
sahilmgandhi 18:6a4db94011d3 8141
sahilmgandhi 18:6a4db94011d3 8142 #define FMC_PCR3_TCLR_Pos (9U)
sahilmgandhi 18:6a4db94011d3 8143 #define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
sahilmgandhi 18:6a4db94011d3 8144 #define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
sahilmgandhi 18:6a4db94011d3 8145 #define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8146 #define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8147 #define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8148 #define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8149
sahilmgandhi 18:6a4db94011d3 8150 #define FMC_PCR3_TAR_Pos (13U)
sahilmgandhi 18:6a4db94011d3 8151 #define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
sahilmgandhi 18:6a4db94011d3 8152 #define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
sahilmgandhi 18:6a4db94011d3 8153 #define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8154 #define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8155 #define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8156 #define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8157
sahilmgandhi 18:6a4db94011d3 8158 #define FMC_PCR3_ECCPS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 8159 #define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
sahilmgandhi 18:6a4db94011d3 8160 #define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
sahilmgandhi 18:6a4db94011d3 8161 #define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8162 #define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8163 #define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8164
sahilmgandhi 18:6a4db94011d3 8165 /****************** Bit definition for FMC_PCR4 register *******************/
sahilmgandhi 18:6a4db94011d3 8166 #define FMC_PCR4_PWAITEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 8167 #define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8168 #define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
sahilmgandhi 18:6a4db94011d3 8169 #define FMC_PCR4_PBKEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8170 #define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8171 #define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
sahilmgandhi 18:6a4db94011d3 8172 #define FMC_PCR4_PTYP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 8173 #define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8174 #define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
sahilmgandhi 18:6a4db94011d3 8175
sahilmgandhi 18:6a4db94011d3 8176 #define FMC_PCR4_PWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8177 #define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 8178 #define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
sahilmgandhi 18:6a4db94011d3 8179 #define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8180 #define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8181
sahilmgandhi 18:6a4db94011d3 8182 #define FMC_PCR4_ECCEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8183 #define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8184 #define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
sahilmgandhi 18:6a4db94011d3 8185
sahilmgandhi 18:6a4db94011d3 8186 #define FMC_PCR4_TCLR_Pos (9U)
sahilmgandhi 18:6a4db94011d3 8187 #define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
sahilmgandhi 18:6a4db94011d3 8188 #define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
sahilmgandhi 18:6a4db94011d3 8189 #define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8190 #define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8191 #define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8192 #define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8193
sahilmgandhi 18:6a4db94011d3 8194 #define FMC_PCR4_TAR_Pos (13U)
sahilmgandhi 18:6a4db94011d3 8195 #define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
sahilmgandhi 18:6a4db94011d3 8196 #define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
sahilmgandhi 18:6a4db94011d3 8197 #define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8198 #define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8199 #define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8200 #define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8201
sahilmgandhi 18:6a4db94011d3 8202 #define FMC_PCR4_ECCPS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 8203 #define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
sahilmgandhi 18:6a4db94011d3 8204 #define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
sahilmgandhi 18:6a4db94011d3 8205 #define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8206 #define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8207 #define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8208
sahilmgandhi 18:6a4db94011d3 8209 /******************* Bit definition for FMC_SR2 register *******************/
sahilmgandhi 18:6a4db94011d3 8210 #define FMC_SR2_IRS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8211 #define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8212 #define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
sahilmgandhi 18:6a4db94011d3 8213 #define FMC_SR2_ILS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 8214 #define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8215 #define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
sahilmgandhi 18:6a4db94011d3 8216 #define FMC_SR2_IFS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8217 #define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8218 #define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
sahilmgandhi 18:6a4db94011d3 8219 #define FMC_SR2_IREN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 8220 #define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8221 #define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8222 #define FMC_SR2_ILEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8223 #define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8224 #define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8225 #define FMC_SR2_IFEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 8226 #define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8227 #define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8228 #define FMC_SR2_FEMPT_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8229 #define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8230 #define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
sahilmgandhi 18:6a4db94011d3 8231
sahilmgandhi 18:6a4db94011d3 8232 /******************* Bit definition for FMC_SR3 register *******************/
sahilmgandhi 18:6a4db94011d3 8233 #define FMC_SR3_IRS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8234 #define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8235 #define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
sahilmgandhi 18:6a4db94011d3 8236 #define FMC_SR3_ILS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 8237 #define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8238 #define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
sahilmgandhi 18:6a4db94011d3 8239 #define FMC_SR3_IFS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8240 #define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8241 #define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
sahilmgandhi 18:6a4db94011d3 8242 #define FMC_SR3_IREN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 8243 #define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8244 #define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8245 #define FMC_SR3_ILEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8246 #define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8247 #define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8248 #define FMC_SR3_IFEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 8249 #define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8250 #define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8251 #define FMC_SR3_FEMPT_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8252 #define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8253 #define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
sahilmgandhi 18:6a4db94011d3 8254
sahilmgandhi 18:6a4db94011d3 8255 /******************* Bit definition for FMC_SR4 register *******************/
sahilmgandhi 18:6a4db94011d3 8256 #define FMC_SR4_IRS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8257 #define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8258 #define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
sahilmgandhi 18:6a4db94011d3 8259 #define FMC_SR4_ILS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 8260 #define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8261 #define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
sahilmgandhi 18:6a4db94011d3 8262 #define FMC_SR4_IFS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8263 #define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8264 #define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
sahilmgandhi 18:6a4db94011d3 8265 #define FMC_SR4_IREN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 8266 #define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8267 #define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8268 #define FMC_SR4_ILEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8269 #define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8270 #define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8271 #define FMC_SR4_IFEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 8272 #define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8273 #define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
sahilmgandhi 18:6a4db94011d3 8274 #define FMC_SR4_FEMPT_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8275 #define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8276 #define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
sahilmgandhi 18:6a4db94011d3 8277
sahilmgandhi 18:6a4db94011d3 8278 /****************** Bit definition for FMC_PMEM2 register ******************/
sahilmgandhi 18:6a4db94011d3 8279 #define FMC_PMEM2_MEMSET2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8280 #define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 8281 #define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
sahilmgandhi 18:6a4db94011d3 8282 #define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8283 #define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8284 #define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8285 #define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8286 #define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8287 #define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8288 #define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8289 #define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8290
sahilmgandhi 18:6a4db94011d3 8291 #define FMC_PMEM2_MEMWAIT2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8292 #define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8293 #define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
sahilmgandhi 18:6a4db94011d3 8294 #define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8295 #define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8296 #define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8297 #define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8298 #define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8299 #define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8300 #define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8301 #define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8302
sahilmgandhi 18:6a4db94011d3 8303 #define FMC_PMEM2_MEMHOLD2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8304 #define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 8305 #define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
sahilmgandhi 18:6a4db94011d3 8306 #define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8307 #define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8308 #define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8309 #define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8310 #define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8311 #define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8312 #define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8313 #define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 8314
sahilmgandhi 18:6a4db94011d3 8315 #define FMC_PMEM2_MEMHIZ2_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8316 #define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 8317 #define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 8318 #define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8319 #define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8320 #define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8321 #define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 8322 #define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8323 #define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8324 #define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 8325 #define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 8326
sahilmgandhi 18:6a4db94011d3 8327 /****************** Bit definition for FMC_PMEM3 register ******************/
sahilmgandhi 18:6a4db94011d3 8328 #define FMC_PMEM3_MEMSET3_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8329 #define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 8330 #define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
sahilmgandhi 18:6a4db94011d3 8331 #define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8332 #define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8333 #define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8334 #define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8335 #define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8336 #define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8337 #define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8338 #define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8339
sahilmgandhi 18:6a4db94011d3 8340 #define FMC_PMEM3_MEMWAIT3_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8341 #define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8342 #define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
sahilmgandhi 18:6a4db94011d3 8343 #define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8344 #define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8345 #define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8346 #define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8347 #define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8348 #define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8349 #define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8350 #define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8351
sahilmgandhi 18:6a4db94011d3 8352 #define FMC_PMEM3_MEMHOLD3_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8353 #define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 8354 #define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
sahilmgandhi 18:6a4db94011d3 8355 #define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8356 #define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8357 #define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8358 #define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8359 #define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8360 #define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8361 #define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8362 #define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 8363
sahilmgandhi 18:6a4db94011d3 8364 #define FMC_PMEM3_MEMHIZ3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8365 #define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 8366 #define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 8367 #define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8368 #define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8369 #define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8370 #define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 8371 #define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8372 #define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8373 #define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 8374 #define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 8375
sahilmgandhi 18:6a4db94011d3 8376 /****************** Bit definition for FMC_PMEM4 register ******************/
sahilmgandhi 18:6a4db94011d3 8377 #define FMC_PMEM4_MEMSET4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8378 #define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 8379 #define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
sahilmgandhi 18:6a4db94011d3 8380 #define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8381 #define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8382 #define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8383 #define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8384 #define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8385 #define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8386 #define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8387 #define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8388
sahilmgandhi 18:6a4db94011d3 8389 #define FMC_PMEM4_MEMWAIT4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8390 #define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8391 #define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
sahilmgandhi 18:6a4db94011d3 8392 #define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8393 #define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8394 #define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8395 #define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8396 #define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8397 #define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8398 #define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8399 #define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8400
sahilmgandhi 18:6a4db94011d3 8401 #define FMC_PMEM4_MEMHOLD4_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8402 #define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 8403 #define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
sahilmgandhi 18:6a4db94011d3 8404 #define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8405 #define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8406 #define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8407 #define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8408 #define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8409 #define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8410 #define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8411 #define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 8412
sahilmgandhi 18:6a4db94011d3 8413 #define FMC_PMEM4_MEMHIZ4_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8414 #define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 8415 #define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 8416 #define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8417 #define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8418 #define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8419 #define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 8420 #define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8421 #define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8422 #define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 8423 #define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 8424
sahilmgandhi 18:6a4db94011d3 8425 /****************** Bit definition for FMC_PATT2 register ******************/
sahilmgandhi 18:6a4db94011d3 8426 #define FMC_PATT2_ATTSET2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8427 #define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 8428 #define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
sahilmgandhi 18:6a4db94011d3 8429 #define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8430 #define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8431 #define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8432 #define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8433 #define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8434 #define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8435 #define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8436 #define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8437
sahilmgandhi 18:6a4db94011d3 8438 #define FMC_PATT2_ATTWAIT2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8439 #define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8440 #define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
sahilmgandhi 18:6a4db94011d3 8441 #define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8442 #define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8443 #define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8444 #define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8445 #define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8446 #define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8447 #define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8448 #define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8449
sahilmgandhi 18:6a4db94011d3 8450 #define FMC_PATT2_ATTHOLD2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8451 #define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 8452 #define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
sahilmgandhi 18:6a4db94011d3 8453 #define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8454 #define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8455 #define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8456 #define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8457 #define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8458 #define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8459 #define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8460 #define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 8461
sahilmgandhi 18:6a4db94011d3 8462 #define FMC_PATT2_ATTHIZ2_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8463 #define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 8464 #define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 8465 #define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8466 #define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8467 #define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8468 #define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 8469 #define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8470 #define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8471 #define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 8472 #define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 8473
sahilmgandhi 18:6a4db94011d3 8474 /****************** Bit definition for FMC_PATT3 register ******************/
sahilmgandhi 18:6a4db94011d3 8475 #define FMC_PATT3_ATTSET3_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8476 #define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 8477 #define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
sahilmgandhi 18:6a4db94011d3 8478 #define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8479 #define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8480 #define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8481 #define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8482 #define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8483 #define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8484 #define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8485 #define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8486
sahilmgandhi 18:6a4db94011d3 8487 #define FMC_PATT3_ATTWAIT3_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8488 #define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8489 #define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
sahilmgandhi 18:6a4db94011d3 8490 #define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8491 #define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8492 #define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8493 #define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8494 #define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8495 #define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8496 #define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8497 #define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8498
sahilmgandhi 18:6a4db94011d3 8499 #define FMC_PATT3_ATTHOLD3_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8500 #define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 8501 #define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
sahilmgandhi 18:6a4db94011d3 8502 #define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8503 #define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8504 #define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8505 #define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8506 #define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8507 #define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8508 #define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8509 #define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 8510
sahilmgandhi 18:6a4db94011d3 8511 #define FMC_PATT3_ATTHIZ3_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8512 #define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 8513 #define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 8514 #define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8515 #define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8516 #define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8517 #define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 8518 #define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8519 #define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8520 #define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 8521 #define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 8522
sahilmgandhi 18:6a4db94011d3 8523 /****************** Bit definition for FMC_PATT4 register ******************/
sahilmgandhi 18:6a4db94011d3 8524 #define FMC_PATT4_ATTSET4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8525 #define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 8526 #define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
sahilmgandhi 18:6a4db94011d3 8527 #define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8528 #define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8529 #define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8530 #define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8531 #define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8532 #define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8533 #define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8534 #define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8535
sahilmgandhi 18:6a4db94011d3 8536 #define FMC_PATT4_ATTWAIT4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8537 #define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8538 #define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
sahilmgandhi 18:6a4db94011d3 8539 #define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8540 #define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8541 #define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8542 #define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8543 #define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8544 #define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8545 #define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8546 #define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8547
sahilmgandhi 18:6a4db94011d3 8548 #define FMC_PATT4_ATTHOLD4_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8549 #define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 8550 #define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
sahilmgandhi 18:6a4db94011d3 8551 #define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8552 #define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8553 #define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8554 #define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8555 #define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8556 #define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8557 #define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8558 #define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 8559
sahilmgandhi 18:6a4db94011d3 8560 #define FMC_PATT4_ATTHIZ4_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8561 #define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 8562 #define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 8563 #define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8564 #define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8565 #define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8566 #define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 8567 #define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8568 #define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8569 #define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 8570 #define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 8571
sahilmgandhi 18:6a4db94011d3 8572 /****************** Bit definition for FMC_PIO4 register *******************/
sahilmgandhi 18:6a4db94011d3 8573 #define FMC_PIO4_IOSET4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8574 #define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 8575 #define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
sahilmgandhi 18:6a4db94011d3 8576 #define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8577 #define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8578 #define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8579 #define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8580 #define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8581 #define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8582 #define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8583 #define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8584
sahilmgandhi 18:6a4db94011d3 8585 #define FMC_PIO4_IOWAIT4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8586 #define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 8587 #define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
sahilmgandhi 18:6a4db94011d3 8588 #define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8589 #define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8590 #define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8591 #define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8592 #define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8593 #define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8594 #define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8595 #define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8596
sahilmgandhi 18:6a4db94011d3 8597 #define FMC_PIO4_IOHOLD4_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8598 #define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 8599 #define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
sahilmgandhi 18:6a4db94011d3 8600 #define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8601 #define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8602 #define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8603 #define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8604 #define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8605 #define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8606 #define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8607 #define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 8608
sahilmgandhi 18:6a4db94011d3 8609 #define FMC_PIO4_IOHIZ4_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8610 #define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 8611 #define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
sahilmgandhi 18:6a4db94011d3 8612 #define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8613 #define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8614 #define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8615 #define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 8616 #define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8617 #define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8618 #define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 8619 #define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 8620
sahilmgandhi 18:6a4db94011d3 8621
sahilmgandhi 18:6a4db94011d3 8622 /****************** Bit definition for FMC_ECCR2 register ******************/
sahilmgandhi 18:6a4db94011d3 8623 #define FMC_ECCR2_ECC2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8624 #define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 8625 #define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
sahilmgandhi 18:6a4db94011d3 8626
sahilmgandhi 18:6a4db94011d3 8627 /****************** Bit definition for FMC_ECCR3 register ******************/
sahilmgandhi 18:6a4db94011d3 8628 #define FMC_ECCR3_ECC3_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8629 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 8630 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
sahilmgandhi 18:6a4db94011d3 8631
sahilmgandhi 18:6a4db94011d3 8632 /****************** Bit definition for FMC_SDCR1 register ******************/
sahilmgandhi 18:6a4db94011d3 8633 #define FMC_SDCR1_NC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8634 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 8635 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
sahilmgandhi 18:6a4db94011d3 8636 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8637 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8638
sahilmgandhi 18:6a4db94011d3 8639 #define FMC_SDCR1_NR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8640 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 8641 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
sahilmgandhi 18:6a4db94011d3 8642 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8643 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8644
sahilmgandhi 18:6a4db94011d3 8645 #define FMC_SDCR1_MWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8646 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 8647 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
sahilmgandhi 18:6a4db94011d3 8648 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8649 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8650
sahilmgandhi 18:6a4db94011d3 8651 #define FMC_SDCR1_NB_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8652 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8653 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
sahilmgandhi 18:6a4db94011d3 8654
sahilmgandhi 18:6a4db94011d3 8655 #define FMC_SDCR1_CAS_Pos (7U)
sahilmgandhi 18:6a4db94011d3 8656 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
sahilmgandhi 18:6a4db94011d3 8657 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
sahilmgandhi 18:6a4db94011d3 8658 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8659 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8660
sahilmgandhi 18:6a4db94011d3 8661 #define FMC_SDCR1_WP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 8662 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8663 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
sahilmgandhi 18:6a4db94011d3 8664
sahilmgandhi 18:6a4db94011d3 8665 #define FMC_SDCR1_SDCLK_Pos (10U)
sahilmgandhi 18:6a4db94011d3 8666 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 8667 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
sahilmgandhi 18:6a4db94011d3 8668 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8669 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8670
sahilmgandhi 18:6a4db94011d3 8671 #define FMC_SDCR1_RBURST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 8672 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8673 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
sahilmgandhi 18:6a4db94011d3 8674
sahilmgandhi 18:6a4db94011d3 8675 #define FMC_SDCR1_RPIPE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 8676 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
sahilmgandhi 18:6a4db94011d3 8677 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
sahilmgandhi 18:6a4db94011d3 8678 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8679 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8680
sahilmgandhi 18:6a4db94011d3 8681 /****************** Bit definition for FMC_SDCR2 register ******************/
sahilmgandhi 18:6a4db94011d3 8682 #define FMC_SDCR2_NC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8683 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 8684 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
sahilmgandhi 18:6a4db94011d3 8685 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8686 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8687
sahilmgandhi 18:6a4db94011d3 8688 #define FMC_SDCR2_NR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8689 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 8690 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
sahilmgandhi 18:6a4db94011d3 8691 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8692 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8693
sahilmgandhi 18:6a4db94011d3 8694 #define FMC_SDCR2_MWID_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8695 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 8696 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
sahilmgandhi 18:6a4db94011d3 8697 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8698 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8699
sahilmgandhi 18:6a4db94011d3 8700 #define FMC_SDCR2_NB_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8701 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8702 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
sahilmgandhi 18:6a4db94011d3 8703
sahilmgandhi 18:6a4db94011d3 8704 #define FMC_SDCR2_CAS_Pos (7U)
sahilmgandhi 18:6a4db94011d3 8705 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
sahilmgandhi 18:6a4db94011d3 8706 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
sahilmgandhi 18:6a4db94011d3 8707 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8708 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8709
sahilmgandhi 18:6a4db94011d3 8710 #define FMC_SDCR2_WP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 8711 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8712 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
sahilmgandhi 18:6a4db94011d3 8713
sahilmgandhi 18:6a4db94011d3 8714 #define FMC_SDCR2_SDCLK_Pos (10U)
sahilmgandhi 18:6a4db94011d3 8715 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 8716 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
sahilmgandhi 18:6a4db94011d3 8717 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8718 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8719
sahilmgandhi 18:6a4db94011d3 8720 #define FMC_SDCR2_RBURST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 8721 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8722 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
sahilmgandhi 18:6a4db94011d3 8723
sahilmgandhi 18:6a4db94011d3 8724 #define FMC_SDCR2_RPIPE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 8725 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
sahilmgandhi 18:6a4db94011d3 8726 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
sahilmgandhi 18:6a4db94011d3 8727 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8728 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8729
sahilmgandhi 18:6a4db94011d3 8730 /****************** Bit definition for FMC_SDTR1 register ******************/
sahilmgandhi 18:6a4db94011d3 8731 #define FMC_SDTR1_TMRD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8732 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 8733 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
sahilmgandhi 18:6a4db94011d3 8734 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8735 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8736 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8737 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8738
sahilmgandhi 18:6a4db94011d3 8739 #define FMC_SDTR1_TXSR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8740 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 8741 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
sahilmgandhi 18:6a4db94011d3 8742 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8743 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8744 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8745 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8746
sahilmgandhi 18:6a4db94011d3 8747 #define FMC_SDTR1_TRAS_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8748 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 8749 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
sahilmgandhi 18:6a4db94011d3 8750 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8751 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8752 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8753 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8754
sahilmgandhi 18:6a4db94011d3 8755 #define FMC_SDTR1_TRC_Pos (12U)
sahilmgandhi 18:6a4db94011d3 8756 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 8757 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
sahilmgandhi 18:6a4db94011d3 8758 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8759 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8760 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8761
sahilmgandhi 18:6a4db94011d3 8762 #define FMC_SDTR1_TWR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8763 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 8764 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
sahilmgandhi 18:6a4db94011d3 8765 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8766 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8767 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8768
sahilmgandhi 18:6a4db94011d3 8769 #define FMC_SDTR1_TRP_Pos (20U)
sahilmgandhi 18:6a4db94011d3 8770 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 8771 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
sahilmgandhi 18:6a4db94011d3 8772 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8773 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8774 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8775
sahilmgandhi 18:6a4db94011d3 8776 #define FMC_SDTR1_TRCD_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8777 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 8778 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
sahilmgandhi 18:6a4db94011d3 8779 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8780 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8781 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8782
sahilmgandhi 18:6a4db94011d3 8783 /****************** Bit definition for FMC_SDTR2 register ******************/
sahilmgandhi 18:6a4db94011d3 8784 #define FMC_SDTR2_TMRD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8785 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 8786 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
sahilmgandhi 18:6a4db94011d3 8787 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8788 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8789 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8790 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8791
sahilmgandhi 18:6a4db94011d3 8792 #define FMC_SDTR2_TXSR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8793 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 8794 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
sahilmgandhi 18:6a4db94011d3 8795 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8796 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8797 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8798 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8799
sahilmgandhi 18:6a4db94011d3 8800 #define FMC_SDTR2_TRAS_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8801 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 8802 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
sahilmgandhi 18:6a4db94011d3 8803 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8804 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8805 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8806 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8807
sahilmgandhi 18:6a4db94011d3 8808 #define FMC_SDTR2_TRC_Pos (12U)
sahilmgandhi 18:6a4db94011d3 8809 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 8810 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
sahilmgandhi 18:6a4db94011d3 8811 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8812 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8813 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8814
sahilmgandhi 18:6a4db94011d3 8815 #define FMC_SDTR2_TWR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8816 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 8817 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
sahilmgandhi 18:6a4db94011d3 8818 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8819 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8820 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8821
sahilmgandhi 18:6a4db94011d3 8822 #define FMC_SDTR2_TRP_Pos (20U)
sahilmgandhi 18:6a4db94011d3 8823 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 8824 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
sahilmgandhi 18:6a4db94011d3 8825 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8826 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8827 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8828
sahilmgandhi 18:6a4db94011d3 8829 #define FMC_SDTR2_TRCD_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8830 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 8831 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
sahilmgandhi 18:6a4db94011d3 8832 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8833 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8834 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8835
sahilmgandhi 18:6a4db94011d3 8836 /****************** Bit definition for FMC_SDCMR register ******************/
sahilmgandhi 18:6a4db94011d3 8837 #define FMC_SDCMR_MODE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8838 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 8839 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
sahilmgandhi 18:6a4db94011d3 8840 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8841 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8842 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8843
sahilmgandhi 18:6a4db94011d3 8844 #define FMC_SDCMR_CTB2_Pos (3U)
sahilmgandhi 18:6a4db94011d3 8845 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8846 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
sahilmgandhi 18:6a4db94011d3 8847
sahilmgandhi 18:6a4db94011d3 8848 #define FMC_SDCMR_CTB1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8849 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8850 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
sahilmgandhi 18:6a4db94011d3 8851
sahilmgandhi 18:6a4db94011d3 8852 #define FMC_SDCMR_NRFS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 8853 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
sahilmgandhi 18:6a4db94011d3 8854 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
sahilmgandhi 18:6a4db94011d3 8855 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8856 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8857 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8858 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8859
sahilmgandhi 18:6a4db94011d3 8860 #define FMC_SDCMR_MRD_Pos (9U)
sahilmgandhi 18:6a4db94011d3 8861 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
sahilmgandhi 18:6a4db94011d3 8862 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
sahilmgandhi 18:6a4db94011d3 8863
sahilmgandhi 18:6a4db94011d3 8864 /****************** Bit definition for FMC_SDRTR register ******************/
sahilmgandhi 18:6a4db94011d3 8865 #define FMC_SDRTR_CRE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8866 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8867 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
sahilmgandhi 18:6a4db94011d3 8868
sahilmgandhi 18:6a4db94011d3 8869 #define FMC_SDRTR_COUNT_Pos (1U)
sahilmgandhi 18:6a4db94011d3 8870 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
sahilmgandhi 18:6a4db94011d3 8871 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
sahilmgandhi 18:6a4db94011d3 8872
sahilmgandhi 18:6a4db94011d3 8873 #define FMC_SDRTR_REIE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 8874 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8875 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
sahilmgandhi 18:6a4db94011d3 8876
sahilmgandhi 18:6a4db94011d3 8877 /****************** Bit definition for FMC_SDSR register ******************/
sahilmgandhi 18:6a4db94011d3 8878 #define FMC_SDSR_RE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8879 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8880 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
sahilmgandhi 18:6a4db94011d3 8881
sahilmgandhi 18:6a4db94011d3 8882 #define FMC_SDSR_MODES1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 8883 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
sahilmgandhi 18:6a4db94011d3 8884 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
sahilmgandhi 18:6a4db94011d3 8885 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8886 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8887
sahilmgandhi 18:6a4db94011d3 8888 #define FMC_SDSR_MODES2_Pos (3U)
sahilmgandhi 18:6a4db94011d3 8889 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 8890 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
sahilmgandhi 18:6a4db94011d3 8891 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8892 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8893 #define FMC_SDSR_BUSY_Pos (5U)
sahilmgandhi 18:6a4db94011d3 8894 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8895 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
sahilmgandhi 18:6a4db94011d3 8896
sahilmgandhi 18:6a4db94011d3 8897 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 8898 /* */
sahilmgandhi 18:6a4db94011d3 8899 /* General Purpose I/O */
sahilmgandhi 18:6a4db94011d3 8900 /* */
sahilmgandhi 18:6a4db94011d3 8901 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 8902 /****************** Bits definition for GPIO_MODER register *****************/
sahilmgandhi 18:6a4db94011d3 8903 #define GPIO_MODER_MODE0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8904 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 8905 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
sahilmgandhi 18:6a4db94011d3 8906 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8907 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8908 #define GPIO_MODER_MODE1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8909 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 8910 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
sahilmgandhi 18:6a4db94011d3 8911 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8912 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8913 #define GPIO_MODER_MODE2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8914 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 8915 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
sahilmgandhi 18:6a4db94011d3 8916 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8917 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 8918 #define GPIO_MODER_MODE3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 8919 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 8920 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
sahilmgandhi 18:6a4db94011d3 8921 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 8922 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 8923 #define GPIO_MODER_MODE4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 8924 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 8925 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
sahilmgandhi 18:6a4db94011d3 8926 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 8927 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 8928 #define GPIO_MODER_MODE5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 8929 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 8930 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
sahilmgandhi 18:6a4db94011d3 8931 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 8932 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 8933 #define GPIO_MODER_MODE6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 8934 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 8935 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
sahilmgandhi 18:6a4db94011d3 8936 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 8937 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 8938 #define GPIO_MODER_MODE7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 8939 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 8940 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
sahilmgandhi 18:6a4db94011d3 8941 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 8942 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 8943 #define GPIO_MODER_MODE8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 8944 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 8945 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
sahilmgandhi 18:6a4db94011d3 8946 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 8947 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 8948 #define GPIO_MODER_MODE9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 8949 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 8950 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
sahilmgandhi 18:6a4db94011d3 8951 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 8952 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 8953 #define GPIO_MODER_MODE10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 8954 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 8955 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
sahilmgandhi 18:6a4db94011d3 8956 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 8957 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 8958 #define GPIO_MODER_MODE11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 8959 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 8960 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
sahilmgandhi 18:6a4db94011d3 8961 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 8962 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 8963 #define GPIO_MODER_MODE12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 8964 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 8965 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
sahilmgandhi 18:6a4db94011d3 8966 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 8967 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 8968 #define GPIO_MODER_MODE13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 8969 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 8970 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
sahilmgandhi 18:6a4db94011d3 8971 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 8972 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 8973 #define GPIO_MODER_MODE14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 8974 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 8975 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
sahilmgandhi 18:6a4db94011d3 8976 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 8977 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 8978 #define GPIO_MODER_MODE15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 8979 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 8980 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
sahilmgandhi 18:6a4db94011d3 8981 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 8982 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 8983
sahilmgandhi 18:6a4db94011d3 8984 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 8985 #define GPIO_MODER_MODER0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 8986 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 8987 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
sahilmgandhi 18:6a4db94011d3 8988 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 8989 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 8990 #define GPIO_MODER_MODER1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 8991 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 8992 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
sahilmgandhi 18:6a4db94011d3 8993 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 8994 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 8995 #define GPIO_MODER_MODER2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 8996 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 8997 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
sahilmgandhi 18:6a4db94011d3 8998 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 8999 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9000 #define GPIO_MODER_MODER3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9001 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 9002 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
sahilmgandhi 18:6a4db94011d3 9003 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9004 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9005 #define GPIO_MODER_MODER4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9006 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 9007 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
sahilmgandhi 18:6a4db94011d3 9008 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9009 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9010 #define GPIO_MODER_MODER5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9011 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 9012 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
sahilmgandhi 18:6a4db94011d3 9013 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9014 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9015 #define GPIO_MODER_MODER6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9016 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 9017 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
sahilmgandhi 18:6a4db94011d3 9018 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9019 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9020 #define GPIO_MODER_MODER7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9021 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 9022 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
sahilmgandhi 18:6a4db94011d3 9023 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9024 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9025 #define GPIO_MODER_MODER8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 9026 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 9027 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
sahilmgandhi 18:6a4db94011d3 9028 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 9029 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 9030 #define GPIO_MODER_MODER9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 9031 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 9032 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
sahilmgandhi 18:6a4db94011d3 9033 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 9034 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 9035 #define GPIO_MODER_MODER10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 9036 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 9037 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
sahilmgandhi 18:6a4db94011d3 9038 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 9039 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 9040 #define GPIO_MODER_MODER11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 9041 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 9042 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
sahilmgandhi 18:6a4db94011d3 9043 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 9044 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 9045 #define GPIO_MODER_MODER12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 9046 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 9047 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
sahilmgandhi 18:6a4db94011d3 9048 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 9049 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 9050 #define GPIO_MODER_MODER13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 9051 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 9052 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
sahilmgandhi 18:6a4db94011d3 9053 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 9054 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 9055 #define GPIO_MODER_MODER14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 9056 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 9057 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
sahilmgandhi 18:6a4db94011d3 9058 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 9059 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 9060 #define GPIO_MODER_MODER15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 9061 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 9062 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
sahilmgandhi 18:6a4db94011d3 9063 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 9064 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 9065
sahilmgandhi 18:6a4db94011d3 9066 /****************** Bits definition for GPIO_OTYPER register ****************/
sahilmgandhi 18:6a4db94011d3 9067 #define GPIO_OTYPER_OT0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9068 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9069 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
sahilmgandhi 18:6a4db94011d3 9070 #define GPIO_OTYPER_OT1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 9071 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9072 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
sahilmgandhi 18:6a4db94011d3 9073 #define GPIO_OTYPER_OT2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9074 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9075 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
sahilmgandhi 18:6a4db94011d3 9076 #define GPIO_OTYPER_OT3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 9077 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9078 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
sahilmgandhi 18:6a4db94011d3 9079 #define GPIO_OTYPER_OT4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9080 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9081 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
sahilmgandhi 18:6a4db94011d3 9082 #define GPIO_OTYPER_OT5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 9083 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9084 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
sahilmgandhi 18:6a4db94011d3 9085 #define GPIO_OTYPER_OT6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9086 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9087 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
sahilmgandhi 18:6a4db94011d3 9088 #define GPIO_OTYPER_OT7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 9089 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9090 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
sahilmgandhi 18:6a4db94011d3 9091 #define GPIO_OTYPER_OT8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9092 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9093 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
sahilmgandhi 18:6a4db94011d3 9094 #define GPIO_OTYPER_OT9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 9095 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9096 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
sahilmgandhi 18:6a4db94011d3 9097 #define GPIO_OTYPER_OT10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9098 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9099 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
sahilmgandhi 18:6a4db94011d3 9100 #define GPIO_OTYPER_OT11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 9101 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9102 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
sahilmgandhi 18:6a4db94011d3 9103 #define GPIO_OTYPER_OT12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9104 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9105 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
sahilmgandhi 18:6a4db94011d3 9106 #define GPIO_OTYPER_OT13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 9107 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9108 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
sahilmgandhi 18:6a4db94011d3 9109 #define GPIO_OTYPER_OT14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9110 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9111 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
sahilmgandhi 18:6a4db94011d3 9112 #define GPIO_OTYPER_OT15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 9113 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9114 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
sahilmgandhi 18:6a4db94011d3 9115
sahilmgandhi 18:6a4db94011d3 9116 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 9117 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
sahilmgandhi 18:6a4db94011d3 9118 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
sahilmgandhi 18:6a4db94011d3 9119 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
sahilmgandhi 18:6a4db94011d3 9120 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
sahilmgandhi 18:6a4db94011d3 9121 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
sahilmgandhi 18:6a4db94011d3 9122 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
sahilmgandhi 18:6a4db94011d3 9123 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
sahilmgandhi 18:6a4db94011d3 9124 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
sahilmgandhi 18:6a4db94011d3 9125 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
sahilmgandhi 18:6a4db94011d3 9126 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
sahilmgandhi 18:6a4db94011d3 9127 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
sahilmgandhi 18:6a4db94011d3 9128 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
sahilmgandhi 18:6a4db94011d3 9129 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
sahilmgandhi 18:6a4db94011d3 9130 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
sahilmgandhi 18:6a4db94011d3 9131 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
sahilmgandhi 18:6a4db94011d3 9132 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
sahilmgandhi 18:6a4db94011d3 9133
sahilmgandhi 18:6a4db94011d3 9134 /****************** Bits definition for GPIO_OSPEEDR register ***************/
sahilmgandhi 18:6a4db94011d3 9135 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9136 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 9137 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
sahilmgandhi 18:6a4db94011d3 9138 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9139 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9140 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9141 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 9142 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
sahilmgandhi 18:6a4db94011d3 9143 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9144 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9145 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9146 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 9147 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
sahilmgandhi 18:6a4db94011d3 9148 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9149 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9150 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9151 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 9152 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
sahilmgandhi 18:6a4db94011d3 9153 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9154 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9155 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9156 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 9157 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
sahilmgandhi 18:6a4db94011d3 9158 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9159 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9160 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9161 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 9162 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
sahilmgandhi 18:6a4db94011d3 9163 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9164 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9165 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9166 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 9167 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
sahilmgandhi 18:6a4db94011d3 9168 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9169 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9170 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9171 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 9172 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
sahilmgandhi 18:6a4db94011d3 9173 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9174 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9175 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 9176 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 9177 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
sahilmgandhi 18:6a4db94011d3 9178 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 9179 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 9180 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 9181 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 9182 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
sahilmgandhi 18:6a4db94011d3 9183 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 9184 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 9185 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 9186 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 9187 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
sahilmgandhi 18:6a4db94011d3 9188 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 9189 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 9190 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 9191 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 9192 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
sahilmgandhi 18:6a4db94011d3 9193 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 9194 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 9195 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 9196 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 9197 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
sahilmgandhi 18:6a4db94011d3 9198 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 9199 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 9200 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 9201 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 9202 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
sahilmgandhi 18:6a4db94011d3 9203 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 9204 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 9205 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 9206 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 9207 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
sahilmgandhi 18:6a4db94011d3 9208 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 9209 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 9210 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 9211 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 9212 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
sahilmgandhi 18:6a4db94011d3 9213 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 9214 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 9215
sahilmgandhi 18:6a4db94011d3 9216 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 9217 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
sahilmgandhi 18:6a4db94011d3 9218 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
sahilmgandhi 18:6a4db94011d3 9219 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
sahilmgandhi 18:6a4db94011d3 9220 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
sahilmgandhi 18:6a4db94011d3 9221 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
sahilmgandhi 18:6a4db94011d3 9222 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
sahilmgandhi 18:6a4db94011d3 9223 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
sahilmgandhi 18:6a4db94011d3 9224 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
sahilmgandhi 18:6a4db94011d3 9225 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
sahilmgandhi 18:6a4db94011d3 9226 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
sahilmgandhi 18:6a4db94011d3 9227 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
sahilmgandhi 18:6a4db94011d3 9228 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
sahilmgandhi 18:6a4db94011d3 9229 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
sahilmgandhi 18:6a4db94011d3 9230 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
sahilmgandhi 18:6a4db94011d3 9231 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
sahilmgandhi 18:6a4db94011d3 9232 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
sahilmgandhi 18:6a4db94011d3 9233 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
sahilmgandhi 18:6a4db94011d3 9234 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
sahilmgandhi 18:6a4db94011d3 9235 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
sahilmgandhi 18:6a4db94011d3 9236 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
sahilmgandhi 18:6a4db94011d3 9237 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
sahilmgandhi 18:6a4db94011d3 9238 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
sahilmgandhi 18:6a4db94011d3 9239 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
sahilmgandhi 18:6a4db94011d3 9240 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
sahilmgandhi 18:6a4db94011d3 9241 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
sahilmgandhi 18:6a4db94011d3 9242 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
sahilmgandhi 18:6a4db94011d3 9243 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
sahilmgandhi 18:6a4db94011d3 9244 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
sahilmgandhi 18:6a4db94011d3 9245 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
sahilmgandhi 18:6a4db94011d3 9246 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
sahilmgandhi 18:6a4db94011d3 9247 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
sahilmgandhi 18:6a4db94011d3 9248 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
sahilmgandhi 18:6a4db94011d3 9249 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
sahilmgandhi 18:6a4db94011d3 9250 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
sahilmgandhi 18:6a4db94011d3 9251 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
sahilmgandhi 18:6a4db94011d3 9252 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
sahilmgandhi 18:6a4db94011d3 9253 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
sahilmgandhi 18:6a4db94011d3 9254 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
sahilmgandhi 18:6a4db94011d3 9255 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
sahilmgandhi 18:6a4db94011d3 9256 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
sahilmgandhi 18:6a4db94011d3 9257 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
sahilmgandhi 18:6a4db94011d3 9258 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
sahilmgandhi 18:6a4db94011d3 9259 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
sahilmgandhi 18:6a4db94011d3 9260 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
sahilmgandhi 18:6a4db94011d3 9261 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
sahilmgandhi 18:6a4db94011d3 9262 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
sahilmgandhi 18:6a4db94011d3 9263 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
sahilmgandhi 18:6a4db94011d3 9264 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
sahilmgandhi 18:6a4db94011d3 9265
sahilmgandhi 18:6a4db94011d3 9266 /****************** Bits definition for GPIO_PUPDR register *****************/
sahilmgandhi 18:6a4db94011d3 9267 #define GPIO_PUPDR_PUPD0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9268 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 9269 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
sahilmgandhi 18:6a4db94011d3 9270 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9271 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9272 #define GPIO_PUPDR_PUPD1_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9273 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 9274 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
sahilmgandhi 18:6a4db94011d3 9275 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9276 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9277 #define GPIO_PUPDR_PUPD2_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9278 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 9279 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
sahilmgandhi 18:6a4db94011d3 9280 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9281 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9282 #define GPIO_PUPDR_PUPD3_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9283 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 9284 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
sahilmgandhi 18:6a4db94011d3 9285 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9286 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9287 #define GPIO_PUPDR_PUPD4_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9288 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 9289 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
sahilmgandhi 18:6a4db94011d3 9290 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9291 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9292 #define GPIO_PUPDR_PUPD5_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9293 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 9294 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
sahilmgandhi 18:6a4db94011d3 9295 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9296 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9297 #define GPIO_PUPDR_PUPD6_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9298 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 9299 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
sahilmgandhi 18:6a4db94011d3 9300 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9301 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9302 #define GPIO_PUPDR_PUPD7_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9303 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 9304 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
sahilmgandhi 18:6a4db94011d3 9305 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9306 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9307 #define GPIO_PUPDR_PUPD8_Pos (16U)
sahilmgandhi 18:6a4db94011d3 9308 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 9309 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
sahilmgandhi 18:6a4db94011d3 9310 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 9311 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 9312 #define GPIO_PUPDR_PUPD9_Pos (18U)
sahilmgandhi 18:6a4db94011d3 9313 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 9314 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
sahilmgandhi 18:6a4db94011d3 9315 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 9316 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 9317 #define GPIO_PUPDR_PUPD10_Pos (20U)
sahilmgandhi 18:6a4db94011d3 9318 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 9319 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
sahilmgandhi 18:6a4db94011d3 9320 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 9321 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 9322 #define GPIO_PUPDR_PUPD11_Pos (22U)
sahilmgandhi 18:6a4db94011d3 9323 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 9324 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
sahilmgandhi 18:6a4db94011d3 9325 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 9326 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 9327 #define GPIO_PUPDR_PUPD12_Pos (24U)
sahilmgandhi 18:6a4db94011d3 9328 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 9329 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
sahilmgandhi 18:6a4db94011d3 9330 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 9331 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 9332 #define GPIO_PUPDR_PUPD13_Pos (26U)
sahilmgandhi 18:6a4db94011d3 9333 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
sahilmgandhi 18:6a4db94011d3 9334 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
sahilmgandhi 18:6a4db94011d3 9335 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 9336 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 9337 #define GPIO_PUPDR_PUPD14_Pos (28U)
sahilmgandhi 18:6a4db94011d3 9338 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 9339 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
sahilmgandhi 18:6a4db94011d3 9340 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 9341 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 9342 #define GPIO_PUPDR_PUPD15_Pos (30U)
sahilmgandhi 18:6a4db94011d3 9343 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 9344 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
sahilmgandhi 18:6a4db94011d3 9345 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 9346 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 9347
sahilmgandhi 18:6a4db94011d3 9348 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 9349 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
sahilmgandhi 18:6a4db94011d3 9350 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
sahilmgandhi 18:6a4db94011d3 9351 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
sahilmgandhi 18:6a4db94011d3 9352 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
sahilmgandhi 18:6a4db94011d3 9353 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
sahilmgandhi 18:6a4db94011d3 9354 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
sahilmgandhi 18:6a4db94011d3 9355 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
sahilmgandhi 18:6a4db94011d3 9356 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
sahilmgandhi 18:6a4db94011d3 9357 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
sahilmgandhi 18:6a4db94011d3 9358 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
sahilmgandhi 18:6a4db94011d3 9359 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
sahilmgandhi 18:6a4db94011d3 9360 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
sahilmgandhi 18:6a4db94011d3 9361 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
sahilmgandhi 18:6a4db94011d3 9362 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
sahilmgandhi 18:6a4db94011d3 9363 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
sahilmgandhi 18:6a4db94011d3 9364 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
sahilmgandhi 18:6a4db94011d3 9365 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
sahilmgandhi 18:6a4db94011d3 9366 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
sahilmgandhi 18:6a4db94011d3 9367 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
sahilmgandhi 18:6a4db94011d3 9368 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
sahilmgandhi 18:6a4db94011d3 9369 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
sahilmgandhi 18:6a4db94011d3 9370 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
sahilmgandhi 18:6a4db94011d3 9371 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
sahilmgandhi 18:6a4db94011d3 9372 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
sahilmgandhi 18:6a4db94011d3 9373 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
sahilmgandhi 18:6a4db94011d3 9374 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
sahilmgandhi 18:6a4db94011d3 9375 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
sahilmgandhi 18:6a4db94011d3 9376 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
sahilmgandhi 18:6a4db94011d3 9377 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
sahilmgandhi 18:6a4db94011d3 9378 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
sahilmgandhi 18:6a4db94011d3 9379 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
sahilmgandhi 18:6a4db94011d3 9380 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
sahilmgandhi 18:6a4db94011d3 9381 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
sahilmgandhi 18:6a4db94011d3 9382 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
sahilmgandhi 18:6a4db94011d3 9383 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
sahilmgandhi 18:6a4db94011d3 9384 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
sahilmgandhi 18:6a4db94011d3 9385 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
sahilmgandhi 18:6a4db94011d3 9386 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
sahilmgandhi 18:6a4db94011d3 9387 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
sahilmgandhi 18:6a4db94011d3 9388 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
sahilmgandhi 18:6a4db94011d3 9389 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
sahilmgandhi 18:6a4db94011d3 9390 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
sahilmgandhi 18:6a4db94011d3 9391 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
sahilmgandhi 18:6a4db94011d3 9392 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
sahilmgandhi 18:6a4db94011d3 9393 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
sahilmgandhi 18:6a4db94011d3 9394 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
sahilmgandhi 18:6a4db94011d3 9395 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
sahilmgandhi 18:6a4db94011d3 9396 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
sahilmgandhi 18:6a4db94011d3 9397
sahilmgandhi 18:6a4db94011d3 9398 /****************** Bits definition for GPIO_IDR register *******************/
sahilmgandhi 18:6a4db94011d3 9399 #define GPIO_IDR_ID0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9400 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9401 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
sahilmgandhi 18:6a4db94011d3 9402 #define GPIO_IDR_ID1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 9403 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9404 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
sahilmgandhi 18:6a4db94011d3 9405 #define GPIO_IDR_ID2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9406 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9407 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
sahilmgandhi 18:6a4db94011d3 9408 #define GPIO_IDR_ID3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 9409 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9410 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
sahilmgandhi 18:6a4db94011d3 9411 #define GPIO_IDR_ID4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9412 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9413 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
sahilmgandhi 18:6a4db94011d3 9414 #define GPIO_IDR_ID5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 9415 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9416 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
sahilmgandhi 18:6a4db94011d3 9417 #define GPIO_IDR_ID6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9418 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9419 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
sahilmgandhi 18:6a4db94011d3 9420 #define GPIO_IDR_ID7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 9421 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9422 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
sahilmgandhi 18:6a4db94011d3 9423 #define GPIO_IDR_ID8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9424 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9425 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
sahilmgandhi 18:6a4db94011d3 9426 #define GPIO_IDR_ID9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 9427 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9428 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
sahilmgandhi 18:6a4db94011d3 9429 #define GPIO_IDR_ID10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9430 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9431 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
sahilmgandhi 18:6a4db94011d3 9432 #define GPIO_IDR_ID11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 9433 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9434 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
sahilmgandhi 18:6a4db94011d3 9435 #define GPIO_IDR_ID12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9436 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9437 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
sahilmgandhi 18:6a4db94011d3 9438 #define GPIO_IDR_ID13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 9439 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9440 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
sahilmgandhi 18:6a4db94011d3 9441 #define GPIO_IDR_ID14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9442 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9443 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
sahilmgandhi 18:6a4db94011d3 9444 #define GPIO_IDR_ID15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 9445 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9446 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
sahilmgandhi 18:6a4db94011d3 9447
sahilmgandhi 18:6a4db94011d3 9448 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 9449 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
sahilmgandhi 18:6a4db94011d3 9450 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
sahilmgandhi 18:6a4db94011d3 9451 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
sahilmgandhi 18:6a4db94011d3 9452 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
sahilmgandhi 18:6a4db94011d3 9453 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
sahilmgandhi 18:6a4db94011d3 9454 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
sahilmgandhi 18:6a4db94011d3 9455 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
sahilmgandhi 18:6a4db94011d3 9456 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
sahilmgandhi 18:6a4db94011d3 9457 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
sahilmgandhi 18:6a4db94011d3 9458 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
sahilmgandhi 18:6a4db94011d3 9459 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
sahilmgandhi 18:6a4db94011d3 9460 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
sahilmgandhi 18:6a4db94011d3 9461 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
sahilmgandhi 18:6a4db94011d3 9462 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
sahilmgandhi 18:6a4db94011d3 9463 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
sahilmgandhi 18:6a4db94011d3 9464 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
sahilmgandhi 18:6a4db94011d3 9465
sahilmgandhi 18:6a4db94011d3 9466 /****************** Bits definition for GPIO_ODR register *******************/
sahilmgandhi 18:6a4db94011d3 9467 #define GPIO_ODR_OD0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9468 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9469 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
sahilmgandhi 18:6a4db94011d3 9470 #define GPIO_ODR_OD1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 9471 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9472 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
sahilmgandhi 18:6a4db94011d3 9473 #define GPIO_ODR_OD2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9474 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9475 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
sahilmgandhi 18:6a4db94011d3 9476 #define GPIO_ODR_OD3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 9477 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9478 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
sahilmgandhi 18:6a4db94011d3 9479 #define GPIO_ODR_OD4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9480 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9481 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
sahilmgandhi 18:6a4db94011d3 9482 #define GPIO_ODR_OD5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 9483 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9484 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
sahilmgandhi 18:6a4db94011d3 9485 #define GPIO_ODR_OD6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9486 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9487 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
sahilmgandhi 18:6a4db94011d3 9488 #define GPIO_ODR_OD7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 9489 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9490 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
sahilmgandhi 18:6a4db94011d3 9491 #define GPIO_ODR_OD8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9492 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9493 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
sahilmgandhi 18:6a4db94011d3 9494 #define GPIO_ODR_OD9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 9495 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9496 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
sahilmgandhi 18:6a4db94011d3 9497 #define GPIO_ODR_OD10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9498 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9499 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
sahilmgandhi 18:6a4db94011d3 9500 #define GPIO_ODR_OD11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 9501 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9502 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
sahilmgandhi 18:6a4db94011d3 9503 #define GPIO_ODR_OD12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9504 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9505 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
sahilmgandhi 18:6a4db94011d3 9506 #define GPIO_ODR_OD13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 9507 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9508 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
sahilmgandhi 18:6a4db94011d3 9509 #define GPIO_ODR_OD14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9510 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9511 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
sahilmgandhi 18:6a4db94011d3 9512 #define GPIO_ODR_OD15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 9513 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9514 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
sahilmgandhi 18:6a4db94011d3 9515 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 9516 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
sahilmgandhi 18:6a4db94011d3 9517 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
sahilmgandhi 18:6a4db94011d3 9518 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
sahilmgandhi 18:6a4db94011d3 9519 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
sahilmgandhi 18:6a4db94011d3 9520 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
sahilmgandhi 18:6a4db94011d3 9521 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
sahilmgandhi 18:6a4db94011d3 9522 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
sahilmgandhi 18:6a4db94011d3 9523 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
sahilmgandhi 18:6a4db94011d3 9524 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
sahilmgandhi 18:6a4db94011d3 9525 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
sahilmgandhi 18:6a4db94011d3 9526 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
sahilmgandhi 18:6a4db94011d3 9527 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
sahilmgandhi 18:6a4db94011d3 9528 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
sahilmgandhi 18:6a4db94011d3 9529 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
sahilmgandhi 18:6a4db94011d3 9530 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
sahilmgandhi 18:6a4db94011d3 9531 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
sahilmgandhi 18:6a4db94011d3 9532
sahilmgandhi 18:6a4db94011d3 9533 /****************** Bits definition for GPIO_BSRR register ******************/
sahilmgandhi 18:6a4db94011d3 9534 #define GPIO_BSRR_BS0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9535 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9536 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
sahilmgandhi 18:6a4db94011d3 9537 #define GPIO_BSRR_BS1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 9538 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9539 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
sahilmgandhi 18:6a4db94011d3 9540 #define GPIO_BSRR_BS2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9541 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9542 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
sahilmgandhi 18:6a4db94011d3 9543 #define GPIO_BSRR_BS3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 9544 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9545 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
sahilmgandhi 18:6a4db94011d3 9546 #define GPIO_BSRR_BS4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9547 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9548 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
sahilmgandhi 18:6a4db94011d3 9549 #define GPIO_BSRR_BS5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 9550 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9551 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
sahilmgandhi 18:6a4db94011d3 9552 #define GPIO_BSRR_BS6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9553 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9554 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
sahilmgandhi 18:6a4db94011d3 9555 #define GPIO_BSRR_BS7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 9556 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9557 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
sahilmgandhi 18:6a4db94011d3 9558 #define GPIO_BSRR_BS8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9559 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9560 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
sahilmgandhi 18:6a4db94011d3 9561 #define GPIO_BSRR_BS9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 9562 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9563 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
sahilmgandhi 18:6a4db94011d3 9564 #define GPIO_BSRR_BS10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9565 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9566 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
sahilmgandhi 18:6a4db94011d3 9567 #define GPIO_BSRR_BS11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 9568 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9569 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
sahilmgandhi 18:6a4db94011d3 9570 #define GPIO_BSRR_BS12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9571 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9572 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
sahilmgandhi 18:6a4db94011d3 9573 #define GPIO_BSRR_BS13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 9574 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9575 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
sahilmgandhi 18:6a4db94011d3 9576 #define GPIO_BSRR_BS14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9577 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9578 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
sahilmgandhi 18:6a4db94011d3 9579 #define GPIO_BSRR_BS15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 9580 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9581 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
sahilmgandhi 18:6a4db94011d3 9582 #define GPIO_BSRR_BR0_Pos (16U)
sahilmgandhi 18:6a4db94011d3 9583 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 9584 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
sahilmgandhi 18:6a4db94011d3 9585 #define GPIO_BSRR_BR1_Pos (17U)
sahilmgandhi 18:6a4db94011d3 9586 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 9587 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
sahilmgandhi 18:6a4db94011d3 9588 #define GPIO_BSRR_BR2_Pos (18U)
sahilmgandhi 18:6a4db94011d3 9589 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 9590 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
sahilmgandhi 18:6a4db94011d3 9591 #define GPIO_BSRR_BR3_Pos (19U)
sahilmgandhi 18:6a4db94011d3 9592 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 9593 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
sahilmgandhi 18:6a4db94011d3 9594 #define GPIO_BSRR_BR4_Pos (20U)
sahilmgandhi 18:6a4db94011d3 9595 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 9596 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
sahilmgandhi 18:6a4db94011d3 9597 #define GPIO_BSRR_BR5_Pos (21U)
sahilmgandhi 18:6a4db94011d3 9598 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 9599 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
sahilmgandhi 18:6a4db94011d3 9600 #define GPIO_BSRR_BR6_Pos (22U)
sahilmgandhi 18:6a4db94011d3 9601 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 9602 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
sahilmgandhi 18:6a4db94011d3 9603 #define GPIO_BSRR_BR7_Pos (23U)
sahilmgandhi 18:6a4db94011d3 9604 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 9605 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
sahilmgandhi 18:6a4db94011d3 9606 #define GPIO_BSRR_BR8_Pos (24U)
sahilmgandhi 18:6a4db94011d3 9607 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 9608 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
sahilmgandhi 18:6a4db94011d3 9609 #define GPIO_BSRR_BR9_Pos (25U)
sahilmgandhi 18:6a4db94011d3 9610 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 9611 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
sahilmgandhi 18:6a4db94011d3 9612 #define GPIO_BSRR_BR10_Pos (26U)
sahilmgandhi 18:6a4db94011d3 9613 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 9614 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
sahilmgandhi 18:6a4db94011d3 9615 #define GPIO_BSRR_BR11_Pos (27U)
sahilmgandhi 18:6a4db94011d3 9616 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 9617 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
sahilmgandhi 18:6a4db94011d3 9618 #define GPIO_BSRR_BR12_Pos (28U)
sahilmgandhi 18:6a4db94011d3 9619 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 9620 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
sahilmgandhi 18:6a4db94011d3 9621 #define GPIO_BSRR_BR13_Pos (29U)
sahilmgandhi 18:6a4db94011d3 9622 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 9623 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
sahilmgandhi 18:6a4db94011d3 9624 #define GPIO_BSRR_BR14_Pos (30U)
sahilmgandhi 18:6a4db94011d3 9625 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 9626 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
sahilmgandhi 18:6a4db94011d3 9627 #define GPIO_BSRR_BR15_Pos (31U)
sahilmgandhi 18:6a4db94011d3 9628 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 9629 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
sahilmgandhi 18:6a4db94011d3 9630
sahilmgandhi 18:6a4db94011d3 9631 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 9632 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
sahilmgandhi 18:6a4db94011d3 9633 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
sahilmgandhi 18:6a4db94011d3 9634 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
sahilmgandhi 18:6a4db94011d3 9635 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
sahilmgandhi 18:6a4db94011d3 9636 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
sahilmgandhi 18:6a4db94011d3 9637 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
sahilmgandhi 18:6a4db94011d3 9638 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
sahilmgandhi 18:6a4db94011d3 9639 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
sahilmgandhi 18:6a4db94011d3 9640 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
sahilmgandhi 18:6a4db94011d3 9641 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
sahilmgandhi 18:6a4db94011d3 9642 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
sahilmgandhi 18:6a4db94011d3 9643 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
sahilmgandhi 18:6a4db94011d3 9644 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
sahilmgandhi 18:6a4db94011d3 9645 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
sahilmgandhi 18:6a4db94011d3 9646 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
sahilmgandhi 18:6a4db94011d3 9647 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
sahilmgandhi 18:6a4db94011d3 9648 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
sahilmgandhi 18:6a4db94011d3 9649 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
sahilmgandhi 18:6a4db94011d3 9650 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
sahilmgandhi 18:6a4db94011d3 9651 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
sahilmgandhi 18:6a4db94011d3 9652 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
sahilmgandhi 18:6a4db94011d3 9653 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
sahilmgandhi 18:6a4db94011d3 9654 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
sahilmgandhi 18:6a4db94011d3 9655 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
sahilmgandhi 18:6a4db94011d3 9656 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
sahilmgandhi 18:6a4db94011d3 9657 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
sahilmgandhi 18:6a4db94011d3 9658 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
sahilmgandhi 18:6a4db94011d3 9659 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
sahilmgandhi 18:6a4db94011d3 9660 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
sahilmgandhi 18:6a4db94011d3 9661 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
sahilmgandhi 18:6a4db94011d3 9662 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
sahilmgandhi 18:6a4db94011d3 9663 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
sahilmgandhi 18:6a4db94011d3 9664 /****************** Bit definition for GPIO_LCKR register *********************/
sahilmgandhi 18:6a4db94011d3 9665 #define GPIO_LCKR_LCK0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9666 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9667 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
sahilmgandhi 18:6a4db94011d3 9668 #define GPIO_LCKR_LCK1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 9669 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9670 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
sahilmgandhi 18:6a4db94011d3 9671 #define GPIO_LCKR_LCK2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9672 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9673 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
sahilmgandhi 18:6a4db94011d3 9674 #define GPIO_LCKR_LCK3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 9675 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9676 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
sahilmgandhi 18:6a4db94011d3 9677 #define GPIO_LCKR_LCK4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9678 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9679 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
sahilmgandhi 18:6a4db94011d3 9680 #define GPIO_LCKR_LCK5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 9681 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9682 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
sahilmgandhi 18:6a4db94011d3 9683 #define GPIO_LCKR_LCK6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9684 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9685 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
sahilmgandhi 18:6a4db94011d3 9686 #define GPIO_LCKR_LCK7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 9687 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9688 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
sahilmgandhi 18:6a4db94011d3 9689 #define GPIO_LCKR_LCK8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9690 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9691 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
sahilmgandhi 18:6a4db94011d3 9692 #define GPIO_LCKR_LCK9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 9693 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9694 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
sahilmgandhi 18:6a4db94011d3 9695 #define GPIO_LCKR_LCK10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9696 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9697 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
sahilmgandhi 18:6a4db94011d3 9698 #define GPIO_LCKR_LCK11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 9699 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9700 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
sahilmgandhi 18:6a4db94011d3 9701 #define GPIO_LCKR_LCK12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9702 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9703 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
sahilmgandhi 18:6a4db94011d3 9704 #define GPIO_LCKR_LCK13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 9705 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9706 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
sahilmgandhi 18:6a4db94011d3 9707 #define GPIO_LCKR_LCK14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9708 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9709 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
sahilmgandhi 18:6a4db94011d3 9710 #define GPIO_LCKR_LCK15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 9711 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9712 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
sahilmgandhi 18:6a4db94011d3 9713 #define GPIO_LCKR_LCKK_Pos (16U)
sahilmgandhi 18:6a4db94011d3 9714 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 9715 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
sahilmgandhi 18:6a4db94011d3 9716 /****************** Bit definition for GPIO_AFRL register *********************/
sahilmgandhi 18:6a4db94011d3 9717 #define GPIO_AFRL_AFSEL0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9718 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 9719 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
sahilmgandhi 18:6a4db94011d3 9720 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9721 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9722 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9723 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9724 #define GPIO_AFRL_AFSEL1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9725 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 9726 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
sahilmgandhi 18:6a4db94011d3 9727 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9728 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9729 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9730 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9731 #define GPIO_AFRL_AFSEL2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9732 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 9733 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
sahilmgandhi 18:6a4db94011d3 9734 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9735 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9736 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9737 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9738 #define GPIO_AFRL_AFSEL3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9739 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 9740 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
sahilmgandhi 18:6a4db94011d3 9741 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9742 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9743 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9744 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9745 #define GPIO_AFRL_AFSEL4_Pos (16U)
sahilmgandhi 18:6a4db94011d3 9746 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 9747 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
sahilmgandhi 18:6a4db94011d3 9748 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 9749 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 9750 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 9751 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 9752 #define GPIO_AFRL_AFSEL5_Pos (20U)
sahilmgandhi 18:6a4db94011d3 9753 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 9754 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
sahilmgandhi 18:6a4db94011d3 9755 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 9756 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 9757 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 9758 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 9759 #define GPIO_AFRL_AFSEL6_Pos (24U)
sahilmgandhi 18:6a4db94011d3 9760 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 9761 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
sahilmgandhi 18:6a4db94011d3 9762 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 9763 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 9764 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 9765 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 9766 #define GPIO_AFRL_AFSEL7_Pos (28U)
sahilmgandhi 18:6a4db94011d3 9767 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 9768 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
sahilmgandhi 18:6a4db94011d3 9769 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 9770 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 9771 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 9772 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 9773
sahilmgandhi 18:6a4db94011d3 9774 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 9775 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
sahilmgandhi 18:6a4db94011d3 9776 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
sahilmgandhi 18:6a4db94011d3 9777 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
sahilmgandhi 18:6a4db94011d3 9778 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
sahilmgandhi 18:6a4db94011d3 9779 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
sahilmgandhi 18:6a4db94011d3 9780 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
sahilmgandhi 18:6a4db94011d3 9781 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
sahilmgandhi 18:6a4db94011d3 9782 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
sahilmgandhi 18:6a4db94011d3 9783 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
sahilmgandhi 18:6a4db94011d3 9784 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
sahilmgandhi 18:6a4db94011d3 9785 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
sahilmgandhi 18:6a4db94011d3 9786 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
sahilmgandhi 18:6a4db94011d3 9787 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
sahilmgandhi 18:6a4db94011d3 9788 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
sahilmgandhi 18:6a4db94011d3 9789 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
sahilmgandhi 18:6a4db94011d3 9790 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
sahilmgandhi 18:6a4db94011d3 9791 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
sahilmgandhi 18:6a4db94011d3 9792 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
sahilmgandhi 18:6a4db94011d3 9793 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
sahilmgandhi 18:6a4db94011d3 9794 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
sahilmgandhi 18:6a4db94011d3 9795 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
sahilmgandhi 18:6a4db94011d3 9796 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
sahilmgandhi 18:6a4db94011d3 9797 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
sahilmgandhi 18:6a4db94011d3 9798 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
sahilmgandhi 18:6a4db94011d3 9799 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
sahilmgandhi 18:6a4db94011d3 9800 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
sahilmgandhi 18:6a4db94011d3 9801 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
sahilmgandhi 18:6a4db94011d3 9802 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
sahilmgandhi 18:6a4db94011d3 9803 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
sahilmgandhi 18:6a4db94011d3 9804 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
sahilmgandhi 18:6a4db94011d3 9805 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
sahilmgandhi 18:6a4db94011d3 9806 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
sahilmgandhi 18:6a4db94011d3 9807 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
sahilmgandhi 18:6a4db94011d3 9808 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
sahilmgandhi 18:6a4db94011d3 9809 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
sahilmgandhi 18:6a4db94011d3 9810 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
sahilmgandhi 18:6a4db94011d3 9811 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
sahilmgandhi 18:6a4db94011d3 9812 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
sahilmgandhi 18:6a4db94011d3 9813 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
sahilmgandhi 18:6a4db94011d3 9814 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
sahilmgandhi 18:6a4db94011d3 9815
sahilmgandhi 18:6a4db94011d3 9816 /****************** Bit definition for GPIO_AFRH register *********************/
sahilmgandhi 18:6a4db94011d3 9817 #define GPIO_AFRH_AFSEL8_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9818 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 9819 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
sahilmgandhi 18:6a4db94011d3 9820 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9821 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9822 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9823 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9824 #define GPIO_AFRH_AFSEL9_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9825 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 9826 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
sahilmgandhi 18:6a4db94011d3 9827 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9828 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9829 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9830 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9831 #define GPIO_AFRH_AFSEL10_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9832 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 9833 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
sahilmgandhi 18:6a4db94011d3 9834 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9835 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9836 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9837 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9838 #define GPIO_AFRH_AFSEL11_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9839 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 9840 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
sahilmgandhi 18:6a4db94011d3 9841 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9842 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9843 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9844 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9845 #define GPIO_AFRH_AFSEL12_Pos (16U)
sahilmgandhi 18:6a4db94011d3 9846 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 9847 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
sahilmgandhi 18:6a4db94011d3 9848 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 9849 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 9850 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 9851 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 9852 #define GPIO_AFRH_AFSEL13_Pos (20U)
sahilmgandhi 18:6a4db94011d3 9853 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 9854 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
sahilmgandhi 18:6a4db94011d3 9855 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 9856 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 9857 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 9858 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 9859 #define GPIO_AFRH_AFSEL14_Pos (24U)
sahilmgandhi 18:6a4db94011d3 9860 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 9861 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
sahilmgandhi 18:6a4db94011d3 9862 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 9863 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 9864 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 9865 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 9866 #define GPIO_AFRH_AFSEL15_Pos (28U)
sahilmgandhi 18:6a4db94011d3 9867 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
sahilmgandhi 18:6a4db94011d3 9868 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
sahilmgandhi 18:6a4db94011d3 9869 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 9870 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 9871 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 9872 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 9873
sahilmgandhi 18:6a4db94011d3 9874 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 9875 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
sahilmgandhi 18:6a4db94011d3 9876 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
sahilmgandhi 18:6a4db94011d3 9877 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
sahilmgandhi 18:6a4db94011d3 9878 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
sahilmgandhi 18:6a4db94011d3 9879 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
sahilmgandhi 18:6a4db94011d3 9880 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
sahilmgandhi 18:6a4db94011d3 9881 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
sahilmgandhi 18:6a4db94011d3 9882 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
sahilmgandhi 18:6a4db94011d3 9883 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
sahilmgandhi 18:6a4db94011d3 9884 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
sahilmgandhi 18:6a4db94011d3 9885 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
sahilmgandhi 18:6a4db94011d3 9886 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
sahilmgandhi 18:6a4db94011d3 9887 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
sahilmgandhi 18:6a4db94011d3 9888 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
sahilmgandhi 18:6a4db94011d3 9889 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
sahilmgandhi 18:6a4db94011d3 9890 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
sahilmgandhi 18:6a4db94011d3 9891 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
sahilmgandhi 18:6a4db94011d3 9892 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
sahilmgandhi 18:6a4db94011d3 9893 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
sahilmgandhi 18:6a4db94011d3 9894 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
sahilmgandhi 18:6a4db94011d3 9895 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
sahilmgandhi 18:6a4db94011d3 9896 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
sahilmgandhi 18:6a4db94011d3 9897 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
sahilmgandhi 18:6a4db94011d3 9898 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
sahilmgandhi 18:6a4db94011d3 9899 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
sahilmgandhi 18:6a4db94011d3 9900 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
sahilmgandhi 18:6a4db94011d3 9901 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
sahilmgandhi 18:6a4db94011d3 9902 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
sahilmgandhi 18:6a4db94011d3 9903 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
sahilmgandhi 18:6a4db94011d3 9904 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
sahilmgandhi 18:6a4db94011d3 9905 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
sahilmgandhi 18:6a4db94011d3 9906 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
sahilmgandhi 18:6a4db94011d3 9907 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
sahilmgandhi 18:6a4db94011d3 9908 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
sahilmgandhi 18:6a4db94011d3 9909 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
sahilmgandhi 18:6a4db94011d3 9910 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
sahilmgandhi 18:6a4db94011d3 9911 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
sahilmgandhi 18:6a4db94011d3 9912 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
sahilmgandhi 18:6a4db94011d3 9913 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
sahilmgandhi 18:6a4db94011d3 9914 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
sahilmgandhi 18:6a4db94011d3 9915
sahilmgandhi 18:6a4db94011d3 9916 /****************** Bits definition for GPIO_BRR register ******************/
sahilmgandhi 18:6a4db94011d3 9917 #define GPIO_BRR_BR0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 9918 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 9919 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
sahilmgandhi 18:6a4db94011d3 9920 #define GPIO_BRR_BR1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 9921 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 9922 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
sahilmgandhi 18:6a4db94011d3 9923 #define GPIO_BRR_BR2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9924 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9925 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
sahilmgandhi 18:6a4db94011d3 9926 #define GPIO_BRR_BR3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 9927 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9928 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
sahilmgandhi 18:6a4db94011d3 9929 #define GPIO_BRR_BR4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9930 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9931 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
sahilmgandhi 18:6a4db94011d3 9932 #define GPIO_BRR_BR5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 9933 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9934 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
sahilmgandhi 18:6a4db94011d3 9935 #define GPIO_BRR_BR6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9936 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9937 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
sahilmgandhi 18:6a4db94011d3 9938 #define GPIO_BRR_BR7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 9939 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9940 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
sahilmgandhi 18:6a4db94011d3 9941 #define GPIO_BRR_BR8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9942 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9943 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
sahilmgandhi 18:6a4db94011d3 9944 #define GPIO_BRR_BR9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 9945 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9946 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
sahilmgandhi 18:6a4db94011d3 9947 #define GPIO_BRR_BR10_Pos (10U)
sahilmgandhi 18:6a4db94011d3 9948 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9949 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
sahilmgandhi 18:6a4db94011d3 9950 #define GPIO_BRR_BR11_Pos (11U)
sahilmgandhi 18:6a4db94011d3 9951 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9952 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
sahilmgandhi 18:6a4db94011d3 9953 #define GPIO_BRR_BR12_Pos (12U)
sahilmgandhi 18:6a4db94011d3 9954 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 9955 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
sahilmgandhi 18:6a4db94011d3 9956 #define GPIO_BRR_BR13_Pos (13U)
sahilmgandhi 18:6a4db94011d3 9957 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 9958 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
sahilmgandhi 18:6a4db94011d3 9959 #define GPIO_BRR_BR14_Pos (14U)
sahilmgandhi 18:6a4db94011d3 9960 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 9961 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
sahilmgandhi 18:6a4db94011d3 9962 #define GPIO_BRR_BR15_Pos (15U)
sahilmgandhi 18:6a4db94011d3 9963 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 9964 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
sahilmgandhi 18:6a4db94011d3 9965
sahilmgandhi 18:6a4db94011d3 9966
sahilmgandhi 18:6a4db94011d3 9967 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 9968 /* */
sahilmgandhi 18:6a4db94011d3 9969 /* HASH */
sahilmgandhi 18:6a4db94011d3 9970 /* */
sahilmgandhi 18:6a4db94011d3 9971 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 9972 /****************** Bits definition for HASH_CR register ********************/
sahilmgandhi 18:6a4db94011d3 9973 #define HASH_CR_INIT_Pos (2U)
sahilmgandhi 18:6a4db94011d3 9974 #define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 9975 #define HASH_CR_INIT HASH_CR_INIT_Msk
sahilmgandhi 18:6a4db94011d3 9976 #define HASH_CR_DMAE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 9977 #define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 9978 #define HASH_CR_DMAE HASH_CR_DMAE_Msk
sahilmgandhi 18:6a4db94011d3 9979 #define HASH_CR_DATATYPE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 9980 #define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 9981 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
sahilmgandhi 18:6a4db94011d3 9982 #define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 9983 #define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 9984 #define HASH_CR_MODE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 9985 #define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 9986 #define HASH_CR_MODE HASH_CR_MODE_Msk
sahilmgandhi 18:6a4db94011d3 9987 #define HASH_CR_ALGO_Pos (7U)
sahilmgandhi 18:6a4db94011d3 9988 #define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
sahilmgandhi 18:6a4db94011d3 9989 #define HASH_CR_ALGO HASH_CR_ALGO_Msk
sahilmgandhi 18:6a4db94011d3 9990 #define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 9991 #define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 9992 #define HASH_CR_NBW_Pos (8U)
sahilmgandhi 18:6a4db94011d3 9993 #define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 9994 #define HASH_CR_NBW HASH_CR_NBW_Msk
sahilmgandhi 18:6a4db94011d3 9995 #define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 9996 #define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 9997 #define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 9998 #define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 9999 #define HASH_CR_DINNE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 10000 #define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10001 #define HASH_CR_DINNE HASH_CR_DINNE_Msk
sahilmgandhi 18:6a4db94011d3 10002 #define HASH_CR_MDMAT_Pos (13U)
sahilmgandhi 18:6a4db94011d3 10003 #define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 10004 #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
sahilmgandhi 18:6a4db94011d3 10005 #define HASH_CR_LKEY_Pos (16U)
sahilmgandhi 18:6a4db94011d3 10006 #define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 10007 #define HASH_CR_LKEY HASH_CR_LKEY_Msk
sahilmgandhi 18:6a4db94011d3 10008
sahilmgandhi 18:6a4db94011d3 10009 /****************** Bits definition for HASH_STR register *******************/
sahilmgandhi 18:6a4db94011d3 10010 #define HASH_STR_NBLW_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10011 #define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 10012 #define HASH_STR_NBLW HASH_STR_NBLW_Msk
sahilmgandhi 18:6a4db94011d3 10013 #define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10014 #define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10015 #define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10016 #define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10017 #define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10018 #define HASH_STR_DCAL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10019 #define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10020 #define HASH_STR_DCAL HASH_STR_DCAL_Msk
sahilmgandhi 18:6a4db94011d3 10021 /* Aliases for HASH_STR register */
sahilmgandhi 18:6a4db94011d3 10022 #define HASH_STR_NBW HASH_STR_NBLW
sahilmgandhi 18:6a4db94011d3 10023 #define HASH_STR_NBW_0 HASH_STR_NBLW_0
sahilmgandhi 18:6a4db94011d3 10024 #define HASH_STR_NBW_1 HASH_STR_NBLW_1
sahilmgandhi 18:6a4db94011d3 10025 #define HASH_STR_NBW_2 HASH_STR_NBLW_2
sahilmgandhi 18:6a4db94011d3 10026 #define HASH_STR_NBW_3 HASH_STR_NBLW_3
sahilmgandhi 18:6a4db94011d3 10027 #define HASH_STR_NBW_4 HASH_STR_NBLW_4
sahilmgandhi 18:6a4db94011d3 10028
sahilmgandhi 18:6a4db94011d3 10029 /****************** Bits definition for HASH_IMR register *******************/
sahilmgandhi 18:6a4db94011d3 10030 #define HASH_IMR_DINIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10031 #define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10032 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
sahilmgandhi 18:6a4db94011d3 10033 #define HASH_IMR_DCIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10034 #define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10035 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
sahilmgandhi 18:6a4db94011d3 10036 /* Aliases for HASH_IMR register */
sahilmgandhi 18:6a4db94011d3 10037 #define HASH_IMR_DINIM HASH_IMR_DINIE
sahilmgandhi 18:6a4db94011d3 10038 #define HASH_IMR_DCIM HASH_IMR_DCIE
sahilmgandhi 18:6a4db94011d3 10039
sahilmgandhi 18:6a4db94011d3 10040 /****************** Bits definition for HASH_SR register ********************/
sahilmgandhi 18:6a4db94011d3 10041 #define HASH_SR_DINIS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10042 #define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10043 #define HASH_SR_DINIS HASH_SR_DINIS_Msk
sahilmgandhi 18:6a4db94011d3 10044 #define HASH_SR_DCIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10045 #define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10046 #define HASH_SR_DCIS HASH_SR_DCIS_Msk
sahilmgandhi 18:6a4db94011d3 10047 #define HASH_SR_DMAS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10048 #define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10049 #define HASH_SR_DMAS HASH_SR_DMAS_Msk
sahilmgandhi 18:6a4db94011d3 10050 #define HASH_SR_BUSY_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10051 #define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10052 #define HASH_SR_BUSY HASH_SR_BUSY_Msk
sahilmgandhi 18:6a4db94011d3 10053
sahilmgandhi 18:6a4db94011d3 10054 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10055 /* */
sahilmgandhi 18:6a4db94011d3 10056 /* Inter-integrated Circuit Interface */
sahilmgandhi 18:6a4db94011d3 10057 /* */
sahilmgandhi 18:6a4db94011d3 10058 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10059 /******************* Bit definition for I2C_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 10060 #define I2C_CR1_PE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10061 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10062 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
sahilmgandhi 18:6a4db94011d3 10063 #define I2C_CR1_SMBUS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10064 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10065 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
sahilmgandhi 18:6a4db94011d3 10066 #define I2C_CR1_SMBTYPE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10067 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10068 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
sahilmgandhi 18:6a4db94011d3 10069 #define I2C_CR1_ENARP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10070 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10071 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
sahilmgandhi 18:6a4db94011d3 10072 #define I2C_CR1_ENPEC_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10073 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10074 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
sahilmgandhi 18:6a4db94011d3 10075 #define I2C_CR1_ENGC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10076 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10077 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
sahilmgandhi 18:6a4db94011d3 10078 #define I2C_CR1_NOSTRETCH_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10079 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10080 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
sahilmgandhi 18:6a4db94011d3 10081 #define I2C_CR1_START_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10082 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10083 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
sahilmgandhi 18:6a4db94011d3 10084 #define I2C_CR1_STOP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10085 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10086 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
sahilmgandhi 18:6a4db94011d3 10087 #define I2C_CR1_ACK_Pos (10U)
sahilmgandhi 18:6a4db94011d3 10088 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10089 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
sahilmgandhi 18:6a4db94011d3 10090 #define I2C_CR1_POS_Pos (11U)
sahilmgandhi 18:6a4db94011d3 10091 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10092 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
sahilmgandhi 18:6a4db94011d3 10093 #define I2C_CR1_PEC_Pos (12U)
sahilmgandhi 18:6a4db94011d3 10094 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10095 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
sahilmgandhi 18:6a4db94011d3 10096 #define I2C_CR1_ALERT_Pos (13U)
sahilmgandhi 18:6a4db94011d3 10097 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 10098 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
sahilmgandhi 18:6a4db94011d3 10099 #define I2C_CR1_SWRST_Pos (15U)
sahilmgandhi 18:6a4db94011d3 10100 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 10101 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
sahilmgandhi 18:6a4db94011d3 10102
sahilmgandhi 18:6a4db94011d3 10103 /******************* Bit definition for I2C_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 10104 #define I2C_CR2_FREQ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10105 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
sahilmgandhi 18:6a4db94011d3 10106 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
sahilmgandhi 18:6a4db94011d3 10107 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10108 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10109 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10110 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10111 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10112 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10113
sahilmgandhi 18:6a4db94011d3 10114 #define I2C_CR2_ITERREN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10115 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10116 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 10117 #define I2C_CR2_ITEVTEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10118 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10119 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 10120 #define I2C_CR2_ITBUFEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 10121 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10122 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 10123 #define I2C_CR2_DMAEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 10124 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10125 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
sahilmgandhi 18:6a4db94011d3 10126 #define I2C_CR2_LAST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 10127 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10128 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
sahilmgandhi 18:6a4db94011d3 10129
sahilmgandhi 18:6a4db94011d3 10130 /******************* Bit definition for I2C_OAR1 register *******************/
sahilmgandhi 18:6a4db94011d3 10131 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
sahilmgandhi 18:6a4db94011d3 10132 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
sahilmgandhi 18:6a4db94011d3 10133
sahilmgandhi 18:6a4db94011d3 10134 #define I2C_OAR1_ADD0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10135 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10136 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 10137 #define I2C_OAR1_ADD1_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10138 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10139 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 10140 #define I2C_OAR1_ADD2_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10141 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10142 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
sahilmgandhi 18:6a4db94011d3 10143 #define I2C_OAR1_ADD3_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10144 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10145 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
sahilmgandhi 18:6a4db94011d3 10146 #define I2C_OAR1_ADD4_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10147 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10148 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
sahilmgandhi 18:6a4db94011d3 10149 #define I2C_OAR1_ADD5_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10150 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10151 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
sahilmgandhi 18:6a4db94011d3 10152 #define I2C_OAR1_ADD6_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10153 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10154 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
sahilmgandhi 18:6a4db94011d3 10155 #define I2C_OAR1_ADD7_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10156 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10157 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
sahilmgandhi 18:6a4db94011d3 10158 #define I2C_OAR1_ADD8_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10159 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10160 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
sahilmgandhi 18:6a4db94011d3 10161 #define I2C_OAR1_ADD9_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10162 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10163 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
sahilmgandhi 18:6a4db94011d3 10164
sahilmgandhi 18:6a4db94011d3 10165 #define I2C_OAR1_ADDMODE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 10166 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 10167 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
sahilmgandhi 18:6a4db94011d3 10168
sahilmgandhi 18:6a4db94011d3 10169 /******************* Bit definition for I2C_OAR2 register *******************/
sahilmgandhi 18:6a4db94011d3 10170 #define I2C_OAR2_ENDUAL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10171 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10172 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
sahilmgandhi 18:6a4db94011d3 10173 #define I2C_OAR2_ADD2_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10174 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
sahilmgandhi 18:6a4db94011d3 10175 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
sahilmgandhi 18:6a4db94011d3 10176
sahilmgandhi 18:6a4db94011d3 10177 /******************** Bit definition for I2C_DR register ********************/
sahilmgandhi 18:6a4db94011d3 10178 #define I2C_DR_DR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10179 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 10180 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
sahilmgandhi 18:6a4db94011d3 10181
sahilmgandhi 18:6a4db94011d3 10182 /******************* Bit definition for I2C_SR1 register ********************/
sahilmgandhi 18:6a4db94011d3 10183 #define I2C_SR1_SB_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10184 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10185 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
sahilmgandhi 18:6a4db94011d3 10186 #define I2C_SR1_ADDR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10187 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10188 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
sahilmgandhi 18:6a4db94011d3 10189 #define I2C_SR1_BTF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10190 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10191 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
sahilmgandhi 18:6a4db94011d3 10192 #define I2C_SR1_ADD10_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10193 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10194 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
sahilmgandhi 18:6a4db94011d3 10195 #define I2C_SR1_STOPF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10196 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10197 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
sahilmgandhi 18:6a4db94011d3 10198 #define I2C_SR1_RXNE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10199 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10200 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
sahilmgandhi 18:6a4db94011d3 10201 #define I2C_SR1_TXE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10202 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10203 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
sahilmgandhi 18:6a4db94011d3 10204 #define I2C_SR1_BERR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10205 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10206 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
sahilmgandhi 18:6a4db94011d3 10207 #define I2C_SR1_ARLO_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10208 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10209 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
sahilmgandhi 18:6a4db94011d3 10210 #define I2C_SR1_AF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 10211 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10212 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
sahilmgandhi 18:6a4db94011d3 10213 #define I2C_SR1_OVR_Pos (11U)
sahilmgandhi 18:6a4db94011d3 10214 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10215 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
sahilmgandhi 18:6a4db94011d3 10216 #define I2C_SR1_PECERR_Pos (12U)
sahilmgandhi 18:6a4db94011d3 10217 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10218 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
sahilmgandhi 18:6a4db94011d3 10219 #define I2C_SR1_TIMEOUT_Pos (14U)
sahilmgandhi 18:6a4db94011d3 10220 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10221 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
sahilmgandhi 18:6a4db94011d3 10222 #define I2C_SR1_SMBALERT_Pos (15U)
sahilmgandhi 18:6a4db94011d3 10223 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 10224 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
sahilmgandhi 18:6a4db94011d3 10225
sahilmgandhi 18:6a4db94011d3 10226 /******************* Bit definition for I2C_SR2 register ********************/
sahilmgandhi 18:6a4db94011d3 10227 #define I2C_SR2_MSL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10228 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10229 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
sahilmgandhi 18:6a4db94011d3 10230 #define I2C_SR2_BUSY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10231 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10232 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
sahilmgandhi 18:6a4db94011d3 10233 #define I2C_SR2_TRA_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10234 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10235 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
sahilmgandhi 18:6a4db94011d3 10236 #define I2C_SR2_GENCALL_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10237 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10238 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
sahilmgandhi 18:6a4db94011d3 10239 #define I2C_SR2_SMBDEFAULT_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10240 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10241 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
sahilmgandhi 18:6a4db94011d3 10242 #define I2C_SR2_SMBHOST_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10243 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10244 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
sahilmgandhi 18:6a4db94011d3 10245 #define I2C_SR2_DUALF_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10246 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10247 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
sahilmgandhi 18:6a4db94011d3 10248 #define I2C_SR2_PEC_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10249 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 10250 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
sahilmgandhi 18:6a4db94011d3 10251
sahilmgandhi 18:6a4db94011d3 10252 /******************* Bit definition for I2C_CCR register ********************/
sahilmgandhi 18:6a4db94011d3 10253 #define I2C_CCR_CCR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10254 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 10255 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
sahilmgandhi 18:6a4db94011d3 10256 #define I2C_CCR_DUTY_Pos (14U)
sahilmgandhi 18:6a4db94011d3 10257 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10258 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
sahilmgandhi 18:6a4db94011d3 10259 #define I2C_CCR_FS_Pos (15U)
sahilmgandhi 18:6a4db94011d3 10260 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 10261 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
sahilmgandhi 18:6a4db94011d3 10262
sahilmgandhi 18:6a4db94011d3 10263 /****************** Bit definition for I2C_TRISE register *******************/
sahilmgandhi 18:6a4db94011d3 10264 #define I2C_TRISE_TRISE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10265 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
sahilmgandhi 18:6a4db94011d3 10266 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
sahilmgandhi 18:6a4db94011d3 10267
sahilmgandhi 18:6a4db94011d3 10268 /****************** Bit definition for I2C_FLTR register *******************/
sahilmgandhi 18:6a4db94011d3 10269 #define I2C_FLTR_DNF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10270 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 10271 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
sahilmgandhi 18:6a4db94011d3 10272 #define I2C_FLTR_ANOFF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10273 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10274 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
sahilmgandhi 18:6a4db94011d3 10275
sahilmgandhi 18:6a4db94011d3 10276 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10277 /* */
sahilmgandhi 18:6a4db94011d3 10278 /* Independent WATCHDOG */
sahilmgandhi 18:6a4db94011d3 10279 /* */
sahilmgandhi 18:6a4db94011d3 10280 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10281 /******************* Bit definition for IWDG_KR register ********************/
sahilmgandhi 18:6a4db94011d3 10282 #define IWDG_KR_KEY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10283 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 10284 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
sahilmgandhi 18:6a4db94011d3 10285
sahilmgandhi 18:6a4db94011d3 10286 /******************* Bit definition for IWDG_PR register ********************/
sahilmgandhi 18:6a4db94011d3 10287 #define IWDG_PR_PR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10288 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 10289 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
sahilmgandhi 18:6a4db94011d3 10290 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
sahilmgandhi 18:6a4db94011d3 10291 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
sahilmgandhi 18:6a4db94011d3 10292 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
sahilmgandhi 18:6a4db94011d3 10293
sahilmgandhi 18:6a4db94011d3 10294 /******************* Bit definition for IWDG_RLR register *******************/
sahilmgandhi 18:6a4db94011d3 10295 #define IWDG_RLR_RL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10296 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 10297 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
sahilmgandhi 18:6a4db94011d3 10298
sahilmgandhi 18:6a4db94011d3 10299 /******************* Bit definition for IWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 10300 #define IWDG_SR_PVU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10301 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10302 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
sahilmgandhi 18:6a4db94011d3 10303 #define IWDG_SR_RVU_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10304 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10305 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
sahilmgandhi 18:6a4db94011d3 10306
sahilmgandhi 18:6a4db94011d3 10307
sahilmgandhi 18:6a4db94011d3 10308
sahilmgandhi 18:6a4db94011d3 10309 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10310 /* */
sahilmgandhi 18:6a4db94011d3 10311 /* Power Control */
sahilmgandhi 18:6a4db94011d3 10312 /* */
sahilmgandhi 18:6a4db94011d3 10313 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10314 /******************** Bit definition for PWR_CR register ********************/
sahilmgandhi 18:6a4db94011d3 10315 #define PWR_CR_LPDS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10316 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10317 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
sahilmgandhi 18:6a4db94011d3 10318 #define PWR_CR_PDDS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10319 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10320 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
sahilmgandhi 18:6a4db94011d3 10321 #define PWR_CR_CWUF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10322 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10323 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 10324 #define PWR_CR_CSBF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10325 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10326 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
sahilmgandhi 18:6a4db94011d3 10327 #define PWR_CR_PVDE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10328 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10329 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
sahilmgandhi 18:6a4db94011d3 10330
sahilmgandhi 18:6a4db94011d3 10331 #define PWR_CR_PLS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10332 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
sahilmgandhi 18:6a4db94011d3 10333 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
sahilmgandhi 18:6a4db94011d3 10334 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10335 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10336 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10337
sahilmgandhi 18:6a4db94011d3 10338 /*!< PVD level configuration */
sahilmgandhi 18:6a4db94011d3 10339 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
sahilmgandhi 18:6a4db94011d3 10340 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
sahilmgandhi 18:6a4db94011d3 10341 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
sahilmgandhi 18:6a4db94011d3 10342 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
sahilmgandhi 18:6a4db94011d3 10343 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
sahilmgandhi 18:6a4db94011d3 10344 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
sahilmgandhi 18:6a4db94011d3 10345 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
sahilmgandhi 18:6a4db94011d3 10346 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
sahilmgandhi 18:6a4db94011d3 10347 #define PWR_CR_DBP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10348 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10349 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
sahilmgandhi 18:6a4db94011d3 10350 #define PWR_CR_FPDS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10351 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10352 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
sahilmgandhi 18:6a4db94011d3 10353 #define PWR_CR_LPLVDS_Pos (10U)
sahilmgandhi 18:6a4db94011d3 10354 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10355 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
sahilmgandhi 18:6a4db94011d3 10356 #define PWR_CR_MRLVDS_Pos (11U)
sahilmgandhi 18:6a4db94011d3 10357 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10358 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
sahilmgandhi 18:6a4db94011d3 10359 #define PWR_CR_ADCDC1_Pos (13U)
sahilmgandhi 18:6a4db94011d3 10360 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 10361 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
sahilmgandhi 18:6a4db94011d3 10362 #define PWR_CR_VOS_Pos (14U)
sahilmgandhi 18:6a4db94011d3 10363 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 10364 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
sahilmgandhi 18:6a4db94011d3 10365 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
sahilmgandhi 18:6a4db94011d3 10366 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
sahilmgandhi 18:6a4db94011d3 10367 #define PWR_CR_ODEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 10368 #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 10369 #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
sahilmgandhi 18:6a4db94011d3 10370 #define PWR_CR_ODSWEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 10371 #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 10372 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
sahilmgandhi 18:6a4db94011d3 10373 #define PWR_CR_UDEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 10374 #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 10375 #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
sahilmgandhi 18:6a4db94011d3 10376 #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 10377 #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 10378
sahilmgandhi 18:6a4db94011d3 10379 /* Legacy define */
sahilmgandhi 18:6a4db94011d3 10380 #define PWR_CR_PMODE PWR_CR_VOS
sahilmgandhi 18:6a4db94011d3 10381 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
sahilmgandhi 18:6a4db94011d3 10382 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
sahilmgandhi 18:6a4db94011d3 10383
sahilmgandhi 18:6a4db94011d3 10384 /******************* Bit definition for PWR_CSR register ********************/
sahilmgandhi 18:6a4db94011d3 10385 #define PWR_CSR_WUF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10386 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10387 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
sahilmgandhi 18:6a4db94011d3 10388 #define PWR_CSR_SBF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10389 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10390 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
sahilmgandhi 18:6a4db94011d3 10391 #define PWR_CSR_PVDO_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10392 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10393 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
sahilmgandhi 18:6a4db94011d3 10394 #define PWR_CSR_BRR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10395 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10396 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
sahilmgandhi 18:6a4db94011d3 10397 #define PWR_CSR_EWUP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10398 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10399 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
sahilmgandhi 18:6a4db94011d3 10400 #define PWR_CSR_BRE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10401 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10402 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
sahilmgandhi 18:6a4db94011d3 10403 #define PWR_CSR_VOSRDY_Pos (14U)
sahilmgandhi 18:6a4db94011d3 10404 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10405 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
sahilmgandhi 18:6a4db94011d3 10406 #define PWR_CSR_ODRDY_Pos (16U)
sahilmgandhi 18:6a4db94011d3 10407 #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 10408 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
sahilmgandhi 18:6a4db94011d3 10409 #define PWR_CSR_ODSWRDY_Pos (17U)
sahilmgandhi 18:6a4db94011d3 10410 #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 10411 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
sahilmgandhi 18:6a4db94011d3 10412 #define PWR_CSR_UDRDY_Pos (18U)
sahilmgandhi 18:6a4db94011d3 10413 #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 10414 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
sahilmgandhi 18:6a4db94011d3 10415 /* Legacy define */
sahilmgandhi 18:6a4db94011d3 10416 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
sahilmgandhi 18:6a4db94011d3 10417
sahilmgandhi 18:6a4db94011d3 10418 /* Legacy define */
sahilmgandhi 18:6a4db94011d3 10419 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
sahilmgandhi 18:6a4db94011d3 10420
sahilmgandhi 18:6a4db94011d3 10421 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10422 /* */
sahilmgandhi 18:6a4db94011d3 10423 /* Reset and Clock Control */
sahilmgandhi 18:6a4db94011d3 10424 /* */
sahilmgandhi 18:6a4db94011d3 10425 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 10426 /******************** Bit definition for RCC_CR register ********************/
sahilmgandhi 18:6a4db94011d3 10427 #define RCC_CR_HSION_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10428 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10429 #define RCC_CR_HSION RCC_CR_HSION_Msk
sahilmgandhi 18:6a4db94011d3 10430 #define RCC_CR_HSIRDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10431 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10432 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
sahilmgandhi 18:6a4db94011d3 10433
sahilmgandhi 18:6a4db94011d3 10434 #define RCC_CR_HSITRIM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10435 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
sahilmgandhi 18:6a4db94011d3 10436 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
sahilmgandhi 18:6a4db94011d3 10437 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10438 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10439 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10440 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10441 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10442
sahilmgandhi 18:6a4db94011d3 10443 #define RCC_CR_HSICAL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10444 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 10445 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
sahilmgandhi 18:6a4db94011d3 10446 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10447 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10448 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10449 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10450 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10451 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 10452 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10453 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 10454
sahilmgandhi 18:6a4db94011d3 10455 #define RCC_CR_HSEON_Pos (16U)
sahilmgandhi 18:6a4db94011d3 10456 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 10457 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
sahilmgandhi 18:6a4db94011d3 10458 #define RCC_CR_HSERDY_Pos (17U)
sahilmgandhi 18:6a4db94011d3 10459 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 10460 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
sahilmgandhi 18:6a4db94011d3 10461 #define RCC_CR_HSEBYP_Pos (18U)
sahilmgandhi 18:6a4db94011d3 10462 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 10463 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
sahilmgandhi 18:6a4db94011d3 10464 #define RCC_CR_CSSON_Pos (19U)
sahilmgandhi 18:6a4db94011d3 10465 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 10466 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
sahilmgandhi 18:6a4db94011d3 10467 #define RCC_CR_PLLON_Pos (24U)
sahilmgandhi 18:6a4db94011d3 10468 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 10469 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
sahilmgandhi 18:6a4db94011d3 10470 #define RCC_CR_PLLRDY_Pos (25U)
sahilmgandhi 18:6a4db94011d3 10471 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 10472 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
sahilmgandhi 18:6a4db94011d3 10473 #define RCC_CR_PLLI2SON_Pos (26U)
sahilmgandhi 18:6a4db94011d3 10474 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 10475 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
sahilmgandhi 18:6a4db94011d3 10476 #define RCC_CR_PLLI2SRDY_Pos (27U)
sahilmgandhi 18:6a4db94011d3 10477 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 10478 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
sahilmgandhi 18:6a4db94011d3 10479 #define RCC_CR_PLLSAION_Pos (28U)
sahilmgandhi 18:6a4db94011d3 10480 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 10481 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
sahilmgandhi 18:6a4db94011d3 10482 #define RCC_CR_PLLSAIRDY_Pos (29U)
sahilmgandhi 18:6a4db94011d3 10483 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 10484 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
sahilmgandhi 18:6a4db94011d3 10485
sahilmgandhi 18:6a4db94011d3 10486 /******************** Bit definition for RCC_PLLCFGR register ***************/
sahilmgandhi 18:6a4db94011d3 10487 #define RCC_PLLCFGR_PLLM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10488 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
sahilmgandhi 18:6a4db94011d3 10489 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
sahilmgandhi 18:6a4db94011d3 10490 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10491 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10492 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10493 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10494 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10495 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10496
sahilmgandhi 18:6a4db94011d3 10497 #define RCC_PLLCFGR_PLLN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10498 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
sahilmgandhi 18:6a4db94011d3 10499 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
sahilmgandhi 18:6a4db94011d3 10500 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10501 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10502 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10503 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10504 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10505 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10506 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10507 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 10508 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10509
sahilmgandhi 18:6a4db94011d3 10510 #define RCC_PLLCFGR_PLLP_Pos (16U)
sahilmgandhi 18:6a4db94011d3 10511 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 10512 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
sahilmgandhi 18:6a4db94011d3 10513 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 10514 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 10515
sahilmgandhi 18:6a4db94011d3 10516 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
sahilmgandhi 18:6a4db94011d3 10517 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 10518 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
sahilmgandhi 18:6a4db94011d3 10519 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
sahilmgandhi 18:6a4db94011d3 10520 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 10521 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
sahilmgandhi 18:6a4db94011d3 10522 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
sahilmgandhi 18:6a4db94011d3 10523
sahilmgandhi 18:6a4db94011d3 10524 #define RCC_PLLCFGR_PLLQ_Pos (24U)
sahilmgandhi 18:6a4db94011d3 10525 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 10526 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
sahilmgandhi 18:6a4db94011d3 10527 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 10528 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 10529 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 10530 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 10531
sahilmgandhi 18:6a4db94011d3 10532 /******************** Bit definition for RCC_CFGR register ******************/
sahilmgandhi 18:6a4db94011d3 10533 /*!< SW configuration */
sahilmgandhi 18:6a4db94011d3 10534 #define RCC_CFGR_SW_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10535 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 10536 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
sahilmgandhi 18:6a4db94011d3 10537 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10538 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10539
sahilmgandhi 18:6a4db94011d3 10540 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
sahilmgandhi 18:6a4db94011d3 10541 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
sahilmgandhi 18:6a4db94011d3 10542 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
sahilmgandhi 18:6a4db94011d3 10543
sahilmgandhi 18:6a4db94011d3 10544 /*!< SWS configuration */
sahilmgandhi 18:6a4db94011d3 10545 #define RCC_CFGR_SWS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10546 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 10547 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
sahilmgandhi 18:6a4db94011d3 10548 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10549 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10550
sahilmgandhi 18:6a4db94011d3 10551 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 10552 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
sahilmgandhi 18:6a4db94011d3 10553 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
sahilmgandhi 18:6a4db94011d3 10554
sahilmgandhi 18:6a4db94011d3 10555 /*!< HPRE configuration */
sahilmgandhi 18:6a4db94011d3 10556 #define RCC_CFGR_HPRE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10557 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 10558 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
sahilmgandhi 18:6a4db94011d3 10559 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10560 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10561 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10562 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10563
sahilmgandhi 18:6a4db94011d3 10564 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
sahilmgandhi 18:6a4db94011d3 10565 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 10566 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 10567 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 10568 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 10569 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
sahilmgandhi 18:6a4db94011d3 10570 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
sahilmgandhi 18:6a4db94011d3 10571 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
sahilmgandhi 18:6a4db94011d3 10572 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
sahilmgandhi 18:6a4db94011d3 10573
sahilmgandhi 18:6a4db94011d3 10574 /*!< PPRE1 configuration */
sahilmgandhi 18:6a4db94011d3 10575 #define RCC_CFGR_PPRE1_Pos (10U)
sahilmgandhi 18:6a4db94011d3 10576 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
sahilmgandhi 18:6a4db94011d3 10577 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
sahilmgandhi 18:6a4db94011d3 10578 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10579 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10580 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10581
sahilmgandhi 18:6a4db94011d3 10582 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 10583 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 10584 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 10585 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 10586 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 10587
sahilmgandhi 18:6a4db94011d3 10588 /*!< PPRE2 configuration */
sahilmgandhi 18:6a4db94011d3 10589 #define RCC_CFGR_PPRE2_Pos (13U)
sahilmgandhi 18:6a4db94011d3 10590 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 10591 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
sahilmgandhi 18:6a4db94011d3 10592 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 10593 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10594 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 10595
sahilmgandhi 18:6a4db94011d3 10596 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
sahilmgandhi 18:6a4db94011d3 10597 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
sahilmgandhi 18:6a4db94011d3 10598 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
sahilmgandhi 18:6a4db94011d3 10599 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
sahilmgandhi 18:6a4db94011d3 10600 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
sahilmgandhi 18:6a4db94011d3 10601
sahilmgandhi 18:6a4db94011d3 10602 /*!< RTCPRE configuration */
sahilmgandhi 18:6a4db94011d3 10603 #define RCC_CFGR_RTCPRE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 10604 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
sahilmgandhi 18:6a4db94011d3 10605 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
sahilmgandhi 18:6a4db94011d3 10606 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 10607 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 10608 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 10609 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 10610 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 10611
sahilmgandhi 18:6a4db94011d3 10612 /*!< MCO1 configuration */
sahilmgandhi 18:6a4db94011d3 10613 #define RCC_CFGR_MCO1_Pos (21U)
sahilmgandhi 18:6a4db94011d3 10614 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
sahilmgandhi 18:6a4db94011d3 10615 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
sahilmgandhi 18:6a4db94011d3 10616 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 10617 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 10618
sahilmgandhi 18:6a4db94011d3 10619 #define RCC_CFGR_I2SSRC_Pos (23U)
sahilmgandhi 18:6a4db94011d3 10620 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 10621 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
sahilmgandhi 18:6a4db94011d3 10622
sahilmgandhi 18:6a4db94011d3 10623 #define RCC_CFGR_MCO1PRE_Pos (24U)
sahilmgandhi 18:6a4db94011d3 10624 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
sahilmgandhi 18:6a4db94011d3 10625 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
sahilmgandhi 18:6a4db94011d3 10626 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 10627 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 10628 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 10629
sahilmgandhi 18:6a4db94011d3 10630 #define RCC_CFGR_MCO2PRE_Pos (27U)
sahilmgandhi 18:6a4db94011d3 10631 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
sahilmgandhi 18:6a4db94011d3 10632 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
sahilmgandhi 18:6a4db94011d3 10633 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 10634 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 10635 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 10636
sahilmgandhi 18:6a4db94011d3 10637 #define RCC_CFGR_MCO2_Pos (30U)
sahilmgandhi 18:6a4db94011d3 10638 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
sahilmgandhi 18:6a4db94011d3 10639 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
sahilmgandhi 18:6a4db94011d3 10640 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 10641 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 10642
sahilmgandhi 18:6a4db94011d3 10643 /******************** Bit definition for RCC_CIR register *******************/
sahilmgandhi 18:6a4db94011d3 10644 #define RCC_CIR_LSIRDYF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10645 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10646 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
sahilmgandhi 18:6a4db94011d3 10647 #define RCC_CIR_LSERDYF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10648 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10649 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
sahilmgandhi 18:6a4db94011d3 10650 #define RCC_CIR_HSIRDYF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10651 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10652 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
sahilmgandhi 18:6a4db94011d3 10653 #define RCC_CIR_HSERDYF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10654 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10655 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
sahilmgandhi 18:6a4db94011d3 10656 #define RCC_CIR_PLLRDYF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10657 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10658 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
sahilmgandhi 18:6a4db94011d3 10659 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10660 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10661 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
sahilmgandhi 18:6a4db94011d3 10662
sahilmgandhi 18:6a4db94011d3 10663 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10664 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10665 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
sahilmgandhi 18:6a4db94011d3 10666 #define RCC_CIR_CSSF_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10667 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10668 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
sahilmgandhi 18:6a4db94011d3 10669 #define RCC_CIR_LSIRDYIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10670 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10671 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
sahilmgandhi 18:6a4db94011d3 10672 #define RCC_CIR_LSERDYIE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10673 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10674 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
sahilmgandhi 18:6a4db94011d3 10675 #define RCC_CIR_HSIRDYIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 10676 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10677 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
sahilmgandhi 18:6a4db94011d3 10678 #define RCC_CIR_HSERDYIE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 10679 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10680 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
sahilmgandhi 18:6a4db94011d3 10681 #define RCC_CIR_PLLRDYIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 10682 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10683 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
sahilmgandhi 18:6a4db94011d3 10684 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 10685 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 10686 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
sahilmgandhi 18:6a4db94011d3 10687
sahilmgandhi 18:6a4db94011d3 10688 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 10689 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10690 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
sahilmgandhi 18:6a4db94011d3 10691 #define RCC_CIR_LSIRDYC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 10692 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 10693 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
sahilmgandhi 18:6a4db94011d3 10694 #define RCC_CIR_LSERDYC_Pos (17U)
sahilmgandhi 18:6a4db94011d3 10695 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 10696 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
sahilmgandhi 18:6a4db94011d3 10697 #define RCC_CIR_HSIRDYC_Pos (18U)
sahilmgandhi 18:6a4db94011d3 10698 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 10699 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
sahilmgandhi 18:6a4db94011d3 10700 #define RCC_CIR_HSERDYC_Pos (19U)
sahilmgandhi 18:6a4db94011d3 10701 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 10702 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
sahilmgandhi 18:6a4db94011d3 10703 #define RCC_CIR_PLLRDYC_Pos (20U)
sahilmgandhi 18:6a4db94011d3 10704 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 10705 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
sahilmgandhi 18:6a4db94011d3 10706 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
sahilmgandhi 18:6a4db94011d3 10707 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 10708 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
sahilmgandhi 18:6a4db94011d3 10709 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
sahilmgandhi 18:6a4db94011d3 10710 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 10711 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
sahilmgandhi 18:6a4db94011d3 10712
sahilmgandhi 18:6a4db94011d3 10713 #define RCC_CIR_CSSC_Pos (23U)
sahilmgandhi 18:6a4db94011d3 10714 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 10715 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
sahilmgandhi 18:6a4db94011d3 10716
sahilmgandhi 18:6a4db94011d3 10717 /******************** Bit definition for RCC_AHB1RSTR register **************/
sahilmgandhi 18:6a4db94011d3 10718 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10719 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10720 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
sahilmgandhi 18:6a4db94011d3 10721 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10722 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10723 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
sahilmgandhi 18:6a4db94011d3 10724 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10725 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10726 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
sahilmgandhi 18:6a4db94011d3 10727 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10728 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10729 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
sahilmgandhi 18:6a4db94011d3 10730 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10731 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10732 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
sahilmgandhi 18:6a4db94011d3 10733 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10734 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10735 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
sahilmgandhi 18:6a4db94011d3 10736 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10737 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10738 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
sahilmgandhi 18:6a4db94011d3 10739 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10740 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10741 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
sahilmgandhi 18:6a4db94011d3 10742 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10743 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10744 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
sahilmgandhi 18:6a4db94011d3 10745 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10746 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10747 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
sahilmgandhi 18:6a4db94011d3 10748 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
sahilmgandhi 18:6a4db94011d3 10749 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10750 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
sahilmgandhi 18:6a4db94011d3 10751 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 10752 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10753 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
sahilmgandhi 18:6a4db94011d3 10754 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
sahilmgandhi 18:6a4db94011d3 10755 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 10756 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
sahilmgandhi 18:6a4db94011d3 10757 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
sahilmgandhi 18:6a4db94011d3 10758 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 10759 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
sahilmgandhi 18:6a4db94011d3 10760 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
sahilmgandhi 18:6a4db94011d3 10761 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 10762 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
sahilmgandhi 18:6a4db94011d3 10763 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
sahilmgandhi 18:6a4db94011d3 10764 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 10765 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
sahilmgandhi 18:6a4db94011d3 10766 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
sahilmgandhi 18:6a4db94011d3 10767 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 10768 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
sahilmgandhi 18:6a4db94011d3 10769
sahilmgandhi 18:6a4db94011d3 10770 /******************** Bit definition for RCC_AHB2RSTR register **************/
sahilmgandhi 18:6a4db94011d3 10771 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10772 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10773 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
sahilmgandhi 18:6a4db94011d3 10774 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10775 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10776 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
sahilmgandhi 18:6a4db94011d3 10777 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10778 #define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10779 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
sahilmgandhi 18:6a4db94011d3 10780 /* maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 10781 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
sahilmgandhi 18:6a4db94011d3 10782 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10783 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10784 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
sahilmgandhi 18:6a4db94011d3 10785 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10786 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10787 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
sahilmgandhi 18:6a4db94011d3 10788 /******************** Bit definition for RCC_AHB3RSTR register **************/
sahilmgandhi 18:6a4db94011d3 10789 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10790 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10791 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
sahilmgandhi 18:6a4db94011d3 10792
sahilmgandhi 18:6a4db94011d3 10793
sahilmgandhi 18:6a4db94011d3 10794 /******************** Bit definition for RCC_APB1RSTR register **************/
sahilmgandhi 18:6a4db94011d3 10795 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10796 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10797 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
sahilmgandhi 18:6a4db94011d3 10798 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10799 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10800 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
sahilmgandhi 18:6a4db94011d3 10801 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10802 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10803 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
sahilmgandhi 18:6a4db94011d3 10804 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10805 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10806 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
sahilmgandhi 18:6a4db94011d3 10807 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10808 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10809 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
sahilmgandhi 18:6a4db94011d3 10810 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10811 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10812 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
sahilmgandhi 18:6a4db94011d3 10813 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10814 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10815 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
sahilmgandhi 18:6a4db94011d3 10816 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10817 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10818 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
sahilmgandhi 18:6a4db94011d3 10819 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10820 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10821 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
sahilmgandhi 18:6a4db94011d3 10822 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
sahilmgandhi 18:6a4db94011d3 10823 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10824 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
sahilmgandhi 18:6a4db94011d3 10825 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
sahilmgandhi 18:6a4db94011d3 10826 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10827 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
sahilmgandhi 18:6a4db94011d3 10828 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
sahilmgandhi 18:6a4db94011d3 10829 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 10830 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
sahilmgandhi 18:6a4db94011d3 10831 #define RCC_APB1RSTR_USART2RST_Pos (17U)
sahilmgandhi 18:6a4db94011d3 10832 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 10833 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
sahilmgandhi 18:6a4db94011d3 10834 #define RCC_APB1RSTR_USART3RST_Pos (18U)
sahilmgandhi 18:6a4db94011d3 10835 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 10836 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
sahilmgandhi 18:6a4db94011d3 10837 #define RCC_APB1RSTR_UART4RST_Pos (19U)
sahilmgandhi 18:6a4db94011d3 10838 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 10839 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
sahilmgandhi 18:6a4db94011d3 10840 #define RCC_APB1RSTR_UART5RST_Pos (20U)
sahilmgandhi 18:6a4db94011d3 10841 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 10842 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
sahilmgandhi 18:6a4db94011d3 10843 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
sahilmgandhi 18:6a4db94011d3 10844 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 10845 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
sahilmgandhi 18:6a4db94011d3 10846 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
sahilmgandhi 18:6a4db94011d3 10847 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 10848 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
sahilmgandhi 18:6a4db94011d3 10849 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
sahilmgandhi 18:6a4db94011d3 10850 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 10851 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
sahilmgandhi 18:6a4db94011d3 10852 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
sahilmgandhi 18:6a4db94011d3 10853 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 10854 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
sahilmgandhi 18:6a4db94011d3 10855 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
sahilmgandhi 18:6a4db94011d3 10856 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 10857 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
sahilmgandhi 18:6a4db94011d3 10858 #define RCC_APB1RSTR_PWRRST_Pos (28U)
sahilmgandhi 18:6a4db94011d3 10859 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 10860 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
sahilmgandhi 18:6a4db94011d3 10861 #define RCC_APB1RSTR_DACRST_Pos (29U)
sahilmgandhi 18:6a4db94011d3 10862 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 10863 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
sahilmgandhi 18:6a4db94011d3 10864 #define RCC_APB1RSTR_UART7RST_Pos (30U)
sahilmgandhi 18:6a4db94011d3 10865 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 10866 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
sahilmgandhi 18:6a4db94011d3 10867 #define RCC_APB1RSTR_UART8RST_Pos (31U)
sahilmgandhi 18:6a4db94011d3 10868 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 10869 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
sahilmgandhi 18:6a4db94011d3 10870
sahilmgandhi 18:6a4db94011d3 10871 /******************** Bit definition for RCC_APB2RSTR register **************/
sahilmgandhi 18:6a4db94011d3 10872 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10873 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10874 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
sahilmgandhi 18:6a4db94011d3 10875 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10876 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10877 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
sahilmgandhi 18:6a4db94011d3 10878 #define RCC_APB2RSTR_USART1RST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10879 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10880 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
sahilmgandhi 18:6a4db94011d3 10881 #define RCC_APB2RSTR_USART6RST_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10882 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10883 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
sahilmgandhi 18:6a4db94011d3 10884 #define RCC_APB2RSTR_ADCRST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10885 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10886 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
sahilmgandhi 18:6a4db94011d3 10887 #define RCC_APB2RSTR_SDIORST_Pos (11U)
sahilmgandhi 18:6a4db94011d3 10888 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 10889 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
sahilmgandhi 18:6a4db94011d3 10890 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 10891 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10892 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
sahilmgandhi 18:6a4db94011d3 10893 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
sahilmgandhi 18:6a4db94011d3 10894 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 10895 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
sahilmgandhi 18:6a4db94011d3 10896 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
sahilmgandhi 18:6a4db94011d3 10897 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 10898 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
sahilmgandhi 18:6a4db94011d3 10899 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
sahilmgandhi 18:6a4db94011d3 10900 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 10901 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
sahilmgandhi 18:6a4db94011d3 10902 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
sahilmgandhi 18:6a4db94011d3 10903 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 10904 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
sahilmgandhi 18:6a4db94011d3 10905 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
sahilmgandhi 18:6a4db94011d3 10906 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 10907 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
sahilmgandhi 18:6a4db94011d3 10908 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
sahilmgandhi 18:6a4db94011d3 10909 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 10910 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
sahilmgandhi 18:6a4db94011d3 10911 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
sahilmgandhi 18:6a4db94011d3 10912 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 10913 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
sahilmgandhi 18:6a4db94011d3 10914 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
sahilmgandhi 18:6a4db94011d3 10915 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 10916 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
sahilmgandhi 18:6a4db94011d3 10917
sahilmgandhi 18:6a4db94011d3 10918 /* Old SPI1RST bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 10919 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
sahilmgandhi 18:6a4db94011d3 10920
sahilmgandhi 18:6a4db94011d3 10921 /******************** Bit definition for RCC_AHB1ENR register ***************/
sahilmgandhi 18:6a4db94011d3 10922 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10923 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10924 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
sahilmgandhi 18:6a4db94011d3 10925 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 10926 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 10927 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
sahilmgandhi 18:6a4db94011d3 10928 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 10929 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 10930 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
sahilmgandhi 18:6a4db94011d3 10931 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 10932 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 10933 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
sahilmgandhi 18:6a4db94011d3 10934 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10935 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10936 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
sahilmgandhi 18:6a4db94011d3 10937 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10938 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 10939 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
sahilmgandhi 18:6a4db94011d3 10940 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 10941 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 10942 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
sahilmgandhi 18:6a4db94011d3 10943 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 10944 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 10945 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
sahilmgandhi 18:6a4db94011d3 10946 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 10947 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 10948 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
sahilmgandhi 18:6a4db94011d3 10949 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 10950 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 10951 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
sahilmgandhi 18:6a4db94011d3 10952 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 10953 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 10954 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
sahilmgandhi 18:6a4db94011d3 10955 #define RCC_AHB1ENR_CRCEN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 10956 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 10957 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
sahilmgandhi 18:6a4db94011d3 10958 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 10959 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 10960 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
sahilmgandhi 18:6a4db94011d3 10961 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 10962 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 10963 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
sahilmgandhi 18:6a4db94011d3 10964 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 10965 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 10966 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
sahilmgandhi 18:6a4db94011d3 10967 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 10968 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 10969 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
sahilmgandhi 18:6a4db94011d3 10970 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 10971 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 10972 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
sahilmgandhi 18:6a4db94011d3 10973 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
sahilmgandhi 18:6a4db94011d3 10974 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 10975 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
sahilmgandhi 18:6a4db94011d3 10976 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
sahilmgandhi 18:6a4db94011d3 10977 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 10978 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
sahilmgandhi 18:6a4db94011d3 10979 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
sahilmgandhi 18:6a4db94011d3 10980 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 10981 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
sahilmgandhi 18:6a4db94011d3 10982 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 10983 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 10984 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
sahilmgandhi 18:6a4db94011d3 10985 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
sahilmgandhi 18:6a4db94011d3 10986 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 10987 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
sahilmgandhi 18:6a4db94011d3 10988 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
sahilmgandhi 18:6a4db94011d3 10989 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 10990 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
sahilmgandhi 18:6a4db94011d3 10991 /******************** Bit definition for RCC_AHB2ENR register ***************/
sahilmgandhi 18:6a4db94011d3 10992 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 10993 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 10994 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
sahilmgandhi 18:6a4db94011d3 10995 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 10996 #define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 10997 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
sahilmgandhi 18:6a4db94011d3 10998 #define RCC_AHB2ENR_HASHEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 10999 #define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11000 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
sahilmgandhi 18:6a4db94011d3 11001 #define RCC_AHB2ENR_RNGEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11002 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11003 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
sahilmgandhi 18:6a4db94011d3 11004 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11005 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11006 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
sahilmgandhi 18:6a4db94011d3 11007
sahilmgandhi 18:6a4db94011d3 11008 /******************** Bit definition for RCC_AHB3ENR register ***************/
sahilmgandhi 18:6a4db94011d3 11009 #define RCC_AHB3ENR_FMCEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11010 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11011 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
sahilmgandhi 18:6a4db94011d3 11012
sahilmgandhi 18:6a4db94011d3 11013 /******************** Bit definition for RCC_APB1ENR register ***************/
sahilmgandhi 18:6a4db94011d3 11014 #define RCC_APB1ENR_TIM2EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11015 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11016 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
sahilmgandhi 18:6a4db94011d3 11017 #define RCC_APB1ENR_TIM3EN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11018 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11019 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
sahilmgandhi 18:6a4db94011d3 11020 #define RCC_APB1ENR_TIM4EN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 11021 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11022 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
sahilmgandhi 18:6a4db94011d3 11023 #define RCC_APB1ENR_TIM5EN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 11024 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11025 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
sahilmgandhi 18:6a4db94011d3 11026 #define RCC_APB1ENR_TIM6EN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11027 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11028 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
sahilmgandhi 18:6a4db94011d3 11029 #define RCC_APB1ENR_TIM7EN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11030 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11031 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
sahilmgandhi 18:6a4db94011d3 11032 #define RCC_APB1ENR_TIM12EN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11033 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11034 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
sahilmgandhi 18:6a4db94011d3 11035 #define RCC_APB1ENR_TIM13EN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11036 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11037 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
sahilmgandhi 18:6a4db94011d3 11038 #define RCC_APB1ENR_TIM14EN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11039 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11040 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
sahilmgandhi 18:6a4db94011d3 11041 #define RCC_APB1ENR_WWDGEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 11042 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11043 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
sahilmgandhi 18:6a4db94011d3 11044 #define RCC_APB1ENR_SPI2EN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 11045 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11046 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
sahilmgandhi 18:6a4db94011d3 11047 #define RCC_APB1ENR_SPI3EN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 11048 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 11049 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
sahilmgandhi 18:6a4db94011d3 11050 #define RCC_APB1ENR_USART2EN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 11051 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11052 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
sahilmgandhi 18:6a4db94011d3 11053 #define RCC_APB1ENR_USART3EN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 11054 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11055 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
sahilmgandhi 18:6a4db94011d3 11056 #define RCC_APB1ENR_UART4EN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 11057 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11058 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
sahilmgandhi 18:6a4db94011d3 11059 #define RCC_APB1ENR_UART5EN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11060 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11061 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
sahilmgandhi 18:6a4db94011d3 11062 #define RCC_APB1ENR_I2C1EN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 11063 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11064 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
sahilmgandhi 18:6a4db94011d3 11065 #define RCC_APB1ENR_I2C2EN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11066 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11067 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
sahilmgandhi 18:6a4db94011d3 11068 #define RCC_APB1ENR_I2C3EN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 11069 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 11070 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
sahilmgandhi 18:6a4db94011d3 11071 #define RCC_APB1ENR_CAN1EN_Pos (25U)
sahilmgandhi 18:6a4db94011d3 11072 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 11073 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
sahilmgandhi 18:6a4db94011d3 11074 #define RCC_APB1ENR_CAN2EN_Pos (26U)
sahilmgandhi 18:6a4db94011d3 11075 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 11076 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
sahilmgandhi 18:6a4db94011d3 11077 #define RCC_APB1ENR_PWREN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 11078 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 11079 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
sahilmgandhi 18:6a4db94011d3 11080 #define RCC_APB1ENR_DACEN_Pos (29U)
sahilmgandhi 18:6a4db94011d3 11081 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 11082 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
sahilmgandhi 18:6a4db94011d3 11083 #define RCC_APB1ENR_UART7EN_Pos (30U)
sahilmgandhi 18:6a4db94011d3 11084 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11085 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
sahilmgandhi 18:6a4db94011d3 11086 #define RCC_APB1ENR_UART8EN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 11087 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 11088 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
sahilmgandhi 18:6a4db94011d3 11089
sahilmgandhi 18:6a4db94011d3 11090 /******************** Bit definition for RCC_APB2ENR register ***************/
sahilmgandhi 18:6a4db94011d3 11091 #define RCC_APB2ENR_TIM1EN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11092 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11093 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
sahilmgandhi 18:6a4db94011d3 11094 #define RCC_APB2ENR_TIM8EN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11095 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11096 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
sahilmgandhi 18:6a4db94011d3 11097 #define RCC_APB2ENR_USART1EN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11098 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11099 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
sahilmgandhi 18:6a4db94011d3 11100 #define RCC_APB2ENR_USART6EN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11101 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11102 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
sahilmgandhi 18:6a4db94011d3 11103 #define RCC_APB2ENR_ADC1EN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11104 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11105 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
sahilmgandhi 18:6a4db94011d3 11106 #define RCC_APB2ENR_ADC2EN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 11107 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11108 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
sahilmgandhi 18:6a4db94011d3 11109 #define RCC_APB2ENR_ADC3EN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 11110 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11111 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
sahilmgandhi 18:6a4db94011d3 11112 #define RCC_APB2ENR_SDIOEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 11113 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11114 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
sahilmgandhi 18:6a4db94011d3 11115 #define RCC_APB2ENR_SPI1EN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11116 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11117 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
sahilmgandhi 18:6a4db94011d3 11118 #define RCC_APB2ENR_SPI4EN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 11119 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11120 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
sahilmgandhi 18:6a4db94011d3 11121 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 11122 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11123 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
sahilmgandhi 18:6a4db94011d3 11124 #define RCC_APB2ENR_TIM9EN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11125 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11126 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
sahilmgandhi 18:6a4db94011d3 11127 #define RCC_APB2ENR_TIM10EN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 11128 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11129 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
sahilmgandhi 18:6a4db94011d3 11130 #define RCC_APB2ENR_TIM11EN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 11131 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11132 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
sahilmgandhi 18:6a4db94011d3 11133 #define RCC_APB2ENR_SPI5EN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11134 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11135 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
sahilmgandhi 18:6a4db94011d3 11136 #define RCC_APB2ENR_SPI6EN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 11137 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11138 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
sahilmgandhi 18:6a4db94011d3 11139 #define RCC_APB2ENR_SAI1EN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11140 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11141 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
sahilmgandhi 18:6a4db94011d3 11142
sahilmgandhi 18:6a4db94011d3 11143 /******************** Bit definition for RCC_AHB1LPENR register *************/
sahilmgandhi 18:6a4db94011d3 11144 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11145 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11146 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
sahilmgandhi 18:6a4db94011d3 11147 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11148 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11149 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11150 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 11151 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11152 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11153 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 11154 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11155 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11156 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11157 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11158 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
sahilmgandhi 18:6a4db94011d3 11159 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11160 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11161 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11162 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11163 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11164 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11165 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11166 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11167 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11168 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11169 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11170 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
sahilmgandhi 18:6a4db94011d3 11171 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 11172 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11173 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11174 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 11175 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11176 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11177 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11178 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11179 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11180 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 11181 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 11182 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11183 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11184 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11185 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11186 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 11187 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11188 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11189 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 11190 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11191 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11192 #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 11193 #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11194 #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11195 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 11196 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11197 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11198 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11199 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11200 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11201 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 11202 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 11203 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11204
sahilmgandhi 18:6a4db94011d3 11205 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
sahilmgandhi 18:6a4db94011d3 11206 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 11207 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11208 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
sahilmgandhi 18:6a4db94011d3 11209 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 11210 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11211 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
sahilmgandhi 18:6a4db94011d3 11212 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 11213 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11214 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 11215 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 11216 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11217 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
sahilmgandhi 18:6a4db94011d3 11218 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 11219 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11220 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
sahilmgandhi 18:6a4db94011d3 11221 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11222 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
sahilmgandhi 18:6a4db94011d3 11223
sahilmgandhi 18:6a4db94011d3 11224 /******************** Bit definition for RCC_AHB2LPENR register *************/
sahilmgandhi 18:6a4db94011d3 11225 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11226 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11227 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
sahilmgandhi 18:6a4db94011d3 11228 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11229 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11230 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11231 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11232 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11233 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11234 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11235 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11236 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11237 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11238 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11239 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11240
sahilmgandhi 18:6a4db94011d3 11241 /******************** Bit definition for RCC_AHB3LPENR register *************/
sahilmgandhi 18:6a4db94011d3 11242 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11243 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11244 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11245
sahilmgandhi 18:6a4db94011d3 11246 /******************** Bit definition for RCC_APB1LPENR register *************/
sahilmgandhi 18:6a4db94011d3 11247 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11248 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11249 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11250 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11251 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11252 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11253 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 11254 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11255 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11256 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 11257 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11258 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11259 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11260 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11261 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11262 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11263 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11264 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11265 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11266 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11267 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11268 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11269 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11270 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11271 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11272 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11273 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11274 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 11275 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11276 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11277 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 11278 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11279 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11280 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 11281 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 11282 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11283 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 11284 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11285 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11286 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 11287 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11288 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11289 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 11290 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11291 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11292 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11293 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11294 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11295 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 11296 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11297 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11298 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11299 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11300 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11301 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
sahilmgandhi 18:6a4db94011d3 11302 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 11303 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11304 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
sahilmgandhi 18:6a4db94011d3 11305 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 11306 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11307 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
sahilmgandhi 18:6a4db94011d3 11308 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 11309 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11310 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
sahilmgandhi 18:6a4db94011d3 11311 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 11312 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11313 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
sahilmgandhi 18:6a4db94011d3 11314 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 11315 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11316 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
sahilmgandhi 18:6a4db94011d3 11317 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11318 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11319 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 11320 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 11321 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11322
sahilmgandhi 18:6a4db94011d3 11323 /******************** Bit definition for RCC_APB2LPENR register *************/
sahilmgandhi 18:6a4db94011d3 11324 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11325 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11326 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11327 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11328 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11329 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11330 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11331 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11332 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11333 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11334 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11335 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11336 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11337 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11338 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11339 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
sahilmgandhi 18:6a4db94011d3 11340 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11341 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11342 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 11343 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11344 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11345 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 11346 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11347 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11348 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11349 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11350 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11351 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 11352 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11353 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11354 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 11355 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11356 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
sahilmgandhi 18:6a4db94011d3 11357 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11358 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11359 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11360 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 11361 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11362 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11363 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 11364 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11365 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11366 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11367 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11368 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11369 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
sahilmgandhi 18:6a4db94011d3 11370 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11371 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11372 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11373 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11374 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
sahilmgandhi 18:6a4db94011d3 11375
sahilmgandhi 18:6a4db94011d3 11376 /******************** Bit definition for RCC_BDCR register ******************/
sahilmgandhi 18:6a4db94011d3 11377 #define RCC_BDCR_LSEON_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11378 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11379 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
sahilmgandhi 18:6a4db94011d3 11380 #define RCC_BDCR_LSERDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11381 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11382 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
sahilmgandhi 18:6a4db94011d3 11383 #define RCC_BDCR_LSEBYP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 11384 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11385 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
sahilmgandhi 18:6a4db94011d3 11386
sahilmgandhi 18:6a4db94011d3 11387 #define RCC_BDCR_RTCSEL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11388 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 11389 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
sahilmgandhi 18:6a4db94011d3 11390 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11391 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11392
sahilmgandhi 18:6a4db94011d3 11393 #define RCC_BDCR_RTCEN_Pos (15U)
sahilmgandhi 18:6a4db94011d3 11394 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 11395 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
sahilmgandhi 18:6a4db94011d3 11396 #define RCC_BDCR_BDRST_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11397 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11398 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
sahilmgandhi 18:6a4db94011d3 11399
sahilmgandhi 18:6a4db94011d3 11400 /******************** Bit definition for RCC_CSR register *******************/
sahilmgandhi 18:6a4db94011d3 11401 #define RCC_CSR_LSION_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11402 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11403 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
sahilmgandhi 18:6a4db94011d3 11404 #define RCC_CSR_LSIRDY_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11405 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11406 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
sahilmgandhi 18:6a4db94011d3 11407 #define RCC_CSR_RMVF_Pos (24U)
sahilmgandhi 18:6a4db94011d3 11408 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 11409 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
sahilmgandhi 18:6a4db94011d3 11410 #define RCC_CSR_BORRSTF_Pos (25U)
sahilmgandhi 18:6a4db94011d3 11411 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 11412 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
sahilmgandhi 18:6a4db94011d3 11413 #define RCC_CSR_PADRSTF_Pos (26U)
sahilmgandhi 18:6a4db94011d3 11414 #define RCC_CSR_PADRSTF_Msk (0x1U << RCC_CSR_PADRSTF_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 11415 #define RCC_CSR_PADRSTF RCC_CSR_PADRSTF_Msk
sahilmgandhi 18:6a4db94011d3 11416 #define RCC_CSR_PORRSTF_Pos (27U)
sahilmgandhi 18:6a4db94011d3 11417 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 11418 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
sahilmgandhi 18:6a4db94011d3 11419 #define RCC_CSR_SFTRSTF_Pos (28U)
sahilmgandhi 18:6a4db94011d3 11420 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 11421 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
sahilmgandhi 18:6a4db94011d3 11422 #define RCC_CSR_WDGRSTF_Pos (29U)
sahilmgandhi 18:6a4db94011d3 11423 #define RCC_CSR_WDGRSTF_Msk (0x1U << RCC_CSR_WDGRSTF_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 11424 #define RCC_CSR_WDGRSTF RCC_CSR_WDGRSTF_Msk
sahilmgandhi 18:6a4db94011d3 11425 #define RCC_CSR_WWDGRSTF_Pos (30U)
sahilmgandhi 18:6a4db94011d3 11426 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11427 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
sahilmgandhi 18:6a4db94011d3 11428 #define RCC_CSR_LPWRRSTF_Pos (31U)
sahilmgandhi 18:6a4db94011d3 11429 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 11430 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
sahilmgandhi 18:6a4db94011d3 11431
sahilmgandhi 18:6a4db94011d3 11432 /******************** Bit definition for RCC_SSCGR register *****************/
sahilmgandhi 18:6a4db94011d3 11433 #define RCC_SSCGR_MODPER_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11434 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
sahilmgandhi 18:6a4db94011d3 11435 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
sahilmgandhi 18:6a4db94011d3 11436 #define RCC_SSCGR_INCSTEP_Pos (13U)
sahilmgandhi 18:6a4db94011d3 11437 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
sahilmgandhi 18:6a4db94011d3 11438 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
sahilmgandhi 18:6a4db94011d3 11439 #define RCC_SSCGR_SPREADSEL_Pos (30U)
sahilmgandhi 18:6a4db94011d3 11440 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11441 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
sahilmgandhi 18:6a4db94011d3 11442 #define RCC_SSCGR_SSCGEN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 11443 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 11444 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
sahilmgandhi 18:6a4db94011d3 11445
sahilmgandhi 18:6a4db94011d3 11446 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
sahilmgandhi 18:6a4db94011d3 11447 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11448 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
sahilmgandhi 18:6a4db94011d3 11449 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
sahilmgandhi 18:6a4db94011d3 11450 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11451 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11452 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11453 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11454 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11455 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11456 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11457 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11458 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11459
sahilmgandhi 18:6a4db94011d3 11460 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
sahilmgandhi 18:6a4db94011d3 11461 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 11462 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
sahilmgandhi 18:6a4db94011d3 11463 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 11464 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 11465 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 11466 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 11467 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
sahilmgandhi 18:6a4db94011d3 11468 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
sahilmgandhi 18:6a4db94011d3 11469 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
sahilmgandhi 18:6a4db94011d3 11470 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 11471 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 11472 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11473
sahilmgandhi 18:6a4db94011d3 11474 /******************** Bit definition for RCC_PLLSAICFGR register ************/
sahilmgandhi 18:6a4db94011d3 11475 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11476 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
sahilmgandhi 18:6a4db94011d3 11477 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
sahilmgandhi 18:6a4db94011d3 11478 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11479 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11480 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11481 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11482 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11483 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11484 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11485 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11486 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11487
sahilmgandhi 18:6a4db94011d3 11488
sahilmgandhi 18:6a4db94011d3 11489 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
sahilmgandhi 18:6a4db94011d3 11490 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 11491 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
sahilmgandhi 18:6a4db94011d3 11492 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 11493 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 11494 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 11495 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 11496
sahilmgandhi 18:6a4db94011d3 11497 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
sahilmgandhi 18:6a4db94011d3 11498 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
sahilmgandhi 18:6a4db94011d3 11499 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
sahilmgandhi 18:6a4db94011d3 11500 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 11501 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 11502 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11503
sahilmgandhi 18:6a4db94011d3 11504 /******************** Bit definition for RCC_DCKCFGR register ***************/
sahilmgandhi 18:6a4db94011d3 11505 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11506 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 11507 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
sahilmgandhi 18:6a4db94011d3 11508 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11509 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
sahilmgandhi 18:6a4db94011d3 11510 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
sahilmgandhi 18:6a4db94011d3 11511 #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11512 #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 11513 #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
sahilmgandhi 18:6a4db94011d3 11514 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11515 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 11516 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
sahilmgandhi 18:6a4db94011d3 11517 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11518 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11519 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11520 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
sahilmgandhi 18:6a4db94011d3 11521 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
sahilmgandhi 18:6a4db94011d3 11522 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11523 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 11524 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
sahilmgandhi 18:6a4db94011d3 11525 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 11526 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
sahilmgandhi 18:6a4db94011d3 11527
sahilmgandhi 18:6a4db94011d3 11528
sahilmgandhi 18:6a4db94011d3 11529 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 11530 /* */
sahilmgandhi 18:6a4db94011d3 11531 /* RNG */
sahilmgandhi 18:6a4db94011d3 11532 /* */
sahilmgandhi 18:6a4db94011d3 11533 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 11534 /******************** Bits definition for RNG_CR register *******************/
sahilmgandhi 18:6a4db94011d3 11535 #define RNG_CR_RNGEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 11536 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11537 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
sahilmgandhi 18:6a4db94011d3 11538 #define RNG_CR_IE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 11539 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11540 #define RNG_CR_IE RNG_CR_IE_Msk
sahilmgandhi 18:6a4db94011d3 11541
sahilmgandhi 18:6a4db94011d3 11542 /******************** Bits definition for RNG_SR register *******************/
sahilmgandhi 18:6a4db94011d3 11543 #define RNG_SR_DRDY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11544 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11545 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
sahilmgandhi 18:6a4db94011d3 11546 #define RNG_SR_CECS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11547 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11548 #define RNG_SR_CECS RNG_SR_CECS_Msk
sahilmgandhi 18:6a4db94011d3 11549 #define RNG_SR_SECS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 11550 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11551 #define RNG_SR_SECS RNG_SR_SECS_Msk
sahilmgandhi 18:6a4db94011d3 11552 #define RNG_SR_CEIS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11553 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11554 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
sahilmgandhi 18:6a4db94011d3 11555 #define RNG_SR_SEIS_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11556 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11557 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
sahilmgandhi 18:6a4db94011d3 11558
sahilmgandhi 18:6a4db94011d3 11559 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 11560 /* */
sahilmgandhi 18:6a4db94011d3 11561 /* Real-Time Clock (RTC) */
sahilmgandhi 18:6a4db94011d3 11562 /* */
sahilmgandhi 18:6a4db94011d3 11563 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 11564 /******************** Bits definition for RTC_TR register *******************/
sahilmgandhi 18:6a4db94011d3 11565 #define RTC_TR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11566 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11567 #define RTC_TR_PM RTC_TR_PM_Msk
sahilmgandhi 18:6a4db94011d3 11568 #define RTC_TR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11569 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 11570 #define RTC_TR_HT RTC_TR_HT_Msk
sahilmgandhi 18:6a4db94011d3 11571 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11572 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11573 #define RTC_TR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11574 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 11575 #define RTC_TR_HU RTC_TR_HU_Msk
sahilmgandhi 18:6a4db94011d3 11576 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11577 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11578 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11579 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11580 #define RTC_TR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11581 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 11582 #define RTC_TR_MNT RTC_TR_MNT_Msk
sahilmgandhi 18:6a4db94011d3 11583 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11584 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11585 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11586 #define RTC_TR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11587 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 11588 #define RTC_TR_MNU RTC_TR_MNU_Msk
sahilmgandhi 18:6a4db94011d3 11589 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11590 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11591 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11592 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11593 #define RTC_TR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11594 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 11595 #define RTC_TR_ST RTC_TR_ST_Msk
sahilmgandhi 18:6a4db94011d3 11596 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11597 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11598 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11599 #define RTC_TR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11600 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 11601 #define RTC_TR_SU RTC_TR_SU_Msk
sahilmgandhi 18:6a4db94011d3 11602 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11603 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11604 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11605 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11606
sahilmgandhi 18:6a4db94011d3 11607 /******************** Bits definition for RTC_DR register *******************/
sahilmgandhi 18:6a4db94011d3 11608 #define RTC_DR_YT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11609 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 11610 #define RTC_DR_YT RTC_DR_YT_Msk
sahilmgandhi 18:6a4db94011d3 11611 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11612 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11613 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11614 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 11615 #define RTC_DR_YU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11616 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 11617 #define RTC_DR_YU RTC_DR_YU_Msk
sahilmgandhi 18:6a4db94011d3 11618 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11619 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11620 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11621 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11622 #define RTC_DR_WDU_Pos (13U)
sahilmgandhi 18:6a4db94011d3 11623 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 11624 #define RTC_DR_WDU RTC_DR_WDU_Msk
sahilmgandhi 18:6a4db94011d3 11625 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11626 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11627 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 11628 #define RTC_DR_MT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11629 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11630 #define RTC_DR_MT RTC_DR_MT_Msk
sahilmgandhi 18:6a4db94011d3 11631 #define RTC_DR_MU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11632 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 11633 #define RTC_DR_MU RTC_DR_MU_Msk
sahilmgandhi 18:6a4db94011d3 11634 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11635 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11636 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11637 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11638 #define RTC_DR_DT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11639 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 11640 #define RTC_DR_DT RTC_DR_DT_Msk
sahilmgandhi 18:6a4db94011d3 11641 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11642 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11643 #define RTC_DR_DU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11644 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 11645 #define RTC_DR_DU RTC_DR_DU_Msk
sahilmgandhi 18:6a4db94011d3 11646 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11647 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11648 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11649 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11650
sahilmgandhi 18:6a4db94011d3 11651 /******************** Bits definition for RTC_CR register *******************/
sahilmgandhi 18:6a4db94011d3 11652 #define RTC_CR_COE_Pos (23U)
sahilmgandhi 18:6a4db94011d3 11653 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 11654 #define RTC_CR_COE RTC_CR_COE_Msk
sahilmgandhi 18:6a4db94011d3 11655 #define RTC_CR_OSEL_Pos (21U)
sahilmgandhi 18:6a4db94011d3 11656 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
sahilmgandhi 18:6a4db94011d3 11657 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
sahilmgandhi 18:6a4db94011d3 11658 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11659 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11660 #define RTC_CR_POL_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11661 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11662 #define RTC_CR_POL RTC_CR_POL_Msk
sahilmgandhi 18:6a4db94011d3 11663 #define RTC_CR_COSEL_Pos (19U)
sahilmgandhi 18:6a4db94011d3 11664 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11665 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
sahilmgandhi 18:6a4db94011d3 11666 #define RTC_CR_BCK_Pos (18U)
sahilmgandhi 18:6a4db94011d3 11667 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11668 #define RTC_CR_BCK RTC_CR_BCK_Msk
sahilmgandhi 18:6a4db94011d3 11669 #define RTC_CR_SUB1H_Pos (17U)
sahilmgandhi 18:6a4db94011d3 11670 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11671 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
sahilmgandhi 18:6a4db94011d3 11672 #define RTC_CR_ADD1H_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11673 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11674 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
sahilmgandhi 18:6a4db94011d3 11675 #define RTC_CR_TSIE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 11676 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 11677 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
sahilmgandhi 18:6a4db94011d3 11678 #define RTC_CR_WUTIE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 11679 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11680 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
sahilmgandhi 18:6a4db94011d3 11681 #define RTC_CR_ALRBIE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 11682 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11683 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
sahilmgandhi 18:6a4db94011d3 11684 #define RTC_CR_ALRAIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11685 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11686 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
sahilmgandhi 18:6a4db94011d3 11687 #define RTC_CR_TSE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 11688 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11689 #define RTC_CR_TSE RTC_CR_TSE_Msk
sahilmgandhi 18:6a4db94011d3 11690 #define RTC_CR_WUTE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 11691 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11692 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
sahilmgandhi 18:6a4db94011d3 11693 #define RTC_CR_ALRBE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 11694 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11695 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
sahilmgandhi 18:6a4db94011d3 11696 #define RTC_CR_ALRAE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11697 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11698 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
sahilmgandhi 18:6a4db94011d3 11699 #define RTC_CR_DCE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11700 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11701 #define RTC_CR_DCE RTC_CR_DCE_Msk
sahilmgandhi 18:6a4db94011d3 11702 #define RTC_CR_FMT_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11703 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11704 #define RTC_CR_FMT RTC_CR_FMT_Msk
sahilmgandhi 18:6a4db94011d3 11705 #define RTC_CR_BYPSHAD_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11706 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11707 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
sahilmgandhi 18:6a4db94011d3 11708 #define RTC_CR_REFCKON_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11709 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11710 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
sahilmgandhi 18:6a4db94011d3 11711 #define RTC_CR_TSEDGE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 11712 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11713 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
sahilmgandhi 18:6a4db94011d3 11714 #define RTC_CR_WUCKSEL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11715 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 11716 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
sahilmgandhi 18:6a4db94011d3 11717 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11718 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11719 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11720
sahilmgandhi 18:6a4db94011d3 11721 /******************** Bits definition for RTC_ISR register ******************/
sahilmgandhi 18:6a4db94011d3 11722 #define RTC_ISR_RECALPF_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11723 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11724 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
sahilmgandhi 18:6a4db94011d3 11725 #define RTC_ISR_TAMP1F_Pos (13U)
sahilmgandhi 18:6a4db94011d3 11726 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11727 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
sahilmgandhi 18:6a4db94011d3 11728 #define RTC_ISR_TAMP2F_Pos (14U)
sahilmgandhi 18:6a4db94011d3 11729 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11730 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
sahilmgandhi 18:6a4db94011d3 11731 #define RTC_ISR_TSOVF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11732 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11733 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
sahilmgandhi 18:6a4db94011d3 11734 #define RTC_ISR_TSF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 11735 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11736 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
sahilmgandhi 18:6a4db94011d3 11737 #define RTC_ISR_WUTF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 11738 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11739 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
sahilmgandhi 18:6a4db94011d3 11740 #define RTC_ISR_ALRBF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 11741 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11742 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
sahilmgandhi 18:6a4db94011d3 11743 #define RTC_ISR_ALRAF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11744 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11745 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
sahilmgandhi 18:6a4db94011d3 11746 #define RTC_ISR_INIT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11747 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11748 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
sahilmgandhi 18:6a4db94011d3 11749 #define RTC_ISR_INITF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 11750 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11751 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
sahilmgandhi 18:6a4db94011d3 11752 #define RTC_ISR_RSF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 11753 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11754 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
sahilmgandhi 18:6a4db94011d3 11755 #define RTC_ISR_INITS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11756 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11757 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
sahilmgandhi 18:6a4db94011d3 11758 #define RTC_ISR_SHPF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 11759 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11760 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
sahilmgandhi 18:6a4db94011d3 11761 #define RTC_ISR_WUTWF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 11762 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11763 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
sahilmgandhi 18:6a4db94011d3 11764 #define RTC_ISR_ALRBWF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 11765 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11766 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
sahilmgandhi 18:6a4db94011d3 11767 #define RTC_ISR_ALRAWF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11768 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11769 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
sahilmgandhi 18:6a4db94011d3 11770
sahilmgandhi 18:6a4db94011d3 11771 /******************** Bits definition for RTC_PRER register *****************/
sahilmgandhi 18:6a4db94011d3 11772 #define RTC_PRER_PREDIV_A_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11773 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
sahilmgandhi 18:6a4db94011d3 11774 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
sahilmgandhi 18:6a4db94011d3 11775 #define RTC_PRER_PREDIV_S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11776 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 11777 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
sahilmgandhi 18:6a4db94011d3 11778
sahilmgandhi 18:6a4db94011d3 11779 /******************** Bits definition for RTC_WUTR register *****************/
sahilmgandhi 18:6a4db94011d3 11780 #define RTC_WUTR_WUT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11781 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 11782 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
sahilmgandhi 18:6a4db94011d3 11783
sahilmgandhi 18:6a4db94011d3 11784 /******************** Bits definition for RTC_CALIBR register ***************/
sahilmgandhi 18:6a4db94011d3 11785 #define RTC_CALIBR_DCS_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11786 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11787 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
sahilmgandhi 18:6a4db94011d3 11788 #define RTC_CALIBR_DC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11789 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 11790 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
sahilmgandhi 18:6a4db94011d3 11791
sahilmgandhi 18:6a4db94011d3 11792 /******************** Bits definition for RTC_ALRMAR register ***************/
sahilmgandhi 18:6a4db94011d3 11793 #define RTC_ALRMAR_MSK4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 11794 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 11795 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
sahilmgandhi 18:6a4db94011d3 11796 #define RTC_ALRMAR_WDSEL_Pos (30U)
sahilmgandhi 18:6a4db94011d3 11797 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11798 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
sahilmgandhi 18:6a4db94011d3 11799 #define RTC_ALRMAR_DT_Pos (28U)
sahilmgandhi 18:6a4db94011d3 11800 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 11801 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
sahilmgandhi 18:6a4db94011d3 11802 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 11803 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 11804 #define RTC_ALRMAR_DU_Pos (24U)
sahilmgandhi 18:6a4db94011d3 11805 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 11806 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
sahilmgandhi 18:6a4db94011d3 11807 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 11808 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 11809 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 11810 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 11811 #define RTC_ALRMAR_MSK3_Pos (23U)
sahilmgandhi 18:6a4db94011d3 11812 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 11813 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
sahilmgandhi 18:6a4db94011d3 11814 #define RTC_ALRMAR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11815 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11816 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
sahilmgandhi 18:6a4db94011d3 11817 #define RTC_ALRMAR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11818 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 11819 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
sahilmgandhi 18:6a4db94011d3 11820 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11821 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11822 #define RTC_ALRMAR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11823 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 11824 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
sahilmgandhi 18:6a4db94011d3 11825 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11826 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11827 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11828 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11829 #define RTC_ALRMAR_MSK2_Pos (15U)
sahilmgandhi 18:6a4db94011d3 11830 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 11831 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
sahilmgandhi 18:6a4db94011d3 11832 #define RTC_ALRMAR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11833 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 11834 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
sahilmgandhi 18:6a4db94011d3 11835 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11836 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11837 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11838 #define RTC_ALRMAR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11839 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 11840 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
sahilmgandhi 18:6a4db94011d3 11841 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11842 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11843 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11844 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11845 #define RTC_ALRMAR_MSK1_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11846 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11847 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
sahilmgandhi 18:6a4db94011d3 11848 #define RTC_ALRMAR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11849 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 11850 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
sahilmgandhi 18:6a4db94011d3 11851 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11852 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11853 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11854 #define RTC_ALRMAR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11855 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 11856 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
sahilmgandhi 18:6a4db94011d3 11857 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11858 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11859 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11860 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11861
sahilmgandhi 18:6a4db94011d3 11862 /******************** Bits definition for RTC_ALRMBR register ***************/
sahilmgandhi 18:6a4db94011d3 11863 #define RTC_ALRMBR_MSK4_Pos (31U)
sahilmgandhi 18:6a4db94011d3 11864 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 11865 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
sahilmgandhi 18:6a4db94011d3 11866 #define RTC_ALRMBR_WDSEL_Pos (30U)
sahilmgandhi 18:6a4db94011d3 11867 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 11868 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
sahilmgandhi 18:6a4db94011d3 11869 #define RTC_ALRMBR_DT_Pos (28U)
sahilmgandhi 18:6a4db94011d3 11870 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
sahilmgandhi 18:6a4db94011d3 11871 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
sahilmgandhi 18:6a4db94011d3 11872 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 11873 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 11874 #define RTC_ALRMBR_DU_Pos (24U)
sahilmgandhi 18:6a4db94011d3 11875 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 11876 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
sahilmgandhi 18:6a4db94011d3 11877 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 11878 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 11879 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 11880 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 11881 #define RTC_ALRMBR_MSK3_Pos (23U)
sahilmgandhi 18:6a4db94011d3 11882 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 11883 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
sahilmgandhi 18:6a4db94011d3 11884 #define RTC_ALRMBR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11885 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11886 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
sahilmgandhi 18:6a4db94011d3 11887 #define RTC_ALRMBR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11888 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 11889 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
sahilmgandhi 18:6a4db94011d3 11890 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11891 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11892 #define RTC_ALRMBR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11893 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 11894 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
sahilmgandhi 18:6a4db94011d3 11895 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11896 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11897 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11898 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11899 #define RTC_ALRMBR_MSK2_Pos (15U)
sahilmgandhi 18:6a4db94011d3 11900 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 11901 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
sahilmgandhi 18:6a4db94011d3 11902 #define RTC_ALRMBR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11903 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 11904 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
sahilmgandhi 18:6a4db94011d3 11905 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11906 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11907 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11908 #define RTC_ALRMBR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11909 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 11910 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
sahilmgandhi 18:6a4db94011d3 11911 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11912 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11913 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11914 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11915 #define RTC_ALRMBR_MSK1_Pos (7U)
sahilmgandhi 18:6a4db94011d3 11916 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 11917 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
sahilmgandhi 18:6a4db94011d3 11918 #define RTC_ALRMBR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11919 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 11920 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
sahilmgandhi 18:6a4db94011d3 11921 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11922 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11923 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11924 #define RTC_ALRMBR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11925 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 11926 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
sahilmgandhi 18:6a4db94011d3 11927 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11928 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11929 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11930 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11931
sahilmgandhi 18:6a4db94011d3 11932 /******************** Bits definition for RTC_WPR register ******************/
sahilmgandhi 18:6a4db94011d3 11933 #define RTC_WPR_KEY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11934 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 11935 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
sahilmgandhi 18:6a4db94011d3 11936
sahilmgandhi 18:6a4db94011d3 11937 /******************** Bits definition for RTC_SSR register ******************/
sahilmgandhi 18:6a4db94011d3 11938 #define RTC_SSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11939 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 11940 #define RTC_SSR_SS RTC_SSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 11941
sahilmgandhi 18:6a4db94011d3 11942 /******************** Bits definition for RTC_SHIFTR register ***************/
sahilmgandhi 18:6a4db94011d3 11943 #define RTC_SHIFTR_SUBFS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11944 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 11945 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
sahilmgandhi 18:6a4db94011d3 11946 #define RTC_SHIFTR_ADD1S_Pos (31U)
sahilmgandhi 18:6a4db94011d3 11947 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 11948 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
sahilmgandhi 18:6a4db94011d3 11949
sahilmgandhi 18:6a4db94011d3 11950 /******************** Bits definition for RTC_TSTR register *****************/
sahilmgandhi 18:6a4db94011d3 11951 #define RTC_TSTR_PM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 11952 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 11953 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
sahilmgandhi 18:6a4db94011d3 11954 #define RTC_TSTR_HT_Pos (20U)
sahilmgandhi 18:6a4db94011d3 11955 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 11956 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
sahilmgandhi 18:6a4db94011d3 11957 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 11958 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 11959 #define RTC_TSTR_HU_Pos (16U)
sahilmgandhi 18:6a4db94011d3 11960 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
sahilmgandhi 18:6a4db94011d3 11961 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
sahilmgandhi 18:6a4db94011d3 11962 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 11963 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 11964 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 11965 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 11966 #define RTC_TSTR_MNT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 11967 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 11968 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
sahilmgandhi 18:6a4db94011d3 11969 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 11970 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11971 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11972 #define RTC_TSTR_MNU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 11973 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 11974 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
sahilmgandhi 18:6a4db94011d3 11975 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 11976 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 11977 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 11978 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 11979 #define RTC_TSTR_ST_Pos (4U)
sahilmgandhi 18:6a4db94011d3 11980 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 11981 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
sahilmgandhi 18:6a4db94011d3 11982 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 11983 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 11984 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 11985 #define RTC_TSTR_SU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 11986 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 11987 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
sahilmgandhi 18:6a4db94011d3 11988 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 11989 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 11990 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 11991 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 11992
sahilmgandhi 18:6a4db94011d3 11993 /******************** Bits definition for RTC_TSDR register *****************/
sahilmgandhi 18:6a4db94011d3 11994 #define RTC_TSDR_WDU_Pos (13U)
sahilmgandhi 18:6a4db94011d3 11995 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
sahilmgandhi 18:6a4db94011d3 11996 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
sahilmgandhi 18:6a4db94011d3 11997 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 11998 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 11999 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 12000 #define RTC_TSDR_MT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 12001 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12002 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
sahilmgandhi 18:6a4db94011d3 12003 #define RTC_TSDR_MU_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12004 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 12005 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
sahilmgandhi 18:6a4db94011d3 12006 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12007 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12008 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12009 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12010 #define RTC_TSDR_DT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12011 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 12012 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
sahilmgandhi 18:6a4db94011d3 12013 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12014 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12015 #define RTC_TSDR_DU_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12016 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 12017 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
sahilmgandhi 18:6a4db94011d3 12018 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12019 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12020 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12021 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12022
sahilmgandhi 18:6a4db94011d3 12023 /******************** Bits definition for RTC_TSSSR register ****************/
sahilmgandhi 18:6a4db94011d3 12024 #define RTC_TSSSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12025 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 12026 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 12027
sahilmgandhi 18:6a4db94011d3 12028 /******************** Bits definition for RTC_CAL register *****************/
sahilmgandhi 18:6a4db94011d3 12029 #define RTC_CALR_CALP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 12030 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 12031 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
sahilmgandhi 18:6a4db94011d3 12032 #define RTC_CALR_CALW8_Pos (14U)
sahilmgandhi 18:6a4db94011d3 12033 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12034 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
sahilmgandhi 18:6a4db94011d3 12035 #define RTC_CALR_CALW16_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12036 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12037 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
sahilmgandhi 18:6a4db94011d3 12038 #define RTC_CALR_CALM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12039 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
sahilmgandhi 18:6a4db94011d3 12040 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
sahilmgandhi 18:6a4db94011d3 12041 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12042 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12043 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12044 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12045 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12046 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12047 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12048 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12049 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12050
sahilmgandhi 18:6a4db94011d3 12051 /******************** Bits definition for RTC_TAFCR register ****************/
sahilmgandhi 18:6a4db94011d3 12052 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
sahilmgandhi 18:6a4db94011d3 12053 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 12054 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
sahilmgandhi 18:6a4db94011d3 12055 #define RTC_TAFCR_TSINSEL_Pos (17U)
sahilmgandhi 18:6a4db94011d3 12056 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 12057 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
sahilmgandhi 18:6a4db94011d3 12058 #define RTC_TAFCR_TAMPINSEL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 12059 #define RTC_TAFCR_TAMPINSEL_Msk (0x1U << RTC_TAFCR_TAMPINSEL_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 12060 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMPINSEL_Msk
sahilmgandhi 18:6a4db94011d3 12061 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
sahilmgandhi 18:6a4db94011d3 12062 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 12063 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
sahilmgandhi 18:6a4db94011d3 12064 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12065 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
sahilmgandhi 18:6a4db94011d3 12066 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
sahilmgandhi 18:6a4db94011d3 12067 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12068 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12069 #define RTC_TAFCR_TAMPFLT_Pos (11U)
sahilmgandhi 18:6a4db94011d3 12070 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 12071 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
sahilmgandhi 18:6a4db94011d3 12072 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12073 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12074 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12075 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
sahilmgandhi 18:6a4db94011d3 12076 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
sahilmgandhi 18:6a4db94011d3 12077 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12078 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12079 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12080 #define RTC_TAFCR_TAMPTS_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12081 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12082 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
sahilmgandhi 18:6a4db94011d3 12083 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12084 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12085 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
sahilmgandhi 18:6a4db94011d3 12086 #define RTC_TAFCR_TAMP2E_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12087 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12088 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
sahilmgandhi 18:6a4db94011d3 12089 #define RTC_TAFCR_TAMPIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12090 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12091 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
sahilmgandhi 18:6a4db94011d3 12092 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12093 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12094 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
sahilmgandhi 18:6a4db94011d3 12095 #define RTC_TAFCR_TAMP1E_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12096 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12097 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
sahilmgandhi 18:6a4db94011d3 12098
sahilmgandhi 18:6a4db94011d3 12099 /******************** Bits definition for RTC_ALRMASSR register *************/
sahilmgandhi 18:6a4db94011d3 12100 #define RTC_ALRMASSR_MASKSS_Pos (24U)
sahilmgandhi 18:6a4db94011d3 12101 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 12102 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
sahilmgandhi 18:6a4db94011d3 12103 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 12104 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 12105 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 12106 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 12107 #define RTC_ALRMASSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12108 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 12109 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 12110
sahilmgandhi 18:6a4db94011d3 12111 /******************** Bits definition for RTC_ALRMBSSR register *************/
sahilmgandhi 18:6a4db94011d3 12112 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
sahilmgandhi 18:6a4db94011d3 12113 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
sahilmgandhi 18:6a4db94011d3 12114 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
sahilmgandhi 18:6a4db94011d3 12115 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 12116 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 12117 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 12118 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 12119 #define RTC_ALRMBSSR_SS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12120 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
sahilmgandhi 18:6a4db94011d3 12121 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
sahilmgandhi 18:6a4db94011d3 12122
sahilmgandhi 18:6a4db94011d3 12123 /******************** Bits definition for RTC_BKP0R register ****************/
sahilmgandhi 18:6a4db94011d3 12124 #define RTC_BKP0R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12125 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12126 #define RTC_BKP0R RTC_BKP0R_Msk
sahilmgandhi 18:6a4db94011d3 12127
sahilmgandhi 18:6a4db94011d3 12128 /******************** Bits definition for RTC_BKP1R register ****************/
sahilmgandhi 18:6a4db94011d3 12129 #define RTC_BKP1R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12130 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12131 #define RTC_BKP1R RTC_BKP1R_Msk
sahilmgandhi 18:6a4db94011d3 12132
sahilmgandhi 18:6a4db94011d3 12133 /******************** Bits definition for RTC_BKP2R register ****************/
sahilmgandhi 18:6a4db94011d3 12134 #define RTC_BKP2R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12135 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12136 #define RTC_BKP2R RTC_BKP2R_Msk
sahilmgandhi 18:6a4db94011d3 12137
sahilmgandhi 18:6a4db94011d3 12138 /******************** Bits definition for RTC_BKP3R register ****************/
sahilmgandhi 18:6a4db94011d3 12139 #define RTC_BKP3R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12140 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12141 #define RTC_BKP3R RTC_BKP3R_Msk
sahilmgandhi 18:6a4db94011d3 12142
sahilmgandhi 18:6a4db94011d3 12143 /******************** Bits definition for RTC_BKP4R register ****************/
sahilmgandhi 18:6a4db94011d3 12144 #define RTC_BKP4R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12145 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12146 #define RTC_BKP4R RTC_BKP4R_Msk
sahilmgandhi 18:6a4db94011d3 12147
sahilmgandhi 18:6a4db94011d3 12148 /******************** Bits definition for RTC_BKP5R register ****************/
sahilmgandhi 18:6a4db94011d3 12149 #define RTC_BKP5R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12150 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12151 #define RTC_BKP5R RTC_BKP5R_Msk
sahilmgandhi 18:6a4db94011d3 12152
sahilmgandhi 18:6a4db94011d3 12153 /******************** Bits definition for RTC_BKP6R register ****************/
sahilmgandhi 18:6a4db94011d3 12154 #define RTC_BKP6R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12155 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12156 #define RTC_BKP6R RTC_BKP6R_Msk
sahilmgandhi 18:6a4db94011d3 12157
sahilmgandhi 18:6a4db94011d3 12158 /******************** Bits definition for RTC_BKP7R register ****************/
sahilmgandhi 18:6a4db94011d3 12159 #define RTC_BKP7R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12160 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12161 #define RTC_BKP7R RTC_BKP7R_Msk
sahilmgandhi 18:6a4db94011d3 12162
sahilmgandhi 18:6a4db94011d3 12163 /******************** Bits definition for RTC_BKP8R register ****************/
sahilmgandhi 18:6a4db94011d3 12164 #define RTC_BKP8R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12165 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12166 #define RTC_BKP8R RTC_BKP8R_Msk
sahilmgandhi 18:6a4db94011d3 12167
sahilmgandhi 18:6a4db94011d3 12168 /******************** Bits definition for RTC_BKP9R register ****************/
sahilmgandhi 18:6a4db94011d3 12169 #define RTC_BKP9R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12170 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12171 #define RTC_BKP9R RTC_BKP9R_Msk
sahilmgandhi 18:6a4db94011d3 12172
sahilmgandhi 18:6a4db94011d3 12173 /******************** Bits definition for RTC_BKP10R register ***************/
sahilmgandhi 18:6a4db94011d3 12174 #define RTC_BKP10R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12175 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12176 #define RTC_BKP10R RTC_BKP10R_Msk
sahilmgandhi 18:6a4db94011d3 12177
sahilmgandhi 18:6a4db94011d3 12178 /******************** Bits definition for RTC_BKP11R register ***************/
sahilmgandhi 18:6a4db94011d3 12179 #define RTC_BKP11R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12180 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12181 #define RTC_BKP11R RTC_BKP11R_Msk
sahilmgandhi 18:6a4db94011d3 12182
sahilmgandhi 18:6a4db94011d3 12183 /******************** Bits definition for RTC_BKP12R register ***************/
sahilmgandhi 18:6a4db94011d3 12184 #define RTC_BKP12R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12185 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12186 #define RTC_BKP12R RTC_BKP12R_Msk
sahilmgandhi 18:6a4db94011d3 12187
sahilmgandhi 18:6a4db94011d3 12188 /******************** Bits definition for RTC_BKP13R register ***************/
sahilmgandhi 18:6a4db94011d3 12189 #define RTC_BKP13R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12190 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12191 #define RTC_BKP13R RTC_BKP13R_Msk
sahilmgandhi 18:6a4db94011d3 12192
sahilmgandhi 18:6a4db94011d3 12193 /******************** Bits definition for RTC_BKP14R register ***************/
sahilmgandhi 18:6a4db94011d3 12194 #define RTC_BKP14R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12195 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12196 #define RTC_BKP14R RTC_BKP14R_Msk
sahilmgandhi 18:6a4db94011d3 12197
sahilmgandhi 18:6a4db94011d3 12198 /******************** Bits definition for RTC_BKP15R register ***************/
sahilmgandhi 18:6a4db94011d3 12199 #define RTC_BKP15R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12200 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12201 #define RTC_BKP15R RTC_BKP15R_Msk
sahilmgandhi 18:6a4db94011d3 12202
sahilmgandhi 18:6a4db94011d3 12203 /******************** Bits definition for RTC_BKP16R register ***************/
sahilmgandhi 18:6a4db94011d3 12204 #define RTC_BKP16R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12205 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12206 #define RTC_BKP16R RTC_BKP16R_Msk
sahilmgandhi 18:6a4db94011d3 12207
sahilmgandhi 18:6a4db94011d3 12208 /******************** Bits definition for RTC_BKP17R register ***************/
sahilmgandhi 18:6a4db94011d3 12209 #define RTC_BKP17R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12210 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12211 #define RTC_BKP17R RTC_BKP17R_Msk
sahilmgandhi 18:6a4db94011d3 12212
sahilmgandhi 18:6a4db94011d3 12213 /******************** Bits definition for RTC_BKP18R register ***************/
sahilmgandhi 18:6a4db94011d3 12214 #define RTC_BKP18R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12215 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12216 #define RTC_BKP18R RTC_BKP18R_Msk
sahilmgandhi 18:6a4db94011d3 12217
sahilmgandhi 18:6a4db94011d3 12218 /******************** Bits definition for RTC_BKP19R register ***************/
sahilmgandhi 18:6a4db94011d3 12219 #define RTC_BKP19R_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12220 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12221 #define RTC_BKP19R RTC_BKP19R_Msk
sahilmgandhi 18:6a4db94011d3 12222
sahilmgandhi 18:6a4db94011d3 12223 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 12224 /* */
sahilmgandhi 18:6a4db94011d3 12225 /* Serial Audio Interface */
sahilmgandhi 18:6a4db94011d3 12226 /* */
sahilmgandhi 18:6a4db94011d3 12227 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 12228 /******************** Bit definition for SAI_GCR register *******************/
sahilmgandhi 18:6a4db94011d3 12229 #define SAI_GCR_SYNCIN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12230 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 12231 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
sahilmgandhi 18:6a4db94011d3 12232 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12233 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12234
sahilmgandhi 18:6a4db94011d3 12235 #define SAI_GCR_SYNCOUT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12236 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 12237 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
sahilmgandhi 18:6a4db94011d3 12238 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12239 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12240
sahilmgandhi 18:6a4db94011d3 12241 /******************* Bit definition for SAI_xCR1 register *******************/
sahilmgandhi 18:6a4db94011d3 12242 #define SAI_xCR1_MODE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12243 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 12244 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
sahilmgandhi 18:6a4db94011d3 12245 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12246 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12247
sahilmgandhi 18:6a4db94011d3 12248 #define SAI_xCR1_PRTCFG_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12249 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 12250 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
sahilmgandhi 18:6a4db94011d3 12251 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12252 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12253
sahilmgandhi 18:6a4db94011d3 12254 #define SAI_xCR1_DS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12255 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
sahilmgandhi 18:6a4db94011d3 12256 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
sahilmgandhi 18:6a4db94011d3 12257 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12258 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12259 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12260
sahilmgandhi 18:6a4db94011d3 12261 #define SAI_xCR1_LSBFIRST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12262 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12263 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
sahilmgandhi 18:6a4db94011d3 12264 #define SAI_xCR1_CKSTR_Pos (9U)
sahilmgandhi 18:6a4db94011d3 12265 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12266 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
sahilmgandhi 18:6a4db94011d3 12267
sahilmgandhi 18:6a4db94011d3 12268 #define SAI_xCR1_SYNCEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 12269 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 12270 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
sahilmgandhi 18:6a4db94011d3 12271 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12272 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12273
sahilmgandhi 18:6a4db94011d3 12274 #define SAI_xCR1_MONO_Pos (12U)
sahilmgandhi 18:6a4db94011d3 12275 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12276 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
sahilmgandhi 18:6a4db94011d3 12277 #define SAI_xCR1_OUTDRIV_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12278 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12279 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
sahilmgandhi 18:6a4db94011d3 12280 #define SAI_xCR1_SAIEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 12281 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 12282 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
sahilmgandhi 18:6a4db94011d3 12283 #define SAI_xCR1_DMAEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 12284 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 12285 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
sahilmgandhi 18:6a4db94011d3 12286 #define SAI_xCR1_NODIV_Pos (19U)
sahilmgandhi 18:6a4db94011d3 12287 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 12288 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
sahilmgandhi 18:6a4db94011d3 12289
sahilmgandhi 18:6a4db94011d3 12290 #define SAI_xCR1_MCKDIV_Pos (20U)
sahilmgandhi 18:6a4db94011d3 12291 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
sahilmgandhi 18:6a4db94011d3 12292 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
sahilmgandhi 18:6a4db94011d3 12293 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 12294 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 12295 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 12296 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 12297
sahilmgandhi 18:6a4db94011d3 12298 /******************* Bit definition for SAI_xCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 12299 #define SAI_xCR2_FTH_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12300 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 12301 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
sahilmgandhi 18:6a4db94011d3 12302 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12303 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12304 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12305
sahilmgandhi 18:6a4db94011d3 12306 #define SAI_xCR2_FFLUSH_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12307 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12308 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
sahilmgandhi 18:6a4db94011d3 12309 #define SAI_xCR2_TRIS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12310 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12311 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
sahilmgandhi 18:6a4db94011d3 12312 #define SAI_xCR2_MUTE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12313 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12314 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
sahilmgandhi 18:6a4db94011d3 12315 #define SAI_xCR2_MUTEVAL_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12316 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12317 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
sahilmgandhi 18:6a4db94011d3 12318
sahilmgandhi 18:6a4db94011d3 12319 #define SAI_xCR2_MUTECNT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12320 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
sahilmgandhi 18:6a4db94011d3 12321 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
sahilmgandhi 18:6a4db94011d3 12322 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12323 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12324 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12325 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12326 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12327 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12328
sahilmgandhi 18:6a4db94011d3 12329 #define SAI_xCR2_CPL_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12330 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12331 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
sahilmgandhi 18:6a4db94011d3 12332
sahilmgandhi 18:6a4db94011d3 12333 #define SAI_xCR2_COMP_Pos (14U)
sahilmgandhi 18:6a4db94011d3 12334 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 12335 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
sahilmgandhi 18:6a4db94011d3 12336 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12337 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 12338
sahilmgandhi 18:6a4db94011d3 12339 /****************** Bit definition for SAI_xFRCR register *******************/
sahilmgandhi 18:6a4db94011d3 12340 #define SAI_xFRCR_FRL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12341 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 12342 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
sahilmgandhi 18:6a4db94011d3 12343 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12344 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12345 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12346 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12347 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12348 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12349 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12350 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12351
sahilmgandhi 18:6a4db94011d3 12352 #define SAI_xFRCR_FSALL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12353 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
sahilmgandhi 18:6a4db94011d3 12354 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
sahilmgandhi 18:6a4db94011d3 12355 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12356 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12357 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12358 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12359 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12360 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12361 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12362
sahilmgandhi 18:6a4db94011d3 12363 #define SAI_xFRCR_FSDEF_Pos (16U)
sahilmgandhi 18:6a4db94011d3 12364 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 12365 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
sahilmgandhi 18:6a4db94011d3 12366 #define SAI_xFRCR_FSPOL_Pos (17U)
sahilmgandhi 18:6a4db94011d3 12367 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 12368 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
sahilmgandhi 18:6a4db94011d3 12369 #define SAI_xFRCR_FSOFF_Pos (18U)
sahilmgandhi 18:6a4db94011d3 12370 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 12371 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
sahilmgandhi 18:6a4db94011d3 12372 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 12373 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
sahilmgandhi 18:6a4db94011d3 12374
sahilmgandhi 18:6a4db94011d3 12375 /****************** Bit definition for SAI_xSLOTR register *******************/
sahilmgandhi 18:6a4db94011d3 12376 #define SAI_xSLOTR_FBOFF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12377 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 12378 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
sahilmgandhi 18:6a4db94011d3 12379 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12380 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12381 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12382 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12383 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12384
sahilmgandhi 18:6a4db94011d3 12385 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12386 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 12387 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
sahilmgandhi 18:6a4db94011d3 12388 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12389 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12390
sahilmgandhi 18:6a4db94011d3 12391 #define SAI_xSLOTR_NBSLOT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12392 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 12393 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
sahilmgandhi 18:6a4db94011d3 12394 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12395 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12396 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12397 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12398
sahilmgandhi 18:6a4db94011d3 12399 #define SAI_xSLOTR_SLOTEN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 12400 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 12401 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
sahilmgandhi 18:6a4db94011d3 12402
sahilmgandhi 18:6a4db94011d3 12403 /******************* Bit definition for SAI_xIMR register *******************/
sahilmgandhi 18:6a4db94011d3 12404 #define SAI_xIMR_OVRUDRIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12405 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12406 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
sahilmgandhi 18:6a4db94011d3 12407 #define SAI_xIMR_MUTEDETIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12408 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12409 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
sahilmgandhi 18:6a4db94011d3 12410 #define SAI_xIMR_WCKCFGIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12411 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12412 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
sahilmgandhi 18:6a4db94011d3 12413 #define SAI_xIMR_FREQIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12414 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12415 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
sahilmgandhi 18:6a4db94011d3 12416 #define SAI_xIMR_CNRDYIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12417 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12418 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
sahilmgandhi 18:6a4db94011d3 12419 #define SAI_xIMR_AFSDETIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12420 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12421 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
sahilmgandhi 18:6a4db94011d3 12422 #define SAI_xIMR_LFSDETIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12423 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12424 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
sahilmgandhi 18:6a4db94011d3 12425
sahilmgandhi 18:6a4db94011d3 12426 /******************** Bit definition for SAI_xSR register *******************/
sahilmgandhi 18:6a4db94011d3 12427 #define SAI_xSR_OVRUDR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12428 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12429 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
sahilmgandhi 18:6a4db94011d3 12430 #define SAI_xSR_MUTEDET_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12431 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12432 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
sahilmgandhi 18:6a4db94011d3 12433 #define SAI_xSR_WCKCFG_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12434 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12435 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
sahilmgandhi 18:6a4db94011d3 12436 #define SAI_xSR_FREQ_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12437 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12438 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
sahilmgandhi 18:6a4db94011d3 12439 #define SAI_xSR_CNRDY_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12440 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12441 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
sahilmgandhi 18:6a4db94011d3 12442 #define SAI_xSR_AFSDET_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12443 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12444 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
sahilmgandhi 18:6a4db94011d3 12445 #define SAI_xSR_LFSDET_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12446 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12447 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
sahilmgandhi 18:6a4db94011d3 12448
sahilmgandhi 18:6a4db94011d3 12449 #define SAI_xSR_FLVL_Pos (16U)
sahilmgandhi 18:6a4db94011d3 12450 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
sahilmgandhi 18:6a4db94011d3 12451 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
sahilmgandhi 18:6a4db94011d3 12452 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 12453 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 12454 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 12455
sahilmgandhi 18:6a4db94011d3 12456 /****************** Bit definition for SAI_xCLRFR register ******************/
sahilmgandhi 18:6a4db94011d3 12457 #define SAI_xCLRFR_COVRUDR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12458 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12459 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
sahilmgandhi 18:6a4db94011d3 12460 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12461 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12462 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
sahilmgandhi 18:6a4db94011d3 12463 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12464 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12465 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
sahilmgandhi 18:6a4db94011d3 12466 #define SAI_xCLRFR_CFREQ_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12467 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12468 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
sahilmgandhi 18:6a4db94011d3 12469 #define SAI_xCLRFR_CCNRDY_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12470 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12471 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
sahilmgandhi 18:6a4db94011d3 12472 #define SAI_xCLRFR_CAFSDET_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12473 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12474 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
sahilmgandhi 18:6a4db94011d3 12475 #define SAI_xCLRFR_CLFSDET_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12476 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12477 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
sahilmgandhi 18:6a4db94011d3 12478
sahilmgandhi 18:6a4db94011d3 12479 /****************** Bit definition for SAI_xDR register ******************/
sahilmgandhi 18:6a4db94011d3 12480 #define SAI_xDR_DATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12481 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12482 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
sahilmgandhi 18:6a4db94011d3 12483
sahilmgandhi 18:6a4db94011d3 12484
sahilmgandhi 18:6a4db94011d3 12485 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 12486 /* */
sahilmgandhi 18:6a4db94011d3 12487 /* SD host Interface */
sahilmgandhi 18:6a4db94011d3 12488 /* */
sahilmgandhi 18:6a4db94011d3 12489 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 12490 /****************** Bit definition for SDIO_POWER register ******************/
sahilmgandhi 18:6a4db94011d3 12491 #define SDIO_POWER_PWRCTRL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12492 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 12493 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
sahilmgandhi 18:6a4db94011d3 12494 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
sahilmgandhi 18:6a4db94011d3 12495 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
sahilmgandhi 18:6a4db94011d3 12496
sahilmgandhi 18:6a4db94011d3 12497 /****************** Bit definition for SDIO_CLKCR register ******************/
sahilmgandhi 18:6a4db94011d3 12498 #define SDIO_CLKCR_CLKDIV_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12499 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 12500 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
sahilmgandhi 18:6a4db94011d3 12501 #define SDIO_CLKCR_CLKEN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12502 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12503 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
sahilmgandhi 18:6a4db94011d3 12504 #define SDIO_CLKCR_PWRSAV_Pos (9U)
sahilmgandhi 18:6a4db94011d3 12505 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12506 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
sahilmgandhi 18:6a4db94011d3 12507 #define SDIO_CLKCR_BYPASS_Pos (10U)
sahilmgandhi 18:6a4db94011d3 12508 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12509 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
sahilmgandhi 18:6a4db94011d3 12510
sahilmgandhi 18:6a4db94011d3 12511 #define SDIO_CLKCR_WIDBUS_Pos (11U)
sahilmgandhi 18:6a4db94011d3 12512 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 12513 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
sahilmgandhi 18:6a4db94011d3 12514 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
sahilmgandhi 18:6a4db94011d3 12515 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
sahilmgandhi 18:6a4db94011d3 12516
sahilmgandhi 18:6a4db94011d3 12517 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12518 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12519 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
sahilmgandhi 18:6a4db94011d3 12520 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 12521 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12522 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
sahilmgandhi 18:6a4db94011d3 12523
sahilmgandhi 18:6a4db94011d3 12524 /******************* Bit definition for SDIO_ARG register *******************/
sahilmgandhi 18:6a4db94011d3 12525 #define SDIO_ARG_CMDARG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12526 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12527 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
sahilmgandhi 18:6a4db94011d3 12528
sahilmgandhi 18:6a4db94011d3 12529 /******************* Bit definition for SDIO_CMD register *******************/
sahilmgandhi 18:6a4db94011d3 12530 #define SDIO_CMD_CMDINDEX_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12531 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
sahilmgandhi 18:6a4db94011d3 12532 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
sahilmgandhi 18:6a4db94011d3 12533
sahilmgandhi 18:6a4db94011d3 12534 #define SDIO_CMD_WAITRESP_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12535 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 12536 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
sahilmgandhi 18:6a4db94011d3 12537 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 12538 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
sahilmgandhi 18:6a4db94011d3 12539
sahilmgandhi 18:6a4db94011d3 12540 #define SDIO_CMD_WAITINT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12541 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12542 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
sahilmgandhi 18:6a4db94011d3 12543 #define SDIO_CMD_WAITPEND_Pos (9U)
sahilmgandhi 18:6a4db94011d3 12544 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12545 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
sahilmgandhi 18:6a4db94011d3 12546 #define SDIO_CMD_CPSMEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 12547 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12548 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
sahilmgandhi 18:6a4db94011d3 12549 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
sahilmgandhi 18:6a4db94011d3 12550 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12551 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
sahilmgandhi 18:6a4db94011d3 12552 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
sahilmgandhi 18:6a4db94011d3 12553 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12554 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
sahilmgandhi 18:6a4db94011d3 12555 #define SDIO_CMD_NIEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12556 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12557 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12558 #define SDIO_CMD_CEATACMD_Pos (14U)
sahilmgandhi 18:6a4db94011d3 12559 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12560 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
sahilmgandhi 18:6a4db94011d3 12561
sahilmgandhi 18:6a4db94011d3 12562 /***************** Bit definition for SDIO_RESPCMD register *****************/
sahilmgandhi 18:6a4db94011d3 12563 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12564 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
sahilmgandhi 18:6a4db94011d3 12565 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
sahilmgandhi 18:6a4db94011d3 12566
sahilmgandhi 18:6a4db94011d3 12567 /****************** Bit definition for SDIO_RESP0 register ******************/
sahilmgandhi 18:6a4db94011d3 12568 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12569 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12570 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 12571
sahilmgandhi 18:6a4db94011d3 12572 /****************** Bit definition for SDIO_RESP1 register ******************/
sahilmgandhi 18:6a4db94011d3 12573 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12574 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12575 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 12576
sahilmgandhi 18:6a4db94011d3 12577 /****************** Bit definition for SDIO_RESP2 register ******************/
sahilmgandhi 18:6a4db94011d3 12578 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12579 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12580 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 12581
sahilmgandhi 18:6a4db94011d3 12582 /****************** Bit definition for SDIO_RESP3 register ******************/
sahilmgandhi 18:6a4db94011d3 12583 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12584 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12585 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 12586
sahilmgandhi 18:6a4db94011d3 12587 /****************** Bit definition for SDIO_RESP4 register ******************/
sahilmgandhi 18:6a4db94011d3 12588 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12589 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12590 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
sahilmgandhi 18:6a4db94011d3 12591
sahilmgandhi 18:6a4db94011d3 12592 /****************** Bit definition for SDIO_DTIMER register *****************/
sahilmgandhi 18:6a4db94011d3 12593 #define SDIO_DTIMER_DATATIME_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12594 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12595 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
sahilmgandhi 18:6a4db94011d3 12596
sahilmgandhi 18:6a4db94011d3 12597 /****************** Bit definition for SDIO_DLEN register *******************/
sahilmgandhi 18:6a4db94011d3 12598 #define SDIO_DLEN_DATALENGTH_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12599 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
sahilmgandhi 18:6a4db94011d3 12600 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
sahilmgandhi 18:6a4db94011d3 12601
sahilmgandhi 18:6a4db94011d3 12602 /****************** Bit definition for SDIO_DCTRL register ******************/
sahilmgandhi 18:6a4db94011d3 12603 #define SDIO_DCTRL_DTEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12604 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12605 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
sahilmgandhi 18:6a4db94011d3 12606 #define SDIO_DCTRL_DTDIR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12607 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12608 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
sahilmgandhi 18:6a4db94011d3 12609 #define SDIO_DCTRL_DTMODE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12610 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12611 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
sahilmgandhi 18:6a4db94011d3 12612 #define SDIO_DCTRL_DMAEN_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12613 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12614 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
sahilmgandhi 18:6a4db94011d3 12615
sahilmgandhi 18:6a4db94011d3 12616 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12617 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 12618 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
sahilmgandhi 18:6a4db94011d3 12619 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 12620 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 12621 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 12622 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
sahilmgandhi 18:6a4db94011d3 12623
sahilmgandhi 18:6a4db94011d3 12624 #define SDIO_DCTRL_RWSTART_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12625 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12626 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
sahilmgandhi 18:6a4db94011d3 12627 #define SDIO_DCTRL_RWSTOP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 12628 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12629 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
sahilmgandhi 18:6a4db94011d3 12630 #define SDIO_DCTRL_RWMOD_Pos (10U)
sahilmgandhi 18:6a4db94011d3 12631 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12632 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
sahilmgandhi 18:6a4db94011d3 12633 #define SDIO_DCTRL_SDIOEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 12634 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12635 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
sahilmgandhi 18:6a4db94011d3 12636
sahilmgandhi 18:6a4db94011d3 12637 /****************** Bit definition for SDIO_DCOUNT register *****************/
sahilmgandhi 18:6a4db94011d3 12638 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12639 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
sahilmgandhi 18:6a4db94011d3 12640 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
sahilmgandhi 18:6a4db94011d3 12641
sahilmgandhi 18:6a4db94011d3 12642 /****************** Bit definition for SDIO_STA register ********************/
sahilmgandhi 18:6a4db94011d3 12643 #define SDIO_STA_CCRCFAIL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12644 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12645 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
sahilmgandhi 18:6a4db94011d3 12646 #define SDIO_STA_DCRCFAIL_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12647 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12648 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
sahilmgandhi 18:6a4db94011d3 12649 #define SDIO_STA_CTIMEOUT_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12650 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12651 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
sahilmgandhi 18:6a4db94011d3 12652 #define SDIO_STA_DTIMEOUT_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12653 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12654 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
sahilmgandhi 18:6a4db94011d3 12655 #define SDIO_STA_TXUNDERR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12656 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12657 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
sahilmgandhi 18:6a4db94011d3 12658 #define SDIO_STA_RXOVERR_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12659 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12660 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
sahilmgandhi 18:6a4db94011d3 12661 #define SDIO_STA_CMDREND_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12662 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12663 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
sahilmgandhi 18:6a4db94011d3 12664 #define SDIO_STA_CMDSENT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12665 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12666 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
sahilmgandhi 18:6a4db94011d3 12667 #define SDIO_STA_DATAEND_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12668 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12669 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
sahilmgandhi 18:6a4db94011d3 12670 #define SDIO_STA_STBITERR_Pos (9U)
sahilmgandhi 18:6a4db94011d3 12671 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12672 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
sahilmgandhi 18:6a4db94011d3 12673 #define SDIO_STA_DBCKEND_Pos (10U)
sahilmgandhi 18:6a4db94011d3 12674 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12675 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
sahilmgandhi 18:6a4db94011d3 12676 #define SDIO_STA_CMDACT_Pos (11U)
sahilmgandhi 18:6a4db94011d3 12677 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12678 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
sahilmgandhi 18:6a4db94011d3 12679 #define SDIO_STA_TXACT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 12680 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12681 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
sahilmgandhi 18:6a4db94011d3 12682 #define SDIO_STA_RXACT_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12683 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12684 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
sahilmgandhi 18:6a4db94011d3 12685 #define SDIO_STA_TXFIFOHE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 12686 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12687 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
sahilmgandhi 18:6a4db94011d3 12688 #define SDIO_STA_RXFIFOHF_Pos (15U)
sahilmgandhi 18:6a4db94011d3 12689 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 12690 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
sahilmgandhi 18:6a4db94011d3 12691 #define SDIO_STA_TXFIFOF_Pos (16U)
sahilmgandhi 18:6a4db94011d3 12692 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 12693 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
sahilmgandhi 18:6a4db94011d3 12694 #define SDIO_STA_RXFIFOF_Pos (17U)
sahilmgandhi 18:6a4db94011d3 12695 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 12696 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
sahilmgandhi 18:6a4db94011d3 12697 #define SDIO_STA_TXFIFOE_Pos (18U)
sahilmgandhi 18:6a4db94011d3 12698 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 12699 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
sahilmgandhi 18:6a4db94011d3 12700 #define SDIO_STA_RXFIFOE_Pos (19U)
sahilmgandhi 18:6a4db94011d3 12701 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 12702 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
sahilmgandhi 18:6a4db94011d3 12703 #define SDIO_STA_TXDAVL_Pos (20U)
sahilmgandhi 18:6a4db94011d3 12704 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 12705 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
sahilmgandhi 18:6a4db94011d3 12706 #define SDIO_STA_RXDAVL_Pos (21U)
sahilmgandhi 18:6a4db94011d3 12707 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 12708 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
sahilmgandhi 18:6a4db94011d3 12709 #define SDIO_STA_SDIOIT_Pos (22U)
sahilmgandhi 18:6a4db94011d3 12710 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 12711 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
sahilmgandhi 18:6a4db94011d3 12712 #define SDIO_STA_CEATAEND_Pos (23U)
sahilmgandhi 18:6a4db94011d3 12713 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 12714 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
sahilmgandhi 18:6a4db94011d3 12715
sahilmgandhi 18:6a4db94011d3 12716 /******************* Bit definition for SDIO_ICR register *******************/
sahilmgandhi 18:6a4db94011d3 12717 #define SDIO_ICR_CCRCFAILC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12718 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12719 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
sahilmgandhi 18:6a4db94011d3 12720 #define SDIO_ICR_DCRCFAILC_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12721 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12722 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
sahilmgandhi 18:6a4db94011d3 12723 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12724 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12725 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
sahilmgandhi 18:6a4db94011d3 12726 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12727 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12728 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
sahilmgandhi 18:6a4db94011d3 12729 #define SDIO_ICR_TXUNDERRC_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12730 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12731 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 12732 #define SDIO_ICR_RXOVERRC_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12733 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12734 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 12735 #define SDIO_ICR_CMDRENDC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12736 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12737 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
sahilmgandhi 18:6a4db94011d3 12738 #define SDIO_ICR_CMDSENTC_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12739 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12740 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
sahilmgandhi 18:6a4db94011d3 12741 #define SDIO_ICR_DATAENDC_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12742 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12743 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 12744 #define SDIO_ICR_STBITERRC_Pos (9U)
sahilmgandhi 18:6a4db94011d3 12745 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12746 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
sahilmgandhi 18:6a4db94011d3 12747 #define SDIO_ICR_DBCKENDC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 12748 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12749 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 12750 #define SDIO_ICR_SDIOITC_Pos (22U)
sahilmgandhi 18:6a4db94011d3 12751 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 12752 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
sahilmgandhi 18:6a4db94011d3 12753 #define SDIO_ICR_CEATAENDC_Pos (23U)
sahilmgandhi 18:6a4db94011d3 12754 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 12755 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
sahilmgandhi 18:6a4db94011d3 12756
sahilmgandhi 18:6a4db94011d3 12757 /****************** Bit definition for SDIO_MASK register *******************/
sahilmgandhi 18:6a4db94011d3 12758 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12759 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12760 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12761 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12762 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12763 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12764 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12765 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12766 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12767 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12768 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12769 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12770 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12771 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12772 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12773 #define SDIO_MASK_RXOVERRIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12774 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12775 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12776 #define SDIO_MASK_CMDRENDIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12777 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12778 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12779 #define SDIO_MASK_CMDSENTIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12780 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12781 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12782 #define SDIO_MASK_DATAENDIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12783 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12784 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12785 #define SDIO_MASK_STBITERRIE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 12786 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12787 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12788 #define SDIO_MASK_DBCKENDIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 12789 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12790 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12791 #define SDIO_MASK_CMDACTIE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 12792 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12793 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12794 #define SDIO_MASK_TXACTIE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 12795 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12796 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12797 #define SDIO_MASK_RXACTIE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12798 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12799 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
sahilmgandhi 18:6a4db94011d3 12800 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 12801 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12802 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12803 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 12804 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 12805 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12806 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 12807 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 12808 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12809 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
sahilmgandhi 18:6a4db94011d3 12810 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 12811 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12812 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
sahilmgandhi 18:6a4db94011d3 12813 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 12814 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12815 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
sahilmgandhi 18:6a4db94011d3 12816 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 12817 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12818 #define SDIO_MASK_TXDAVLIE_Pos (20U)
sahilmgandhi 18:6a4db94011d3 12819 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 12820 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12821 #define SDIO_MASK_RXDAVLIE_Pos (21U)
sahilmgandhi 18:6a4db94011d3 12822 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 12823 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12824 #define SDIO_MASK_SDIOITIE_Pos (22U)
sahilmgandhi 18:6a4db94011d3 12825 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 12826 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12827 #define SDIO_MASK_CEATAENDIE_Pos (23U)
sahilmgandhi 18:6a4db94011d3 12828 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 12829 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12830
sahilmgandhi 18:6a4db94011d3 12831 /***************** Bit definition for SDIO_FIFOCNT register *****************/
sahilmgandhi 18:6a4db94011d3 12832 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12833 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
sahilmgandhi 18:6a4db94011d3 12834 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
sahilmgandhi 18:6a4db94011d3 12835
sahilmgandhi 18:6a4db94011d3 12836 /****************** Bit definition for SDIO_FIFO register *******************/
sahilmgandhi 18:6a4db94011d3 12837 #define SDIO_FIFO_FIFODATA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12838 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 12839 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
sahilmgandhi 18:6a4db94011d3 12840
sahilmgandhi 18:6a4db94011d3 12841 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 12842 /* */
sahilmgandhi 18:6a4db94011d3 12843 /* Serial Peripheral Interface */
sahilmgandhi 18:6a4db94011d3 12844 /* */
sahilmgandhi 18:6a4db94011d3 12845 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 12846 /*
sahilmgandhi 18:6a4db94011d3 12847 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
sahilmgandhi 18:6a4db94011d3 12848 */
sahilmgandhi 18:6a4db94011d3 12849 #define SPI_I2S_SUPPORT /*!< I2S support */
sahilmgandhi 18:6a4db94011d3 12850 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
sahilmgandhi 18:6a4db94011d3 12851 /******************* Bit definition for SPI_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 12852 #define SPI_CR1_CPHA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12853 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12854 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
sahilmgandhi 18:6a4db94011d3 12855 #define SPI_CR1_CPOL_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12856 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12857 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
sahilmgandhi 18:6a4db94011d3 12858 #define SPI_CR1_MSTR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12859 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12860 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
sahilmgandhi 18:6a4db94011d3 12861
sahilmgandhi 18:6a4db94011d3 12862 #define SPI_CR1_BR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12863 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
sahilmgandhi 18:6a4db94011d3 12864 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
sahilmgandhi 18:6a4db94011d3 12865 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12866 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12867 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12868
sahilmgandhi 18:6a4db94011d3 12869 #define SPI_CR1_SPE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12870 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12871 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
sahilmgandhi 18:6a4db94011d3 12872 #define SPI_CR1_LSBFIRST_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12873 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12874 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
sahilmgandhi 18:6a4db94011d3 12875 #define SPI_CR1_SSI_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12876 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12877 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
sahilmgandhi 18:6a4db94011d3 12878 #define SPI_CR1_SSM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 12879 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 12880 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
sahilmgandhi 18:6a4db94011d3 12881 #define SPI_CR1_RXONLY_Pos (10U)
sahilmgandhi 18:6a4db94011d3 12882 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 12883 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
sahilmgandhi 18:6a4db94011d3 12884 #define SPI_CR1_DFF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 12885 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 12886 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
sahilmgandhi 18:6a4db94011d3 12887 #define SPI_CR1_CRCNEXT_Pos (12U)
sahilmgandhi 18:6a4db94011d3 12888 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 12889 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
sahilmgandhi 18:6a4db94011d3 12890 #define SPI_CR1_CRCEN_Pos (13U)
sahilmgandhi 18:6a4db94011d3 12891 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 12892 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
sahilmgandhi 18:6a4db94011d3 12893 #define SPI_CR1_BIDIOE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 12894 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 12895 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
sahilmgandhi 18:6a4db94011d3 12896 #define SPI_CR1_BIDIMODE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 12897 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 12898 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
sahilmgandhi 18:6a4db94011d3 12899
sahilmgandhi 18:6a4db94011d3 12900 /******************* Bit definition for SPI_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 12901 #define SPI_CR2_RXDMAEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12902 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12903 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 12904 #define SPI_CR2_TXDMAEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12905 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12906 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
sahilmgandhi 18:6a4db94011d3 12907 #define SPI_CR2_SSOE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12908 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12909 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
sahilmgandhi 18:6a4db94011d3 12910 #define SPI_CR2_FRF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12911 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12912 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
sahilmgandhi 18:6a4db94011d3 12913 #define SPI_CR2_ERRIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12914 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12915 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12916 #define SPI_CR2_RXNEIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12917 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12918 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12919 #define SPI_CR2_TXEIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12920 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12921 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 12922
sahilmgandhi 18:6a4db94011d3 12923 /******************** Bit definition for SPI_SR register ********************/
sahilmgandhi 18:6a4db94011d3 12924 #define SPI_SR_RXNE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12925 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12926 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
sahilmgandhi 18:6a4db94011d3 12927 #define SPI_SR_TXE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12928 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12929 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
sahilmgandhi 18:6a4db94011d3 12930 #define SPI_SR_CHSIDE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 12931 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12932 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
sahilmgandhi 18:6a4db94011d3 12933 #define SPI_SR_UDR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12934 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12935 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
sahilmgandhi 18:6a4db94011d3 12936 #define SPI_SR_CRCERR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12937 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12938 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
sahilmgandhi 18:6a4db94011d3 12939 #define SPI_SR_MODF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 12940 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12941 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
sahilmgandhi 18:6a4db94011d3 12942 #define SPI_SR_OVR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 12943 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 12944 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
sahilmgandhi 18:6a4db94011d3 12945 #define SPI_SR_BSY_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12946 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12947 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
sahilmgandhi 18:6a4db94011d3 12948 #define SPI_SR_FRE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12949 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 12950 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
sahilmgandhi 18:6a4db94011d3 12951
sahilmgandhi 18:6a4db94011d3 12952 /******************** Bit definition for SPI_DR register ********************/
sahilmgandhi 18:6a4db94011d3 12953 #define SPI_DR_DR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12954 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 12955 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
sahilmgandhi 18:6a4db94011d3 12956
sahilmgandhi 18:6a4db94011d3 12957 /******************* Bit definition for SPI_CRCPR register ******************/
sahilmgandhi 18:6a4db94011d3 12958 #define SPI_CRCPR_CRCPOLY_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12959 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 12960 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
sahilmgandhi 18:6a4db94011d3 12961
sahilmgandhi 18:6a4db94011d3 12962 /****************** Bit definition for SPI_RXCRCR register ******************/
sahilmgandhi 18:6a4db94011d3 12963 #define SPI_RXCRCR_RXCRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12964 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 12965 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
sahilmgandhi 18:6a4db94011d3 12966
sahilmgandhi 18:6a4db94011d3 12967 /****************** Bit definition for SPI_TXCRCR register ******************/
sahilmgandhi 18:6a4db94011d3 12968 #define SPI_TXCRCR_TXCRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12969 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 12970 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
sahilmgandhi 18:6a4db94011d3 12971
sahilmgandhi 18:6a4db94011d3 12972 /****************** Bit definition for SPI_I2SCFGR register *****************/
sahilmgandhi 18:6a4db94011d3 12973 #define SPI_I2SCFGR_CHLEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 12974 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 12975 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
sahilmgandhi 18:6a4db94011d3 12976
sahilmgandhi 18:6a4db94011d3 12977 #define SPI_I2SCFGR_DATLEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 12978 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
sahilmgandhi 18:6a4db94011d3 12979 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
sahilmgandhi 18:6a4db94011d3 12980 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 12981 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 12982
sahilmgandhi 18:6a4db94011d3 12983 #define SPI_I2SCFGR_CKPOL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 12984 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 12985 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
sahilmgandhi 18:6a4db94011d3 12986
sahilmgandhi 18:6a4db94011d3 12987 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 12988 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 12989 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
sahilmgandhi 18:6a4db94011d3 12990 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 12991 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 12992
sahilmgandhi 18:6a4db94011d3 12993 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
sahilmgandhi 18:6a4db94011d3 12994 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 12995 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
sahilmgandhi 18:6a4db94011d3 12996
sahilmgandhi 18:6a4db94011d3 12997 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
sahilmgandhi 18:6a4db94011d3 12998 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 12999 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
sahilmgandhi 18:6a4db94011d3 13000 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13001 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 13002
sahilmgandhi 18:6a4db94011d3 13003 #define SPI_I2SCFGR_I2SE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13004 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13005 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
sahilmgandhi 18:6a4db94011d3 13006 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13007 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13008 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
sahilmgandhi 18:6a4db94011d3 13009
sahilmgandhi 18:6a4db94011d3 13010 /****************** Bit definition for SPI_I2SPR register *******************/
sahilmgandhi 18:6a4db94011d3 13011 #define SPI_I2SPR_I2SDIV_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13012 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 13013 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
sahilmgandhi 18:6a4db94011d3 13014 #define SPI_I2SPR_ODD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13015 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13016 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
sahilmgandhi 18:6a4db94011d3 13017 #define SPI_I2SPR_MCKOE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 13018 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 13019 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
sahilmgandhi 18:6a4db94011d3 13020
sahilmgandhi 18:6a4db94011d3 13021 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 13022 /* */
sahilmgandhi 18:6a4db94011d3 13023 /* SYSCFG */
sahilmgandhi 18:6a4db94011d3 13024 /* */
sahilmgandhi 18:6a4db94011d3 13025 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 13026 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
sahilmgandhi 18:6a4db94011d3 13027 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13028 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 13029 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
sahilmgandhi 18:6a4db94011d3 13030 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13031 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 13032 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13033 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13034 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13035 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
sahilmgandhi 18:6a4db94011d3 13036 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13037 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 13038 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
sahilmgandhi 18:6a4db94011d3 13039 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13040 /* Legacy Defines */
sahilmgandhi 18:6a4db94011d3 13041 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
sahilmgandhi 18:6a4db94011d3 13042 /****************** Bit definition for SYSCFG_PMC register ******************/
sahilmgandhi 18:6a4db94011d3 13043 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 13044 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
sahilmgandhi 18:6a4db94011d3 13045 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
sahilmgandhi 18:6a4db94011d3 13046 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
sahilmgandhi 18:6a4db94011d3 13047 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 13048 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
sahilmgandhi 18:6a4db94011d3 13049 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
sahilmgandhi 18:6a4db94011d3 13050 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 13051 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
sahilmgandhi 18:6a4db94011d3 13052 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
sahilmgandhi 18:6a4db94011d3 13053 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 13054 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
sahilmgandhi 18:6a4db94011d3 13055 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
sahilmgandhi 18:6a4db94011d3 13056 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 13057 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
sahilmgandhi 18:6a4db94011d3 13058 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 13059 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
sahilmgandhi 18:6a4db94011d3 13060
sahilmgandhi 18:6a4db94011d3 13061 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
sahilmgandhi 18:6a4db94011d3 13062 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13063 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 13064 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
sahilmgandhi 18:6a4db94011d3 13065 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13066 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 13067 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
sahilmgandhi 18:6a4db94011d3 13068 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13069 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 13070 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
sahilmgandhi 18:6a4db94011d3 13071 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13072 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 13073 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
sahilmgandhi 18:6a4db94011d3 13074 /**
sahilmgandhi 18:6a4db94011d3 13075 * @brief EXTI0 configuration
sahilmgandhi 18:6a4db94011d3 13076 */
sahilmgandhi 18:6a4db94011d3 13077 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
sahilmgandhi 18:6a4db94011d3 13078 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
sahilmgandhi 18:6a4db94011d3 13079 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
sahilmgandhi 18:6a4db94011d3 13080 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
sahilmgandhi 18:6a4db94011d3 13081 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
sahilmgandhi 18:6a4db94011d3 13082 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
sahilmgandhi 18:6a4db94011d3 13083 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
sahilmgandhi 18:6a4db94011d3 13084 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
sahilmgandhi 18:6a4db94011d3 13085 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
sahilmgandhi 18:6a4db94011d3 13086 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
sahilmgandhi 18:6a4db94011d3 13087 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
sahilmgandhi 18:6a4db94011d3 13088
sahilmgandhi 18:6a4db94011d3 13089 /**
sahilmgandhi 18:6a4db94011d3 13090 * @brief EXTI1 configuration
sahilmgandhi 18:6a4db94011d3 13091 */
sahilmgandhi 18:6a4db94011d3 13092 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
sahilmgandhi 18:6a4db94011d3 13093 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
sahilmgandhi 18:6a4db94011d3 13094 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
sahilmgandhi 18:6a4db94011d3 13095 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
sahilmgandhi 18:6a4db94011d3 13096 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
sahilmgandhi 18:6a4db94011d3 13097 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
sahilmgandhi 18:6a4db94011d3 13098 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
sahilmgandhi 18:6a4db94011d3 13099 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
sahilmgandhi 18:6a4db94011d3 13100 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
sahilmgandhi 18:6a4db94011d3 13101 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
sahilmgandhi 18:6a4db94011d3 13102 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
sahilmgandhi 18:6a4db94011d3 13103
sahilmgandhi 18:6a4db94011d3 13104 /**
sahilmgandhi 18:6a4db94011d3 13105 * @brief EXTI2 configuration
sahilmgandhi 18:6a4db94011d3 13106 */
sahilmgandhi 18:6a4db94011d3 13107 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
sahilmgandhi 18:6a4db94011d3 13108 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
sahilmgandhi 18:6a4db94011d3 13109 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
sahilmgandhi 18:6a4db94011d3 13110 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
sahilmgandhi 18:6a4db94011d3 13111 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
sahilmgandhi 18:6a4db94011d3 13112 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
sahilmgandhi 18:6a4db94011d3 13113 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
sahilmgandhi 18:6a4db94011d3 13114 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
sahilmgandhi 18:6a4db94011d3 13115 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
sahilmgandhi 18:6a4db94011d3 13116 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
sahilmgandhi 18:6a4db94011d3 13117 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
sahilmgandhi 18:6a4db94011d3 13118
sahilmgandhi 18:6a4db94011d3 13119 /**
sahilmgandhi 18:6a4db94011d3 13120 * @brief EXTI3 configuration
sahilmgandhi 18:6a4db94011d3 13121 */
sahilmgandhi 18:6a4db94011d3 13122 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
sahilmgandhi 18:6a4db94011d3 13123 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
sahilmgandhi 18:6a4db94011d3 13124 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
sahilmgandhi 18:6a4db94011d3 13125 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
sahilmgandhi 18:6a4db94011d3 13126 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
sahilmgandhi 18:6a4db94011d3 13127 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
sahilmgandhi 18:6a4db94011d3 13128 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
sahilmgandhi 18:6a4db94011d3 13129 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
sahilmgandhi 18:6a4db94011d3 13130 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
sahilmgandhi 18:6a4db94011d3 13131 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
sahilmgandhi 18:6a4db94011d3 13132 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
sahilmgandhi 18:6a4db94011d3 13133
sahilmgandhi 18:6a4db94011d3 13134 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
sahilmgandhi 18:6a4db94011d3 13135 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13136 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 13137 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
sahilmgandhi 18:6a4db94011d3 13138 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13139 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 13140 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
sahilmgandhi 18:6a4db94011d3 13141 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13142 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 13143 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
sahilmgandhi 18:6a4db94011d3 13144 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13145 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 13146 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
sahilmgandhi 18:6a4db94011d3 13147
sahilmgandhi 18:6a4db94011d3 13148 /**
sahilmgandhi 18:6a4db94011d3 13149 * @brief EXTI4 configuration
sahilmgandhi 18:6a4db94011d3 13150 */
sahilmgandhi 18:6a4db94011d3 13151 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
sahilmgandhi 18:6a4db94011d3 13152 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
sahilmgandhi 18:6a4db94011d3 13153 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
sahilmgandhi 18:6a4db94011d3 13154 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
sahilmgandhi 18:6a4db94011d3 13155 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
sahilmgandhi 18:6a4db94011d3 13156 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
sahilmgandhi 18:6a4db94011d3 13157 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
sahilmgandhi 18:6a4db94011d3 13158 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
sahilmgandhi 18:6a4db94011d3 13159 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
sahilmgandhi 18:6a4db94011d3 13160 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
sahilmgandhi 18:6a4db94011d3 13161 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
sahilmgandhi 18:6a4db94011d3 13162
sahilmgandhi 18:6a4db94011d3 13163 /**
sahilmgandhi 18:6a4db94011d3 13164 * @brief EXTI5 configuration
sahilmgandhi 18:6a4db94011d3 13165 */
sahilmgandhi 18:6a4db94011d3 13166 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
sahilmgandhi 18:6a4db94011d3 13167 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
sahilmgandhi 18:6a4db94011d3 13168 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
sahilmgandhi 18:6a4db94011d3 13169 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
sahilmgandhi 18:6a4db94011d3 13170 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
sahilmgandhi 18:6a4db94011d3 13171 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
sahilmgandhi 18:6a4db94011d3 13172 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
sahilmgandhi 18:6a4db94011d3 13173 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
sahilmgandhi 18:6a4db94011d3 13174 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
sahilmgandhi 18:6a4db94011d3 13175 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
sahilmgandhi 18:6a4db94011d3 13176 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
sahilmgandhi 18:6a4db94011d3 13177
sahilmgandhi 18:6a4db94011d3 13178 /**
sahilmgandhi 18:6a4db94011d3 13179 * @brief EXTI6 configuration
sahilmgandhi 18:6a4db94011d3 13180 */
sahilmgandhi 18:6a4db94011d3 13181 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
sahilmgandhi 18:6a4db94011d3 13182 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
sahilmgandhi 18:6a4db94011d3 13183 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
sahilmgandhi 18:6a4db94011d3 13184 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
sahilmgandhi 18:6a4db94011d3 13185 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
sahilmgandhi 18:6a4db94011d3 13186 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
sahilmgandhi 18:6a4db94011d3 13187 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
sahilmgandhi 18:6a4db94011d3 13188 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
sahilmgandhi 18:6a4db94011d3 13189 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
sahilmgandhi 18:6a4db94011d3 13190 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
sahilmgandhi 18:6a4db94011d3 13191 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
sahilmgandhi 18:6a4db94011d3 13192
sahilmgandhi 18:6a4db94011d3 13193 /**
sahilmgandhi 18:6a4db94011d3 13194 * @brief EXTI7 configuration
sahilmgandhi 18:6a4db94011d3 13195 */
sahilmgandhi 18:6a4db94011d3 13196 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
sahilmgandhi 18:6a4db94011d3 13197 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
sahilmgandhi 18:6a4db94011d3 13198 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
sahilmgandhi 18:6a4db94011d3 13199 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
sahilmgandhi 18:6a4db94011d3 13200 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
sahilmgandhi 18:6a4db94011d3 13201 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
sahilmgandhi 18:6a4db94011d3 13202 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
sahilmgandhi 18:6a4db94011d3 13203 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
sahilmgandhi 18:6a4db94011d3 13204 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
sahilmgandhi 18:6a4db94011d3 13205 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
sahilmgandhi 18:6a4db94011d3 13206 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
sahilmgandhi 18:6a4db94011d3 13207
sahilmgandhi 18:6a4db94011d3 13208 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
sahilmgandhi 18:6a4db94011d3 13209 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13210 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 13211 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
sahilmgandhi 18:6a4db94011d3 13212 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13213 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 13214 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
sahilmgandhi 18:6a4db94011d3 13215 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13216 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 13217 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
sahilmgandhi 18:6a4db94011d3 13218 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13219 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 13220 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
sahilmgandhi 18:6a4db94011d3 13221
sahilmgandhi 18:6a4db94011d3 13222 /**
sahilmgandhi 18:6a4db94011d3 13223 * @brief EXTI8 configuration
sahilmgandhi 18:6a4db94011d3 13224 */
sahilmgandhi 18:6a4db94011d3 13225 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
sahilmgandhi 18:6a4db94011d3 13226 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
sahilmgandhi 18:6a4db94011d3 13227 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
sahilmgandhi 18:6a4db94011d3 13228 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
sahilmgandhi 18:6a4db94011d3 13229 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
sahilmgandhi 18:6a4db94011d3 13230 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
sahilmgandhi 18:6a4db94011d3 13231 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
sahilmgandhi 18:6a4db94011d3 13232 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
sahilmgandhi 18:6a4db94011d3 13233 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
sahilmgandhi 18:6a4db94011d3 13234 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
sahilmgandhi 18:6a4db94011d3 13235
sahilmgandhi 18:6a4db94011d3 13236 /**
sahilmgandhi 18:6a4db94011d3 13237 * @brief EXTI9 configuration
sahilmgandhi 18:6a4db94011d3 13238 */
sahilmgandhi 18:6a4db94011d3 13239 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
sahilmgandhi 18:6a4db94011d3 13240 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
sahilmgandhi 18:6a4db94011d3 13241 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
sahilmgandhi 18:6a4db94011d3 13242 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
sahilmgandhi 18:6a4db94011d3 13243 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
sahilmgandhi 18:6a4db94011d3 13244 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
sahilmgandhi 18:6a4db94011d3 13245 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
sahilmgandhi 18:6a4db94011d3 13246 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
sahilmgandhi 18:6a4db94011d3 13247 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
sahilmgandhi 18:6a4db94011d3 13248 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
sahilmgandhi 18:6a4db94011d3 13249
sahilmgandhi 18:6a4db94011d3 13250 /**
sahilmgandhi 18:6a4db94011d3 13251 * @brief EXTI10 configuration
sahilmgandhi 18:6a4db94011d3 13252 */
sahilmgandhi 18:6a4db94011d3 13253 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
sahilmgandhi 18:6a4db94011d3 13254 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
sahilmgandhi 18:6a4db94011d3 13255 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
sahilmgandhi 18:6a4db94011d3 13256 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
sahilmgandhi 18:6a4db94011d3 13257 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
sahilmgandhi 18:6a4db94011d3 13258 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
sahilmgandhi 18:6a4db94011d3 13259 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
sahilmgandhi 18:6a4db94011d3 13260 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
sahilmgandhi 18:6a4db94011d3 13261 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
sahilmgandhi 18:6a4db94011d3 13262 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
sahilmgandhi 18:6a4db94011d3 13263
sahilmgandhi 18:6a4db94011d3 13264 /**
sahilmgandhi 18:6a4db94011d3 13265 * @brief EXTI11 configuration
sahilmgandhi 18:6a4db94011d3 13266 */
sahilmgandhi 18:6a4db94011d3 13267 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
sahilmgandhi 18:6a4db94011d3 13268 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
sahilmgandhi 18:6a4db94011d3 13269 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
sahilmgandhi 18:6a4db94011d3 13270 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
sahilmgandhi 18:6a4db94011d3 13271 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
sahilmgandhi 18:6a4db94011d3 13272 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
sahilmgandhi 18:6a4db94011d3 13273 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
sahilmgandhi 18:6a4db94011d3 13274 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
sahilmgandhi 18:6a4db94011d3 13275 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
sahilmgandhi 18:6a4db94011d3 13276 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
sahilmgandhi 18:6a4db94011d3 13277
sahilmgandhi 18:6a4db94011d3 13278
sahilmgandhi 18:6a4db94011d3 13279 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
sahilmgandhi 18:6a4db94011d3 13280 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13281 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 13282 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
sahilmgandhi 18:6a4db94011d3 13283 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13284 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 13285 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
sahilmgandhi 18:6a4db94011d3 13286 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13287 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 13288 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
sahilmgandhi 18:6a4db94011d3 13289 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13290 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 13291 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
sahilmgandhi 18:6a4db94011d3 13292
sahilmgandhi 18:6a4db94011d3 13293 /**
sahilmgandhi 18:6a4db94011d3 13294 * @brief EXTI12 configuration
sahilmgandhi 18:6a4db94011d3 13295 */
sahilmgandhi 18:6a4db94011d3 13296 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
sahilmgandhi 18:6a4db94011d3 13297 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
sahilmgandhi 18:6a4db94011d3 13298 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
sahilmgandhi 18:6a4db94011d3 13299 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
sahilmgandhi 18:6a4db94011d3 13300 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
sahilmgandhi 18:6a4db94011d3 13301 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
sahilmgandhi 18:6a4db94011d3 13302 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
sahilmgandhi 18:6a4db94011d3 13303 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
sahilmgandhi 18:6a4db94011d3 13304 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
sahilmgandhi 18:6a4db94011d3 13305 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
sahilmgandhi 18:6a4db94011d3 13306
sahilmgandhi 18:6a4db94011d3 13307 /**
sahilmgandhi 18:6a4db94011d3 13308 * @brief EXTI13 configuration
sahilmgandhi 18:6a4db94011d3 13309 */
sahilmgandhi 18:6a4db94011d3 13310 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
sahilmgandhi 18:6a4db94011d3 13311 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
sahilmgandhi 18:6a4db94011d3 13312 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
sahilmgandhi 18:6a4db94011d3 13313 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
sahilmgandhi 18:6a4db94011d3 13314 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
sahilmgandhi 18:6a4db94011d3 13315 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
sahilmgandhi 18:6a4db94011d3 13316 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
sahilmgandhi 18:6a4db94011d3 13317 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
sahilmgandhi 18:6a4db94011d3 13318 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
sahilmgandhi 18:6a4db94011d3 13319 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
sahilmgandhi 18:6a4db94011d3 13320
sahilmgandhi 18:6a4db94011d3 13321 /**
sahilmgandhi 18:6a4db94011d3 13322 * @brief EXTI14 configuration
sahilmgandhi 18:6a4db94011d3 13323 */
sahilmgandhi 18:6a4db94011d3 13324 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
sahilmgandhi 18:6a4db94011d3 13325 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
sahilmgandhi 18:6a4db94011d3 13326 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
sahilmgandhi 18:6a4db94011d3 13327 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
sahilmgandhi 18:6a4db94011d3 13328 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
sahilmgandhi 18:6a4db94011d3 13329 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
sahilmgandhi 18:6a4db94011d3 13330 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
sahilmgandhi 18:6a4db94011d3 13331 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
sahilmgandhi 18:6a4db94011d3 13332 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
sahilmgandhi 18:6a4db94011d3 13333 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
sahilmgandhi 18:6a4db94011d3 13334
sahilmgandhi 18:6a4db94011d3 13335 /**
sahilmgandhi 18:6a4db94011d3 13336 * @brief EXTI15 configuration
sahilmgandhi 18:6a4db94011d3 13337 */
sahilmgandhi 18:6a4db94011d3 13338 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
sahilmgandhi 18:6a4db94011d3 13339 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
sahilmgandhi 18:6a4db94011d3 13340 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
sahilmgandhi 18:6a4db94011d3 13341 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
sahilmgandhi 18:6a4db94011d3 13342 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
sahilmgandhi 18:6a4db94011d3 13343 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
sahilmgandhi 18:6a4db94011d3 13344 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
sahilmgandhi 18:6a4db94011d3 13345 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
sahilmgandhi 18:6a4db94011d3 13346 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
sahilmgandhi 18:6a4db94011d3 13347 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
sahilmgandhi 18:6a4db94011d3 13348
sahilmgandhi 18:6a4db94011d3 13349 /****************** Bit definition for SYSCFG_CMPCR register ****************/
sahilmgandhi 18:6a4db94011d3 13350 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13351 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13352 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
sahilmgandhi 18:6a4db94011d3 13353 #define SYSCFG_CMPCR_READY_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13354 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13355 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
sahilmgandhi 18:6a4db94011d3 13356
sahilmgandhi 18:6a4db94011d3 13357 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 13358 /* */
sahilmgandhi 18:6a4db94011d3 13359 /* TIM */
sahilmgandhi 18:6a4db94011d3 13360 /* */
sahilmgandhi 18:6a4db94011d3 13361 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 13362 /******************* Bit definition for TIM_CR1 register ********************/
sahilmgandhi 18:6a4db94011d3 13363 #define TIM_CR1_CEN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13364 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13365 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
sahilmgandhi 18:6a4db94011d3 13366 #define TIM_CR1_UDIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 13367 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 13368 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
sahilmgandhi 18:6a4db94011d3 13369 #define TIM_CR1_URS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13370 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13371 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
sahilmgandhi 18:6a4db94011d3 13372 #define TIM_CR1_OPM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13373 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13374 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
sahilmgandhi 18:6a4db94011d3 13375 #define TIM_CR1_DIR_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13376 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 13377 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
sahilmgandhi 18:6a4db94011d3 13378
sahilmgandhi 18:6a4db94011d3 13379 #define TIM_CR1_CMS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 13380 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 13381 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
sahilmgandhi 18:6a4db94011d3 13382 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 13383 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13384
sahilmgandhi 18:6a4db94011d3 13385 #define TIM_CR1_ARPE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13386 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13387 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
sahilmgandhi 18:6a4db94011d3 13388
sahilmgandhi 18:6a4db94011d3 13389 #define TIM_CR1_CKD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13390 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 13391 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
sahilmgandhi 18:6a4db94011d3 13392 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
sahilmgandhi 18:6a4db94011d3 13393 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
sahilmgandhi 18:6a4db94011d3 13394
sahilmgandhi 18:6a4db94011d3 13395 /******************* Bit definition for TIM_CR2 register ********************/
sahilmgandhi 18:6a4db94011d3 13396 #define TIM_CR2_CCPC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13397 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13398 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
sahilmgandhi 18:6a4db94011d3 13399 #define TIM_CR2_CCUS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13400 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13401 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
sahilmgandhi 18:6a4db94011d3 13402 #define TIM_CR2_CCDS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13403 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13404 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
sahilmgandhi 18:6a4db94011d3 13405
sahilmgandhi 18:6a4db94011d3 13406 #define TIM_CR2_MMS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13407 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 13408 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
sahilmgandhi 18:6a4db94011d3 13409 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 13410 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 13411 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13412
sahilmgandhi 18:6a4db94011d3 13413 #define TIM_CR2_TI1S_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13414 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13415 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
sahilmgandhi 18:6a4db94011d3 13416 #define TIM_CR2_OIS1_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13417 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13418 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
sahilmgandhi 18:6a4db94011d3 13419 #define TIM_CR2_OIS1N_Pos (9U)
sahilmgandhi 18:6a4db94011d3 13420 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 13421 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
sahilmgandhi 18:6a4db94011d3 13422 #define TIM_CR2_OIS2_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13423 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13424 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
sahilmgandhi 18:6a4db94011d3 13425 #define TIM_CR2_OIS2N_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13426 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13427 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
sahilmgandhi 18:6a4db94011d3 13428 #define TIM_CR2_OIS3_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13429 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 13430 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
sahilmgandhi 18:6a4db94011d3 13431 #define TIM_CR2_OIS3N_Pos (13U)
sahilmgandhi 18:6a4db94011d3 13432 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 13433 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
sahilmgandhi 18:6a4db94011d3 13434 #define TIM_CR2_OIS4_Pos (14U)
sahilmgandhi 18:6a4db94011d3 13435 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 13436 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
sahilmgandhi 18:6a4db94011d3 13437
sahilmgandhi 18:6a4db94011d3 13438 /******************* Bit definition for TIM_SMCR register *******************/
sahilmgandhi 18:6a4db94011d3 13439 #define TIM_SMCR_SMS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13440 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 13441 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
sahilmgandhi 18:6a4db94011d3 13442 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
sahilmgandhi 18:6a4db94011d3 13443 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
sahilmgandhi 18:6a4db94011d3 13444 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
sahilmgandhi 18:6a4db94011d3 13445
sahilmgandhi 18:6a4db94011d3 13446 #define TIM_SMCR_TS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13447 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 13448 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
sahilmgandhi 18:6a4db94011d3 13449 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 13450 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 13451 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13452
sahilmgandhi 18:6a4db94011d3 13453 #define TIM_SMCR_MSM_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13454 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13455 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
sahilmgandhi 18:6a4db94011d3 13456
sahilmgandhi 18:6a4db94011d3 13457 #define TIM_SMCR_ETF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13458 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
sahilmgandhi 18:6a4db94011d3 13459 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
sahilmgandhi 18:6a4db94011d3 13460 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
sahilmgandhi 18:6a4db94011d3 13461 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
sahilmgandhi 18:6a4db94011d3 13462 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
sahilmgandhi 18:6a4db94011d3 13463 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
sahilmgandhi 18:6a4db94011d3 13464
sahilmgandhi 18:6a4db94011d3 13465 #define TIM_SMCR_ETPS_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13466 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 13467 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
sahilmgandhi 18:6a4db94011d3 13468 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
sahilmgandhi 18:6a4db94011d3 13469 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
sahilmgandhi 18:6a4db94011d3 13470
sahilmgandhi 18:6a4db94011d3 13471 #define TIM_SMCR_ECE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 13472 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 13473 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
sahilmgandhi 18:6a4db94011d3 13474 #define TIM_SMCR_ETP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 13475 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 13476 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
sahilmgandhi 18:6a4db94011d3 13477
sahilmgandhi 18:6a4db94011d3 13478 /******************* Bit definition for TIM_DIER register *******************/
sahilmgandhi 18:6a4db94011d3 13479 #define TIM_DIER_UIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13480 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13481 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
sahilmgandhi 18:6a4db94011d3 13482 #define TIM_DIER_CC1IE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 13483 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 13484 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
sahilmgandhi 18:6a4db94011d3 13485 #define TIM_DIER_CC2IE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13486 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13487 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
sahilmgandhi 18:6a4db94011d3 13488 #define TIM_DIER_CC3IE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13489 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13490 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
sahilmgandhi 18:6a4db94011d3 13491 #define TIM_DIER_CC4IE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13492 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 13493 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
sahilmgandhi 18:6a4db94011d3 13494 #define TIM_DIER_COMIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 13495 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 13496 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
sahilmgandhi 18:6a4db94011d3 13497 #define TIM_DIER_TIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 13498 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 13499 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
sahilmgandhi 18:6a4db94011d3 13500 #define TIM_DIER_BIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13501 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13502 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
sahilmgandhi 18:6a4db94011d3 13503 #define TIM_DIER_UDE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13504 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13505 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
sahilmgandhi 18:6a4db94011d3 13506 #define TIM_DIER_CC1DE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 13507 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 13508 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
sahilmgandhi 18:6a4db94011d3 13509 #define TIM_DIER_CC2DE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13510 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13511 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
sahilmgandhi 18:6a4db94011d3 13512 #define TIM_DIER_CC3DE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13513 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13514 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
sahilmgandhi 18:6a4db94011d3 13515 #define TIM_DIER_CC4DE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13516 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 13517 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
sahilmgandhi 18:6a4db94011d3 13518 #define TIM_DIER_COMDE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 13519 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 13520 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
sahilmgandhi 18:6a4db94011d3 13521 #define TIM_DIER_TDE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 13522 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 13523 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
sahilmgandhi 18:6a4db94011d3 13524
sahilmgandhi 18:6a4db94011d3 13525 /******************** Bit definition for TIM_SR register ********************/
sahilmgandhi 18:6a4db94011d3 13526 #define TIM_SR_UIF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13527 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13528 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
sahilmgandhi 18:6a4db94011d3 13529 #define TIM_SR_CC1IF_Pos (1U)
sahilmgandhi 18:6a4db94011d3 13530 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 13531 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 13532 #define TIM_SR_CC2IF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13533 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13534 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 13535 #define TIM_SR_CC3IF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13536 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13537 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 13538 #define TIM_SR_CC4IF_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13539 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 13540 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
sahilmgandhi 18:6a4db94011d3 13541 #define TIM_SR_COMIF_Pos (5U)
sahilmgandhi 18:6a4db94011d3 13542 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 13543 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
sahilmgandhi 18:6a4db94011d3 13544 #define TIM_SR_TIF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 13545 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 13546 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
sahilmgandhi 18:6a4db94011d3 13547 #define TIM_SR_BIF_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13548 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13549 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
sahilmgandhi 18:6a4db94011d3 13550 #define TIM_SR_CC1OF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 13551 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 13552 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 13553 #define TIM_SR_CC2OF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13554 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13555 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 13556 #define TIM_SR_CC3OF_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13557 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13558 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 13559 #define TIM_SR_CC4OF_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13560 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 13561 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
sahilmgandhi 18:6a4db94011d3 13562
sahilmgandhi 18:6a4db94011d3 13563 /******************* Bit definition for TIM_EGR register ********************/
sahilmgandhi 18:6a4db94011d3 13564 #define TIM_EGR_UG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13565 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13566 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
sahilmgandhi 18:6a4db94011d3 13567 #define TIM_EGR_CC1G_Pos (1U)
sahilmgandhi 18:6a4db94011d3 13568 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 13569 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
sahilmgandhi 18:6a4db94011d3 13570 #define TIM_EGR_CC2G_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13571 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13572 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
sahilmgandhi 18:6a4db94011d3 13573 #define TIM_EGR_CC3G_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13574 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13575 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
sahilmgandhi 18:6a4db94011d3 13576 #define TIM_EGR_CC4G_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13577 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 13578 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
sahilmgandhi 18:6a4db94011d3 13579 #define TIM_EGR_COMG_Pos (5U)
sahilmgandhi 18:6a4db94011d3 13580 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 13581 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
sahilmgandhi 18:6a4db94011d3 13582 #define TIM_EGR_TG_Pos (6U)
sahilmgandhi 18:6a4db94011d3 13583 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 13584 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
sahilmgandhi 18:6a4db94011d3 13585 #define TIM_EGR_BG_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13586 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13587 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
sahilmgandhi 18:6a4db94011d3 13588
sahilmgandhi 18:6a4db94011d3 13589 /****************** Bit definition for TIM_CCMR1 register *******************/
sahilmgandhi 18:6a4db94011d3 13590 #define TIM_CCMR1_CC1S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13591 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 13592 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
sahilmgandhi 18:6a4db94011d3 13593 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
sahilmgandhi 18:6a4db94011d3 13594 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
sahilmgandhi 18:6a4db94011d3 13595
sahilmgandhi 18:6a4db94011d3 13596 #define TIM_CCMR1_OC1FE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13597 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13598 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
sahilmgandhi 18:6a4db94011d3 13599 #define TIM_CCMR1_OC1PE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13600 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13601 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
sahilmgandhi 18:6a4db94011d3 13602
sahilmgandhi 18:6a4db94011d3 13603 #define TIM_CCMR1_OC1M_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13604 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 13605 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
sahilmgandhi 18:6a4db94011d3 13606 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 13607 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 13608 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13609
sahilmgandhi 18:6a4db94011d3 13610 #define TIM_CCMR1_OC1CE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13611 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13612 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
sahilmgandhi 18:6a4db94011d3 13613
sahilmgandhi 18:6a4db94011d3 13614 #define TIM_CCMR1_CC2S_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13615 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 13616 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
sahilmgandhi 18:6a4db94011d3 13617 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
sahilmgandhi 18:6a4db94011d3 13618 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
sahilmgandhi 18:6a4db94011d3 13619
sahilmgandhi 18:6a4db94011d3 13620 #define TIM_CCMR1_OC2FE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13621 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13622 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
sahilmgandhi 18:6a4db94011d3 13623 #define TIM_CCMR1_OC2PE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13624 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13625 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
sahilmgandhi 18:6a4db94011d3 13626
sahilmgandhi 18:6a4db94011d3 13627 #define TIM_CCMR1_OC2M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13628 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 13629 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
sahilmgandhi 18:6a4db94011d3 13630 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
sahilmgandhi 18:6a4db94011d3 13631 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
sahilmgandhi 18:6a4db94011d3 13632 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
sahilmgandhi 18:6a4db94011d3 13633
sahilmgandhi 18:6a4db94011d3 13634 #define TIM_CCMR1_OC2CE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 13635 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 13636 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
sahilmgandhi 18:6a4db94011d3 13637
sahilmgandhi 18:6a4db94011d3 13638 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 13639
sahilmgandhi 18:6a4db94011d3 13640 #define TIM_CCMR1_IC1PSC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13641 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 13642 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
sahilmgandhi 18:6a4db94011d3 13643 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
sahilmgandhi 18:6a4db94011d3 13644 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
sahilmgandhi 18:6a4db94011d3 13645
sahilmgandhi 18:6a4db94011d3 13646 #define TIM_CCMR1_IC1F_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13647 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 13648 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
sahilmgandhi 18:6a4db94011d3 13649 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 13650 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 13651 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13652 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
sahilmgandhi 18:6a4db94011d3 13653
sahilmgandhi 18:6a4db94011d3 13654 #define TIM_CCMR1_IC2PSC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13655 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 13656 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
sahilmgandhi 18:6a4db94011d3 13657 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
sahilmgandhi 18:6a4db94011d3 13658 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
sahilmgandhi 18:6a4db94011d3 13659
sahilmgandhi 18:6a4db94011d3 13660 #define TIM_CCMR1_IC2F_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13661 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 13662 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
sahilmgandhi 18:6a4db94011d3 13663 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
sahilmgandhi 18:6a4db94011d3 13664 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
sahilmgandhi 18:6a4db94011d3 13665 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
sahilmgandhi 18:6a4db94011d3 13666 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
sahilmgandhi 18:6a4db94011d3 13667
sahilmgandhi 18:6a4db94011d3 13668 /****************** Bit definition for TIM_CCMR2 register *******************/
sahilmgandhi 18:6a4db94011d3 13669 #define TIM_CCMR2_CC3S_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13670 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 13671 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
sahilmgandhi 18:6a4db94011d3 13672 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
sahilmgandhi 18:6a4db94011d3 13673 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
sahilmgandhi 18:6a4db94011d3 13674
sahilmgandhi 18:6a4db94011d3 13675 #define TIM_CCMR2_OC3FE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13676 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13677 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
sahilmgandhi 18:6a4db94011d3 13678 #define TIM_CCMR2_OC3PE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13679 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13680 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
sahilmgandhi 18:6a4db94011d3 13681
sahilmgandhi 18:6a4db94011d3 13682 #define TIM_CCMR2_OC3M_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13683 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 13684 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
sahilmgandhi 18:6a4db94011d3 13685 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 13686 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 13687 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13688
sahilmgandhi 18:6a4db94011d3 13689 #define TIM_CCMR2_OC3CE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13690 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13691 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
sahilmgandhi 18:6a4db94011d3 13692
sahilmgandhi 18:6a4db94011d3 13693 #define TIM_CCMR2_CC4S_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13694 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 13695 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
sahilmgandhi 18:6a4db94011d3 13696 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
sahilmgandhi 18:6a4db94011d3 13697 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
sahilmgandhi 18:6a4db94011d3 13698
sahilmgandhi 18:6a4db94011d3 13699 #define TIM_CCMR2_OC4FE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13700 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13701 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
sahilmgandhi 18:6a4db94011d3 13702 #define TIM_CCMR2_OC4PE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13703 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13704 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
sahilmgandhi 18:6a4db94011d3 13705
sahilmgandhi 18:6a4db94011d3 13706 #define TIM_CCMR2_OC4M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13707 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
sahilmgandhi 18:6a4db94011d3 13708 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
sahilmgandhi 18:6a4db94011d3 13709 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
sahilmgandhi 18:6a4db94011d3 13710 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
sahilmgandhi 18:6a4db94011d3 13711 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
sahilmgandhi 18:6a4db94011d3 13712
sahilmgandhi 18:6a4db94011d3 13713 #define TIM_CCMR2_OC4CE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 13714 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 13715 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
sahilmgandhi 18:6a4db94011d3 13716
sahilmgandhi 18:6a4db94011d3 13717 /*----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 13718
sahilmgandhi 18:6a4db94011d3 13719 #define TIM_CCMR2_IC3PSC_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13720 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 13721 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
sahilmgandhi 18:6a4db94011d3 13722 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
sahilmgandhi 18:6a4db94011d3 13723 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
sahilmgandhi 18:6a4db94011d3 13724
sahilmgandhi 18:6a4db94011d3 13725 #define TIM_CCMR2_IC3F_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13726 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
sahilmgandhi 18:6a4db94011d3 13727 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
sahilmgandhi 18:6a4db94011d3 13728 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 13729 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 13730 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13731 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
sahilmgandhi 18:6a4db94011d3 13732
sahilmgandhi 18:6a4db94011d3 13733 #define TIM_CCMR2_IC4PSC_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13734 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 13735 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
sahilmgandhi 18:6a4db94011d3 13736 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
sahilmgandhi 18:6a4db94011d3 13737 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
sahilmgandhi 18:6a4db94011d3 13738
sahilmgandhi 18:6a4db94011d3 13739 #define TIM_CCMR2_IC4F_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13740 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
sahilmgandhi 18:6a4db94011d3 13741 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
sahilmgandhi 18:6a4db94011d3 13742 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
sahilmgandhi 18:6a4db94011d3 13743 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
sahilmgandhi 18:6a4db94011d3 13744 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
sahilmgandhi 18:6a4db94011d3 13745 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
sahilmgandhi 18:6a4db94011d3 13746
sahilmgandhi 18:6a4db94011d3 13747 /******************* Bit definition for TIM_CCER register *******************/
sahilmgandhi 18:6a4db94011d3 13748 #define TIM_CCER_CC1E_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13749 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13750 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
sahilmgandhi 18:6a4db94011d3 13751 #define TIM_CCER_CC1P_Pos (1U)
sahilmgandhi 18:6a4db94011d3 13752 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 13753 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
sahilmgandhi 18:6a4db94011d3 13754 #define TIM_CCER_CC1NE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13755 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13756 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 13757 #define TIM_CCER_CC1NP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13758 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13759 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 13760 #define TIM_CCER_CC2E_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13761 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 13762 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
sahilmgandhi 18:6a4db94011d3 13763 #define TIM_CCER_CC2P_Pos (5U)
sahilmgandhi 18:6a4db94011d3 13764 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 13765 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
sahilmgandhi 18:6a4db94011d3 13766 #define TIM_CCER_CC2NE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 13767 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 13768 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 13769 #define TIM_CCER_CC2NP_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13770 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13771 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 13772 #define TIM_CCER_CC3E_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13773 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13774 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
sahilmgandhi 18:6a4db94011d3 13775 #define TIM_CCER_CC3P_Pos (9U)
sahilmgandhi 18:6a4db94011d3 13776 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 13777 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
sahilmgandhi 18:6a4db94011d3 13778 #define TIM_CCER_CC3NE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13779 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13780 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
sahilmgandhi 18:6a4db94011d3 13781 #define TIM_CCER_CC3NP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13782 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13783 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 13784 #define TIM_CCER_CC4E_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13785 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 13786 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
sahilmgandhi 18:6a4db94011d3 13787 #define TIM_CCER_CC4P_Pos (13U)
sahilmgandhi 18:6a4db94011d3 13788 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 13789 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
sahilmgandhi 18:6a4db94011d3 13790 #define TIM_CCER_CC4NP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 13791 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 13792 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
sahilmgandhi 18:6a4db94011d3 13793
sahilmgandhi 18:6a4db94011d3 13794 /******************* Bit definition for TIM_CNT register ********************/
sahilmgandhi 18:6a4db94011d3 13795 #define TIM_CNT_CNT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13796 #define TIM_CNT_CNT_Msk (0xFFFFU << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 13797 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
sahilmgandhi 18:6a4db94011d3 13798
sahilmgandhi 18:6a4db94011d3 13799 /******************* Bit definition for TIM_PSC register ********************/
sahilmgandhi 18:6a4db94011d3 13800 #define TIM_PSC_PSC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13801 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 13802 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
sahilmgandhi 18:6a4db94011d3 13803
sahilmgandhi 18:6a4db94011d3 13804 /******************* Bit definition for TIM_ARR register ********************/
sahilmgandhi 18:6a4db94011d3 13805 #define TIM_ARR_ARR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13806 #define TIM_ARR_ARR_Msk (0xFFFFU << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 13807 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
sahilmgandhi 18:6a4db94011d3 13808
sahilmgandhi 18:6a4db94011d3 13809 /******************* Bit definition for TIM_RCR register ********************/
sahilmgandhi 18:6a4db94011d3 13810 #define TIM_RCR_REP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13811 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 13812 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
sahilmgandhi 18:6a4db94011d3 13813
sahilmgandhi 18:6a4db94011d3 13814 /******************* Bit definition for TIM_CCR1 register *******************/
sahilmgandhi 18:6a4db94011d3 13815 #define TIM_CCR1_CCR1_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13816 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 13817 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
sahilmgandhi 18:6a4db94011d3 13818
sahilmgandhi 18:6a4db94011d3 13819 /******************* Bit definition for TIM_CCR2 register *******************/
sahilmgandhi 18:6a4db94011d3 13820 #define TIM_CCR2_CCR2_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13821 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 13822 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
sahilmgandhi 18:6a4db94011d3 13823
sahilmgandhi 18:6a4db94011d3 13824 /******************* Bit definition for TIM_CCR3 register *******************/
sahilmgandhi 18:6a4db94011d3 13825 #define TIM_CCR3_CCR3_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13826 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 13827 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
sahilmgandhi 18:6a4db94011d3 13828
sahilmgandhi 18:6a4db94011d3 13829 /******************* Bit definition for TIM_CCR4 register *******************/
sahilmgandhi 18:6a4db94011d3 13830 #define TIM_CCR4_CCR4_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13831 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 13832 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
sahilmgandhi 18:6a4db94011d3 13833
sahilmgandhi 18:6a4db94011d3 13834 /******************* Bit definition for TIM_BDTR register *******************/
sahilmgandhi 18:6a4db94011d3 13835 #define TIM_BDTR_DTG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13836 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 13837 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
sahilmgandhi 18:6a4db94011d3 13838 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
sahilmgandhi 18:6a4db94011d3 13839 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
sahilmgandhi 18:6a4db94011d3 13840 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
sahilmgandhi 18:6a4db94011d3 13841 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
sahilmgandhi 18:6a4db94011d3 13842 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 13843 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 13844 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13845 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
sahilmgandhi 18:6a4db94011d3 13846
sahilmgandhi 18:6a4db94011d3 13847 #define TIM_BDTR_LOCK_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13848 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 13849 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
sahilmgandhi 18:6a4db94011d3 13850 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
sahilmgandhi 18:6a4db94011d3 13851 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
sahilmgandhi 18:6a4db94011d3 13852
sahilmgandhi 18:6a4db94011d3 13853 #define TIM_BDTR_OSSI_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13854 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13855 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
sahilmgandhi 18:6a4db94011d3 13856 #define TIM_BDTR_OSSR_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13857 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13858 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
sahilmgandhi 18:6a4db94011d3 13859 #define TIM_BDTR_BKE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13860 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 13861 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
sahilmgandhi 18:6a4db94011d3 13862 #define TIM_BDTR_BKP_Pos (13U)
sahilmgandhi 18:6a4db94011d3 13863 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 13864 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
sahilmgandhi 18:6a4db94011d3 13865 #define TIM_BDTR_AOE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 13866 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 13867 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
sahilmgandhi 18:6a4db94011d3 13868 #define TIM_BDTR_MOE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 13869 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 13870 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
sahilmgandhi 18:6a4db94011d3 13871
sahilmgandhi 18:6a4db94011d3 13872 /******************* Bit definition for TIM_DCR register ********************/
sahilmgandhi 18:6a4db94011d3 13873 #define TIM_DCR_DBA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13874 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
sahilmgandhi 18:6a4db94011d3 13875 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
sahilmgandhi 18:6a4db94011d3 13876 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
sahilmgandhi 18:6a4db94011d3 13877 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
sahilmgandhi 18:6a4db94011d3 13878 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
sahilmgandhi 18:6a4db94011d3 13879 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
sahilmgandhi 18:6a4db94011d3 13880 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 13881
sahilmgandhi 18:6a4db94011d3 13882 #define TIM_DCR_DBL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13883 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
sahilmgandhi 18:6a4db94011d3 13884 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
sahilmgandhi 18:6a4db94011d3 13885 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
sahilmgandhi 18:6a4db94011d3 13886 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
sahilmgandhi 18:6a4db94011d3 13887 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
sahilmgandhi 18:6a4db94011d3 13888 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
sahilmgandhi 18:6a4db94011d3 13889 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
sahilmgandhi 18:6a4db94011d3 13890
sahilmgandhi 18:6a4db94011d3 13891 /******************* Bit definition for TIM_DMAR register *******************/
sahilmgandhi 18:6a4db94011d3 13892 #define TIM_DMAR_DMAB_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13893 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 13894 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
sahilmgandhi 18:6a4db94011d3 13895
sahilmgandhi 18:6a4db94011d3 13896 /******************* Bit definition for TIM_OR register *********************/
sahilmgandhi 18:6a4db94011d3 13897 #define TIM_OR_TI4_RMP_Pos (6U)
sahilmgandhi 18:6a4db94011d3 13898 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 13899 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
sahilmgandhi 18:6a4db94011d3 13900 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 13901 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
sahilmgandhi 18:6a4db94011d3 13902 #define TIM_OR_ITR1_RMP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13903 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 13904 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
sahilmgandhi 18:6a4db94011d3 13905 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
sahilmgandhi 18:6a4db94011d3 13906 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
sahilmgandhi 18:6a4db94011d3 13907
sahilmgandhi 18:6a4db94011d3 13908
sahilmgandhi 18:6a4db94011d3 13909 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 13910 /* */
sahilmgandhi 18:6a4db94011d3 13911 /* Universal Synchronous Asynchronous Receiver Transmitter */
sahilmgandhi 18:6a4db94011d3 13912 /* */
sahilmgandhi 18:6a4db94011d3 13913 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 13914 /******************* Bit definition for USART_SR register *******************/
sahilmgandhi 18:6a4db94011d3 13915 #define USART_SR_PE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13916 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13917 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
sahilmgandhi 18:6a4db94011d3 13918 #define USART_SR_FE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 13919 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 13920 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
sahilmgandhi 18:6a4db94011d3 13921 #define USART_SR_NE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13922 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13923 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
sahilmgandhi 18:6a4db94011d3 13924 #define USART_SR_ORE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13925 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13926 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
sahilmgandhi 18:6a4db94011d3 13927 #define USART_SR_IDLE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13928 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 13929 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
sahilmgandhi 18:6a4db94011d3 13930 #define USART_SR_RXNE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 13931 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 13932 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
sahilmgandhi 18:6a4db94011d3 13933 #define USART_SR_TC_Pos (6U)
sahilmgandhi 18:6a4db94011d3 13934 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 13935 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
sahilmgandhi 18:6a4db94011d3 13936 #define USART_SR_TXE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13937 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13938 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
sahilmgandhi 18:6a4db94011d3 13939 #define USART_SR_LBD_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13940 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13941 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
sahilmgandhi 18:6a4db94011d3 13942 #define USART_SR_CTS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 13943 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 13944 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
sahilmgandhi 18:6a4db94011d3 13945
sahilmgandhi 18:6a4db94011d3 13946 /******************* Bit definition for USART_DR register *******************/
sahilmgandhi 18:6a4db94011d3 13947 #define USART_DR_DR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13948 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
sahilmgandhi 18:6a4db94011d3 13949 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
sahilmgandhi 18:6a4db94011d3 13950
sahilmgandhi 18:6a4db94011d3 13951 /****************** Bit definition for USART_BRR register *******************/
sahilmgandhi 18:6a4db94011d3 13952 #define USART_BRR_DIV_Fraction_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13953 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 13954 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
sahilmgandhi 18:6a4db94011d3 13955 #define USART_BRR_DIV_Mantissa_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13956 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
sahilmgandhi 18:6a4db94011d3 13957 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
sahilmgandhi 18:6a4db94011d3 13958
sahilmgandhi 18:6a4db94011d3 13959 /****************** Bit definition for USART_CR1 register *******************/
sahilmgandhi 18:6a4db94011d3 13960 #define USART_CR1_SBK_Pos (0U)
sahilmgandhi 18:6a4db94011d3 13961 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 13962 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
sahilmgandhi 18:6a4db94011d3 13963 #define USART_CR1_RWU_Pos (1U)
sahilmgandhi 18:6a4db94011d3 13964 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 13965 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
sahilmgandhi 18:6a4db94011d3 13966 #define USART_CR1_RE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 13967 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 13968 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
sahilmgandhi 18:6a4db94011d3 13969 #define USART_CR1_TE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 13970 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 13971 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
sahilmgandhi 18:6a4db94011d3 13972 #define USART_CR1_IDLEIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 13973 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 13974 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 13975 #define USART_CR1_RXNEIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 13976 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 13977 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 13978 #define USART_CR1_TCIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 13979 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 13980 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 13981 #define USART_CR1_TXEIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 13982 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 13983 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 13984 #define USART_CR1_PEIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 13985 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 13986 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 13987 #define USART_CR1_PS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 13988 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 13989 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
sahilmgandhi 18:6a4db94011d3 13990 #define USART_CR1_PCE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 13991 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 13992 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
sahilmgandhi 18:6a4db94011d3 13993 #define USART_CR1_WAKE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 13994 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 13995 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
sahilmgandhi 18:6a4db94011d3 13996 #define USART_CR1_M_Pos (12U)
sahilmgandhi 18:6a4db94011d3 13997 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 13998 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
sahilmgandhi 18:6a4db94011d3 13999 #define USART_CR1_UE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 14000 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 14001 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
sahilmgandhi 18:6a4db94011d3 14002 #define USART_CR1_OVER8_Pos (15U)
sahilmgandhi 18:6a4db94011d3 14003 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 14004 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
sahilmgandhi 18:6a4db94011d3 14005
sahilmgandhi 18:6a4db94011d3 14006 /****************** Bit definition for USART_CR2 register *******************/
sahilmgandhi 18:6a4db94011d3 14007 #define USART_CR2_ADD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14008 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 14009 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
sahilmgandhi 18:6a4db94011d3 14010 #define USART_CR2_LBDL_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14011 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14012 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
sahilmgandhi 18:6a4db94011d3 14013 #define USART_CR2_LBDIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14014 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14015 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 14016 #define USART_CR2_LBCL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14017 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 14018 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
sahilmgandhi 18:6a4db94011d3 14019 #define USART_CR2_CPHA_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14020 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14021 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
sahilmgandhi 18:6a4db94011d3 14022 #define USART_CR2_CPOL_Pos (10U)
sahilmgandhi 18:6a4db94011d3 14023 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 14024 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
sahilmgandhi 18:6a4db94011d3 14025 #define USART_CR2_CLKEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 14026 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 14027 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
sahilmgandhi 18:6a4db94011d3 14028
sahilmgandhi 18:6a4db94011d3 14029 #define USART_CR2_STOP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 14030 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
sahilmgandhi 18:6a4db94011d3 14031 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
sahilmgandhi 18:6a4db94011d3 14032 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
sahilmgandhi 18:6a4db94011d3 14033 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
sahilmgandhi 18:6a4db94011d3 14034
sahilmgandhi 18:6a4db94011d3 14035 #define USART_CR2_LINEN_Pos (14U)
sahilmgandhi 18:6a4db94011d3 14036 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 14037 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
sahilmgandhi 18:6a4db94011d3 14038
sahilmgandhi 18:6a4db94011d3 14039 /****************** Bit definition for USART_CR3 register *******************/
sahilmgandhi 18:6a4db94011d3 14040 #define USART_CR3_EIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14041 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14042 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 14043 #define USART_CR3_IREN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14044 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14045 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
sahilmgandhi 18:6a4db94011d3 14046 #define USART_CR3_IRLP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14047 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14048 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
sahilmgandhi 18:6a4db94011d3 14049 #define USART_CR3_HDSEL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14050 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14051 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
sahilmgandhi 18:6a4db94011d3 14052 #define USART_CR3_NACK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14053 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14054 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
sahilmgandhi 18:6a4db94011d3 14055 #define USART_CR3_SCEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14056 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14057 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
sahilmgandhi 18:6a4db94011d3 14058 #define USART_CR3_DMAR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14059 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14060 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
sahilmgandhi 18:6a4db94011d3 14061 #define USART_CR3_DMAT_Pos (7U)
sahilmgandhi 18:6a4db94011d3 14062 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 14063 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
sahilmgandhi 18:6a4db94011d3 14064 #define USART_CR3_RTSE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14065 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 14066 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
sahilmgandhi 18:6a4db94011d3 14067 #define USART_CR3_CTSE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14068 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14069 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
sahilmgandhi 18:6a4db94011d3 14070 #define USART_CR3_CTSIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 14071 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 14072 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 14073 #define USART_CR3_ONEBIT_Pos (11U)
sahilmgandhi 18:6a4db94011d3 14074 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 14075 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
sahilmgandhi 18:6a4db94011d3 14076
sahilmgandhi 18:6a4db94011d3 14077 /****************** Bit definition for USART_GTPR register ******************/
sahilmgandhi 18:6a4db94011d3 14078 #define USART_GTPR_PSC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14079 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 14080 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
sahilmgandhi 18:6a4db94011d3 14081 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
sahilmgandhi 18:6a4db94011d3 14082 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
sahilmgandhi 18:6a4db94011d3 14083 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
sahilmgandhi 18:6a4db94011d3 14084 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
sahilmgandhi 18:6a4db94011d3 14085 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 14086 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 14087 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 14088 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
sahilmgandhi 18:6a4db94011d3 14089
sahilmgandhi 18:6a4db94011d3 14090 #define USART_GTPR_GT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14091 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
sahilmgandhi 18:6a4db94011d3 14092 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
sahilmgandhi 18:6a4db94011d3 14093
sahilmgandhi 18:6a4db94011d3 14094 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14095 /* */
sahilmgandhi 18:6a4db94011d3 14096 /* Window WATCHDOG */
sahilmgandhi 18:6a4db94011d3 14097 /* */
sahilmgandhi 18:6a4db94011d3 14098 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14099 /******************* Bit definition for WWDG_CR register ********************/
sahilmgandhi 18:6a4db94011d3 14100 #define WWDG_CR_T_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14101 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
sahilmgandhi 18:6a4db94011d3 14102 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
sahilmgandhi 18:6a4db94011d3 14103 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
sahilmgandhi 18:6a4db94011d3 14104 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
sahilmgandhi 18:6a4db94011d3 14105 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
sahilmgandhi 18:6a4db94011d3 14106 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
sahilmgandhi 18:6a4db94011d3 14107 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
sahilmgandhi 18:6a4db94011d3 14108 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
sahilmgandhi 18:6a4db94011d3 14109 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
sahilmgandhi 18:6a4db94011d3 14110 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 14111 #define WWDG_CR_T0 WWDG_CR_T_0
sahilmgandhi 18:6a4db94011d3 14112 #define WWDG_CR_T1 WWDG_CR_T_1
sahilmgandhi 18:6a4db94011d3 14113 #define WWDG_CR_T2 WWDG_CR_T_2
sahilmgandhi 18:6a4db94011d3 14114 #define WWDG_CR_T3 WWDG_CR_T_3
sahilmgandhi 18:6a4db94011d3 14115 #define WWDG_CR_T4 WWDG_CR_T_4
sahilmgandhi 18:6a4db94011d3 14116 #define WWDG_CR_T5 WWDG_CR_T_5
sahilmgandhi 18:6a4db94011d3 14117 #define WWDG_CR_T6 WWDG_CR_T_6
sahilmgandhi 18:6a4db94011d3 14118
sahilmgandhi 18:6a4db94011d3 14119 #define WWDG_CR_WDGA_Pos (7U)
sahilmgandhi 18:6a4db94011d3 14120 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 14121 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
sahilmgandhi 18:6a4db94011d3 14122
sahilmgandhi 18:6a4db94011d3 14123 /******************* Bit definition for WWDG_CFR register *******************/
sahilmgandhi 18:6a4db94011d3 14124 #define WWDG_CFR_W_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14125 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
sahilmgandhi 18:6a4db94011d3 14126 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
sahilmgandhi 18:6a4db94011d3 14127 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
sahilmgandhi 18:6a4db94011d3 14128 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
sahilmgandhi 18:6a4db94011d3 14129 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
sahilmgandhi 18:6a4db94011d3 14130 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
sahilmgandhi 18:6a4db94011d3 14131 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
sahilmgandhi 18:6a4db94011d3 14132 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
sahilmgandhi 18:6a4db94011d3 14133 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
sahilmgandhi 18:6a4db94011d3 14134 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 14135 #define WWDG_CFR_W0 WWDG_CFR_W_0
sahilmgandhi 18:6a4db94011d3 14136 #define WWDG_CFR_W1 WWDG_CFR_W_1
sahilmgandhi 18:6a4db94011d3 14137 #define WWDG_CFR_W2 WWDG_CFR_W_2
sahilmgandhi 18:6a4db94011d3 14138 #define WWDG_CFR_W3 WWDG_CFR_W_3
sahilmgandhi 18:6a4db94011d3 14139 #define WWDG_CFR_W4 WWDG_CFR_W_4
sahilmgandhi 18:6a4db94011d3 14140 #define WWDG_CFR_W5 WWDG_CFR_W_5
sahilmgandhi 18:6a4db94011d3 14141 #define WWDG_CFR_W6 WWDG_CFR_W_6
sahilmgandhi 18:6a4db94011d3 14142
sahilmgandhi 18:6a4db94011d3 14143 #define WWDG_CFR_WDGTB_Pos (7U)
sahilmgandhi 18:6a4db94011d3 14144 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
sahilmgandhi 18:6a4db94011d3 14145 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
sahilmgandhi 18:6a4db94011d3 14146 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
sahilmgandhi 18:6a4db94011d3 14147 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
sahilmgandhi 18:6a4db94011d3 14148 /* Legacy defines */
sahilmgandhi 18:6a4db94011d3 14149 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
sahilmgandhi 18:6a4db94011d3 14150 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
sahilmgandhi 18:6a4db94011d3 14151
sahilmgandhi 18:6a4db94011d3 14152 #define WWDG_CFR_EWI_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14153 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14154 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
sahilmgandhi 18:6a4db94011d3 14155
sahilmgandhi 18:6a4db94011d3 14156 /******************* Bit definition for WWDG_SR register ********************/
sahilmgandhi 18:6a4db94011d3 14157 #define WWDG_SR_EWIF_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14158 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14159 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 14160
sahilmgandhi 18:6a4db94011d3 14161
sahilmgandhi 18:6a4db94011d3 14162 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14163 /* */
sahilmgandhi 18:6a4db94011d3 14164 /* DBG */
sahilmgandhi 18:6a4db94011d3 14165 /* */
sahilmgandhi 18:6a4db94011d3 14166 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14167 /******************** Bit definition for DBGMCU_IDCODE register *************/
sahilmgandhi 18:6a4db94011d3 14168 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14169 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 14170 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
sahilmgandhi 18:6a4db94011d3 14171 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
sahilmgandhi 18:6a4db94011d3 14172 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 14173 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
sahilmgandhi 18:6a4db94011d3 14174
sahilmgandhi 18:6a4db94011d3 14175 /******************** Bit definition for DBGMCU_CR register *****************/
sahilmgandhi 18:6a4db94011d3 14176 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14177 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14178 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
sahilmgandhi 18:6a4db94011d3 14179 #define DBGMCU_CR_DBG_STOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14180 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14181 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14182 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14183 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14184 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
sahilmgandhi 18:6a4db94011d3 14185 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14186 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14187 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
sahilmgandhi 18:6a4db94011d3 14188
sahilmgandhi 18:6a4db94011d3 14189 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14190 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 14191 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
sahilmgandhi 18:6a4db94011d3 14192 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14193 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 14194
sahilmgandhi 18:6a4db94011d3 14195 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
sahilmgandhi 18:6a4db94011d3 14196 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14197 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14198 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14199 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14200 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14201 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14202 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14203 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14204 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14205 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14206 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14207 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14208 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14209 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14210 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14211 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14212 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14213 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14214 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14215 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14216 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14217 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
sahilmgandhi 18:6a4db94011d3 14218 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 14219 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14220 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14221 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 14222 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14223 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 14224 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 14225 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14226 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 14227 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 14228 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14229 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
sahilmgandhi 18:6a4db94011d3 14230 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 14231 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14232 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
sahilmgandhi 18:6a4db94011d3 14233 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 14234 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
sahilmgandhi 18:6a4db94011d3 14235 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
sahilmgandhi 18:6a4db94011d3 14236 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 14237 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
sahilmgandhi 18:6a4db94011d3 14238 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
sahilmgandhi 18:6a4db94011d3 14239 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 14240 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
sahilmgandhi 18:6a4db94011d3 14241 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
sahilmgandhi 18:6a4db94011d3 14242 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 14243 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14244 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
sahilmgandhi 18:6a4db94011d3 14245 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 14246 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14247 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
sahilmgandhi 18:6a4db94011d3 14248 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
sahilmgandhi 18:6a4db94011d3 14249
sahilmgandhi 18:6a4db94011d3 14250 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
sahilmgandhi 18:6a4db94011d3 14251 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14252 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14253 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14254 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14255 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14256 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14257 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
sahilmgandhi 18:6a4db94011d3 14258 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 14259 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14260 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
sahilmgandhi 18:6a4db94011d3 14261 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 14262 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14263 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
sahilmgandhi 18:6a4db94011d3 14264 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 14265 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
sahilmgandhi 18:6a4db94011d3 14266
sahilmgandhi 18:6a4db94011d3 14267 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14268 /* */
sahilmgandhi 18:6a4db94011d3 14269 /* Ethernet MAC Registers bits definitions */
sahilmgandhi 18:6a4db94011d3 14270 /* */
sahilmgandhi 18:6a4db94011d3 14271 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14272 /* Bit definition for Ethernet MAC Control Register register */
sahilmgandhi 18:6a4db94011d3 14273 #define ETH_MACCR_WD_Pos (23U)
sahilmgandhi 18:6a4db94011d3 14274 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 14275 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
sahilmgandhi 18:6a4db94011d3 14276 #define ETH_MACCR_JD_Pos (22U)
sahilmgandhi 18:6a4db94011d3 14277 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 14278 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
sahilmgandhi 18:6a4db94011d3 14279 #define ETH_MACCR_IFG_Pos (17U)
sahilmgandhi 18:6a4db94011d3 14280 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
sahilmgandhi 18:6a4db94011d3 14281 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
sahilmgandhi 18:6a4db94011d3 14282 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
sahilmgandhi 18:6a4db94011d3 14283 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
sahilmgandhi 18:6a4db94011d3 14284 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
sahilmgandhi 18:6a4db94011d3 14285 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
sahilmgandhi 18:6a4db94011d3 14286 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
sahilmgandhi 18:6a4db94011d3 14287 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
sahilmgandhi 18:6a4db94011d3 14288 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
sahilmgandhi 18:6a4db94011d3 14289 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
sahilmgandhi 18:6a4db94011d3 14290 #define ETH_MACCR_CSD_Pos (16U)
sahilmgandhi 18:6a4db94011d3 14291 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 14292 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
sahilmgandhi 18:6a4db94011d3 14293 #define ETH_MACCR_FES_Pos (14U)
sahilmgandhi 18:6a4db94011d3 14294 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 14295 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
sahilmgandhi 18:6a4db94011d3 14296 #define ETH_MACCR_ROD_Pos (13U)
sahilmgandhi 18:6a4db94011d3 14297 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 14298 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
sahilmgandhi 18:6a4db94011d3 14299 #define ETH_MACCR_LM_Pos (12U)
sahilmgandhi 18:6a4db94011d3 14300 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 14301 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
sahilmgandhi 18:6a4db94011d3 14302 #define ETH_MACCR_DM_Pos (11U)
sahilmgandhi 18:6a4db94011d3 14303 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 14304 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
sahilmgandhi 18:6a4db94011d3 14305 #define ETH_MACCR_IPCO_Pos (10U)
sahilmgandhi 18:6a4db94011d3 14306 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 14307 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
sahilmgandhi 18:6a4db94011d3 14308 #define ETH_MACCR_RD_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14309 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14310 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
sahilmgandhi 18:6a4db94011d3 14311 #define ETH_MACCR_APCS_Pos (7U)
sahilmgandhi 18:6a4db94011d3 14312 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 14313 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
sahilmgandhi 18:6a4db94011d3 14314 #define ETH_MACCR_BL_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14315 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 14316 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
sahilmgandhi 18:6a4db94011d3 14317 a transmission attempt during retries after a collision: 0 =< r <2^k */
sahilmgandhi 18:6a4db94011d3 14318 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
sahilmgandhi 18:6a4db94011d3 14319 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
sahilmgandhi 18:6a4db94011d3 14320 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
sahilmgandhi 18:6a4db94011d3 14321 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
sahilmgandhi 18:6a4db94011d3 14322 #define ETH_MACCR_DC_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14323 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14324 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
sahilmgandhi 18:6a4db94011d3 14325 #define ETH_MACCR_TE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14326 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14327 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
sahilmgandhi 18:6a4db94011d3 14328 #define ETH_MACCR_RE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14329 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14330 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
sahilmgandhi 18:6a4db94011d3 14331
sahilmgandhi 18:6a4db94011d3 14332 /* Bit definition for Ethernet MAC Frame Filter Register */
sahilmgandhi 18:6a4db94011d3 14333 #define ETH_MACFFR_RA_Pos (31U)
sahilmgandhi 18:6a4db94011d3 14334 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 14335 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
sahilmgandhi 18:6a4db94011d3 14336 #define ETH_MACFFR_HPF_Pos (10U)
sahilmgandhi 18:6a4db94011d3 14337 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 14338 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
sahilmgandhi 18:6a4db94011d3 14339 #define ETH_MACFFR_SAF_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14340 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14341 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
sahilmgandhi 18:6a4db94011d3 14342 #define ETH_MACFFR_SAIF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14343 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 14344 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
sahilmgandhi 18:6a4db94011d3 14345 #define ETH_MACFFR_PCF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14346 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 14347 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
sahilmgandhi 18:6a4db94011d3 14348 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14349 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14350 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
sahilmgandhi 18:6a4db94011d3 14351 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
sahilmgandhi 18:6a4db94011d3 14352 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 14353 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
sahilmgandhi 18:6a4db94011d3 14354 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14355 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
sahilmgandhi 18:6a4db94011d3 14356 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
sahilmgandhi 18:6a4db94011d3 14357 #define ETH_MACFFR_BFD_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14358 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14359 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
sahilmgandhi 18:6a4db94011d3 14360 #define ETH_MACFFR_PAM_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14361 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14362 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
sahilmgandhi 18:6a4db94011d3 14363 #define ETH_MACFFR_DAIF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14364 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14365 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
sahilmgandhi 18:6a4db94011d3 14366 #define ETH_MACFFR_HM_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14367 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14368 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
sahilmgandhi 18:6a4db94011d3 14369 #define ETH_MACFFR_HU_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14370 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14371 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
sahilmgandhi 18:6a4db94011d3 14372 #define ETH_MACFFR_PM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14373 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14374 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
sahilmgandhi 18:6a4db94011d3 14375
sahilmgandhi 18:6a4db94011d3 14376 /* Bit definition for Ethernet MAC Hash Table High Register */
sahilmgandhi 18:6a4db94011d3 14377 #define ETH_MACHTHR_HTH_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14378 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14379 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
sahilmgandhi 18:6a4db94011d3 14380
sahilmgandhi 18:6a4db94011d3 14381 /* Bit definition for Ethernet MAC Hash Table Low Register */
sahilmgandhi 18:6a4db94011d3 14382 #define ETH_MACHTLR_HTL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14383 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14384 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
sahilmgandhi 18:6a4db94011d3 14385
sahilmgandhi 18:6a4db94011d3 14386 /* Bit definition for Ethernet MAC MII Address Register */
sahilmgandhi 18:6a4db94011d3 14387 #define ETH_MACMIIAR_PA_Pos (11U)
sahilmgandhi 18:6a4db94011d3 14388 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
sahilmgandhi 18:6a4db94011d3 14389 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
sahilmgandhi 18:6a4db94011d3 14390 #define ETH_MACMIIAR_MR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14391 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
sahilmgandhi 18:6a4db94011d3 14392 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
sahilmgandhi 18:6a4db94011d3 14393 #define ETH_MACMIIAR_CR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14394 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
sahilmgandhi 18:6a4db94011d3 14395 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
sahilmgandhi 18:6a4db94011d3 14396 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
sahilmgandhi 18:6a4db94011d3 14397 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14398 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14399 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
sahilmgandhi 18:6a4db94011d3 14400 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14401 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14402 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
sahilmgandhi 18:6a4db94011d3 14403 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14404 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
sahilmgandhi 18:6a4db94011d3 14405 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
sahilmgandhi 18:6a4db94011d3 14406 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14407 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14408 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
sahilmgandhi 18:6a4db94011d3 14409 #define ETH_MACMIIAR_MW_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14410 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14411 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
sahilmgandhi 18:6a4db94011d3 14412 #define ETH_MACMIIAR_MB_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14413 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14414 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
sahilmgandhi 18:6a4db94011d3 14415
sahilmgandhi 18:6a4db94011d3 14416 /* Bit definition for Ethernet MAC MII Data Register */
sahilmgandhi 18:6a4db94011d3 14417 #define ETH_MACMIIDR_MD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14418 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 14419 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
sahilmgandhi 18:6a4db94011d3 14420
sahilmgandhi 18:6a4db94011d3 14421 /* Bit definition for Ethernet MAC Flow Control Register */
sahilmgandhi 18:6a4db94011d3 14422 #define ETH_MACFCR_PT_Pos (16U)
sahilmgandhi 18:6a4db94011d3 14423 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 14424 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
sahilmgandhi 18:6a4db94011d3 14425 #define ETH_MACFCR_ZQPD_Pos (7U)
sahilmgandhi 18:6a4db94011d3 14426 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 14427 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
sahilmgandhi 18:6a4db94011d3 14428 #define ETH_MACFCR_PLT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14429 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 14430 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
sahilmgandhi 18:6a4db94011d3 14431 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
sahilmgandhi 18:6a4db94011d3 14432 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14433 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14434 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
sahilmgandhi 18:6a4db94011d3 14435 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14436 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14437 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
sahilmgandhi 18:6a4db94011d3 14438 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14439 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
sahilmgandhi 18:6a4db94011d3 14440 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
sahilmgandhi 18:6a4db94011d3 14441 #define ETH_MACFCR_UPFD_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14442 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14443 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
sahilmgandhi 18:6a4db94011d3 14444 #define ETH_MACFCR_RFCE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14445 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14446 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
sahilmgandhi 18:6a4db94011d3 14447 #define ETH_MACFCR_TFCE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14448 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14449 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
sahilmgandhi 18:6a4db94011d3 14450 #define ETH_MACFCR_FCBBPA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14451 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14452 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
sahilmgandhi 18:6a4db94011d3 14453
sahilmgandhi 18:6a4db94011d3 14454 /* Bit definition for Ethernet MAC VLAN Tag Register */
sahilmgandhi 18:6a4db94011d3 14455 #define ETH_MACVLANTR_VLANTC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 14456 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 14457 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
sahilmgandhi 18:6a4db94011d3 14458 #define ETH_MACVLANTR_VLANTI_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14459 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 14460 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
sahilmgandhi 18:6a4db94011d3 14461
sahilmgandhi 18:6a4db94011d3 14462 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
sahilmgandhi 18:6a4db94011d3 14463 #define ETH_MACRWUFFR_D_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14464 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14465 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
sahilmgandhi 18:6a4db94011d3 14466 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
sahilmgandhi 18:6a4db94011d3 14467 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
sahilmgandhi 18:6a4db94011d3 14468 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
sahilmgandhi 18:6a4db94011d3 14469 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
sahilmgandhi 18:6a4db94011d3 14470 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
sahilmgandhi 18:6a4db94011d3 14471 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
sahilmgandhi 18:6a4db94011d3 14472 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
sahilmgandhi 18:6a4db94011d3 14473 RSVD - Filter1 Command - RSVD - Filter0 Command
sahilmgandhi 18:6a4db94011d3 14474 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
sahilmgandhi 18:6a4db94011d3 14475 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
sahilmgandhi 18:6a4db94011d3 14476 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
sahilmgandhi 18:6a4db94011d3 14477
sahilmgandhi 18:6a4db94011d3 14478 /* Bit definition for Ethernet MAC PMT Control and Status Register */
sahilmgandhi 18:6a4db94011d3 14479 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
sahilmgandhi 18:6a4db94011d3 14480 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 14481 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
sahilmgandhi 18:6a4db94011d3 14482 #define ETH_MACPMTCSR_GU_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14483 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14484 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
sahilmgandhi 18:6a4db94011d3 14485 #define ETH_MACPMTCSR_WFR_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14486 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14487 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
sahilmgandhi 18:6a4db94011d3 14488 #define ETH_MACPMTCSR_MPR_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14489 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14490 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
sahilmgandhi 18:6a4db94011d3 14491 #define ETH_MACPMTCSR_WFE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14492 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14493 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
sahilmgandhi 18:6a4db94011d3 14494 #define ETH_MACPMTCSR_MPE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14495 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14496 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
sahilmgandhi 18:6a4db94011d3 14497 #define ETH_MACPMTCSR_PD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14498 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14499 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
sahilmgandhi 18:6a4db94011d3 14500
sahilmgandhi 18:6a4db94011d3 14501 /* Bit definition for Ethernet MAC debug Register */
sahilmgandhi 18:6a4db94011d3 14502 #define ETH_MACDBGR_TFF_Pos (25U)
sahilmgandhi 18:6a4db94011d3 14503 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 14504 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
sahilmgandhi 18:6a4db94011d3 14505 #define ETH_MACDBGR_TFNE_Pos (24U)
sahilmgandhi 18:6a4db94011d3 14506 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 14507 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
sahilmgandhi 18:6a4db94011d3 14508 #define ETH_MACDBGR_TPWA_Pos (22U)
sahilmgandhi 18:6a4db94011d3 14509 #define ETH_MACDBGR_TPWA_Msk (0x1U << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 14510 #define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
sahilmgandhi 18:6a4db94011d3 14511 #define ETH_MACDBGR_TFRS_Pos (20U)
sahilmgandhi 18:6a4db94011d3 14512 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 14513 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
sahilmgandhi 18:6a4db94011d3 14514 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
sahilmgandhi 18:6a4db94011d3 14515 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 14516 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
sahilmgandhi 18:6a4db94011d3 14517 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
sahilmgandhi 18:6a4db94011d3 14518 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 14519 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
sahilmgandhi 18:6a4db94011d3 14520 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
sahilmgandhi 18:6a4db94011d3 14521 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 14522 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
sahilmgandhi 18:6a4db94011d3 14523 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
sahilmgandhi 18:6a4db94011d3 14524 #define ETH_MACDBGR_MTP_Pos (19U)
sahilmgandhi 18:6a4db94011d3 14525 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 14526 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
sahilmgandhi 18:6a4db94011d3 14527 #define ETH_MACDBGR_MTFCS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 14528 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
sahilmgandhi 18:6a4db94011d3 14529 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
sahilmgandhi 18:6a4db94011d3 14530 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
sahilmgandhi 18:6a4db94011d3 14531 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
sahilmgandhi 18:6a4db94011d3 14532 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
sahilmgandhi 18:6a4db94011d3 14533 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
sahilmgandhi 18:6a4db94011d3 14534 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 14535 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
sahilmgandhi 18:6a4db94011d3 14536 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
sahilmgandhi 18:6a4db94011d3 14537 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 14538 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
sahilmgandhi 18:6a4db94011d3 14539 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
sahilmgandhi 18:6a4db94011d3 14540 #define ETH_MACDBGR_MMTEA_Pos (16U)
sahilmgandhi 18:6a4db94011d3 14541 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 14542 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
sahilmgandhi 18:6a4db94011d3 14543 #define ETH_MACDBGR_RFFL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14544 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 14545 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
sahilmgandhi 18:6a4db94011d3 14546 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14547 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
sahilmgandhi 18:6a4db94011d3 14548 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
sahilmgandhi 18:6a4db94011d3 14549 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14550 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14551 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
sahilmgandhi 18:6a4db94011d3 14552 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14553 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 14554 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
sahilmgandhi 18:6a4db94011d3 14555 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
sahilmgandhi 18:6a4db94011d3 14556 #define ETH_MACDBGR_RFRCS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14557 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 14558 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
sahilmgandhi 18:6a4db94011d3 14559 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14560 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
sahilmgandhi 18:6a4db94011d3 14561 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
sahilmgandhi 18:6a4db94011d3 14562 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14563 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14564 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
sahilmgandhi 18:6a4db94011d3 14565 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14566 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14567 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
sahilmgandhi 18:6a4db94011d3 14568 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
sahilmgandhi 18:6a4db94011d3 14569 #define ETH_MACDBGR_RFWRA_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14570 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14571 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
sahilmgandhi 18:6a4db94011d3 14572 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14573 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
sahilmgandhi 18:6a4db94011d3 14574 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
sahilmgandhi 18:6a4db94011d3 14575 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14576 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14577 #define ETH_MACDBGR_MMRPEA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14578 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14579 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
sahilmgandhi 18:6a4db94011d3 14580
sahilmgandhi 18:6a4db94011d3 14581 /* Bit definition for Ethernet MAC Status Register */
sahilmgandhi 18:6a4db94011d3 14582 #define ETH_MACSR_TSTS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14583 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14584 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
sahilmgandhi 18:6a4db94011d3 14585 #define ETH_MACSR_MMCTS_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14586 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14587 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
sahilmgandhi 18:6a4db94011d3 14588 #define ETH_MACSR_MMMCRS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14589 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14590 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
sahilmgandhi 18:6a4db94011d3 14591 #define ETH_MACSR_MMCS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14592 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14593 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
sahilmgandhi 18:6a4db94011d3 14594 #define ETH_MACSR_PMTS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14595 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14596 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
sahilmgandhi 18:6a4db94011d3 14597
sahilmgandhi 18:6a4db94011d3 14598 /* Bit definition for Ethernet MAC Interrupt Mask Register */
sahilmgandhi 18:6a4db94011d3 14599 #define ETH_MACIMR_TSTIM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14600 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14601 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
sahilmgandhi 18:6a4db94011d3 14602 #define ETH_MACIMR_PMTIM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14603 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14604 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
sahilmgandhi 18:6a4db94011d3 14605
sahilmgandhi 18:6a4db94011d3 14606 /* Bit definition for Ethernet MAC Address0 High Register */
sahilmgandhi 18:6a4db94011d3 14607 #define ETH_MACA0HR_MACA0H_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14608 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 14609 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
sahilmgandhi 18:6a4db94011d3 14610
sahilmgandhi 18:6a4db94011d3 14611 /* Bit definition for Ethernet MAC Address0 Low Register */
sahilmgandhi 18:6a4db94011d3 14612 #define ETH_MACA0LR_MACA0L_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14613 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14614 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
sahilmgandhi 18:6a4db94011d3 14615
sahilmgandhi 18:6a4db94011d3 14616 /* Bit definition for Ethernet MAC Address1 High Register */
sahilmgandhi 18:6a4db94011d3 14617 #define ETH_MACA1HR_AE_Pos (31U)
sahilmgandhi 18:6a4db94011d3 14618 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 14619 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
sahilmgandhi 18:6a4db94011d3 14620 #define ETH_MACA1HR_SA_Pos (30U)
sahilmgandhi 18:6a4db94011d3 14621 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 14622 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
sahilmgandhi 18:6a4db94011d3 14623 #define ETH_MACA1HR_MBC_Pos (24U)
sahilmgandhi 18:6a4db94011d3 14624 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
sahilmgandhi 18:6a4db94011d3 14625 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
sahilmgandhi 18:6a4db94011d3 14626 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 14627 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
sahilmgandhi 18:6a4db94011d3 14628 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
sahilmgandhi 18:6a4db94011d3 14629 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
sahilmgandhi 18:6a4db94011d3 14630 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 14631 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
sahilmgandhi 18:6a4db94011d3 14632 #define ETH_MACA1HR_MACA1H_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14633 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 14634 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
sahilmgandhi 18:6a4db94011d3 14635
sahilmgandhi 18:6a4db94011d3 14636 /* Bit definition for Ethernet MAC Address1 Low Register */
sahilmgandhi 18:6a4db94011d3 14637 #define ETH_MACA1LR_MACA1L_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14638 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14639 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
sahilmgandhi 18:6a4db94011d3 14640
sahilmgandhi 18:6a4db94011d3 14641 /* Bit definition for Ethernet MAC Address2 High Register */
sahilmgandhi 18:6a4db94011d3 14642 #define ETH_MACA2HR_AE_Pos (31U)
sahilmgandhi 18:6a4db94011d3 14643 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 14644 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
sahilmgandhi 18:6a4db94011d3 14645 #define ETH_MACA2HR_SA_Pos (30U)
sahilmgandhi 18:6a4db94011d3 14646 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 14647 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
sahilmgandhi 18:6a4db94011d3 14648 #define ETH_MACA2HR_MBC_Pos (24U)
sahilmgandhi 18:6a4db94011d3 14649 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
sahilmgandhi 18:6a4db94011d3 14650 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
sahilmgandhi 18:6a4db94011d3 14651 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 14652 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
sahilmgandhi 18:6a4db94011d3 14653 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
sahilmgandhi 18:6a4db94011d3 14654 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
sahilmgandhi 18:6a4db94011d3 14655 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 14656 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
sahilmgandhi 18:6a4db94011d3 14657 #define ETH_MACA2HR_MACA2H_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14658 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 14659 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
sahilmgandhi 18:6a4db94011d3 14660
sahilmgandhi 18:6a4db94011d3 14661 /* Bit definition for Ethernet MAC Address2 Low Register */
sahilmgandhi 18:6a4db94011d3 14662 #define ETH_MACA2LR_MACA2L_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14663 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14664 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
sahilmgandhi 18:6a4db94011d3 14665
sahilmgandhi 18:6a4db94011d3 14666 /* Bit definition for Ethernet MAC Address3 High Register */
sahilmgandhi 18:6a4db94011d3 14667 #define ETH_MACA3HR_AE_Pos (31U)
sahilmgandhi 18:6a4db94011d3 14668 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 14669 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
sahilmgandhi 18:6a4db94011d3 14670 #define ETH_MACA3HR_SA_Pos (30U)
sahilmgandhi 18:6a4db94011d3 14671 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 14672 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
sahilmgandhi 18:6a4db94011d3 14673 #define ETH_MACA3HR_MBC_Pos (24U)
sahilmgandhi 18:6a4db94011d3 14674 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
sahilmgandhi 18:6a4db94011d3 14675 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
sahilmgandhi 18:6a4db94011d3 14676 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 14677 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
sahilmgandhi 18:6a4db94011d3 14678 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
sahilmgandhi 18:6a4db94011d3 14679 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
sahilmgandhi 18:6a4db94011d3 14680 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
sahilmgandhi 18:6a4db94011d3 14681 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
sahilmgandhi 18:6a4db94011d3 14682 #define ETH_MACA3HR_MACA3H_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14683 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 14684 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
sahilmgandhi 18:6a4db94011d3 14685
sahilmgandhi 18:6a4db94011d3 14686 /* Bit definition for Ethernet MAC Address3 Low Register */
sahilmgandhi 18:6a4db94011d3 14687 #define ETH_MACA3LR_MACA3L_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14688 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14689 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
sahilmgandhi 18:6a4db94011d3 14690
sahilmgandhi 18:6a4db94011d3 14691 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14692 /* Ethernet MMC Registers bits definition */
sahilmgandhi 18:6a4db94011d3 14693 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14694
sahilmgandhi 18:6a4db94011d3 14695 /* Bit definition for Ethernet MMC Contol Register */
sahilmgandhi 18:6a4db94011d3 14696 #define ETH_MMCCR_MCFHP_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14697 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14698 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
sahilmgandhi 18:6a4db94011d3 14699 #define ETH_MMCCR_MCP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14700 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14701 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
sahilmgandhi 18:6a4db94011d3 14702 #define ETH_MMCCR_MCF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14703 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14704 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
sahilmgandhi 18:6a4db94011d3 14705 #define ETH_MMCCR_ROR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14706 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14707 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
sahilmgandhi 18:6a4db94011d3 14708 #define ETH_MMCCR_CSR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14709 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14710 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
sahilmgandhi 18:6a4db94011d3 14711 #define ETH_MMCCR_CR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14712 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14713 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
sahilmgandhi 18:6a4db94011d3 14714
sahilmgandhi 18:6a4db94011d3 14715 /* Bit definition for Ethernet MMC Receive Interrupt Register */
sahilmgandhi 18:6a4db94011d3 14716 #define ETH_MMCRIR_RGUFS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 14717 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 14718 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14719 #define ETH_MMCRIR_RFAES_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14720 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14721 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14722 #define ETH_MMCRIR_RFCES_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14723 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14724 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14725
sahilmgandhi 18:6a4db94011d3 14726 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
sahilmgandhi 18:6a4db94011d3 14727 #define ETH_MMCTIR_TGFS_Pos (21U)
sahilmgandhi 18:6a4db94011d3 14728 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 14729 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14730 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
sahilmgandhi 18:6a4db94011d3 14731 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 14732 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14733 #define ETH_MMCTIR_TGFSCS_Pos (14U)
sahilmgandhi 18:6a4db94011d3 14734 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 14735 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14736
sahilmgandhi 18:6a4db94011d3 14737 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
sahilmgandhi 18:6a4db94011d3 14738 #define ETH_MMCRIMR_RGUFM_Pos (17U)
sahilmgandhi 18:6a4db94011d3 14739 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 14740 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14741 #define ETH_MMCRIMR_RFAEM_Pos (6U)
sahilmgandhi 18:6a4db94011d3 14742 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 14743 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14744 #define ETH_MMCRIMR_RFCEM_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14745 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14746 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14747
sahilmgandhi 18:6a4db94011d3 14748 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
sahilmgandhi 18:6a4db94011d3 14749 #define ETH_MMCTIMR_TGFM_Pos (21U)
sahilmgandhi 18:6a4db94011d3 14750 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 14751 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14752 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
sahilmgandhi 18:6a4db94011d3 14753 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 14754 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14755 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
sahilmgandhi 18:6a4db94011d3 14756 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 14757 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
sahilmgandhi 18:6a4db94011d3 14758
sahilmgandhi 18:6a4db94011d3 14759 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
sahilmgandhi 18:6a4db94011d3 14760 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14761 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14762 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
sahilmgandhi 18:6a4db94011d3 14763
sahilmgandhi 18:6a4db94011d3 14764 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
sahilmgandhi 18:6a4db94011d3 14765 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14766 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14767 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
sahilmgandhi 18:6a4db94011d3 14768
sahilmgandhi 18:6a4db94011d3 14769 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
sahilmgandhi 18:6a4db94011d3 14770 #define ETH_MMCTGFCR_TGFC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14771 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14772 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
sahilmgandhi 18:6a4db94011d3 14773
sahilmgandhi 18:6a4db94011d3 14774 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
sahilmgandhi 18:6a4db94011d3 14775 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14776 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14777 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
sahilmgandhi 18:6a4db94011d3 14778
sahilmgandhi 18:6a4db94011d3 14779 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
sahilmgandhi 18:6a4db94011d3 14780 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14781 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14782 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
sahilmgandhi 18:6a4db94011d3 14783
sahilmgandhi 18:6a4db94011d3 14784 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
sahilmgandhi 18:6a4db94011d3 14785 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14786 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14787 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
sahilmgandhi 18:6a4db94011d3 14788
sahilmgandhi 18:6a4db94011d3 14789 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14790 /* Ethernet PTP Registers bits definition */
sahilmgandhi 18:6a4db94011d3 14791 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14792
sahilmgandhi 18:6a4db94011d3 14793 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
sahilmgandhi 18:6a4db94011d3 14794 #define ETH_PTPTSCR_TSCNT_Pos (16U)
sahilmgandhi 18:6a4db94011d3 14795 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
sahilmgandhi 18:6a4db94011d3 14796 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
sahilmgandhi 18:6a4db94011d3 14797 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
sahilmgandhi 18:6a4db94011d3 14798 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 14799 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
sahilmgandhi 18:6a4db94011d3 14800 #define ETH_PTPTSSR_TSSEME_Pos (14U)
sahilmgandhi 18:6a4db94011d3 14801 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 14802 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
sahilmgandhi 18:6a4db94011d3 14803 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 14804 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 14805 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
sahilmgandhi 18:6a4db94011d3 14806 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
sahilmgandhi 18:6a4db94011d3 14807 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 14808 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
sahilmgandhi 18:6a4db94011d3 14809 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 14810 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 14811 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
sahilmgandhi 18:6a4db94011d3 14812 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
sahilmgandhi 18:6a4db94011d3 14813 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 14814 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
sahilmgandhi 18:6a4db94011d3 14815 #define ETH_PTPTSSR_TSSSR_Pos (9U)
sahilmgandhi 18:6a4db94011d3 14816 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 14817 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
sahilmgandhi 18:6a4db94011d3 14818 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14819 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 14820 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
sahilmgandhi 18:6a4db94011d3 14821
sahilmgandhi 18:6a4db94011d3 14822 #define ETH_PTPTSCR_TSARU_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14823 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14824 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
sahilmgandhi 18:6a4db94011d3 14825 #define ETH_PTPTSCR_TSITE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14826 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14827 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
sahilmgandhi 18:6a4db94011d3 14828 #define ETH_PTPTSCR_TSSTU_Pos (3U)
sahilmgandhi 18:6a4db94011d3 14829 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 14830 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
sahilmgandhi 18:6a4db94011d3 14831 #define ETH_PTPTSCR_TSSTI_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14832 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 14833 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
sahilmgandhi 18:6a4db94011d3 14834 #define ETH_PTPTSCR_TSFCU_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14835 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14836 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
sahilmgandhi 18:6a4db94011d3 14837 #define ETH_PTPTSCR_TSE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14838 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14839 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
sahilmgandhi 18:6a4db94011d3 14840
sahilmgandhi 18:6a4db94011d3 14841 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
sahilmgandhi 18:6a4db94011d3 14842 #define ETH_PTPSSIR_STSSI_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14843 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
sahilmgandhi 18:6a4db94011d3 14844 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
sahilmgandhi 18:6a4db94011d3 14845
sahilmgandhi 18:6a4db94011d3 14846 /* Bit definition for Ethernet PTP Time Stamp High Register */
sahilmgandhi 18:6a4db94011d3 14847 #define ETH_PTPTSHR_STS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14848 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14849 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
sahilmgandhi 18:6a4db94011d3 14850
sahilmgandhi 18:6a4db94011d3 14851 /* Bit definition for Ethernet PTP Time Stamp Low Register */
sahilmgandhi 18:6a4db94011d3 14852 #define ETH_PTPTSLR_STPNS_Pos (31U)
sahilmgandhi 18:6a4db94011d3 14853 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 14854 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
sahilmgandhi 18:6a4db94011d3 14855 #define ETH_PTPTSLR_STSS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14856 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
sahilmgandhi 18:6a4db94011d3 14857 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
sahilmgandhi 18:6a4db94011d3 14858
sahilmgandhi 18:6a4db94011d3 14859 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
sahilmgandhi 18:6a4db94011d3 14860 #define ETH_PTPTSHUR_TSUS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14861 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14862 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
sahilmgandhi 18:6a4db94011d3 14863
sahilmgandhi 18:6a4db94011d3 14864 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
sahilmgandhi 18:6a4db94011d3 14865 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
sahilmgandhi 18:6a4db94011d3 14866 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 14867 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
sahilmgandhi 18:6a4db94011d3 14868 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14869 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
sahilmgandhi 18:6a4db94011d3 14870 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
sahilmgandhi 18:6a4db94011d3 14871
sahilmgandhi 18:6a4db94011d3 14872 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
sahilmgandhi 18:6a4db94011d3 14873 #define ETH_PTPTSAR_TSA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14874 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14875 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
sahilmgandhi 18:6a4db94011d3 14876
sahilmgandhi 18:6a4db94011d3 14877 /* Bit definition for Ethernet PTP Target Time High Register */
sahilmgandhi 18:6a4db94011d3 14878 #define ETH_PTPTTHR_TTSH_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14879 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14880 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
sahilmgandhi 18:6a4db94011d3 14881
sahilmgandhi 18:6a4db94011d3 14882 /* Bit definition for Ethernet PTP Target Time Low Register */
sahilmgandhi 18:6a4db94011d3 14883 #define ETH_PTPTTLR_TTSL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14884 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14885 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
sahilmgandhi 18:6a4db94011d3 14886
sahilmgandhi 18:6a4db94011d3 14887 /* Bit definition for Ethernet PTP Time Stamp Status Register */
sahilmgandhi 18:6a4db94011d3 14888 #define ETH_PTPTSSR_TSTTR_Pos (5U)
sahilmgandhi 18:6a4db94011d3 14889 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 14890 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
sahilmgandhi 18:6a4db94011d3 14891 #define ETH_PTPTSSR_TSSO_Pos (4U)
sahilmgandhi 18:6a4db94011d3 14892 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 14893 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
sahilmgandhi 18:6a4db94011d3 14894
sahilmgandhi 18:6a4db94011d3 14895 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14896 /* Ethernet DMA Registers bits definition */
sahilmgandhi 18:6a4db94011d3 14897 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 14898
sahilmgandhi 18:6a4db94011d3 14899 /* Bit definition for Ethernet DMA Bus Mode Register */
sahilmgandhi 18:6a4db94011d3 14900 #define ETH_DMABMR_AAB_Pos (25U)
sahilmgandhi 18:6a4db94011d3 14901 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 14902 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
sahilmgandhi 18:6a4db94011d3 14903 #define ETH_DMABMR_FPM_Pos (24U)
sahilmgandhi 18:6a4db94011d3 14904 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 14905 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
sahilmgandhi 18:6a4db94011d3 14906 #define ETH_DMABMR_USP_Pos (23U)
sahilmgandhi 18:6a4db94011d3 14907 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 14908 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
sahilmgandhi 18:6a4db94011d3 14909 #define ETH_DMABMR_RDP_Pos (17U)
sahilmgandhi 18:6a4db94011d3 14910 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
sahilmgandhi 18:6a4db94011d3 14911 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
sahilmgandhi 18:6a4db94011d3 14912 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
sahilmgandhi 18:6a4db94011d3 14913 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
sahilmgandhi 18:6a4db94011d3 14914 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
sahilmgandhi 18:6a4db94011d3 14915 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
sahilmgandhi 18:6a4db94011d3 14916 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
sahilmgandhi 18:6a4db94011d3 14917 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
sahilmgandhi 18:6a4db94011d3 14918 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
sahilmgandhi 18:6a4db94011d3 14919 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
sahilmgandhi 18:6a4db94011d3 14920 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
sahilmgandhi 18:6a4db94011d3 14921 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
sahilmgandhi 18:6a4db94011d3 14922 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
sahilmgandhi 18:6a4db94011d3 14923 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
sahilmgandhi 18:6a4db94011d3 14924 #define ETH_DMABMR_FB_Pos (16U)
sahilmgandhi 18:6a4db94011d3 14925 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 14926 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
sahilmgandhi 18:6a4db94011d3 14927 #define ETH_DMABMR_RTPR_Pos (14U)
sahilmgandhi 18:6a4db94011d3 14928 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 14929 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 14930 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 14931 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 14932 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 14933 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
sahilmgandhi 18:6a4db94011d3 14934 #define ETH_DMABMR_PBL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 14935 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
sahilmgandhi 18:6a4db94011d3 14936 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
sahilmgandhi 18:6a4db94011d3 14937 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
sahilmgandhi 18:6a4db94011d3 14938 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
sahilmgandhi 18:6a4db94011d3 14939 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
sahilmgandhi 18:6a4db94011d3 14940 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
sahilmgandhi 18:6a4db94011d3 14941 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
sahilmgandhi 18:6a4db94011d3 14942 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
sahilmgandhi 18:6a4db94011d3 14943 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
sahilmgandhi 18:6a4db94011d3 14944 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
sahilmgandhi 18:6a4db94011d3 14945 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
sahilmgandhi 18:6a4db94011d3 14946 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
sahilmgandhi 18:6a4db94011d3 14947 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
sahilmgandhi 18:6a4db94011d3 14948 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
sahilmgandhi 18:6a4db94011d3 14949 #define ETH_DMABMR_EDE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 14950 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 14951 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
sahilmgandhi 18:6a4db94011d3 14952 #define ETH_DMABMR_DSL_Pos (2U)
sahilmgandhi 18:6a4db94011d3 14953 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
sahilmgandhi 18:6a4db94011d3 14954 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
sahilmgandhi 18:6a4db94011d3 14955 #define ETH_DMABMR_DA_Pos (1U)
sahilmgandhi 18:6a4db94011d3 14956 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 14957 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
sahilmgandhi 18:6a4db94011d3 14958 #define ETH_DMABMR_SR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14959 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 14960 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
sahilmgandhi 18:6a4db94011d3 14961
sahilmgandhi 18:6a4db94011d3 14962 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
sahilmgandhi 18:6a4db94011d3 14963 #define ETH_DMATPDR_TPD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14964 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14965 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
sahilmgandhi 18:6a4db94011d3 14966
sahilmgandhi 18:6a4db94011d3 14967 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
sahilmgandhi 18:6a4db94011d3 14968 #define ETH_DMARPDR_RPD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14969 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14970 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
sahilmgandhi 18:6a4db94011d3 14971
sahilmgandhi 18:6a4db94011d3 14972 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
sahilmgandhi 18:6a4db94011d3 14973 #define ETH_DMARDLAR_SRL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14974 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14975 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
sahilmgandhi 18:6a4db94011d3 14976
sahilmgandhi 18:6a4db94011d3 14977 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
sahilmgandhi 18:6a4db94011d3 14978 #define ETH_DMATDLAR_STL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 14979 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 14980 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
sahilmgandhi 18:6a4db94011d3 14981
sahilmgandhi 18:6a4db94011d3 14982 /* Bit definition for Ethernet DMA Status Register */
sahilmgandhi 18:6a4db94011d3 14983 #define ETH_DMASR_TSTS_Pos (29U)
sahilmgandhi 18:6a4db94011d3 14984 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 14985 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
sahilmgandhi 18:6a4db94011d3 14986 #define ETH_DMASR_PMTS_Pos (28U)
sahilmgandhi 18:6a4db94011d3 14987 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 14988 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
sahilmgandhi 18:6a4db94011d3 14989 #define ETH_DMASR_MMCS_Pos (27U)
sahilmgandhi 18:6a4db94011d3 14990 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 14991 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
sahilmgandhi 18:6a4db94011d3 14992 #define ETH_DMASR_EBS_Pos (23U)
sahilmgandhi 18:6a4db94011d3 14993 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
sahilmgandhi 18:6a4db94011d3 14994 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
sahilmgandhi 18:6a4db94011d3 14995 /* combination with EBS[2:0] for GetFlagStatus function */
sahilmgandhi 18:6a4db94011d3 14996 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
sahilmgandhi 18:6a4db94011d3 14997 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 14998 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
sahilmgandhi 18:6a4db94011d3 14999 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
sahilmgandhi 18:6a4db94011d3 15000 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15001 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
sahilmgandhi 18:6a4db94011d3 15002 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
sahilmgandhi 18:6a4db94011d3 15003 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 15004 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
sahilmgandhi 18:6a4db94011d3 15005 #define ETH_DMASR_TPS_Pos (20U)
sahilmgandhi 18:6a4db94011d3 15006 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
sahilmgandhi 18:6a4db94011d3 15007 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
sahilmgandhi 18:6a4db94011d3 15008 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
sahilmgandhi 18:6a4db94011d3 15009 #define ETH_DMASR_TPS_Fetching_Pos (20U)
sahilmgandhi 18:6a4db94011d3 15010 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15011 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
sahilmgandhi 18:6a4db94011d3 15012 #define ETH_DMASR_TPS_Waiting_Pos (21U)
sahilmgandhi 18:6a4db94011d3 15013 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15014 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
sahilmgandhi 18:6a4db94011d3 15015 #define ETH_DMASR_TPS_Reading_Pos (20U)
sahilmgandhi 18:6a4db94011d3 15016 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 15017 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
sahilmgandhi 18:6a4db94011d3 15018 #define ETH_DMASR_TPS_Suspended_Pos (21U)
sahilmgandhi 18:6a4db94011d3 15019 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
sahilmgandhi 18:6a4db94011d3 15020 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
sahilmgandhi 18:6a4db94011d3 15021 #define ETH_DMASR_TPS_Closing_Pos (20U)
sahilmgandhi 18:6a4db94011d3 15022 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
sahilmgandhi 18:6a4db94011d3 15023 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
sahilmgandhi 18:6a4db94011d3 15024 #define ETH_DMASR_RPS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15025 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
sahilmgandhi 18:6a4db94011d3 15026 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
sahilmgandhi 18:6a4db94011d3 15027 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
sahilmgandhi 18:6a4db94011d3 15028 #define ETH_DMASR_RPS_Fetching_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15029 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15030 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
sahilmgandhi 18:6a4db94011d3 15031 #define ETH_DMASR_RPS_Waiting_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15032 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
sahilmgandhi 18:6a4db94011d3 15033 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
sahilmgandhi 18:6a4db94011d3 15034 #define ETH_DMASR_RPS_Suspended_Pos (19U)
sahilmgandhi 18:6a4db94011d3 15035 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15036 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
sahilmgandhi 18:6a4db94011d3 15037 #define ETH_DMASR_RPS_Closing_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15038 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
sahilmgandhi 18:6a4db94011d3 15039 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
sahilmgandhi 18:6a4db94011d3 15040 #define ETH_DMASR_RPS_Queuing_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15041 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
sahilmgandhi 18:6a4db94011d3 15042 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
sahilmgandhi 18:6a4db94011d3 15043 #define ETH_DMASR_NIS_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15044 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15045 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
sahilmgandhi 18:6a4db94011d3 15046 #define ETH_DMASR_AIS_Pos (15U)
sahilmgandhi 18:6a4db94011d3 15047 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 15048 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
sahilmgandhi 18:6a4db94011d3 15049 #define ETH_DMASR_ERS_Pos (14U)
sahilmgandhi 18:6a4db94011d3 15050 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 15051 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
sahilmgandhi 18:6a4db94011d3 15052 #define ETH_DMASR_FBES_Pos (13U)
sahilmgandhi 18:6a4db94011d3 15053 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 15054 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
sahilmgandhi 18:6a4db94011d3 15055 #define ETH_DMASR_ETS_Pos (10U)
sahilmgandhi 18:6a4db94011d3 15056 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15057 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
sahilmgandhi 18:6a4db94011d3 15058 #define ETH_DMASR_RWTS_Pos (9U)
sahilmgandhi 18:6a4db94011d3 15059 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15060 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
sahilmgandhi 18:6a4db94011d3 15061 #define ETH_DMASR_RPSS_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15062 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15063 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
sahilmgandhi 18:6a4db94011d3 15064 #define ETH_DMASR_RBUS_Pos (7U)
sahilmgandhi 18:6a4db94011d3 15065 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15066 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
sahilmgandhi 18:6a4db94011d3 15067 #define ETH_DMASR_RS_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15068 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15069 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
sahilmgandhi 18:6a4db94011d3 15070 #define ETH_DMASR_TUS_Pos (5U)
sahilmgandhi 18:6a4db94011d3 15071 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15072 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
sahilmgandhi 18:6a4db94011d3 15073 #define ETH_DMASR_ROS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15074 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15075 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
sahilmgandhi 18:6a4db94011d3 15076 #define ETH_DMASR_TJTS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15077 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15078 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
sahilmgandhi 18:6a4db94011d3 15079 #define ETH_DMASR_TBUS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15080 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15081 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
sahilmgandhi 18:6a4db94011d3 15082 #define ETH_DMASR_TPSS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15083 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15084 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
sahilmgandhi 18:6a4db94011d3 15085 #define ETH_DMASR_TS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15086 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15087 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
sahilmgandhi 18:6a4db94011d3 15088
sahilmgandhi 18:6a4db94011d3 15089 /* Bit definition for Ethernet DMA Operation Mode Register */
sahilmgandhi 18:6a4db94011d3 15090 #define ETH_DMAOMR_DTCEFD_Pos (26U)
sahilmgandhi 18:6a4db94011d3 15091 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 15092 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
sahilmgandhi 18:6a4db94011d3 15093 #define ETH_DMAOMR_RSF_Pos (25U)
sahilmgandhi 18:6a4db94011d3 15094 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 15095 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
sahilmgandhi 18:6a4db94011d3 15096 #define ETH_DMAOMR_DFRF_Pos (24U)
sahilmgandhi 18:6a4db94011d3 15097 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15098 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
sahilmgandhi 18:6a4db94011d3 15099 #define ETH_DMAOMR_TSF_Pos (21U)
sahilmgandhi 18:6a4db94011d3 15100 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15101 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
sahilmgandhi 18:6a4db94011d3 15102 #define ETH_DMAOMR_FTF_Pos (20U)
sahilmgandhi 18:6a4db94011d3 15103 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15104 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
sahilmgandhi 18:6a4db94011d3 15105 #define ETH_DMAOMR_TTC_Pos (14U)
sahilmgandhi 18:6a4db94011d3 15106 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
sahilmgandhi 18:6a4db94011d3 15107 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
sahilmgandhi 18:6a4db94011d3 15108 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
sahilmgandhi 18:6a4db94011d3 15109 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
sahilmgandhi 18:6a4db94011d3 15110 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
sahilmgandhi 18:6a4db94011d3 15111 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
sahilmgandhi 18:6a4db94011d3 15112 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
sahilmgandhi 18:6a4db94011d3 15113 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
sahilmgandhi 18:6a4db94011d3 15114 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
sahilmgandhi 18:6a4db94011d3 15115 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
sahilmgandhi 18:6a4db94011d3 15116 #define ETH_DMAOMR_ST_Pos (13U)
sahilmgandhi 18:6a4db94011d3 15117 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 15118 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
sahilmgandhi 18:6a4db94011d3 15119 #define ETH_DMAOMR_FEF_Pos (7U)
sahilmgandhi 18:6a4db94011d3 15120 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15121 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
sahilmgandhi 18:6a4db94011d3 15122 #define ETH_DMAOMR_FUGF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15123 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15124 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
sahilmgandhi 18:6a4db94011d3 15125 #define ETH_DMAOMR_RTC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15126 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
sahilmgandhi 18:6a4db94011d3 15127 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
sahilmgandhi 18:6a4db94011d3 15128 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
sahilmgandhi 18:6a4db94011d3 15129 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
sahilmgandhi 18:6a4db94011d3 15130 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
sahilmgandhi 18:6a4db94011d3 15131 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
sahilmgandhi 18:6a4db94011d3 15132 #define ETH_DMAOMR_OSF_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15133 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15134 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
sahilmgandhi 18:6a4db94011d3 15135 #define ETH_DMAOMR_SR_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15136 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15137 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
sahilmgandhi 18:6a4db94011d3 15138
sahilmgandhi 18:6a4db94011d3 15139 /* Bit definition for Ethernet DMA Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 15140 #define ETH_DMAIER_NISE_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15141 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15142 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
sahilmgandhi 18:6a4db94011d3 15143 #define ETH_DMAIER_AISE_Pos (15U)
sahilmgandhi 18:6a4db94011d3 15144 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 15145 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
sahilmgandhi 18:6a4db94011d3 15146 #define ETH_DMAIER_ERIE_Pos (14U)
sahilmgandhi 18:6a4db94011d3 15147 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 15148 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
sahilmgandhi 18:6a4db94011d3 15149 #define ETH_DMAIER_FBEIE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 15150 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 15151 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
sahilmgandhi 18:6a4db94011d3 15152 #define ETH_DMAIER_ETIE_Pos (10U)
sahilmgandhi 18:6a4db94011d3 15153 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15154 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
sahilmgandhi 18:6a4db94011d3 15155 #define ETH_DMAIER_RWTIE_Pos (9U)
sahilmgandhi 18:6a4db94011d3 15156 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15157 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
sahilmgandhi 18:6a4db94011d3 15158 #define ETH_DMAIER_RPSIE_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15159 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15160 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
sahilmgandhi 18:6a4db94011d3 15161 #define ETH_DMAIER_RBUIE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 15162 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15163 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
sahilmgandhi 18:6a4db94011d3 15164 #define ETH_DMAIER_RIE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15165 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15166 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
sahilmgandhi 18:6a4db94011d3 15167 #define ETH_DMAIER_TUIE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 15168 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15169 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
sahilmgandhi 18:6a4db94011d3 15170 #define ETH_DMAIER_ROIE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15171 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15172 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
sahilmgandhi 18:6a4db94011d3 15173 #define ETH_DMAIER_TJTIE_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15174 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15175 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
sahilmgandhi 18:6a4db94011d3 15176 #define ETH_DMAIER_TBUIE_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15177 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15178 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
sahilmgandhi 18:6a4db94011d3 15179 #define ETH_DMAIER_TPSIE_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15180 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15181 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
sahilmgandhi 18:6a4db94011d3 15182 #define ETH_DMAIER_TIE_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15183 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15184 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
sahilmgandhi 18:6a4db94011d3 15185
sahilmgandhi 18:6a4db94011d3 15186 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
sahilmgandhi 18:6a4db94011d3 15187 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
sahilmgandhi 18:6a4db94011d3 15188 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 15189 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
sahilmgandhi 18:6a4db94011d3 15190 #define ETH_DMAMFBOCR_MFA_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15191 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
sahilmgandhi 18:6a4db94011d3 15192 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
sahilmgandhi 18:6a4db94011d3 15193 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15194 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15195 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
sahilmgandhi 18:6a4db94011d3 15196 #define ETH_DMAMFBOCR_MFC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15197 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15198 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
sahilmgandhi 18:6a4db94011d3 15199
sahilmgandhi 18:6a4db94011d3 15200 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
sahilmgandhi 18:6a4db94011d3 15201 #define ETH_DMACHTDR_HTDAP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15202 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 15203 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
sahilmgandhi 18:6a4db94011d3 15204
sahilmgandhi 18:6a4db94011d3 15205 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
sahilmgandhi 18:6a4db94011d3 15206 #define ETH_DMACHRDR_HRDAP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15207 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 15208 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
sahilmgandhi 18:6a4db94011d3 15209
sahilmgandhi 18:6a4db94011d3 15210 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
sahilmgandhi 18:6a4db94011d3 15211 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15212 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 15213 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
sahilmgandhi 18:6a4db94011d3 15214
sahilmgandhi 18:6a4db94011d3 15215 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
sahilmgandhi 18:6a4db94011d3 15216 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15217 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 15218 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
sahilmgandhi 18:6a4db94011d3 15219
sahilmgandhi 18:6a4db94011d3 15220 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 15221 /* */
sahilmgandhi 18:6a4db94011d3 15222 /* USB_OTG */
sahilmgandhi 18:6a4db94011d3 15223 /* */
sahilmgandhi 18:6a4db94011d3 15224 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 15225 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
sahilmgandhi 18:6a4db94011d3 15226 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15227 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15228 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
sahilmgandhi 18:6a4db94011d3 15229 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15230 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15231 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
sahilmgandhi 18:6a4db94011d3 15232 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15233 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15234 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
sahilmgandhi 18:6a4db94011d3 15235 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
sahilmgandhi 18:6a4db94011d3 15236 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15237 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
sahilmgandhi 18:6a4db94011d3 15238 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
sahilmgandhi 18:6a4db94011d3 15239 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15240 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
sahilmgandhi 18:6a4db94011d3 15241 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
sahilmgandhi 18:6a4db94011d3 15242 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 15243 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
sahilmgandhi 18:6a4db94011d3 15244 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15245 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15246 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
sahilmgandhi 18:6a4db94011d3 15247 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15248 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15249 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
sahilmgandhi 18:6a4db94011d3 15250 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
sahilmgandhi 18:6a4db94011d3 15251 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15252 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
sahilmgandhi 18:6a4db94011d3 15253 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
sahilmgandhi 18:6a4db94011d3 15254 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15255 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
sahilmgandhi 18:6a4db94011d3 15256
sahilmgandhi 18:6a4db94011d3 15257 /******************** Bit definition forUSB_OTG_HCFG register ********************/
sahilmgandhi 18:6a4db94011d3 15258
sahilmgandhi 18:6a4db94011d3 15259 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15260 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 15261 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
sahilmgandhi 18:6a4db94011d3 15262 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15263 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15264 #define USB_OTG_HCFG_FSLSS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15265 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15266 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
sahilmgandhi 18:6a4db94011d3 15267
sahilmgandhi 18:6a4db94011d3 15268 /******************** Bit definition for USB_OTG_DCFG register ********************/
sahilmgandhi 18:6a4db94011d3 15269
sahilmgandhi 18:6a4db94011d3 15270 #define USB_OTG_DCFG_DSPD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15271 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
sahilmgandhi 18:6a4db94011d3 15272 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
sahilmgandhi 18:6a4db94011d3 15273 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15274 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15275 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15276 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15277 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
sahilmgandhi 18:6a4db94011d3 15278
sahilmgandhi 18:6a4db94011d3 15279 #define USB_OTG_DCFG_DAD_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15280 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
sahilmgandhi 18:6a4db94011d3 15281 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
sahilmgandhi 18:6a4db94011d3 15282 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15283 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15284 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15285 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15286 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15287 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15288 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15289
sahilmgandhi 18:6a4db94011d3 15290 #define USB_OTG_DCFG_PFIVL_Pos (11U)
sahilmgandhi 18:6a4db94011d3 15291 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
sahilmgandhi 18:6a4db94011d3 15292 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
sahilmgandhi 18:6a4db94011d3 15293 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 15294 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 15295
sahilmgandhi 18:6a4db94011d3 15296 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
sahilmgandhi 18:6a4db94011d3 15297 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
sahilmgandhi 18:6a4db94011d3 15298 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
sahilmgandhi 18:6a4db94011d3 15299 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15300 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 15301
sahilmgandhi 18:6a4db94011d3 15302 /******************** Bit definition for USB_OTG_PCGCR register ********************/
sahilmgandhi 18:6a4db94011d3 15303 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15304 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15305 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
sahilmgandhi 18:6a4db94011d3 15306 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15307 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15308 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
sahilmgandhi 18:6a4db94011d3 15309 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15310 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15311 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
sahilmgandhi 18:6a4db94011d3 15312
sahilmgandhi 18:6a4db94011d3 15313 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
sahilmgandhi 18:6a4db94011d3 15314 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15315 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15316 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
sahilmgandhi 18:6a4db94011d3 15317 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15318 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15319 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
sahilmgandhi 18:6a4db94011d3 15320 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
sahilmgandhi 18:6a4db94011d3 15321 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15322 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
sahilmgandhi 18:6a4db94011d3 15323 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15324 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15325 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
sahilmgandhi 18:6a4db94011d3 15326 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
sahilmgandhi 18:6a4db94011d3 15327 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15328 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
sahilmgandhi 18:6a4db94011d3 15329 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
sahilmgandhi 18:6a4db94011d3 15330 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15331 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
sahilmgandhi 18:6a4db94011d3 15332
sahilmgandhi 18:6a4db94011d3 15333 /******************** Bit definition for USB_OTG_DCTL register ********************/
sahilmgandhi 18:6a4db94011d3 15334 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15335 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15336 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
sahilmgandhi 18:6a4db94011d3 15337 #define USB_OTG_DCTL_SDIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15338 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15339 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
sahilmgandhi 18:6a4db94011d3 15340 #define USB_OTG_DCTL_GINSTS_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15341 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15342 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
sahilmgandhi 18:6a4db94011d3 15343 #define USB_OTG_DCTL_GONSTS_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15344 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15345 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
sahilmgandhi 18:6a4db94011d3 15346
sahilmgandhi 18:6a4db94011d3 15347 #define USB_OTG_DCTL_TCTL_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15348 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
sahilmgandhi 18:6a4db94011d3 15349 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
sahilmgandhi 18:6a4db94011d3 15350 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15351 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15352 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15353 #define USB_OTG_DCTL_SGINAK_Pos (7U)
sahilmgandhi 18:6a4db94011d3 15354 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15355 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
sahilmgandhi 18:6a4db94011d3 15356 #define USB_OTG_DCTL_CGINAK_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15357 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15358 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
sahilmgandhi 18:6a4db94011d3 15359 #define USB_OTG_DCTL_SGONAK_Pos (9U)
sahilmgandhi 18:6a4db94011d3 15360 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15361 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
sahilmgandhi 18:6a4db94011d3 15362 #define USB_OTG_DCTL_CGONAK_Pos (10U)
sahilmgandhi 18:6a4db94011d3 15363 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15364 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
sahilmgandhi 18:6a4db94011d3 15365 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
sahilmgandhi 18:6a4db94011d3 15366 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 15367 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
sahilmgandhi 18:6a4db94011d3 15368
sahilmgandhi 18:6a4db94011d3 15369 /******************** Bit definition for USB_OTG_HFIR register ********************/
sahilmgandhi 18:6a4db94011d3 15370 #define USB_OTG_HFIR_FRIVL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15371 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15372 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
sahilmgandhi 18:6a4db94011d3 15373
sahilmgandhi 18:6a4db94011d3 15374 /******************** Bit definition for USB_OTG_HFNUM register ********************/
sahilmgandhi 18:6a4db94011d3 15375 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15376 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15377 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 15378 #define USB_OTG_HFNUM_FTREM_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15379 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 15380 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
sahilmgandhi 18:6a4db94011d3 15381
sahilmgandhi 18:6a4db94011d3 15382 /******************** Bit definition for USB_OTG_DSTS register ********************/
sahilmgandhi 18:6a4db94011d3 15383 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15384 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15385 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
sahilmgandhi 18:6a4db94011d3 15386
sahilmgandhi 18:6a4db94011d3 15387 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15388 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
sahilmgandhi 18:6a4db94011d3 15389 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
sahilmgandhi 18:6a4db94011d3 15390 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15391 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15392 #define USB_OTG_DSTS_EERR_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15393 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15394 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
sahilmgandhi 18:6a4db94011d3 15395 #define USB_OTG_DSTS_FNSOF_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15396 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
sahilmgandhi 18:6a4db94011d3 15397 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
sahilmgandhi 18:6a4db94011d3 15398
sahilmgandhi 18:6a4db94011d3 15399 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
sahilmgandhi 18:6a4db94011d3 15400 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15401 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15402 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
sahilmgandhi 18:6a4db94011d3 15403 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15404 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
sahilmgandhi 18:6a4db94011d3 15405 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
sahilmgandhi 18:6a4db94011d3 15406 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15407 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15408 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15409 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15410 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
sahilmgandhi 18:6a4db94011d3 15411 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15412 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
sahilmgandhi 18:6a4db94011d3 15413 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
sahilmgandhi 18:6a4db94011d3 15414 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15415 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
sahilmgandhi 18:6a4db94011d3 15416 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15417 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15418 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
sahilmgandhi 18:6a4db94011d3 15419
sahilmgandhi 18:6a4db94011d3 15420 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
sahilmgandhi 18:6a4db94011d3 15421
sahilmgandhi 18:6a4db94011d3 15422 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15423 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
sahilmgandhi 18:6a4db94011d3 15424 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
sahilmgandhi 18:6a4db94011d3 15425 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15426 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15427 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15428 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15429 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15430 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
sahilmgandhi 18:6a4db94011d3 15431 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15432 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15433 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
sahilmgandhi 18:6a4db94011d3 15434 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
sahilmgandhi 18:6a4db94011d3 15435 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15436 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
sahilmgandhi 18:6a4db94011d3 15437 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
sahilmgandhi 18:6a4db94011d3 15438 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
sahilmgandhi 18:6a4db94011d3 15439 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
sahilmgandhi 18:6a4db94011d3 15440 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15441 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 15442 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 15443 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 15444 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
sahilmgandhi 18:6a4db94011d3 15445 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 15446 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
sahilmgandhi 18:6a4db94011d3 15447 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15448 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15449 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
sahilmgandhi 18:6a4db94011d3 15450 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
sahilmgandhi 18:6a4db94011d3 15451 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15452 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
sahilmgandhi 18:6a4db94011d3 15453 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
sahilmgandhi 18:6a4db94011d3 15454 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15455 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
sahilmgandhi 18:6a4db94011d3 15456 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
sahilmgandhi 18:6a4db94011d3 15457 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15458 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
sahilmgandhi 18:6a4db94011d3 15459 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
sahilmgandhi 18:6a4db94011d3 15460 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15461 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
sahilmgandhi 18:6a4db94011d3 15462 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
sahilmgandhi 18:6a4db94011d3 15463 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 15464 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
sahilmgandhi 18:6a4db94011d3 15465 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
sahilmgandhi 18:6a4db94011d3 15466 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 15467 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
sahilmgandhi 18:6a4db94011d3 15468 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
sahilmgandhi 18:6a4db94011d3 15469 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15470 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
sahilmgandhi 18:6a4db94011d3 15471 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
sahilmgandhi 18:6a4db94011d3 15472 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 15473 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
sahilmgandhi 18:6a4db94011d3 15474 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
sahilmgandhi 18:6a4db94011d3 15475 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 15476 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
sahilmgandhi 18:6a4db94011d3 15477 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
sahilmgandhi 18:6a4db94011d3 15478 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 15479 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
sahilmgandhi 18:6a4db94011d3 15480 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
sahilmgandhi 18:6a4db94011d3 15481 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 15482 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
sahilmgandhi 18:6a4db94011d3 15483
sahilmgandhi 18:6a4db94011d3 15484 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
sahilmgandhi 18:6a4db94011d3 15485 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15486 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15487 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
sahilmgandhi 18:6a4db94011d3 15488 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15489 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15490 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
sahilmgandhi 18:6a4db94011d3 15491 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15492 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15493 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
sahilmgandhi 18:6a4db94011d3 15494 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15495 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15496 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
sahilmgandhi 18:6a4db94011d3 15497 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
sahilmgandhi 18:6a4db94011d3 15498 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15499 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
sahilmgandhi 18:6a4db94011d3 15500
sahilmgandhi 18:6a4db94011d3 15501
sahilmgandhi 18:6a4db94011d3 15502 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15503 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
sahilmgandhi 18:6a4db94011d3 15504 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
sahilmgandhi 18:6a4db94011d3 15505 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15506 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15507 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15508 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15509 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15510 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
sahilmgandhi 18:6a4db94011d3 15511 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 15512 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
sahilmgandhi 18:6a4db94011d3 15513 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
sahilmgandhi 18:6a4db94011d3 15514 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 15515 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
sahilmgandhi 18:6a4db94011d3 15516
sahilmgandhi 18:6a4db94011d3 15517 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 15518 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15519 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15520 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 15521 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15522 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15523 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 15524 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15525 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15526 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
sahilmgandhi 18:6a4db94011d3 15527 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15528 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15529 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 15530 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
sahilmgandhi 18:6a4db94011d3 15531 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15532 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 15533 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15534 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15535 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 15536 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15537 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15538 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
sahilmgandhi 18:6a4db94011d3 15539 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 15540 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15541 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 15542
sahilmgandhi 18:6a4db94011d3 15543 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
sahilmgandhi 18:6a4db94011d3 15544 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15545 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15546 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
sahilmgandhi 18:6a4db94011d3 15547 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15548 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 15549 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
sahilmgandhi 18:6a4db94011d3 15550 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15551 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15552 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15553 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15554 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15555 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15556 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 15557 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 15558
sahilmgandhi 18:6a4db94011d3 15559 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
sahilmgandhi 18:6a4db94011d3 15560 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
sahilmgandhi 18:6a4db94011d3 15561 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
sahilmgandhi 18:6a4db94011d3 15562 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15563 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 15564 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 15565 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 15566 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 15567 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 15568 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 15569 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 15570
sahilmgandhi 18:6a4db94011d3 15571 /******************** Bit definition for USB_OTG_HAINT register ********************/
sahilmgandhi 18:6a4db94011d3 15572 #define USB_OTG_HAINT_HAINT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15573 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15574 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
sahilmgandhi 18:6a4db94011d3 15575
sahilmgandhi 18:6a4db94011d3 15576 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 15577 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15578 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15579 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 15580 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15581 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15582 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 15583 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15584 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15585 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
sahilmgandhi 18:6a4db94011d3 15586 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15587 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15588 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
sahilmgandhi 18:6a4db94011d3 15589 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15590 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15591 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
sahilmgandhi 18:6a4db94011d3 15592 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 15593 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15594 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
sahilmgandhi 18:6a4db94011d3 15595 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 15596 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15597 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 15598
sahilmgandhi 18:6a4db94011d3 15599 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
sahilmgandhi 18:6a4db94011d3 15600 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15601 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15602 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
sahilmgandhi 18:6a4db94011d3 15603 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15604 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15605 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
sahilmgandhi 18:6a4db94011d3 15606 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15607 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15608 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
sahilmgandhi 18:6a4db94011d3 15609 #define USB_OTG_GINTSTS_SOF_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15610 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15611 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
sahilmgandhi 18:6a4db94011d3 15612 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15613 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15614 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
sahilmgandhi 18:6a4db94011d3 15615 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
sahilmgandhi 18:6a4db94011d3 15616 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15617 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
sahilmgandhi 18:6a4db94011d3 15618 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15619 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15620 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
sahilmgandhi 18:6a4db94011d3 15621 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
sahilmgandhi 18:6a4db94011d3 15622 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15623 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
sahilmgandhi 18:6a4db94011d3 15624 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
sahilmgandhi 18:6a4db94011d3 15625 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15626 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
sahilmgandhi 18:6a4db94011d3 15627 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
sahilmgandhi 18:6a4db94011d3 15628 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 15629 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
sahilmgandhi 18:6a4db94011d3 15630 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 15631 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 15632 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
sahilmgandhi 18:6a4db94011d3 15633 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
sahilmgandhi 18:6a4db94011d3 15634 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 15635 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
sahilmgandhi 18:6a4db94011d3 15636 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
sahilmgandhi 18:6a4db94011d3 15637 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 15638 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
sahilmgandhi 18:6a4db94011d3 15639 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
sahilmgandhi 18:6a4db94011d3 15640 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 15641 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
sahilmgandhi 18:6a4db94011d3 15642 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
sahilmgandhi 18:6a4db94011d3 15643 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15644 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
sahilmgandhi 18:6a4db94011d3 15645 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
sahilmgandhi 18:6a4db94011d3 15646 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15647 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
sahilmgandhi 18:6a4db94011d3 15648 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
sahilmgandhi 18:6a4db94011d3 15649 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15650 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
sahilmgandhi 18:6a4db94011d3 15651 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
sahilmgandhi 18:6a4db94011d3 15652 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15653 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
sahilmgandhi 18:6a4db94011d3 15654 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
sahilmgandhi 18:6a4db94011d3 15655 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 15656 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
sahilmgandhi 18:6a4db94011d3 15657 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
sahilmgandhi 18:6a4db94011d3 15658 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15659 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
sahilmgandhi 18:6a4db94011d3 15660 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
sahilmgandhi 18:6a4db94011d3 15661 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 15662 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
sahilmgandhi 18:6a4db94011d3 15663 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
sahilmgandhi 18:6a4db94011d3 15664 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 15665 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
sahilmgandhi 18:6a4db94011d3 15666 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
sahilmgandhi 18:6a4db94011d3 15667 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 15668 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
sahilmgandhi 18:6a4db94011d3 15669 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
sahilmgandhi 18:6a4db94011d3 15670 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 15671 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
sahilmgandhi 18:6a4db94011d3 15672 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
sahilmgandhi 18:6a4db94011d3 15673 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 15674 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
sahilmgandhi 18:6a4db94011d3 15675 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
sahilmgandhi 18:6a4db94011d3 15676 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 15677 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
sahilmgandhi 18:6a4db94011d3 15678
sahilmgandhi 18:6a4db94011d3 15679 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 15680 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15681 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15682 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
sahilmgandhi 18:6a4db94011d3 15683 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15684 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15685 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
sahilmgandhi 18:6a4db94011d3 15686 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 15687 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15688 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
sahilmgandhi 18:6a4db94011d3 15689 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15690 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15691 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
sahilmgandhi 18:6a4db94011d3 15692 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
sahilmgandhi 18:6a4db94011d3 15693 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15694 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 15695 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
sahilmgandhi 18:6a4db94011d3 15696 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15697 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
sahilmgandhi 18:6a4db94011d3 15698 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
sahilmgandhi 18:6a4db94011d3 15699 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15700 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
sahilmgandhi 18:6a4db94011d3 15701 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
sahilmgandhi 18:6a4db94011d3 15702 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15703 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
sahilmgandhi 18:6a4db94011d3 15704 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
sahilmgandhi 18:6a4db94011d3 15705 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 15706 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
sahilmgandhi 18:6a4db94011d3 15707 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
sahilmgandhi 18:6a4db94011d3 15708 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 15709 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
sahilmgandhi 18:6a4db94011d3 15710 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
sahilmgandhi 18:6a4db94011d3 15711 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 15712 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
sahilmgandhi 18:6a4db94011d3 15713 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
sahilmgandhi 18:6a4db94011d3 15714 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 15715 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
sahilmgandhi 18:6a4db94011d3 15716 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
sahilmgandhi 18:6a4db94011d3 15717 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 15718 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
sahilmgandhi 18:6a4db94011d3 15719 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15720 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15721 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
sahilmgandhi 18:6a4db94011d3 15722 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
sahilmgandhi 18:6a4db94011d3 15723 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15724 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
sahilmgandhi 18:6a4db94011d3 15725 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
sahilmgandhi 18:6a4db94011d3 15726 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15727 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
sahilmgandhi 18:6a4db94011d3 15728 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
sahilmgandhi 18:6a4db94011d3 15729 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15730 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
sahilmgandhi 18:6a4db94011d3 15731 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
sahilmgandhi 18:6a4db94011d3 15732 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15733 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
sahilmgandhi 18:6a4db94011d3 15734 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 15735 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 15736 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
sahilmgandhi 18:6a4db94011d3 15737 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
sahilmgandhi 18:6a4db94011d3 15738 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15739 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
sahilmgandhi 18:6a4db94011d3 15740 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
sahilmgandhi 18:6a4db94011d3 15741 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 15742 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
sahilmgandhi 18:6a4db94011d3 15743 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
sahilmgandhi 18:6a4db94011d3 15744 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 15745 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 15746 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
sahilmgandhi 18:6a4db94011d3 15747 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 15748 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
sahilmgandhi 18:6a4db94011d3 15749 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
sahilmgandhi 18:6a4db94011d3 15750 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 15751 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 15752 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
sahilmgandhi 18:6a4db94011d3 15753 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 15754 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 15755 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
sahilmgandhi 18:6a4db94011d3 15756 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 15757 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
sahilmgandhi 18:6a4db94011d3 15758
sahilmgandhi 18:6a4db94011d3 15759 /******************** Bit definition for USB_OTG_DAINT register ********************/
sahilmgandhi 18:6a4db94011d3 15760 #define USB_OTG_DAINT_IEPINT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15761 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15762 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
sahilmgandhi 18:6a4db94011d3 15763 #define USB_OTG_DAINT_OEPINT_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15764 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 15765 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
sahilmgandhi 18:6a4db94011d3 15766
sahilmgandhi 18:6a4db94011d3 15767 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 15768 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15769 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15770 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
sahilmgandhi 18:6a4db94011d3 15771
sahilmgandhi 18:6a4db94011d3 15772 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
sahilmgandhi 18:6a4db94011d3 15773 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15774 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 15775 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 15776 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15777 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
sahilmgandhi 18:6a4db94011d3 15778 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 15779 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
sahilmgandhi 18:6a4db94011d3 15780 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
sahilmgandhi 18:6a4db94011d3 15781 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 15782 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15783 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
sahilmgandhi 18:6a4db94011d3 15784 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 15785
sahilmgandhi 18:6a4db94011d3 15786 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 15787 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15788 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15789 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 15790 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15791 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 15792 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 15793
sahilmgandhi 18:6a4db94011d3 15794 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 15795
sahilmgandhi 18:6a4db94011d3 15796 #define USB_OTG_CHNUM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15797 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 15798 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
sahilmgandhi 18:6a4db94011d3 15799 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15800 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15801 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15802 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15803 #define USB_OTG_BCNT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15804 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
sahilmgandhi 18:6a4db94011d3 15805 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
sahilmgandhi 18:6a4db94011d3 15806
sahilmgandhi 18:6a4db94011d3 15807 #define USB_OTG_DPID_Pos (15U)
sahilmgandhi 18:6a4db94011d3 15808 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
sahilmgandhi 18:6a4db94011d3 15809 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 15810 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 15811 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15812
sahilmgandhi 18:6a4db94011d3 15813 #define USB_OTG_PKTSTS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15814 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
sahilmgandhi 18:6a4db94011d3 15815 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
sahilmgandhi 18:6a4db94011d3 15816 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15817 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15818 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15819 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15820
sahilmgandhi 18:6a4db94011d3 15821 #define USB_OTG_EPNUM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15822 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 15823 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 15824 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15825 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15826 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15827 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15828
sahilmgandhi 18:6a4db94011d3 15829 #define USB_OTG_FRMNUM_Pos (21U)
sahilmgandhi 18:6a4db94011d3 15830 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
sahilmgandhi 18:6a4db94011d3 15831 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 15832 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15833 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 15834 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 15835 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15836
sahilmgandhi 18:6a4db94011d3 15837 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 15838
sahilmgandhi 18:6a4db94011d3 15839 #define USB_OTG_CHNUM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15840 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 15841 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
sahilmgandhi 18:6a4db94011d3 15842 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15843 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15844 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15845 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15846 #define USB_OTG_BCNT_Pos (4U)
sahilmgandhi 18:6a4db94011d3 15847 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
sahilmgandhi 18:6a4db94011d3 15848 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
sahilmgandhi 18:6a4db94011d3 15849
sahilmgandhi 18:6a4db94011d3 15850 #define USB_OTG_DPID_Pos (15U)
sahilmgandhi 18:6a4db94011d3 15851 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
sahilmgandhi 18:6a4db94011d3 15852 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 15853 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 15854 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15855
sahilmgandhi 18:6a4db94011d3 15856 #define USB_OTG_PKTSTS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15857 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
sahilmgandhi 18:6a4db94011d3 15858 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
sahilmgandhi 18:6a4db94011d3 15859 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15860 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15861 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15862 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15863
sahilmgandhi 18:6a4db94011d3 15864 #define USB_OTG_EPNUM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15865 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
sahilmgandhi 18:6a4db94011d3 15866 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 15867 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15868 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15869 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15870 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15871
sahilmgandhi 18:6a4db94011d3 15872 #define USB_OTG_FRMNUM_Pos (21U)
sahilmgandhi 18:6a4db94011d3 15873 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
sahilmgandhi 18:6a4db94011d3 15874 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
sahilmgandhi 18:6a4db94011d3 15875 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15876 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 15877 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 15878 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15879
sahilmgandhi 18:6a4db94011d3 15880 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 15881 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15882 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15883 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
sahilmgandhi 18:6a4db94011d3 15884
sahilmgandhi 18:6a4db94011d3 15885 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
sahilmgandhi 18:6a4db94011d3 15886 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15887 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15888 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
sahilmgandhi 18:6a4db94011d3 15889
sahilmgandhi 18:6a4db94011d3 15890 /******************** Bit definition for OTG register ********************/
sahilmgandhi 18:6a4db94011d3 15891 #define USB_OTG_NPTXFSA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15892 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15893 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 15894 #define USB_OTG_NPTXFD_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15895 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 15896 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 15897 #define USB_OTG_TX0FSA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15898 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15899 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 15900 #define USB_OTG_TX0FD_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15901 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 15902 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 15903
sahilmgandhi 18:6a4db94011d3 15904 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
sahilmgandhi 18:6a4db94011d3 15905 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15906 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
sahilmgandhi 18:6a4db94011d3 15907 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
sahilmgandhi 18:6a4db94011d3 15908
sahilmgandhi 18:6a4db94011d3 15909 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
sahilmgandhi 18:6a4db94011d3 15910 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15911 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15912 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
sahilmgandhi 18:6a4db94011d3 15913
sahilmgandhi 18:6a4db94011d3 15914 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15915 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
sahilmgandhi 18:6a4db94011d3 15916 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
sahilmgandhi 18:6a4db94011d3 15917 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15918 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15919 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15920 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15921 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15922 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15923 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 15924 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 15925
sahilmgandhi 18:6a4db94011d3 15926 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
sahilmgandhi 18:6a4db94011d3 15927 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
sahilmgandhi 18:6a4db94011d3 15928 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
sahilmgandhi 18:6a4db94011d3 15929 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15930 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 15931 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 15932 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 15933 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 15934 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 15935 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 15936
sahilmgandhi 18:6a4db94011d3 15937 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
sahilmgandhi 18:6a4db94011d3 15938 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15939 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 15940 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
sahilmgandhi 18:6a4db94011d3 15941 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15942 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15943 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
sahilmgandhi 18:6a4db94011d3 15944
sahilmgandhi 18:6a4db94011d3 15945 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
sahilmgandhi 18:6a4db94011d3 15946 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
sahilmgandhi 18:6a4db94011d3 15947 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
sahilmgandhi 18:6a4db94011d3 15948 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 15949 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 15950 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 15951 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 15952 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 15953 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 15954 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 15955 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 15956 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 15957 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15958 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15959 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
sahilmgandhi 18:6a4db94011d3 15960
sahilmgandhi 18:6a4db94011d3 15961 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15962 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
sahilmgandhi 18:6a4db94011d3 15963 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
sahilmgandhi 18:6a4db94011d3 15964 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15965 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15966 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 15967 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 15968 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 15969 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 15970 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 15971 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 15972 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 15973 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
sahilmgandhi 18:6a4db94011d3 15974 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 15975 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
sahilmgandhi 18:6a4db94011d3 15976
sahilmgandhi 18:6a4db94011d3 15977 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
sahilmgandhi 18:6a4db94011d3 15978 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 15979 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 15980 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
sahilmgandhi 18:6a4db94011d3 15981
sahilmgandhi 18:6a4db94011d3 15982 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
sahilmgandhi 18:6a4db94011d3 15983 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
sahilmgandhi 18:6a4db94011d3 15984 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 15985 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
sahilmgandhi 18:6a4db94011d3 15986 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15987 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15988 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
sahilmgandhi 18:6a4db94011d3 15989
sahilmgandhi 18:6a4db94011d3 15990 /******************** Bit definition for USB_OTG_GCCFG register ********************/
sahilmgandhi 18:6a4db94011d3 15991 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
sahilmgandhi 18:6a4db94011d3 15992 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 15993 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
sahilmgandhi 18:6a4db94011d3 15994 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
sahilmgandhi 18:6a4db94011d3 15995 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 15996 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
sahilmgandhi 18:6a4db94011d3 15997 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
sahilmgandhi 18:6a4db94011d3 15998 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 15999 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
sahilmgandhi 18:6a4db94011d3 16000 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
sahilmgandhi 18:6a4db94011d3 16001 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 16002 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
sahilmgandhi 18:6a4db94011d3 16003 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
sahilmgandhi 18:6a4db94011d3 16004 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 16005 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
sahilmgandhi 18:6a4db94011d3 16006 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
sahilmgandhi 18:6a4db94011d3 16007 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 16008 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
sahilmgandhi 18:6a4db94011d3 16009
sahilmgandhi 18:6a4db94011d3 16010 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 16011 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16012 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16013 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
sahilmgandhi 18:6a4db94011d3 16014 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
sahilmgandhi 18:6a4db94011d3 16015 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 16016 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
sahilmgandhi 18:6a4db94011d3 16017
sahilmgandhi 18:6a4db94011d3 16018 /******************** Bit definition for USB_OTG_CID register ********************/
sahilmgandhi 18:6a4db94011d3 16019 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16020 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 16021 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
sahilmgandhi 18:6a4db94011d3 16022
sahilmgandhi 18:6a4db94011d3 16023 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
sahilmgandhi 18:6a4db94011d3 16024 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16025 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16026 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 16027 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16028 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16029 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 16030 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 16031 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 16032 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
sahilmgandhi 18:6a4db94011d3 16033 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 16034 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16035 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 16036 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
sahilmgandhi 18:6a4db94011d3 16037 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 16038 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 16039 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
sahilmgandhi 18:6a4db94011d3 16040 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 16041 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 16042 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 16043 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 16044 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
sahilmgandhi 18:6a4db94011d3 16045 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 16046 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 16047 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 16048 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
sahilmgandhi 18:6a4db94011d3 16049 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 16050 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
sahilmgandhi 18:6a4db94011d3 16051
sahilmgandhi 18:6a4db94011d3 16052 /******************** Bit definition for USB_OTG_HPRT register ********************/
sahilmgandhi 18:6a4db94011d3 16053 #define USB_OTG_HPRT_PCSTS_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16054 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16055 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
sahilmgandhi 18:6a4db94011d3 16056 #define USB_OTG_HPRT_PCDET_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16057 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16058 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
sahilmgandhi 18:6a4db94011d3 16059 #define USB_OTG_HPRT_PENA_Pos (2U)
sahilmgandhi 18:6a4db94011d3 16060 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 16061 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
sahilmgandhi 18:6a4db94011d3 16062 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
sahilmgandhi 18:6a4db94011d3 16063 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 16064 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
sahilmgandhi 18:6a4db94011d3 16065 #define USB_OTG_HPRT_POCA_Pos (4U)
sahilmgandhi 18:6a4db94011d3 16066 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16067 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
sahilmgandhi 18:6a4db94011d3 16068 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
sahilmgandhi 18:6a4db94011d3 16069 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 16070 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
sahilmgandhi 18:6a4db94011d3 16071 #define USB_OTG_HPRT_PRES_Pos (6U)
sahilmgandhi 18:6a4db94011d3 16072 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 16073 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
sahilmgandhi 18:6a4db94011d3 16074 #define USB_OTG_HPRT_PSUSP_Pos (7U)
sahilmgandhi 18:6a4db94011d3 16075 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 16076 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
sahilmgandhi 18:6a4db94011d3 16077 #define USB_OTG_HPRT_PRST_Pos (8U)
sahilmgandhi 18:6a4db94011d3 16078 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 16079 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
sahilmgandhi 18:6a4db94011d3 16080
sahilmgandhi 18:6a4db94011d3 16081 #define USB_OTG_HPRT_PLSTS_Pos (10U)
sahilmgandhi 18:6a4db94011d3 16082 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
sahilmgandhi 18:6a4db94011d3 16083 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
sahilmgandhi 18:6a4db94011d3 16084 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 16085 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 16086 #define USB_OTG_HPRT_PPWR_Pos (12U)
sahilmgandhi 18:6a4db94011d3 16087 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 16088 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
sahilmgandhi 18:6a4db94011d3 16089
sahilmgandhi 18:6a4db94011d3 16090 #define USB_OTG_HPRT_PTCTL_Pos (13U)
sahilmgandhi 18:6a4db94011d3 16091 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
sahilmgandhi 18:6a4db94011d3 16092 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
sahilmgandhi 18:6a4db94011d3 16093 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 16094 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 16095 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 16096 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 16097
sahilmgandhi 18:6a4db94011d3 16098 #define USB_OTG_HPRT_PSPD_Pos (17U)
sahilmgandhi 18:6a4db94011d3 16099 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
sahilmgandhi 18:6a4db94011d3 16100 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
sahilmgandhi 18:6a4db94011d3 16101 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 16102 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 16103
sahilmgandhi 18:6a4db94011d3 16104 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
sahilmgandhi 18:6a4db94011d3 16105 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16106 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16107 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
sahilmgandhi 18:6a4db94011d3 16108 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16109 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16110 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
sahilmgandhi 18:6a4db94011d3 16111 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 16112 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 16113 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
sahilmgandhi 18:6a4db94011d3 16114 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 16115 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16116 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
sahilmgandhi 18:6a4db94011d3 16117 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
sahilmgandhi 18:6a4db94011d3 16118 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 16119 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
sahilmgandhi 18:6a4db94011d3 16120 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
sahilmgandhi 18:6a4db94011d3 16121 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 16122 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
sahilmgandhi 18:6a4db94011d3 16123 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 16124 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 16125 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
sahilmgandhi 18:6a4db94011d3 16126 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 16127 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 16128 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
sahilmgandhi 18:6a4db94011d3 16129 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
sahilmgandhi 18:6a4db94011d3 16130 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 16131 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
sahilmgandhi 18:6a4db94011d3 16132 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
sahilmgandhi 18:6a4db94011d3 16133 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 16134 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
sahilmgandhi 18:6a4db94011d3 16135 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
sahilmgandhi 18:6a4db94011d3 16136 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 16137 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
sahilmgandhi 18:6a4db94011d3 16138
sahilmgandhi 18:6a4db94011d3 16139 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 16140 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16141 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 16142 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
sahilmgandhi 18:6a4db94011d3 16143 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
sahilmgandhi 18:6a4db94011d3 16144 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 16145 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 16146
sahilmgandhi 18:6a4db94011d3 16147 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
sahilmgandhi 18:6a4db94011d3 16148 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16149 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
sahilmgandhi 18:6a4db94011d3 16150 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
sahilmgandhi 18:6a4db94011d3 16151 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 16152 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 16153 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
sahilmgandhi 18:6a4db94011d3 16154 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
sahilmgandhi 18:6a4db94011d3 16155 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 16156 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
sahilmgandhi 18:6a4db94011d3 16157 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 16158 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 16159 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
sahilmgandhi 18:6a4db94011d3 16160
sahilmgandhi 18:6a4db94011d3 16161 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
sahilmgandhi 18:6a4db94011d3 16162 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 16163 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 16164 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 16165 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 16166 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
sahilmgandhi 18:6a4db94011d3 16167 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 16168 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
sahilmgandhi 18:6a4db94011d3 16169
sahilmgandhi 18:6a4db94011d3 16170 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
sahilmgandhi 18:6a4db94011d3 16171 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
sahilmgandhi 18:6a4db94011d3 16172 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
sahilmgandhi 18:6a4db94011d3 16173 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 16174 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 16175 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 16176 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 16177 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
sahilmgandhi 18:6a4db94011d3 16178 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 16179 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
sahilmgandhi 18:6a4db94011d3 16180 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
sahilmgandhi 18:6a4db94011d3 16181 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 16182 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
sahilmgandhi 18:6a4db94011d3 16183 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
sahilmgandhi 18:6a4db94011d3 16184 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 16185 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
sahilmgandhi 18:6a4db94011d3 16186 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
sahilmgandhi 18:6a4db94011d3 16187 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 16188 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
sahilmgandhi 18:6a4db94011d3 16189 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
sahilmgandhi 18:6a4db94011d3 16190 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 16191 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
sahilmgandhi 18:6a4db94011d3 16192 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
sahilmgandhi 18:6a4db94011d3 16193 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 16194 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
sahilmgandhi 18:6a4db94011d3 16195
sahilmgandhi 18:6a4db94011d3 16196 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
sahilmgandhi 18:6a4db94011d3 16197 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16198 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
sahilmgandhi 18:6a4db94011d3 16199 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
sahilmgandhi 18:6a4db94011d3 16200
sahilmgandhi 18:6a4db94011d3 16201 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
sahilmgandhi 18:6a4db94011d3 16202 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
sahilmgandhi 18:6a4db94011d3 16203 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
sahilmgandhi 18:6a4db94011d3 16204 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 16205 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 16206 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 16207 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 16208 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
sahilmgandhi 18:6a4db94011d3 16209 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 16210 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
sahilmgandhi 18:6a4db94011d3 16211 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
sahilmgandhi 18:6a4db94011d3 16212 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 16213 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
sahilmgandhi 18:6a4db94011d3 16214
sahilmgandhi 18:6a4db94011d3 16215 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
sahilmgandhi 18:6a4db94011d3 16216 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 16217 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 16218 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 16219 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 16220
sahilmgandhi 18:6a4db94011d3 16221 #define USB_OTG_HCCHAR_MC_Pos (20U)
sahilmgandhi 18:6a4db94011d3 16222 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
sahilmgandhi 18:6a4db94011d3 16223 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
sahilmgandhi 18:6a4db94011d3 16224 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 16225 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 16226
sahilmgandhi 18:6a4db94011d3 16227 #define USB_OTG_HCCHAR_DAD_Pos (22U)
sahilmgandhi 18:6a4db94011d3 16228 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
sahilmgandhi 18:6a4db94011d3 16229 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
sahilmgandhi 18:6a4db94011d3 16230 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
sahilmgandhi 18:6a4db94011d3 16231 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
sahilmgandhi 18:6a4db94011d3 16232 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
sahilmgandhi 18:6a4db94011d3 16233 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
sahilmgandhi 18:6a4db94011d3 16234 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 16235 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 16236 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 16237 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
sahilmgandhi 18:6a4db94011d3 16238 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 16239 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
sahilmgandhi 18:6a4db94011d3 16240 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
sahilmgandhi 18:6a4db94011d3 16241 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 16242 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
sahilmgandhi 18:6a4db94011d3 16243 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
sahilmgandhi 18:6a4db94011d3 16244 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 16245 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
sahilmgandhi 18:6a4db94011d3 16246
sahilmgandhi 18:6a4db94011d3 16247 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
sahilmgandhi 18:6a4db94011d3 16248
sahilmgandhi 18:6a4db94011d3 16249 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16250 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
sahilmgandhi 18:6a4db94011d3 16251 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
sahilmgandhi 18:6a4db94011d3 16252 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16253 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16254 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 16255 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 16256 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16257 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 16258 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 16259
sahilmgandhi 18:6a4db94011d3 16260 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
sahilmgandhi 18:6a4db94011d3 16261 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
sahilmgandhi 18:6a4db94011d3 16262 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
sahilmgandhi 18:6a4db94011d3 16263 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 16264 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 16265 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 16266 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 16267 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 16268 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 16269 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 16270
sahilmgandhi 18:6a4db94011d3 16271 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
sahilmgandhi 18:6a4db94011d3 16272 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
sahilmgandhi 18:6a4db94011d3 16273 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
sahilmgandhi 18:6a4db94011d3 16274 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 16275 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 16276 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
sahilmgandhi 18:6a4db94011d3 16277 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
sahilmgandhi 18:6a4db94011d3 16278 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
sahilmgandhi 18:6a4db94011d3 16279 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
sahilmgandhi 18:6a4db94011d3 16280 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 16281 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
sahilmgandhi 18:6a4db94011d3 16282
sahilmgandhi 18:6a4db94011d3 16283 /******************** Bit definition for USB_OTG_HCINT register ********************/
sahilmgandhi 18:6a4db94011d3 16284 #define USB_OTG_HCINT_XFRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16285 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16286 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
sahilmgandhi 18:6a4db94011d3 16287 #define USB_OTG_HCINT_CHH_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16288 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16289 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
sahilmgandhi 18:6a4db94011d3 16290 #define USB_OTG_HCINT_AHBERR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 16291 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 16292 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
sahilmgandhi 18:6a4db94011d3 16293 #define USB_OTG_HCINT_STALL_Pos (3U)
sahilmgandhi 18:6a4db94011d3 16294 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 16295 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
sahilmgandhi 18:6a4db94011d3 16296 #define USB_OTG_HCINT_NAK_Pos (4U)
sahilmgandhi 18:6a4db94011d3 16297 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16298 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
sahilmgandhi 18:6a4db94011d3 16299 #define USB_OTG_HCINT_ACK_Pos (5U)
sahilmgandhi 18:6a4db94011d3 16300 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 16301 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
sahilmgandhi 18:6a4db94011d3 16302 #define USB_OTG_HCINT_NYET_Pos (6U)
sahilmgandhi 18:6a4db94011d3 16303 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 16304 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
sahilmgandhi 18:6a4db94011d3 16305 #define USB_OTG_HCINT_TXERR_Pos (7U)
sahilmgandhi 18:6a4db94011d3 16306 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 16307 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
sahilmgandhi 18:6a4db94011d3 16308 #define USB_OTG_HCINT_BBERR_Pos (8U)
sahilmgandhi 18:6a4db94011d3 16309 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 16310 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
sahilmgandhi 18:6a4db94011d3 16311 #define USB_OTG_HCINT_FRMOR_Pos (9U)
sahilmgandhi 18:6a4db94011d3 16312 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 16313 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
sahilmgandhi 18:6a4db94011d3 16314 #define USB_OTG_HCINT_DTERR_Pos (10U)
sahilmgandhi 18:6a4db94011d3 16315 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 16316 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
sahilmgandhi 18:6a4db94011d3 16317
sahilmgandhi 18:6a4db94011d3 16318 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
sahilmgandhi 18:6a4db94011d3 16319 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16320 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16321 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
sahilmgandhi 18:6a4db94011d3 16322 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16323 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16324 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
sahilmgandhi 18:6a4db94011d3 16325 #define USB_OTG_DIEPINT_TOC_Pos (3U)
sahilmgandhi 18:6a4db94011d3 16326 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 16327 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
sahilmgandhi 18:6a4db94011d3 16328 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
sahilmgandhi 18:6a4db94011d3 16329 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16330 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
sahilmgandhi 18:6a4db94011d3 16331 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
sahilmgandhi 18:6a4db94011d3 16332 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 16333 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
sahilmgandhi 18:6a4db94011d3 16334 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
sahilmgandhi 18:6a4db94011d3 16335 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 16336 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
sahilmgandhi 18:6a4db94011d3 16337 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
sahilmgandhi 18:6a4db94011d3 16338 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 16339 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
sahilmgandhi 18:6a4db94011d3 16340 #define USB_OTG_DIEPINT_BNA_Pos (9U)
sahilmgandhi 18:6a4db94011d3 16341 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 16342 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
sahilmgandhi 18:6a4db94011d3 16343 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
sahilmgandhi 18:6a4db94011d3 16344 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
sahilmgandhi 18:6a4db94011d3 16345 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
sahilmgandhi 18:6a4db94011d3 16346 #define USB_OTG_DIEPINT_BERR_Pos (12U)
sahilmgandhi 18:6a4db94011d3 16347 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
sahilmgandhi 18:6a4db94011d3 16348 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
sahilmgandhi 18:6a4db94011d3 16349 #define USB_OTG_DIEPINT_NAK_Pos (13U)
sahilmgandhi 18:6a4db94011d3 16350 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
sahilmgandhi 18:6a4db94011d3 16351 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
sahilmgandhi 18:6a4db94011d3 16352
sahilmgandhi 18:6a4db94011d3 16353 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
sahilmgandhi 18:6a4db94011d3 16354 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16355 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16356 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
sahilmgandhi 18:6a4db94011d3 16357 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16358 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16359 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
sahilmgandhi 18:6a4db94011d3 16360 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
sahilmgandhi 18:6a4db94011d3 16361 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
sahilmgandhi 18:6a4db94011d3 16362 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
sahilmgandhi 18:6a4db94011d3 16363 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
sahilmgandhi 18:6a4db94011d3 16364 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 16365 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 16366 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
sahilmgandhi 18:6a4db94011d3 16367 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16368 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 16369 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
sahilmgandhi 18:6a4db94011d3 16370 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
sahilmgandhi 18:6a4db94011d3 16371 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
sahilmgandhi 18:6a4db94011d3 16372 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
sahilmgandhi 18:6a4db94011d3 16373 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 16374 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
sahilmgandhi 18:6a4db94011d3 16375 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
sahilmgandhi 18:6a4db94011d3 16376 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
sahilmgandhi 18:6a4db94011d3 16377 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
sahilmgandhi 18:6a4db94011d3 16378 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
sahilmgandhi 18:6a4db94011d3 16379 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
sahilmgandhi 18:6a4db94011d3 16380 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
sahilmgandhi 18:6a4db94011d3 16381 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
sahilmgandhi 18:6a4db94011d3 16382 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
sahilmgandhi 18:6a4db94011d3 16383 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
sahilmgandhi 18:6a4db94011d3 16384 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
sahilmgandhi 18:6a4db94011d3 16385 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
sahilmgandhi 18:6a4db94011d3 16386 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
sahilmgandhi 18:6a4db94011d3 16387
sahilmgandhi 18:6a4db94011d3 16388 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 16389
sahilmgandhi 18:6a4db94011d3 16390 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16391 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
sahilmgandhi 18:6a4db94011d3 16392 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 16393 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
sahilmgandhi 18:6a4db94011d3 16394 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
sahilmgandhi 18:6a4db94011d3 16395 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 16396 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
sahilmgandhi 18:6a4db94011d3 16397 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
sahilmgandhi 18:6a4db94011d3 16398 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 16399 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 16400 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16401 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
sahilmgandhi 18:6a4db94011d3 16402 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 16403 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
sahilmgandhi 18:6a4db94011d3 16404 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
sahilmgandhi 18:6a4db94011d3 16405 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 16406 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
sahilmgandhi 18:6a4db94011d3 16407 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 16408 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
sahilmgandhi 18:6a4db94011d3 16409 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
sahilmgandhi 18:6a4db94011d3 16410 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
sahilmgandhi 18:6a4db94011d3 16411 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
sahilmgandhi 18:6a4db94011d3 16412 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 16413 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 16414
sahilmgandhi 18:6a4db94011d3 16415 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
sahilmgandhi 18:6a4db94011d3 16416 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16417 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 16418 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
sahilmgandhi 18:6a4db94011d3 16419
sahilmgandhi 18:6a4db94011d3 16420 /******************** Bit definition for USB_OTG_HCDMA register ********************/
sahilmgandhi 18:6a4db94011d3 16421 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16422 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
sahilmgandhi 18:6a4db94011d3 16423 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
sahilmgandhi 18:6a4db94011d3 16424
sahilmgandhi 18:6a4db94011d3 16425 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
sahilmgandhi 18:6a4db94011d3 16426 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16427 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 16428 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
sahilmgandhi 18:6a4db94011d3 16429
sahilmgandhi 18:6a4db94011d3 16430 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
sahilmgandhi 18:6a4db94011d3 16431 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16432 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
sahilmgandhi 18:6a4db94011d3 16433 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
sahilmgandhi 18:6a4db94011d3 16434 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
sahilmgandhi 18:6a4db94011d3 16435 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
sahilmgandhi 18:6a4db94011d3 16436 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
sahilmgandhi 18:6a4db94011d3 16437
sahilmgandhi 18:6a4db94011d3 16438 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
sahilmgandhi 18:6a4db94011d3 16439
sahilmgandhi 18:6a4db94011d3 16440 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16441 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
sahilmgandhi 18:6a4db94011d3 16442 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 16443 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
sahilmgandhi 18:6a4db94011d3 16444 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
sahilmgandhi 18:6a4db94011d3 16445 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
sahilmgandhi 18:6a4db94011d3 16446 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
sahilmgandhi 18:6a4db94011d3 16447 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
sahilmgandhi 18:6a4db94011d3 16448 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
sahilmgandhi 18:6a4db94011d3 16449 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
sahilmgandhi 18:6a4db94011d3 16450 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
sahilmgandhi 18:6a4db94011d3 16451 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
sahilmgandhi 18:6a4db94011d3 16452 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
sahilmgandhi 18:6a4db94011d3 16453 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 16454 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
sahilmgandhi 18:6a4db94011d3 16455 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
sahilmgandhi 18:6a4db94011d3 16456 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
sahilmgandhi 18:6a4db94011d3 16457 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
sahilmgandhi 18:6a4db94011d3 16458 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
sahilmgandhi 18:6a4db94011d3 16459 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
sahilmgandhi 18:6a4db94011d3 16460 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
sahilmgandhi 18:6a4db94011d3 16461 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
sahilmgandhi 18:6a4db94011d3 16462 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
sahilmgandhi 18:6a4db94011d3 16463 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
sahilmgandhi 18:6a4db94011d3 16464 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
sahilmgandhi 18:6a4db94011d3 16465 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
sahilmgandhi 18:6a4db94011d3 16466 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
sahilmgandhi 18:6a4db94011d3 16467 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
sahilmgandhi 18:6a4db94011d3 16468 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
sahilmgandhi 18:6a4db94011d3 16469 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
sahilmgandhi 18:6a4db94011d3 16470 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
sahilmgandhi 18:6a4db94011d3 16471 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
sahilmgandhi 18:6a4db94011d3 16472 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
sahilmgandhi 18:6a4db94011d3 16473 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 16474 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
sahilmgandhi 18:6a4db94011d3 16475 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
sahilmgandhi 18:6a4db94011d3 16476 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
sahilmgandhi 18:6a4db94011d3 16477 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
sahilmgandhi 18:6a4db94011d3 16478
sahilmgandhi 18:6a4db94011d3 16479 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
sahilmgandhi 18:6a4db94011d3 16480 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16481 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16482 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
sahilmgandhi 18:6a4db94011d3 16483 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16484 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16485 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
sahilmgandhi 18:6a4db94011d3 16486 #define USB_OTG_DOEPINT_STUP_Pos (3U)
sahilmgandhi 18:6a4db94011d3 16487 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
sahilmgandhi 18:6a4db94011d3 16488 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
sahilmgandhi 18:6a4db94011d3 16489 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
sahilmgandhi 18:6a4db94011d3 16490 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16491 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
sahilmgandhi 18:6a4db94011d3 16492 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
sahilmgandhi 18:6a4db94011d3 16493 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
sahilmgandhi 18:6a4db94011d3 16494 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
sahilmgandhi 18:6a4db94011d3 16495 #define USB_OTG_DOEPINT_NYET_Pos (14U)
sahilmgandhi 18:6a4db94011d3 16496 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
sahilmgandhi 18:6a4db94011d3 16497 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
sahilmgandhi 18:6a4db94011d3 16498
sahilmgandhi 18:6a4db94011d3 16499 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
sahilmgandhi 18:6a4db94011d3 16500
sahilmgandhi 18:6a4db94011d3 16501 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16502 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
sahilmgandhi 18:6a4db94011d3 16503 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
sahilmgandhi 18:6a4db94011d3 16504 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
sahilmgandhi 18:6a4db94011d3 16505 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
sahilmgandhi 18:6a4db94011d3 16506 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
sahilmgandhi 18:6a4db94011d3 16507
sahilmgandhi 18:6a4db94011d3 16508 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
sahilmgandhi 18:6a4db94011d3 16509 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
sahilmgandhi 18:6a4db94011d3 16510 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
sahilmgandhi 18:6a4db94011d3 16511 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
sahilmgandhi 18:6a4db94011d3 16512 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
sahilmgandhi 18:6a4db94011d3 16513
sahilmgandhi 18:6a4db94011d3 16514 /******************** Bit definition for PCGCCTL register ********************/
sahilmgandhi 18:6a4db94011d3 16515 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
sahilmgandhi 18:6a4db94011d3 16516 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
sahilmgandhi 18:6a4db94011d3 16517 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
sahilmgandhi 18:6a4db94011d3 16518 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
sahilmgandhi 18:6a4db94011d3 16519 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
sahilmgandhi 18:6a4db94011d3 16520 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
sahilmgandhi 18:6a4db94011d3 16521 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
sahilmgandhi 18:6a4db94011d3 16522 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
sahilmgandhi 18:6a4db94011d3 16523 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
sahilmgandhi 18:6a4db94011d3 16524
sahilmgandhi 18:6a4db94011d3 16525 /**
sahilmgandhi 18:6a4db94011d3 16526 * @}
sahilmgandhi 18:6a4db94011d3 16527 */
sahilmgandhi 18:6a4db94011d3 16528
sahilmgandhi 18:6a4db94011d3 16529 /**
sahilmgandhi 18:6a4db94011d3 16530 * @}
sahilmgandhi 18:6a4db94011d3 16531 */
sahilmgandhi 18:6a4db94011d3 16532
sahilmgandhi 18:6a4db94011d3 16533 /** @addtogroup Exported_macros
sahilmgandhi 18:6a4db94011d3 16534 * @{
sahilmgandhi 18:6a4db94011d3 16535 */
sahilmgandhi 18:6a4db94011d3 16536
sahilmgandhi 18:6a4db94011d3 16537 /******************************* ADC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16538 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
sahilmgandhi 18:6a4db94011d3 16539 ((INSTANCE) == ADC2) || \
sahilmgandhi 18:6a4db94011d3 16540 ((INSTANCE) == ADC3))
sahilmgandhi 18:6a4db94011d3 16541
sahilmgandhi 18:6a4db94011d3 16542 /******************************* CAN Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16543 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
sahilmgandhi 18:6a4db94011d3 16544 ((INSTANCE) == CAN2))
sahilmgandhi 18:6a4db94011d3 16545 /******************************* CRC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16546 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
sahilmgandhi 18:6a4db94011d3 16547
sahilmgandhi 18:6a4db94011d3 16548 /******************************* DAC Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16549 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
sahilmgandhi 18:6a4db94011d3 16550
sahilmgandhi 18:6a4db94011d3 16551 /******************************* DCMI Instances *******************************/
sahilmgandhi 18:6a4db94011d3 16552 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
sahilmgandhi 18:6a4db94011d3 16553
sahilmgandhi 18:6a4db94011d3 16554 /******************************* DMA2D Instances *******************************/
sahilmgandhi 18:6a4db94011d3 16555 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
sahilmgandhi 18:6a4db94011d3 16556
sahilmgandhi 18:6a4db94011d3 16557 /******************************** DMA Instances *******************************/
sahilmgandhi 18:6a4db94011d3 16558 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
sahilmgandhi 18:6a4db94011d3 16559 ((INSTANCE) == DMA1_Stream1) || \
sahilmgandhi 18:6a4db94011d3 16560 ((INSTANCE) == DMA1_Stream2) || \
sahilmgandhi 18:6a4db94011d3 16561 ((INSTANCE) == DMA1_Stream3) || \
sahilmgandhi 18:6a4db94011d3 16562 ((INSTANCE) == DMA1_Stream4) || \
sahilmgandhi 18:6a4db94011d3 16563 ((INSTANCE) == DMA1_Stream5) || \
sahilmgandhi 18:6a4db94011d3 16564 ((INSTANCE) == DMA1_Stream6) || \
sahilmgandhi 18:6a4db94011d3 16565 ((INSTANCE) == DMA1_Stream7) || \
sahilmgandhi 18:6a4db94011d3 16566 ((INSTANCE) == DMA2_Stream0) || \
sahilmgandhi 18:6a4db94011d3 16567 ((INSTANCE) == DMA2_Stream1) || \
sahilmgandhi 18:6a4db94011d3 16568 ((INSTANCE) == DMA2_Stream2) || \
sahilmgandhi 18:6a4db94011d3 16569 ((INSTANCE) == DMA2_Stream3) || \
sahilmgandhi 18:6a4db94011d3 16570 ((INSTANCE) == DMA2_Stream4) || \
sahilmgandhi 18:6a4db94011d3 16571 ((INSTANCE) == DMA2_Stream5) || \
sahilmgandhi 18:6a4db94011d3 16572 ((INSTANCE) == DMA2_Stream6) || \
sahilmgandhi 18:6a4db94011d3 16573 ((INSTANCE) == DMA2_Stream7))
sahilmgandhi 18:6a4db94011d3 16574
sahilmgandhi 18:6a4db94011d3 16575 /******************************* GPIO Instances *******************************/
sahilmgandhi 18:6a4db94011d3 16576 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
sahilmgandhi 18:6a4db94011d3 16577 ((INSTANCE) == GPIOB) || \
sahilmgandhi 18:6a4db94011d3 16578 ((INSTANCE) == GPIOC) || \
sahilmgandhi 18:6a4db94011d3 16579 ((INSTANCE) == GPIOD) || \
sahilmgandhi 18:6a4db94011d3 16580 ((INSTANCE) == GPIOE) || \
sahilmgandhi 18:6a4db94011d3 16581 ((INSTANCE) == GPIOF) || \
sahilmgandhi 18:6a4db94011d3 16582 ((INSTANCE) == GPIOG) || \
sahilmgandhi 18:6a4db94011d3 16583 ((INSTANCE) == GPIOH) || \
sahilmgandhi 18:6a4db94011d3 16584 ((INSTANCE) == GPIOI) || \
sahilmgandhi 18:6a4db94011d3 16585 ((INSTANCE) == GPIOJ) || \
sahilmgandhi 18:6a4db94011d3 16586 ((INSTANCE) == GPIOK))
sahilmgandhi 18:6a4db94011d3 16587
sahilmgandhi 18:6a4db94011d3 16588 /******************************** I2C Instances *******************************/
sahilmgandhi 18:6a4db94011d3 16589 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
sahilmgandhi 18:6a4db94011d3 16590 ((INSTANCE) == I2C2) || \
sahilmgandhi 18:6a4db94011d3 16591 ((INSTANCE) == I2C3))
sahilmgandhi 18:6a4db94011d3 16592
sahilmgandhi 18:6a4db94011d3 16593 /******************************* SMBUS Instances ******************************/
sahilmgandhi 18:6a4db94011d3 16594 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
sahilmgandhi 18:6a4db94011d3 16595
sahilmgandhi 18:6a4db94011d3 16596 /******************************** I2S Instances *******************************/
sahilmgandhi 18:6a4db94011d3 16597 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 16598 ((INSTANCE) == SPI3))
sahilmgandhi 18:6a4db94011d3 16599
sahilmgandhi 18:6a4db94011d3 16600 /*************************** I2S Extended Instances ***************************/
sahilmgandhi 18:6a4db94011d3 16601 #define IS_I2S_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == I2S2ext)|| \
sahilmgandhi 18:6a4db94011d3 16602 ((INSTANCE) == I2S3ext))
sahilmgandhi 18:6a4db94011d3 16603
sahilmgandhi 18:6a4db94011d3 16604 /******************************* RNG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16605 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
sahilmgandhi 18:6a4db94011d3 16606
sahilmgandhi 18:6a4db94011d3 16607 /****************************** RTC Instances *********************************/
sahilmgandhi 18:6a4db94011d3 16608 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
sahilmgandhi 18:6a4db94011d3 16609
sahilmgandhi 18:6a4db94011d3 16610 /******************************* SAI Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16611 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
sahilmgandhi 18:6a4db94011d3 16612 ((PERIPH) == SAI1_Block_B))
sahilmgandhi 18:6a4db94011d3 16613 /* Legacy define */
sahilmgandhi 18:6a4db94011d3 16614
sahilmgandhi 18:6a4db94011d3 16615 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
sahilmgandhi 18:6a4db94011d3 16616
sahilmgandhi 18:6a4db94011d3 16617 /******************************** SPI Instances *******************************/
sahilmgandhi 18:6a4db94011d3 16618 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
sahilmgandhi 18:6a4db94011d3 16619 ((INSTANCE) == SPI2) || \
sahilmgandhi 18:6a4db94011d3 16620 ((INSTANCE) == SPI3) || \
sahilmgandhi 18:6a4db94011d3 16621 ((INSTANCE) == SPI4) || \
sahilmgandhi 18:6a4db94011d3 16622 ((INSTANCE) == SPI5) || \
sahilmgandhi 18:6a4db94011d3 16623 ((INSTANCE) == SPI6))
sahilmgandhi 18:6a4db94011d3 16624
sahilmgandhi 18:6a4db94011d3 16625
sahilmgandhi 18:6a4db94011d3 16626 /****************** TIM Instances : All supported instances *******************/
sahilmgandhi 18:6a4db94011d3 16627 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16628 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16629 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16630 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16631 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16632 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 16633 ((INSTANCE) == TIM7) || \
sahilmgandhi 18:6a4db94011d3 16634 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 16635 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 16636 ((INSTANCE) == TIM10)|| \
sahilmgandhi 18:6a4db94011d3 16637 ((INSTANCE) == TIM11)|| \
sahilmgandhi 18:6a4db94011d3 16638 ((INSTANCE) == TIM12)|| \
sahilmgandhi 18:6a4db94011d3 16639 ((INSTANCE) == TIM13)|| \
sahilmgandhi 18:6a4db94011d3 16640 ((INSTANCE) == TIM14))
sahilmgandhi 18:6a4db94011d3 16641
sahilmgandhi 18:6a4db94011d3 16642 /************* TIM Instances : at least 1 capture/compare channel *************/
sahilmgandhi 18:6a4db94011d3 16643 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16644 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16645 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16646 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16647 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16648 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 16649 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 16650 ((INSTANCE) == TIM10) || \
sahilmgandhi 18:6a4db94011d3 16651 ((INSTANCE) == TIM11) || \
sahilmgandhi 18:6a4db94011d3 16652 ((INSTANCE) == TIM12) || \
sahilmgandhi 18:6a4db94011d3 16653 ((INSTANCE) == TIM13) || \
sahilmgandhi 18:6a4db94011d3 16654 ((INSTANCE) == TIM14))
sahilmgandhi 18:6a4db94011d3 16655
sahilmgandhi 18:6a4db94011d3 16656 /************ TIM Instances : at least 2 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 16657 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16658 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16659 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16660 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16661 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16662 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 16663 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 16664 ((INSTANCE) == TIM12))
sahilmgandhi 18:6a4db94011d3 16665
sahilmgandhi 18:6a4db94011d3 16666 /************ TIM Instances : at least 3 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 16667 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16668 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16669 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16670 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16671 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16672 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16673
sahilmgandhi 18:6a4db94011d3 16674 /************ TIM Instances : at least 4 capture/compare channels *************/
sahilmgandhi 18:6a4db94011d3 16675 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16676 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16677 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16678 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16679 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16680 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16681
sahilmgandhi 18:6a4db94011d3 16682 /******************** TIM Instances : Advanced-control timers *****************/
sahilmgandhi 18:6a4db94011d3 16683 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16684 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16685
sahilmgandhi 18:6a4db94011d3 16686 /******************* TIM Instances : Timer input XOR function *****************/
sahilmgandhi 18:6a4db94011d3 16687 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16688 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16689 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16690 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16691 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16692 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16693
sahilmgandhi 18:6a4db94011d3 16694 /****************** TIM Instances : DMA requests generation (UDE) *************/
sahilmgandhi 18:6a4db94011d3 16695 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16696 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16697 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16698 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16699 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16700 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 16701 ((INSTANCE) == TIM7) || \
sahilmgandhi 18:6a4db94011d3 16702 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16703
sahilmgandhi 18:6a4db94011d3 16704 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
sahilmgandhi 18:6a4db94011d3 16705 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16706 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16707 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16708 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16709 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16710 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16711
sahilmgandhi 18:6a4db94011d3 16712 /************ TIM Instances : DMA requests generation (COMDE) *****************/
sahilmgandhi 18:6a4db94011d3 16713 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16714 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16715 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16716 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16717 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16718 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16719
sahilmgandhi 18:6a4db94011d3 16720 /******************** TIM Instances : DMA burst feature ***********************/
sahilmgandhi 18:6a4db94011d3 16721 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16722 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16723 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16724 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16725 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16726 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16727
sahilmgandhi 18:6a4db94011d3 16728 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
sahilmgandhi 18:6a4db94011d3 16729 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16730 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16731 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16732 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16733 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16734 ((INSTANCE) == TIM6) || \
sahilmgandhi 18:6a4db94011d3 16735 ((INSTANCE) == TIM7) || \
sahilmgandhi 18:6a4db94011d3 16736 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 16737 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 16738 ((INSTANCE) == TIM12))
sahilmgandhi 18:6a4db94011d3 16739
sahilmgandhi 18:6a4db94011d3 16740 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
sahilmgandhi 18:6a4db94011d3 16741 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16742 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16743 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16744 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16745 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16746 ((INSTANCE) == TIM8) || \
sahilmgandhi 18:6a4db94011d3 16747 ((INSTANCE) == TIM9) || \
sahilmgandhi 18:6a4db94011d3 16748 ((INSTANCE) == TIM12))
sahilmgandhi 18:6a4db94011d3 16749
sahilmgandhi 18:6a4db94011d3 16750 /********************** TIM Instances : 32 bit Counter ************************/
sahilmgandhi 18:6a4db94011d3 16751 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16752 ((INSTANCE) == TIM5))
sahilmgandhi 18:6a4db94011d3 16753
sahilmgandhi 18:6a4db94011d3 16754 /***************** TIM Instances : external trigger input availabe ************/
sahilmgandhi 18:6a4db94011d3 16755 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
sahilmgandhi 18:6a4db94011d3 16756 ((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16757 ((INSTANCE) == TIM3) || \
sahilmgandhi 18:6a4db94011d3 16758 ((INSTANCE) == TIM4) || \
sahilmgandhi 18:6a4db94011d3 16759 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16760 ((INSTANCE) == TIM8))
sahilmgandhi 18:6a4db94011d3 16761
sahilmgandhi 18:6a4db94011d3 16762 /****************** TIM Instances : remapping capability **********************/
sahilmgandhi 18:6a4db94011d3 16763 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
sahilmgandhi 18:6a4db94011d3 16764 ((INSTANCE) == TIM5) || \
sahilmgandhi 18:6a4db94011d3 16765 ((INSTANCE) == TIM11))
sahilmgandhi 18:6a4db94011d3 16766
sahilmgandhi 18:6a4db94011d3 16767 /******************* TIM Instances : output(s) available **********************/
sahilmgandhi 18:6a4db94011d3 16768 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 16769 ((((INSTANCE) == TIM1) && \
sahilmgandhi 18:6a4db94011d3 16770 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16771 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 16772 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 16773 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 16774 || \
sahilmgandhi 18:6a4db94011d3 16775 (((INSTANCE) == TIM2) && \
sahilmgandhi 18:6a4db94011d3 16776 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16777 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 16778 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 16779 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 16780 || \
sahilmgandhi 18:6a4db94011d3 16781 (((INSTANCE) == TIM3) && \
sahilmgandhi 18:6a4db94011d3 16782 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16783 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 16784 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 16785 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 16786 || \
sahilmgandhi 18:6a4db94011d3 16787 (((INSTANCE) == TIM4) && \
sahilmgandhi 18:6a4db94011d3 16788 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16789 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 16790 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 16791 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 16792 || \
sahilmgandhi 18:6a4db94011d3 16793 (((INSTANCE) == TIM5) && \
sahilmgandhi 18:6a4db94011d3 16794 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16795 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 16796 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 16797 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 16798 || \
sahilmgandhi 18:6a4db94011d3 16799 (((INSTANCE) == TIM8) && \
sahilmgandhi 18:6a4db94011d3 16800 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16801 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 16802 ((CHANNEL) == TIM_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 16803 ((CHANNEL) == TIM_CHANNEL_4))) \
sahilmgandhi 18:6a4db94011d3 16804 || \
sahilmgandhi 18:6a4db94011d3 16805 (((INSTANCE) == TIM9) && \
sahilmgandhi 18:6a4db94011d3 16806 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16807 ((CHANNEL) == TIM_CHANNEL_2))) \
sahilmgandhi 18:6a4db94011d3 16808 || \
sahilmgandhi 18:6a4db94011d3 16809 (((INSTANCE) == TIM10) && \
sahilmgandhi 18:6a4db94011d3 16810 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 16811 || \
sahilmgandhi 18:6a4db94011d3 16812 (((INSTANCE) == TIM11) && \
sahilmgandhi 18:6a4db94011d3 16813 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 16814 || \
sahilmgandhi 18:6a4db94011d3 16815 (((INSTANCE) == TIM12) && \
sahilmgandhi 18:6a4db94011d3 16816 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16817 ((CHANNEL) == TIM_CHANNEL_2))) \
sahilmgandhi 18:6a4db94011d3 16818 || \
sahilmgandhi 18:6a4db94011d3 16819 (((INSTANCE) == TIM13) && \
sahilmgandhi 18:6a4db94011d3 16820 (((CHANNEL) == TIM_CHANNEL_1))) \
sahilmgandhi 18:6a4db94011d3 16821 || \
sahilmgandhi 18:6a4db94011d3 16822 (((INSTANCE) == TIM14) && \
sahilmgandhi 18:6a4db94011d3 16823 (((CHANNEL) == TIM_CHANNEL_1))))
sahilmgandhi 18:6a4db94011d3 16824
sahilmgandhi 18:6a4db94011d3 16825 /************ TIM Instances : complementary output(s) available ***************/
sahilmgandhi 18:6a4db94011d3 16826 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
sahilmgandhi 18:6a4db94011d3 16827 ((((INSTANCE) == TIM1) && \
sahilmgandhi 18:6a4db94011d3 16828 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16829 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 16830 ((CHANNEL) == TIM_CHANNEL_3))) \
sahilmgandhi 18:6a4db94011d3 16831 || \
sahilmgandhi 18:6a4db94011d3 16832 (((INSTANCE) == TIM8) && \
sahilmgandhi 18:6a4db94011d3 16833 (((CHANNEL) == TIM_CHANNEL_1) || \
sahilmgandhi 18:6a4db94011d3 16834 ((CHANNEL) == TIM_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 16835 ((CHANNEL) == TIM_CHANNEL_3))))
sahilmgandhi 18:6a4db94011d3 16836
sahilmgandhi 18:6a4db94011d3 16837 /******************** USART Instances : Synchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 16838 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 16839 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 16840 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 16841 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 16842
sahilmgandhi 18:6a4db94011d3 16843 /******************** UART Instances : Asynchronous mode **********************/
sahilmgandhi 18:6a4db94011d3 16844 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 16845 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 16846 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 16847 ((INSTANCE) == UART4) || \
sahilmgandhi 18:6a4db94011d3 16848 ((INSTANCE) == UART5) || \
sahilmgandhi 18:6a4db94011d3 16849 ((INSTANCE) == USART6) || \
sahilmgandhi 18:6a4db94011d3 16850 ((INSTANCE) == UART7) || \
sahilmgandhi 18:6a4db94011d3 16851 ((INSTANCE) == UART8))
sahilmgandhi 18:6a4db94011d3 16852
sahilmgandhi 18:6a4db94011d3 16853 /****************** UART Instances : Hardware Flow control ********************/
sahilmgandhi 18:6a4db94011d3 16854 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 16855 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 16856 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 16857 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 16858
sahilmgandhi 18:6a4db94011d3 16859 /********************* UART Instances : Smart card mode ***********************/
sahilmgandhi 18:6a4db94011d3 16860 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 16861 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 16862 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 16863 ((INSTANCE) == USART6))
sahilmgandhi 18:6a4db94011d3 16864
sahilmgandhi 18:6a4db94011d3 16865 /*********************** UART Instances : IRDA mode ***************************/
sahilmgandhi 18:6a4db94011d3 16866 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
sahilmgandhi 18:6a4db94011d3 16867 ((INSTANCE) == USART2) || \
sahilmgandhi 18:6a4db94011d3 16868 ((INSTANCE) == USART3) || \
sahilmgandhi 18:6a4db94011d3 16869 ((INSTANCE) == UART4) || \
sahilmgandhi 18:6a4db94011d3 16870 ((INSTANCE) == UART5) || \
sahilmgandhi 18:6a4db94011d3 16871 ((INSTANCE) == USART6) || \
sahilmgandhi 18:6a4db94011d3 16872 ((INSTANCE) == UART7) || \
sahilmgandhi 18:6a4db94011d3 16873 ((INSTANCE) == UART8))
sahilmgandhi 18:6a4db94011d3 16874
sahilmgandhi 18:6a4db94011d3 16875 /*********************** PCD Instances ****************************************/
sahilmgandhi 18:6a4db94011d3 16876 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
sahilmgandhi 18:6a4db94011d3 16877 ((INSTANCE) == USB_OTG_HS))
sahilmgandhi 18:6a4db94011d3 16878
sahilmgandhi 18:6a4db94011d3 16879 /*********************** HCD Instances ****************************************/
sahilmgandhi 18:6a4db94011d3 16880 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
sahilmgandhi 18:6a4db94011d3 16881 ((INSTANCE) == USB_OTG_HS))
sahilmgandhi 18:6a4db94011d3 16882
sahilmgandhi 18:6a4db94011d3 16883 /****************************** SDIO Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16884 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
sahilmgandhi 18:6a4db94011d3 16885
sahilmgandhi 18:6a4db94011d3 16886 /****************************** IWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16887 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
sahilmgandhi 18:6a4db94011d3 16888
sahilmgandhi 18:6a4db94011d3 16889 /****************************** WWDG Instances ********************************/
sahilmgandhi 18:6a4db94011d3 16890 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
sahilmgandhi 18:6a4db94011d3 16891
sahilmgandhi 18:6a4db94011d3 16892 /****************************** USB Exported Constants ************************/
sahilmgandhi 18:6a4db94011d3 16893 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
sahilmgandhi 18:6a4db94011d3 16894 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 16895 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 16896 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
sahilmgandhi 18:6a4db94011d3 16897
sahilmgandhi 18:6a4db94011d3 16898
sahilmgandhi 18:6a4db94011d3 16899 #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
sahilmgandhi 18:6a4db94011d3 16900 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
sahilmgandhi 18:6a4db94011d3 16901 #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
sahilmgandhi 18:6a4db94011d3 16902 #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
sahilmgandhi 18:6a4db94011d3 16903 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
sahilmgandhi 18:6a4db94011d3 16904 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
sahilmgandhi 18:6a4db94011d3 16905 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
sahilmgandhi 18:6a4db94011d3 16906 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
sahilmgandhi 18:6a4db94011d3 16907
sahilmgandhi 18:6a4db94011d3 16908 #define RCC_PLLN_MIN_VALUE 50U
sahilmgandhi 18:6a4db94011d3 16909 #define RCC_PLLN_MAX_VALUE 432U
sahilmgandhi 18:6a4db94011d3 16910
sahilmgandhi 18:6a4db94011d3 16911 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
sahilmgandhi 18:6a4db94011d3 16912 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
sahilmgandhi 18:6a4db94011d3 16913 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
sahilmgandhi 18:6a4db94011d3 16914 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
sahilmgandhi 18:6a4db94011d3 16915 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
sahilmgandhi 18:6a4db94011d3 16916
sahilmgandhi 18:6a4db94011d3 16917 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
sahilmgandhi 18:6a4db94011d3 16918 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
sahilmgandhi 18:6a4db94011d3 16919 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
sahilmgandhi 18:6a4db94011d3 16920 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
sahilmgandhi 18:6a4db94011d3 16921 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
sahilmgandhi 18:6a4db94011d3 16922
sahilmgandhi 18:6a4db94011d3 16923 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
sahilmgandhi 18:6a4db94011d3 16924 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
sahilmgandhi 18:6a4db94011d3 16925 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
sahilmgandhi 18:6a4db94011d3 16926
sahilmgandhi 18:6a4db94011d3 16927 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
sahilmgandhi 18:6a4db94011d3 16928 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 16929 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
sahilmgandhi 18:6a4db94011d3 16930 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
sahilmgandhi 18:6a4db94011d3 16931
sahilmgandhi 18:6a4db94011d3 16932 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 16933 /* For a painless codes migration between the STM32F4xx device product */
sahilmgandhi 18:6a4db94011d3 16934 /* lines, the aliases defined below are put in place to overcome the */
sahilmgandhi 18:6a4db94011d3 16935 /* differences in the interrupt handlers and IRQn definitions. */
sahilmgandhi 18:6a4db94011d3 16936 /* No need to update developed interrupt code when moving across */
sahilmgandhi 18:6a4db94011d3 16937 /* product lines within the same STM32F4 Family */
sahilmgandhi 18:6a4db94011d3 16938 /******************************************************************************/
sahilmgandhi 18:6a4db94011d3 16939 /* Aliases for __IRQn */
sahilmgandhi 18:6a4db94011d3 16940 #define FSMC_IRQn FMC_IRQn
sahilmgandhi 18:6a4db94011d3 16941
sahilmgandhi 18:6a4db94011d3 16942 /* Aliases for __IRQHandler */
sahilmgandhi 18:6a4db94011d3 16943 #define FSMC_IRQHandler FMC_IRQHandler
sahilmgandhi 18:6a4db94011d3 16944 /**
sahilmgandhi 18:6a4db94011d3 16945 * @}
sahilmgandhi 18:6a4db94011d3 16946 */
sahilmgandhi 18:6a4db94011d3 16947
sahilmgandhi 18:6a4db94011d3 16948 /**
sahilmgandhi 18:6a4db94011d3 16949 * @}
sahilmgandhi 18:6a4db94011d3 16950 */
sahilmgandhi 18:6a4db94011d3 16951
sahilmgandhi 18:6a4db94011d3 16952 /**
sahilmgandhi 18:6a4db94011d3 16953 * @}
sahilmgandhi 18:6a4db94011d3 16954 */
sahilmgandhi 18:6a4db94011d3 16955
sahilmgandhi 18:6a4db94011d3 16956 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 16957 }
sahilmgandhi 18:6a4db94011d3 16958 #endif /* __cplusplus */
sahilmgandhi 18:6a4db94011d3 16959
sahilmgandhi 18:6a4db94011d3 16960 #endif /* __STM32F437xx_H */
sahilmgandhi 18:6a4db94011d3 16961
sahilmgandhi 18:6a4db94011d3 16962
sahilmgandhi 18:6a4db94011d3 16963
sahilmgandhi 18:6a4db94011d3 16964 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/