MouseCode - Mouse code for the MacroRat

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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_stm32f4xx.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:: sahilmgandhi
Date:: Sun May 14 23:18:57 2017 +0000
Revision:: 18:6a4db94011d3

Publishing again

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User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file system_stm32f4xx.c
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V2.5.0
sahilmgandhi	18:6a4db94011d3	6	* @date 22-April-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
sahilmgandhi	18:6a4db94011d3	8	*
sahilmgandhi	18:6a4db94011d3	9	* This file provides two functions and one global variable to be called from
sahilmgandhi	18:6a4db94011d3	10	* user application:
sahilmgandhi	18:6a4db94011d3	11	* - SystemInit(): This function is called at startup just after reset and
sahilmgandhi	18:6a4db94011d3	12	* before branch to main program. This call is made inside
sahilmgandhi	18:6a4db94011d3	13	* the "startup_stm32f4xx.s" file.
sahilmgandhi	18:6a4db94011d3	14	*
sahilmgandhi	18:6a4db94011d3	15	* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
sahilmgandhi	18:6a4db94011d3	16	* by the user application to setup the SysTick
sahilmgandhi	18:6a4db94011d3	17	* timer or configure other parameters.
sahilmgandhi	18:6a4db94011d3	18	*
sahilmgandhi	18:6a4db94011d3	19	* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
sahilmgandhi	18:6a4db94011d3	20	* be called whenever the core clock is changed
sahilmgandhi	18:6a4db94011d3	21	* during program execution.
sahilmgandhi	18:6a4db94011d3	22	*
sahilmgandhi	18:6a4db94011d3	23	* This file configures the system clock as follows:
sahilmgandhi	18:6a4db94011d3	24	*-----------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	25	* System clock source \| 1- PLL_HSE_EXTC \| 3- PLL_HSI
sahilmgandhi	18:6a4db94011d3	26	* \| (external 8 MHz clock) \| (internal 16 MHz)
sahilmgandhi	18:6a4db94011d3	27	* \| 2- PLL_HSE_XTAL \|
sahilmgandhi	18:6a4db94011d3	28	* \| (external 8 MHz xtal) \|
sahilmgandhi	18:6a4db94011d3	29	*-----------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	30	* SYSCLK(MHz) \| 168 \| 168
sahilmgandhi	18:6a4db94011d3	31	*-----------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	32	* AHBCLK (MHz) \| 168 \| 168
sahilmgandhi	18:6a4db94011d3	33	*-----------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	34	* APB1CLK (MHz) \| 42 \| 42
sahilmgandhi	18:6a4db94011d3	35	*-----------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	36	* APB2CLK (MHz) \| 84 \| 84
sahilmgandhi	18:6a4db94011d3	37	*-----------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	38	* USB capable (48 MHz precise clock) \| YES \| NO
sahilmgandhi	18:6a4db94011d3	39	*-----------------------------------------------------------------------------
sahilmgandhi	18:6a4db94011d3	40	******************************************************************************
sahilmgandhi	18:6a4db94011d3	41	* @attention
sahilmgandhi	18:6a4db94011d3	42	*
sahilmgandhi	18:6a4db94011d3	43	* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	44	*
sahilmgandhi	18:6a4db94011d3	45	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	46	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	47	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	48	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	49	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	50	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	51	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	52	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	53	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	54	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	55	*
sahilmgandhi	18:6a4db94011d3	56	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	57	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	58	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	59	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	60	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	61	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	62	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	63	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	64	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	65	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	66	*
sahilmgandhi	18:6a4db94011d3	67	******************************************************************************
sahilmgandhi	18:6a4db94011d3	68	*/
sahilmgandhi	18:6a4db94011d3	69
sahilmgandhi	18:6a4db94011d3	70	/** @addtogroup CMSIS
sahilmgandhi	18:6a4db94011d3	71	* @{
sahilmgandhi	18:6a4db94011d3	72	*/
sahilmgandhi	18:6a4db94011d3	73
sahilmgandhi	18:6a4db94011d3	74	/** @addtogroup stm32f4xx_system
sahilmgandhi	18:6a4db94011d3	75	* @{
sahilmgandhi	18:6a4db94011d3	76	*/
sahilmgandhi	18:6a4db94011d3	77
sahilmgandhi	18:6a4db94011d3	78	/** @addtogroup STM32F4xx_System_Private_Includes
sahilmgandhi	18:6a4db94011d3	79	* @{
sahilmgandhi	18:6a4db94011d3	80	*/
sahilmgandhi	18:6a4db94011d3	81
sahilmgandhi	18:6a4db94011d3	82	#include "stm32f4xx.h"
sahilmgandhi	18:6a4db94011d3	83	#include "hal_tick.h"
sahilmgandhi	18:6a4db94011d3	84
sahilmgandhi	18:6a4db94011d3	85	#if !defined (HSE_VALUE)
sahilmgandhi	18:6a4db94011d3	86	#define HSE_VALUE ((uint32_t)8000000) /!< Default value of the External oscillator in Hz /
sahilmgandhi	18:6a4db94011d3	87	#endif /* HSE_VALUE */
sahilmgandhi	18:6a4db94011d3	88
sahilmgandhi	18:6a4db94011d3	89	#if !defined (HSI_VALUE)
sahilmgandhi	18:6a4db94011d3	90	#define HSI_VALUE ((uint32_t)16000000) /!< Value of the Internal oscillator in Hz/
sahilmgandhi	18:6a4db94011d3	91	#endif /* HSI_VALUE */
sahilmgandhi	18:6a4db94011d3	92
sahilmgandhi	18:6a4db94011d3	93	/**
sahilmgandhi	18:6a4db94011d3	94	* @}
sahilmgandhi	18:6a4db94011d3	95	*/
sahilmgandhi	18:6a4db94011d3	96
sahilmgandhi	18:6a4db94011d3	97	/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
sahilmgandhi	18:6a4db94011d3	98	* @{
sahilmgandhi	18:6a4db94011d3	99	*/
sahilmgandhi	18:6a4db94011d3	100
sahilmgandhi	18:6a4db94011d3	101	/**
sahilmgandhi	18:6a4db94011d3	102	* @}
sahilmgandhi	18:6a4db94011d3	103	*/
sahilmgandhi	18:6a4db94011d3	104
sahilmgandhi	18:6a4db94011d3	105	/** @addtogroup STM32F4xx_System_Private_Defines
sahilmgandhi	18:6a4db94011d3	106	* @{
sahilmgandhi	18:6a4db94011d3	107	*/
sahilmgandhi	18:6a4db94011d3	108
sahilmgandhi	18:6a4db94011d3	109	/*********************** Miscellaneous Configuration **********************/
sahilmgandhi	18:6a4db94011d3	110	/!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory /
sahilmgandhi	18:6a4db94011d3	111	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)\
sahilmgandhi	18:6a4db94011d3	112	\|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)\
sahilmgandhi	18:6a4db94011d3	113	\|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx)
sahilmgandhi	18:6a4db94011d3	114	/* #define DATA_IN_ExtSRAM */
sahilmgandhi	18:6a4db94011d3	115	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx \|\|\
sahilmgandhi	18:6a4db94011d3	116	STM32F412Zx \|\| STM32F412Vx */
sahilmgandhi	18:6a4db94011d3	117
sahilmgandhi	18:6a4db94011d3	118	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)\
sahilmgandhi	18:6a4db94011d3	119	\|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	120	/* #define DATA_IN_ExtSDRAM */
sahilmgandhi	18:6a4db94011d3	121	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\|\
sahilmgandhi	18:6a4db94011d3	122	STM32F479xx */
sahilmgandhi	18:6a4db94011d3	123
sahilmgandhi	18:6a4db94011d3	124	/*!< Uncomment the following line if you need to relocate your vector Table in
sahilmgandhi	18:6a4db94011d3	125	Internal SRAM. */
sahilmgandhi	18:6a4db94011d3	126	/* #define VECT_TAB_SRAM */
sahilmgandhi	18:6a4db94011d3	127	#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
sahilmgandhi	18:6a4db94011d3	128	This value must be a multiple of 0x200. */
sahilmgandhi	18:6a4db94011d3	129	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	130
sahilmgandhi	18:6a4db94011d3	131	/**
sahilmgandhi	18:6a4db94011d3	132	* @}
sahilmgandhi	18:6a4db94011d3	133	*/
sahilmgandhi	18:6a4db94011d3	134
sahilmgandhi	18:6a4db94011d3	135	/** @addtogroup STM32F4xx_System_Private_Macros
sahilmgandhi	18:6a4db94011d3	136	* @{
sahilmgandhi	18:6a4db94011d3	137	*/
sahilmgandhi	18:6a4db94011d3	138
sahilmgandhi	18:6a4db94011d3	139	/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
sahilmgandhi	18:6a4db94011d3	140	#define USE_PLL_HSE_EXTC (1) /* Use external clock */
sahilmgandhi	18:6a4db94011d3	141	#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
sahilmgandhi	18:6a4db94011d3	142
sahilmgandhi	18:6a4db94011d3	143	/**
sahilmgandhi	18:6a4db94011d3	144	* @}
sahilmgandhi	18:6a4db94011d3	145	*/
sahilmgandhi	18:6a4db94011d3	146
sahilmgandhi	18:6a4db94011d3	147	/** @addtogroup STM32F4xx_System_Private_Variables
sahilmgandhi	18:6a4db94011d3	148	* @{
sahilmgandhi	18:6a4db94011d3	149	*/
sahilmgandhi	18:6a4db94011d3	150	/* This variable is updated in three ways:
sahilmgandhi	18:6a4db94011d3	151	1) by calling CMSIS function SystemCoreClockUpdate()
sahilmgandhi	18:6a4db94011d3	152	2) by calling HAL API function HAL_RCC_GetHCLKFreq()
sahilmgandhi	18:6a4db94011d3	153	3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
sahilmgandhi	18:6a4db94011d3	154	Note: If you use this function to configure the system clock; then there
sahilmgandhi	18:6a4db94011d3	155	is no need to call the 2 first functions listed above, since SystemCoreClock
sahilmgandhi	18:6a4db94011d3	156	variable is updated automatically.
sahilmgandhi	18:6a4db94011d3	157	*/
sahilmgandhi	18:6a4db94011d3	158	uint32_t SystemCoreClock = 168000000; /* [CHANGED FOR MBED] */
sahilmgandhi	18:6a4db94011d3	159	const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
sahilmgandhi	18:6a4db94011d3	160
sahilmgandhi	18:6a4db94011d3	161	/**
sahilmgandhi	18:6a4db94011d3	162	* @}
sahilmgandhi	18:6a4db94011d3	163	*/
sahilmgandhi	18:6a4db94011d3	164
sahilmgandhi	18:6a4db94011d3	165	/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
sahilmgandhi	18:6a4db94011d3	166	* @{
sahilmgandhi	18:6a4db94011d3	167	*/
sahilmgandhi	18:6a4db94011d3	168
sahilmgandhi	18:6a4db94011d3	169	#if defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
sahilmgandhi	18:6a4db94011d3	170	static void SystemInit_ExtMemCtl(void);
sahilmgandhi	18:6a4db94011d3	171	#endif /* DATA_IN_ExtSRAM \|\| DATA_IN_ExtSDRAM */
sahilmgandhi	18:6a4db94011d3	172
sahilmgandhi	18:6a4db94011d3	173	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
sahilmgandhi	18:6a4db94011d3	174	uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
sahilmgandhi	18:6a4db94011d3	175	#endif
sahilmgandhi	18:6a4db94011d3	176
sahilmgandhi	18:6a4db94011d3	177	uint8_t SetSysClock_PLL_HSI(void);
sahilmgandhi	18:6a4db94011d3	178
sahilmgandhi	18:6a4db94011d3	179	/**
sahilmgandhi	18:6a4db94011d3	180	* @}
sahilmgandhi	18:6a4db94011d3	181	*/
sahilmgandhi	18:6a4db94011d3	182
sahilmgandhi	18:6a4db94011d3	183	/** @addtogroup STM32F4xx_System_Private_Functions
sahilmgandhi	18:6a4db94011d3	184	* @{
sahilmgandhi	18:6a4db94011d3	185	*/
sahilmgandhi	18:6a4db94011d3	186
sahilmgandhi	18:6a4db94011d3	187	/**
sahilmgandhi	18:6a4db94011d3	188	* @brief Setup the microcontroller system
sahilmgandhi	18:6a4db94011d3	189	* Initialize the FPU setting, vector table location and External memory
sahilmgandhi	18:6a4db94011d3	190	* configuration.
sahilmgandhi	18:6a4db94011d3	191	* @param None
sahilmgandhi	18:6a4db94011d3	192	* @retval None
sahilmgandhi	18:6a4db94011d3	193	*/
sahilmgandhi	18:6a4db94011d3	194	void SystemInit(void)
sahilmgandhi	18:6a4db94011d3	195	{
sahilmgandhi	18:6a4db94011d3	196	/* FPU settings ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	197	#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
sahilmgandhi	18:6a4db94011d3	198	SCB->CPACR \|= ((3UL << 102)\|(3UL << 112)); /* set CP10 and CP11 Full Access */
sahilmgandhi	18:6a4db94011d3	199	#endif
sahilmgandhi	18:6a4db94011d3	200	/* Reset the RCC clock configuration to the default reset state ------------*/
sahilmgandhi	18:6a4db94011d3	201	/* Set HSION bit */
sahilmgandhi	18:6a4db94011d3	202	RCC->CR \|= (uint32_t)0x00000001;
sahilmgandhi	18:6a4db94011d3	203
sahilmgandhi	18:6a4db94011d3	204	/* Reset CFGR register */
sahilmgandhi	18:6a4db94011d3	205	RCC->CFGR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	206
sahilmgandhi	18:6a4db94011d3	207	/* Reset HSEON, CSSON and PLLON bits */
sahilmgandhi	18:6a4db94011d3	208	RCC->CR &= (uint32_t)0xFEF6FFFF;
sahilmgandhi	18:6a4db94011d3	209
sahilmgandhi	18:6a4db94011d3	210	/* Reset PLLCFGR register */
sahilmgandhi	18:6a4db94011d3	211	RCC->PLLCFGR = 0x24003010;
sahilmgandhi	18:6a4db94011d3	212
sahilmgandhi	18:6a4db94011d3	213	/* Reset HSEBYP bit */
sahilmgandhi	18:6a4db94011d3	214	RCC->CR &= (uint32_t)0xFFFBFFFF;
sahilmgandhi	18:6a4db94011d3	215
sahilmgandhi	18:6a4db94011d3	216	/* Disable all interrupts */
sahilmgandhi	18:6a4db94011d3	217	RCC->CIR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	218
sahilmgandhi	18:6a4db94011d3	219	#if defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
sahilmgandhi	18:6a4db94011d3	220	SystemInit_ExtMemCtl();
sahilmgandhi	18:6a4db94011d3	221	#endif /* DATA_IN_ExtSRAM \|\| DATA_IN_ExtSDRAM */
sahilmgandhi	18:6a4db94011d3	222
sahilmgandhi	18:6a4db94011d3	223	/* Configure the Vector Table location add offset address ------------------*/
sahilmgandhi	18:6a4db94011d3	224	#ifdef VECT_TAB_SRAM
sahilmgandhi	18:6a4db94011d3	225	SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
sahilmgandhi	18:6a4db94011d3	226	#else
sahilmgandhi	18:6a4db94011d3	227	SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
sahilmgandhi	18:6a4db94011d3	228	#endif
sahilmgandhi	18:6a4db94011d3	229
sahilmgandhi	18:6a4db94011d3	230	/* Configure the Cube driver */
sahilmgandhi	18:6a4db94011d3	231	SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
sahilmgandhi	18:6a4db94011d3	232	HAL_Init();
sahilmgandhi	18:6a4db94011d3	233
sahilmgandhi	18:6a4db94011d3	234	/* Configure the System clock source, PLL Multiplier and Divider factors,
sahilmgandhi	18:6a4db94011d3	235	AHB/APBx prescalers and Flash settings */
sahilmgandhi	18:6a4db94011d3	236	SetSysClock();
sahilmgandhi	18:6a4db94011d3	237	SystemCoreClockUpdate();
sahilmgandhi	18:6a4db94011d3	238
sahilmgandhi	18:6a4db94011d3	239	/* Reset the timer to avoid issues after the RAM initialization */
sahilmgandhi	18:6a4db94011d3	240	TIM_MST_RESET_ON;
sahilmgandhi	18:6a4db94011d3	241	TIM_MST_RESET_OFF;
sahilmgandhi	18:6a4db94011d3	242	}
sahilmgandhi	18:6a4db94011d3	243
sahilmgandhi	18:6a4db94011d3	244	/**
sahilmgandhi	18:6a4db94011d3	245	* @brief Update SystemCoreClock variable according to Clock Register Values.
sahilmgandhi	18:6a4db94011d3	246	* The SystemCoreClock variable contains the core clock (HCLK), it can
sahilmgandhi	18:6a4db94011d3	247	* be used by the user application to setup the SysTick timer or configure
sahilmgandhi	18:6a4db94011d3	248	* other parameters.
sahilmgandhi	18:6a4db94011d3	249	*
sahilmgandhi	18:6a4db94011d3	250	* @note Each time the core clock (HCLK) changes, this function must be called
sahilmgandhi	18:6a4db94011d3	251	* to update SystemCoreClock variable value. Otherwise, any configuration
sahilmgandhi	18:6a4db94011d3	252	* based on this variable will be incorrect.
sahilmgandhi	18:6a4db94011d3	253	*
sahilmgandhi	18:6a4db94011d3	254	* @note - The system frequency computed by this function is not the real
sahilmgandhi	18:6a4db94011d3	255	* frequency in the chip. It is calculated based on the predefined
sahilmgandhi	18:6a4db94011d3	256	* constant and the selected clock source:
sahilmgandhi	18:6a4db94011d3	257	*
sahilmgandhi	18:6a4db94011d3	258	* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
sahilmgandhi	18:6a4db94011d3	259	*
sahilmgandhi	18:6a4db94011d3	260	* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
sahilmgandhi	18:6a4db94011d3	261	*
sahilmgandhi	18:6a4db94011d3	262	* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
sahilmgandhi	18:6a4db94011d3	263	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
sahilmgandhi	18:6a4db94011d3	264	*
sahilmgandhi	18:6a4db94011d3	265	* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
sahilmgandhi	18:6a4db94011d3	266	* 16 MHz) but the real value may vary depending on the variations
sahilmgandhi	18:6a4db94011d3	267	* in voltage and temperature.
sahilmgandhi	18:6a4db94011d3	268	*
sahilmgandhi	18:6a4db94011d3	269	* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
sahilmgandhi	18:6a4db94011d3	270	* depends on the application requirements), user has to ensure that HSE_VALUE
sahilmgandhi	18:6a4db94011d3	271	* is same as the real frequency of the crystal used. Otherwise, this function
sahilmgandhi	18:6a4db94011d3	272	* may have wrong result.
sahilmgandhi	18:6a4db94011d3	273	*
sahilmgandhi	18:6a4db94011d3	274	* - The result of this function could be not correct when using fractional
sahilmgandhi	18:6a4db94011d3	275	* value for HSE crystal.
sahilmgandhi	18:6a4db94011d3	276	*
sahilmgandhi	18:6a4db94011d3	277	* @param None
sahilmgandhi	18:6a4db94011d3	278	* @retval None
sahilmgandhi	18:6a4db94011d3	279	*/
sahilmgandhi	18:6a4db94011d3	280	void SystemCoreClockUpdate(void)
sahilmgandhi	18:6a4db94011d3	281	{
sahilmgandhi	18:6a4db94011d3	282	uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
sahilmgandhi	18:6a4db94011d3	283
sahilmgandhi	18:6a4db94011d3	284	/* Get SYSCLK source -------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	285	tmp = RCC->CFGR & RCC_CFGR_SWS;
sahilmgandhi	18:6a4db94011d3	286
sahilmgandhi	18:6a4db94011d3	287	switch (tmp)
sahilmgandhi	18:6a4db94011d3	288	{
sahilmgandhi	18:6a4db94011d3	289	case 0x00: /* HSI used as system clock source */
sahilmgandhi	18:6a4db94011d3	290	SystemCoreClock = HSI_VALUE;
sahilmgandhi	18:6a4db94011d3	291	break;
sahilmgandhi	18:6a4db94011d3	292	case 0x04: /* HSE used as system clock source */
sahilmgandhi	18:6a4db94011d3	293	SystemCoreClock = HSE_VALUE;
sahilmgandhi	18:6a4db94011d3	294	break;
sahilmgandhi	18:6a4db94011d3	295	case 0x08: /* PLL used as system clock source */
sahilmgandhi	18:6a4db94011d3	296
sahilmgandhi	18:6a4db94011d3	297	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
sahilmgandhi	18:6a4db94011d3	298	SYSCLK = PLL_VCO / PLL_P
sahilmgandhi	18:6a4db94011d3	299	*/
sahilmgandhi	18:6a4db94011d3	300	pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
sahilmgandhi	18:6a4db94011d3	301	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
sahilmgandhi	18:6a4db94011d3	302
sahilmgandhi	18:6a4db94011d3	303	if (pllsource != 0)
sahilmgandhi	18:6a4db94011d3	304	{
sahilmgandhi	18:6a4db94011d3	305	/* HSE used as PLL clock source */
sahilmgandhi	18:6a4db94011d3	306	pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
sahilmgandhi	18:6a4db94011d3	307	}
sahilmgandhi	18:6a4db94011d3	308	else
sahilmgandhi	18:6a4db94011d3	309	{
sahilmgandhi	18:6a4db94011d3	310	/* HSI used as PLL clock source */
sahilmgandhi	18:6a4db94011d3	311	pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
sahilmgandhi	18:6a4db94011d3	312	}
sahilmgandhi	18:6a4db94011d3	313
sahilmgandhi	18:6a4db94011d3	314	pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
sahilmgandhi	18:6a4db94011d3	315	SystemCoreClock = pllvco/pllp;
sahilmgandhi	18:6a4db94011d3	316	break;
sahilmgandhi	18:6a4db94011d3	317	default:
sahilmgandhi	18:6a4db94011d3	318	SystemCoreClock = HSI_VALUE;
sahilmgandhi	18:6a4db94011d3	319	break;
sahilmgandhi	18:6a4db94011d3	320	}
sahilmgandhi	18:6a4db94011d3	321	/* Compute HCLK frequency --------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	322	/* Get HCLK prescaler */
sahilmgandhi	18:6a4db94011d3	323	tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
sahilmgandhi	18:6a4db94011d3	324	/* HCLK frequency */
sahilmgandhi	18:6a4db94011d3	325	SystemCoreClock >>= tmp;
sahilmgandhi	18:6a4db94011d3	326	}
sahilmgandhi	18:6a4db94011d3	327
sahilmgandhi	18:6a4db94011d3	328	#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
sahilmgandhi	18:6a4db94011d3	329	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
sahilmgandhi	18:6a4db94011d3	330	defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	331	/**
sahilmgandhi	18:6a4db94011d3	332	* @brief Setup the external memory controller.
sahilmgandhi	18:6a4db94011d3	333	* Called in startup_stm32f4xx.s before jump to main.
sahilmgandhi	18:6a4db94011d3	334	* This function configures the external memories (SRAM/SDRAM)
sahilmgandhi	18:6a4db94011d3	335	* This SRAM/SDRAM will be used as program data memory (including heap and stack).
sahilmgandhi	18:6a4db94011d3	336	* @param None
sahilmgandhi	18:6a4db94011d3	337	* @retval None
sahilmgandhi	18:6a4db94011d3	338	*/
sahilmgandhi	18:6a4db94011d3	339	void SystemInit_ExtMemCtl(void)
sahilmgandhi	18:6a4db94011d3	340	{
sahilmgandhi	18:6a4db94011d3	341	__IO uint32_t tmp = 0x00;
sahilmgandhi	18:6a4db94011d3	342
sahilmgandhi	18:6a4db94011d3	343	register uint32_t tmpreg = 0, timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	344	register __IO uint32_t index;
sahilmgandhi	18:6a4db94011d3	345
sahilmgandhi	18:6a4db94011d3	346	/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
sahilmgandhi	18:6a4db94011d3	347	RCC->AHB1ENR \|= 0x000001F8;
sahilmgandhi	18:6a4db94011d3	348
sahilmgandhi	18:6a4db94011d3	349	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	350	tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
sahilmgandhi	18:6a4db94011d3	351
sahilmgandhi	18:6a4db94011d3	352	/* Connect PDx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	353	GPIOD->AFR[0] = 0x00CCC0CC;
sahilmgandhi	18:6a4db94011d3	354	GPIOD->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	355	/* Configure PDx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	356	GPIOD->MODER = 0xAAAA0A8A;
sahilmgandhi	18:6a4db94011d3	357	/* Configure PDx pins speed to 100 MHz */
sahilmgandhi	18:6a4db94011d3	358	GPIOD->OSPEEDR = 0xFFFF0FCF;
sahilmgandhi	18:6a4db94011d3	359	/* Configure PDx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	360	GPIOD->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	361	/* No pull-up, pull-down for PDx pins */
sahilmgandhi	18:6a4db94011d3	362	GPIOD->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	363
sahilmgandhi	18:6a4db94011d3	364	/* Connect PEx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	365	GPIOE->AFR[0] = 0xC00CC0CC;
sahilmgandhi	18:6a4db94011d3	366	GPIOE->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	367	/* Configure PEx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	368	GPIOE->MODER = 0xAAAA828A;
sahilmgandhi	18:6a4db94011d3	369	/* Configure PEx pins speed to 100 MHz */
sahilmgandhi	18:6a4db94011d3	370	GPIOE->OSPEEDR = 0xFFFFC3CF;
sahilmgandhi	18:6a4db94011d3	371	/* Configure PEx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	372	GPIOE->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	373	/* No pull-up, pull-down for PEx pins */
sahilmgandhi	18:6a4db94011d3	374	GPIOE->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	375
sahilmgandhi	18:6a4db94011d3	376	/* Connect PFx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	377	GPIOF->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	378	GPIOF->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	379	/* Configure PFx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	380	GPIOF->MODER = 0xAA800AAA;
sahilmgandhi	18:6a4db94011d3	381	/* Configure PFx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	382	GPIOF->OSPEEDR = 0xAA800AAA;
sahilmgandhi	18:6a4db94011d3	383	/* Configure PFx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	384	GPIOF->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	385	/* No pull-up, pull-down for PFx pins */
sahilmgandhi	18:6a4db94011d3	386	GPIOF->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	387
sahilmgandhi	18:6a4db94011d3	388	/* Connect PGx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	389	GPIOG->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	390	GPIOG->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	391	/* Configure PGx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	392	GPIOG->MODER = 0xAAAAAAAA;
sahilmgandhi	18:6a4db94011d3	393	/* Configure PGx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	394	GPIOG->OSPEEDR = 0xAAAAAAAA;
sahilmgandhi	18:6a4db94011d3	395	/* Configure PGx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	396	GPIOG->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	397	/* No pull-up, pull-down for PGx pins */
sahilmgandhi	18:6a4db94011d3	398	GPIOG->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	399
sahilmgandhi	18:6a4db94011d3	400	/* Connect PHx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	401	GPIOH->AFR[0] = 0x00C0CC00;
sahilmgandhi	18:6a4db94011d3	402	GPIOH->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	403	/* Configure PHx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	404	GPIOH->MODER = 0xAAAA08A0;
sahilmgandhi	18:6a4db94011d3	405	/* Configure PHx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	406	GPIOH->OSPEEDR = 0xAAAA08A0;
sahilmgandhi	18:6a4db94011d3	407	/* Configure PHx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	408	GPIOH->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	409	/* No pull-up, pull-down for PHx pins */
sahilmgandhi	18:6a4db94011d3	410	GPIOH->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	411
sahilmgandhi	18:6a4db94011d3	412	/* Connect PIx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	413	GPIOI->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	414	GPIOI->AFR[1] = 0x00000CC0;
sahilmgandhi	18:6a4db94011d3	415	/* Configure PIx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	416	GPIOI->MODER = 0x0028AAAA;
sahilmgandhi	18:6a4db94011d3	417	/* Configure PIx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	418	GPIOI->OSPEEDR = 0x0028AAAA;
sahilmgandhi	18:6a4db94011d3	419	/* Configure PIx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	420	GPIOI->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	421	/* No pull-up, pull-down for PIx pins */
sahilmgandhi	18:6a4db94011d3	422	GPIOI->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	423
sahilmgandhi	18:6a4db94011d3	424	/-- FMC Configuration -------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	425	/* Enable the FMC interface clock */
sahilmgandhi	18:6a4db94011d3	426	RCC->AHB3ENR \|= 0x00000001;
sahilmgandhi	18:6a4db94011d3	427	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	428	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
sahilmgandhi	18:6a4db94011d3	429
sahilmgandhi	18:6a4db94011d3	430	FMC_Bank5_6->SDCR[0] = 0x000019E4;
sahilmgandhi	18:6a4db94011d3	431	FMC_Bank5_6->SDTR[0] = 0x01115351;
sahilmgandhi	18:6a4db94011d3	432
sahilmgandhi	18:6a4db94011d3	433	/* SDRAM initialization sequence */
sahilmgandhi	18:6a4db94011d3	434	/* Clock enable command */
sahilmgandhi	18:6a4db94011d3	435	FMC_Bank5_6->SDCMR = 0x00000011;
sahilmgandhi	18:6a4db94011d3	436	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	437	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	438	{
sahilmgandhi	18:6a4db94011d3	439	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	440	}
sahilmgandhi	18:6a4db94011d3	441
sahilmgandhi	18:6a4db94011d3	442	/* Delay */
sahilmgandhi	18:6a4db94011d3	443	for (index = 0; index<1000; index++);
sahilmgandhi	18:6a4db94011d3	444
sahilmgandhi	18:6a4db94011d3	445	/* PALL command */
sahilmgandhi	18:6a4db94011d3	446	FMC_Bank5_6->SDCMR = 0x00000012;
sahilmgandhi	18:6a4db94011d3	447	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	448	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	449	{
sahilmgandhi	18:6a4db94011d3	450	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	451	}
sahilmgandhi	18:6a4db94011d3	452
sahilmgandhi	18:6a4db94011d3	453	/* Auto refresh command */
sahilmgandhi	18:6a4db94011d3	454	FMC_Bank5_6->SDCMR = 0x00000073;
sahilmgandhi	18:6a4db94011d3	455	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	456	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	457	{
sahilmgandhi	18:6a4db94011d3	458	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	459	}
sahilmgandhi	18:6a4db94011d3	460
sahilmgandhi	18:6a4db94011d3	461	/* MRD register program */
sahilmgandhi	18:6a4db94011d3	462	FMC_Bank5_6->SDCMR = 0x00046014;
sahilmgandhi	18:6a4db94011d3	463	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	464	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	465	{
sahilmgandhi	18:6a4db94011d3	466	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	467	}
sahilmgandhi	18:6a4db94011d3	468
sahilmgandhi	18:6a4db94011d3	469	/* Set refresh count */
sahilmgandhi	18:6a4db94011d3	470	tmpreg = FMC_Bank5_6->SDRTR;
sahilmgandhi	18:6a4db94011d3	471	FMC_Bank5_6->SDRTR = (tmpreg \| (0x0000027C<<1));
sahilmgandhi	18:6a4db94011d3	472
sahilmgandhi	18:6a4db94011d3	473	/* Disable write protection */
sahilmgandhi	18:6a4db94011d3	474	tmpreg = FMC_Bank5_6->SDCR[0];
sahilmgandhi	18:6a4db94011d3	475	FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
sahilmgandhi	18:6a4db94011d3	476
sahilmgandhi	18:6a4db94011d3	477	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
sahilmgandhi	18:6a4db94011d3	478	/* Configure and enable Bank1_SRAM2 */
sahilmgandhi	18:6a4db94011d3	479	FMC_Bank1->BTCR[2] = 0x00001011;
sahilmgandhi	18:6a4db94011d3	480	FMC_Bank1->BTCR[3] = 0x00000201;
sahilmgandhi	18:6a4db94011d3	481	FMC_Bank1E->BWTR[2] = 0x0fffffff;
sahilmgandhi	18:6a4db94011d3	482	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
sahilmgandhi	18:6a4db94011d3	483	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	484	/* Configure and enable Bank1_SRAM2 */
sahilmgandhi	18:6a4db94011d3	485	FMC_Bank1->BTCR[2] = 0x00001091;
sahilmgandhi	18:6a4db94011d3	486	FMC_Bank1->BTCR[3] = 0x00110212;
sahilmgandhi	18:6a4db94011d3	487	FMC_Bank1E->BWTR[2] = 0x0fffffff;
sahilmgandhi	18:6a4db94011d3	488	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	489
sahilmgandhi	18:6a4db94011d3	490	(void)(tmp);
sahilmgandhi	18:6a4db94011d3	491	}
sahilmgandhi	18:6a4db94011d3	492	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	493	#elif defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
sahilmgandhi	18:6a4db94011d3	494	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
sahilmgandhi	18:6a4db94011d3	495	defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	496	/**
sahilmgandhi	18:6a4db94011d3	497	* @brief Setup the external memory controller.
sahilmgandhi	18:6a4db94011d3	498	* Called in startup_stm32f4xx.s before jump to main.
sahilmgandhi	18:6a4db94011d3	499	* This function configures the external memories (SRAM/SDRAM)
sahilmgandhi	18:6a4db94011d3	500	* This SRAM/SDRAM will be used as program data memory (including heap and stack).
sahilmgandhi	18:6a4db94011d3	501	* @param None
sahilmgandhi	18:6a4db94011d3	502	* @retval None
sahilmgandhi	18:6a4db94011d3	503	*/
sahilmgandhi	18:6a4db94011d3	504	void SystemInit_ExtMemCtl(void)
sahilmgandhi	18:6a4db94011d3	505	{
sahilmgandhi	18:6a4db94011d3	506	__IO uint32_t tmp = 0x00;
sahilmgandhi	18:6a4db94011d3	507
sahilmgandhi	18:6a4db94011d3	508	register uint32_t tmpreg = 0, timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	509	register __IO uint32_t index;
sahilmgandhi	18:6a4db94011d3	510
sahilmgandhi	18:6a4db94011d3	511	/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
sahilmgandhi	18:6a4db94011d3	512	RCC->AHB1ENR \|= 0x000001F8;
sahilmgandhi	18:6a4db94011d3	513
sahilmgandhi	18:6a4db94011d3	514	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	515	tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
sahilmgandhi	18:6a4db94011d3	516
sahilmgandhi	18:6a4db94011d3	517	/* Connect PDx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	518	GPIOD->AFR[0] = 0x00CCC0CC;
sahilmgandhi	18:6a4db94011d3	519	GPIOD->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	520	/* Configure PDx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	521	GPIOD->MODER = 0xAAAA0A8A;
sahilmgandhi	18:6a4db94011d3	522	/* Configure PDx pins speed to 100 MHz */
sahilmgandhi	18:6a4db94011d3	523	GPIOD->OSPEEDR = 0xFFFF0FCF;
sahilmgandhi	18:6a4db94011d3	524	/* Configure PDx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	525	GPIOD->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	526	/* No pull-up, pull-down for PDx pins */
sahilmgandhi	18:6a4db94011d3	527	GPIOD->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	528
sahilmgandhi	18:6a4db94011d3	529	/* Connect PEx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	530	GPIOE->AFR[0] = 0xC00CC0CC;
sahilmgandhi	18:6a4db94011d3	531	GPIOE->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	532	/* Configure PEx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	533	GPIOE->MODER = 0xAAAA828A;
sahilmgandhi	18:6a4db94011d3	534	/* Configure PEx pins speed to 100 MHz */
sahilmgandhi	18:6a4db94011d3	535	GPIOE->OSPEEDR = 0xFFFFC3CF;
sahilmgandhi	18:6a4db94011d3	536	/* Configure PEx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	537	GPIOE->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	538	/* No pull-up, pull-down for PEx pins */
sahilmgandhi	18:6a4db94011d3	539	GPIOE->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	540
sahilmgandhi	18:6a4db94011d3	541	/* Connect PFx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	542	GPIOF->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	543	GPIOF->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	544	/* Configure PFx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	545	GPIOF->MODER = 0xAA800AAA;
sahilmgandhi	18:6a4db94011d3	546	/* Configure PFx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	547	GPIOF->OSPEEDR = 0xAA800AAA;
sahilmgandhi	18:6a4db94011d3	548	/* Configure PFx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	549	GPIOF->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	550	/* No pull-up, pull-down for PFx pins */
sahilmgandhi	18:6a4db94011d3	551	GPIOF->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	552
sahilmgandhi	18:6a4db94011d3	553	/* Connect PGx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	554	GPIOG->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	555	GPIOG->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	556	/* Configure PGx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	557	GPIOG->MODER = 0xAAAAAAAA;
sahilmgandhi	18:6a4db94011d3	558	/* Configure PGx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	559	GPIOG->OSPEEDR = 0xAAAAAAAA;
sahilmgandhi	18:6a4db94011d3	560	/* Configure PGx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	561	GPIOG->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	562	/* No pull-up, pull-down for PGx pins */
sahilmgandhi	18:6a4db94011d3	563	GPIOG->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	564
sahilmgandhi	18:6a4db94011d3	565	/* Connect PHx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	566	GPIOH->AFR[0] = 0x00C0CC00;
sahilmgandhi	18:6a4db94011d3	567	GPIOH->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	568	/* Configure PHx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	569	GPIOH->MODER = 0xAAAA08A0;
sahilmgandhi	18:6a4db94011d3	570	/* Configure PHx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	571	GPIOH->OSPEEDR = 0xAAAA08A0;
sahilmgandhi	18:6a4db94011d3	572	/* Configure PHx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	573	GPIOH->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	574	/* No pull-up, pull-down for PHx pins */
sahilmgandhi	18:6a4db94011d3	575	GPIOH->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	576
sahilmgandhi	18:6a4db94011d3	577	/* Connect PIx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	578	GPIOI->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	579	GPIOI->AFR[1] = 0x00000CC0;
sahilmgandhi	18:6a4db94011d3	580	/* Configure PIx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	581	GPIOI->MODER = 0x0028AAAA;
sahilmgandhi	18:6a4db94011d3	582	/* Configure PIx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	583	GPIOI->OSPEEDR = 0x0028AAAA;
sahilmgandhi	18:6a4db94011d3	584	/* Configure PIx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	585	GPIOI->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	586	/* No pull-up, pull-down for PIx pins */
sahilmgandhi	18:6a4db94011d3	587	GPIOI->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	588
sahilmgandhi	18:6a4db94011d3	589	/-- FMC Configuration -------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	590	/* Enable the FMC interface clock */
sahilmgandhi	18:6a4db94011d3	591	RCC->AHB3ENR \|= 0x00000001;
sahilmgandhi	18:6a4db94011d3	592	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	593	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
sahilmgandhi	18:6a4db94011d3	594
sahilmgandhi	18:6a4db94011d3	595	FMC_Bank5_6->SDCR[0] = 0x000019E4;
sahilmgandhi	18:6a4db94011d3	596	FMC_Bank5_6->SDTR[0] = 0x01115351;
sahilmgandhi	18:6a4db94011d3	597
sahilmgandhi	18:6a4db94011d3	598	/* SDRAM initialization sequence */
sahilmgandhi	18:6a4db94011d3	599	/* Clock enable command */
sahilmgandhi	18:6a4db94011d3	600	FMC_Bank5_6->SDCMR = 0x00000011;
sahilmgandhi	18:6a4db94011d3	601	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	602	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	603	{
sahilmgandhi	18:6a4db94011d3	604	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	605	}
sahilmgandhi	18:6a4db94011d3	606
sahilmgandhi	18:6a4db94011d3	607	/* Delay */
sahilmgandhi	18:6a4db94011d3	608	for (index = 0; index<1000; index++);
sahilmgandhi	18:6a4db94011d3	609
sahilmgandhi	18:6a4db94011d3	610	/* PALL command */
sahilmgandhi	18:6a4db94011d3	611	FMC_Bank5_6->SDCMR = 0x00000012;
sahilmgandhi	18:6a4db94011d3	612	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	613	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	614	{
sahilmgandhi	18:6a4db94011d3	615	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	616	}
sahilmgandhi	18:6a4db94011d3	617
sahilmgandhi	18:6a4db94011d3	618	/* Auto refresh command */
sahilmgandhi	18:6a4db94011d3	619	FMC_Bank5_6->SDCMR = 0x00000073;
sahilmgandhi	18:6a4db94011d3	620	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	621	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	622	{
sahilmgandhi	18:6a4db94011d3	623	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	624	}
sahilmgandhi	18:6a4db94011d3	625
sahilmgandhi	18:6a4db94011d3	626	/* MRD register program */
sahilmgandhi	18:6a4db94011d3	627	FMC_Bank5_6->SDCMR = 0x00046014;
sahilmgandhi	18:6a4db94011d3	628	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	629	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	630	{
sahilmgandhi	18:6a4db94011d3	631	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	632	}
sahilmgandhi	18:6a4db94011d3	633
sahilmgandhi	18:6a4db94011d3	634	/* Set refresh count */
sahilmgandhi	18:6a4db94011d3	635	tmpreg = FMC_Bank5_6->SDRTR;
sahilmgandhi	18:6a4db94011d3	636	FMC_Bank5_6->SDRTR = (tmpreg \| (0x0000027C<<1));
sahilmgandhi	18:6a4db94011d3	637
sahilmgandhi	18:6a4db94011d3	638	/* Disable write protection */
sahilmgandhi	18:6a4db94011d3	639	tmpreg = FMC_Bank5_6->SDCR[0];
sahilmgandhi	18:6a4db94011d3	640	FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
sahilmgandhi	18:6a4db94011d3	641
sahilmgandhi	18:6a4db94011d3	642	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
sahilmgandhi	18:6a4db94011d3	643	/* Configure and enable Bank1_SRAM2 */
sahilmgandhi	18:6a4db94011d3	644	FMC_Bank1->BTCR[2] = 0x00001011;
sahilmgandhi	18:6a4db94011d3	645	FMC_Bank1->BTCR[3] = 0x00000201;
sahilmgandhi	18:6a4db94011d3	646	FMC_Bank1E->BWTR[2] = 0x0fffffff;
sahilmgandhi	18:6a4db94011d3	647	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
sahilmgandhi	18:6a4db94011d3	648	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	649	/* Configure and enable Bank1_SRAM2 */
sahilmgandhi	18:6a4db94011d3	650	FMC_Bank1->BTCR[2] = 0x00001091;
sahilmgandhi	18:6a4db94011d3	651	FMC_Bank1->BTCR[3] = 0x00110212;
sahilmgandhi	18:6a4db94011d3	652	FMC_Bank1E->BWTR[2] = 0x0fffffff;
sahilmgandhi	18:6a4db94011d3	653	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	654
sahilmgandhi	18:6a4db94011d3	655	(void)(tmp);
sahilmgandhi	18:6a4db94011d3	656	}
sahilmgandhi	18:6a4db94011d3	657	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	658	#elif defined (DATA_IN_ExtSRAM) \|\| defined (DATA_IN_ExtSDRAM)
sahilmgandhi	18:6a4db94011d3	659	/**
sahilmgandhi	18:6a4db94011d3	660	* @brief Setup the external memory controller.
sahilmgandhi	18:6a4db94011d3	661	* Called in startup_stm32f4xx.s before jump to main.
sahilmgandhi	18:6a4db94011d3	662	* This function configures the external memories (SRAM/SDRAM)
sahilmgandhi	18:6a4db94011d3	663	* This SRAM/SDRAM will be used as program data memory (including heap and stack).
sahilmgandhi	18:6a4db94011d3	664	* @param None
sahilmgandhi	18:6a4db94011d3	665	* @retval None
sahilmgandhi	18:6a4db94011d3	666	*/
sahilmgandhi	18:6a4db94011d3	667	void SystemInit_ExtMemCtl(void)
sahilmgandhi	18:6a4db94011d3	668	{
sahilmgandhi	18:6a4db94011d3	669	__IO uint32_t tmp = 0x00;
sahilmgandhi	18:6a4db94011d3	670	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)\
sahilmgandhi	18:6a4db94011d3	671	\|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	672	#if defined (DATA_IN_ExtSDRAM)
sahilmgandhi	18:6a4db94011d3	673	register uint32_t tmpreg = 0, timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	674	register __IO uint32_t index;
sahilmgandhi	18:6a4db94011d3	675
sahilmgandhi	18:6a4db94011d3	676	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	677	/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
sahilmgandhi	18:6a4db94011d3	678	clock */
sahilmgandhi	18:6a4db94011d3	679	RCC->AHB1ENR \|= 0x0000007D;
sahilmgandhi	18:6a4db94011d3	680	#else
sahilmgandhi	18:6a4db94011d3	681	/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
sahilmgandhi	18:6a4db94011d3	682	clock */
sahilmgandhi	18:6a4db94011d3	683	RCC->AHB1ENR \|= 0x000001F8;
sahilmgandhi	18:6a4db94011d3	684	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	685	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	686	tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
sahilmgandhi	18:6a4db94011d3	687
sahilmgandhi	18:6a4db94011d3	688	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	689	/* Connect PAx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	690	GPIOA->AFR[0] \|= 0xC0000000;
sahilmgandhi	18:6a4db94011d3	691	GPIOA->AFR[1] \|= 0x00000000;
sahilmgandhi	18:6a4db94011d3	692	/* Configure PDx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	693	GPIOA->MODER \|= 0x00008000;
sahilmgandhi	18:6a4db94011d3	694	/* Configure PDx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	695	GPIOA->OSPEEDR \|= 0x00008000;
sahilmgandhi	18:6a4db94011d3	696	/* Configure PDx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	697	GPIOA->OTYPER \|= 0x00000000;
sahilmgandhi	18:6a4db94011d3	698	/* No pull-up, pull-down for PDx pins */
sahilmgandhi	18:6a4db94011d3	699	GPIOA->PUPDR \|= 0x00000000;
sahilmgandhi	18:6a4db94011d3	700
sahilmgandhi	18:6a4db94011d3	701	/* Connect PCx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	702	GPIOC->AFR[0] \|= 0x00CC0000;
sahilmgandhi	18:6a4db94011d3	703	GPIOC->AFR[1] \|= 0x00000000;
sahilmgandhi	18:6a4db94011d3	704	/* Configure PDx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	705	GPIOC->MODER \|= 0x00000A00;
sahilmgandhi	18:6a4db94011d3	706	/* Configure PDx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	707	GPIOC->OSPEEDR \|= 0x00000A00;
sahilmgandhi	18:6a4db94011d3	708	/* Configure PDx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	709	GPIOC->OTYPER \|= 0x00000000;
sahilmgandhi	18:6a4db94011d3	710	/* No pull-up, pull-down for PDx pins */
sahilmgandhi	18:6a4db94011d3	711	GPIOC->PUPDR \|= 0x00000000;
sahilmgandhi	18:6a4db94011d3	712	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	713
sahilmgandhi	18:6a4db94011d3	714	/* Connect PDx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	715	GPIOD->AFR[0] = 0x000000CC;
sahilmgandhi	18:6a4db94011d3	716	GPIOD->AFR[1] = 0xCC000CCC;
sahilmgandhi	18:6a4db94011d3	717	/* Configure PDx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	718	GPIOD->MODER = 0xA02A000A;
sahilmgandhi	18:6a4db94011d3	719	/* Configure PDx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	720	GPIOD->OSPEEDR = 0xA02A000A;
sahilmgandhi	18:6a4db94011d3	721	/* Configure PDx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	722	GPIOD->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	723	/* No pull-up, pull-down for PDx pins */
sahilmgandhi	18:6a4db94011d3	724	GPIOD->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	725
sahilmgandhi	18:6a4db94011d3	726	/* Connect PEx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	727	GPIOE->AFR[0] = 0xC00000CC;
sahilmgandhi	18:6a4db94011d3	728	GPIOE->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	729	/* Configure PEx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	730	GPIOE->MODER = 0xAAAA800A;
sahilmgandhi	18:6a4db94011d3	731	/* Configure PEx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	732	GPIOE->OSPEEDR = 0xAAAA800A;
sahilmgandhi	18:6a4db94011d3	733	/* Configure PEx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	734	GPIOE->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	735	/* No pull-up, pull-down for PEx pins */
sahilmgandhi	18:6a4db94011d3	736	GPIOE->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	737
sahilmgandhi	18:6a4db94011d3	738	/* Connect PFx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	739	GPIOF->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	740	GPIOF->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	741	/* Configure PFx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	742	GPIOF->MODER = 0xAA800AAA;
sahilmgandhi	18:6a4db94011d3	743	/* Configure PFx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	744	GPIOF->OSPEEDR = 0xAA800AAA;
sahilmgandhi	18:6a4db94011d3	745	/* Configure PFx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	746	GPIOF->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	747	/* No pull-up, pull-down for PFx pins */
sahilmgandhi	18:6a4db94011d3	748	GPIOF->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	749
sahilmgandhi	18:6a4db94011d3	750	/* Connect PGx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	751	GPIOG->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	752	GPIOG->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	753	/* Configure PGx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	754	GPIOG->MODER = 0xAAAAAAAA;
sahilmgandhi	18:6a4db94011d3	755	/* Configure PGx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	756	GPIOG->OSPEEDR = 0xAAAAAAAA;
sahilmgandhi	18:6a4db94011d3	757	/* Configure PGx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	758	GPIOG->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	759	/* No pull-up, pull-down for PGx pins */
sahilmgandhi	18:6a4db94011d3	760	GPIOG->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	761
sahilmgandhi	18:6a4db94011d3	762	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)\
sahilmgandhi	18:6a4db94011d3	763	\|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	764	/* Connect PHx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	765	GPIOH->AFR[0] = 0x00C0CC00;
sahilmgandhi	18:6a4db94011d3	766	GPIOH->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	767	/* Configure PHx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	768	GPIOH->MODER = 0xAAAA08A0;
sahilmgandhi	18:6a4db94011d3	769	/* Configure PHx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	770	GPIOH->OSPEEDR = 0xAAAA08A0;
sahilmgandhi	18:6a4db94011d3	771	/* Configure PHx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	772	GPIOH->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	773	/* No pull-up, pull-down for PHx pins */
sahilmgandhi	18:6a4db94011d3	774	GPIOH->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	775
sahilmgandhi	18:6a4db94011d3	776	/* Connect PIx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	777	GPIOI->AFR[0] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	778	GPIOI->AFR[1] = 0x00000CC0;
sahilmgandhi	18:6a4db94011d3	779	/* Configure PIx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	780	GPIOI->MODER = 0x0028AAAA;
sahilmgandhi	18:6a4db94011d3	781	/* Configure PIx pins speed to 50 MHz */
sahilmgandhi	18:6a4db94011d3	782	GPIOI->OSPEEDR = 0x0028AAAA;
sahilmgandhi	18:6a4db94011d3	783	/* Configure PIx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	784	GPIOI->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	785	/* No pull-up, pull-down for PIx pins */
sahilmgandhi	18:6a4db94011d3	786	GPIOI->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	787	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	788
sahilmgandhi	18:6a4db94011d3	789	/-- FMC Configuration -------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	790	/* Enable the FMC interface clock */
sahilmgandhi	18:6a4db94011d3	791	RCC->AHB3ENR \|= 0x00000001;
sahilmgandhi	18:6a4db94011d3	792	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	793	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
sahilmgandhi	18:6a4db94011d3	794
sahilmgandhi	18:6a4db94011d3	795	/* Configure and enable SDRAM bank1 */
sahilmgandhi	18:6a4db94011d3	796	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	797	FMC_Bank5_6->SDCR[0] = 0x00001954;
sahilmgandhi	18:6a4db94011d3	798	#else
sahilmgandhi	18:6a4db94011d3	799	FMC_Bank5_6->SDCR[0] = 0x000019E4;
sahilmgandhi	18:6a4db94011d3	800	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	801	FMC_Bank5_6->SDTR[0] = 0x01115351;
sahilmgandhi	18:6a4db94011d3	802
sahilmgandhi	18:6a4db94011d3	803	/* SDRAM initialization sequence */
sahilmgandhi	18:6a4db94011d3	804	/* Clock enable command */
sahilmgandhi	18:6a4db94011d3	805	FMC_Bank5_6->SDCMR = 0x00000011;
sahilmgandhi	18:6a4db94011d3	806	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	807	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	808	{
sahilmgandhi	18:6a4db94011d3	809	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	810	}
sahilmgandhi	18:6a4db94011d3	811
sahilmgandhi	18:6a4db94011d3	812	/* Delay */
sahilmgandhi	18:6a4db94011d3	813	for (index = 0; index<1000; index++);
sahilmgandhi	18:6a4db94011d3	814
sahilmgandhi	18:6a4db94011d3	815	/* PALL command */
sahilmgandhi	18:6a4db94011d3	816	FMC_Bank5_6->SDCMR = 0x00000012;
sahilmgandhi	18:6a4db94011d3	817	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	818	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	819	{
sahilmgandhi	18:6a4db94011d3	820	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	821	}
sahilmgandhi	18:6a4db94011d3	822
sahilmgandhi	18:6a4db94011d3	823	/* Auto refresh command */
sahilmgandhi	18:6a4db94011d3	824	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	825	FMC_Bank5_6->SDCMR = 0x000000F3;
sahilmgandhi	18:6a4db94011d3	826	#else
sahilmgandhi	18:6a4db94011d3	827	FMC_Bank5_6->SDCMR = 0x00000073;
sahilmgandhi	18:6a4db94011d3	828	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	829	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	830	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	831	{
sahilmgandhi	18:6a4db94011d3	832	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	833	}
sahilmgandhi	18:6a4db94011d3	834
sahilmgandhi	18:6a4db94011d3	835	/* MRD register program */
sahilmgandhi	18:6a4db94011d3	836	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	837	FMC_Bank5_6->SDCMR = 0x00044014;
sahilmgandhi	18:6a4db94011d3	838	#else
sahilmgandhi	18:6a4db94011d3	839	FMC_Bank5_6->SDCMR = 0x00046014;
sahilmgandhi	18:6a4db94011d3	840	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	841	timeout = 0xFFFF;
sahilmgandhi	18:6a4db94011d3	842	while((tmpreg != 0) && (timeout-- > 0))
sahilmgandhi	18:6a4db94011d3	843	{
sahilmgandhi	18:6a4db94011d3	844	tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
sahilmgandhi	18:6a4db94011d3	845	}
sahilmgandhi	18:6a4db94011d3	846
sahilmgandhi	18:6a4db94011d3	847	/* Set refresh count */
sahilmgandhi	18:6a4db94011d3	848	tmpreg = FMC_Bank5_6->SDRTR;
sahilmgandhi	18:6a4db94011d3	849	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	850	FMC_Bank5_6->SDRTR = (tmpreg \| (0x0000050C<<1));
sahilmgandhi	18:6a4db94011d3	851	#else
sahilmgandhi	18:6a4db94011d3	852	FMC_Bank5_6->SDRTR = (tmpreg \| (0x0000027C<<1));
sahilmgandhi	18:6a4db94011d3	853	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	854
sahilmgandhi	18:6a4db94011d3	855	/* Disable write protection */
sahilmgandhi	18:6a4db94011d3	856	tmpreg = FMC_Bank5_6->SDCR[0];
sahilmgandhi	18:6a4db94011d3	857	FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
sahilmgandhi	18:6a4db94011d3	858	#endif /* DATA_IN_ExtSDRAM */
sahilmgandhi	18:6a4db94011d3	859	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	860
sahilmgandhi	18:6a4db94011d3	861	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx)\
sahilmgandhi	18:6a4db94011d3	862	\|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)\
sahilmgandhi	18:6a4db94011d3	863	\|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx)
sahilmgandhi	18:6a4db94011d3	864
sahilmgandhi	18:6a4db94011d3	865	#if defined(DATA_IN_ExtSRAM)
sahilmgandhi	18:6a4db94011d3	866	/-- GPIOs Configuration -----------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	867	/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
sahilmgandhi	18:6a4db94011d3	868	RCC->AHB1ENR \|= 0x00000078;
sahilmgandhi	18:6a4db94011d3	869	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	870	tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
sahilmgandhi	18:6a4db94011d3	871
sahilmgandhi	18:6a4db94011d3	872	/* Connect PDx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	873	GPIOD->AFR[0] = 0x00CCC0CC;
sahilmgandhi	18:6a4db94011d3	874	GPIOD->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	875	/* Configure PDx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	876	GPIOD->MODER = 0xAAAA0A8A;
sahilmgandhi	18:6a4db94011d3	877	/* Configure PDx pins speed to 100 MHz */
sahilmgandhi	18:6a4db94011d3	878	GPIOD->OSPEEDR = 0xFFFF0FCF;
sahilmgandhi	18:6a4db94011d3	879	/* Configure PDx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	880	GPIOD->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	881	/* No pull-up, pull-down for PDx pins */
sahilmgandhi	18:6a4db94011d3	882	GPIOD->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	883
sahilmgandhi	18:6a4db94011d3	884	/* Connect PEx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	885	GPIOE->AFR[0] = 0xC00CC0CC;
sahilmgandhi	18:6a4db94011d3	886	GPIOE->AFR[1] = 0xCCCCCCCC;
sahilmgandhi	18:6a4db94011d3	887	/* Configure PEx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	888	GPIOE->MODER = 0xAAAA828A;
sahilmgandhi	18:6a4db94011d3	889	/* Configure PEx pins speed to 100 MHz */
sahilmgandhi	18:6a4db94011d3	890	GPIOE->OSPEEDR = 0xFFFFC3CF;
sahilmgandhi	18:6a4db94011d3	891	/* Configure PEx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	892	GPIOE->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	893	/* No pull-up, pull-down for PEx pins */
sahilmgandhi	18:6a4db94011d3	894	GPIOE->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	895
sahilmgandhi	18:6a4db94011d3	896	/* Connect PFx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	897	GPIOF->AFR[0] = 0x00CCCCCC;
sahilmgandhi	18:6a4db94011d3	898	GPIOF->AFR[1] = 0xCCCC0000;
sahilmgandhi	18:6a4db94011d3	899	/* Configure PFx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	900	GPIOF->MODER = 0xAA000AAA;
sahilmgandhi	18:6a4db94011d3	901	/* Configure PFx pins speed to 100 MHz */
sahilmgandhi	18:6a4db94011d3	902	GPIOF->OSPEEDR = 0xFF000FFF;
sahilmgandhi	18:6a4db94011d3	903	/* Configure PFx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	904	GPIOF->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	905	/* No pull-up, pull-down for PFx pins */
sahilmgandhi	18:6a4db94011d3	906	GPIOF->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	907
sahilmgandhi	18:6a4db94011d3	908	/* Connect PGx pins to FMC Alternate function */
sahilmgandhi	18:6a4db94011d3	909	GPIOG->AFR[0] = 0x00CCCCCC;
sahilmgandhi	18:6a4db94011d3	910	GPIOG->AFR[1] = 0x000000C0;
sahilmgandhi	18:6a4db94011d3	911	/* Configure PGx pins in Alternate function mode */
sahilmgandhi	18:6a4db94011d3	912	GPIOG->MODER = 0x00085AAA;
sahilmgandhi	18:6a4db94011d3	913	/* Configure PGx pins speed to 100 MHz */
sahilmgandhi	18:6a4db94011d3	914	GPIOG->OSPEEDR = 0x000CAFFF;
sahilmgandhi	18:6a4db94011d3	915	/* Configure PGx pins Output type to push-pull */
sahilmgandhi	18:6a4db94011d3	916	GPIOG->OTYPER = 0x00000000;
sahilmgandhi	18:6a4db94011d3	917	/* No pull-up, pull-down for PGx pins */
sahilmgandhi	18:6a4db94011d3	918	GPIOG->PUPDR = 0x00000000;
sahilmgandhi	18:6a4db94011d3	919
sahilmgandhi	18:6a4db94011d3	920	/-- FMC/FSMC Configuration --------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	921	/* Enable the FMC/FSMC interface clock */
sahilmgandhi	18:6a4db94011d3	922	RCC->AHB3ENR \|= 0x00000001;
sahilmgandhi	18:6a4db94011d3	923
sahilmgandhi	18:6a4db94011d3	924	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
sahilmgandhi	18:6a4db94011d3	925	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	926	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
sahilmgandhi	18:6a4db94011d3	927	/* Configure and enable Bank1_SRAM2 */
sahilmgandhi	18:6a4db94011d3	928	FMC_Bank1->BTCR[2] = 0x00001011;
sahilmgandhi	18:6a4db94011d3	929	FMC_Bank1->BTCR[3] = 0x00000201;
sahilmgandhi	18:6a4db94011d3	930	FMC_Bank1E->BWTR[2] = 0x0fffffff;
sahilmgandhi	18:6a4db94011d3	931	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
sahilmgandhi	18:6a4db94011d3	932	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	933	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	934	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
sahilmgandhi	18:6a4db94011d3	935	/* Configure and enable Bank1_SRAM2 */
sahilmgandhi	18:6a4db94011d3	936	FMC_Bank1->BTCR[2] = 0x00001091;
sahilmgandhi	18:6a4db94011d3	937	FMC_Bank1->BTCR[3] = 0x00110212;
sahilmgandhi	18:6a4db94011d3	938	FMC_Bank1E->BWTR[2] = 0x0fffffff;
sahilmgandhi	18:6a4db94011d3	939	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	940	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)\
sahilmgandhi	18:6a4db94011d3	941	\|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx)
sahilmgandhi	18:6a4db94011d3	942	/* Delay after an RCC peripheral clock enabling */
sahilmgandhi	18:6a4db94011d3	943	tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
sahilmgandhi	18:6a4db94011d3	944	/* Configure and enable Bank1_SRAM2 */
sahilmgandhi	18:6a4db94011d3	945	FSMC_Bank1->BTCR[2] = 0x00001011;
sahilmgandhi	18:6a4db94011d3	946	FSMC_Bank1->BTCR[3] = 0x00000201;
sahilmgandhi	18:6a4db94011d3	947	FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
sahilmgandhi	18:6a4db94011d3	948	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F412Zx \|\| STM32F412Vx */
sahilmgandhi	18:6a4db94011d3	949
sahilmgandhi	18:6a4db94011d3	950	#endif /* DATA_IN_ExtSRAM */
sahilmgandhi	18:6a4db94011d3	951	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|\
sahilmgandhi	18:6a4db94011d3	952	STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx */
sahilmgandhi	18:6a4db94011d3	953	(void)(tmp);
sahilmgandhi	18:6a4db94011d3	954	}
sahilmgandhi	18:6a4db94011d3	955	#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
sahilmgandhi	18:6a4db94011d3	956
sahilmgandhi	18:6a4db94011d3	957	/**
sahilmgandhi	18:6a4db94011d3	958	* @brief Configures the System clock source, PLL Multiplier and Divider factors,
sahilmgandhi	18:6a4db94011d3	959	* AHB/APBx prescalers and Flash settings
sahilmgandhi	18:6a4db94011d3	960	* @note This function should be called only once the RCC clock configuration
sahilmgandhi	18:6a4db94011d3	961	* is reset to the default reset state (done in SystemInit() function).
sahilmgandhi	18:6a4db94011d3	962	* @param None
sahilmgandhi	18:6a4db94011d3	963	* @retval None
sahilmgandhi	18:6a4db94011d3	964	*/
sahilmgandhi	18:6a4db94011d3	965	void SetSysClock(void)
sahilmgandhi	18:6a4db94011d3	966	{
sahilmgandhi	18:6a4db94011d3	967	/* 1- Try to start with HSE and external clock */
sahilmgandhi	18:6a4db94011d3	968	#if USE_PLL_HSE_EXTC != 0
sahilmgandhi	18:6a4db94011d3	969	if (SetSysClock_PLL_HSE(1) == 0)
sahilmgandhi	18:6a4db94011d3	970	#endif
sahilmgandhi	18:6a4db94011d3	971	{
sahilmgandhi	18:6a4db94011d3	972	/* 2- If fail try to start with HSE and external xtal */
sahilmgandhi	18:6a4db94011d3	973	#if USE_PLL_HSE_XTAL != 0
sahilmgandhi	18:6a4db94011d3	974	if (SetSysClock_PLL_HSE(0) == 0)
sahilmgandhi	18:6a4db94011d3	975	#endif
sahilmgandhi	18:6a4db94011d3	976	{
sahilmgandhi	18:6a4db94011d3	977	/* 3- If fail start with HSI clock */
sahilmgandhi	18:6a4db94011d3	978	if (SetSysClock_PLL_HSI() == 0)
sahilmgandhi	18:6a4db94011d3	979	{
sahilmgandhi	18:6a4db94011d3	980	while(1)
sahilmgandhi	18:6a4db94011d3	981	{
sahilmgandhi	18:6a4db94011d3	982	// [TODO] Put something here to tell the user that a problem occured...
sahilmgandhi	18:6a4db94011d3	983	}
sahilmgandhi	18:6a4db94011d3	984	}
sahilmgandhi	18:6a4db94011d3	985	}
sahilmgandhi	18:6a4db94011d3	986	}
sahilmgandhi	18:6a4db94011d3	987
sahilmgandhi	18:6a4db94011d3	988	/* Output clock on MCO2 pin(PC9) for debugging purpose */
sahilmgandhi	18:6a4db94011d3	989	//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
sahilmgandhi	18:6a4db94011d3	990	}
sahilmgandhi	18:6a4db94011d3	991
sahilmgandhi	18:6a4db94011d3	992	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
sahilmgandhi	18:6a4db94011d3	993	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	994	/* PLL (clocked by HSE) used as System clock source */
sahilmgandhi	18:6a4db94011d3	995	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	996	uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
sahilmgandhi	18:6a4db94011d3	997	{
sahilmgandhi	18:6a4db94011d3	998	RCC_ClkInitTypeDef RCC_ClkInitStruct;
sahilmgandhi	18:6a4db94011d3	999	RCC_OscInitTypeDef RCC_OscInitStruct;
sahilmgandhi	18:6a4db94011d3	1000
sahilmgandhi	18:6a4db94011d3	1001	/* The voltage scaling allows optimizing the power consumption when the device is
sahilmgandhi	18:6a4db94011d3	1002	clocked below the maximum system frequency, to update the voltage scaling value
sahilmgandhi	18:6a4db94011d3	1003	regarding system frequency refer to product datasheet. */
sahilmgandhi	18:6a4db94011d3	1004	__PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	1005	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
sahilmgandhi	18:6a4db94011d3	1006
sahilmgandhi	18:6a4db94011d3	1007	/* Enable HSE oscillator and activate PLL with HSE as source */
sahilmgandhi	18:6a4db94011d3	1008	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
sahilmgandhi	18:6a4db94011d3	1009	if (bypass == 0)
sahilmgandhi	18:6a4db94011d3	1010	{
sahilmgandhi	18:6a4db94011d3	1011	RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
sahilmgandhi	18:6a4db94011d3	1012	}
sahilmgandhi	18:6a4db94011d3	1013	else
sahilmgandhi	18:6a4db94011d3	1014	{
sahilmgandhi	18:6a4db94011d3	1015	RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
sahilmgandhi	18:6a4db94011d3	1016	}
sahilmgandhi	18:6a4db94011d3	1017	RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
sahilmgandhi	18:6a4db94011d3	1018	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
sahilmgandhi	18:6a4db94011d3	1019	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
sahilmgandhi	18:6a4db94011d3	1020	RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
sahilmgandhi	18:6a4db94011d3	1021	RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
sahilmgandhi	18:6a4db94011d3	1022	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
sahilmgandhi	18:6a4db94011d3	1023	RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
sahilmgandhi	18:6a4db94011d3	1024	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	1025	{
sahilmgandhi	18:6a4db94011d3	1026	return 0; // FAIL
sahilmgandhi	18:6a4db94011d3	1027	}
sahilmgandhi	18:6a4db94011d3	1028
sahilmgandhi	18:6a4db94011d3	1029	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
sahilmgandhi	18:6a4db94011d3	1030	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
sahilmgandhi	18:6a4db94011d3	1031	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
sahilmgandhi	18:6a4db94011d3	1032	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
sahilmgandhi	18:6a4db94011d3	1033	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
sahilmgandhi	18:6a4db94011d3	1034	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz (SPI1 clock...)
sahilmgandhi	18:6a4db94011d3	1035	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	1036	{
sahilmgandhi	18:6a4db94011d3	1037	return 0; // FAIL
sahilmgandhi	18:6a4db94011d3	1038	}
sahilmgandhi	18:6a4db94011d3	1039
sahilmgandhi	18:6a4db94011d3	1040	/* Output clock on MCO1 pin(PA8) for debugging purpose */
sahilmgandhi	18:6a4db94011d3	1041	/*
sahilmgandhi	18:6a4db94011d3	1042	if (bypass == 0)
sahilmgandhi	18:6a4db94011d3	1043	HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
sahilmgandhi	18:6a4db94011d3	1044	else
sahilmgandhi	18:6a4db94011d3	1045	HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
sahilmgandhi	18:6a4db94011d3	1046	*/
sahilmgandhi	18:6a4db94011d3	1047
sahilmgandhi	18:6a4db94011d3	1048	return 1; // OK
sahilmgandhi	18:6a4db94011d3	1049	}
sahilmgandhi	18:6a4db94011d3	1050	#endif
sahilmgandhi	18:6a4db94011d3	1051
sahilmgandhi	18:6a4db94011d3	1052	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	1053	/* PLL (clocked by HSI) used as System clock source */
sahilmgandhi	18:6a4db94011d3	1054	/******************************************************************************/
sahilmgandhi	18:6a4db94011d3	1055	uint8_t SetSysClock_PLL_HSI(void)
sahilmgandhi	18:6a4db94011d3	1056	{
sahilmgandhi	18:6a4db94011d3	1057	RCC_ClkInitTypeDef RCC_ClkInitStruct;
sahilmgandhi	18:6a4db94011d3	1058	RCC_OscInitTypeDef RCC_OscInitStruct;
sahilmgandhi	18:6a4db94011d3	1059
sahilmgandhi	18:6a4db94011d3	1060	/* The voltage scaling allows optimizing the power consumption when the device is
sahilmgandhi	18:6a4db94011d3	1061	clocked below the maximum system frequency, to update the voltage scaling value
sahilmgandhi	18:6a4db94011d3	1062	regarding system frequency refer to product datasheet. */
sahilmgandhi	18:6a4db94011d3	1063	__PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	1064	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
sahilmgandhi	18:6a4db94011d3	1065
sahilmgandhi	18:6a4db94011d3	1066	/* Enable HSI oscillator and activate PLL with HSI as source */
sahilmgandhi	18:6a4db94011d3	1067	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_HSE;
sahilmgandhi	18:6a4db94011d3	1068	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
sahilmgandhi	18:6a4db94011d3	1069	RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
sahilmgandhi	18:6a4db94011d3	1070	RCC_OscInitStruct.HSICalibrationValue = 16;
sahilmgandhi	18:6a4db94011d3	1071	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
sahilmgandhi	18:6a4db94011d3	1072	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
sahilmgandhi	18:6a4db94011d3	1073	RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
sahilmgandhi	18:6a4db94011d3	1074	RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
sahilmgandhi	18:6a4db94011d3	1075	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)
sahilmgandhi	18:6a4db94011d3	1076	RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
sahilmgandhi	18:6a4db94011d3	1077	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	1078	{
sahilmgandhi	18:6a4db94011d3	1079	return 0; // FAIL
sahilmgandhi	18:6a4db94011d3	1080	}
sahilmgandhi	18:6a4db94011d3	1081
sahilmgandhi	18:6a4db94011d3	1082	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
sahilmgandhi	18:6a4db94011d3	1083	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
sahilmgandhi	18:6a4db94011d3	1084	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz
sahilmgandhi	18:6a4db94011d3	1085	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz
sahilmgandhi	18:6a4db94011d3	1086	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz
sahilmgandhi	18:6a4db94011d3	1087	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz
sahilmgandhi	18:6a4db94011d3	1088	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	1089	{
sahilmgandhi	18:6a4db94011d3	1090	return 0; // FAIL
sahilmgandhi	18:6a4db94011d3	1091	}
sahilmgandhi	18:6a4db94011d3	1092
sahilmgandhi	18:6a4db94011d3	1093	/* Output clock on MCO1 pin(PA8) for debugging purpose */
sahilmgandhi	18:6a4db94011d3	1094	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
sahilmgandhi	18:6a4db94011d3	1095
sahilmgandhi	18:6a4db94011d3	1096	return 1; // OK
sahilmgandhi	18:6a4db94011d3	1097	}
sahilmgandhi	18:6a4db94011d3	1098
sahilmgandhi	18:6a4db94011d3	1099	/**
sahilmgandhi	18:6a4db94011d3	1100	* @}
sahilmgandhi	18:6a4db94011d3	1101	*/
sahilmgandhi	18:6a4db94011d3	1102
sahilmgandhi	18:6a4db94011d3	1103	/**
sahilmgandhi	18:6a4db94011d3	1104	* @}
sahilmgandhi	18:6a4db94011d3	1105	*/
sahilmgandhi	18:6a4db94011d3	1106
sahilmgandhi	18:6a4db94011d3	1107	/**
sahilmgandhi	18:6a4db94011d3	1108	* @}
sahilmgandhi	18:6a4db94011d3	1109	*/
sahilmgandhi	18:6a4db94011d3	1110	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_stm32f4xx.c@18:6a4db94011d3, 2017-05-14 (annotated)

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