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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:: sahilmgandhi
Date:: Sun May 14 23:18:57 2017 +0000
Revision:: 18:6a4db94011d3

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User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f2xx_hal_tim.c
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.1.3
sahilmgandhi	18:6a4db94011d3	6	* @date 29-June-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief TIM HAL module driver.
sahilmgandhi	18:6a4db94011d3	8	* This file provides firmware functions to manage the following
sahilmgandhi	18:6a4db94011d3	9	* functionalities of the Timer (TIM) peripheral:
sahilmgandhi	18:6a4db94011d3	10	* + Time Base Initialization
sahilmgandhi	18:6a4db94011d3	11	* + Time Base Start
sahilmgandhi	18:6a4db94011d3	12	* + Time Base Start Interruption
sahilmgandhi	18:6a4db94011d3	13	* + Time Base Start DMA
sahilmgandhi	18:6a4db94011d3	14	* + Time Output Compare/PWM Initialization
sahilmgandhi	18:6a4db94011d3	15	* + Time Output Compare/PWM Channel Configuration
sahilmgandhi	18:6a4db94011d3	16	* + Time Output Compare/PWM Start
sahilmgandhi	18:6a4db94011d3	17	* + Time Output Compare/PWM Start Interruption
sahilmgandhi	18:6a4db94011d3	18	* + Time Output Compare/PWM Start DMA
sahilmgandhi	18:6a4db94011d3	19	* + Time Input Capture Initialization
sahilmgandhi	18:6a4db94011d3	20	* + Time Input Capture Channel Configuration
sahilmgandhi	18:6a4db94011d3	21	* + Time Input Capture Start
sahilmgandhi	18:6a4db94011d3	22	* + Time Input Capture Start Interruption
sahilmgandhi	18:6a4db94011d3	23	* + Time Input Capture Start DMA
sahilmgandhi	18:6a4db94011d3	24	* + Time One Pulse Initialization
sahilmgandhi	18:6a4db94011d3	25	* + Time One Pulse Channel Configuration
sahilmgandhi	18:6a4db94011d3	26	* + Time One Pulse Start
sahilmgandhi	18:6a4db94011d3	27	* + Time Encoder Interface Initialization
sahilmgandhi	18:6a4db94011d3	28	* + Time Encoder Interface Start
sahilmgandhi	18:6a4db94011d3	29	* + Time Encoder Interface Start Interruption
sahilmgandhi	18:6a4db94011d3	30	* + Time Encoder Interface Start DMA
sahilmgandhi	18:6a4db94011d3	31	* + Commutation Event configuration with Interruption and DMA
sahilmgandhi	18:6a4db94011d3	32	* + Time OCRef clear configuration
sahilmgandhi	18:6a4db94011d3	33	* + Time External Clock configuration
sahilmgandhi	18:6a4db94011d3	34	@verbatim
sahilmgandhi	18:6a4db94011d3	35	==============================================================================
sahilmgandhi	18:6a4db94011d3	36	##### TIMER Generic features #####
sahilmgandhi	18:6a4db94011d3	37	==============================================================================
sahilmgandhi	18:6a4db94011d3	38	[..] The Timer features include:
sahilmgandhi	18:6a4db94011d3	39	(#) 16-bit up, down, up/down auto-reload counter.
sahilmgandhi	18:6a4db94011d3	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
sahilmgandhi	18:6a4db94011d3	41	counter clock frequency either by any factor between 1 and 65536.
sahilmgandhi	18:6a4db94011d3	42	(#) Up to 4 independent channels for:
sahilmgandhi	18:6a4db94011d3	43	(++) Input Capture
sahilmgandhi	18:6a4db94011d3	44	(++) Output Compare
sahilmgandhi	18:6a4db94011d3	45	(++) PWM generation (Edge and Center-aligned Mode)
sahilmgandhi	18:6a4db94011d3	46	(++) One-pulse mode output
sahilmgandhi	18:6a4db94011d3	47
sahilmgandhi	18:6a4db94011d3	48	##### How to use this driver #####
sahilmgandhi	18:6a4db94011d3	49	==============================================================================
sahilmgandhi	18:6a4db94011d3	50	[..]
sahilmgandhi	18:6a4db94011d3	51	(#) Initialize the TIM low level resources by implementing the following functions
sahilmgandhi	18:6a4db94011d3	52	depending from feature used :
sahilmgandhi	18:6a4db94011d3	53	(++) Time Base : HAL_TIM_Base_MspInit()
sahilmgandhi	18:6a4db94011d3	54	(++) Input Capture : HAL_TIM_IC_MspInit()
sahilmgandhi	18:6a4db94011d3	55	(++) Output Compare : HAL_TIM_OC_MspInit()
sahilmgandhi	18:6a4db94011d3	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
sahilmgandhi	18:6a4db94011d3	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
sahilmgandhi	18:6a4db94011d3	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
sahilmgandhi	18:6a4db94011d3	59
sahilmgandhi	18:6a4db94011d3	60	(#) Initialize the TIM low level resources :
sahilmgandhi	18:6a4db94011d3	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	62	(##) TIM pins configuration
sahilmgandhi	18:6a4db94011d3	63	(+++) Enable the clock for the TIM GPIOs using the following function:
sahilmgandhi	18:6a4db94011d3	64	__GPIOx_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
sahilmgandhi	18:6a4db94011d3	66
sahilmgandhi	18:6a4db94011d3	67	(#) The external Clock can be configured, if needed (the default clock is the
sahilmgandhi	18:6a4db94011d3	68	internal clock from the APBx), using the following function:
sahilmgandhi	18:6a4db94011d3	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
sahilmgandhi	18:6a4db94011d3	70	any start function.
sahilmgandhi	18:6a4db94011d3	71
sahilmgandhi	18:6a4db94011d3	72	(#) Configure the TIM in the desired functioning mode using one of the
sahilmgandhi	18:6a4db94011d3	73	initialization function of this driver:
sahilmgandhi	18:6a4db94011d3	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
sahilmgandhi	18:6a4db94011d3	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
sahilmgandhi	18:6a4db94011d3	76	Output Compare signal.
sahilmgandhi	18:6a4db94011d3	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
sahilmgandhi	18:6a4db94011d3	78	PWM signal.
sahilmgandhi	18:6a4db94011d3	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
sahilmgandhi	18:6a4db94011d3	80	external signal.
sahilmgandhi	18:6a4db94011d3	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
sahilmgandhi	18:6a4db94011d3	82	in One Pulse Mode.
sahilmgandhi	18:6a4db94011d3	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
sahilmgandhi	18:6a4db94011d3	84
sahilmgandhi	18:6a4db94011d3	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
sahilmgandhi	18:6a4db94011d3	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
sahilmgandhi	18:6a4db94011d3	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
sahilmgandhi	18:6a4db94011d3	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
sahilmgandhi	18:6a4db94011d3	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
sahilmgandhi	18:6a4db94011d3	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
sahilmgandhi	18:6a4db94011d3	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
sahilmgandhi	18:6a4db94011d3	92
sahilmgandhi	18:6a4db94011d3	93	(#) The DMA Burst is managed with the two following functions:
sahilmgandhi	18:6a4db94011d3	94	HAL_TIM_DMABurst_WriteStart()
sahilmgandhi	18:6a4db94011d3	95	HAL_TIM_DMABurst_ReadStart()
sahilmgandhi	18:6a4db94011d3	96
sahilmgandhi	18:6a4db94011d3	97	@endverbatim
sahilmgandhi	18:6a4db94011d3	98	******************************************************************************
sahilmgandhi	18:6a4db94011d3	99	* @attention
sahilmgandhi	18:6a4db94011d3	100	*
sahilmgandhi	18:6a4db94011d3	101	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	102	*
sahilmgandhi	18:6a4db94011d3	103	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	104	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	105	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	106	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	108	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	109	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	111	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	112	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	113	*
sahilmgandhi	18:6a4db94011d3	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	124	*
sahilmgandhi	18:6a4db94011d3	125	******************************************************************************
sahilmgandhi	18:6a4db94011d3	126	*/
sahilmgandhi	18:6a4db94011d3	127
sahilmgandhi	18:6a4db94011d3	128	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	129	#include "stm32f2xx_hal.h"
sahilmgandhi	18:6a4db94011d3	130
sahilmgandhi	18:6a4db94011d3	131	/** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	132	* @{
sahilmgandhi	18:6a4db94011d3	133	*/
sahilmgandhi	18:6a4db94011d3	134
sahilmgandhi	18:6a4db94011d3	135	/** @defgroup TIM TIM
sahilmgandhi	18:6a4db94011d3	136	* @brief TIM HAL module driver
sahilmgandhi	18:6a4db94011d3	137	* @{
sahilmgandhi	18:6a4db94011d3	138	*/
sahilmgandhi	18:6a4db94011d3	139
sahilmgandhi	18:6a4db94011d3	140	#ifdef HAL_TIM_MODULE_ENABLED
sahilmgandhi	18:6a4db94011d3	141
sahilmgandhi	18:6a4db94011d3	142	/* Private typedef -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	143	/* Private define ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	144	/* Private macro -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	145	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	146	/** @addtogroup TIM_Private_Functions
sahilmgandhi	18:6a4db94011d3	147	* @{
sahilmgandhi	18:6a4db94011d3	148	*/
sahilmgandhi	18:6a4db94011d3	149	/* Private function prototypes -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	150	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
sahilmgandhi	18:6a4db94011d3	151	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
sahilmgandhi	18:6a4db94011d3	152	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
sahilmgandhi	18:6a4db94011d3	153
sahilmgandhi	18:6a4db94011d3	154	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
sahilmgandhi	18:6a4db94011d3	155	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
sahilmgandhi	18:6a4db94011d3	156	uint32_t TIM_ICFilter);
sahilmgandhi	18:6a4db94011d3	157	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
sahilmgandhi	18:6a4db94011d3	158	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
sahilmgandhi	18:6a4db94011d3	159	uint32_t TIM_ICFilter);
sahilmgandhi	18:6a4db94011d3	160	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
sahilmgandhi	18:6a4db94011d3	161	uint32_t TIM_ICFilter);
sahilmgandhi	18:6a4db94011d3	162
sahilmgandhi	18:6a4db94011d3	163	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
sahilmgandhi	18:6a4db94011d3	164	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
sahilmgandhi	18:6a4db94011d3	165
sahilmgandhi	18:6a4db94011d3	166	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
sahilmgandhi	18:6a4db94011d3	167	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	168	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	169	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
sahilmgandhi	18:6a4db94011d3	170	TIM_SlaveConfigTypeDef * sSlaveConfig);
sahilmgandhi	18:6a4db94011d3	171	/**
sahilmgandhi	18:6a4db94011d3	172	* @}
sahilmgandhi	18:6a4db94011d3	173	*/
sahilmgandhi	18:6a4db94011d3	174
sahilmgandhi	18:6a4db94011d3	175	/* Exported functions --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	176	/** @defgroup TIM_Exported_Functions TIM Exported Functions
sahilmgandhi	18:6a4db94011d3	177	* @{
sahilmgandhi	18:6a4db94011d3	178	*/
sahilmgandhi	18:6a4db94011d3	179
sahilmgandhi	18:6a4db94011d3	180	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
sahilmgandhi	18:6a4db94011d3	181	* @brief Time Base functions
sahilmgandhi	18:6a4db94011d3	182	*
sahilmgandhi	18:6a4db94011d3	183	@verbatim
sahilmgandhi	18:6a4db94011d3	184	==============================================================================
sahilmgandhi	18:6a4db94011d3	185	##### Time Base functions #####
sahilmgandhi	18:6a4db94011d3	186	==============================================================================
sahilmgandhi	18:6a4db94011d3	187	[..]
sahilmgandhi	18:6a4db94011d3	188	This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	189	(+) Initialize and configure the TIM base.
sahilmgandhi	18:6a4db94011d3	190	(+) De-initialize the TIM base.
sahilmgandhi	18:6a4db94011d3	191	(+) Start the Time Base.
sahilmgandhi	18:6a4db94011d3	192	(+) Stop the Time Base.
sahilmgandhi	18:6a4db94011d3	193	(+) Start the Time Base and enable interrupt.
sahilmgandhi	18:6a4db94011d3	194	(+) Stop the Time Base and disable interrupt.
sahilmgandhi	18:6a4db94011d3	195	(+) Start the Time Base and enable DMA transfer.
sahilmgandhi	18:6a4db94011d3	196	(+) Stop the Time Base and disable DMA transfer.
sahilmgandhi	18:6a4db94011d3	197
sahilmgandhi	18:6a4db94011d3	198	@endverbatim
sahilmgandhi	18:6a4db94011d3	199	* @{
sahilmgandhi	18:6a4db94011d3	200	*/
sahilmgandhi	18:6a4db94011d3	201	/**
sahilmgandhi	18:6a4db94011d3	202	* @brief Initializes the TIM Time base Unit according to the specified
sahilmgandhi	18:6a4db94011d3	203	* parameters in the TIM_HandleTypeDef and create the associated handle.
sahilmgandhi	18:6a4db94011d3	204	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	205	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	206	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	207	*/
sahilmgandhi	18:6a4db94011d3	208	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	209	{
sahilmgandhi	18:6a4db94011d3	210	/* Check the TIM handle allocation */
sahilmgandhi	18:6a4db94011d3	211	if(htim == NULL)
sahilmgandhi	18:6a4db94011d3	212	{
sahilmgandhi	18:6a4db94011d3	213	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	214	}
sahilmgandhi	18:6a4db94011d3	215
sahilmgandhi	18:6a4db94011d3	216	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	217	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	218	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
sahilmgandhi	18:6a4db94011d3	219	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
sahilmgandhi	18:6a4db94011d3	220
sahilmgandhi	18:6a4db94011d3	221	if(htim->State == HAL_TIM_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	222	{
sahilmgandhi	18:6a4db94011d3	223	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	224	htim->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	225	/* Init the low level hardware : GPIO, CLOCK, NVIC */
sahilmgandhi	18:6a4db94011d3	226	HAL_TIM_Base_MspInit(htim);
sahilmgandhi	18:6a4db94011d3	227	}
sahilmgandhi	18:6a4db94011d3	228
sahilmgandhi	18:6a4db94011d3	229	/* Set the TIM state */
sahilmgandhi	18:6a4db94011d3	230	htim->State= HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	231
sahilmgandhi	18:6a4db94011d3	232	/* Set the Time Base configuration */
sahilmgandhi	18:6a4db94011d3	233	TIM_Base_SetConfig(htim->Instance, &htim->Init);
sahilmgandhi	18:6a4db94011d3	234
sahilmgandhi	18:6a4db94011d3	235	/* Initialize the TIM state*/
sahilmgandhi	18:6a4db94011d3	236	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	237
sahilmgandhi	18:6a4db94011d3	238	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	239	}
sahilmgandhi	18:6a4db94011d3	240
sahilmgandhi	18:6a4db94011d3	241	/**
sahilmgandhi	18:6a4db94011d3	242	* @brief DeInitializes the TIM Base peripheral
sahilmgandhi	18:6a4db94011d3	243	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	244	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	245	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	246	*/
sahilmgandhi	18:6a4db94011d3	247	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	248	{
sahilmgandhi	18:6a4db94011d3	249	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	250	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	251
sahilmgandhi	18:6a4db94011d3	252	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	253
sahilmgandhi	18:6a4db94011d3	254	/* Disable the TIM Peripheral Clock */
sahilmgandhi	18:6a4db94011d3	255	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	256
sahilmgandhi	18:6a4db94011d3	257	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
sahilmgandhi	18:6a4db94011d3	258	HAL_TIM_Base_MspDeInit(htim);
sahilmgandhi	18:6a4db94011d3	259
sahilmgandhi	18:6a4db94011d3	260	/* Change TIM state */
sahilmgandhi	18:6a4db94011d3	261	htim->State = HAL_TIM_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	262
sahilmgandhi	18:6a4db94011d3	263	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	264	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	265
sahilmgandhi	18:6a4db94011d3	266	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	267	}
sahilmgandhi	18:6a4db94011d3	268
sahilmgandhi	18:6a4db94011d3	269	/**
sahilmgandhi	18:6a4db94011d3	270	* @brief Initializes the TIM Base MSP.
sahilmgandhi	18:6a4db94011d3	271	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	272	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	273	* @retval None
sahilmgandhi	18:6a4db94011d3	274	*/
sahilmgandhi	18:6a4db94011d3	275	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	276	{
sahilmgandhi	18:6a4db94011d3	277	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	278	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	279	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	280	the HAL_TIM_Base_MspInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	281	*/
sahilmgandhi	18:6a4db94011d3	282	}
sahilmgandhi	18:6a4db94011d3	283
sahilmgandhi	18:6a4db94011d3	284	/**
sahilmgandhi	18:6a4db94011d3	285	* @brief DeInitializes TIM Base MSP.
sahilmgandhi	18:6a4db94011d3	286	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	287	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	288	* @retval None
sahilmgandhi	18:6a4db94011d3	289	*/
sahilmgandhi	18:6a4db94011d3	290	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	291	{
sahilmgandhi	18:6a4db94011d3	292	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	293	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	294	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	295	the HAL_TIM_Base_MspDeInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	296	*/
sahilmgandhi	18:6a4db94011d3	297	}
sahilmgandhi	18:6a4db94011d3	298
sahilmgandhi	18:6a4db94011d3	299	/**
sahilmgandhi	18:6a4db94011d3	300	* @brief Starts the TIM Base generation.
sahilmgandhi	18:6a4db94011d3	301	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	302	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	303	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	304	*/
sahilmgandhi	18:6a4db94011d3	305	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	306	{
sahilmgandhi	18:6a4db94011d3	307	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	308	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	309
sahilmgandhi	18:6a4db94011d3	310	/* Set the TIM state */
sahilmgandhi	18:6a4db94011d3	311	htim->State= HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	312
sahilmgandhi	18:6a4db94011d3	313	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	314	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	315
sahilmgandhi	18:6a4db94011d3	316	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	317	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	318
sahilmgandhi	18:6a4db94011d3	319	/* Return function status */
sahilmgandhi	18:6a4db94011d3	320	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	321	}
sahilmgandhi	18:6a4db94011d3	322
sahilmgandhi	18:6a4db94011d3	323	/**
sahilmgandhi	18:6a4db94011d3	324	* @brief Stops the TIM Base generation.
sahilmgandhi	18:6a4db94011d3	325	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	326	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	327	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	328	*/
sahilmgandhi	18:6a4db94011d3	329	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	330	{
sahilmgandhi	18:6a4db94011d3	331	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	332	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	333
sahilmgandhi	18:6a4db94011d3	334	/* Set the TIM state */
sahilmgandhi	18:6a4db94011d3	335	htim->State= HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	336
sahilmgandhi	18:6a4db94011d3	337	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	338	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	339
sahilmgandhi	18:6a4db94011d3	340	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	341	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	342
sahilmgandhi	18:6a4db94011d3	343	/* Return function status */
sahilmgandhi	18:6a4db94011d3	344	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	345	}
sahilmgandhi	18:6a4db94011d3	346
sahilmgandhi	18:6a4db94011d3	347	/**
sahilmgandhi	18:6a4db94011d3	348	* @brief Starts the TIM Base generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	349	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	350	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	351	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	352	*/
sahilmgandhi	18:6a4db94011d3	353	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	354	{
sahilmgandhi	18:6a4db94011d3	355	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	356	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	357
sahilmgandhi	18:6a4db94011d3	358	/* Enable the TIM Update interrupt */
sahilmgandhi	18:6a4db94011d3	359	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
sahilmgandhi	18:6a4db94011d3	360
sahilmgandhi	18:6a4db94011d3	361	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	362	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	363
sahilmgandhi	18:6a4db94011d3	364	/* Return function status */
sahilmgandhi	18:6a4db94011d3	365	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	366	}
sahilmgandhi	18:6a4db94011d3	367
sahilmgandhi	18:6a4db94011d3	368	/**
sahilmgandhi	18:6a4db94011d3	369	* @brief Stops the TIM Base generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	370	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	371	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	372	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	373	*/
sahilmgandhi	18:6a4db94011d3	374	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	375	{
sahilmgandhi	18:6a4db94011d3	376	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	377	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	378	/* Disable the TIM Update interrupt */
sahilmgandhi	18:6a4db94011d3	379	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
sahilmgandhi	18:6a4db94011d3	380
sahilmgandhi	18:6a4db94011d3	381	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	382	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	383
sahilmgandhi	18:6a4db94011d3	384	/* Return function status */
sahilmgandhi	18:6a4db94011d3	385	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	386	}
sahilmgandhi	18:6a4db94011d3	387
sahilmgandhi	18:6a4db94011d3	388	/**
sahilmgandhi	18:6a4db94011d3	389	* @brief Starts the TIM Base generation in DMA mode.
sahilmgandhi	18:6a4db94011d3	390	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	391	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	392	* @param pData: The source Buffer address.
sahilmgandhi	18:6a4db94011d3	393	* @param Length: The length of data to be transferred from memory to peripheral.
sahilmgandhi	18:6a4db94011d3	394	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	395	*/
sahilmgandhi	18:6a4db94011d3	396	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
sahilmgandhi	18:6a4db94011d3	397	{
sahilmgandhi	18:6a4db94011d3	398	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	399	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	400
sahilmgandhi	18:6a4db94011d3	401	if((htim->State == HAL_TIM_STATE_BUSY))
sahilmgandhi	18:6a4db94011d3	402	{
sahilmgandhi	18:6a4db94011d3	403	return HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	404	}
sahilmgandhi	18:6a4db94011d3	405	else if((htim->State == HAL_TIM_STATE_READY))
sahilmgandhi	18:6a4db94011d3	406	{
sahilmgandhi	18:6a4db94011d3	407	if((pData == 0 ) && (Length > 0))
sahilmgandhi	18:6a4db94011d3	408	{
sahilmgandhi	18:6a4db94011d3	409	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	410	}
sahilmgandhi	18:6a4db94011d3	411	else
sahilmgandhi	18:6a4db94011d3	412	{
sahilmgandhi	18:6a4db94011d3	413	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	414	}
sahilmgandhi	18:6a4db94011d3	415	}
sahilmgandhi	18:6a4db94011d3	416	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	417	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
sahilmgandhi	18:6a4db94011d3	418
sahilmgandhi	18:6a4db94011d3	419	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	420	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	421
sahilmgandhi	18:6a4db94011d3	422	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	423	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
sahilmgandhi	18:6a4db94011d3	424
sahilmgandhi	18:6a4db94011d3	425	/* Enable the TIM Update DMA request */
sahilmgandhi	18:6a4db94011d3	426	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
sahilmgandhi	18:6a4db94011d3	427
sahilmgandhi	18:6a4db94011d3	428	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	429	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	430
sahilmgandhi	18:6a4db94011d3	431	/* Return function status */
sahilmgandhi	18:6a4db94011d3	432	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	433	}
sahilmgandhi	18:6a4db94011d3	434
sahilmgandhi	18:6a4db94011d3	435	/**
sahilmgandhi	18:6a4db94011d3	436	* @brief Stops the TIM Base generation in DMA mode.
sahilmgandhi	18:6a4db94011d3	437	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	438	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	439	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	440	*/
sahilmgandhi	18:6a4db94011d3	441	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	442	{
sahilmgandhi	18:6a4db94011d3	443	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	444	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	445
sahilmgandhi	18:6a4db94011d3	446	/* Disable the TIM Update DMA request */
sahilmgandhi	18:6a4db94011d3	447	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
sahilmgandhi	18:6a4db94011d3	448
sahilmgandhi	18:6a4db94011d3	449	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	450	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	451
sahilmgandhi	18:6a4db94011d3	452	/* Change the htim state */
sahilmgandhi	18:6a4db94011d3	453	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	454
sahilmgandhi	18:6a4db94011d3	455	/* Return function status */
sahilmgandhi	18:6a4db94011d3	456	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	457	}
sahilmgandhi	18:6a4db94011d3	458	/**
sahilmgandhi	18:6a4db94011d3	459	* @}
sahilmgandhi	18:6a4db94011d3	460	*/
sahilmgandhi	18:6a4db94011d3	461
sahilmgandhi	18:6a4db94011d3	462	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
sahilmgandhi	18:6a4db94011d3	463	* @brief Time Output Compare functions
sahilmgandhi	18:6a4db94011d3	464	*
sahilmgandhi	18:6a4db94011d3	465	@verbatim
sahilmgandhi	18:6a4db94011d3	466	==============================================================================
sahilmgandhi	18:6a4db94011d3	467	##### Time Output Compare functions #####
sahilmgandhi	18:6a4db94011d3	468	==============================================================================
sahilmgandhi	18:6a4db94011d3	469	[..]
sahilmgandhi	18:6a4db94011d3	470	This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	471	(+) Initialize and configure the TIM Output Compare.
sahilmgandhi	18:6a4db94011d3	472	(+) De-initialize the TIM Output Compare.
sahilmgandhi	18:6a4db94011d3	473	(+) Start the Time Output Compare.
sahilmgandhi	18:6a4db94011d3	474	(+) Stop the Time Output Compare.
sahilmgandhi	18:6a4db94011d3	475	(+) Start the Time Output Compare and enable interrupt.
sahilmgandhi	18:6a4db94011d3	476	(+) Stop the Time Output Compare and disable interrupt.
sahilmgandhi	18:6a4db94011d3	477	(+) Start the Time Output Compare and enable DMA transfer.
sahilmgandhi	18:6a4db94011d3	478	(+) Stop the Time Output Compare and disable DMA transfer.
sahilmgandhi	18:6a4db94011d3	479
sahilmgandhi	18:6a4db94011d3	480	@endverbatim
sahilmgandhi	18:6a4db94011d3	481	* @{
sahilmgandhi	18:6a4db94011d3	482	*/
sahilmgandhi	18:6a4db94011d3	483	/**
sahilmgandhi	18:6a4db94011d3	484	* @brief Initializes the TIM Output Compare according to the specified
sahilmgandhi	18:6a4db94011d3	485	* parameters in the TIM_HandleTypeDef and create the associated handle.
sahilmgandhi	18:6a4db94011d3	486	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	487	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	488	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	489	*/
sahilmgandhi	18:6a4db94011d3	490	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
sahilmgandhi	18:6a4db94011d3	491	{
sahilmgandhi	18:6a4db94011d3	492	/* Check the TIM handle allocation */
sahilmgandhi	18:6a4db94011d3	493	if(htim == NULL)
sahilmgandhi	18:6a4db94011d3	494	{
sahilmgandhi	18:6a4db94011d3	495	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	496	}
sahilmgandhi	18:6a4db94011d3	497
sahilmgandhi	18:6a4db94011d3	498	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	499	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	500	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
sahilmgandhi	18:6a4db94011d3	501	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
sahilmgandhi	18:6a4db94011d3	502
sahilmgandhi	18:6a4db94011d3	503	if(htim->State == HAL_TIM_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	504	{
sahilmgandhi	18:6a4db94011d3	505	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	506	htim->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	507	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
sahilmgandhi	18:6a4db94011d3	508	HAL_TIM_OC_MspInit(htim);
sahilmgandhi	18:6a4db94011d3	509	}
sahilmgandhi	18:6a4db94011d3	510
sahilmgandhi	18:6a4db94011d3	511	/* Set the TIM state */
sahilmgandhi	18:6a4db94011d3	512	htim->State= HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	513
sahilmgandhi	18:6a4db94011d3	514	/* Init the base time for the Output Compare */
sahilmgandhi	18:6a4db94011d3	515	TIM_Base_SetConfig(htim->Instance, &htim->Init);
sahilmgandhi	18:6a4db94011d3	516
sahilmgandhi	18:6a4db94011d3	517	/* Initialize the TIM state*/
sahilmgandhi	18:6a4db94011d3	518	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	519
sahilmgandhi	18:6a4db94011d3	520	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	521	}
sahilmgandhi	18:6a4db94011d3	522
sahilmgandhi	18:6a4db94011d3	523	/**
sahilmgandhi	18:6a4db94011d3	524	* @brief DeInitializes the TIM peripheral
sahilmgandhi	18:6a4db94011d3	525	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	526	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	527	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	528	*/
sahilmgandhi	18:6a4db94011d3	529	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	530	{
sahilmgandhi	18:6a4db94011d3	531	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	532	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	533
sahilmgandhi	18:6a4db94011d3	534	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	535
sahilmgandhi	18:6a4db94011d3	536	/* Disable the TIM Peripheral Clock */
sahilmgandhi	18:6a4db94011d3	537	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	538
sahilmgandhi	18:6a4db94011d3	539	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
sahilmgandhi	18:6a4db94011d3	540	HAL_TIM_OC_MspDeInit(htim);
sahilmgandhi	18:6a4db94011d3	541
sahilmgandhi	18:6a4db94011d3	542	/* Change TIM state */
sahilmgandhi	18:6a4db94011d3	543	htim->State = HAL_TIM_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	544
sahilmgandhi	18:6a4db94011d3	545	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	546	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	547
sahilmgandhi	18:6a4db94011d3	548	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	549	}
sahilmgandhi	18:6a4db94011d3	550
sahilmgandhi	18:6a4db94011d3	551	/**
sahilmgandhi	18:6a4db94011d3	552	* @brief Initializes the TIM Output Compare MSP.
sahilmgandhi	18:6a4db94011d3	553	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	554	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	555	* @retval None
sahilmgandhi	18:6a4db94011d3	556	*/
sahilmgandhi	18:6a4db94011d3	557	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	558	{
sahilmgandhi	18:6a4db94011d3	559	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	560	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	561	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	562	the HAL_TIM_OC_MspInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	563	*/
sahilmgandhi	18:6a4db94011d3	564	}
sahilmgandhi	18:6a4db94011d3	565
sahilmgandhi	18:6a4db94011d3	566	/**
sahilmgandhi	18:6a4db94011d3	567	* @brief DeInitializes TIM Output Compare MSP.
sahilmgandhi	18:6a4db94011d3	568	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	569	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	570	* @retval None
sahilmgandhi	18:6a4db94011d3	571	*/
sahilmgandhi	18:6a4db94011d3	572	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	573	{
sahilmgandhi	18:6a4db94011d3	574	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	575	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	576	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	577	the HAL_TIM_OC_MspDeInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	578	*/
sahilmgandhi	18:6a4db94011d3	579	}
sahilmgandhi	18:6a4db94011d3	580
sahilmgandhi	18:6a4db94011d3	581	/**
sahilmgandhi	18:6a4db94011d3	582	* @brief Starts the TIM Output Compare signal generation.
sahilmgandhi	18:6a4db94011d3	583	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	584	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	585	* @param Channel: TIM Channel to be enabled.
sahilmgandhi	18:6a4db94011d3	586	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	587	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	588	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	589	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	590	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	591	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	592	*/
sahilmgandhi	18:6a4db94011d3	593	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	594	{
sahilmgandhi	18:6a4db94011d3	595	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	596	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	597
sahilmgandhi	18:6a4db94011d3	598	/* Enable the Output compare channel */
sahilmgandhi	18:6a4db94011d3	599	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	600
sahilmgandhi	18:6a4db94011d3	601	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	602	{
sahilmgandhi	18:6a4db94011d3	603	/* Enable the main output */
sahilmgandhi	18:6a4db94011d3	604	__HAL_TIM_MOE_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	605	}
sahilmgandhi	18:6a4db94011d3	606
sahilmgandhi	18:6a4db94011d3	607	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	608	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	609
sahilmgandhi	18:6a4db94011d3	610	/* Return function status */
sahilmgandhi	18:6a4db94011d3	611	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	612	}
sahilmgandhi	18:6a4db94011d3	613
sahilmgandhi	18:6a4db94011d3	614	/**
sahilmgandhi	18:6a4db94011d3	615	* @brief Stops the TIM Output Compare signal generation.
sahilmgandhi	18:6a4db94011d3	616	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	617	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	618	* @param Channel: TIM Channel to be disabled.
sahilmgandhi	18:6a4db94011d3	619	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	620	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	621	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	622	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	623	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	624	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	625	*/
sahilmgandhi	18:6a4db94011d3	626	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	627	{
sahilmgandhi	18:6a4db94011d3	628	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	629	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	630
sahilmgandhi	18:6a4db94011d3	631	/* Disable the Output compare channel */
sahilmgandhi	18:6a4db94011d3	632	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	633
sahilmgandhi	18:6a4db94011d3	634	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	635	{
sahilmgandhi	18:6a4db94011d3	636	/* Disable the Main Output */
sahilmgandhi	18:6a4db94011d3	637	__HAL_TIM_MOE_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	638	}
sahilmgandhi	18:6a4db94011d3	639
sahilmgandhi	18:6a4db94011d3	640	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	641	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	642
sahilmgandhi	18:6a4db94011d3	643	/* Return function status */
sahilmgandhi	18:6a4db94011d3	644	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	645	}
sahilmgandhi	18:6a4db94011d3	646
sahilmgandhi	18:6a4db94011d3	647	/**
sahilmgandhi	18:6a4db94011d3	648	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	649	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	650	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	651	* @param Channel: TIM Channel to be enabled.
sahilmgandhi	18:6a4db94011d3	652	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	653	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	654	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	655	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	656	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	657	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	658	*/
sahilmgandhi	18:6a4db94011d3	659	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	660	{
sahilmgandhi	18:6a4db94011d3	661	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	662	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	663
sahilmgandhi	18:6a4db94011d3	664	switch (Channel)
sahilmgandhi	18:6a4db94011d3	665	{
sahilmgandhi	18:6a4db94011d3	666	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	667	{
sahilmgandhi	18:6a4db94011d3	668	/* Enable the TIM Capture/Compare 1 interrupt */
sahilmgandhi	18:6a4db94011d3	669	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	670	}
sahilmgandhi	18:6a4db94011d3	671	break;
sahilmgandhi	18:6a4db94011d3	672
sahilmgandhi	18:6a4db94011d3	673	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	674	{
sahilmgandhi	18:6a4db94011d3	675	/* Enable the TIM Capture/Compare 2 interrupt */
sahilmgandhi	18:6a4db94011d3	676	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	677	}
sahilmgandhi	18:6a4db94011d3	678	break;
sahilmgandhi	18:6a4db94011d3	679
sahilmgandhi	18:6a4db94011d3	680	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	681	{
sahilmgandhi	18:6a4db94011d3	682	/* Enable the TIM Capture/Compare 3 interrupt */
sahilmgandhi	18:6a4db94011d3	683	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
sahilmgandhi	18:6a4db94011d3	684	}
sahilmgandhi	18:6a4db94011d3	685	break;
sahilmgandhi	18:6a4db94011d3	686
sahilmgandhi	18:6a4db94011d3	687	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	688	{
sahilmgandhi	18:6a4db94011d3	689	/* Enable the TIM Capture/Compare 4 interrupt */
sahilmgandhi	18:6a4db94011d3	690	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
sahilmgandhi	18:6a4db94011d3	691	}
sahilmgandhi	18:6a4db94011d3	692	break;
sahilmgandhi	18:6a4db94011d3	693
sahilmgandhi	18:6a4db94011d3	694	default:
sahilmgandhi	18:6a4db94011d3	695	break;
sahilmgandhi	18:6a4db94011d3	696	}
sahilmgandhi	18:6a4db94011d3	697
sahilmgandhi	18:6a4db94011d3	698	/* Enable the Output compare channel */
sahilmgandhi	18:6a4db94011d3	699	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	700
sahilmgandhi	18:6a4db94011d3	701	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	702	{
sahilmgandhi	18:6a4db94011d3	703	/* Enable the main output */
sahilmgandhi	18:6a4db94011d3	704	__HAL_TIM_MOE_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	705	}
sahilmgandhi	18:6a4db94011d3	706
sahilmgandhi	18:6a4db94011d3	707	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	708	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	709
sahilmgandhi	18:6a4db94011d3	710	/* Return function status */
sahilmgandhi	18:6a4db94011d3	711	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	712	}
sahilmgandhi	18:6a4db94011d3	713
sahilmgandhi	18:6a4db94011d3	714	/**
sahilmgandhi	18:6a4db94011d3	715	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	716	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	717	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	718	* @param Channel: TIM Channel to be disabled.
sahilmgandhi	18:6a4db94011d3	719	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	720	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	721	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	722	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	723	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	724	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	725	*/
sahilmgandhi	18:6a4db94011d3	726	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	727	{
sahilmgandhi	18:6a4db94011d3	728	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	729	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	730
sahilmgandhi	18:6a4db94011d3	731	switch (Channel)
sahilmgandhi	18:6a4db94011d3	732	{
sahilmgandhi	18:6a4db94011d3	733	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	734	{
sahilmgandhi	18:6a4db94011d3	735	/* Disable the TIM Capture/Compare 1 interrupt */
sahilmgandhi	18:6a4db94011d3	736	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	737	}
sahilmgandhi	18:6a4db94011d3	738	break;
sahilmgandhi	18:6a4db94011d3	739
sahilmgandhi	18:6a4db94011d3	740	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	741	{
sahilmgandhi	18:6a4db94011d3	742	/* Disable the TIM Capture/Compare 2 interrupt */
sahilmgandhi	18:6a4db94011d3	743	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	744	}
sahilmgandhi	18:6a4db94011d3	745	break;
sahilmgandhi	18:6a4db94011d3	746
sahilmgandhi	18:6a4db94011d3	747	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	748	{
sahilmgandhi	18:6a4db94011d3	749	/* Disable the TIM Capture/Compare 3 interrupt */
sahilmgandhi	18:6a4db94011d3	750	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
sahilmgandhi	18:6a4db94011d3	751	}
sahilmgandhi	18:6a4db94011d3	752	break;
sahilmgandhi	18:6a4db94011d3	753
sahilmgandhi	18:6a4db94011d3	754	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	755	{
sahilmgandhi	18:6a4db94011d3	756	/* Disable the TIM Capture/Compare 4 interrupt */
sahilmgandhi	18:6a4db94011d3	757	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
sahilmgandhi	18:6a4db94011d3	758	}
sahilmgandhi	18:6a4db94011d3	759	break;
sahilmgandhi	18:6a4db94011d3	760
sahilmgandhi	18:6a4db94011d3	761	default:
sahilmgandhi	18:6a4db94011d3	762	break;
sahilmgandhi	18:6a4db94011d3	763	}
sahilmgandhi	18:6a4db94011d3	764
sahilmgandhi	18:6a4db94011d3	765	/* Disable the Output compare channel */
sahilmgandhi	18:6a4db94011d3	766	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	767
sahilmgandhi	18:6a4db94011d3	768	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	769	{
sahilmgandhi	18:6a4db94011d3	770	/* Disable the Main Output */
sahilmgandhi	18:6a4db94011d3	771	__HAL_TIM_MOE_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	772	}
sahilmgandhi	18:6a4db94011d3	773
sahilmgandhi	18:6a4db94011d3	774	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	775	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	776
sahilmgandhi	18:6a4db94011d3	777	/* Return function status */
sahilmgandhi	18:6a4db94011d3	778	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	779	}
sahilmgandhi	18:6a4db94011d3	780
sahilmgandhi	18:6a4db94011d3	781	/**
sahilmgandhi	18:6a4db94011d3	782	* @brief Starts the TIM Output Compare signal generation in DMA mode.
sahilmgandhi	18:6a4db94011d3	783	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	784	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	785	* @param Channel: TIM Channel to be enabled.
sahilmgandhi	18:6a4db94011d3	786	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	787	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	788	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	789	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	790	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	791	* @param pData: The source Buffer address.
sahilmgandhi	18:6a4db94011d3	792	* @param Length: The length of data to be transferred from memory to TIM peripheral
sahilmgandhi	18:6a4db94011d3	793	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	794	*/
sahilmgandhi	18:6a4db94011d3	795	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
sahilmgandhi	18:6a4db94011d3	796	{
sahilmgandhi	18:6a4db94011d3	797	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	798	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	799
sahilmgandhi	18:6a4db94011d3	800	if((htim->State == HAL_TIM_STATE_BUSY))
sahilmgandhi	18:6a4db94011d3	801	{
sahilmgandhi	18:6a4db94011d3	802	return HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	803	}
sahilmgandhi	18:6a4db94011d3	804	else if((htim->State == HAL_TIM_STATE_READY))
sahilmgandhi	18:6a4db94011d3	805	{
sahilmgandhi	18:6a4db94011d3	806	if(((uint32_t)pData == 0U ) && (Length > 0U))
sahilmgandhi	18:6a4db94011d3	807	{
sahilmgandhi	18:6a4db94011d3	808	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	809	}
sahilmgandhi	18:6a4db94011d3	810	else
sahilmgandhi	18:6a4db94011d3	811	{
sahilmgandhi	18:6a4db94011d3	812	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	813	}
sahilmgandhi	18:6a4db94011d3	814	}
sahilmgandhi	18:6a4db94011d3	815	switch (Channel)
sahilmgandhi	18:6a4db94011d3	816	{
sahilmgandhi	18:6a4db94011d3	817	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	818	{
sahilmgandhi	18:6a4db94011d3	819	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	820	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	821
sahilmgandhi	18:6a4db94011d3	822	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	823	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	824
sahilmgandhi	18:6a4db94011d3	825	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	826	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
sahilmgandhi	18:6a4db94011d3	827
sahilmgandhi	18:6a4db94011d3	828	/* Enable the TIM Capture/Compare 1 DMA request */
sahilmgandhi	18:6a4db94011d3	829	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	830	}
sahilmgandhi	18:6a4db94011d3	831	break;
sahilmgandhi	18:6a4db94011d3	832
sahilmgandhi	18:6a4db94011d3	833	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	834	{
sahilmgandhi	18:6a4db94011d3	835	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	836	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	837
sahilmgandhi	18:6a4db94011d3	838	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	839	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	840
sahilmgandhi	18:6a4db94011d3	841	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	842	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
sahilmgandhi	18:6a4db94011d3	843
sahilmgandhi	18:6a4db94011d3	844	/* Enable the TIM Capture/Compare 2 DMA request */
sahilmgandhi	18:6a4db94011d3	845	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	846	}
sahilmgandhi	18:6a4db94011d3	847	break;
sahilmgandhi	18:6a4db94011d3	848
sahilmgandhi	18:6a4db94011d3	849	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	850	{
sahilmgandhi	18:6a4db94011d3	851	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	852	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	853
sahilmgandhi	18:6a4db94011d3	854	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	855	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	856
sahilmgandhi	18:6a4db94011d3	857	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	858	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
sahilmgandhi	18:6a4db94011d3	859
sahilmgandhi	18:6a4db94011d3	860	/* Enable the TIM Capture/Compare 3 DMA request */
sahilmgandhi	18:6a4db94011d3	861	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
sahilmgandhi	18:6a4db94011d3	862	}
sahilmgandhi	18:6a4db94011d3	863	break;
sahilmgandhi	18:6a4db94011d3	864
sahilmgandhi	18:6a4db94011d3	865	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	866	{
sahilmgandhi	18:6a4db94011d3	867	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	868	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	869
sahilmgandhi	18:6a4db94011d3	870	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	871	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	872
sahilmgandhi	18:6a4db94011d3	873	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	874	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
sahilmgandhi	18:6a4db94011d3	875
sahilmgandhi	18:6a4db94011d3	876	/* Enable the TIM Capture/Compare 4 DMA request */
sahilmgandhi	18:6a4db94011d3	877	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
sahilmgandhi	18:6a4db94011d3	878	}
sahilmgandhi	18:6a4db94011d3	879	break;
sahilmgandhi	18:6a4db94011d3	880
sahilmgandhi	18:6a4db94011d3	881	default:
sahilmgandhi	18:6a4db94011d3	882	break;
sahilmgandhi	18:6a4db94011d3	883	}
sahilmgandhi	18:6a4db94011d3	884
sahilmgandhi	18:6a4db94011d3	885	/* Enable the Output compare channel */
sahilmgandhi	18:6a4db94011d3	886	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	887
sahilmgandhi	18:6a4db94011d3	888	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	889	{
sahilmgandhi	18:6a4db94011d3	890	/* Enable the main output */
sahilmgandhi	18:6a4db94011d3	891	__HAL_TIM_MOE_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	892	}
sahilmgandhi	18:6a4db94011d3	893
sahilmgandhi	18:6a4db94011d3	894	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	895	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	896
sahilmgandhi	18:6a4db94011d3	897	/* Return function status */
sahilmgandhi	18:6a4db94011d3	898	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	899	}
sahilmgandhi	18:6a4db94011d3	900
sahilmgandhi	18:6a4db94011d3	901	/**
sahilmgandhi	18:6a4db94011d3	902	* @brief Stops the TIM Output Compare signal generation in DMA mode.
sahilmgandhi	18:6a4db94011d3	903	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	904	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	905	* @param Channel: TIM Channel to be disabled.
sahilmgandhi	18:6a4db94011d3	906	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	907	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	908	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	909	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	910	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	911	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	912	*/
sahilmgandhi	18:6a4db94011d3	913	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	914	{
sahilmgandhi	18:6a4db94011d3	915	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	916	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	917
sahilmgandhi	18:6a4db94011d3	918	switch (Channel)
sahilmgandhi	18:6a4db94011d3	919	{
sahilmgandhi	18:6a4db94011d3	920	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	921	{
sahilmgandhi	18:6a4db94011d3	922	/* Disable the TIM Capture/Compare 1 DMA request */
sahilmgandhi	18:6a4db94011d3	923	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	924	}
sahilmgandhi	18:6a4db94011d3	925	break;
sahilmgandhi	18:6a4db94011d3	926
sahilmgandhi	18:6a4db94011d3	927	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	928	{
sahilmgandhi	18:6a4db94011d3	929	/* Disable the TIM Capture/Compare 2 DMA request */
sahilmgandhi	18:6a4db94011d3	930	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	931	}
sahilmgandhi	18:6a4db94011d3	932	break;
sahilmgandhi	18:6a4db94011d3	933
sahilmgandhi	18:6a4db94011d3	934	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	935	{
sahilmgandhi	18:6a4db94011d3	936	/* Disable the TIM Capture/Compare 3 DMA request */
sahilmgandhi	18:6a4db94011d3	937	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
sahilmgandhi	18:6a4db94011d3	938	}
sahilmgandhi	18:6a4db94011d3	939	break;
sahilmgandhi	18:6a4db94011d3	940
sahilmgandhi	18:6a4db94011d3	941	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	942	{
sahilmgandhi	18:6a4db94011d3	943	/* Disable the TIM Capture/Compare 4 interrupt */
sahilmgandhi	18:6a4db94011d3	944	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
sahilmgandhi	18:6a4db94011d3	945	}
sahilmgandhi	18:6a4db94011d3	946	break;
sahilmgandhi	18:6a4db94011d3	947
sahilmgandhi	18:6a4db94011d3	948	default:
sahilmgandhi	18:6a4db94011d3	949	break;
sahilmgandhi	18:6a4db94011d3	950	}
sahilmgandhi	18:6a4db94011d3	951
sahilmgandhi	18:6a4db94011d3	952	/* Disable the Output compare channel */
sahilmgandhi	18:6a4db94011d3	953	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	954
sahilmgandhi	18:6a4db94011d3	955	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	956	{
sahilmgandhi	18:6a4db94011d3	957	/* Disable the Main Output */
sahilmgandhi	18:6a4db94011d3	958	__HAL_TIM_MOE_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	959	}
sahilmgandhi	18:6a4db94011d3	960
sahilmgandhi	18:6a4db94011d3	961	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	962	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	963
sahilmgandhi	18:6a4db94011d3	964	/* Change the htim state */
sahilmgandhi	18:6a4db94011d3	965	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	966
sahilmgandhi	18:6a4db94011d3	967	/* Return function status */
sahilmgandhi	18:6a4db94011d3	968	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	969	}
sahilmgandhi	18:6a4db94011d3	970	/**
sahilmgandhi	18:6a4db94011d3	971	* @}
sahilmgandhi	18:6a4db94011d3	972	*/
sahilmgandhi	18:6a4db94011d3	973
sahilmgandhi	18:6a4db94011d3	974	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
sahilmgandhi	18:6a4db94011d3	975	* @brief Time PWM functions
sahilmgandhi	18:6a4db94011d3	976	*
sahilmgandhi	18:6a4db94011d3	977	@verbatim
sahilmgandhi	18:6a4db94011d3	978	==============================================================================
sahilmgandhi	18:6a4db94011d3	979	##### Time PWM functions #####
sahilmgandhi	18:6a4db94011d3	980	==============================================================================
sahilmgandhi	18:6a4db94011d3	981	[..]
sahilmgandhi	18:6a4db94011d3	982	This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	983	(+) Initialize and configure the TIM OPWM.
sahilmgandhi	18:6a4db94011d3	984	(+) De-initialize the TIM PWM.
sahilmgandhi	18:6a4db94011d3	985	(+) Start the Time PWM.
sahilmgandhi	18:6a4db94011d3	986	(+) Stop the Time PWM.
sahilmgandhi	18:6a4db94011d3	987	(+) Start the Time PWM and enable interrupt.
sahilmgandhi	18:6a4db94011d3	988	(+) Stop the Time PWM and disable interrupt.
sahilmgandhi	18:6a4db94011d3	989	(+) Start the Time PWM and enable DMA transfer.
sahilmgandhi	18:6a4db94011d3	990	(+) Stop the Time PWM and disable DMA transfer.
sahilmgandhi	18:6a4db94011d3	991
sahilmgandhi	18:6a4db94011d3	992	@endverbatim
sahilmgandhi	18:6a4db94011d3	993	* @{
sahilmgandhi	18:6a4db94011d3	994	*/
sahilmgandhi	18:6a4db94011d3	995	/**
sahilmgandhi	18:6a4db94011d3	996	* @brief Initializes the TIM PWM Time Base according to the specified
sahilmgandhi	18:6a4db94011d3	997	* parameters in the TIM_HandleTypeDef and create the associated handle.
sahilmgandhi	18:6a4db94011d3	998	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	999	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1000	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1001	*/
sahilmgandhi	18:6a4db94011d3	1002	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	1003	{
sahilmgandhi	18:6a4db94011d3	1004	/* Check the TIM handle allocation */
sahilmgandhi	18:6a4db94011d3	1005	if(htim == NULL)
sahilmgandhi	18:6a4db94011d3	1006	{
sahilmgandhi	18:6a4db94011d3	1007	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1008	}
sahilmgandhi	18:6a4db94011d3	1009
sahilmgandhi	18:6a4db94011d3	1010	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1011	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	1012	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
sahilmgandhi	18:6a4db94011d3	1013	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
sahilmgandhi	18:6a4db94011d3	1014
sahilmgandhi	18:6a4db94011d3	1015	if(htim->State == HAL_TIM_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	1016	{
sahilmgandhi	18:6a4db94011d3	1017	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	1018	htim->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	1019	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
sahilmgandhi	18:6a4db94011d3	1020	HAL_TIM_PWM_MspInit(htim);
sahilmgandhi	18:6a4db94011d3	1021	}
sahilmgandhi	18:6a4db94011d3	1022
sahilmgandhi	18:6a4db94011d3	1023	/* Set the TIM state */
sahilmgandhi	18:6a4db94011d3	1024	htim->State= HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1025
sahilmgandhi	18:6a4db94011d3	1026	/* Init the base time for the PWM */
sahilmgandhi	18:6a4db94011d3	1027	TIM_Base_SetConfig(htim->Instance, &htim->Init);
sahilmgandhi	18:6a4db94011d3	1028
sahilmgandhi	18:6a4db94011d3	1029	/* Initialize the TIM state*/
sahilmgandhi	18:6a4db94011d3	1030	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1031
sahilmgandhi	18:6a4db94011d3	1032	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1033	}
sahilmgandhi	18:6a4db94011d3	1034
sahilmgandhi	18:6a4db94011d3	1035	/**
sahilmgandhi	18:6a4db94011d3	1036	* @brief DeInitializes the TIM peripheral
sahilmgandhi	18:6a4db94011d3	1037	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1038	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1039	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1040	*/
sahilmgandhi	18:6a4db94011d3	1041	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	1042	{
sahilmgandhi	18:6a4db94011d3	1043	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1044	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	1045
sahilmgandhi	18:6a4db94011d3	1046	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1047
sahilmgandhi	18:6a4db94011d3	1048	/* Disable the TIM Peripheral Clock */
sahilmgandhi	18:6a4db94011d3	1049	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1050
sahilmgandhi	18:6a4db94011d3	1051	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
sahilmgandhi	18:6a4db94011d3	1052	HAL_TIM_PWM_MspDeInit(htim);
sahilmgandhi	18:6a4db94011d3	1053
sahilmgandhi	18:6a4db94011d3	1054	/* Change TIM state */
sahilmgandhi	18:6a4db94011d3	1055	htim->State = HAL_TIM_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	1056
sahilmgandhi	18:6a4db94011d3	1057	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	1058	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	1059
sahilmgandhi	18:6a4db94011d3	1060	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1061	}
sahilmgandhi	18:6a4db94011d3	1062
sahilmgandhi	18:6a4db94011d3	1063	/**
sahilmgandhi	18:6a4db94011d3	1064	* @brief Initializes the TIM PWM MSP.
sahilmgandhi	18:6a4db94011d3	1065	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1066	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1067	* @retval None
sahilmgandhi	18:6a4db94011d3	1068	*/
sahilmgandhi	18:6a4db94011d3	1069	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	1070	{
sahilmgandhi	18:6a4db94011d3	1071	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1072	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	1073	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1074	the HAL_TIM_PWM_MspInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1075	*/
sahilmgandhi	18:6a4db94011d3	1076	}
sahilmgandhi	18:6a4db94011d3	1077
sahilmgandhi	18:6a4db94011d3	1078	/**
sahilmgandhi	18:6a4db94011d3	1079	* @brief DeInitializes TIM PWM MSP.
sahilmgandhi	18:6a4db94011d3	1080	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1081	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1082	* @retval None
sahilmgandhi	18:6a4db94011d3	1083	*/
sahilmgandhi	18:6a4db94011d3	1084	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	1085	{
sahilmgandhi	18:6a4db94011d3	1086	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1087	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	1088	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1089	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1090	*/
sahilmgandhi	18:6a4db94011d3	1091	}
sahilmgandhi	18:6a4db94011d3	1092
sahilmgandhi	18:6a4db94011d3	1093	/**
sahilmgandhi	18:6a4db94011d3	1094	* @brief Starts the PWM signal generation.
sahilmgandhi	18:6a4db94011d3	1095	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1096	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1097	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	1098	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1099	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1100	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1101	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1102	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1103	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1104	*/
sahilmgandhi	18:6a4db94011d3	1105	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1106	{
sahilmgandhi	18:6a4db94011d3	1107	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1108	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1109
sahilmgandhi	18:6a4db94011d3	1110	/* Enable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	1111	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	1112
sahilmgandhi	18:6a4db94011d3	1113	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	1114	{
sahilmgandhi	18:6a4db94011d3	1115	/* Enable the main output */
sahilmgandhi	18:6a4db94011d3	1116	__HAL_TIM_MOE_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1117	}
sahilmgandhi	18:6a4db94011d3	1118
sahilmgandhi	18:6a4db94011d3	1119	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1120	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1121
sahilmgandhi	18:6a4db94011d3	1122	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1123	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1124	}
sahilmgandhi	18:6a4db94011d3	1125
sahilmgandhi	18:6a4db94011d3	1126	/**
sahilmgandhi	18:6a4db94011d3	1127	* @brief Stops the PWM signal generation.
sahilmgandhi	18:6a4db94011d3	1128	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1129	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1130	* @param Channel: TIM Channels to be disabled.
sahilmgandhi	18:6a4db94011d3	1131	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1132	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1133	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1134	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1135	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1136	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1137	*/
sahilmgandhi	18:6a4db94011d3	1138	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1139	{
sahilmgandhi	18:6a4db94011d3	1140	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1141	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1142
sahilmgandhi	18:6a4db94011d3	1143	/* Disable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	1144	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	1145
sahilmgandhi	18:6a4db94011d3	1146	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	1147	{
sahilmgandhi	18:6a4db94011d3	1148	/* Disable the Main Output */
sahilmgandhi	18:6a4db94011d3	1149	__HAL_TIM_MOE_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1150	}
sahilmgandhi	18:6a4db94011d3	1151
sahilmgandhi	18:6a4db94011d3	1152	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1153	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1154
sahilmgandhi	18:6a4db94011d3	1155	/* Change the htim state */
sahilmgandhi	18:6a4db94011d3	1156	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1157
sahilmgandhi	18:6a4db94011d3	1158	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1159	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1160	}
sahilmgandhi	18:6a4db94011d3	1161
sahilmgandhi	18:6a4db94011d3	1162	/**
sahilmgandhi	18:6a4db94011d3	1163	* @brief Starts the PWM signal generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	1164	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1165	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1166	* @param Channel: TIM Channel to be enabled.
sahilmgandhi	18:6a4db94011d3	1167	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1168	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1169	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1170	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1171	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1172	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1173	*/
sahilmgandhi	18:6a4db94011d3	1174	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1175	{
sahilmgandhi	18:6a4db94011d3	1176	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1177	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1178
sahilmgandhi	18:6a4db94011d3	1179	switch (Channel)
sahilmgandhi	18:6a4db94011d3	1180	{
sahilmgandhi	18:6a4db94011d3	1181	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	1182	{
sahilmgandhi	18:6a4db94011d3	1183	/* Enable the TIM Capture/Compare 1 interrupt */
sahilmgandhi	18:6a4db94011d3	1184	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	1185	}
sahilmgandhi	18:6a4db94011d3	1186	break;
sahilmgandhi	18:6a4db94011d3	1187
sahilmgandhi	18:6a4db94011d3	1188	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	1189	{
sahilmgandhi	18:6a4db94011d3	1190	/* Enable the TIM Capture/Compare 2 interrupt */
sahilmgandhi	18:6a4db94011d3	1191	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	1192	}
sahilmgandhi	18:6a4db94011d3	1193	break;
sahilmgandhi	18:6a4db94011d3	1194
sahilmgandhi	18:6a4db94011d3	1195	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	1196	{
sahilmgandhi	18:6a4db94011d3	1197	/* Enable the TIM Capture/Compare 3 interrupt */
sahilmgandhi	18:6a4db94011d3	1198	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
sahilmgandhi	18:6a4db94011d3	1199	}
sahilmgandhi	18:6a4db94011d3	1200	break;
sahilmgandhi	18:6a4db94011d3	1201
sahilmgandhi	18:6a4db94011d3	1202	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	1203	{
sahilmgandhi	18:6a4db94011d3	1204	/* Enable the TIM Capture/Compare 4 interrupt */
sahilmgandhi	18:6a4db94011d3	1205	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
sahilmgandhi	18:6a4db94011d3	1206	}
sahilmgandhi	18:6a4db94011d3	1207	break;
sahilmgandhi	18:6a4db94011d3	1208
sahilmgandhi	18:6a4db94011d3	1209	default:
sahilmgandhi	18:6a4db94011d3	1210	break;
sahilmgandhi	18:6a4db94011d3	1211	}
sahilmgandhi	18:6a4db94011d3	1212
sahilmgandhi	18:6a4db94011d3	1213	/* Enable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	1214	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	1215
sahilmgandhi	18:6a4db94011d3	1216	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	1217	{
sahilmgandhi	18:6a4db94011d3	1218	/* Enable the main output */
sahilmgandhi	18:6a4db94011d3	1219	__HAL_TIM_MOE_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1220	}
sahilmgandhi	18:6a4db94011d3	1221
sahilmgandhi	18:6a4db94011d3	1222	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1223	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1224
sahilmgandhi	18:6a4db94011d3	1225	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1226	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1227	}
sahilmgandhi	18:6a4db94011d3	1228
sahilmgandhi	18:6a4db94011d3	1229	/**
sahilmgandhi	18:6a4db94011d3	1230	* @brief Stops the PWM signal generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	1231	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1232	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1233	* @param Channel: TIM Channels to be disabled.
sahilmgandhi	18:6a4db94011d3	1234	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1235	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1236	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1237	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1238	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1239	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1240	*/
sahilmgandhi	18:6a4db94011d3	1241	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1242	{
sahilmgandhi	18:6a4db94011d3	1243	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1244	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1245
sahilmgandhi	18:6a4db94011d3	1246	switch (Channel)
sahilmgandhi	18:6a4db94011d3	1247	{
sahilmgandhi	18:6a4db94011d3	1248	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	1249	{
sahilmgandhi	18:6a4db94011d3	1250	/* Disable the TIM Capture/Compare 1 interrupt */
sahilmgandhi	18:6a4db94011d3	1251	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	1252	}
sahilmgandhi	18:6a4db94011d3	1253	break;
sahilmgandhi	18:6a4db94011d3	1254
sahilmgandhi	18:6a4db94011d3	1255	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	1256	{
sahilmgandhi	18:6a4db94011d3	1257	/* Disable the TIM Capture/Compare 2 interrupt */
sahilmgandhi	18:6a4db94011d3	1258	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	1259	}
sahilmgandhi	18:6a4db94011d3	1260	break;
sahilmgandhi	18:6a4db94011d3	1261
sahilmgandhi	18:6a4db94011d3	1262	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	1263	{
sahilmgandhi	18:6a4db94011d3	1264	/* Disable the TIM Capture/Compare 3 interrupt */
sahilmgandhi	18:6a4db94011d3	1265	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
sahilmgandhi	18:6a4db94011d3	1266	}
sahilmgandhi	18:6a4db94011d3	1267	break;
sahilmgandhi	18:6a4db94011d3	1268
sahilmgandhi	18:6a4db94011d3	1269	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	1270	{
sahilmgandhi	18:6a4db94011d3	1271	/* Disable the TIM Capture/Compare 4 interrupt */
sahilmgandhi	18:6a4db94011d3	1272	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
sahilmgandhi	18:6a4db94011d3	1273	}
sahilmgandhi	18:6a4db94011d3	1274	break;
sahilmgandhi	18:6a4db94011d3	1275
sahilmgandhi	18:6a4db94011d3	1276	default:
sahilmgandhi	18:6a4db94011d3	1277	break;
sahilmgandhi	18:6a4db94011d3	1278	}
sahilmgandhi	18:6a4db94011d3	1279
sahilmgandhi	18:6a4db94011d3	1280	/* Disable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	1281	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	1282
sahilmgandhi	18:6a4db94011d3	1283	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	1284	{
sahilmgandhi	18:6a4db94011d3	1285	/* Disable the Main Output */
sahilmgandhi	18:6a4db94011d3	1286	__HAL_TIM_MOE_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1287	}
sahilmgandhi	18:6a4db94011d3	1288
sahilmgandhi	18:6a4db94011d3	1289	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1290	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1291
sahilmgandhi	18:6a4db94011d3	1292	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1293	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1294	}
sahilmgandhi	18:6a4db94011d3	1295
sahilmgandhi	18:6a4db94011d3	1296	/**
sahilmgandhi	18:6a4db94011d3	1297	* @brief Starts the TIM PWM signal generation in DMA mode.
sahilmgandhi	18:6a4db94011d3	1298	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1299	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1300	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	1301	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1302	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1303	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1304	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1305	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1306	* @param pData: The source Buffer address.
sahilmgandhi	18:6a4db94011d3	1307	* @param Length: The length of data to be transferred from memory to TIM peripheral
sahilmgandhi	18:6a4db94011d3	1308	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1309	*/
sahilmgandhi	18:6a4db94011d3	1310	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
sahilmgandhi	18:6a4db94011d3	1311	{
sahilmgandhi	18:6a4db94011d3	1312	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1313	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1314
sahilmgandhi	18:6a4db94011d3	1315	if((htim->State == HAL_TIM_STATE_BUSY))
sahilmgandhi	18:6a4db94011d3	1316	{
sahilmgandhi	18:6a4db94011d3	1317	return HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	1318	}
sahilmgandhi	18:6a4db94011d3	1319	else if((htim->State == HAL_TIM_STATE_READY))
sahilmgandhi	18:6a4db94011d3	1320	{
sahilmgandhi	18:6a4db94011d3	1321	if(((uint32_t)pData == 0U ) && (Length > 0U))
sahilmgandhi	18:6a4db94011d3	1322	{
sahilmgandhi	18:6a4db94011d3	1323	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1324	}
sahilmgandhi	18:6a4db94011d3	1325	else
sahilmgandhi	18:6a4db94011d3	1326	{
sahilmgandhi	18:6a4db94011d3	1327	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1328	}
sahilmgandhi	18:6a4db94011d3	1329	}
sahilmgandhi	18:6a4db94011d3	1330	switch (Channel)
sahilmgandhi	18:6a4db94011d3	1331	{
sahilmgandhi	18:6a4db94011d3	1332	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	1333	{
sahilmgandhi	18:6a4db94011d3	1334	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	1335	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	1336
sahilmgandhi	18:6a4db94011d3	1337	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1338	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	1339
sahilmgandhi	18:6a4db94011d3	1340	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	1341	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
sahilmgandhi	18:6a4db94011d3	1342
sahilmgandhi	18:6a4db94011d3	1343	/* Enable the TIM Capture/Compare 1 DMA request */
sahilmgandhi	18:6a4db94011d3	1344	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	1345	}
sahilmgandhi	18:6a4db94011d3	1346	break;
sahilmgandhi	18:6a4db94011d3	1347
sahilmgandhi	18:6a4db94011d3	1348	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	1349	{
sahilmgandhi	18:6a4db94011d3	1350	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	1351	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	1352
sahilmgandhi	18:6a4db94011d3	1353	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1354	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	1355
sahilmgandhi	18:6a4db94011d3	1356	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	1357	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
sahilmgandhi	18:6a4db94011d3	1358
sahilmgandhi	18:6a4db94011d3	1359	/* Enable the TIM Capture/Compare 2 DMA request */
sahilmgandhi	18:6a4db94011d3	1360	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	1361	}
sahilmgandhi	18:6a4db94011d3	1362	break;
sahilmgandhi	18:6a4db94011d3	1363
sahilmgandhi	18:6a4db94011d3	1364	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	1365	{
sahilmgandhi	18:6a4db94011d3	1366	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	1367	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	1368
sahilmgandhi	18:6a4db94011d3	1369	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1370	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	1371
sahilmgandhi	18:6a4db94011d3	1372	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	1373	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
sahilmgandhi	18:6a4db94011d3	1374
sahilmgandhi	18:6a4db94011d3	1375	/* Enable the TIM Output Capture/Compare 3 request */
sahilmgandhi	18:6a4db94011d3	1376	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
sahilmgandhi	18:6a4db94011d3	1377	}
sahilmgandhi	18:6a4db94011d3	1378	break;
sahilmgandhi	18:6a4db94011d3	1379
sahilmgandhi	18:6a4db94011d3	1380	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	1381	{
sahilmgandhi	18:6a4db94011d3	1382	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	1383	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	1384
sahilmgandhi	18:6a4db94011d3	1385	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1386	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	1387
sahilmgandhi	18:6a4db94011d3	1388	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	1389	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
sahilmgandhi	18:6a4db94011d3	1390
sahilmgandhi	18:6a4db94011d3	1391	/* Enable the TIM Capture/Compare 4 DMA request */
sahilmgandhi	18:6a4db94011d3	1392	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
sahilmgandhi	18:6a4db94011d3	1393	}
sahilmgandhi	18:6a4db94011d3	1394	break;
sahilmgandhi	18:6a4db94011d3	1395
sahilmgandhi	18:6a4db94011d3	1396	default:
sahilmgandhi	18:6a4db94011d3	1397	break;
sahilmgandhi	18:6a4db94011d3	1398	}
sahilmgandhi	18:6a4db94011d3	1399
sahilmgandhi	18:6a4db94011d3	1400	/* Enable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	1401	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	1402
sahilmgandhi	18:6a4db94011d3	1403	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	1404	{
sahilmgandhi	18:6a4db94011d3	1405	/* Enable the main output */
sahilmgandhi	18:6a4db94011d3	1406	__HAL_TIM_MOE_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1407	}
sahilmgandhi	18:6a4db94011d3	1408
sahilmgandhi	18:6a4db94011d3	1409	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1410	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1411
sahilmgandhi	18:6a4db94011d3	1412	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1413	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1414	}
sahilmgandhi	18:6a4db94011d3	1415
sahilmgandhi	18:6a4db94011d3	1416	/**
sahilmgandhi	18:6a4db94011d3	1417	* @brief Stops the TIM PWM signal generation in DMA mode.
sahilmgandhi	18:6a4db94011d3	1418	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1419	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1420	* @param Channel: TIM Channels to be disabled.
sahilmgandhi	18:6a4db94011d3	1421	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1422	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1423	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1424	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1425	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1426	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1427	*/
sahilmgandhi	18:6a4db94011d3	1428	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1429	{
sahilmgandhi	18:6a4db94011d3	1430	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1431	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1432
sahilmgandhi	18:6a4db94011d3	1433	switch (Channel)
sahilmgandhi	18:6a4db94011d3	1434	{
sahilmgandhi	18:6a4db94011d3	1435	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	1436	{
sahilmgandhi	18:6a4db94011d3	1437	/* Disable the TIM Capture/Compare 1 DMA request */
sahilmgandhi	18:6a4db94011d3	1438	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	1439	}
sahilmgandhi	18:6a4db94011d3	1440	break;
sahilmgandhi	18:6a4db94011d3	1441
sahilmgandhi	18:6a4db94011d3	1442	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	1443	{
sahilmgandhi	18:6a4db94011d3	1444	/* Disable the TIM Capture/Compare 2 DMA request */
sahilmgandhi	18:6a4db94011d3	1445	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	1446	}
sahilmgandhi	18:6a4db94011d3	1447	break;
sahilmgandhi	18:6a4db94011d3	1448
sahilmgandhi	18:6a4db94011d3	1449	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	1450	{
sahilmgandhi	18:6a4db94011d3	1451	/* Disable the TIM Capture/Compare 3 DMA request */
sahilmgandhi	18:6a4db94011d3	1452	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
sahilmgandhi	18:6a4db94011d3	1453	}
sahilmgandhi	18:6a4db94011d3	1454	break;
sahilmgandhi	18:6a4db94011d3	1455
sahilmgandhi	18:6a4db94011d3	1456	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	1457	{
sahilmgandhi	18:6a4db94011d3	1458	/* Disable the TIM Capture/Compare 4 interrupt */
sahilmgandhi	18:6a4db94011d3	1459	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
sahilmgandhi	18:6a4db94011d3	1460	}
sahilmgandhi	18:6a4db94011d3	1461	break;
sahilmgandhi	18:6a4db94011d3	1462
sahilmgandhi	18:6a4db94011d3	1463	default:
sahilmgandhi	18:6a4db94011d3	1464	break;
sahilmgandhi	18:6a4db94011d3	1465	}
sahilmgandhi	18:6a4db94011d3	1466
sahilmgandhi	18:6a4db94011d3	1467	/* Disable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	1468	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	1469
sahilmgandhi	18:6a4db94011d3	1470	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	1471	{
sahilmgandhi	18:6a4db94011d3	1472	/* Disable the Main Output */
sahilmgandhi	18:6a4db94011d3	1473	__HAL_TIM_MOE_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1474	}
sahilmgandhi	18:6a4db94011d3	1475
sahilmgandhi	18:6a4db94011d3	1476	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1477	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1478
sahilmgandhi	18:6a4db94011d3	1479	/* Change the htim state */
sahilmgandhi	18:6a4db94011d3	1480	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1481
sahilmgandhi	18:6a4db94011d3	1482	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1483	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1484	}
sahilmgandhi	18:6a4db94011d3	1485	/**
sahilmgandhi	18:6a4db94011d3	1486	* @}
sahilmgandhi	18:6a4db94011d3	1487	*/
sahilmgandhi	18:6a4db94011d3	1488
sahilmgandhi	18:6a4db94011d3	1489	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
sahilmgandhi	18:6a4db94011d3	1490	* @brief Time Input Capture functions
sahilmgandhi	18:6a4db94011d3	1491	*
sahilmgandhi	18:6a4db94011d3	1492	@verbatim
sahilmgandhi	18:6a4db94011d3	1493	==============================================================================
sahilmgandhi	18:6a4db94011d3	1494	##### Time Input Capture functions #####
sahilmgandhi	18:6a4db94011d3	1495	==============================================================================
sahilmgandhi	18:6a4db94011d3	1496	[..]
sahilmgandhi	18:6a4db94011d3	1497	This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	1498	(+) Initialize and configure the TIM Input Capture.
sahilmgandhi	18:6a4db94011d3	1499	(+) De-initialize the TIM Input Capture.
sahilmgandhi	18:6a4db94011d3	1500	(+) Start the Time Input Capture.
sahilmgandhi	18:6a4db94011d3	1501	(+) Stop the Time Input Capture.
sahilmgandhi	18:6a4db94011d3	1502	(+) Start the Time Input Capture and enable interrupt.
sahilmgandhi	18:6a4db94011d3	1503	(+) Stop the Time Input Capture and disable interrupt.
sahilmgandhi	18:6a4db94011d3	1504	(+) Start the Time Input Capture and enable DMA transfer.
sahilmgandhi	18:6a4db94011d3	1505	(+) Stop the Time Input Capture and disable DMA transfer.
sahilmgandhi	18:6a4db94011d3	1506
sahilmgandhi	18:6a4db94011d3	1507	@endverbatim
sahilmgandhi	18:6a4db94011d3	1508	* @{
sahilmgandhi	18:6a4db94011d3	1509	*/
sahilmgandhi	18:6a4db94011d3	1510	/**
sahilmgandhi	18:6a4db94011d3	1511	* @brief Initializes the TIM Input Capture Time base according to the specified
sahilmgandhi	18:6a4db94011d3	1512	* parameters in the TIM_HandleTypeDef and create the associated handle.
sahilmgandhi	18:6a4db94011d3	1513	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1514	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1515	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1516	*/
sahilmgandhi	18:6a4db94011d3	1517	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	1518	{
sahilmgandhi	18:6a4db94011d3	1519	/* Check the TIM handle allocation */
sahilmgandhi	18:6a4db94011d3	1520	if(htim == NULL)
sahilmgandhi	18:6a4db94011d3	1521	{
sahilmgandhi	18:6a4db94011d3	1522	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1523	}
sahilmgandhi	18:6a4db94011d3	1524
sahilmgandhi	18:6a4db94011d3	1525	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1526	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	1527	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
sahilmgandhi	18:6a4db94011d3	1528	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
sahilmgandhi	18:6a4db94011d3	1529
sahilmgandhi	18:6a4db94011d3	1530	if(htim->State == HAL_TIM_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	1531	{
sahilmgandhi	18:6a4db94011d3	1532	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	1533	htim->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	1534	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
sahilmgandhi	18:6a4db94011d3	1535	HAL_TIM_IC_MspInit(htim);
sahilmgandhi	18:6a4db94011d3	1536	}
sahilmgandhi	18:6a4db94011d3	1537
sahilmgandhi	18:6a4db94011d3	1538	/* Set the TIM state */
sahilmgandhi	18:6a4db94011d3	1539	htim->State= HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1540
sahilmgandhi	18:6a4db94011d3	1541	/* Init the base time for the input capture */
sahilmgandhi	18:6a4db94011d3	1542	TIM_Base_SetConfig(htim->Instance, &htim->Init);
sahilmgandhi	18:6a4db94011d3	1543
sahilmgandhi	18:6a4db94011d3	1544	/* Initialize the TIM state*/
sahilmgandhi	18:6a4db94011d3	1545	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1546
sahilmgandhi	18:6a4db94011d3	1547	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1548	}
sahilmgandhi	18:6a4db94011d3	1549
sahilmgandhi	18:6a4db94011d3	1550	/**
sahilmgandhi	18:6a4db94011d3	1551	* @brief DeInitializes the TIM peripheral
sahilmgandhi	18:6a4db94011d3	1552	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1553	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1554	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1555	*/
sahilmgandhi	18:6a4db94011d3	1556	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	1557	{
sahilmgandhi	18:6a4db94011d3	1558	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1559	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	1560
sahilmgandhi	18:6a4db94011d3	1561	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1562
sahilmgandhi	18:6a4db94011d3	1563	/* Disable the TIM Peripheral Clock */
sahilmgandhi	18:6a4db94011d3	1564	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1565
sahilmgandhi	18:6a4db94011d3	1566	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
sahilmgandhi	18:6a4db94011d3	1567	HAL_TIM_IC_MspDeInit(htim);
sahilmgandhi	18:6a4db94011d3	1568
sahilmgandhi	18:6a4db94011d3	1569	/* Change TIM state */
sahilmgandhi	18:6a4db94011d3	1570	htim->State = HAL_TIM_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	1571
sahilmgandhi	18:6a4db94011d3	1572	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	1573	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	1574
sahilmgandhi	18:6a4db94011d3	1575	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1576	}
sahilmgandhi	18:6a4db94011d3	1577
sahilmgandhi	18:6a4db94011d3	1578	/**
sahilmgandhi	18:6a4db94011d3	1579	* @brief Initializes the TIM INput Capture MSP.
sahilmgandhi	18:6a4db94011d3	1580	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1581	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1582	* @retval None
sahilmgandhi	18:6a4db94011d3	1583	*/
sahilmgandhi	18:6a4db94011d3	1584	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	1585	{
sahilmgandhi	18:6a4db94011d3	1586	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1587	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	1588	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1589	the HAL_TIM_IC_MspInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1590	*/
sahilmgandhi	18:6a4db94011d3	1591	}
sahilmgandhi	18:6a4db94011d3	1592
sahilmgandhi	18:6a4db94011d3	1593	/**
sahilmgandhi	18:6a4db94011d3	1594	* @brief DeInitializes TIM Input Capture MSP.
sahilmgandhi	18:6a4db94011d3	1595	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1596	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1597	* @retval None
sahilmgandhi	18:6a4db94011d3	1598	*/
sahilmgandhi	18:6a4db94011d3	1599	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	1600	{
sahilmgandhi	18:6a4db94011d3	1601	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1602	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	1603	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1604	the HAL_TIM_IC_MspDeInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1605	*/
sahilmgandhi	18:6a4db94011d3	1606	}
sahilmgandhi	18:6a4db94011d3	1607
sahilmgandhi	18:6a4db94011d3	1608	/**
sahilmgandhi	18:6a4db94011d3	1609	* @brief Starts the TIM Input Capture measurement.
sahilmgandhi	18:6a4db94011d3	1610	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1611	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1612	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	1613	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1614	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1615	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1616	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1617	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1618	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1619	*/
sahilmgandhi	18:6a4db94011d3	1620	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1621	{
sahilmgandhi	18:6a4db94011d3	1622	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1623	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1624
sahilmgandhi	18:6a4db94011d3	1625	/* Enable the Input Capture channel */
sahilmgandhi	18:6a4db94011d3	1626	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	1627
sahilmgandhi	18:6a4db94011d3	1628	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1629	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1630
sahilmgandhi	18:6a4db94011d3	1631	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1632	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1633	}
sahilmgandhi	18:6a4db94011d3	1634
sahilmgandhi	18:6a4db94011d3	1635	/**
sahilmgandhi	18:6a4db94011d3	1636	* @brief Stops the TIM Input Capture measurement.
sahilmgandhi	18:6a4db94011d3	1637	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1638	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1639	* @param Channel: TIM Channels to be disabled.
sahilmgandhi	18:6a4db94011d3	1640	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1641	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1642	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1643	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1644	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1645	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1646	*/
sahilmgandhi	18:6a4db94011d3	1647	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1648	{
sahilmgandhi	18:6a4db94011d3	1649	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1650	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1651
sahilmgandhi	18:6a4db94011d3	1652	/* Disable the Input Capture channel */
sahilmgandhi	18:6a4db94011d3	1653	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	1654
sahilmgandhi	18:6a4db94011d3	1655	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1656	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1657
sahilmgandhi	18:6a4db94011d3	1658	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1659	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1660	}
sahilmgandhi	18:6a4db94011d3	1661
sahilmgandhi	18:6a4db94011d3	1662	/**
sahilmgandhi	18:6a4db94011d3	1663	* @brief Starts the TIM Input Capture measurement in interrupt mode.
sahilmgandhi	18:6a4db94011d3	1664	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1665	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1666	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	1667	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1668	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1669	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1670	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1671	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1672	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1673	*/
sahilmgandhi	18:6a4db94011d3	1674	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1675	{
sahilmgandhi	18:6a4db94011d3	1676	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1677	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1678
sahilmgandhi	18:6a4db94011d3	1679	switch (Channel)
sahilmgandhi	18:6a4db94011d3	1680	{
sahilmgandhi	18:6a4db94011d3	1681	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	1682	{
sahilmgandhi	18:6a4db94011d3	1683	/* Enable the TIM Capture/Compare 1 interrupt */
sahilmgandhi	18:6a4db94011d3	1684	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	1685	}
sahilmgandhi	18:6a4db94011d3	1686	break;
sahilmgandhi	18:6a4db94011d3	1687
sahilmgandhi	18:6a4db94011d3	1688	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	1689	{
sahilmgandhi	18:6a4db94011d3	1690	/* Enable the TIM Capture/Compare 2 interrupt */
sahilmgandhi	18:6a4db94011d3	1691	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	1692	}
sahilmgandhi	18:6a4db94011d3	1693	break;
sahilmgandhi	18:6a4db94011d3	1694
sahilmgandhi	18:6a4db94011d3	1695	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	1696	{
sahilmgandhi	18:6a4db94011d3	1697	/* Enable the TIM Capture/Compare 3 interrupt */
sahilmgandhi	18:6a4db94011d3	1698	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
sahilmgandhi	18:6a4db94011d3	1699	}
sahilmgandhi	18:6a4db94011d3	1700	break;
sahilmgandhi	18:6a4db94011d3	1701
sahilmgandhi	18:6a4db94011d3	1702	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	1703	{
sahilmgandhi	18:6a4db94011d3	1704	/* Enable the TIM Capture/Compare 4 interrupt */
sahilmgandhi	18:6a4db94011d3	1705	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
sahilmgandhi	18:6a4db94011d3	1706	}
sahilmgandhi	18:6a4db94011d3	1707	break;
sahilmgandhi	18:6a4db94011d3	1708
sahilmgandhi	18:6a4db94011d3	1709	default:
sahilmgandhi	18:6a4db94011d3	1710	break;
sahilmgandhi	18:6a4db94011d3	1711	}
sahilmgandhi	18:6a4db94011d3	1712	/* Enable the Input Capture channel */
sahilmgandhi	18:6a4db94011d3	1713	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	1714
sahilmgandhi	18:6a4db94011d3	1715	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1716	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1717
sahilmgandhi	18:6a4db94011d3	1718	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1719	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1720	}
sahilmgandhi	18:6a4db94011d3	1721
sahilmgandhi	18:6a4db94011d3	1722	/**
sahilmgandhi	18:6a4db94011d3	1723	* @brief Stops the TIM Input Capture measurement in interrupt mode.
sahilmgandhi	18:6a4db94011d3	1724	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1725	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1726	* @param Channel: TIM Channels to be disabled.
sahilmgandhi	18:6a4db94011d3	1727	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1728	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1729	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1730	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1731	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1732	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1733	*/
sahilmgandhi	18:6a4db94011d3	1734	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1735	{
sahilmgandhi	18:6a4db94011d3	1736	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1737	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1738
sahilmgandhi	18:6a4db94011d3	1739	switch (Channel)
sahilmgandhi	18:6a4db94011d3	1740	{
sahilmgandhi	18:6a4db94011d3	1741	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	1742	{
sahilmgandhi	18:6a4db94011d3	1743	/* Disable the TIM Capture/Compare 1 interrupt */
sahilmgandhi	18:6a4db94011d3	1744	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	1745	}
sahilmgandhi	18:6a4db94011d3	1746	break;
sahilmgandhi	18:6a4db94011d3	1747
sahilmgandhi	18:6a4db94011d3	1748	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	1749	{
sahilmgandhi	18:6a4db94011d3	1750	/* Disable the TIM Capture/Compare 2 interrupt */
sahilmgandhi	18:6a4db94011d3	1751	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	1752	}
sahilmgandhi	18:6a4db94011d3	1753	break;
sahilmgandhi	18:6a4db94011d3	1754
sahilmgandhi	18:6a4db94011d3	1755	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	1756	{
sahilmgandhi	18:6a4db94011d3	1757	/* Disable the TIM Capture/Compare 3 interrupt */
sahilmgandhi	18:6a4db94011d3	1758	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
sahilmgandhi	18:6a4db94011d3	1759	}
sahilmgandhi	18:6a4db94011d3	1760	break;
sahilmgandhi	18:6a4db94011d3	1761
sahilmgandhi	18:6a4db94011d3	1762	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	1763	{
sahilmgandhi	18:6a4db94011d3	1764	/* Disable the TIM Capture/Compare 4 interrupt */
sahilmgandhi	18:6a4db94011d3	1765	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
sahilmgandhi	18:6a4db94011d3	1766	}
sahilmgandhi	18:6a4db94011d3	1767	break;
sahilmgandhi	18:6a4db94011d3	1768
sahilmgandhi	18:6a4db94011d3	1769	default:
sahilmgandhi	18:6a4db94011d3	1770	break;
sahilmgandhi	18:6a4db94011d3	1771	}
sahilmgandhi	18:6a4db94011d3	1772
sahilmgandhi	18:6a4db94011d3	1773	/* Disable the Input Capture channel */
sahilmgandhi	18:6a4db94011d3	1774	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	1775
sahilmgandhi	18:6a4db94011d3	1776	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1777	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1778
sahilmgandhi	18:6a4db94011d3	1779	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1780	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1781	}
sahilmgandhi	18:6a4db94011d3	1782
sahilmgandhi	18:6a4db94011d3	1783	/**
sahilmgandhi	18:6a4db94011d3	1784	* @brief Starts the TIM Input Capture measurement on in DMA mode.
sahilmgandhi	18:6a4db94011d3	1785	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1786	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1787	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	1788	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1789	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1790	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1791	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1792	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1793	* @param pData: The destination Buffer address.
sahilmgandhi	18:6a4db94011d3	1794	* @param Length: The length of data to be transferred from TIM peripheral to memory.
sahilmgandhi	18:6a4db94011d3	1795	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1796	*/
sahilmgandhi	18:6a4db94011d3	1797	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
sahilmgandhi	18:6a4db94011d3	1798	{
sahilmgandhi	18:6a4db94011d3	1799	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1800	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1801	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	1802
sahilmgandhi	18:6a4db94011d3	1803	if((htim->State == HAL_TIM_STATE_BUSY))
sahilmgandhi	18:6a4db94011d3	1804	{
sahilmgandhi	18:6a4db94011d3	1805	return HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	1806	}
sahilmgandhi	18:6a4db94011d3	1807	else if((htim->State == HAL_TIM_STATE_READY))
sahilmgandhi	18:6a4db94011d3	1808	{
sahilmgandhi	18:6a4db94011d3	1809	if((pData == 0U ) && (Length > 0U))
sahilmgandhi	18:6a4db94011d3	1810	{
sahilmgandhi	18:6a4db94011d3	1811	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1812	}
sahilmgandhi	18:6a4db94011d3	1813	else
sahilmgandhi	18:6a4db94011d3	1814	{
sahilmgandhi	18:6a4db94011d3	1815	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1816	}
sahilmgandhi	18:6a4db94011d3	1817	}
sahilmgandhi	18:6a4db94011d3	1818
sahilmgandhi	18:6a4db94011d3	1819	switch (Channel)
sahilmgandhi	18:6a4db94011d3	1820	{
sahilmgandhi	18:6a4db94011d3	1821	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	1822	{
sahilmgandhi	18:6a4db94011d3	1823	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	1824	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	1825
sahilmgandhi	18:6a4db94011d3	1826	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1827	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	1828
sahilmgandhi	18:6a4db94011d3	1829	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	1830	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
sahilmgandhi	18:6a4db94011d3	1831
sahilmgandhi	18:6a4db94011d3	1832	/* Enable the TIM Capture/Compare 1 DMA request */
sahilmgandhi	18:6a4db94011d3	1833	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	1834	}
sahilmgandhi	18:6a4db94011d3	1835	break;
sahilmgandhi	18:6a4db94011d3	1836
sahilmgandhi	18:6a4db94011d3	1837	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	1838	{
sahilmgandhi	18:6a4db94011d3	1839	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	1840	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	1841
sahilmgandhi	18:6a4db94011d3	1842	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1843	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	1844
sahilmgandhi	18:6a4db94011d3	1845	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	1846	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
sahilmgandhi	18:6a4db94011d3	1847
sahilmgandhi	18:6a4db94011d3	1848	/* Enable the TIM Capture/Compare 2 DMA request */
sahilmgandhi	18:6a4db94011d3	1849	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	1850	}
sahilmgandhi	18:6a4db94011d3	1851	break;
sahilmgandhi	18:6a4db94011d3	1852
sahilmgandhi	18:6a4db94011d3	1853	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	1854	{
sahilmgandhi	18:6a4db94011d3	1855	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	1856	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	1857
sahilmgandhi	18:6a4db94011d3	1858	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1859	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	1860
sahilmgandhi	18:6a4db94011d3	1861	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	1862	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
sahilmgandhi	18:6a4db94011d3	1863
sahilmgandhi	18:6a4db94011d3	1864	/* Enable the TIM Capture/Compare 3 DMA request */
sahilmgandhi	18:6a4db94011d3	1865	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
sahilmgandhi	18:6a4db94011d3	1866	}
sahilmgandhi	18:6a4db94011d3	1867	break;
sahilmgandhi	18:6a4db94011d3	1868
sahilmgandhi	18:6a4db94011d3	1869	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	1870	{
sahilmgandhi	18:6a4db94011d3	1871	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	1872	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	1873
sahilmgandhi	18:6a4db94011d3	1874	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1875	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	1876
sahilmgandhi	18:6a4db94011d3	1877	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	1878	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
sahilmgandhi	18:6a4db94011d3	1879
sahilmgandhi	18:6a4db94011d3	1880	/* Enable the TIM Capture/Compare 4 DMA request */
sahilmgandhi	18:6a4db94011d3	1881	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
sahilmgandhi	18:6a4db94011d3	1882	}
sahilmgandhi	18:6a4db94011d3	1883	break;
sahilmgandhi	18:6a4db94011d3	1884
sahilmgandhi	18:6a4db94011d3	1885	default:
sahilmgandhi	18:6a4db94011d3	1886	break;
sahilmgandhi	18:6a4db94011d3	1887	}
sahilmgandhi	18:6a4db94011d3	1888
sahilmgandhi	18:6a4db94011d3	1889	/* Enable the Input Capture channel */
sahilmgandhi	18:6a4db94011d3	1890	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	1891
sahilmgandhi	18:6a4db94011d3	1892	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1893	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	1894
sahilmgandhi	18:6a4db94011d3	1895	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1896	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1897	}
sahilmgandhi	18:6a4db94011d3	1898
sahilmgandhi	18:6a4db94011d3	1899	/**
sahilmgandhi	18:6a4db94011d3	1900	* @brief Stops the TIM Input Capture measurement on in DMA mode.
sahilmgandhi	18:6a4db94011d3	1901	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1902	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1903	* @param Channel: TIM Channels to be disabled.
sahilmgandhi	18:6a4db94011d3	1904	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1905	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1906	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1907	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1908	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1909	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1910	*/
sahilmgandhi	18:6a4db94011d3	1911	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	1912	{
sahilmgandhi	18:6a4db94011d3	1913	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1914	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
sahilmgandhi	18:6a4db94011d3	1915	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	1916
sahilmgandhi	18:6a4db94011d3	1917	switch (Channel)
sahilmgandhi	18:6a4db94011d3	1918	{
sahilmgandhi	18:6a4db94011d3	1919	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	1920	{
sahilmgandhi	18:6a4db94011d3	1921	/* Disable the TIM Capture/Compare 1 DMA request */
sahilmgandhi	18:6a4db94011d3	1922	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	1923	}
sahilmgandhi	18:6a4db94011d3	1924	break;
sahilmgandhi	18:6a4db94011d3	1925
sahilmgandhi	18:6a4db94011d3	1926	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	1927	{
sahilmgandhi	18:6a4db94011d3	1928	/* Disable the TIM Capture/Compare 2 DMA request */
sahilmgandhi	18:6a4db94011d3	1929	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	1930	}
sahilmgandhi	18:6a4db94011d3	1931	break;
sahilmgandhi	18:6a4db94011d3	1932
sahilmgandhi	18:6a4db94011d3	1933	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	1934	{
sahilmgandhi	18:6a4db94011d3	1935	/* Disable the TIM Capture/Compare 3 DMA request */
sahilmgandhi	18:6a4db94011d3	1936	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
sahilmgandhi	18:6a4db94011d3	1937	}
sahilmgandhi	18:6a4db94011d3	1938	break;
sahilmgandhi	18:6a4db94011d3	1939
sahilmgandhi	18:6a4db94011d3	1940	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	1941	{
sahilmgandhi	18:6a4db94011d3	1942	/* Disable the TIM Capture/Compare 4 DMA request */
sahilmgandhi	18:6a4db94011d3	1943	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
sahilmgandhi	18:6a4db94011d3	1944	}
sahilmgandhi	18:6a4db94011d3	1945	break;
sahilmgandhi	18:6a4db94011d3	1946
sahilmgandhi	18:6a4db94011d3	1947	default:
sahilmgandhi	18:6a4db94011d3	1948	break;
sahilmgandhi	18:6a4db94011d3	1949	}
sahilmgandhi	18:6a4db94011d3	1950
sahilmgandhi	18:6a4db94011d3	1951	/* Disable the Input Capture channel */
sahilmgandhi	18:6a4db94011d3	1952	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	1953
sahilmgandhi	18:6a4db94011d3	1954	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1955	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	1956
sahilmgandhi	18:6a4db94011d3	1957	/* Change the htim state */
sahilmgandhi	18:6a4db94011d3	1958	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1959
sahilmgandhi	18:6a4db94011d3	1960	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1961	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1962	}
sahilmgandhi	18:6a4db94011d3	1963	/**
sahilmgandhi	18:6a4db94011d3	1964	* @}
sahilmgandhi	18:6a4db94011d3	1965	*/
sahilmgandhi	18:6a4db94011d3	1966
sahilmgandhi	18:6a4db94011d3	1967	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
sahilmgandhi	18:6a4db94011d3	1968	* @brief Time One Pulse functions
sahilmgandhi	18:6a4db94011d3	1969	*
sahilmgandhi	18:6a4db94011d3	1970	@verbatim
sahilmgandhi	18:6a4db94011d3	1971	==============================================================================
sahilmgandhi	18:6a4db94011d3	1972	##### Time One Pulse functions #####
sahilmgandhi	18:6a4db94011d3	1973	==============================================================================
sahilmgandhi	18:6a4db94011d3	1974	[..]
sahilmgandhi	18:6a4db94011d3	1975	This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	1976	(+) Initialize and configure the TIM One Pulse.
sahilmgandhi	18:6a4db94011d3	1977	(+) De-initialize the TIM One Pulse.
sahilmgandhi	18:6a4db94011d3	1978	(+) Start the Time One Pulse.
sahilmgandhi	18:6a4db94011d3	1979	(+) Stop the Time One Pulse.
sahilmgandhi	18:6a4db94011d3	1980	(+) Start the Time One Pulse and enable interrupt.
sahilmgandhi	18:6a4db94011d3	1981	(+) Stop the Time One Pulse and disable interrupt.
sahilmgandhi	18:6a4db94011d3	1982	(+) Start the Time One Pulse and enable DMA transfer.
sahilmgandhi	18:6a4db94011d3	1983	(+) Stop the Time One Pulse and disable DMA transfer.
sahilmgandhi	18:6a4db94011d3	1984
sahilmgandhi	18:6a4db94011d3	1985	@endverbatim
sahilmgandhi	18:6a4db94011d3	1986	* @{
sahilmgandhi	18:6a4db94011d3	1987	*/
sahilmgandhi	18:6a4db94011d3	1988	/**
sahilmgandhi	18:6a4db94011d3	1989	* @brief Initializes the TIM One Pulse Time Base according to the specified
sahilmgandhi	18:6a4db94011d3	1990	* parameters in the TIM_HandleTypeDef and create the associated handle.
sahilmgandhi	18:6a4db94011d3	1991	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1992	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	1993	* @param OnePulseMode: Select the One pulse mode.
sahilmgandhi	18:6a4db94011d3	1994	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1995	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
sahilmgandhi	18:6a4db94011d3	1996	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
sahilmgandhi	18:6a4db94011d3	1997	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1998	*/
sahilmgandhi	18:6a4db94011d3	1999	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
sahilmgandhi	18:6a4db94011d3	2000	{
sahilmgandhi	18:6a4db94011d3	2001	/* Check the TIM handle allocation */
sahilmgandhi	18:6a4db94011d3	2002	if(htim == NULL)
sahilmgandhi	18:6a4db94011d3	2003	{
sahilmgandhi	18:6a4db94011d3	2004	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	2005	}
sahilmgandhi	18:6a4db94011d3	2006
sahilmgandhi	18:6a4db94011d3	2007	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2008	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2009	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
sahilmgandhi	18:6a4db94011d3	2010	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
sahilmgandhi	18:6a4db94011d3	2011	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
sahilmgandhi	18:6a4db94011d3	2012
sahilmgandhi	18:6a4db94011d3	2013	if(htim->State == HAL_TIM_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	2014	{
sahilmgandhi	18:6a4db94011d3	2015	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	2016	htim->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	2017	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
sahilmgandhi	18:6a4db94011d3	2018	HAL_TIM_OnePulse_MspInit(htim);
sahilmgandhi	18:6a4db94011d3	2019	}
sahilmgandhi	18:6a4db94011d3	2020
sahilmgandhi	18:6a4db94011d3	2021	/* Set the TIM state */
sahilmgandhi	18:6a4db94011d3	2022	htim->State= HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	2023
sahilmgandhi	18:6a4db94011d3	2024	/* Configure the Time base in the One Pulse Mode */
sahilmgandhi	18:6a4db94011d3	2025	TIM_Base_SetConfig(htim->Instance, &htim->Init);
sahilmgandhi	18:6a4db94011d3	2026
sahilmgandhi	18:6a4db94011d3	2027	/* Reset the OPM Bit */
sahilmgandhi	18:6a4db94011d3	2028	htim->Instance->CR1 &= ~TIM_CR1_OPM;
sahilmgandhi	18:6a4db94011d3	2029
sahilmgandhi	18:6a4db94011d3	2030	/* Configure the OPM Mode */
sahilmgandhi	18:6a4db94011d3	2031	htim->Instance->CR1 \|= OnePulseMode;
sahilmgandhi	18:6a4db94011d3	2032
sahilmgandhi	18:6a4db94011d3	2033	/* Initialize the TIM state*/
sahilmgandhi	18:6a4db94011d3	2034	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2035
sahilmgandhi	18:6a4db94011d3	2036	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2037	}
sahilmgandhi	18:6a4db94011d3	2038
sahilmgandhi	18:6a4db94011d3	2039	/**
sahilmgandhi	18:6a4db94011d3	2040	* @brief DeInitializes the TIM One Pulse
sahilmgandhi	18:6a4db94011d3	2041	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2042	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2043	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2044	*/
sahilmgandhi	18:6a4db94011d3	2045	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	2046	{
sahilmgandhi	18:6a4db94011d3	2047	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2048	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2049
sahilmgandhi	18:6a4db94011d3	2050	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	2051
sahilmgandhi	18:6a4db94011d3	2052	/* Disable the TIM Peripheral Clock */
sahilmgandhi	18:6a4db94011d3	2053	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2054
sahilmgandhi	18:6a4db94011d3	2055	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
sahilmgandhi	18:6a4db94011d3	2056	HAL_TIM_OnePulse_MspDeInit(htim);
sahilmgandhi	18:6a4db94011d3	2057
sahilmgandhi	18:6a4db94011d3	2058	/* Change TIM state */
sahilmgandhi	18:6a4db94011d3	2059	htim->State = HAL_TIM_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	2060
sahilmgandhi	18:6a4db94011d3	2061	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	2062	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	2063
sahilmgandhi	18:6a4db94011d3	2064	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2065	}
sahilmgandhi	18:6a4db94011d3	2066
sahilmgandhi	18:6a4db94011d3	2067	/**
sahilmgandhi	18:6a4db94011d3	2068	* @brief Initializes the TIM One Pulse MSP.
sahilmgandhi	18:6a4db94011d3	2069	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2070	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2071	* @retval None
sahilmgandhi	18:6a4db94011d3	2072	*/
sahilmgandhi	18:6a4db94011d3	2073	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	2074	{
sahilmgandhi	18:6a4db94011d3	2075	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	2076	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	2077	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	2078	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	2079	*/
sahilmgandhi	18:6a4db94011d3	2080	}
sahilmgandhi	18:6a4db94011d3	2081
sahilmgandhi	18:6a4db94011d3	2082	/**
sahilmgandhi	18:6a4db94011d3	2083	* @brief DeInitializes TIM One Pulse MSP.
sahilmgandhi	18:6a4db94011d3	2084	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2085	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2086	* @retval None
sahilmgandhi	18:6a4db94011d3	2087	*/
sahilmgandhi	18:6a4db94011d3	2088	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	2089	{
sahilmgandhi	18:6a4db94011d3	2090	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	2091	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	2092	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	2093	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	2094	*/
sahilmgandhi	18:6a4db94011d3	2095	}
sahilmgandhi	18:6a4db94011d3	2096
sahilmgandhi	18:6a4db94011d3	2097	/**
sahilmgandhi	18:6a4db94011d3	2098	* @brief Starts the TIM One Pulse signal generation.
sahilmgandhi	18:6a4db94011d3	2099	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2100	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2101	* @param OutputChannel : TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	2102	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2103	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2104	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2105	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2106	*/
sahilmgandhi	18:6a4db94011d3	2107	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
sahilmgandhi	18:6a4db94011d3	2108	{
sahilmgandhi	18:6a4db94011d3	2109	/* Enable the Capture compare and the Input Capture channels
sahilmgandhi	18:6a4db94011d3	2110	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
sahilmgandhi	18:6a4db94011d3	2111	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
sahilmgandhi	18:6a4db94011d3	2112	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
sahilmgandhi	18:6a4db94011d3	2113	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
sahilmgandhi	18:6a4db94011d3	2114
sahilmgandhi	18:6a4db94011d3	2115	No need to enable the counter, it's enabled automatically by hardware
sahilmgandhi	18:6a4db94011d3	2116	(the counter starts in response to a stimulus and generate a pulse */
sahilmgandhi	18:6a4db94011d3	2117
sahilmgandhi	18:6a4db94011d3	2118	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2119	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2120
sahilmgandhi	18:6a4db94011d3	2121	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	2122	{
sahilmgandhi	18:6a4db94011d3	2123	/* Enable the main output */
sahilmgandhi	18:6a4db94011d3	2124	__HAL_TIM_MOE_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	2125	}
sahilmgandhi	18:6a4db94011d3	2126
sahilmgandhi	18:6a4db94011d3	2127	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2128	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2129	}
sahilmgandhi	18:6a4db94011d3	2130
sahilmgandhi	18:6a4db94011d3	2131	/**
sahilmgandhi	18:6a4db94011d3	2132	* @brief Stops the TIM One Pulse signal generation.
sahilmgandhi	18:6a4db94011d3	2133	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2134	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2135	* @param OutputChannel : TIM Channels to be disable.
sahilmgandhi	18:6a4db94011d3	2136	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2137	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2138	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2139	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2140	*/
sahilmgandhi	18:6a4db94011d3	2141	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
sahilmgandhi	18:6a4db94011d3	2142	{
sahilmgandhi	18:6a4db94011d3	2143	/* Disable the Capture compare and the Input Capture channels
sahilmgandhi	18:6a4db94011d3	2144	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
sahilmgandhi	18:6a4db94011d3	2145	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
sahilmgandhi	18:6a4db94011d3	2146	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
sahilmgandhi	18:6a4db94011d3	2147	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
sahilmgandhi	18:6a4db94011d3	2148
sahilmgandhi	18:6a4db94011d3	2149	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2150	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2151
sahilmgandhi	18:6a4db94011d3	2152	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	2153	{
sahilmgandhi	18:6a4db94011d3	2154	/* Disable the Main Output */
sahilmgandhi	18:6a4db94011d3	2155	__HAL_TIM_MOE_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2156	}
sahilmgandhi	18:6a4db94011d3	2157
sahilmgandhi	18:6a4db94011d3	2158	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2159	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2160
sahilmgandhi	18:6a4db94011d3	2161	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2162	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2163	}
sahilmgandhi	18:6a4db94011d3	2164
sahilmgandhi	18:6a4db94011d3	2165	/**
sahilmgandhi	18:6a4db94011d3	2166	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	2167	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2168	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2169	* @param OutputChannel : TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	2170	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2171	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2172	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2173	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2174	*/
sahilmgandhi	18:6a4db94011d3	2175	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
sahilmgandhi	18:6a4db94011d3	2176	{
sahilmgandhi	18:6a4db94011d3	2177	/* Enable the Capture compare and the Input Capture channels
sahilmgandhi	18:6a4db94011d3	2178	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
sahilmgandhi	18:6a4db94011d3	2179	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
sahilmgandhi	18:6a4db94011d3	2180	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
sahilmgandhi	18:6a4db94011d3	2181	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
sahilmgandhi	18:6a4db94011d3	2182
sahilmgandhi	18:6a4db94011d3	2183	No need to enable the counter, it's enabled automatically by hardware
sahilmgandhi	18:6a4db94011d3	2184	(the counter starts in response to a stimulus and generate a pulse */
sahilmgandhi	18:6a4db94011d3	2185
sahilmgandhi	18:6a4db94011d3	2186	/* Enable the TIM Capture/Compare 1 interrupt */
sahilmgandhi	18:6a4db94011d3	2187	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	2188
sahilmgandhi	18:6a4db94011d3	2189	/* Enable the TIM Capture/Compare 2 interrupt */
sahilmgandhi	18:6a4db94011d3	2190	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	2191
sahilmgandhi	18:6a4db94011d3	2192	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2193	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2194
sahilmgandhi	18:6a4db94011d3	2195	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	2196	{
sahilmgandhi	18:6a4db94011d3	2197	/* Enable the main output */
sahilmgandhi	18:6a4db94011d3	2198	__HAL_TIM_MOE_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	2199	}
sahilmgandhi	18:6a4db94011d3	2200
sahilmgandhi	18:6a4db94011d3	2201	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2202	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2203	}
sahilmgandhi	18:6a4db94011d3	2204
sahilmgandhi	18:6a4db94011d3	2205	/**
sahilmgandhi	18:6a4db94011d3	2206	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	2207	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2208	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2209	* @param OutputChannel : TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	2210	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2211	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2212	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2213	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2214	*/
sahilmgandhi	18:6a4db94011d3	2215	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
sahilmgandhi	18:6a4db94011d3	2216	{
sahilmgandhi	18:6a4db94011d3	2217	/* Disable the TIM Capture/Compare 1 interrupt */
sahilmgandhi	18:6a4db94011d3	2218	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	2219
sahilmgandhi	18:6a4db94011d3	2220	/* Disable the TIM Capture/Compare 2 interrupt */
sahilmgandhi	18:6a4db94011d3	2221	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	2222
sahilmgandhi	18:6a4db94011d3	2223	/* Disable the Capture compare and the Input Capture channels
sahilmgandhi	18:6a4db94011d3	2224	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
sahilmgandhi	18:6a4db94011d3	2225	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
sahilmgandhi	18:6a4db94011d3	2226	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
sahilmgandhi	18:6a4db94011d3	2227	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
sahilmgandhi	18:6a4db94011d3	2228	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2229	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2230
sahilmgandhi	18:6a4db94011d3	2231	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
sahilmgandhi	18:6a4db94011d3	2232	{
sahilmgandhi	18:6a4db94011d3	2233	/* Disable the Main Output */
sahilmgandhi	18:6a4db94011d3	2234	__HAL_TIM_MOE_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2235	}
sahilmgandhi	18:6a4db94011d3	2236
sahilmgandhi	18:6a4db94011d3	2237	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2238	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2239
sahilmgandhi	18:6a4db94011d3	2240	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2241	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2242	}
sahilmgandhi	18:6a4db94011d3	2243	/**
sahilmgandhi	18:6a4db94011d3	2244	* @}
sahilmgandhi	18:6a4db94011d3	2245	*/
sahilmgandhi	18:6a4db94011d3	2246
sahilmgandhi	18:6a4db94011d3	2247	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
sahilmgandhi	18:6a4db94011d3	2248	* @brief Time Encoder functions
sahilmgandhi	18:6a4db94011d3	2249	*
sahilmgandhi	18:6a4db94011d3	2250	@verbatim
sahilmgandhi	18:6a4db94011d3	2251	==============================================================================
sahilmgandhi	18:6a4db94011d3	2252	##### Time Encoder functions #####
sahilmgandhi	18:6a4db94011d3	2253	==============================================================================
sahilmgandhi	18:6a4db94011d3	2254	[..]
sahilmgandhi	18:6a4db94011d3	2255	This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	2256	(+) Initialize and configure the TIM Encoder.
sahilmgandhi	18:6a4db94011d3	2257	(+) De-initialize the TIM Encoder.
sahilmgandhi	18:6a4db94011d3	2258	(+) Start the Time Encoder.
sahilmgandhi	18:6a4db94011d3	2259	(+) Stop the Time Encoder.
sahilmgandhi	18:6a4db94011d3	2260	(+) Start the Time Encoder and enable interrupt.
sahilmgandhi	18:6a4db94011d3	2261	(+) Stop the Time Encoder and disable interrupt.
sahilmgandhi	18:6a4db94011d3	2262	(+) Start the Time Encoder and enable DMA transfer.
sahilmgandhi	18:6a4db94011d3	2263	(+) Stop the Time Encoder and disable DMA transfer.
sahilmgandhi	18:6a4db94011d3	2264
sahilmgandhi	18:6a4db94011d3	2265	@endverbatim
sahilmgandhi	18:6a4db94011d3	2266	* @{
sahilmgandhi	18:6a4db94011d3	2267	*/
sahilmgandhi	18:6a4db94011d3	2268	/**
sahilmgandhi	18:6a4db94011d3	2269	* @brief Initializes the TIM Encoder Interface and create the associated handle.
sahilmgandhi	18:6a4db94011d3	2270	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2271	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2272	* @param sConfig: TIM Encoder Interface configuration structure
sahilmgandhi	18:6a4db94011d3	2273	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2274	*/
sahilmgandhi	18:6a4db94011d3	2275	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
sahilmgandhi	18:6a4db94011d3	2276	{
sahilmgandhi	18:6a4db94011d3	2277	uint32_t tmpsmcr = 0U;
sahilmgandhi	18:6a4db94011d3	2278	uint32_t tmpccmr1 = 0U;
sahilmgandhi	18:6a4db94011d3	2279	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	2280
sahilmgandhi	18:6a4db94011d3	2281	/* Check the TIM handle allocation */
sahilmgandhi	18:6a4db94011d3	2282	if(htim == NULL)
sahilmgandhi	18:6a4db94011d3	2283	{
sahilmgandhi	18:6a4db94011d3	2284	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	2285	}
sahilmgandhi	18:6a4db94011d3	2286
sahilmgandhi	18:6a4db94011d3	2287	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2288	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2289	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
sahilmgandhi	18:6a4db94011d3	2290	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
sahilmgandhi	18:6a4db94011d3	2291	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
sahilmgandhi	18:6a4db94011d3	2292	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
sahilmgandhi	18:6a4db94011d3	2293	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
sahilmgandhi	18:6a4db94011d3	2294	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
sahilmgandhi	18:6a4db94011d3	2295	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
sahilmgandhi	18:6a4db94011d3	2296	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
sahilmgandhi	18:6a4db94011d3	2297	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
sahilmgandhi	18:6a4db94011d3	2298
sahilmgandhi	18:6a4db94011d3	2299	if(htim->State == HAL_TIM_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	2300	{
sahilmgandhi	18:6a4db94011d3	2301	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	2302	htim->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	2303	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
sahilmgandhi	18:6a4db94011d3	2304	HAL_TIM_Encoder_MspInit(htim);
sahilmgandhi	18:6a4db94011d3	2305	}
sahilmgandhi	18:6a4db94011d3	2306
sahilmgandhi	18:6a4db94011d3	2307	/* Set the TIM state */
sahilmgandhi	18:6a4db94011d3	2308	htim->State= HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	2309
sahilmgandhi	18:6a4db94011d3	2310	/* Reset the SMS bits */
sahilmgandhi	18:6a4db94011d3	2311	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
sahilmgandhi	18:6a4db94011d3	2312
sahilmgandhi	18:6a4db94011d3	2313	/* Configure the Time base in the Encoder Mode */
sahilmgandhi	18:6a4db94011d3	2314	TIM_Base_SetConfig(htim->Instance, &htim->Init);
sahilmgandhi	18:6a4db94011d3	2315
sahilmgandhi	18:6a4db94011d3	2316	/* Get the TIMx SMCR register value */
sahilmgandhi	18:6a4db94011d3	2317	tmpsmcr = htim->Instance->SMCR;
sahilmgandhi	18:6a4db94011d3	2318
sahilmgandhi	18:6a4db94011d3	2319	/* Get the TIMx CCMR1 register value */
sahilmgandhi	18:6a4db94011d3	2320	tmpccmr1 = htim->Instance->CCMR1;
sahilmgandhi	18:6a4db94011d3	2321
sahilmgandhi	18:6a4db94011d3	2322	/* Get the TIMx CCER register value */
sahilmgandhi	18:6a4db94011d3	2323	tmpccer = htim->Instance->CCER;
sahilmgandhi	18:6a4db94011d3	2324
sahilmgandhi	18:6a4db94011d3	2325	/* Set the encoder Mode */
sahilmgandhi	18:6a4db94011d3	2326	tmpsmcr \|= sConfig->EncoderMode;
sahilmgandhi	18:6a4db94011d3	2327
sahilmgandhi	18:6a4db94011d3	2328	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
sahilmgandhi	18:6a4db94011d3	2329	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
sahilmgandhi	18:6a4db94011d3	2330	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8U));
sahilmgandhi	18:6a4db94011d3	2331
sahilmgandhi	18:6a4db94011d3	2332	/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
sahilmgandhi	18:6a4db94011d3	2333	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
sahilmgandhi	18:6a4db94011d3	2334	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
sahilmgandhi	18:6a4db94011d3	2335	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8U);
sahilmgandhi	18:6a4db94011d3	2336	tmpccmr1 \|= (sConfig->IC1Filter << 4U) \| (sConfig->IC2Filter << 12U);
sahilmgandhi	18:6a4db94011d3	2337
sahilmgandhi	18:6a4db94011d3	2338	/* Set the TI1 and the TI2 Polarities */
sahilmgandhi	18:6a4db94011d3	2339	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
sahilmgandhi	18:6a4db94011d3	2340	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
sahilmgandhi	18:6a4db94011d3	2341	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4U);
sahilmgandhi	18:6a4db94011d3	2342
sahilmgandhi	18:6a4db94011d3	2343	/* Write to TIMx SMCR */
sahilmgandhi	18:6a4db94011d3	2344	htim->Instance->SMCR = tmpsmcr;
sahilmgandhi	18:6a4db94011d3	2345
sahilmgandhi	18:6a4db94011d3	2346	/* Write to TIMx CCMR1 */
sahilmgandhi	18:6a4db94011d3	2347	htim->Instance->CCMR1 = tmpccmr1;
sahilmgandhi	18:6a4db94011d3	2348
sahilmgandhi	18:6a4db94011d3	2349	/* Write to TIMx CCER */
sahilmgandhi	18:6a4db94011d3	2350	htim->Instance->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	2351
sahilmgandhi	18:6a4db94011d3	2352	/* Initialize the TIM state*/
sahilmgandhi	18:6a4db94011d3	2353	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2354
sahilmgandhi	18:6a4db94011d3	2355	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2356	}
sahilmgandhi	18:6a4db94011d3	2357
sahilmgandhi	18:6a4db94011d3	2358	/**
sahilmgandhi	18:6a4db94011d3	2359	* @brief DeInitializes the TIM Encoder interface
sahilmgandhi	18:6a4db94011d3	2360	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2361	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2362	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2363	*/
sahilmgandhi	18:6a4db94011d3	2364	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	2365	{
sahilmgandhi	18:6a4db94011d3	2366	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2367	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2368
sahilmgandhi	18:6a4db94011d3	2369	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	2370
sahilmgandhi	18:6a4db94011d3	2371	/* Disable the TIM Peripheral Clock */
sahilmgandhi	18:6a4db94011d3	2372	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2373
sahilmgandhi	18:6a4db94011d3	2374	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
sahilmgandhi	18:6a4db94011d3	2375	HAL_TIM_Encoder_MspDeInit(htim);
sahilmgandhi	18:6a4db94011d3	2376
sahilmgandhi	18:6a4db94011d3	2377	/* Change TIM state */
sahilmgandhi	18:6a4db94011d3	2378	htim->State = HAL_TIM_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	2379
sahilmgandhi	18:6a4db94011d3	2380	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	2381	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	2382
sahilmgandhi	18:6a4db94011d3	2383	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2384	}
sahilmgandhi	18:6a4db94011d3	2385
sahilmgandhi	18:6a4db94011d3	2386	/**
sahilmgandhi	18:6a4db94011d3	2387	* @brief Initializes the TIM Encoder Interface MSP.
sahilmgandhi	18:6a4db94011d3	2388	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2389	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2390	* @retval None
sahilmgandhi	18:6a4db94011d3	2391	*/
sahilmgandhi	18:6a4db94011d3	2392	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	2393	{
sahilmgandhi	18:6a4db94011d3	2394	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	2395	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	2396	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	2397	the HAL_TIM_Encoder_MspInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	2398	*/
sahilmgandhi	18:6a4db94011d3	2399	}
sahilmgandhi	18:6a4db94011d3	2400
sahilmgandhi	18:6a4db94011d3	2401	/**
sahilmgandhi	18:6a4db94011d3	2402	* @brief DeInitializes TIM Encoder Interface MSP.
sahilmgandhi	18:6a4db94011d3	2403	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2404	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2405	* @retval None
sahilmgandhi	18:6a4db94011d3	2406	*/
sahilmgandhi	18:6a4db94011d3	2407	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	2408	{
sahilmgandhi	18:6a4db94011d3	2409	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	2410	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	2411	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	2412	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	2413	*/
sahilmgandhi	18:6a4db94011d3	2414	}
sahilmgandhi	18:6a4db94011d3	2415
sahilmgandhi	18:6a4db94011d3	2416	/**
sahilmgandhi	18:6a4db94011d3	2417	* @brief Starts the TIM Encoder Interface.
sahilmgandhi	18:6a4db94011d3	2418	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2419	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2420	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	2421	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2422	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2423	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2424	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
sahilmgandhi	18:6a4db94011d3	2425	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2426	*/
sahilmgandhi	18:6a4db94011d3	2427	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	2428	{
sahilmgandhi	18:6a4db94011d3	2429	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2430	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2431
sahilmgandhi	18:6a4db94011d3	2432	/* Enable the encoder interface channels */
sahilmgandhi	18:6a4db94011d3	2433	switch (Channel)
sahilmgandhi	18:6a4db94011d3	2434	{
sahilmgandhi	18:6a4db94011d3	2435	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	2436	{
sahilmgandhi	18:6a4db94011d3	2437	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2438	break;
sahilmgandhi	18:6a4db94011d3	2439	}
sahilmgandhi	18:6a4db94011d3	2440	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	2441	{
sahilmgandhi	18:6a4db94011d3	2442	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2443	break;
sahilmgandhi	18:6a4db94011d3	2444	}
sahilmgandhi	18:6a4db94011d3	2445	default :
sahilmgandhi	18:6a4db94011d3	2446	{
sahilmgandhi	18:6a4db94011d3	2447	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2448	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2449	break;
sahilmgandhi	18:6a4db94011d3	2450	}
sahilmgandhi	18:6a4db94011d3	2451	}
sahilmgandhi	18:6a4db94011d3	2452	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2453	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	2454
sahilmgandhi	18:6a4db94011d3	2455	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2456	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2457	}
sahilmgandhi	18:6a4db94011d3	2458
sahilmgandhi	18:6a4db94011d3	2459	/**
sahilmgandhi	18:6a4db94011d3	2460	* @brief Stops the TIM Encoder Interface.
sahilmgandhi	18:6a4db94011d3	2461	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2462	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2463	* @param Channel: TIM Channels to be disabled.
sahilmgandhi	18:6a4db94011d3	2464	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2465	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2466	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2467	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
sahilmgandhi	18:6a4db94011d3	2468	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2469	*/
sahilmgandhi	18:6a4db94011d3	2470	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	2471	{
sahilmgandhi	18:6a4db94011d3	2472	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2473	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2474
sahilmgandhi	18:6a4db94011d3	2475	/* Disable the Input Capture channels 1 and 2
sahilmgandhi	18:6a4db94011d3	2476	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
sahilmgandhi	18:6a4db94011d3	2477	switch (Channel)
sahilmgandhi	18:6a4db94011d3	2478	{
sahilmgandhi	18:6a4db94011d3	2479	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	2480	{
sahilmgandhi	18:6a4db94011d3	2481	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2482	break;
sahilmgandhi	18:6a4db94011d3	2483	}
sahilmgandhi	18:6a4db94011d3	2484	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	2485	{
sahilmgandhi	18:6a4db94011d3	2486	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2487	break;
sahilmgandhi	18:6a4db94011d3	2488	}
sahilmgandhi	18:6a4db94011d3	2489	default :
sahilmgandhi	18:6a4db94011d3	2490	{
sahilmgandhi	18:6a4db94011d3	2491	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2492	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2493	break;
sahilmgandhi	18:6a4db94011d3	2494	}
sahilmgandhi	18:6a4db94011d3	2495	}
sahilmgandhi	18:6a4db94011d3	2496	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2497	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2498
sahilmgandhi	18:6a4db94011d3	2499	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2500	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2501	}
sahilmgandhi	18:6a4db94011d3	2502
sahilmgandhi	18:6a4db94011d3	2503	/**
sahilmgandhi	18:6a4db94011d3	2504	* @brief Starts the TIM Encoder Interface in interrupt mode.
sahilmgandhi	18:6a4db94011d3	2505	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2506	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2507	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	2508	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2509	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2510	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2511	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
sahilmgandhi	18:6a4db94011d3	2512	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2513	*/
sahilmgandhi	18:6a4db94011d3	2514	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	2515	{
sahilmgandhi	18:6a4db94011d3	2516	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2517	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2518
sahilmgandhi	18:6a4db94011d3	2519	/* Enable the encoder interface channels */
sahilmgandhi	18:6a4db94011d3	2520	/* Enable the capture compare Interrupts 1 and/or 2 */
sahilmgandhi	18:6a4db94011d3	2521	switch (Channel)
sahilmgandhi	18:6a4db94011d3	2522	{
sahilmgandhi	18:6a4db94011d3	2523	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	2524	{
sahilmgandhi	18:6a4db94011d3	2525	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2526	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	2527	break;
sahilmgandhi	18:6a4db94011d3	2528	}
sahilmgandhi	18:6a4db94011d3	2529	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	2530	{
sahilmgandhi	18:6a4db94011d3	2531	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2532	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	2533	break;
sahilmgandhi	18:6a4db94011d3	2534	}
sahilmgandhi	18:6a4db94011d3	2535	default :
sahilmgandhi	18:6a4db94011d3	2536	{
sahilmgandhi	18:6a4db94011d3	2537	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2538	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2539	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	2540	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	2541	break;
sahilmgandhi	18:6a4db94011d3	2542	}
sahilmgandhi	18:6a4db94011d3	2543	}
sahilmgandhi	18:6a4db94011d3	2544
sahilmgandhi	18:6a4db94011d3	2545	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2546	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	2547
sahilmgandhi	18:6a4db94011d3	2548	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2549	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2550	}
sahilmgandhi	18:6a4db94011d3	2551
sahilmgandhi	18:6a4db94011d3	2552	/**
sahilmgandhi	18:6a4db94011d3	2553	* @brief Stops the TIM Encoder Interface in interrupt mode.
sahilmgandhi	18:6a4db94011d3	2554	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2555	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2556	* @param Channel: TIM Channels to be disabled.
sahilmgandhi	18:6a4db94011d3	2557	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2558	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2559	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2560	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
sahilmgandhi	18:6a4db94011d3	2561	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2562	*/
sahilmgandhi	18:6a4db94011d3	2563	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	2564	{
sahilmgandhi	18:6a4db94011d3	2565	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2566	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2567
sahilmgandhi	18:6a4db94011d3	2568	/* Disable the Input Capture channels 1 and 2
sahilmgandhi	18:6a4db94011d3	2569	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
sahilmgandhi	18:6a4db94011d3	2570	if(Channel == TIM_CHANNEL_1)
sahilmgandhi	18:6a4db94011d3	2571	{
sahilmgandhi	18:6a4db94011d3	2572	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2573
sahilmgandhi	18:6a4db94011d3	2574	/* Disable the capture compare Interrupts 1 */
sahilmgandhi	18:6a4db94011d3	2575	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	2576	}
sahilmgandhi	18:6a4db94011d3	2577	else if(Channel == TIM_CHANNEL_2)
sahilmgandhi	18:6a4db94011d3	2578	{
sahilmgandhi	18:6a4db94011d3	2579	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2580
sahilmgandhi	18:6a4db94011d3	2581	/* Disable the capture compare Interrupts 2 */
sahilmgandhi	18:6a4db94011d3	2582	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	2583	}
sahilmgandhi	18:6a4db94011d3	2584	else
sahilmgandhi	18:6a4db94011d3	2585	{
sahilmgandhi	18:6a4db94011d3	2586	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2587	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2588
sahilmgandhi	18:6a4db94011d3	2589	/* Disable the capture compare Interrupts 1 and 2 */
sahilmgandhi	18:6a4db94011d3	2590	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	2591	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	2592	}
sahilmgandhi	18:6a4db94011d3	2593
sahilmgandhi	18:6a4db94011d3	2594	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2595	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2596
sahilmgandhi	18:6a4db94011d3	2597	/* Change the htim state */
sahilmgandhi	18:6a4db94011d3	2598	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2599
sahilmgandhi	18:6a4db94011d3	2600	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2601	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2602	}
sahilmgandhi	18:6a4db94011d3	2603
sahilmgandhi	18:6a4db94011d3	2604	/**
sahilmgandhi	18:6a4db94011d3	2605	* @brief Starts the TIM Encoder Interface in DMA mode.
sahilmgandhi	18:6a4db94011d3	2606	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2607	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2608	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	2609	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2610	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2611	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2612	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
sahilmgandhi	18:6a4db94011d3	2613	* @param pData1: The destination Buffer address for IC1.
sahilmgandhi	18:6a4db94011d3	2614	* @param pData2: The destination Buffer address for IC2.
sahilmgandhi	18:6a4db94011d3	2615	* @param Length: The length of data to be transferred from TIM peripheral to memory.
sahilmgandhi	18:6a4db94011d3	2616	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2617	*/
sahilmgandhi	18:6a4db94011d3	2618	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
sahilmgandhi	18:6a4db94011d3	2619	{
sahilmgandhi	18:6a4db94011d3	2620	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2621	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2622
sahilmgandhi	18:6a4db94011d3	2623	if((htim->State == HAL_TIM_STATE_BUSY))
sahilmgandhi	18:6a4db94011d3	2624	{
sahilmgandhi	18:6a4db94011d3	2625	return HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	2626	}
sahilmgandhi	18:6a4db94011d3	2627	else if((htim->State == HAL_TIM_STATE_READY))
sahilmgandhi	18:6a4db94011d3	2628	{
sahilmgandhi	18:6a4db94011d3	2629	if((((pData1 == 0U) \|\| (pData2 == 0U) )) && (Length > 0U))
sahilmgandhi	18:6a4db94011d3	2630	{
sahilmgandhi	18:6a4db94011d3	2631	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	2632	}
sahilmgandhi	18:6a4db94011d3	2633	else
sahilmgandhi	18:6a4db94011d3	2634	{
sahilmgandhi	18:6a4db94011d3	2635	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	2636	}
sahilmgandhi	18:6a4db94011d3	2637	}
sahilmgandhi	18:6a4db94011d3	2638
sahilmgandhi	18:6a4db94011d3	2639	switch (Channel)
sahilmgandhi	18:6a4db94011d3	2640	{
sahilmgandhi	18:6a4db94011d3	2641	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	2642	{
sahilmgandhi	18:6a4db94011d3	2643	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	2644	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	2645
sahilmgandhi	18:6a4db94011d3	2646	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	2647	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	2648
sahilmgandhi	18:6a4db94011d3	2649	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	2650	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
sahilmgandhi	18:6a4db94011d3	2651
sahilmgandhi	18:6a4db94011d3	2652	/* Enable the TIM Input Capture DMA request */
sahilmgandhi	18:6a4db94011d3	2653	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	2654
sahilmgandhi	18:6a4db94011d3	2655	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2656	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	2657
sahilmgandhi	18:6a4db94011d3	2658	/* Enable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	2659	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2660	}
sahilmgandhi	18:6a4db94011d3	2661	break;
sahilmgandhi	18:6a4db94011d3	2662
sahilmgandhi	18:6a4db94011d3	2663	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	2664	{
sahilmgandhi	18:6a4db94011d3	2665	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	2666	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	2667
sahilmgandhi	18:6a4db94011d3	2668	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	2669	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
sahilmgandhi	18:6a4db94011d3	2670	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	2671	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
sahilmgandhi	18:6a4db94011d3	2672
sahilmgandhi	18:6a4db94011d3	2673	/* Enable the TIM Input Capture DMA request */
sahilmgandhi	18:6a4db94011d3	2674	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	2675
sahilmgandhi	18:6a4db94011d3	2676	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2677	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	2678
sahilmgandhi	18:6a4db94011d3	2679	/* Enable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	2680	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2681	}
sahilmgandhi	18:6a4db94011d3	2682	break;
sahilmgandhi	18:6a4db94011d3	2683
sahilmgandhi	18:6a4db94011d3	2684	case TIM_CHANNEL_ALL:
sahilmgandhi	18:6a4db94011d3	2685	{
sahilmgandhi	18:6a4db94011d3	2686	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	2687	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	2688
sahilmgandhi	18:6a4db94011d3	2689	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	2690	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	2691
sahilmgandhi	18:6a4db94011d3	2692	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	2693	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
sahilmgandhi	18:6a4db94011d3	2694
sahilmgandhi	18:6a4db94011d3	2695	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	2696	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	2697
sahilmgandhi	18:6a4db94011d3	2698	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	2699	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	2700
sahilmgandhi	18:6a4db94011d3	2701	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	2702	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
sahilmgandhi	18:6a4db94011d3	2703
sahilmgandhi	18:6a4db94011d3	2704	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2705	__HAL_TIM_ENABLE(htim);
sahilmgandhi	18:6a4db94011d3	2706
sahilmgandhi	18:6a4db94011d3	2707	/* Enable the Capture compare channel */
sahilmgandhi	18:6a4db94011d3	2708	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2709	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
sahilmgandhi	18:6a4db94011d3	2710
sahilmgandhi	18:6a4db94011d3	2711	/* Enable the TIM Input Capture DMA request */
sahilmgandhi	18:6a4db94011d3	2712	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	2713	/* Enable the TIM Input Capture DMA request */
sahilmgandhi	18:6a4db94011d3	2714	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	2715	}
sahilmgandhi	18:6a4db94011d3	2716	break;
sahilmgandhi	18:6a4db94011d3	2717
sahilmgandhi	18:6a4db94011d3	2718	default:
sahilmgandhi	18:6a4db94011d3	2719	break;
sahilmgandhi	18:6a4db94011d3	2720	}
sahilmgandhi	18:6a4db94011d3	2721	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2722	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2723	}
sahilmgandhi	18:6a4db94011d3	2724
sahilmgandhi	18:6a4db94011d3	2725	/**
sahilmgandhi	18:6a4db94011d3	2726	* @brief Stops the TIM Encoder Interface in DMA mode.
sahilmgandhi	18:6a4db94011d3	2727	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2728	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2729	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	2730	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2731	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2732	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2733	* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
sahilmgandhi	18:6a4db94011d3	2734	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2735	*/
sahilmgandhi	18:6a4db94011d3	2736	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	2737	{
sahilmgandhi	18:6a4db94011d3	2738	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2739	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2740
sahilmgandhi	18:6a4db94011d3	2741	/* Disable the Input Capture channels 1 and 2
sahilmgandhi	18:6a4db94011d3	2742	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
sahilmgandhi	18:6a4db94011d3	2743	if(Channel == TIM_CHANNEL_1)
sahilmgandhi	18:6a4db94011d3	2744	{
sahilmgandhi	18:6a4db94011d3	2745	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2746
sahilmgandhi	18:6a4db94011d3	2747	/* Disable the capture compare DMA Request 1 */
sahilmgandhi	18:6a4db94011d3	2748	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	2749	}
sahilmgandhi	18:6a4db94011d3	2750	else if(Channel == TIM_CHANNEL_2)
sahilmgandhi	18:6a4db94011d3	2751	{
sahilmgandhi	18:6a4db94011d3	2752	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2753
sahilmgandhi	18:6a4db94011d3	2754	/* Disable the capture compare DMA Request 2 */
sahilmgandhi	18:6a4db94011d3	2755	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	2756	}
sahilmgandhi	18:6a4db94011d3	2757	else
sahilmgandhi	18:6a4db94011d3	2758	{
sahilmgandhi	18:6a4db94011d3	2759	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2760	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
sahilmgandhi	18:6a4db94011d3	2761
sahilmgandhi	18:6a4db94011d3	2762	/* Disable the capture compare DMA Request 1 and 2 */
sahilmgandhi	18:6a4db94011d3	2763	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
sahilmgandhi	18:6a4db94011d3	2764	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
sahilmgandhi	18:6a4db94011d3	2765	}
sahilmgandhi	18:6a4db94011d3	2766
sahilmgandhi	18:6a4db94011d3	2767	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	2768	__HAL_TIM_DISABLE(htim);
sahilmgandhi	18:6a4db94011d3	2769
sahilmgandhi	18:6a4db94011d3	2770	/* Change the htim state */
sahilmgandhi	18:6a4db94011d3	2771	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2772
sahilmgandhi	18:6a4db94011d3	2773	/* Return function status */
sahilmgandhi	18:6a4db94011d3	2774	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2775	}
sahilmgandhi	18:6a4db94011d3	2776	/**
sahilmgandhi	18:6a4db94011d3	2777	* @}
sahilmgandhi	18:6a4db94011d3	2778	*/
sahilmgandhi	18:6a4db94011d3	2779
sahilmgandhi	18:6a4db94011d3	2780	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
sahilmgandhi	18:6a4db94011d3	2781	* @brief IRQ handler management
sahilmgandhi	18:6a4db94011d3	2782	*
sahilmgandhi	18:6a4db94011d3	2783	@verbatim
sahilmgandhi	18:6a4db94011d3	2784	==============================================================================
sahilmgandhi	18:6a4db94011d3	2785	##### IRQ handler management #####
sahilmgandhi	18:6a4db94011d3	2786	==============================================================================
sahilmgandhi	18:6a4db94011d3	2787	[..]
sahilmgandhi	18:6a4db94011d3	2788	This section provides Timer IRQ handler function.
sahilmgandhi	18:6a4db94011d3	2789
sahilmgandhi	18:6a4db94011d3	2790	@endverbatim
sahilmgandhi	18:6a4db94011d3	2791	* @{
sahilmgandhi	18:6a4db94011d3	2792	*/
sahilmgandhi	18:6a4db94011d3	2793	/**
sahilmgandhi	18:6a4db94011d3	2794	* @brief This function handles TIM interrupts requests.
sahilmgandhi	18:6a4db94011d3	2795	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2796	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2797	* @retval None
sahilmgandhi	18:6a4db94011d3	2798	*/
sahilmgandhi	18:6a4db94011d3	2799	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	2800	{
sahilmgandhi	18:6a4db94011d3	2801	/* Capture compare 1 event */
sahilmgandhi	18:6a4db94011d3	2802	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
sahilmgandhi	18:6a4db94011d3	2803	{
sahilmgandhi	18:6a4db94011d3	2804	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
sahilmgandhi	18:6a4db94011d3	2805	{
sahilmgandhi	18:6a4db94011d3	2806	{
sahilmgandhi	18:6a4db94011d3	2807	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
sahilmgandhi	18:6a4db94011d3	2808	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
sahilmgandhi	18:6a4db94011d3	2809
sahilmgandhi	18:6a4db94011d3	2810	/* Input capture event */
sahilmgandhi	18:6a4db94011d3	2811	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
sahilmgandhi	18:6a4db94011d3	2812	{
sahilmgandhi	18:6a4db94011d3	2813	HAL_TIM_IC_CaptureCallback(htim);
sahilmgandhi	18:6a4db94011d3	2814	}
sahilmgandhi	18:6a4db94011d3	2815	/* Output compare event */
sahilmgandhi	18:6a4db94011d3	2816	else
sahilmgandhi	18:6a4db94011d3	2817	{
sahilmgandhi	18:6a4db94011d3	2818	HAL_TIM_OC_DelayElapsedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2819	HAL_TIM_PWM_PulseFinishedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2820	}
sahilmgandhi	18:6a4db94011d3	2821	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
sahilmgandhi	18:6a4db94011d3	2822	}
sahilmgandhi	18:6a4db94011d3	2823	}
sahilmgandhi	18:6a4db94011d3	2824	}
sahilmgandhi	18:6a4db94011d3	2825	/* Capture compare 2 event */
sahilmgandhi	18:6a4db94011d3	2826	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
sahilmgandhi	18:6a4db94011d3	2827	{
sahilmgandhi	18:6a4db94011d3	2828	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
sahilmgandhi	18:6a4db94011d3	2829	{
sahilmgandhi	18:6a4db94011d3	2830	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
sahilmgandhi	18:6a4db94011d3	2831	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
sahilmgandhi	18:6a4db94011d3	2832	/* Input capture event */
sahilmgandhi	18:6a4db94011d3	2833	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
sahilmgandhi	18:6a4db94011d3	2834	{
sahilmgandhi	18:6a4db94011d3	2835	HAL_TIM_IC_CaptureCallback(htim);
sahilmgandhi	18:6a4db94011d3	2836	}
sahilmgandhi	18:6a4db94011d3	2837	/* Output compare event */
sahilmgandhi	18:6a4db94011d3	2838	else
sahilmgandhi	18:6a4db94011d3	2839	{
sahilmgandhi	18:6a4db94011d3	2840	HAL_TIM_OC_DelayElapsedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2841	HAL_TIM_PWM_PulseFinishedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2842	}
sahilmgandhi	18:6a4db94011d3	2843	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
sahilmgandhi	18:6a4db94011d3	2844	}
sahilmgandhi	18:6a4db94011d3	2845	}
sahilmgandhi	18:6a4db94011d3	2846	/* Capture compare 3 event */
sahilmgandhi	18:6a4db94011d3	2847	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
sahilmgandhi	18:6a4db94011d3	2848	{
sahilmgandhi	18:6a4db94011d3	2849	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
sahilmgandhi	18:6a4db94011d3	2850	{
sahilmgandhi	18:6a4db94011d3	2851	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
sahilmgandhi	18:6a4db94011d3	2852	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
sahilmgandhi	18:6a4db94011d3	2853	/* Input capture event */
sahilmgandhi	18:6a4db94011d3	2854	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
sahilmgandhi	18:6a4db94011d3	2855	{
sahilmgandhi	18:6a4db94011d3	2856	HAL_TIM_IC_CaptureCallback(htim);
sahilmgandhi	18:6a4db94011d3	2857	}
sahilmgandhi	18:6a4db94011d3	2858	/* Output compare event */
sahilmgandhi	18:6a4db94011d3	2859	else
sahilmgandhi	18:6a4db94011d3	2860	{
sahilmgandhi	18:6a4db94011d3	2861	HAL_TIM_OC_DelayElapsedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2862	HAL_TIM_PWM_PulseFinishedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2863	}
sahilmgandhi	18:6a4db94011d3	2864	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
sahilmgandhi	18:6a4db94011d3	2865	}
sahilmgandhi	18:6a4db94011d3	2866	}
sahilmgandhi	18:6a4db94011d3	2867	/* Capture compare 4 event */
sahilmgandhi	18:6a4db94011d3	2868	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
sahilmgandhi	18:6a4db94011d3	2869	{
sahilmgandhi	18:6a4db94011d3	2870	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
sahilmgandhi	18:6a4db94011d3	2871	{
sahilmgandhi	18:6a4db94011d3	2872	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
sahilmgandhi	18:6a4db94011d3	2873	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
sahilmgandhi	18:6a4db94011d3	2874	/* Input capture event */
sahilmgandhi	18:6a4db94011d3	2875	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
sahilmgandhi	18:6a4db94011d3	2876	{
sahilmgandhi	18:6a4db94011d3	2877	HAL_TIM_IC_CaptureCallback(htim);
sahilmgandhi	18:6a4db94011d3	2878	}
sahilmgandhi	18:6a4db94011d3	2879	/* Output compare event */
sahilmgandhi	18:6a4db94011d3	2880	else
sahilmgandhi	18:6a4db94011d3	2881	{
sahilmgandhi	18:6a4db94011d3	2882	HAL_TIM_OC_DelayElapsedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2883	HAL_TIM_PWM_PulseFinishedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2884	}
sahilmgandhi	18:6a4db94011d3	2885	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
sahilmgandhi	18:6a4db94011d3	2886	}
sahilmgandhi	18:6a4db94011d3	2887	}
sahilmgandhi	18:6a4db94011d3	2888	/* TIM Update event */
sahilmgandhi	18:6a4db94011d3	2889	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
sahilmgandhi	18:6a4db94011d3	2890	{
sahilmgandhi	18:6a4db94011d3	2891	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
sahilmgandhi	18:6a4db94011d3	2892	{
sahilmgandhi	18:6a4db94011d3	2893	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
sahilmgandhi	18:6a4db94011d3	2894	HAL_TIM_PeriodElapsedCallback(htim);
sahilmgandhi	18:6a4db94011d3	2895	}
sahilmgandhi	18:6a4db94011d3	2896	}
sahilmgandhi	18:6a4db94011d3	2897	/* TIM Break input event */
sahilmgandhi	18:6a4db94011d3	2898	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
sahilmgandhi	18:6a4db94011d3	2899	{
sahilmgandhi	18:6a4db94011d3	2900	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
sahilmgandhi	18:6a4db94011d3	2901	{
sahilmgandhi	18:6a4db94011d3	2902	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
sahilmgandhi	18:6a4db94011d3	2903	HAL_TIMEx_BreakCallback(htim);
sahilmgandhi	18:6a4db94011d3	2904	}
sahilmgandhi	18:6a4db94011d3	2905	}
sahilmgandhi	18:6a4db94011d3	2906	/* TIM Trigger detection event */
sahilmgandhi	18:6a4db94011d3	2907	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
sahilmgandhi	18:6a4db94011d3	2908	{
sahilmgandhi	18:6a4db94011d3	2909	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
sahilmgandhi	18:6a4db94011d3	2910	{
sahilmgandhi	18:6a4db94011d3	2911	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
sahilmgandhi	18:6a4db94011d3	2912	HAL_TIM_TriggerCallback(htim);
sahilmgandhi	18:6a4db94011d3	2913	}
sahilmgandhi	18:6a4db94011d3	2914	}
sahilmgandhi	18:6a4db94011d3	2915	/* TIM commutation event */
sahilmgandhi	18:6a4db94011d3	2916	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
sahilmgandhi	18:6a4db94011d3	2917	{
sahilmgandhi	18:6a4db94011d3	2918	if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
sahilmgandhi	18:6a4db94011d3	2919	{
sahilmgandhi	18:6a4db94011d3	2920	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
sahilmgandhi	18:6a4db94011d3	2921	HAL_TIMEx_CommutationCallback(htim);
sahilmgandhi	18:6a4db94011d3	2922	}
sahilmgandhi	18:6a4db94011d3	2923	}
sahilmgandhi	18:6a4db94011d3	2924	}
sahilmgandhi	18:6a4db94011d3	2925	/**
sahilmgandhi	18:6a4db94011d3	2926	* @}
sahilmgandhi	18:6a4db94011d3	2927	*/
sahilmgandhi	18:6a4db94011d3	2928
sahilmgandhi	18:6a4db94011d3	2929	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	2930	* @brief Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	2931	*
sahilmgandhi	18:6a4db94011d3	2932	@verbatim
sahilmgandhi	18:6a4db94011d3	2933	==============================================================================
sahilmgandhi	18:6a4db94011d3	2934	##### Peripheral Control functions #####
sahilmgandhi	18:6a4db94011d3	2935	==============================================================================
sahilmgandhi	18:6a4db94011d3	2936	[..]
sahilmgandhi	18:6a4db94011d3	2937	This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	2938	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
sahilmgandhi	18:6a4db94011d3	2939	(+) Configure External Clock source.
sahilmgandhi	18:6a4db94011d3	2940	(+) Configure Complementary channels, break features and dead time.
sahilmgandhi	18:6a4db94011d3	2941	(+) Configure Master and the Slave synchronization.
sahilmgandhi	18:6a4db94011d3	2942	(+) Configure the DMA Burst Mode.
sahilmgandhi	18:6a4db94011d3	2943
sahilmgandhi	18:6a4db94011d3	2944	@endverbatim
sahilmgandhi	18:6a4db94011d3	2945	* @{
sahilmgandhi	18:6a4db94011d3	2946	*/
sahilmgandhi	18:6a4db94011d3	2947
sahilmgandhi	18:6a4db94011d3	2948	/**
sahilmgandhi	18:6a4db94011d3	2949	* @brief Initializes the TIM Output Compare Channels according to the specified
sahilmgandhi	18:6a4db94011d3	2950	* parameters in the TIM_OC_InitTypeDef.
sahilmgandhi	18:6a4db94011d3	2951	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2952	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	2953	* @param sConfig: TIM Output Compare configuration structure
sahilmgandhi	18:6a4db94011d3	2954	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	2955	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2956	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	2957	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	2958	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	2959	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	2960	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2961	*/
sahilmgandhi	18:6a4db94011d3	2962	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	2963	{
sahilmgandhi	18:6a4db94011d3	2964	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2965	assert_param(IS_TIM_CHANNELS(Channel));
sahilmgandhi	18:6a4db94011d3	2966	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
sahilmgandhi	18:6a4db94011d3	2967	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
sahilmgandhi	18:6a4db94011d3	2968
sahilmgandhi	18:6a4db94011d3	2969	/* Check input state */
sahilmgandhi	18:6a4db94011d3	2970	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	2971
sahilmgandhi	18:6a4db94011d3	2972	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	2973
sahilmgandhi	18:6a4db94011d3	2974	switch (Channel)
sahilmgandhi	18:6a4db94011d3	2975	{
sahilmgandhi	18:6a4db94011d3	2976	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	2977	{
sahilmgandhi	18:6a4db94011d3	2978	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2979	/* Configure the TIM Channel 1 in Output Compare */
sahilmgandhi	18:6a4db94011d3	2980	TIM_OC1_SetConfig(htim->Instance, sConfig);
sahilmgandhi	18:6a4db94011d3	2981	}
sahilmgandhi	18:6a4db94011d3	2982	break;
sahilmgandhi	18:6a4db94011d3	2983
sahilmgandhi	18:6a4db94011d3	2984	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	2985	{
sahilmgandhi	18:6a4db94011d3	2986	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2987	/* Configure the TIM Channel 2 in Output Compare */
sahilmgandhi	18:6a4db94011d3	2988	TIM_OC2_SetConfig(htim->Instance, sConfig);
sahilmgandhi	18:6a4db94011d3	2989	}
sahilmgandhi	18:6a4db94011d3	2990	break;
sahilmgandhi	18:6a4db94011d3	2991
sahilmgandhi	18:6a4db94011d3	2992	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	2993	{
sahilmgandhi	18:6a4db94011d3	2994	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	2995	/* Configure the TIM Channel 3 in Output Compare */
sahilmgandhi	18:6a4db94011d3	2996	TIM_OC3_SetConfig(htim->Instance, sConfig);
sahilmgandhi	18:6a4db94011d3	2997	}
sahilmgandhi	18:6a4db94011d3	2998	break;
sahilmgandhi	18:6a4db94011d3	2999
sahilmgandhi	18:6a4db94011d3	3000	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	3001	{
sahilmgandhi	18:6a4db94011d3	3002	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3003	/* Configure the TIM Channel 4 in Output Compare */
sahilmgandhi	18:6a4db94011d3	3004	TIM_OC4_SetConfig(htim->Instance, sConfig);
sahilmgandhi	18:6a4db94011d3	3005	}
sahilmgandhi	18:6a4db94011d3	3006	break;
sahilmgandhi	18:6a4db94011d3	3007
sahilmgandhi	18:6a4db94011d3	3008	default:
sahilmgandhi	18:6a4db94011d3	3009	break;
sahilmgandhi	18:6a4db94011d3	3010	}
sahilmgandhi	18:6a4db94011d3	3011	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	3012
sahilmgandhi	18:6a4db94011d3	3013	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	3014
sahilmgandhi	18:6a4db94011d3	3015	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3016	}
sahilmgandhi	18:6a4db94011d3	3017
sahilmgandhi	18:6a4db94011d3	3018	/**
sahilmgandhi	18:6a4db94011d3	3019	* @brief Initializes the TIM Input Capture Channels according to the specified
sahilmgandhi	18:6a4db94011d3	3020	* parameters in the TIM_IC_InitTypeDef.
sahilmgandhi	18:6a4db94011d3	3021	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3022	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3023	* @param sConfig: TIM Input Capture configuration structure
sahilmgandhi	18:6a4db94011d3	3024	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	3025	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	3026	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	3027	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	3028	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	3029	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	3030	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3031	*/
sahilmgandhi	18:6a4db94011d3	3032	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	3033	{
sahilmgandhi	18:6a4db94011d3	3034	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3035	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3036	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
sahilmgandhi	18:6a4db94011d3	3037	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
sahilmgandhi	18:6a4db94011d3	3038	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
sahilmgandhi	18:6a4db94011d3	3039	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
sahilmgandhi	18:6a4db94011d3	3040
sahilmgandhi	18:6a4db94011d3	3041	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	3042
sahilmgandhi	18:6a4db94011d3	3043	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	3044
sahilmgandhi	18:6a4db94011d3	3045	if (Channel == TIM_CHANNEL_1)
sahilmgandhi	18:6a4db94011d3	3046	{
sahilmgandhi	18:6a4db94011d3	3047	/* TI1 Configuration */
sahilmgandhi	18:6a4db94011d3	3048	TIM_TI1_SetConfig(htim->Instance,
sahilmgandhi	18:6a4db94011d3	3049	sConfig->ICPolarity,
sahilmgandhi	18:6a4db94011d3	3050	sConfig->ICSelection,
sahilmgandhi	18:6a4db94011d3	3051	sConfig->ICFilter);
sahilmgandhi	18:6a4db94011d3	3052
sahilmgandhi	18:6a4db94011d3	3053	/* Reset the IC1PSC Bits */
sahilmgandhi	18:6a4db94011d3	3054	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
sahilmgandhi	18:6a4db94011d3	3055
sahilmgandhi	18:6a4db94011d3	3056	/* Set the IC1PSC value */
sahilmgandhi	18:6a4db94011d3	3057	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
sahilmgandhi	18:6a4db94011d3	3058	}
sahilmgandhi	18:6a4db94011d3	3059	else if (Channel == TIM_CHANNEL_2)
sahilmgandhi	18:6a4db94011d3	3060	{
sahilmgandhi	18:6a4db94011d3	3061	/* TI2 Configuration */
sahilmgandhi	18:6a4db94011d3	3062	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3063
sahilmgandhi	18:6a4db94011d3	3064	TIM_TI2_SetConfig(htim->Instance,
sahilmgandhi	18:6a4db94011d3	3065	sConfig->ICPolarity,
sahilmgandhi	18:6a4db94011d3	3066	sConfig->ICSelection,
sahilmgandhi	18:6a4db94011d3	3067	sConfig->ICFilter);
sahilmgandhi	18:6a4db94011d3	3068
sahilmgandhi	18:6a4db94011d3	3069	/* Reset the IC2PSC Bits */
sahilmgandhi	18:6a4db94011d3	3070	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
sahilmgandhi	18:6a4db94011d3	3071
sahilmgandhi	18:6a4db94011d3	3072	/* Set the IC2PSC value */
sahilmgandhi	18:6a4db94011d3	3073	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8U);
sahilmgandhi	18:6a4db94011d3	3074	}
sahilmgandhi	18:6a4db94011d3	3075	else if (Channel == TIM_CHANNEL_3)
sahilmgandhi	18:6a4db94011d3	3076	{
sahilmgandhi	18:6a4db94011d3	3077	/* TI3 Configuration */
sahilmgandhi	18:6a4db94011d3	3078	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3079
sahilmgandhi	18:6a4db94011d3	3080	TIM_TI3_SetConfig(htim->Instance,
sahilmgandhi	18:6a4db94011d3	3081	sConfig->ICPolarity,
sahilmgandhi	18:6a4db94011d3	3082	sConfig->ICSelection,
sahilmgandhi	18:6a4db94011d3	3083	sConfig->ICFilter);
sahilmgandhi	18:6a4db94011d3	3084
sahilmgandhi	18:6a4db94011d3	3085	/* Reset the IC3PSC Bits */
sahilmgandhi	18:6a4db94011d3	3086	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
sahilmgandhi	18:6a4db94011d3	3087
sahilmgandhi	18:6a4db94011d3	3088	/* Set the IC3PSC value */
sahilmgandhi	18:6a4db94011d3	3089	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
sahilmgandhi	18:6a4db94011d3	3090	}
sahilmgandhi	18:6a4db94011d3	3091	else
sahilmgandhi	18:6a4db94011d3	3092	{
sahilmgandhi	18:6a4db94011d3	3093	/* TI4 Configuration */
sahilmgandhi	18:6a4db94011d3	3094	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3095
sahilmgandhi	18:6a4db94011d3	3096	TIM_TI4_SetConfig(htim->Instance,
sahilmgandhi	18:6a4db94011d3	3097	sConfig->ICPolarity,
sahilmgandhi	18:6a4db94011d3	3098	sConfig->ICSelection,
sahilmgandhi	18:6a4db94011d3	3099	sConfig->ICFilter);
sahilmgandhi	18:6a4db94011d3	3100
sahilmgandhi	18:6a4db94011d3	3101	/* Reset the IC4PSC Bits */
sahilmgandhi	18:6a4db94011d3	3102	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
sahilmgandhi	18:6a4db94011d3	3103
sahilmgandhi	18:6a4db94011d3	3104	/* Set the IC4PSC value */
sahilmgandhi	18:6a4db94011d3	3105	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8U);
sahilmgandhi	18:6a4db94011d3	3106	}
sahilmgandhi	18:6a4db94011d3	3107
sahilmgandhi	18:6a4db94011d3	3108	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	3109
sahilmgandhi	18:6a4db94011d3	3110	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	3111
sahilmgandhi	18:6a4db94011d3	3112	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3113	}
sahilmgandhi	18:6a4db94011d3	3114
sahilmgandhi	18:6a4db94011d3	3115	/**
sahilmgandhi	18:6a4db94011d3	3116	* @brief Initializes the TIM PWM channels according to the specified
sahilmgandhi	18:6a4db94011d3	3117	* parameters in the TIM_OC_InitTypeDef.
sahilmgandhi	18:6a4db94011d3	3118	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3119	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3120	* @param sConfig: TIM PWM configuration structure
sahilmgandhi	18:6a4db94011d3	3121	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	3122	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	3123	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	3124	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	3125	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	3126	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	3127	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3128	*/
sahilmgandhi	18:6a4db94011d3	3129	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	3130	{
sahilmgandhi	18:6a4db94011d3	3131	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	3132
sahilmgandhi	18:6a4db94011d3	3133	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3134	assert_param(IS_TIM_CHANNELS(Channel));
sahilmgandhi	18:6a4db94011d3	3135	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
sahilmgandhi	18:6a4db94011d3	3136	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
sahilmgandhi	18:6a4db94011d3	3137	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
sahilmgandhi	18:6a4db94011d3	3138
sahilmgandhi	18:6a4db94011d3	3139	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	3140
sahilmgandhi	18:6a4db94011d3	3141	switch (Channel)
sahilmgandhi	18:6a4db94011d3	3142	{
sahilmgandhi	18:6a4db94011d3	3143	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	3144	{
sahilmgandhi	18:6a4db94011d3	3145	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3146	/* Configure the Channel 1 in PWM mode */
sahilmgandhi	18:6a4db94011d3	3147	TIM_OC1_SetConfig(htim->Instance, sConfig);
sahilmgandhi	18:6a4db94011d3	3148
sahilmgandhi	18:6a4db94011d3	3149	/* Set the Preload enable bit for channel1 */
sahilmgandhi	18:6a4db94011d3	3150	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
sahilmgandhi	18:6a4db94011d3	3151
sahilmgandhi	18:6a4db94011d3	3152	/* Configure the Output Fast mode */
sahilmgandhi	18:6a4db94011d3	3153	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
sahilmgandhi	18:6a4db94011d3	3154	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
sahilmgandhi	18:6a4db94011d3	3155	}
sahilmgandhi	18:6a4db94011d3	3156	break;
sahilmgandhi	18:6a4db94011d3	3157
sahilmgandhi	18:6a4db94011d3	3158	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	3159	{
sahilmgandhi	18:6a4db94011d3	3160	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3161	/* Configure the Channel 2 in PWM mode */
sahilmgandhi	18:6a4db94011d3	3162	TIM_OC2_SetConfig(htim->Instance, sConfig);
sahilmgandhi	18:6a4db94011d3	3163
sahilmgandhi	18:6a4db94011d3	3164	/* Set the Preload enable bit for channel2 */
sahilmgandhi	18:6a4db94011d3	3165	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
sahilmgandhi	18:6a4db94011d3	3166
sahilmgandhi	18:6a4db94011d3	3167	/* Configure the Output Fast mode */
sahilmgandhi	18:6a4db94011d3	3168	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
sahilmgandhi	18:6a4db94011d3	3169	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8U;
sahilmgandhi	18:6a4db94011d3	3170	}
sahilmgandhi	18:6a4db94011d3	3171	break;
sahilmgandhi	18:6a4db94011d3	3172
sahilmgandhi	18:6a4db94011d3	3173	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	3174	{
sahilmgandhi	18:6a4db94011d3	3175	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3176	/* Configure the Channel 3 in PWM mode */
sahilmgandhi	18:6a4db94011d3	3177	TIM_OC3_SetConfig(htim->Instance, sConfig);
sahilmgandhi	18:6a4db94011d3	3178
sahilmgandhi	18:6a4db94011d3	3179	/* Set the Preload enable bit for channel3 */
sahilmgandhi	18:6a4db94011d3	3180	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
sahilmgandhi	18:6a4db94011d3	3181
sahilmgandhi	18:6a4db94011d3	3182	/* Configure the Output Fast mode */
sahilmgandhi	18:6a4db94011d3	3183	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
sahilmgandhi	18:6a4db94011d3	3184	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
sahilmgandhi	18:6a4db94011d3	3185	}
sahilmgandhi	18:6a4db94011d3	3186	break;
sahilmgandhi	18:6a4db94011d3	3187
sahilmgandhi	18:6a4db94011d3	3188	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	3189	{
sahilmgandhi	18:6a4db94011d3	3190	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3191	/* Configure the Channel 4 in PWM mode */
sahilmgandhi	18:6a4db94011d3	3192	TIM_OC4_SetConfig(htim->Instance, sConfig);
sahilmgandhi	18:6a4db94011d3	3193
sahilmgandhi	18:6a4db94011d3	3194	/* Set the Preload enable bit for channel4 */
sahilmgandhi	18:6a4db94011d3	3195	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
sahilmgandhi	18:6a4db94011d3	3196
sahilmgandhi	18:6a4db94011d3	3197	/* Configure the Output Fast mode */
sahilmgandhi	18:6a4db94011d3	3198	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
sahilmgandhi	18:6a4db94011d3	3199	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8U;
sahilmgandhi	18:6a4db94011d3	3200	}
sahilmgandhi	18:6a4db94011d3	3201	break;
sahilmgandhi	18:6a4db94011d3	3202
sahilmgandhi	18:6a4db94011d3	3203	default:
sahilmgandhi	18:6a4db94011d3	3204	break;
sahilmgandhi	18:6a4db94011d3	3205	}
sahilmgandhi	18:6a4db94011d3	3206
sahilmgandhi	18:6a4db94011d3	3207	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	3208
sahilmgandhi	18:6a4db94011d3	3209	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	3210
sahilmgandhi	18:6a4db94011d3	3211	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3212	}
sahilmgandhi	18:6a4db94011d3	3213
sahilmgandhi	18:6a4db94011d3	3214	/**
sahilmgandhi	18:6a4db94011d3	3215	* @brief Initializes the TIM One Pulse Channels according to the specified
sahilmgandhi	18:6a4db94011d3	3216	* parameters in the TIM_OnePulse_InitTypeDef.
sahilmgandhi	18:6a4db94011d3	3217	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3218	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3219	* @param sConfig: TIM One Pulse configuration structure
sahilmgandhi	18:6a4db94011d3	3220	* @param OutputChannel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	3221	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	3222	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	3223	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	3224	* @param InputChannel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	3225	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	3226	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	3227	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	3228	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3229	*/
sahilmgandhi	18:6a4db94011d3	3230	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
sahilmgandhi	18:6a4db94011d3	3231	{
sahilmgandhi	18:6a4db94011d3	3232	TIM_OC_InitTypeDef temp1;
sahilmgandhi	18:6a4db94011d3	3233
sahilmgandhi	18:6a4db94011d3	3234	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3235	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
sahilmgandhi	18:6a4db94011d3	3236	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
sahilmgandhi	18:6a4db94011d3	3237
sahilmgandhi	18:6a4db94011d3	3238	if(OutputChannel != InputChannel)
sahilmgandhi	18:6a4db94011d3	3239	{
sahilmgandhi	18:6a4db94011d3	3240	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	3241
sahilmgandhi	18:6a4db94011d3	3242	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	3243
sahilmgandhi	18:6a4db94011d3	3244	/* Extract the Output compare configuration from sConfig structure */
sahilmgandhi	18:6a4db94011d3	3245	temp1.OCMode = sConfig->OCMode;
sahilmgandhi	18:6a4db94011d3	3246	temp1.Pulse = sConfig->Pulse;
sahilmgandhi	18:6a4db94011d3	3247	temp1.OCPolarity = sConfig->OCPolarity;
sahilmgandhi	18:6a4db94011d3	3248	temp1.OCNPolarity = sConfig->OCNPolarity;
sahilmgandhi	18:6a4db94011d3	3249	temp1.OCIdleState = sConfig->OCIdleState;
sahilmgandhi	18:6a4db94011d3	3250	temp1.OCNIdleState = sConfig->OCNIdleState;
sahilmgandhi	18:6a4db94011d3	3251
sahilmgandhi	18:6a4db94011d3	3252	switch (OutputChannel)
sahilmgandhi	18:6a4db94011d3	3253	{
sahilmgandhi	18:6a4db94011d3	3254	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	3255	{
sahilmgandhi	18:6a4db94011d3	3256	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3257
sahilmgandhi	18:6a4db94011d3	3258	TIM_OC1_SetConfig(htim->Instance, &temp1);
sahilmgandhi	18:6a4db94011d3	3259	}
sahilmgandhi	18:6a4db94011d3	3260	break;
sahilmgandhi	18:6a4db94011d3	3261	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	3262	{
sahilmgandhi	18:6a4db94011d3	3263	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3264
sahilmgandhi	18:6a4db94011d3	3265	TIM_OC2_SetConfig(htim->Instance, &temp1);
sahilmgandhi	18:6a4db94011d3	3266	}
sahilmgandhi	18:6a4db94011d3	3267	break;
sahilmgandhi	18:6a4db94011d3	3268	default:
sahilmgandhi	18:6a4db94011d3	3269	break;
sahilmgandhi	18:6a4db94011d3	3270	}
sahilmgandhi	18:6a4db94011d3	3271	switch (InputChannel)
sahilmgandhi	18:6a4db94011d3	3272	{
sahilmgandhi	18:6a4db94011d3	3273	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	3274	{
sahilmgandhi	18:6a4db94011d3	3275	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3276
sahilmgandhi	18:6a4db94011d3	3277	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
sahilmgandhi	18:6a4db94011d3	3278	sConfig->ICSelection, sConfig->ICFilter);
sahilmgandhi	18:6a4db94011d3	3279
sahilmgandhi	18:6a4db94011d3	3280	/* Reset the IC1PSC Bits */
sahilmgandhi	18:6a4db94011d3	3281	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
sahilmgandhi	18:6a4db94011d3	3282
sahilmgandhi	18:6a4db94011d3	3283	/* Select the Trigger source */
sahilmgandhi	18:6a4db94011d3	3284	htim->Instance->SMCR &= ~TIM_SMCR_TS;
sahilmgandhi	18:6a4db94011d3	3285	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
sahilmgandhi	18:6a4db94011d3	3286
sahilmgandhi	18:6a4db94011d3	3287	/* Select the Slave Mode */
sahilmgandhi	18:6a4db94011d3	3288	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
sahilmgandhi	18:6a4db94011d3	3289	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
sahilmgandhi	18:6a4db94011d3	3290	}
sahilmgandhi	18:6a4db94011d3	3291	break;
sahilmgandhi	18:6a4db94011d3	3292	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	3293	{
sahilmgandhi	18:6a4db94011d3	3294	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3295
sahilmgandhi	18:6a4db94011d3	3296	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
sahilmgandhi	18:6a4db94011d3	3297	sConfig->ICSelection, sConfig->ICFilter);
sahilmgandhi	18:6a4db94011d3	3298
sahilmgandhi	18:6a4db94011d3	3299	/* Reset the IC2PSC Bits */
sahilmgandhi	18:6a4db94011d3	3300	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
sahilmgandhi	18:6a4db94011d3	3301
sahilmgandhi	18:6a4db94011d3	3302	/* Select the Trigger source */
sahilmgandhi	18:6a4db94011d3	3303	htim->Instance->SMCR &= ~TIM_SMCR_TS;
sahilmgandhi	18:6a4db94011d3	3304	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
sahilmgandhi	18:6a4db94011d3	3305
sahilmgandhi	18:6a4db94011d3	3306	/* Select the Slave Mode */
sahilmgandhi	18:6a4db94011d3	3307	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
sahilmgandhi	18:6a4db94011d3	3308	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
sahilmgandhi	18:6a4db94011d3	3309	}
sahilmgandhi	18:6a4db94011d3	3310	break;
sahilmgandhi	18:6a4db94011d3	3311
sahilmgandhi	18:6a4db94011d3	3312	default:
sahilmgandhi	18:6a4db94011d3	3313	break;
sahilmgandhi	18:6a4db94011d3	3314	}
sahilmgandhi	18:6a4db94011d3	3315
sahilmgandhi	18:6a4db94011d3	3316	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	3317
sahilmgandhi	18:6a4db94011d3	3318	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	3319
sahilmgandhi	18:6a4db94011d3	3320	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3321	}
sahilmgandhi	18:6a4db94011d3	3322	else
sahilmgandhi	18:6a4db94011d3	3323	{
sahilmgandhi	18:6a4db94011d3	3324	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	3325	}
sahilmgandhi	18:6a4db94011d3	3326	}
sahilmgandhi	18:6a4db94011d3	3327
sahilmgandhi	18:6a4db94011d3	3328	/**
sahilmgandhi	18:6a4db94011d3	3329	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
sahilmgandhi	18:6a4db94011d3	3330	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3331	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3332	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
sahilmgandhi	18:6a4db94011d3	3333	* This parameters can be on of the following values:
sahilmgandhi	18:6a4db94011d3	3334	* @arg TIM_DMABASE_CR1
sahilmgandhi	18:6a4db94011d3	3335	* @arg TIM_DMABASE_CR2
sahilmgandhi	18:6a4db94011d3	3336	* @arg TIM_DMABASE_SMCR
sahilmgandhi	18:6a4db94011d3	3337	* @arg TIM_DMABASE_DIER
sahilmgandhi	18:6a4db94011d3	3338	* @arg TIM_DMABASE_SR
sahilmgandhi	18:6a4db94011d3	3339	* @arg TIM_DMABASE_EGR
sahilmgandhi	18:6a4db94011d3	3340	* @arg TIM_DMABASE_CCMR1
sahilmgandhi	18:6a4db94011d3	3341	* @arg TIM_DMABASE_CCMR2
sahilmgandhi	18:6a4db94011d3	3342	* @arg TIM_DMABASE_CCER
sahilmgandhi	18:6a4db94011d3	3343	* @arg TIM_DMABASE_CNT
sahilmgandhi	18:6a4db94011d3	3344	* @arg TIM_DMABASE_PSC
sahilmgandhi	18:6a4db94011d3	3345	* @arg TIM_DMABASE_ARR
sahilmgandhi	18:6a4db94011d3	3346	* @arg TIM_DMABASE_RCR
sahilmgandhi	18:6a4db94011d3	3347	* @arg TIM_DMABASE_CCR1
sahilmgandhi	18:6a4db94011d3	3348	* @arg TIM_DMABASE_CCR2
sahilmgandhi	18:6a4db94011d3	3349	* @arg TIM_DMABASE_CCR3
sahilmgandhi	18:6a4db94011d3	3350	* @arg TIM_DMABASE_CCR4
sahilmgandhi	18:6a4db94011d3	3351	* @arg TIM_DMABASE_BDTR
sahilmgandhi	18:6a4db94011d3	3352	* @arg TIM_DMABASE_DCR
sahilmgandhi	18:6a4db94011d3	3353	* @param BurstRequestSrc: TIM DMA Request sources.
sahilmgandhi	18:6a4db94011d3	3354	* This parameters can be on of the following values:
sahilmgandhi	18:6a4db94011d3	3355	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
sahilmgandhi	18:6a4db94011d3	3356	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
sahilmgandhi	18:6a4db94011d3	3357	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
sahilmgandhi	18:6a4db94011d3	3358	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
sahilmgandhi	18:6a4db94011d3	3359	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
sahilmgandhi	18:6a4db94011d3	3360	* @arg TIM_DMA_COM: TIM Commutation DMA source
sahilmgandhi	18:6a4db94011d3	3361	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
sahilmgandhi	18:6a4db94011d3	3362	* @param BurstBuffer: The Buffer address.
sahilmgandhi	18:6a4db94011d3	3363	* @param BurstLength: DMA Burst length. This parameter can be one value
sahilmgandhi	18:6a4db94011d3	3364	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
sahilmgandhi	18:6a4db94011d3	3365	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3366	*/
sahilmgandhi	18:6a4db94011d3	3367	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
sahilmgandhi	18:6a4db94011d3	3368	uint32_t* BurstBuffer, uint32_t BurstLength)
sahilmgandhi	18:6a4db94011d3	3369	{
sahilmgandhi	18:6a4db94011d3	3370	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3371	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3372	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
sahilmgandhi	18:6a4db94011d3	3373	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
sahilmgandhi	18:6a4db94011d3	3374	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
sahilmgandhi	18:6a4db94011d3	3375
sahilmgandhi	18:6a4db94011d3	3376	if((htim->State == HAL_TIM_STATE_BUSY))
sahilmgandhi	18:6a4db94011d3	3377	{
sahilmgandhi	18:6a4db94011d3	3378	return HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	3379	}
sahilmgandhi	18:6a4db94011d3	3380	else if((htim->State == HAL_TIM_STATE_READY))
sahilmgandhi	18:6a4db94011d3	3381	{
sahilmgandhi	18:6a4db94011d3	3382	if((BurstBuffer == 0U ) && (BurstLength > 0U))
sahilmgandhi	18:6a4db94011d3	3383	{
sahilmgandhi	18:6a4db94011d3	3384	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	3385	}
sahilmgandhi	18:6a4db94011d3	3386	else
sahilmgandhi	18:6a4db94011d3	3387	{
sahilmgandhi	18:6a4db94011d3	3388	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	3389	}
sahilmgandhi	18:6a4db94011d3	3390	}
sahilmgandhi	18:6a4db94011d3	3391	switch(BurstRequestSrc)
sahilmgandhi	18:6a4db94011d3	3392	{
sahilmgandhi	18:6a4db94011d3	3393	case TIM_DMA_UPDATE:
sahilmgandhi	18:6a4db94011d3	3394	{
sahilmgandhi	18:6a4db94011d3	3395	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3396	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
sahilmgandhi	18:6a4db94011d3	3397
sahilmgandhi	18:6a4db94011d3	3398	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3399	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3400
sahilmgandhi	18:6a4db94011d3	3401	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3402	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3403	}
sahilmgandhi	18:6a4db94011d3	3404	break;
sahilmgandhi	18:6a4db94011d3	3405	case TIM_DMA_CC1:
sahilmgandhi	18:6a4db94011d3	3406	{
sahilmgandhi	18:6a4db94011d3	3407	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3408	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	3409
sahilmgandhi	18:6a4db94011d3	3410	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3411	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3412
sahilmgandhi	18:6a4db94011d3	3413	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3414	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3415	}
sahilmgandhi	18:6a4db94011d3	3416	break;
sahilmgandhi	18:6a4db94011d3	3417	case TIM_DMA_CC2:
sahilmgandhi	18:6a4db94011d3	3418	{
sahilmgandhi	18:6a4db94011d3	3419	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3420	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	3421
sahilmgandhi	18:6a4db94011d3	3422	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3423	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3424
sahilmgandhi	18:6a4db94011d3	3425	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3426	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3427	}
sahilmgandhi	18:6a4db94011d3	3428	break;
sahilmgandhi	18:6a4db94011d3	3429	case TIM_DMA_CC3:
sahilmgandhi	18:6a4db94011d3	3430	{
sahilmgandhi	18:6a4db94011d3	3431	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3432	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	3433
sahilmgandhi	18:6a4db94011d3	3434	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3435	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3436
sahilmgandhi	18:6a4db94011d3	3437	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3438	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3439	}
sahilmgandhi	18:6a4db94011d3	3440	break;
sahilmgandhi	18:6a4db94011d3	3441	case TIM_DMA_CC4:
sahilmgandhi	18:6a4db94011d3	3442	{
sahilmgandhi	18:6a4db94011d3	3443	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3444	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
sahilmgandhi	18:6a4db94011d3	3445
sahilmgandhi	18:6a4db94011d3	3446	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3447	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3448
sahilmgandhi	18:6a4db94011d3	3449	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3450	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3451	}
sahilmgandhi	18:6a4db94011d3	3452	break;
sahilmgandhi	18:6a4db94011d3	3453	case TIM_DMA_COM:
sahilmgandhi	18:6a4db94011d3	3454	{
sahilmgandhi	18:6a4db94011d3	3455	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3456	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
sahilmgandhi	18:6a4db94011d3	3457
sahilmgandhi	18:6a4db94011d3	3458	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3459	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3460
sahilmgandhi	18:6a4db94011d3	3461	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3462	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3463	}
sahilmgandhi	18:6a4db94011d3	3464	break;
sahilmgandhi	18:6a4db94011d3	3465	case TIM_DMA_TRIGGER:
sahilmgandhi	18:6a4db94011d3	3466	{
sahilmgandhi	18:6a4db94011d3	3467	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3468	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
sahilmgandhi	18:6a4db94011d3	3469
sahilmgandhi	18:6a4db94011d3	3470	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3471	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3472
sahilmgandhi	18:6a4db94011d3	3473	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3474	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3475	}
sahilmgandhi	18:6a4db94011d3	3476	break;
sahilmgandhi	18:6a4db94011d3	3477	default:
sahilmgandhi	18:6a4db94011d3	3478	break;
sahilmgandhi	18:6a4db94011d3	3479	}
sahilmgandhi	18:6a4db94011d3	3480	/* configure the DMA Burst Mode */
sahilmgandhi	18:6a4db94011d3	3481	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
sahilmgandhi	18:6a4db94011d3	3482
sahilmgandhi	18:6a4db94011d3	3483	/* Enable the TIM DMA Request */
sahilmgandhi	18:6a4db94011d3	3484	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
sahilmgandhi	18:6a4db94011d3	3485
sahilmgandhi	18:6a4db94011d3	3486	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	3487
sahilmgandhi	18:6a4db94011d3	3488	/* Return function status */
sahilmgandhi	18:6a4db94011d3	3489	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3490	}
sahilmgandhi	18:6a4db94011d3	3491
sahilmgandhi	18:6a4db94011d3	3492	/**
sahilmgandhi	18:6a4db94011d3	3493	* @brief Stops the TIM DMA Burst mode
sahilmgandhi	18:6a4db94011d3	3494	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3495	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3496	* @param BurstRequestSrc: TIM DMA Request sources to disable
sahilmgandhi	18:6a4db94011d3	3497	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3498	*/
sahilmgandhi	18:6a4db94011d3	3499	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
sahilmgandhi	18:6a4db94011d3	3500	{
sahilmgandhi	18:6a4db94011d3	3501	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3502	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
sahilmgandhi	18:6a4db94011d3	3503
sahilmgandhi	18:6a4db94011d3	3504	/* Abort the DMA transfer (at least disable the DMA channel) */
sahilmgandhi	18:6a4db94011d3	3505	switch(BurstRequestSrc)
sahilmgandhi	18:6a4db94011d3	3506	{
sahilmgandhi	18:6a4db94011d3	3507	case TIM_DMA_UPDATE:
sahilmgandhi	18:6a4db94011d3	3508	{
sahilmgandhi	18:6a4db94011d3	3509	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
sahilmgandhi	18:6a4db94011d3	3510	}
sahilmgandhi	18:6a4db94011d3	3511	break;
sahilmgandhi	18:6a4db94011d3	3512	case TIM_DMA_CC1:
sahilmgandhi	18:6a4db94011d3	3513	{
sahilmgandhi	18:6a4db94011d3	3514	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
sahilmgandhi	18:6a4db94011d3	3515	}
sahilmgandhi	18:6a4db94011d3	3516	break;
sahilmgandhi	18:6a4db94011d3	3517	case TIM_DMA_CC2:
sahilmgandhi	18:6a4db94011d3	3518	{
sahilmgandhi	18:6a4db94011d3	3519	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
sahilmgandhi	18:6a4db94011d3	3520	}
sahilmgandhi	18:6a4db94011d3	3521	break;
sahilmgandhi	18:6a4db94011d3	3522	case TIM_DMA_CC3:
sahilmgandhi	18:6a4db94011d3	3523	{
sahilmgandhi	18:6a4db94011d3	3524	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
sahilmgandhi	18:6a4db94011d3	3525	}
sahilmgandhi	18:6a4db94011d3	3526	break;
sahilmgandhi	18:6a4db94011d3	3527	case TIM_DMA_CC4:
sahilmgandhi	18:6a4db94011d3	3528	{
sahilmgandhi	18:6a4db94011d3	3529	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
sahilmgandhi	18:6a4db94011d3	3530	}
sahilmgandhi	18:6a4db94011d3	3531	break;
sahilmgandhi	18:6a4db94011d3	3532	case TIM_DMA_COM:
sahilmgandhi	18:6a4db94011d3	3533	{
sahilmgandhi	18:6a4db94011d3	3534	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
sahilmgandhi	18:6a4db94011d3	3535	}
sahilmgandhi	18:6a4db94011d3	3536	break;
sahilmgandhi	18:6a4db94011d3	3537	case TIM_DMA_TRIGGER:
sahilmgandhi	18:6a4db94011d3	3538	{
sahilmgandhi	18:6a4db94011d3	3539	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
sahilmgandhi	18:6a4db94011d3	3540	}
sahilmgandhi	18:6a4db94011d3	3541	break;
sahilmgandhi	18:6a4db94011d3	3542	default:
sahilmgandhi	18:6a4db94011d3	3543	break;
sahilmgandhi	18:6a4db94011d3	3544	}
sahilmgandhi	18:6a4db94011d3	3545
sahilmgandhi	18:6a4db94011d3	3546	/* Disable the TIM Update DMA request */
sahilmgandhi	18:6a4db94011d3	3547	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
sahilmgandhi	18:6a4db94011d3	3548
sahilmgandhi	18:6a4db94011d3	3549	/* Return function status */
sahilmgandhi	18:6a4db94011d3	3550	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3551	}
sahilmgandhi	18:6a4db94011d3	3552
sahilmgandhi	18:6a4db94011d3	3553	/**
sahilmgandhi	18:6a4db94011d3	3554	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
sahilmgandhi	18:6a4db94011d3	3555	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3556	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3557	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
sahilmgandhi	18:6a4db94011d3	3558	* This parameters can be on of the following values:
sahilmgandhi	18:6a4db94011d3	3559	* @arg TIM_DMABASE_CR1
sahilmgandhi	18:6a4db94011d3	3560	* @arg TIM_DMABASE_CR2
sahilmgandhi	18:6a4db94011d3	3561	* @arg TIM_DMABASE_SMCR
sahilmgandhi	18:6a4db94011d3	3562	* @arg TIM_DMABASE_DIER
sahilmgandhi	18:6a4db94011d3	3563	* @arg TIM_DMABASE_SR
sahilmgandhi	18:6a4db94011d3	3564	* @arg TIM_DMABASE_EGR
sahilmgandhi	18:6a4db94011d3	3565	* @arg TIM_DMABASE_CCMR1
sahilmgandhi	18:6a4db94011d3	3566	* @arg TIM_DMABASE_CCMR2
sahilmgandhi	18:6a4db94011d3	3567	* @arg TIM_DMABASE_CCER
sahilmgandhi	18:6a4db94011d3	3568	* @arg TIM_DMABASE_CNT
sahilmgandhi	18:6a4db94011d3	3569	* @arg TIM_DMABASE_PSC
sahilmgandhi	18:6a4db94011d3	3570	* @arg TIM_DMABASE_ARR
sahilmgandhi	18:6a4db94011d3	3571	* @arg TIM_DMABASE_RCR
sahilmgandhi	18:6a4db94011d3	3572	* @arg TIM_DMABASE_CCR1
sahilmgandhi	18:6a4db94011d3	3573	* @arg TIM_DMABASE_CCR2
sahilmgandhi	18:6a4db94011d3	3574	* @arg TIM_DMABASE_CCR3
sahilmgandhi	18:6a4db94011d3	3575	* @arg TIM_DMABASE_CCR4
sahilmgandhi	18:6a4db94011d3	3576	* @arg TIM_DMABASE_BDTR
sahilmgandhi	18:6a4db94011d3	3577	* @arg TIM_DMABASE_DCR
sahilmgandhi	18:6a4db94011d3	3578	* @param BurstRequestSrc: TIM DMA Request sources.
sahilmgandhi	18:6a4db94011d3	3579	* This parameters can be on of the following values:
sahilmgandhi	18:6a4db94011d3	3580	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
sahilmgandhi	18:6a4db94011d3	3581	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
sahilmgandhi	18:6a4db94011d3	3582	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
sahilmgandhi	18:6a4db94011d3	3583	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
sahilmgandhi	18:6a4db94011d3	3584	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
sahilmgandhi	18:6a4db94011d3	3585	* @arg TIM_DMA_COM: TIM Commutation DMA source
sahilmgandhi	18:6a4db94011d3	3586	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
sahilmgandhi	18:6a4db94011d3	3587	* @param BurstBuffer: The Buffer address.
sahilmgandhi	18:6a4db94011d3	3588	* @param BurstLength: DMA Burst length. This parameter can be one value
sahilmgandhi	18:6a4db94011d3	3589	* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
sahilmgandhi	18:6a4db94011d3	3590	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3591	*/
sahilmgandhi	18:6a4db94011d3	3592	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
sahilmgandhi	18:6a4db94011d3	3593	uint32_t *BurstBuffer, uint32_t BurstLength)
sahilmgandhi	18:6a4db94011d3	3594	{
sahilmgandhi	18:6a4db94011d3	3595	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3596	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3597	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
sahilmgandhi	18:6a4db94011d3	3598	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
sahilmgandhi	18:6a4db94011d3	3599	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
sahilmgandhi	18:6a4db94011d3	3600
sahilmgandhi	18:6a4db94011d3	3601	if((htim->State == HAL_TIM_STATE_BUSY))
sahilmgandhi	18:6a4db94011d3	3602	{
sahilmgandhi	18:6a4db94011d3	3603	return HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	3604	}
sahilmgandhi	18:6a4db94011d3	3605	else if((htim->State == HAL_TIM_STATE_READY))
sahilmgandhi	18:6a4db94011d3	3606	{
sahilmgandhi	18:6a4db94011d3	3607	if((BurstBuffer == 0 ) && (BurstLength > 0))
sahilmgandhi	18:6a4db94011d3	3608	{
sahilmgandhi	18:6a4db94011d3	3609	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	3610	}
sahilmgandhi	18:6a4db94011d3	3611	else
sahilmgandhi	18:6a4db94011d3	3612	{
sahilmgandhi	18:6a4db94011d3	3613	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	3614	}
sahilmgandhi	18:6a4db94011d3	3615	}
sahilmgandhi	18:6a4db94011d3	3616	switch(BurstRequestSrc)
sahilmgandhi	18:6a4db94011d3	3617	{
sahilmgandhi	18:6a4db94011d3	3618	case TIM_DMA_UPDATE:
sahilmgandhi	18:6a4db94011d3	3619	{
sahilmgandhi	18:6a4db94011d3	3620	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3621	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
sahilmgandhi	18:6a4db94011d3	3622
sahilmgandhi	18:6a4db94011d3	3623	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3624	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3625
sahilmgandhi	18:6a4db94011d3	3626	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3627	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3628	}
sahilmgandhi	18:6a4db94011d3	3629	break;
sahilmgandhi	18:6a4db94011d3	3630	case TIM_DMA_CC1:
sahilmgandhi	18:6a4db94011d3	3631	{
sahilmgandhi	18:6a4db94011d3	3632	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3633	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	3634
sahilmgandhi	18:6a4db94011d3	3635	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3636	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3637
sahilmgandhi	18:6a4db94011d3	3638	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3639	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3640	}
sahilmgandhi	18:6a4db94011d3	3641	break;
sahilmgandhi	18:6a4db94011d3	3642	case TIM_DMA_CC2:
sahilmgandhi	18:6a4db94011d3	3643	{
sahilmgandhi	18:6a4db94011d3	3644	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3645	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	3646
sahilmgandhi	18:6a4db94011d3	3647	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3648	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3649
sahilmgandhi	18:6a4db94011d3	3650	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3651	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3652	}
sahilmgandhi	18:6a4db94011d3	3653	break;
sahilmgandhi	18:6a4db94011d3	3654	case TIM_DMA_CC3:
sahilmgandhi	18:6a4db94011d3	3655	{
sahilmgandhi	18:6a4db94011d3	3656	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3657	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	3658
sahilmgandhi	18:6a4db94011d3	3659	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3660	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3661
sahilmgandhi	18:6a4db94011d3	3662	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3663	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3664	}
sahilmgandhi	18:6a4db94011d3	3665	break;
sahilmgandhi	18:6a4db94011d3	3666	case TIM_DMA_CC4:
sahilmgandhi	18:6a4db94011d3	3667	{
sahilmgandhi	18:6a4db94011d3	3668	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3669	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
sahilmgandhi	18:6a4db94011d3	3670
sahilmgandhi	18:6a4db94011d3	3671	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3672	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3673
sahilmgandhi	18:6a4db94011d3	3674	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3675	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3676	}
sahilmgandhi	18:6a4db94011d3	3677	break;
sahilmgandhi	18:6a4db94011d3	3678	case TIM_DMA_COM:
sahilmgandhi	18:6a4db94011d3	3679	{
sahilmgandhi	18:6a4db94011d3	3680	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3681	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
sahilmgandhi	18:6a4db94011d3	3682
sahilmgandhi	18:6a4db94011d3	3683	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3684	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3685
sahilmgandhi	18:6a4db94011d3	3686	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3687	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3688	}
sahilmgandhi	18:6a4db94011d3	3689	break;
sahilmgandhi	18:6a4db94011d3	3690	case TIM_DMA_TRIGGER:
sahilmgandhi	18:6a4db94011d3	3691	{
sahilmgandhi	18:6a4db94011d3	3692	/* Set the DMA Period elapsed callback */
sahilmgandhi	18:6a4db94011d3	3693	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
sahilmgandhi	18:6a4db94011d3	3694
sahilmgandhi	18:6a4db94011d3	3695	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	3696	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
sahilmgandhi	18:6a4db94011d3	3697
sahilmgandhi	18:6a4db94011d3	3698	/* Enable the DMA Stream */
sahilmgandhi	18:6a4db94011d3	3699	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	3700	}
sahilmgandhi	18:6a4db94011d3	3701	break;
sahilmgandhi	18:6a4db94011d3	3702	default:
sahilmgandhi	18:6a4db94011d3	3703	break;
sahilmgandhi	18:6a4db94011d3	3704	}
sahilmgandhi	18:6a4db94011d3	3705
sahilmgandhi	18:6a4db94011d3	3706	/* configure the DMA Burst Mode */
sahilmgandhi	18:6a4db94011d3	3707	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
sahilmgandhi	18:6a4db94011d3	3708
sahilmgandhi	18:6a4db94011d3	3709	/* Enable the TIM DMA Request */
sahilmgandhi	18:6a4db94011d3	3710	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
sahilmgandhi	18:6a4db94011d3	3711
sahilmgandhi	18:6a4db94011d3	3712	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	3713
sahilmgandhi	18:6a4db94011d3	3714	/* Return function status */
sahilmgandhi	18:6a4db94011d3	3715	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3716	}
sahilmgandhi	18:6a4db94011d3	3717
sahilmgandhi	18:6a4db94011d3	3718	/**
sahilmgandhi	18:6a4db94011d3	3719	* @brief Stop the DMA burst reading
sahilmgandhi	18:6a4db94011d3	3720	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3721	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3722	* @param BurstRequestSrc: TIM DMA Request sources to disable.
sahilmgandhi	18:6a4db94011d3	3723	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3724	*/
sahilmgandhi	18:6a4db94011d3	3725	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
sahilmgandhi	18:6a4db94011d3	3726	{
sahilmgandhi	18:6a4db94011d3	3727	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3728	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
sahilmgandhi	18:6a4db94011d3	3729
sahilmgandhi	18:6a4db94011d3	3730	/* Abort the DMA transfer (at least disable the DMA channel) */
sahilmgandhi	18:6a4db94011d3	3731	switch(BurstRequestSrc)
sahilmgandhi	18:6a4db94011d3	3732	{
sahilmgandhi	18:6a4db94011d3	3733	case TIM_DMA_UPDATE:
sahilmgandhi	18:6a4db94011d3	3734	{
sahilmgandhi	18:6a4db94011d3	3735	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
sahilmgandhi	18:6a4db94011d3	3736	}
sahilmgandhi	18:6a4db94011d3	3737	break;
sahilmgandhi	18:6a4db94011d3	3738	case TIM_DMA_CC1:
sahilmgandhi	18:6a4db94011d3	3739	{
sahilmgandhi	18:6a4db94011d3	3740	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
sahilmgandhi	18:6a4db94011d3	3741	}
sahilmgandhi	18:6a4db94011d3	3742	break;
sahilmgandhi	18:6a4db94011d3	3743	case TIM_DMA_CC2:
sahilmgandhi	18:6a4db94011d3	3744	{
sahilmgandhi	18:6a4db94011d3	3745	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
sahilmgandhi	18:6a4db94011d3	3746	}
sahilmgandhi	18:6a4db94011d3	3747	break;
sahilmgandhi	18:6a4db94011d3	3748	case TIM_DMA_CC3:
sahilmgandhi	18:6a4db94011d3	3749	{
sahilmgandhi	18:6a4db94011d3	3750	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
sahilmgandhi	18:6a4db94011d3	3751	}
sahilmgandhi	18:6a4db94011d3	3752	break;
sahilmgandhi	18:6a4db94011d3	3753	case TIM_DMA_CC4:
sahilmgandhi	18:6a4db94011d3	3754	{
sahilmgandhi	18:6a4db94011d3	3755	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
sahilmgandhi	18:6a4db94011d3	3756	}
sahilmgandhi	18:6a4db94011d3	3757	break;
sahilmgandhi	18:6a4db94011d3	3758	case TIM_DMA_COM:
sahilmgandhi	18:6a4db94011d3	3759	{
sahilmgandhi	18:6a4db94011d3	3760	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
sahilmgandhi	18:6a4db94011d3	3761	}
sahilmgandhi	18:6a4db94011d3	3762	break;
sahilmgandhi	18:6a4db94011d3	3763	case TIM_DMA_TRIGGER:
sahilmgandhi	18:6a4db94011d3	3764	{
sahilmgandhi	18:6a4db94011d3	3765	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
sahilmgandhi	18:6a4db94011d3	3766	}
sahilmgandhi	18:6a4db94011d3	3767	break;
sahilmgandhi	18:6a4db94011d3	3768	default:
sahilmgandhi	18:6a4db94011d3	3769	break;
sahilmgandhi	18:6a4db94011d3	3770	}
sahilmgandhi	18:6a4db94011d3	3771
sahilmgandhi	18:6a4db94011d3	3772	/* Disable the TIM Update DMA request */
sahilmgandhi	18:6a4db94011d3	3773	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
sahilmgandhi	18:6a4db94011d3	3774
sahilmgandhi	18:6a4db94011d3	3775	/* Return function status */
sahilmgandhi	18:6a4db94011d3	3776	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3777	}
sahilmgandhi	18:6a4db94011d3	3778
sahilmgandhi	18:6a4db94011d3	3779	/**
sahilmgandhi	18:6a4db94011d3	3780	* @brief Generate a software event
sahilmgandhi	18:6a4db94011d3	3781	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3782	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3783	* @param EventSource: specifies the event source.
sahilmgandhi	18:6a4db94011d3	3784	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	3785	* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
sahilmgandhi	18:6a4db94011d3	3786	* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
sahilmgandhi	18:6a4db94011d3	3787	* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
sahilmgandhi	18:6a4db94011d3	3788	* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
sahilmgandhi	18:6a4db94011d3	3789	* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
sahilmgandhi	18:6a4db94011d3	3790	* @arg TIM_EVENTSOURCE_COM: Timer COM event source
sahilmgandhi	18:6a4db94011d3	3791	* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
sahilmgandhi	18:6a4db94011d3	3792	* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
sahilmgandhi	18:6a4db94011d3	3793	* @note TIM6 and TIM7 can only generate an update event.
sahilmgandhi	18:6a4db94011d3	3794	* @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
sahilmgandhi	18:6a4db94011d3	3795	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3796	*/
sahilmgandhi	18:6a4db94011d3	3797
sahilmgandhi	18:6a4db94011d3	3798	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
sahilmgandhi	18:6a4db94011d3	3799	{
sahilmgandhi	18:6a4db94011d3	3800	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3801	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3802	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
sahilmgandhi	18:6a4db94011d3	3803
sahilmgandhi	18:6a4db94011d3	3804	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	3805	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	3806
sahilmgandhi	18:6a4db94011d3	3807	/* Change the TIM state */
sahilmgandhi	18:6a4db94011d3	3808	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	3809
sahilmgandhi	18:6a4db94011d3	3810	/* Set the event sources */
sahilmgandhi	18:6a4db94011d3	3811	htim->Instance->EGR = EventSource;
sahilmgandhi	18:6a4db94011d3	3812
sahilmgandhi	18:6a4db94011d3	3813	/* Change the TIM state */
sahilmgandhi	18:6a4db94011d3	3814	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	3815
sahilmgandhi	18:6a4db94011d3	3816	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	3817
sahilmgandhi	18:6a4db94011d3	3818	/* Return function status */
sahilmgandhi	18:6a4db94011d3	3819	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3820	}
sahilmgandhi	18:6a4db94011d3	3821
sahilmgandhi	18:6a4db94011d3	3822	/**
sahilmgandhi	18:6a4db94011d3	3823	* @brief Configures the OCRef clear feature
sahilmgandhi	18:6a4db94011d3	3824	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3825	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3826	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
sahilmgandhi	18:6a4db94011d3	3827	* contains the OCREF clear feature and parameters for the TIM peripheral.
sahilmgandhi	18:6a4db94011d3	3828	* @param Channel: specifies the TIM Channel.
sahilmgandhi	18:6a4db94011d3	3829	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	3830	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	3831	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	3832	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	3833	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	3834	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3835	*/
sahilmgandhi	18:6a4db94011d3	3836	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	3837	{
sahilmgandhi	18:6a4db94011d3	3838	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3839	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3840	assert_param(IS_TIM_CHANNELS(Channel));
sahilmgandhi	18:6a4db94011d3	3841	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
sahilmgandhi	18:6a4db94011d3	3842	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
sahilmgandhi	18:6a4db94011d3	3843	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
sahilmgandhi	18:6a4db94011d3	3844	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
sahilmgandhi	18:6a4db94011d3	3845
sahilmgandhi	18:6a4db94011d3	3846	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	3847	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	3848
sahilmgandhi	18:6a4db94011d3	3849	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	3850
sahilmgandhi	18:6a4db94011d3	3851	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
sahilmgandhi	18:6a4db94011d3	3852	{
sahilmgandhi	18:6a4db94011d3	3853	TIM_ETR_SetConfig(htim->Instance,
sahilmgandhi	18:6a4db94011d3	3854	sClearInputConfig->ClearInputPrescaler,
sahilmgandhi	18:6a4db94011d3	3855	sClearInputConfig->ClearInputPolarity,
sahilmgandhi	18:6a4db94011d3	3856	sClearInputConfig->ClearInputFilter);
sahilmgandhi	18:6a4db94011d3	3857	}
sahilmgandhi	18:6a4db94011d3	3858
sahilmgandhi	18:6a4db94011d3	3859	switch (Channel)
sahilmgandhi	18:6a4db94011d3	3860	{
sahilmgandhi	18:6a4db94011d3	3861	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	3862	{
sahilmgandhi	18:6a4db94011d3	3863	if(sClearInputConfig->ClearInputState != RESET)
sahilmgandhi	18:6a4db94011d3	3864	{
sahilmgandhi	18:6a4db94011d3	3865	/* Enable the Ocref clear feature for Channel 1 */
sahilmgandhi	18:6a4db94011d3	3866	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
sahilmgandhi	18:6a4db94011d3	3867	}
sahilmgandhi	18:6a4db94011d3	3868	else
sahilmgandhi	18:6a4db94011d3	3869	{
sahilmgandhi	18:6a4db94011d3	3870	/* Disable the Ocref clear feature for Channel 1 */
sahilmgandhi	18:6a4db94011d3	3871	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
sahilmgandhi	18:6a4db94011d3	3872	}
sahilmgandhi	18:6a4db94011d3	3873	}
sahilmgandhi	18:6a4db94011d3	3874	break;
sahilmgandhi	18:6a4db94011d3	3875	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	3876	{
sahilmgandhi	18:6a4db94011d3	3877	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3878	if(sClearInputConfig->ClearInputState != RESET)
sahilmgandhi	18:6a4db94011d3	3879	{
sahilmgandhi	18:6a4db94011d3	3880	/* Enable the Ocref clear feature for Channel 2 */
sahilmgandhi	18:6a4db94011d3	3881	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
sahilmgandhi	18:6a4db94011d3	3882	}
sahilmgandhi	18:6a4db94011d3	3883	else
sahilmgandhi	18:6a4db94011d3	3884	{
sahilmgandhi	18:6a4db94011d3	3885	/* Disable the Ocref clear feature for Channel 2 */
sahilmgandhi	18:6a4db94011d3	3886	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
sahilmgandhi	18:6a4db94011d3	3887	}
sahilmgandhi	18:6a4db94011d3	3888	}
sahilmgandhi	18:6a4db94011d3	3889	break;
sahilmgandhi	18:6a4db94011d3	3890	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	3891	{
sahilmgandhi	18:6a4db94011d3	3892	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3893	if(sClearInputConfig->ClearInputState != RESET)
sahilmgandhi	18:6a4db94011d3	3894	{
sahilmgandhi	18:6a4db94011d3	3895	/* Enable the Ocref clear feature for Channel 3 */
sahilmgandhi	18:6a4db94011d3	3896	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
sahilmgandhi	18:6a4db94011d3	3897	}
sahilmgandhi	18:6a4db94011d3	3898	else
sahilmgandhi	18:6a4db94011d3	3899	{
sahilmgandhi	18:6a4db94011d3	3900	/* Disable the Ocref clear feature for Channel 3 */
sahilmgandhi	18:6a4db94011d3	3901	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
sahilmgandhi	18:6a4db94011d3	3902	}
sahilmgandhi	18:6a4db94011d3	3903	}
sahilmgandhi	18:6a4db94011d3	3904	break;
sahilmgandhi	18:6a4db94011d3	3905	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	3906	{
sahilmgandhi	18:6a4db94011d3	3907	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3908	if(sClearInputConfig->ClearInputState != RESET)
sahilmgandhi	18:6a4db94011d3	3909	{
sahilmgandhi	18:6a4db94011d3	3910	/* Enable the Ocref clear feature for Channel 4 */
sahilmgandhi	18:6a4db94011d3	3911	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
sahilmgandhi	18:6a4db94011d3	3912	}
sahilmgandhi	18:6a4db94011d3	3913	else
sahilmgandhi	18:6a4db94011d3	3914	{
sahilmgandhi	18:6a4db94011d3	3915	/* Disable the Ocref clear feature for Channel 4 */
sahilmgandhi	18:6a4db94011d3	3916	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
sahilmgandhi	18:6a4db94011d3	3917	}
sahilmgandhi	18:6a4db94011d3	3918	}
sahilmgandhi	18:6a4db94011d3	3919	break;
sahilmgandhi	18:6a4db94011d3	3920	default:
sahilmgandhi	18:6a4db94011d3	3921	break;
sahilmgandhi	18:6a4db94011d3	3922	}
sahilmgandhi	18:6a4db94011d3	3923
sahilmgandhi	18:6a4db94011d3	3924	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	3925
sahilmgandhi	18:6a4db94011d3	3926	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	3927
sahilmgandhi	18:6a4db94011d3	3928	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	3929	}
sahilmgandhi	18:6a4db94011d3	3930
sahilmgandhi	18:6a4db94011d3	3931	/**
sahilmgandhi	18:6a4db94011d3	3932	* @brief Configures the clock source to be used
sahilmgandhi	18:6a4db94011d3	3933	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	3934	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	3935	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
sahilmgandhi	18:6a4db94011d3	3936	* contains the clock source information for the TIM peripheral.
sahilmgandhi	18:6a4db94011d3	3937	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	3938	*/
sahilmgandhi	18:6a4db94011d3	3939	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
sahilmgandhi	18:6a4db94011d3	3940	{
sahilmgandhi	18:6a4db94011d3	3941	uint32_t tmpsmcr = 0U;
sahilmgandhi	18:6a4db94011d3	3942
sahilmgandhi	18:6a4db94011d3	3943	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	3944	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	3945
sahilmgandhi	18:6a4db94011d3	3946	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	3947
sahilmgandhi	18:6a4db94011d3	3948	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	3949	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
sahilmgandhi	18:6a4db94011d3	3950
sahilmgandhi	18:6a4db94011d3	3951	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
sahilmgandhi	18:6a4db94011d3	3952	tmpsmcr = htim->Instance->SMCR;
sahilmgandhi	18:6a4db94011d3	3953	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
sahilmgandhi	18:6a4db94011d3	3954	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
sahilmgandhi	18:6a4db94011d3	3955	htim->Instance->SMCR = tmpsmcr;
sahilmgandhi	18:6a4db94011d3	3956
sahilmgandhi	18:6a4db94011d3	3957	switch (sClockSourceConfig->ClockSource)
sahilmgandhi	18:6a4db94011d3	3958	{
sahilmgandhi	18:6a4db94011d3	3959	case TIM_CLOCKSOURCE_INTERNAL:
sahilmgandhi	18:6a4db94011d3	3960	{
sahilmgandhi	18:6a4db94011d3	3961	assert_param(IS_TIM_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3962
sahilmgandhi	18:6a4db94011d3	3963	/* Disable slave mode to clock the prescaler directly with the internal clock */
sahilmgandhi	18:6a4db94011d3	3964	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
sahilmgandhi	18:6a4db94011d3	3965	}
sahilmgandhi	18:6a4db94011d3	3966	break;
sahilmgandhi	18:6a4db94011d3	3967
sahilmgandhi	18:6a4db94011d3	3968	case TIM_CLOCKSOURCE_ETRMODE1:
sahilmgandhi	18:6a4db94011d3	3969	{
sahilmgandhi	18:6a4db94011d3	3970	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3971
sahilmgandhi	18:6a4db94011d3	3972	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
sahilmgandhi	18:6a4db94011d3	3973	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
sahilmgandhi	18:6a4db94011d3	3974	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
sahilmgandhi	18:6a4db94011d3	3975
sahilmgandhi	18:6a4db94011d3	3976	/* Configure the ETR Clock source */
sahilmgandhi	18:6a4db94011d3	3977	TIM_ETR_SetConfig(htim->Instance,
sahilmgandhi	18:6a4db94011d3	3978	sClockSourceConfig->ClockPrescaler,
sahilmgandhi	18:6a4db94011d3	3979	sClockSourceConfig->ClockPolarity,
sahilmgandhi	18:6a4db94011d3	3980	sClockSourceConfig->ClockFilter);
sahilmgandhi	18:6a4db94011d3	3981	/* Get the TIMx SMCR register value */
sahilmgandhi	18:6a4db94011d3	3982	tmpsmcr = htim->Instance->SMCR;
sahilmgandhi	18:6a4db94011d3	3983	/* Reset the SMS and TS Bits */
sahilmgandhi	18:6a4db94011d3	3984	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
sahilmgandhi	18:6a4db94011d3	3985	/* Select the External clock mode1 and the ETRF trigger */
sahilmgandhi	18:6a4db94011d3	3986	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
sahilmgandhi	18:6a4db94011d3	3987	/* Write to TIMx SMCR */
sahilmgandhi	18:6a4db94011d3	3988	htim->Instance->SMCR = tmpsmcr;
sahilmgandhi	18:6a4db94011d3	3989	}
sahilmgandhi	18:6a4db94011d3	3990	break;
sahilmgandhi	18:6a4db94011d3	3991
sahilmgandhi	18:6a4db94011d3	3992	case TIM_CLOCKSOURCE_ETRMODE2:
sahilmgandhi	18:6a4db94011d3	3993	{
sahilmgandhi	18:6a4db94011d3	3994	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	3995
sahilmgandhi	18:6a4db94011d3	3996	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
sahilmgandhi	18:6a4db94011d3	3997	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
sahilmgandhi	18:6a4db94011d3	3998	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
sahilmgandhi	18:6a4db94011d3	3999
sahilmgandhi	18:6a4db94011d3	4000	/* Configure the ETR Clock source */
sahilmgandhi	18:6a4db94011d3	4001	TIM_ETR_SetConfig(htim->Instance,
sahilmgandhi	18:6a4db94011d3	4002	sClockSourceConfig->ClockPrescaler,
sahilmgandhi	18:6a4db94011d3	4003	sClockSourceConfig->ClockPolarity,
sahilmgandhi	18:6a4db94011d3	4004	sClockSourceConfig->ClockFilter);
sahilmgandhi	18:6a4db94011d3	4005	/* Enable the External clock mode2 */
sahilmgandhi	18:6a4db94011d3	4006	htim->Instance->SMCR \|= TIM_SMCR_ECE;
sahilmgandhi	18:6a4db94011d3	4007	}
sahilmgandhi	18:6a4db94011d3	4008	break;
sahilmgandhi	18:6a4db94011d3	4009
sahilmgandhi	18:6a4db94011d3	4010	case TIM_CLOCKSOURCE_TI1:
sahilmgandhi	18:6a4db94011d3	4011	{
sahilmgandhi	18:6a4db94011d3	4012	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4013
sahilmgandhi	18:6a4db94011d3	4014	/* Check TI1 input conditioning related parameters */
sahilmgandhi	18:6a4db94011d3	4015	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
sahilmgandhi	18:6a4db94011d3	4016	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
sahilmgandhi	18:6a4db94011d3	4017
sahilmgandhi	18:6a4db94011d3	4018	TIM_TI1_ConfigInputStage(htim->Instance,
sahilmgandhi	18:6a4db94011d3	4019	sClockSourceConfig->ClockPolarity,
sahilmgandhi	18:6a4db94011d3	4020	sClockSourceConfig->ClockFilter);
sahilmgandhi	18:6a4db94011d3	4021	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
sahilmgandhi	18:6a4db94011d3	4022	}
sahilmgandhi	18:6a4db94011d3	4023	break;
sahilmgandhi	18:6a4db94011d3	4024	case TIM_CLOCKSOURCE_TI2:
sahilmgandhi	18:6a4db94011d3	4025	{
sahilmgandhi	18:6a4db94011d3	4026	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4027
sahilmgandhi	18:6a4db94011d3	4028	/* Check TI1 input conditioning related parameters */
sahilmgandhi	18:6a4db94011d3	4029	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
sahilmgandhi	18:6a4db94011d3	4030	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
sahilmgandhi	18:6a4db94011d3	4031
sahilmgandhi	18:6a4db94011d3	4032	TIM_TI2_ConfigInputStage(htim->Instance,
sahilmgandhi	18:6a4db94011d3	4033	sClockSourceConfig->ClockPolarity,
sahilmgandhi	18:6a4db94011d3	4034	sClockSourceConfig->ClockFilter);
sahilmgandhi	18:6a4db94011d3	4035	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
sahilmgandhi	18:6a4db94011d3	4036	}
sahilmgandhi	18:6a4db94011d3	4037	break;
sahilmgandhi	18:6a4db94011d3	4038	case TIM_CLOCKSOURCE_TI1ED:
sahilmgandhi	18:6a4db94011d3	4039	{
sahilmgandhi	18:6a4db94011d3	4040	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4041
sahilmgandhi	18:6a4db94011d3	4042	/* Check TI1 input conditioning related parameters */
sahilmgandhi	18:6a4db94011d3	4043	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
sahilmgandhi	18:6a4db94011d3	4044	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
sahilmgandhi	18:6a4db94011d3	4045
sahilmgandhi	18:6a4db94011d3	4046	TIM_TI1_ConfigInputStage(htim->Instance,
sahilmgandhi	18:6a4db94011d3	4047	sClockSourceConfig->ClockPolarity,
sahilmgandhi	18:6a4db94011d3	4048	sClockSourceConfig->ClockFilter);
sahilmgandhi	18:6a4db94011d3	4049	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
sahilmgandhi	18:6a4db94011d3	4050	}
sahilmgandhi	18:6a4db94011d3	4051	break;
sahilmgandhi	18:6a4db94011d3	4052	case TIM_CLOCKSOURCE_ITR0:
sahilmgandhi	18:6a4db94011d3	4053	{
sahilmgandhi	18:6a4db94011d3	4054	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4055	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
sahilmgandhi	18:6a4db94011d3	4056	}
sahilmgandhi	18:6a4db94011d3	4057	break;
sahilmgandhi	18:6a4db94011d3	4058	case TIM_CLOCKSOURCE_ITR1:
sahilmgandhi	18:6a4db94011d3	4059	{
sahilmgandhi	18:6a4db94011d3	4060	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4061	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
sahilmgandhi	18:6a4db94011d3	4062	}
sahilmgandhi	18:6a4db94011d3	4063	break;
sahilmgandhi	18:6a4db94011d3	4064	case TIM_CLOCKSOURCE_ITR2:
sahilmgandhi	18:6a4db94011d3	4065	{
sahilmgandhi	18:6a4db94011d3	4066	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4067	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
sahilmgandhi	18:6a4db94011d3	4068	}
sahilmgandhi	18:6a4db94011d3	4069	break;
sahilmgandhi	18:6a4db94011d3	4070	case TIM_CLOCKSOURCE_ITR3:
sahilmgandhi	18:6a4db94011d3	4071	{
sahilmgandhi	18:6a4db94011d3	4072	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4073	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
sahilmgandhi	18:6a4db94011d3	4074	}
sahilmgandhi	18:6a4db94011d3	4075	break;
sahilmgandhi	18:6a4db94011d3	4076
sahilmgandhi	18:6a4db94011d3	4077	default:
sahilmgandhi	18:6a4db94011d3	4078	break;
sahilmgandhi	18:6a4db94011d3	4079	}
sahilmgandhi	18:6a4db94011d3	4080	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	4081
sahilmgandhi	18:6a4db94011d3	4082	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	4083
sahilmgandhi	18:6a4db94011d3	4084	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	4085	}
sahilmgandhi	18:6a4db94011d3	4086
sahilmgandhi	18:6a4db94011d3	4087	/**
sahilmgandhi	18:6a4db94011d3	4088	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
sahilmgandhi	18:6a4db94011d3	4089	* or a XOR combination between CH1_input, CH2_input & CH3_input
sahilmgandhi	18:6a4db94011d3	4090	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4091	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4092	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
sahilmgandhi	18:6a4db94011d3	4093	* output of a XOR gate.
sahilmgandhi	18:6a4db94011d3	4094	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	4095	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
sahilmgandhi	18:6a4db94011d3	4096	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
sahilmgandhi	18:6a4db94011d3	4097	* pins are connected to the TI1 input (XOR combination)
sahilmgandhi	18:6a4db94011d3	4098	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	4099	*/
sahilmgandhi	18:6a4db94011d3	4100	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
sahilmgandhi	18:6a4db94011d3	4101	{
sahilmgandhi	18:6a4db94011d3	4102	uint32_t tmpcr2 = 0U;
sahilmgandhi	18:6a4db94011d3	4103
sahilmgandhi	18:6a4db94011d3	4104	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	4105	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4106	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
sahilmgandhi	18:6a4db94011d3	4107
sahilmgandhi	18:6a4db94011d3	4108	/* Get the TIMx CR2 register value */
sahilmgandhi	18:6a4db94011d3	4109	tmpcr2 = htim->Instance->CR2;
sahilmgandhi	18:6a4db94011d3	4110
sahilmgandhi	18:6a4db94011d3	4111	/* Reset the TI1 selection */
sahilmgandhi	18:6a4db94011d3	4112	tmpcr2 &= ~TIM_CR2_TI1S;
sahilmgandhi	18:6a4db94011d3	4113
sahilmgandhi	18:6a4db94011d3	4114	/* Set the TI1 selection */
sahilmgandhi	18:6a4db94011d3	4115	tmpcr2 \|= TI1_Selection;
sahilmgandhi	18:6a4db94011d3	4116
sahilmgandhi	18:6a4db94011d3	4117	/* Write to TIMxCR2 */
sahilmgandhi	18:6a4db94011d3	4118	htim->Instance->CR2 = tmpcr2;
sahilmgandhi	18:6a4db94011d3	4119
sahilmgandhi	18:6a4db94011d3	4120	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	4121	}
sahilmgandhi	18:6a4db94011d3	4122
sahilmgandhi	18:6a4db94011d3	4123	/**
sahilmgandhi	18:6a4db94011d3	4124	* @brief Configures the TIM in Slave mode
sahilmgandhi	18:6a4db94011d3	4125	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4126	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4127	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
sahilmgandhi	18:6a4db94011d3	4128	* contains the selected trigger (internal trigger input, filtered
sahilmgandhi	18:6a4db94011d3	4129	* timer input or external trigger input) and the ) and the Slave
sahilmgandhi	18:6a4db94011d3	4130	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
sahilmgandhi	18:6a4db94011d3	4131	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	4132	*/
sahilmgandhi	18:6a4db94011d3	4133	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
sahilmgandhi	18:6a4db94011d3	4134	{
sahilmgandhi	18:6a4db94011d3	4135	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	4136	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4137	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
sahilmgandhi	18:6a4db94011d3	4138	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
sahilmgandhi	18:6a4db94011d3	4139
sahilmgandhi	18:6a4db94011d3	4140	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	4141
sahilmgandhi	18:6a4db94011d3	4142	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	4143
sahilmgandhi	18:6a4db94011d3	4144	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
sahilmgandhi	18:6a4db94011d3	4145
sahilmgandhi	18:6a4db94011d3	4146	/* Disable Trigger Interrupt */
sahilmgandhi	18:6a4db94011d3	4147	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
sahilmgandhi	18:6a4db94011d3	4148
sahilmgandhi	18:6a4db94011d3	4149	/* Disable Trigger DMA request */
sahilmgandhi	18:6a4db94011d3	4150	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
sahilmgandhi	18:6a4db94011d3	4151
sahilmgandhi	18:6a4db94011d3	4152	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	4153
sahilmgandhi	18:6a4db94011d3	4154	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	4155
sahilmgandhi	18:6a4db94011d3	4156	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	4157	}
sahilmgandhi	18:6a4db94011d3	4158
sahilmgandhi	18:6a4db94011d3	4159	/**
sahilmgandhi	18:6a4db94011d3	4160	* @brief Configures the TIM in Slave mode in interrupt mode
sahilmgandhi	18:6a4db94011d3	4161	* @param htim: TIM handle.
sahilmgandhi	18:6a4db94011d3	4162	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
sahilmgandhi	18:6a4db94011d3	4163	* contains the selected trigger (internal trigger input, filtered
sahilmgandhi	18:6a4db94011d3	4164	* timer input or external trigger input) and the ) and the Slave
sahilmgandhi	18:6a4db94011d3	4165	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
sahilmgandhi	18:6a4db94011d3	4166	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	4167	*/
sahilmgandhi	18:6a4db94011d3	4168	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
sahilmgandhi	18:6a4db94011d3	4169	TIM_SlaveConfigTypeDef * sSlaveConfig)
sahilmgandhi	18:6a4db94011d3	4170	{
sahilmgandhi	18:6a4db94011d3	4171	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	4172	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4173	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
sahilmgandhi	18:6a4db94011d3	4174	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
sahilmgandhi	18:6a4db94011d3	4175
sahilmgandhi	18:6a4db94011d3	4176	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	4177
sahilmgandhi	18:6a4db94011d3	4178	htim->State = HAL_TIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	4179
sahilmgandhi	18:6a4db94011d3	4180	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
sahilmgandhi	18:6a4db94011d3	4181
sahilmgandhi	18:6a4db94011d3	4182	/* Enable Trigger Interrupt */
sahilmgandhi	18:6a4db94011d3	4183	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
sahilmgandhi	18:6a4db94011d3	4184
sahilmgandhi	18:6a4db94011d3	4185	/* Disable Trigger DMA request */
sahilmgandhi	18:6a4db94011d3	4186	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
sahilmgandhi	18:6a4db94011d3	4187
sahilmgandhi	18:6a4db94011d3	4188	htim->State = HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	4189
sahilmgandhi	18:6a4db94011d3	4190	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	4191
sahilmgandhi	18:6a4db94011d3	4192	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	4193	}
sahilmgandhi	18:6a4db94011d3	4194
sahilmgandhi	18:6a4db94011d3	4195	/**
sahilmgandhi	18:6a4db94011d3	4196	* @brief Read the captured value from Capture Compare unit
sahilmgandhi	18:6a4db94011d3	4197	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4198	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4199	* @param Channel: TIM Channels to be enabled.
sahilmgandhi	18:6a4db94011d3	4200	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	4201	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	4202	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	4203	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	4204	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	4205	* @retval Captured value
sahilmgandhi	18:6a4db94011d3	4206	*/
sahilmgandhi	18:6a4db94011d3	4207	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
sahilmgandhi	18:6a4db94011d3	4208	{
sahilmgandhi	18:6a4db94011d3	4209	uint32_t tmpreg = 0U;
sahilmgandhi	18:6a4db94011d3	4210
sahilmgandhi	18:6a4db94011d3	4211	__HAL_LOCK(htim);
sahilmgandhi	18:6a4db94011d3	4212
sahilmgandhi	18:6a4db94011d3	4213	switch (Channel)
sahilmgandhi	18:6a4db94011d3	4214	{
sahilmgandhi	18:6a4db94011d3	4215	case TIM_CHANNEL_1:
sahilmgandhi	18:6a4db94011d3	4216	{
sahilmgandhi	18:6a4db94011d3	4217	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	4218	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4219
sahilmgandhi	18:6a4db94011d3	4220	/* Return the capture 1 value */
sahilmgandhi	18:6a4db94011d3	4221	tmpreg = htim->Instance->CCR1;
sahilmgandhi	18:6a4db94011d3	4222
sahilmgandhi	18:6a4db94011d3	4223	break;
sahilmgandhi	18:6a4db94011d3	4224	}
sahilmgandhi	18:6a4db94011d3	4225	case TIM_CHANNEL_2:
sahilmgandhi	18:6a4db94011d3	4226	{
sahilmgandhi	18:6a4db94011d3	4227	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	4228	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4229
sahilmgandhi	18:6a4db94011d3	4230	/* Return the capture 2 value */
sahilmgandhi	18:6a4db94011d3	4231	tmpreg = htim->Instance->CCR2;
sahilmgandhi	18:6a4db94011d3	4232
sahilmgandhi	18:6a4db94011d3	4233	break;
sahilmgandhi	18:6a4db94011d3	4234	}
sahilmgandhi	18:6a4db94011d3	4235
sahilmgandhi	18:6a4db94011d3	4236	case TIM_CHANNEL_3:
sahilmgandhi	18:6a4db94011d3	4237	{
sahilmgandhi	18:6a4db94011d3	4238	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	4239	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4240
sahilmgandhi	18:6a4db94011d3	4241	/* Return the capture 3 value */
sahilmgandhi	18:6a4db94011d3	4242	tmpreg = htim->Instance->CCR3;
sahilmgandhi	18:6a4db94011d3	4243
sahilmgandhi	18:6a4db94011d3	4244	break;
sahilmgandhi	18:6a4db94011d3	4245	}
sahilmgandhi	18:6a4db94011d3	4246
sahilmgandhi	18:6a4db94011d3	4247	case TIM_CHANNEL_4:
sahilmgandhi	18:6a4db94011d3	4248	{
sahilmgandhi	18:6a4db94011d3	4249	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	4250	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	4251
sahilmgandhi	18:6a4db94011d3	4252	/* Return the capture 4 value */
sahilmgandhi	18:6a4db94011d3	4253	tmpreg = htim->Instance->CCR4;
sahilmgandhi	18:6a4db94011d3	4254
sahilmgandhi	18:6a4db94011d3	4255	break;
sahilmgandhi	18:6a4db94011d3	4256	}
sahilmgandhi	18:6a4db94011d3	4257
sahilmgandhi	18:6a4db94011d3	4258	default:
sahilmgandhi	18:6a4db94011d3	4259	break;
sahilmgandhi	18:6a4db94011d3	4260	}
sahilmgandhi	18:6a4db94011d3	4261
sahilmgandhi	18:6a4db94011d3	4262	__HAL_UNLOCK(htim);
sahilmgandhi	18:6a4db94011d3	4263	return tmpreg;
sahilmgandhi	18:6a4db94011d3	4264	}
sahilmgandhi	18:6a4db94011d3	4265	/**
sahilmgandhi	18:6a4db94011d3	4266	* @}
sahilmgandhi	18:6a4db94011d3	4267	*/
sahilmgandhi	18:6a4db94011d3	4268
sahilmgandhi	18:6a4db94011d3	4269	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
sahilmgandhi	18:6a4db94011d3	4270	* @brief TIM Callbacks functions
sahilmgandhi	18:6a4db94011d3	4271	*
sahilmgandhi	18:6a4db94011d3	4272	@verbatim
sahilmgandhi	18:6a4db94011d3	4273	==============================================================================
sahilmgandhi	18:6a4db94011d3	4274	##### TIM Callbacks functions #####
sahilmgandhi	18:6a4db94011d3	4275	==============================================================================
sahilmgandhi	18:6a4db94011d3	4276	[..]
sahilmgandhi	18:6a4db94011d3	4277	This section provides TIM callback functions:
sahilmgandhi	18:6a4db94011d3	4278	(+) Timer Period elapsed callback
sahilmgandhi	18:6a4db94011d3	4279	(+) Timer Output Compare callback
sahilmgandhi	18:6a4db94011d3	4280	(+) Timer Input capture callback
sahilmgandhi	18:6a4db94011d3	4281	(+) Timer Trigger callback
sahilmgandhi	18:6a4db94011d3	4282	(+) Timer Error callback
sahilmgandhi	18:6a4db94011d3	4283
sahilmgandhi	18:6a4db94011d3	4284	@endverbatim
sahilmgandhi	18:6a4db94011d3	4285	* @{
sahilmgandhi	18:6a4db94011d3	4286	*/
sahilmgandhi	18:6a4db94011d3	4287
sahilmgandhi	18:6a4db94011d3	4288	/**
sahilmgandhi	18:6a4db94011d3	4289	* @brief Period elapsed callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	4290	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4291	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4292	* @retval None
sahilmgandhi	18:6a4db94011d3	4293	*/
sahilmgandhi	18:6a4db94011d3	4294	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4295	{
sahilmgandhi	18:6a4db94011d3	4296	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	4297	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	4298	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	4299	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	4300	*/
sahilmgandhi	18:6a4db94011d3	4301	}
sahilmgandhi	18:6a4db94011d3	4302
sahilmgandhi	18:6a4db94011d3	4303	/**
sahilmgandhi	18:6a4db94011d3	4304	* @brief Output Compare callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	4305	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4306	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4307	* @retval None
sahilmgandhi	18:6a4db94011d3	4308	*/
sahilmgandhi	18:6a4db94011d3	4309	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4310	{
sahilmgandhi	18:6a4db94011d3	4311	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	4312	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	4313	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	4314	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	4315	*/
sahilmgandhi	18:6a4db94011d3	4316	}
sahilmgandhi	18:6a4db94011d3	4317
sahilmgandhi	18:6a4db94011d3	4318	/**
sahilmgandhi	18:6a4db94011d3	4319	* @brief Input Capture callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	4320	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4321	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4322	* @retval None
sahilmgandhi	18:6a4db94011d3	4323	*/
sahilmgandhi	18:6a4db94011d3	4324	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4325	{
sahilmgandhi	18:6a4db94011d3	4326	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	4327	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	4328	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	4329	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	4330	*/
sahilmgandhi	18:6a4db94011d3	4331	}
sahilmgandhi	18:6a4db94011d3	4332
sahilmgandhi	18:6a4db94011d3	4333	/**
sahilmgandhi	18:6a4db94011d3	4334	* @brief PWM Pulse finished callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	4335	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4336	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4337	* @retval None
sahilmgandhi	18:6a4db94011d3	4338	*/
sahilmgandhi	18:6a4db94011d3	4339	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4340	{
sahilmgandhi	18:6a4db94011d3	4341	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	4342	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	4343	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	4344	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	4345	*/
sahilmgandhi	18:6a4db94011d3	4346	}
sahilmgandhi	18:6a4db94011d3	4347
sahilmgandhi	18:6a4db94011d3	4348	/**
sahilmgandhi	18:6a4db94011d3	4349	* @brief Hall Trigger detection callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	4350	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4351	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4352	* @retval None
sahilmgandhi	18:6a4db94011d3	4353	*/
sahilmgandhi	18:6a4db94011d3	4354	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4355	{
sahilmgandhi	18:6a4db94011d3	4356	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	4357	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	4358	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	4359	the HAL_TIM_TriggerCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	4360	*/
sahilmgandhi	18:6a4db94011d3	4361	}
sahilmgandhi	18:6a4db94011d3	4362
sahilmgandhi	18:6a4db94011d3	4363	/**
sahilmgandhi	18:6a4db94011d3	4364	* @brief Timer error callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	4365	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4366	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4367	* @retval None
sahilmgandhi	18:6a4db94011d3	4368	*/
sahilmgandhi	18:6a4db94011d3	4369	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4370	{
sahilmgandhi	18:6a4db94011d3	4371	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	4372	UNUSED(htim);
sahilmgandhi	18:6a4db94011d3	4373	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	4374	the HAL_TIM_ErrorCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	4375	*/
sahilmgandhi	18:6a4db94011d3	4376	}
sahilmgandhi	18:6a4db94011d3	4377	/**
sahilmgandhi	18:6a4db94011d3	4378	* @}
sahilmgandhi	18:6a4db94011d3	4379	*/
sahilmgandhi	18:6a4db94011d3	4380
sahilmgandhi	18:6a4db94011d3	4381	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
sahilmgandhi	18:6a4db94011d3	4382	* @brief Peripheral State functions
sahilmgandhi	18:6a4db94011d3	4383	*
sahilmgandhi	18:6a4db94011d3	4384	@verbatim
sahilmgandhi	18:6a4db94011d3	4385	==============================================================================
sahilmgandhi	18:6a4db94011d3	4386	##### Peripheral State functions #####
sahilmgandhi	18:6a4db94011d3	4387	==============================================================================
sahilmgandhi	18:6a4db94011d3	4388	[..]
sahilmgandhi	18:6a4db94011d3	4389	This subsection permits to get in run-time the status of the peripheral
sahilmgandhi	18:6a4db94011d3	4390	and the data flow.
sahilmgandhi	18:6a4db94011d3	4391
sahilmgandhi	18:6a4db94011d3	4392	@endverbatim
sahilmgandhi	18:6a4db94011d3	4393	* @{
sahilmgandhi	18:6a4db94011d3	4394	*/
sahilmgandhi	18:6a4db94011d3	4395
sahilmgandhi	18:6a4db94011d3	4396	/**
sahilmgandhi	18:6a4db94011d3	4397	* @brief Return the TIM Base state
sahilmgandhi	18:6a4db94011d3	4398	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4399	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4400	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	4401	*/
sahilmgandhi	18:6a4db94011d3	4402	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4403	{
sahilmgandhi	18:6a4db94011d3	4404	return htim->State;
sahilmgandhi	18:6a4db94011d3	4405	}
sahilmgandhi	18:6a4db94011d3	4406
sahilmgandhi	18:6a4db94011d3	4407	/**
sahilmgandhi	18:6a4db94011d3	4408	* @brief Return the TIM OC state
sahilmgandhi	18:6a4db94011d3	4409	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4410	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4411	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	4412	*/
sahilmgandhi	18:6a4db94011d3	4413	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4414	{
sahilmgandhi	18:6a4db94011d3	4415	return htim->State;
sahilmgandhi	18:6a4db94011d3	4416	}
sahilmgandhi	18:6a4db94011d3	4417
sahilmgandhi	18:6a4db94011d3	4418	/**
sahilmgandhi	18:6a4db94011d3	4419	* @brief Return the TIM PWM state
sahilmgandhi	18:6a4db94011d3	4420	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4421	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4422	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	4423	*/
sahilmgandhi	18:6a4db94011d3	4424	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4425	{
sahilmgandhi	18:6a4db94011d3	4426	return htim->State;
sahilmgandhi	18:6a4db94011d3	4427	}
sahilmgandhi	18:6a4db94011d3	4428
sahilmgandhi	18:6a4db94011d3	4429	/**
sahilmgandhi	18:6a4db94011d3	4430	* @brief Return the TIM Input Capture state
sahilmgandhi	18:6a4db94011d3	4431	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4432	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4433	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	4434	*/
sahilmgandhi	18:6a4db94011d3	4435	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4436	{
sahilmgandhi	18:6a4db94011d3	4437	return htim->State;
sahilmgandhi	18:6a4db94011d3	4438	}
sahilmgandhi	18:6a4db94011d3	4439
sahilmgandhi	18:6a4db94011d3	4440	/**
sahilmgandhi	18:6a4db94011d3	4441	* @brief Return the TIM One Pulse Mode state
sahilmgandhi	18:6a4db94011d3	4442	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4443	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4444	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	4445	*/
sahilmgandhi	18:6a4db94011d3	4446	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4447	{
sahilmgandhi	18:6a4db94011d3	4448	return htim->State;
sahilmgandhi	18:6a4db94011d3	4449	}
sahilmgandhi	18:6a4db94011d3	4450
sahilmgandhi	18:6a4db94011d3	4451	/**
sahilmgandhi	18:6a4db94011d3	4452	* @brief Return the TIM Encoder Mode state
sahilmgandhi	18:6a4db94011d3	4453	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4454	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4455	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	4456	*/
sahilmgandhi	18:6a4db94011d3	4457	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
sahilmgandhi	18:6a4db94011d3	4458	{
sahilmgandhi	18:6a4db94011d3	4459	return htim->State;
sahilmgandhi	18:6a4db94011d3	4460	}
sahilmgandhi	18:6a4db94011d3	4461	/**
sahilmgandhi	18:6a4db94011d3	4462	* @}
sahilmgandhi	18:6a4db94011d3	4463	*/
sahilmgandhi	18:6a4db94011d3	4464
sahilmgandhi	18:6a4db94011d3	4465	/**
sahilmgandhi	18:6a4db94011d3	4466	* @brief Time Base configuration
sahilmgandhi	18:6a4db94011d3	4467	* @param TIMx: TIM peripheral
sahilmgandhi	18:6a4db94011d3	4468	* @param Structure: pointer on TIM Time Base required parameters
sahilmgandhi	18:6a4db94011d3	4469	* @retval None
sahilmgandhi	18:6a4db94011d3	4470	*/
sahilmgandhi	18:6a4db94011d3	4471	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
sahilmgandhi	18:6a4db94011d3	4472	{
sahilmgandhi	18:6a4db94011d3	4473	uint32_t tmpcr1 = 0U;
sahilmgandhi	18:6a4db94011d3	4474	tmpcr1 = TIMx->CR1;
sahilmgandhi	18:6a4db94011d3	4475
sahilmgandhi	18:6a4db94011d3	4476	/* Set TIM Time Base Unit parameters ---------------------------------------*/
sahilmgandhi	18:6a4db94011d3	4477	if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
sahilmgandhi	18:6a4db94011d3	4478	{
sahilmgandhi	18:6a4db94011d3	4479	/* Select the Counter Mode */
sahilmgandhi	18:6a4db94011d3	4480	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
sahilmgandhi	18:6a4db94011d3	4481	tmpcr1 \|= Structure->CounterMode;
sahilmgandhi	18:6a4db94011d3	4482	}
sahilmgandhi	18:6a4db94011d3	4483
sahilmgandhi	18:6a4db94011d3	4484	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
sahilmgandhi	18:6a4db94011d3	4485	{
sahilmgandhi	18:6a4db94011d3	4486	/* Set the clock division */
sahilmgandhi	18:6a4db94011d3	4487	tmpcr1 &= ~TIM_CR1_CKD;
sahilmgandhi	18:6a4db94011d3	4488	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
sahilmgandhi	18:6a4db94011d3	4489	}
sahilmgandhi	18:6a4db94011d3	4490
sahilmgandhi	18:6a4db94011d3	4491	TIMx->CR1 = tmpcr1;
sahilmgandhi	18:6a4db94011d3	4492
sahilmgandhi	18:6a4db94011d3	4493	/* Set the Auto-reload value */
sahilmgandhi	18:6a4db94011d3	4494	TIMx->ARR = (uint32_t)Structure->Period ;
sahilmgandhi	18:6a4db94011d3	4495
sahilmgandhi	18:6a4db94011d3	4496	/* Set the Prescaler value */
sahilmgandhi	18:6a4db94011d3	4497	TIMx->PSC = (uint32_t)Structure->Prescaler;
sahilmgandhi	18:6a4db94011d3	4498
sahilmgandhi	18:6a4db94011d3	4499	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
sahilmgandhi	18:6a4db94011d3	4500	{
sahilmgandhi	18:6a4db94011d3	4501	/* Set the Repetition Counter value */
sahilmgandhi	18:6a4db94011d3	4502	TIMx->RCR = Structure->RepetitionCounter;
sahilmgandhi	18:6a4db94011d3	4503	}
sahilmgandhi	18:6a4db94011d3	4504
sahilmgandhi	18:6a4db94011d3	4505	/* Generate an update event to reload the Prescaler
sahilmgandhi	18:6a4db94011d3	4506	and the repetition counter(only for TIM1 and TIM8) value immediately */
sahilmgandhi	18:6a4db94011d3	4507	TIMx->EGR = TIM_EGR_UG;
sahilmgandhi	18:6a4db94011d3	4508	}
sahilmgandhi	18:6a4db94011d3	4509
sahilmgandhi	18:6a4db94011d3	4510	/**
sahilmgandhi	18:6a4db94011d3	4511	* @brief Configure the TI1 as Input.
sahilmgandhi	18:6a4db94011d3	4512	* @param TIMx to select the TIM peripheral.
sahilmgandhi	18:6a4db94011d3	4513	* @param TIM_ICPolarity : The Input Polarity.
sahilmgandhi	18:6a4db94011d3	4514	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	4515	* @arg TIM_ICPolarity_Rising
sahilmgandhi	18:6a4db94011d3	4516	* @arg TIM_ICPolarity_Falling
sahilmgandhi	18:6a4db94011d3	4517	* @arg TIM_ICPolarity_BothEdge
sahilmgandhi	18:6a4db94011d3	4518	* @param TIM_ICSelection: specifies the input to be used.
sahilmgandhi	18:6a4db94011d3	4519	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	4520	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
sahilmgandhi	18:6a4db94011d3	4521	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
sahilmgandhi	18:6a4db94011d3	4522	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
sahilmgandhi	18:6a4db94011d3	4523	* @param TIM_ICFilter: Specifies the Input Capture Filter.
sahilmgandhi	18:6a4db94011d3	4524	* This parameter must be a value between 0x00 and 0x0F.
sahilmgandhi	18:6a4db94011d3	4525	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
sahilmgandhi	18:6a4db94011d3	4526	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
sahilmgandhi	18:6a4db94011d3	4527	* protected against un-initialized filter and polarity values.
sahilmgandhi	18:6a4db94011d3	4528	* @retval None
sahilmgandhi	18:6a4db94011d3	4529	*/
sahilmgandhi	18:6a4db94011d3	4530	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
sahilmgandhi	18:6a4db94011d3	4531	uint32_t TIM_ICFilter)
sahilmgandhi	18:6a4db94011d3	4532	{
sahilmgandhi	18:6a4db94011d3	4533	uint32_t tmpccmr1 = 0U;
sahilmgandhi	18:6a4db94011d3	4534	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	4535
sahilmgandhi	18:6a4db94011d3	4536	/* Disable the Channel 1: Reset the CC1E Bit */
sahilmgandhi	18:6a4db94011d3	4537	TIMx->CCER &= ~TIM_CCER_CC1E;
sahilmgandhi	18:6a4db94011d3	4538	tmpccmr1 = TIMx->CCMR1;
sahilmgandhi	18:6a4db94011d3	4539	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	4540
sahilmgandhi	18:6a4db94011d3	4541	/* Select the Input */
sahilmgandhi	18:6a4db94011d3	4542	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
sahilmgandhi	18:6a4db94011d3	4543	{
sahilmgandhi	18:6a4db94011d3	4544	tmpccmr1 &= ~TIM_CCMR1_CC1S;
sahilmgandhi	18:6a4db94011d3	4545	tmpccmr1 \|= TIM_ICSelection;
sahilmgandhi	18:6a4db94011d3	4546	}
sahilmgandhi	18:6a4db94011d3	4547	else
sahilmgandhi	18:6a4db94011d3	4548	{
sahilmgandhi	18:6a4db94011d3	4549	tmpccmr1 &= ~TIM_CCMR1_CC1S;
sahilmgandhi	18:6a4db94011d3	4550	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
sahilmgandhi	18:6a4db94011d3	4551	}
sahilmgandhi	18:6a4db94011d3	4552
sahilmgandhi	18:6a4db94011d3	4553	/* Set the filter */
sahilmgandhi	18:6a4db94011d3	4554	tmpccmr1 &= ~TIM_CCMR1_IC1F;
sahilmgandhi	18:6a4db94011d3	4555	tmpccmr1 \|= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
sahilmgandhi	18:6a4db94011d3	4556
sahilmgandhi	18:6a4db94011d3	4557	/* Select the Polarity and set the CC1E Bit */
sahilmgandhi	18:6a4db94011d3	4558	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
sahilmgandhi	18:6a4db94011d3	4559	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
sahilmgandhi	18:6a4db94011d3	4560
sahilmgandhi	18:6a4db94011d3	4561	/* Write to TIMx CCMR1 and CCER registers */
sahilmgandhi	18:6a4db94011d3	4562	TIMx->CCMR1 = tmpccmr1;
sahilmgandhi	18:6a4db94011d3	4563	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	4564	}
sahilmgandhi	18:6a4db94011d3	4565
sahilmgandhi	18:6a4db94011d3	4566	/**
sahilmgandhi	18:6a4db94011d3	4567	* @brief Time Output Compare 2 configuration
sahilmgandhi	18:6a4db94011d3	4568	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	4569	* @param OC_Config: The output configuration structure
sahilmgandhi	18:6a4db94011d3	4570	* @retval None
sahilmgandhi	18:6a4db94011d3	4571	*/
sahilmgandhi	18:6a4db94011d3	4572	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
sahilmgandhi	18:6a4db94011d3	4573	{
sahilmgandhi	18:6a4db94011d3	4574	uint32_t tmpccmrx = 0U;
sahilmgandhi	18:6a4db94011d3	4575	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	4576	uint32_t tmpcr2 = 0U;
sahilmgandhi	18:6a4db94011d3	4577
sahilmgandhi	18:6a4db94011d3	4578	/* Disable the Channel 2: Reset the CC2E Bit */
sahilmgandhi	18:6a4db94011d3	4579	TIMx->CCER &= ~TIM_CCER_CC2E;
sahilmgandhi	18:6a4db94011d3	4580
sahilmgandhi	18:6a4db94011d3	4581	/* Get the TIMx CCER register value */
sahilmgandhi	18:6a4db94011d3	4582	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	4583	/* Get the TIMx CR2 register value */
sahilmgandhi	18:6a4db94011d3	4584	tmpcr2 = TIMx->CR2;
sahilmgandhi	18:6a4db94011d3	4585
sahilmgandhi	18:6a4db94011d3	4586	/* Get the TIMx CCMR1 register value */
sahilmgandhi	18:6a4db94011d3	4587	tmpccmrx = TIMx->CCMR1;
sahilmgandhi	18:6a4db94011d3	4588
sahilmgandhi	18:6a4db94011d3	4589	/* Reset the Output Compare mode and Capture/Compare selection Bits */
sahilmgandhi	18:6a4db94011d3	4590	tmpccmrx &= ~TIM_CCMR1_OC2M;
sahilmgandhi	18:6a4db94011d3	4591	tmpccmrx &= ~TIM_CCMR1_CC2S;
sahilmgandhi	18:6a4db94011d3	4592
sahilmgandhi	18:6a4db94011d3	4593	/* Select the Output Compare Mode */
sahilmgandhi	18:6a4db94011d3	4594	tmpccmrx \|= (OC_Config->OCMode << 8U);
sahilmgandhi	18:6a4db94011d3	4595
sahilmgandhi	18:6a4db94011d3	4596	/* Reset the Output Polarity level */
sahilmgandhi	18:6a4db94011d3	4597	tmpccer &= ~TIM_CCER_CC2P;
sahilmgandhi	18:6a4db94011d3	4598	/* Set the Output Compare Polarity */
sahilmgandhi	18:6a4db94011d3	4599	tmpccer \|= (OC_Config->OCPolarity << 4U);
sahilmgandhi	18:6a4db94011d3	4600
sahilmgandhi	18:6a4db94011d3	4601	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
sahilmgandhi	18:6a4db94011d3	4602	{
sahilmgandhi	18:6a4db94011d3	4603	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
sahilmgandhi	18:6a4db94011d3	4604
sahilmgandhi	18:6a4db94011d3	4605	/* Reset the Output N Polarity level */
sahilmgandhi	18:6a4db94011d3	4606	tmpccer &= ~TIM_CCER_CC2NP;
sahilmgandhi	18:6a4db94011d3	4607	/* Set the Output N Polarity */
sahilmgandhi	18:6a4db94011d3	4608	tmpccer \|= (OC_Config->OCNPolarity << 4U);
sahilmgandhi	18:6a4db94011d3	4609	/* Reset the Output N State */
sahilmgandhi	18:6a4db94011d3	4610	tmpccer &= ~TIM_CCER_CC2NE;
sahilmgandhi	18:6a4db94011d3	4611
sahilmgandhi	18:6a4db94011d3	4612	/* Reset the Output Compare and Output Compare N IDLE State */
sahilmgandhi	18:6a4db94011d3	4613	tmpcr2 &= ~TIM_CR2_OIS2;
sahilmgandhi	18:6a4db94011d3	4614	tmpcr2 &= ~TIM_CR2_OIS2N;
sahilmgandhi	18:6a4db94011d3	4615	/* Set the Output Idle state */
sahilmgandhi	18:6a4db94011d3	4616	tmpcr2 \|= (OC_Config->OCIdleState << 2U);
sahilmgandhi	18:6a4db94011d3	4617	/* Set the Output N Idle state */
sahilmgandhi	18:6a4db94011d3	4618	tmpcr2 \|= (OC_Config->OCNIdleState << 2U);
sahilmgandhi	18:6a4db94011d3	4619	}
sahilmgandhi	18:6a4db94011d3	4620	/* Write to TIMx CR2 */
sahilmgandhi	18:6a4db94011d3	4621	TIMx->CR2 = tmpcr2;
sahilmgandhi	18:6a4db94011d3	4622
sahilmgandhi	18:6a4db94011d3	4623	/* Write to TIMx CCMR1 */
sahilmgandhi	18:6a4db94011d3	4624	TIMx->CCMR1 = tmpccmrx;
sahilmgandhi	18:6a4db94011d3	4625
sahilmgandhi	18:6a4db94011d3	4626	/* Set the Capture Compare Register value */
sahilmgandhi	18:6a4db94011d3	4627	TIMx->CCR2 = OC_Config->Pulse;
sahilmgandhi	18:6a4db94011d3	4628
sahilmgandhi	18:6a4db94011d3	4629	/* Write to TIMx CCER */
sahilmgandhi	18:6a4db94011d3	4630	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	4631	}
sahilmgandhi	18:6a4db94011d3	4632
sahilmgandhi	18:6a4db94011d3	4633	/**
sahilmgandhi	18:6a4db94011d3	4634	* @brief TIM DMA Delay Pulse complete callback.
sahilmgandhi	18:6a4db94011d3	4635	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4636	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	4637	* @retval None
sahilmgandhi	18:6a4db94011d3	4638	*/
sahilmgandhi	18:6a4db94011d3	4639	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	4640	{
sahilmgandhi	18:6a4db94011d3	4641	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	4642
sahilmgandhi	18:6a4db94011d3	4643	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	4644
sahilmgandhi	18:6a4db94011d3	4645	if(hdma == htim->hdma[TIM_DMA_ID_CC1])
sahilmgandhi	18:6a4db94011d3	4646	{
sahilmgandhi	18:6a4db94011d3	4647	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
sahilmgandhi	18:6a4db94011d3	4648	}
sahilmgandhi	18:6a4db94011d3	4649	else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
sahilmgandhi	18:6a4db94011d3	4650	{
sahilmgandhi	18:6a4db94011d3	4651	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
sahilmgandhi	18:6a4db94011d3	4652	}
sahilmgandhi	18:6a4db94011d3	4653	else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
sahilmgandhi	18:6a4db94011d3	4654	{
sahilmgandhi	18:6a4db94011d3	4655	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
sahilmgandhi	18:6a4db94011d3	4656	}
sahilmgandhi	18:6a4db94011d3	4657	else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
sahilmgandhi	18:6a4db94011d3	4658	{
sahilmgandhi	18:6a4db94011d3	4659	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
sahilmgandhi	18:6a4db94011d3	4660	}
sahilmgandhi	18:6a4db94011d3	4661
sahilmgandhi	18:6a4db94011d3	4662	HAL_TIM_PWM_PulseFinishedCallback(htim);
sahilmgandhi	18:6a4db94011d3	4663
sahilmgandhi	18:6a4db94011d3	4664	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
sahilmgandhi	18:6a4db94011d3	4665	}
sahilmgandhi	18:6a4db94011d3	4666
sahilmgandhi	18:6a4db94011d3	4667	/**
sahilmgandhi	18:6a4db94011d3	4668	* @brief TIM DMA error callback
sahilmgandhi	18:6a4db94011d3	4669	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4670	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	4671	* @retval None
sahilmgandhi	18:6a4db94011d3	4672	*/
sahilmgandhi	18:6a4db94011d3	4673	void TIM_DMAError(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	4674	{
sahilmgandhi	18:6a4db94011d3	4675	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	4676
sahilmgandhi	18:6a4db94011d3	4677	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	4678
sahilmgandhi	18:6a4db94011d3	4679	HAL_TIM_ErrorCallback(htim);
sahilmgandhi	18:6a4db94011d3	4680	}
sahilmgandhi	18:6a4db94011d3	4681
sahilmgandhi	18:6a4db94011d3	4682	/**
sahilmgandhi	18:6a4db94011d3	4683	* @brief TIM DMA Capture complete callback.
sahilmgandhi	18:6a4db94011d3	4684	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4685	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	4686	* @retval None
sahilmgandhi	18:6a4db94011d3	4687	*/
sahilmgandhi	18:6a4db94011d3	4688	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	4689	{
sahilmgandhi	18:6a4db94011d3	4690	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	4691
sahilmgandhi	18:6a4db94011d3	4692	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	4693
sahilmgandhi	18:6a4db94011d3	4694	if(hdma == htim->hdma[TIM_DMA_ID_CC1])
sahilmgandhi	18:6a4db94011d3	4695	{
sahilmgandhi	18:6a4db94011d3	4696	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
sahilmgandhi	18:6a4db94011d3	4697	}
sahilmgandhi	18:6a4db94011d3	4698	else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
sahilmgandhi	18:6a4db94011d3	4699	{
sahilmgandhi	18:6a4db94011d3	4700	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
sahilmgandhi	18:6a4db94011d3	4701	}
sahilmgandhi	18:6a4db94011d3	4702	else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
sahilmgandhi	18:6a4db94011d3	4703	{
sahilmgandhi	18:6a4db94011d3	4704	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
sahilmgandhi	18:6a4db94011d3	4705	}
sahilmgandhi	18:6a4db94011d3	4706	else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
sahilmgandhi	18:6a4db94011d3	4707	{
sahilmgandhi	18:6a4db94011d3	4708	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
sahilmgandhi	18:6a4db94011d3	4709	}
sahilmgandhi	18:6a4db94011d3	4710
sahilmgandhi	18:6a4db94011d3	4711	HAL_TIM_IC_CaptureCallback(htim);
sahilmgandhi	18:6a4db94011d3	4712
sahilmgandhi	18:6a4db94011d3	4713	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
sahilmgandhi	18:6a4db94011d3	4714	}
sahilmgandhi	18:6a4db94011d3	4715
sahilmgandhi	18:6a4db94011d3	4716	/**
sahilmgandhi	18:6a4db94011d3	4717	* @brief Enables or disables the TIM Capture Compare Channel x.
sahilmgandhi	18:6a4db94011d3	4718	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	4719	* @param Channel: specifies the TIM Channel
sahilmgandhi	18:6a4db94011d3	4720	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	4721	* @arg TIM_Channel_1: TIM Channel 1
sahilmgandhi	18:6a4db94011d3	4722	* @arg TIM_Channel_2: TIM Channel 2
sahilmgandhi	18:6a4db94011d3	4723	* @arg TIM_Channel_3: TIM Channel 3
sahilmgandhi	18:6a4db94011d3	4724	* @arg TIM_Channel_4: TIM Channel 4
sahilmgandhi	18:6a4db94011d3	4725	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
sahilmgandhi	18:6a4db94011d3	4726	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
sahilmgandhi	18:6a4db94011d3	4727	* @retval None
sahilmgandhi	18:6a4db94011d3	4728	*/
sahilmgandhi	18:6a4db94011d3	4729	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
sahilmgandhi	18:6a4db94011d3	4730	{
sahilmgandhi	18:6a4db94011d3	4731	uint32_t tmp = 0;
sahilmgandhi	18:6a4db94011d3	4732
sahilmgandhi	18:6a4db94011d3	4733	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	4734	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
sahilmgandhi	18:6a4db94011d3	4735	assert_param(IS_TIM_CHANNELS(Channel));
sahilmgandhi	18:6a4db94011d3	4736
sahilmgandhi	18:6a4db94011d3	4737	tmp = TIM_CCER_CC1E << Channel;
sahilmgandhi	18:6a4db94011d3	4738
sahilmgandhi	18:6a4db94011d3	4739	/* Reset the CCxE Bit */
sahilmgandhi	18:6a4db94011d3	4740	TIMx->CCER &= ~tmp;
sahilmgandhi	18:6a4db94011d3	4741
sahilmgandhi	18:6a4db94011d3	4742	/* Set or reset the CCxE Bit */
sahilmgandhi	18:6a4db94011d3	4743	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
sahilmgandhi	18:6a4db94011d3	4744	}
sahilmgandhi	18:6a4db94011d3	4745
sahilmgandhi	18:6a4db94011d3	4746	/**
sahilmgandhi	18:6a4db94011d3	4747	* @brief TIM DMA Period Elapse complete callback.
sahilmgandhi	18:6a4db94011d3	4748	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4749	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	4750	* @retval None
sahilmgandhi	18:6a4db94011d3	4751	*/
sahilmgandhi	18:6a4db94011d3	4752	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	4753	{
sahilmgandhi	18:6a4db94011d3	4754	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	4755
sahilmgandhi	18:6a4db94011d3	4756	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	4757
sahilmgandhi	18:6a4db94011d3	4758	HAL_TIM_PeriodElapsedCallback(htim);
sahilmgandhi	18:6a4db94011d3	4759	}
sahilmgandhi	18:6a4db94011d3	4760
sahilmgandhi	18:6a4db94011d3	4761	/**
sahilmgandhi	18:6a4db94011d3	4762	* @brief TIM DMA Trigger callback.
sahilmgandhi	18:6a4db94011d3	4763	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4764	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	4765	* @retval None
sahilmgandhi	18:6a4db94011d3	4766	*/
sahilmgandhi	18:6a4db94011d3	4767	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	4768	{
sahilmgandhi	18:6a4db94011d3	4769	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	4770
sahilmgandhi	18:6a4db94011d3	4771	htim->State= HAL_TIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	4772
sahilmgandhi	18:6a4db94011d3	4773	HAL_TIM_TriggerCallback(htim);
sahilmgandhi	18:6a4db94011d3	4774	}
sahilmgandhi	18:6a4db94011d3	4775
sahilmgandhi	18:6a4db94011d3	4776	/**
sahilmgandhi	18:6a4db94011d3	4777	* @brief Time Output Compare 1 configuration
sahilmgandhi	18:6a4db94011d3	4778	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	4779	* @param OC_Config: The output configuration structure
sahilmgandhi	18:6a4db94011d3	4780	* @retval None
sahilmgandhi	18:6a4db94011d3	4781	*/
sahilmgandhi	18:6a4db94011d3	4782	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
sahilmgandhi	18:6a4db94011d3	4783	{
sahilmgandhi	18:6a4db94011d3	4784	uint32_t tmpccmrx = 0U;
sahilmgandhi	18:6a4db94011d3	4785	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	4786	uint32_t tmpcr2 = 0U;
sahilmgandhi	18:6a4db94011d3	4787
sahilmgandhi	18:6a4db94011d3	4788	/* Disable the Channel 1: Reset the CC1E Bit */
sahilmgandhi	18:6a4db94011d3	4789	TIMx->CCER &= ~TIM_CCER_CC1E;
sahilmgandhi	18:6a4db94011d3	4790
sahilmgandhi	18:6a4db94011d3	4791	/* Get the TIMx CCER register value */
sahilmgandhi	18:6a4db94011d3	4792	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	4793	/* Get the TIMx CR2 register value */
sahilmgandhi	18:6a4db94011d3	4794	tmpcr2 = TIMx->CR2;
sahilmgandhi	18:6a4db94011d3	4795
sahilmgandhi	18:6a4db94011d3	4796	/* Get the TIMx CCMR1 register value */
sahilmgandhi	18:6a4db94011d3	4797	tmpccmrx = TIMx->CCMR1;
sahilmgandhi	18:6a4db94011d3	4798
sahilmgandhi	18:6a4db94011d3	4799	/* Reset the Output Compare Mode Bits */
sahilmgandhi	18:6a4db94011d3	4800	tmpccmrx &= ~TIM_CCMR1_OC1M;
sahilmgandhi	18:6a4db94011d3	4801	tmpccmrx &= ~TIM_CCMR1_CC1S;
sahilmgandhi	18:6a4db94011d3	4802	/* Select the Output Compare Mode */
sahilmgandhi	18:6a4db94011d3	4803	tmpccmrx \|= OC_Config->OCMode;
sahilmgandhi	18:6a4db94011d3	4804
sahilmgandhi	18:6a4db94011d3	4805	/* Reset the Output Polarity level */
sahilmgandhi	18:6a4db94011d3	4806	tmpccer &= ~TIM_CCER_CC1P;
sahilmgandhi	18:6a4db94011d3	4807	/* Set the Output Compare Polarity */
sahilmgandhi	18:6a4db94011d3	4808	tmpccer \|= OC_Config->OCPolarity;
sahilmgandhi	18:6a4db94011d3	4809
sahilmgandhi	18:6a4db94011d3	4810
sahilmgandhi	18:6a4db94011d3	4811	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
sahilmgandhi	18:6a4db94011d3	4812	{
sahilmgandhi	18:6a4db94011d3	4813	/* Reset the Output N Polarity level */
sahilmgandhi	18:6a4db94011d3	4814	tmpccer &= ~TIM_CCER_CC1NP;
sahilmgandhi	18:6a4db94011d3	4815	/* Set the Output N Polarity */
sahilmgandhi	18:6a4db94011d3	4816	tmpccer \|= OC_Config->OCNPolarity;
sahilmgandhi	18:6a4db94011d3	4817	/* Reset the Output N State */
sahilmgandhi	18:6a4db94011d3	4818	tmpccer &= ~TIM_CCER_CC1NE;
sahilmgandhi	18:6a4db94011d3	4819
sahilmgandhi	18:6a4db94011d3	4820	/* Reset the Output Compare and Output Compare N IDLE State */
sahilmgandhi	18:6a4db94011d3	4821	tmpcr2 &= ~TIM_CR2_OIS1;
sahilmgandhi	18:6a4db94011d3	4822	tmpcr2 &= ~TIM_CR2_OIS1N;
sahilmgandhi	18:6a4db94011d3	4823	/* Set the Output Idle state */
sahilmgandhi	18:6a4db94011d3	4824	tmpcr2 \|= OC_Config->OCIdleState;
sahilmgandhi	18:6a4db94011d3	4825	/* Set the Output N Idle state */
sahilmgandhi	18:6a4db94011d3	4826	tmpcr2 \|= OC_Config->OCNIdleState;
sahilmgandhi	18:6a4db94011d3	4827	}
sahilmgandhi	18:6a4db94011d3	4828	/* Write to TIMx CR2 */
sahilmgandhi	18:6a4db94011d3	4829	TIMx->CR2 = tmpcr2;
sahilmgandhi	18:6a4db94011d3	4830
sahilmgandhi	18:6a4db94011d3	4831	/* Write to TIMx CCMR1 */
sahilmgandhi	18:6a4db94011d3	4832	TIMx->CCMR1 = tmpccmrx;
sahilmgandhi	18:6a4db94011d3	4833
sahilmgandhi	18:6a4db94011d3	4834	/* Set the Capture Compare Register value */
sahilmgandhi	18:6a4db94011d3	4835	TIMx->CCR1 = OC_Config->Pulse;
sahilmgandhi	18:6a4db94011d3	4836
sahilmgandhi	18:6a4db94011d3	4837	/* Write to TIMx CCER */
sahilmgandhi	18:6a4db94011d3	4838	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	4839	}
sahilmgandhi	18:6a4db94011d3	4840
sahilmgandhi	18:6a4db94011d3	4841	/**
sahilmgandhi	18:6a4db94011d3	4842	* @brief Time Output Compare 3 configuration
sahilmgandhi	18:6a4db94011d3	4843	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	4844	* @param OC_Config: The output configuration structure
sahilmgandhi	18:6a4db94011d3	4845	* @retval None
sahilmgandhi	18:6a4db94011d3	4846	*/
sahilmgandhi	18:6a4db94011d3	4847	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
sahilmgandhi	18:6a4db94011d3	4848	{
sahilmgandhi	18:6a4db94011d3	4849	uint32_t tmpccmrx = 0U;
sahilmgandhi	18:6a4db94011d3	4850	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	4851	uint32_t tmpcr2 = 0U;
sahilmgandhi	18:6a4db94011d3	4852
sahilmgandhi	18:6a4db94011d3	4853	/* Disable the Channel 3: Reset the CC2E Bit */
sahilmgandhi	18:6a4db94011d3	4854	TIMx->CCER &= ~TIM_CCER_CC3E;
sahilmgandhi	18:6a4db94011d3	4855
sahilmgandhi	18:6a4db94011d3	4856	/* Get the TIMx CCER register value */
sahilmgandhi	18:6a4db94011d3	4857	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	4858	/* Get the TIMx CR2 register value */
sahilmgandhi	18:6a4db94011d3	4859	tmpcr2 = TIMx->CR2;
sahilmgandhi	18:6a4db94011d3	4860
sahilmgandhi	18:6a4db94011d3	4861	/* Get the TIMx CCMR2 register value */
sahilmgandhi	18:6a4db94011d3	4862	tmpccmrx = TIMx->CCMR2;
sahilmgandhi	18:6a4db94011d3	4863
sahilmgandhi	18:6a4db94011d3	4864	/* Reset the Output Compare mode and Capture/Compare selection Bits */
sahilmgandhi	18:6a4db94011d3	4865	tmpccmrx &= ~TIM_CCMR2_OC3M;
sahilmgandhi	18:6a4db94011d3	4866	tmpccmrx &= ~TIM_CCMR2_CC3S;
sahilmgandhi	18:6a4db94011d3	4867	/* Select the Output Compare Mode */
sahilmgandhi	18:6a4db94011d3	4868	tmpccmrx \|= OC_Config->OCMode;
sahilmgandhi	18:6a4db94011d3	4869
sahilmgandhi	18:6a4db94011d3	4870	/* Reset the Output Polarity level */
sahilmgandhi	18:6a4db94011d3	4871	tmpccer &= ~TIM_CCER_CC3P;
sahilmgandhi	18:6a4db94011d3	4872	/* Set the Output Compare Polarity */
sahilmgandhi	18:6a4db94011d3	4873	tmpccer \|= (OC_Config->OCPolarity << 8U);
sahilmgandhi	18:6a4db94011d3	4874
sahilmgandhi	18:6a4db94011d3	4875	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
sahilmgandhi	18:6a4db94011d3	4876	{
sahilmgandhi	18:6a4db94011d3	4877	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
sahilmgandhi	18:6a4db94011d3	4878	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
sahilmgandhi	18:6a4db94011d3	4879	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
sahilmgandhi	18:6a4db94011d3	4880
sahilmgandhi	18:6a4db94011d3	4881	/* Reset the Output N Polarity level */
sahilmgandhi	18:6a4db94011d3	4882	tmpccer &= ~TIM_CCER_CC3NP;
sahilmgandhi	18:6a4db94011d3	4883	/* Set the Output N Polarity */
sahilmgandhi	18:6a4db94011d3	4884	tmpccer \|= (OC_Config->OCNPolarity << 8U);
sahilmgandhi	18:6a4db94011d3	4885	/* Reset the Output N State */
sahilmgandhi	18:6a4db94011d3	4886	tmpccer &= ~TIM_CCER_CC3NE;
sahilmgandhi	18:6a4db94011d3	4887
sahilmgandhi	18:6a4db94011d3	4888	/* Reset the Output Compare and Output Compare N IDLE State */
sahilmgandhi	18:6a4db94011d3	4889	tmpcr2 &= ~TIM_CR2_OIS3;
sahilmgandhi	18:6a4db94011d3	4890	tmpcr2 &= ~TIM_CR2_OIS3N;
sahilmgandhi	18:6a4db94011d3	4891	/* Set the Output Idle state */
sahilmgandhi	18:6a4db94011d3	4892	tmpcr2 \|= (OC_Config->OCIdleState << 4U);
sahilmgandhi	18:6a4db94011d3	4893	/* Set the Output N Idle state */
sahilmgandhi	18:6a4db94011d3	4894	tmpcr2 \|= (OC_Config->OCNIdleState << 4U);
sahilmgandhi	18:6a4db94011d3	4895	}
sahilmgandhi	18:6a4db94011d3	4896	/* Write to TIMx CR2 */
sahilmgandhi	18:6a4db94011d3	4897	TIMx->CR2 = tmpcr2;
sahilmgandhi	18:6a4db94011d3	4898
sahilmgandhi	18:6a4db94011d3	4899	/* Write to TIMx CCMR2 */
sahilmgandhi	18:6a4db94011d3	4900	TIMx->CCMR2 = tmpccmrx;
sahilmgandhi	18:6a4db94011d3	4901
sahilmgandhi	18:6a4db94011d3	4902	/* Set the Capture Compare Register value */
sahilmgandhi	18:6a4db94011d3	4903	TIMx->CCR3 = OC_Config->Pulse;
sahilmgandhi	18:6a4db94011d3	4904
sahilmgandhi	18:6a4db94011d3	4905	/* Write to TIMx CCER */
sahilmgandhi	18:6a4db94011d3	4906	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	4907	}
sahilmgandhi	18:6a4db94011d3	4908
sahilmgandhi	18:6a4db94011d3	4909	/**
sahilmgandhi	18:6a4db94011d3	4910	* @brief Time Output Compare 4 configuration
sahilmgandhi	18:6a4db94011d3	4911	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	4912	* @param OC_Config: The output configuration structure
sahilmgandhi	18:6a4db94011d3	4913	* @retval None
sahilmgandhi	18:6a4db94011d3	4914	*/
sahilmgandhi	18:6a4db94011d3	4915	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
sahilmgandhi	18:6a4db94011d3	4916	{
sahilmgandhi	18:6a4db94011d3	4917	uint32_t tmpccmrx = 0U;
sahilmgandhi	18:6a4db94011d3	4918	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	4919	uint32_t tmpcr2 = 0U;
sahilmgandhi	18:6a4db94011d3	4920
sahilmgandhi	18:6a4db94011d3	4921	/* Disable the Channel 4: Reset the CC4E Bit */
sahilmgandhi	18:6a4db94011d3	4922	TIMx->CCER &= ~TIM_CCER_CC4E;
sahilmgandhi	18:6a4db94011d3	4923
sahilmgandhi	18:6a4db94011d3	4924	/* Get the TIMx CCER register value */
sahilmgandhi	18:6a4db94011d3	4925	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	4926	/* Get the TIMx CR2 register value */
sahilmgandhi	18:6a4db94011d3	4927	tmpcr2 = TIMx->CR2;
sahilmgandhi	18:6a4db94011d3	4928
sahilmgandhi	18:6a4db94011d3	4929	/* Get the TIMx CCMR2 register value */
sahilmgandhi	18:6a4db94011d3	4930	tmpccmrx = TIMx->CCMR2;
sahilmgandhi	18:6a4db94011d3	4931
sahilmgandhi	18:6a4db94011d3	4932	/* Reset the Output Compare mode and Capture/Compare selection Bits */
sahilmgandhi	18:6a4db94011d3	4933	tmpccmrx &= ~TIM_CCMR2_OC4M;
sahilmgandhi	18:6a4db94011d3	4934	tmpccmrx &= ~TIM_CCMR2_CC4S;
sahilmgandhi	18:6a4db94011d3	4935
sahilmgandhi	18:6a4db94011d3	4936	/* Select the Output Compare Mode */
sahilmgandhi	18:6a4db94011d3	4937	tmpccmrx \|= (OC_Config->OCMode << 8U);
sahilmgandhi	18:6a4db94011d3	4938
sahilmgandhi	18:6a4db94011d3	4939	/* Reset the Output Polarity level */
sahilmgandhi	18:6a4db94011d3	4940	tmpccer &= ~TIM_CCER_CC4P;
sahilmgandhi	18:6a4db94011d3	4941	/* Set the Output Compare Polarity */
sahilmgandhi	18:6a4db94011d3	4942	tmpccer \|= (OC_Config->OCPolarity << 12U);
sahilmgandhi	18:6a4db94011d3	4943
sahilmgandhi	18:6a4db94011d3	4944	/if((TIMx == TIM1) \|\| (TIMx == TIM8))/
sahilmgandhi	18:6a4db94011d3	4945	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
sahilmgandhi	18:6a4db94011d3	4946	{
sahilmgandhi	18:6a4db94011d3	4947	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
sahilmgandhi	18:6a4db94011d3	4948	/* Reset the Output Compare IDLE State */
sahilmgandhi	18:6a4db94011d3	4949	tmpcr2 &= ~TIM_CR2_OIS4;
sahilmgandhi	18:6a4db94011d3	4950	/* Set the Output Idle state */
sahilmgandhi	18:6a4db94011d3	4951	tmpcr2 \|= (OC_Config->OCIdleState << 6U);
sahilmgandhi	18:6a4db94011d3	4952	}
sahilmgandhi	18:6a4db94011d3	4953	/* Write to TIMx CR2 */
sahilmgandhi	18:6a4db94011d3	4954	TIMx->CR2 = tmpcr2;
sahilmgandhi	18:6a4db94011d3	4955
sahilmgandhi	18:6a4db94011d3	4956	/* Write to TIMx CCMR2 */
sahilmgandhi	18:6a4db94011d3	4957	TIMx->CCMR2 = tmpccmrx;
sahilmgandhi	18:6a4db94011d3	4958
sahilmgandhi	18:6a4db94011d3	4959	/* Set the Capture Compare Register value */
sahilmgandhi	18:6a4db94011d3	4960	TIMx->CCR4 = OC_Config->Pulse;
sahilmgandhi	18:6a4db94011d3	4961
sahilmgandhi	18:6a4db94011d3	4962	/* Write to TIMx CCER */
sahilmgandhi	18:6a4db94011d3	4963	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	4964	}
sahilmgandhi	18:6a4db94011d3	4965
sahilmgandhi	18:6a4db94011d3	4966	/**
sahilmgandhi	18:6a4db94011d3	4967	* @brief Time Output Compare 4 configuration
sahilmgandhi	18:6a4db94011d3	4968	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	4969	* the configuration information for TIM module.
sahilmgandhi	18:6a4db94011d3	4970	* @param sSlaveConfig: The slave configuration structure
sahilmgandhi	18:6a4db94011d3	4971	* @retval None
sahilmgandhi	18:6a4db94011d3	4972	*/
sahilmgandhi	18:6a4db94011d3	4973	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
sahilmgandhi	18:6a4db94011d3	4974	TIM_SlaveConfigTypeDef * sSlaveConfig)
sahilmgandhi	18:6a4db94011d3	4975	{
sahilmgandhi	18:6a4db94011d3	4976	uint32_t tmpsmcr = 0U;
sahilmgandhi	18:6a4db94011d3	4977	uint32_t tmpccmr1 = 0U;
sahilmgandhi	18:6a4db94011d3	4978	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	4979
sahilmgandhi	18:6a4db94011d3	4980	/* Get the TIMx SMCR register value */
sahilmgandhi	18:6a4db94011d3	4981	tmpsmcr = htim->Instance->SMCR;
sahilmgandhi	18:6a4db94011d3	4982
sahilmgandhi	18:6a4db94011d3	4983	/* Reset the Trigger Selection Bits */
sahilmgandhi	18:6a4db94011d3	4984	tmpsmcr &= ~TIM_SMCR_TS;
sahilmgandhi	18:6a4db94011d3	4985	/* Set the Input Trigger source */
sahilmgandhi	18:6a4db94011d3	4986	tmpsmcr \|= sSlaveConfig->InputTrigger;
sahilmgandhi	18:6a4db94011d3	4987
sahilmgandhi	18:6a4db94011d3	4988	/* Reset the slave mode Bits */
sahilmgandhi	18:6a4db94011d3	4989	tmpsmcr &= ~TIM_SMCR_SMS;
sahilmgandhi	18:6a4db94011d3	4990	/* Set the slave mode */
sahilmgandhi	18:6a4db94011d3	4991	tmpsmcr \|= sSlaveConfig->SlaveMode;
sahilmgandhi	18:6a4db94011d3	4992
sahilmgandhi	18:6a4db94011d3	4993	/* Write to TIMx SMCR */
sahilmgandhi	18:6a4db94011d3	4994	htim->Instance->SMCR = tmpsmcr;
sahilmgandhi	18:6a4db94011d3	4995
sahilmgandhi	18:6a4db94011d3	4996	/* Configure the trigger prescaler, filter, and polarity */
sahilmgandhi	18:6a4db94011d3	4997	switch (sSlaveConfig->InputTrigger)
sahilmgandhi	18:6a4db94011d3	4998	{
sahilmgandhi	18:6a4db94011d3	4999	case TIM_TS_ETRF:
sahilmgandhi	18:6a4db94011d3	5000	{
sahilmgandhi	18:6a4db94011d3	5001	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	5002	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	5003	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
sahilmgandhi	18:6a4db94011d3	5004	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
sahilmgandhi	18:6a4db94011d3	5005	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
sahilmgandhi	18:6a4db94011d3	5006	/* Configure the ETR Trigger source */
sahilmgandhi	18:6a4db94011d3	5007	TIM_ETR_SetConfig(htim->Instance,
sahilmgandhi	18:6a4db94011d3	5008	sSlaveConfig->TriggerPrescaler,
sahilmgandhi	18:6a4db94011d3	5009	sSlaveConfig->TriggerPolarity,
sahilmgandhi	18:6a4db94011d3	5010	sSlaveConfig->TriggerFilter);
sahilmgandhi	18:6a4db94011d3	5011	}
sahilmgandhi	18:6a4db94011d3	5012	break;
sahilmgandhi	18:6a4db94011d3	5013
sahilmgandhi	18:6a4db94011d3	5014	case TIM_TS_TI1F_ED:
sahilmgandhi	18:6a4db94011d3	5015	{
sahilmgandhi	18:6a4db94011d3	5016	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	5017	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	5018	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
sahilmgandhi	18:6a4db94011d3	5019
sahilmgandhi	18:6a4db94011d3	5020	/* Disable the Channel 1: Reset the CC1E Bit */
sahilmgandhi	18:6a4db94011d3	5021	tmpccer = htim->Instance->CCER;
sahilmgandhi	18:6a4db94011d3	5022	htim->Instance->CCER &= ~TIM_CCER_CC1E;
sahilmgandhi	18:6a4db94011d3	5023	tmpccmr1 = htim->Instance->CCMR1;
sahilmgandhi	18:6a4db94011d3	5024
sahilmgandhi	18:6a4db94011d3	5025	/* Set the filter */
sahilmgandhi	18:6a4db94011d3	5026	tmpccmr1 &= ~TIM_CCMR1_IC1F;
sahilmgandhi	18:6a4db94011d3	5027	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
sahilmgandhi	18:6a4db94011d3	5028
sahilmgandhi	18:6a4db94011d3	5029	/* Write to TIMx CCMR1 and CCER registers */
sahilmgandhi	18:6a4db94011d3	5030	htim->Instance->CCMR1 = tmpccmr1;
sahilmgandhi	18:6a4db94011d3	5031	htim->Instance->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	5032
sahilmgandhi	18:6a4db94011d3	5033	}
sahilmgandhi	18:6a4db94011d3	5034	break;
sahilmgandhi	18:6a4db94011d3	5035
sahilmgandhi	18:6a4db94011d3	5036	case TIM_TS_TI1FP1:
sahilmgandhi	18:6a4db94011d3	5037	{
sahilmgandhi	18:6a4db94011d3	5038	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	5039	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	5040	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
sahilmgandhi	18:6a4db94011d3	5041	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
sahilmgandhi	18:6a4db94011d3	5042
sahilmgandhi	18:6a4db94011d3	5043	/* Configure TI1 Filter and Polarity */
sahilmgandhi	18:6a4db94011d3	5044	TIM_TI1_ConfigInputStage(htim->Instance,
sahilmgandhi	18:6a4db94011d3	5045	sSlaveConfig->TriggerPolarity,
sahilmgandhi	18:6a4db94011d3	5046	sSlaveConfig->TriggerFilter);
sahilmgandhi	18:6a4db94011d3	5047	}
sahilmgandhi	18:6a4db94011d3	5048	break;
sahilmgandhi	18:6a4db94011d3	5049
sahilmgandhi	18:6a4db94011d3	5050	case TIM_TS_TI2FP2:
sahilmgandhi	18:6a4db94011d3	5051	{
sahilmgandhi	18:6a4db94011d3	5052	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	5053	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	5054	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
sahilmgandhi	18:6a4db94011d3	5055	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
sahilmgandhi	18:6a4db94011d3	5056
sahilmgandhi	18:6a4db94011d3	5057	/* Configure TI2 Filter and Polarity */
sahilmgandhi	18:6a4db94011d3	5058	TIM_TI2_ConfigInputStage(htim->Instance,
sahilmgandhi	18:6a4db94011d3	5059	sSlaveConfig->TriggerPolarity,
sahilmgandhi	18:6a4db94011d3	5060	sSlaveConfig->TriggerFilter);
sahilmgandhi	18:6a4db94011d3	5061	}
sahilmgandhi	18:6a4db94011d3	5062	break;
sahilmgandhi	18:6a4db94011d3	5063
sahilmgandhi	18:6a4db94011d3	5064	case TIM_TS_ITR0:
sahilmgandhi	18:6a4db94011d3	5065	{
sahilmgandhi	18:6a4db94011d3	5066	/* Check the parameter */
sahilmgandhi	18:6a4db94011d3	5067	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	5068	}
sahilmgandhi	18:6a4db94011d3	5069	break;
sahilmgandhi	18:6a4db94011d3	5070
sahilmgandhi	18:6a4db94011d3	5071	case TIM_TS_ITR1:
sahilmgandhi	18:6a4db94011d3	5072	{
sahilmgandhi	18:6a4db94011d3	5073	/* Check the parameter */
sahilmgandhi	18:6a4db94011d3	5074	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	5075	}
sahilmgandhi	18:6a4db94011d3	5076	break;
sahilmgandhi	18:6a4db94011d3	5077
sahilmgandhi	18:6a4db94011d3	5078	case TIM_TS_ITR2:
sahilmgandhi	18:6a4db94011d3	5079	{
sahilmgandhi	18:6a4db94011d3	5080	/* Check the parameter */
sahilmgandhi	18:6a4db94011d3	5081	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	5082	}
sahilmgandhi	18:6a4db94011d3	5083	break;
sahilmgandhi	18:6a4db94011d3	5084
sahilmgandhi	18:6a4db94011d3	5085	case TIM_TS_ITR3:
sahilmgandhi	18:6a4db94011d3	5086	{
sahilmgandhi	18:6a4db94011d3	5087	/* Check the parameter */
sahilmgandhi	18:6a4db94011d3	5088	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
sahilmgandhi	18:6a4db94011d3	5089	}
sahilmgandhi	18:6a4db94011d3	5090	break;
sahilmgandhi	18:6a4db94011d3	5091
sahilmgandhi	18:6a4db94011d3	5092	default:
sahilmgandhi	18:6a4db94011d3	5093	break;
sahilmgandhi	18:6a4db94011d3	5094	}
sahilmgandhi	18:6a4db94011d3	5095	}
sahilmgandhi	18:6a4db94011d3	5096
sahilmgandhi	18:6a4db94011d3	5097
sahilmgandhi	18:6a4db94011d3	5098	/**
sahilmgandhi	18:6a4db94011d3	5099	* @brief Configure the Polarity and Filter for TI1.
sahilmgandhi	18:6a4db94011d3	5100	* @param TIMx to select the TIM peripheral.
sahilmgandhi	18:6a4db94011d3	5101	* @param TIM_ICPolarity : The Input Polarity.
sahilmgandhi	18:6a4db94011d3	5102	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5103	* @arg TIM_ICPolarity_Rising
sahilmgandhi	18:6a4db94011d3	5104	* @arg TIM_ICPolarity_Falling
sahilmgandhi	18:6a4db94011d3	5105	* @arg TIM_ICPolarity_BothEdge
sahilmgandhi	18:6a4db94011d3	5106	* @param TIM_ICFilter: Specifies the Input Capture Filter.
sahilmgandhi	18:6a4db94011d3	5107	* This parameter must be a value between 0x00 and 0x0F.
sahilmgandhi	18:6a4db94011d3	5108	* @retval None
sahilmgandhi	18:6a4db94011d3	5109	*/
sahilmgandhi	18:6a4db94011d3	5110	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
sahilmgandhi	18:6a4db94011d3	5111	{
sahilmgandhi	18:6a4db94011d3	5112	uint32_t tmpccmr1 = 0U;
sahilmgandhi	18:6a4db94011d3	5113	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	5114
sahilmgandhi	18:6a4db94011d3	5115	/* Disable the Channel 1: Reset the CC1E Bit */
sahilmgandhi	18:6a4db94011d3	5116	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	5117	TIMx->CCER &= ~TIM_CCER_CC1E;
sahilmgandhi	18:6a4db94011d3	5118	tmpccmr1 = TIMx->CCMR1;
sahilmgandhi	18:6a4db94011d3	5119
sahilmgandhi	18:6a4db94011d3	5120	/* Set the filter */
sahilmgandhi	18:6a4db94011d3	5121	tmpccmr1 &= ~TIM_CCMR1_IC1F;
sahilmgandhi	18:6a4db94011d3	5122	tmpccmr1 \|= (TIM_ICFilter << 4U);
sahilmgandhi	18:6a4db94011d3	5123
sahilmgandhi	18:6a4db94011d3	5124	/* Select the Polarity and set the CC1E Bit */
sahilmgandhi	18:6a4db94011d3	5125	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
sahilmgandhi	18:6a4db94011d3	5126	tmpccer \|= TIM_ICPolarity;
sahilmgandhi	18:6a4db94011d3	5127
sahilmgandhi	18:6a4db94011d3	5128	/* Write to TIMx CCMR1 and CCER registers */
sahilmgandhi	18:6a4db94011d3	5129	TIMx->CCMR1 = tmpccmr1;
sahilmgandhi	18:6a4db94011d3	5130	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	5131	}
sahilmgandhi	18:6a4db94011d3	5132
sahilmgandhi	18:6a4db94011d3	5133	/**
sahilmgandhi	18:6a4db94011d3	5134	* @brief Configure the TI2 as Input.
sahilmgandhi	18:6a4db94011d3	5135	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	5136	* @param TIM_ICPolarity : The Input Polarity.
sahilmgandhi	18:6a4db94011d3	5137	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5138	* @arg TIM_ICPolarity_Rising
sahilmgandhi	18:6a4db94011d3	5139	* @arg TIM_ICPolarity_Falling
sahilmgandhi	18:6a4db94011d3	5140	* @arg TIM_ICPolarity_BothEdge
sahilmgandhi	18:6a4db94011d3	5141	* @param TIM_ICSelection: specifies the input to be used.
sahilmgandhi	18:6a4db94011d3	5142	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5143	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
sahilmgandhi	18:6a4db94011d3	5144	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
sahilmgandhi	18:6a4db94011d3	5145	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
sahilmgandhi	18:6a4db94011d3	5146	* @param TIM_ICFilter: Specifies the Input Capture Filter.
sahilmgandhi	18:6a4db94011d3	5147	* This parameter must be a value between 0x00 and 0x0F.
sahilmgandhi	18:6a4db94011d3	5148	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
sahilmgandhi	18:6a4db94011d3	5149	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
sahilmgandhi	18:6a4db94011d3	5150	* protected against un-initialized filter and polarity values.
sahilmgandhi	18:6a4db94011d3	5151	* @retval None
sahilmgandhi	18:6a4db94011d3	5152	*/
sahilmgandhi	18:6a4db94011d3	5153	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
sahilmgandhi	18:6a4db94011d3	5154	uint32_t TIM_ICFilter)
sahilmgandhi	18:6a4db94011d3	5155	{
sahilmgandhi	18:6a4db94011d3	5156	uint32_t tmpccmr1 = 0U;
sahilmgandhi	18:6a4db94011d3	5157	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	5158
sahilmgandhi	18:6a4db94011d3	5159	/* Disable the Channel 2: Reset the CC2E Bit */
sahilmgandhi	18:6a4db94011d3	5160	TIMx->CCER &= ~TIM_CCER_CC2E;
sahilmgandhi	18:6a4db94011d3	5161	tmpccmr1 = TIMx->CCMR1;
sahilmgandhi	18:6a4db94011d3	5162	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	5163
sahilmgandhi	18:6a4db94011d3	5164	/* Select the Input */
sahilmgandhi	18:6a4db94011d3	5165	tmpccmr1 &= ~TIM_CCMR1_CC2S;
sahilmgandhi	18:6a4db94011d3	5166	tmpccmr1 \|= (TIM_ICSelection << 8U);
sahilmgandhi	18:6a4db94011d3	5167
sahilmgandhi	18:6a4db94011d3	5168	/* Set the filter */
sahilmgandhi	18:6a4db94011d3	5169	tmpccmr1 &= ~TIM_CCMR1_IC2F;
sahilmgandhi	18:6a4db94011d3	5170	tmpccmr1 \|= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
sahilmgandhi	18:6a4db94011d3	5171
sahilmgandhi	18:6a4db94011d3	5172	/* Select the Polarity and set the CC2E Bit */
sahilmgandhi	18:6a4db94011d3	5173	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
sahilmgandhi	18:6a4db94011d3	5174	tmpccer \|= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
sahilmgandhi	18:6a4db94011d3	5175
sahilmgandhi	18:6a4db94011d3	5176	/* Write to TIMx CCMR1 and CCER registers */
sahilmgandhi	18:6a4db94011d3	5177	TIMx->CCMR1 = tmpccmr1 ;
sahilmgandhi	18:6a4db94011d3	5178	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	5179	}
sahilmgandhi	18:6a4db94011d3	5180
sahilmgandhi	18:6a4db94011d3	5181	/**
sahilmgandhi	18:6a4db94011d3	5182	* @brief Configure the Polarity and Filter for TI2.
sahilmgandhi	18:6a4db94011d3	5183	* @param TIMx to select the TIM peripheral.
sahilmgandhi	18:6a4db94011d3	5184	* @param TIM_ICPolarity : The Input Polarity.
sahilmgandhi	18:6a4db94011d3	5185	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5186	* @arg TIM_ICPolarity_Rising
sahilmgandhi	18:6a4db94011d3	5187	* @arg TIM_ICPolarity_Falling
sahilmgandhi	18:6a4db94011d3	5188	* @arg TIM_ICPolarity_BothEdge
sahilmgandhi	18:6a4db94011d3	5189	* @param TIM_ICFilter: Specifies the Input Capture Filter.
sahilmgandhi	18:6a4db94011d3	5190	* This parameter must be a value between 0x00 and 0x0F.
sahilmgandhi	18:6a4db94011d3	5191	* @retval None
sahilmgandhi	18:6a4db94011d3	5192	*/
sahilmgandhi	18:6a4db94011d3	5193	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
sahilmgandhi	18:6a4db94011d3	5194	{
sahilmgandhi	18:6a4db94011d3	5195	uint32_t tmpccmr1 = 0U;
sahilmgandhi	18:6a4db94011d3	5196	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	5197
sahilmgandhi	18:6a4db94011d3	5198	/* Disable the Channel 2: Reset the CC2E Bit */
sahilmgandhi	18:6a4db94011d3	5199	TIMx->CCER &= ~TIM_CCER_CC2E;
sahilmgandhi	18:6a4db94011d3	5200	tmpccmr1 = TIMx->CCMR1;
sahilmgandhi	18:6a4db94011d3	5201	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	5202
sahilmgandhi	18:6a4db94011d3	5203	/* Set the filter */
sahilmgandhi	18:6a4db94011d3	5204	tmpccmr1 &= ~TIM_CCMR1_IC2F;
sahilmgandhi	18:6a4db94011d3	5205	tmpccmr1 \|= (TIM_ICFilter << 12U);
sahilmgandhi	18:6a4db94011d3	5206
sahilmgandhi	18:6a4db94011d3	5207	/* Select the Polarity and set the CC2E Bit */
sahilmgandhi	18:6a4db94011d3	5208	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
sahilmgandhi	18:6a4db94011d3	5209	tmpccer \|= (TIM_ICPolarity << 4U);
sahilmgandhi	18:6a4db94011d3	5210
sahilmgandhi	18:6a4db94011d3	5211	/* Write to TIMx CCMR1 and CCER registers */
sahilmgandhi	18:6a4db94011d3	5212	TIMx->CCMR1 = tmpccmr1 ;
sahilmgandhi	18:6a4db94011d3	5213	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	5214	}
sahilmgandhi	18:6a4db94011d3	5215
sahilmgandhi	18:6a4db94011d3	5216	/**
sahilmgandhi	18:6a4db94011d3	5217	* @brief Configure the TI3 as Input.
sahilmgandhi	18:6a4db94011d3	5218	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	5219	* @param TIM_ICPolarity : The Input Polarity.
sahilmgandhi	18:6a4db94011d3	5220	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5221	* @arg TIM_ICPolarity_Rising
sahilmgandhi	18:6a4db94011d3	5222	* @arg TIM_ICPolarity_Falling
sahilmgandhi	18:6a4db94011d3	5223	* @arg TIM_ICPolarity_BothEdge
sahilmgandhi	18:6a4db94011d3	5224	* @param TIM_ICSelection: specifies the input to be used.
sahilmgandhi	18:6a4db94011d3	5225	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5226	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
sahilmgandhi	18:6a4db94011d3	5227	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
sahilmgandhi	18:6a4db94011d3	5228	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
sahilmgandhi	18:6a4db94011d3	5229	* @param TIM_ICFilter: Specifies the Input Capture Filter.
sahilmgandhi	18:6a4db94011d3	5230	* This parameter must be a value between 0x00 and 0x0F.
sahilmgandhi	18:6a4db94011d3	5231	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
sahilmgandhi	18:6a4db94011d3	5232	* (on channel4 path) is used as the input signal. Therefore CCMR2 must be
sahilmgandhi	18:6a4db94011d3	5233	* protected against un-initialized filter and polarity values.
sahilmgandhi	18:6a4db94011d3	5234	* @retval None
sahilmgandhi	18:6a4db94011d3	5235	*/
sahilmgandhi	18:6a4db94011d3	5236	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
sahilmgandhi	18:6a4db94011d3	5237	uint32_t TIM_ICFilter)
sahilmgandhi	18:6a4db94011d3	5238	{
sahilmgandhi	18:6a4db94011d3	5239	uint32_t tmpccmr2 = 0U;
sahilmgandhi	18:6a4db94011d3	5240	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	5241
sahilmgandhi	18:6a4db94011d3	5242	/* Disable the Channel 3: Reset the CC3E Bit */
sahilmgandhi	18:6a4db94011d3	5243	TIMx->CCER &= ~TIM_CCER_CC3E;
sahilmgandhi	18:6a4db94011d3	5244	tmpccmr2 = TIMx->CCMR2;
sahilmgandhi	18:6a4db94011d3	5245	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	5246
sahilmgandhi	18:6a4db94011d3	5247	/* Select the Input */
sahilmgandhi	18:6a4db94011d3	5248	tmpccmr2 &= ~TIM_CCMR2_CC3S;
sahilmgandhi	18:6a4db94011d3	5249	tmpccmr2 \|= TIM_ICSelection;
sahilmgandhi	18:6a4db94011d3	5250
sahilmgandhi	18:6a4db94011d3	5251	/* Set the filter */
sahilmgandhi	18:6a4db94011d3	5252	tmpccmr2 &= ~TIM_CCMR2_IC3F;
sahilmgandhi	18:6a4db94011d3	5253	tmpccmr2 \|= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
sahilmgandhi	18:6a4db94011d3	5254
sahilmgandhi	18:6a4db94011d3	5255	/* Select the Polarity and set the CC3E Bit */
sahilmgandhi	18:6a4db94011d3	5256	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
sahilmgandhi	18:6a4db94011d3	5257	tmpccer \|= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
sahilmgandhi	18:6a4db94011d3	5258
sahilmgandhi	18:6a4db94011d3	5259	/* Write to TIMx CCMR2 and CCER registers */
sahilmgandhi	18:6a4db94011d3	5260	TIMx->CCMR2 = tmpccmr2;
sahilmgandhi	18:6a4db94011d3	5261	TIMx->CCER = tmpccer;
sahilmgandhi	18:6a4db94011d3	5262	}
sahilmgandhi	18:6a4db94011d3	5263
sahilmgandhi	18:6a4db94011d3	5264	/**
sahilmgandhi	18:6a4db94011d3	5265	* @brief Configure the TI4 as Input.
sahilmgandhi	18:6a4db94011d3	5266	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	5267	* @param TIM_ICPolarity : The Input Polarity.
sahilmgandhi	18:6a4db94011d3	5268	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5269	* @arg TIM_ICPolarity_Rising
sahilmgandhi	18:6a4db94011d3	5270	* @arg TIM_ICPolarity_Falling
sahilmgandhi	18:6a4db94011d3	5271	* @arg TIM_ICPolarity_BothEdge
sahilmgandhi	18:6a4db94011d3	5272	* @param TIM_ICSelection: specifies the input to be used.
sahilmgandhi	18:6a4db94011d3	5273	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5274	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
sahilmgandhi	18:6a4db94011d3	5275	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
sahilmgandhi	18:6a4db94011d3	5276	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
sahilmgandhi	18:6a4db94011d3	5277	* @param TIM_ICFilter: Specifies the Input Capture Filter.
sahilmgandhi	18:6a4db94011d3	5278	* This parameter must be a value between 0x00 and 0x0F.
sahilmgandhi	18:6a4db94011d3	5279	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
sahilmgandhi	18:6a4db94011d3	5280	* (on channel3 path) is used as the input signal. Therefore CCMR2 must be
sahilmgandhi	18:6a4db94011d3	5281	* protected against un-initialized filter and polarity values.
sahilmgandhi	18:6a4db94011d3	5282	* @retval None
sahilmgandhi	18:6a4db94011d3	5283	*/
sahilmgandhi	18:6a4db94011d3	5284	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
sahilmgandhi	18:6a4db94011d3	5285	uint32_t TIM_ICFilter)
sahilmgandhi	18:6a4db94011d3	5286	{
sahilmgandhi	18:6a4db94011d3	5287	uint32_t tmpccmr2 = 0U;
sahilmgandhi	18:6a4db94011d3	5288	uint32_t tmpccer = 0U;
sahilmgandhi	18:6a4db94011d3	5289
sahilmgandhi	18:6a4db94011d3	5290	/* Disable the Channel 4: Reset the CC4E Bit */
sahilmgandhi	18:6a4db94011d3	5291	TIMx->CCER &= ~TIM_CCER_CC4E;
sahilmgandhi	18:6a4db94011d3	5292	tmpccmr2 = TIMx->CCMR2;
sahilmgandhi	18:6a4db94011d3	5293	tmpccer = TIMx->CCER;
sahilmgandhi	18:6a4db94011d3	5294
sahilmgandhi	18:6a4db94011d3	5295	/* Select the Input */
sahilmgandhi	18:6a4db94011d3	5296	tmpccmr2 &= ~TIM_CCMR2_CC4S;
sahilmgandhi	18:6a4db94011d3	5297	tmpccmr2 \|= (TIM_ICSelection << 8U);
sahilmgandhi	18:6a4db94011d3	5298
sahilmgandhi	18:6a4db94011d3	5299	/* Set the filter */
sahilmgandhi	18:6a4db94011d3	5300	tmpccmr2 &= ~TIM_CCMR2_IC4F;
sahilmgandhi	18:6a4db94011d3	5301	tmpccmr2 \|= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
sahilmgandhi	18:6a4db94011d3	5302
sahilmgandhi	18:6a4db94011d3	5303	/* Select the Polarity and set the CC4E Bit */
sahilmgandhi	18:6a4db94011d3	5304	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
sahilmgandhi	18:6a4db94011d3	5305	tmpccer \|= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
sahilmgandhi	18:6a4db94011d3	5306
sahilmgandhi	18:6a4db94011d3	5307	/* Write to TIMx CCMR2 and CCER registers */
sahilmgandhi	18:6a4db94011d3	5308	TIMx->CCMR2 = tmpccmr2;
sahilmgandhi	18:6a4db94011d3	5309	TIMx->CCER = tmpccer ;
sahilmgandhi	18:6a4db94011d3	5310	}
sahilmgandhi	18:6a4db94011d3	5311
sahilmgandhi	18:6a4db94011d3	5312	/**
sahilmgandhi	18:6a4db94011d3	5313	* @brief Selects the Input Trigger source
sahilmgandhi	18:6a4db94011d3	5314	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	5315	* @param TIM_ITRx: The Input Trigger source.
sahilmgandhi	18:6a4db94011d3	5316	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5317	* @arg TIM_TS_ITR0: Internal Trigger 0
sahilmgandhi	18:6a4db94011d3	5318	* @arg TIM_TS_ITR1: Internal Trigger 1
sahilmgandhi	18:6a4db94011d3	5319	* @arg TIM_TS_ITR2: Internal Trigger 2
sahilmgandhi	18:6a4db94011d3	5320	* @arg TIM_TS_ITR3: Internal Trigger 3
sahilmgandhi	18:6a4db94011d3	5321	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
sahilmgandhi	18:6a4db94011d3	5322	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
sahilmgandhi	18:6a4db94011d3	5323	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
sahilmgandhi	18:6a4db94011d3	5324	* @arg TIM_TS_ETRF: External Trigger input
sahilmgandhi	18:6a4db94011d3	5325	* @retval None
sahilmgandhi	18:6a4db94011d3	5326	*/
sahilmgandhi	18:6a4db94011d3	5327	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
sahilmgandhi	18:6a4db94011d3	5328	{
sahilmgandhi	18:6a4db94011d3	5329	uint32_t tmpsmcr = 0U;
sahilmgandhi	18:6a4db94011d3	5330
sahilmgandhi	18:6a4db94011d3	5331	/* Get the TIMx SMCR register value */
sahilmgandhi	18:6a4db94011d3	5332	tmpsmcr = TIMx->SMCR;
sahilmgandhi	18:6a4db94011d3	5333	/* Reset the TS Bits */
sahilmgandhi	18:6a4db94011d3	5334	tmpsmcr &= ~TIM_SMCR_TS;
sahilmgandhi	18:6a4db94011d3	5335	/* Set the Input Trigger source and the slave mode*/
sahilmgandhi	18:6a4db94011d3	5336	tmpsmcr \|= TIM_ITRx \| TIM_SLAVEMODE_EXTERNAL1;
sahilmgandhi	18:6a4db94011d3	5337	/* Write to TIMx SMCR */
sahilmgandhi	18:6a4db94011d3	5338	TIMx->SMCR = tmpsmcr;
sahilmgandhi	18:6a4db94011d3	5339	}
sahilmgandhi	18:6a4db94011d3	5340
sahilmgandhi	18:6a4db94011d3	5341	/**
sahilmgandhi	18:6a4db94011d3	5342	* @brief Configures the TIMx External Trigger (ETR).
sahilmgandhi	18:6a4db94011d3	5343	* @param TIMx to select the TIM peripheral
sahilmgandhi	18:6a4db94011d3	5344	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
sahilmgandhi	18:6a4db94011d3	5345	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5346	* @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
sahilmgandhi	18:6a4db94011d3	5347	* @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
sahilmgandhi	18:6a4db94011d3	5348	* @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
sahilmgandhi	18:6a4db94011d3	5349	* @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
sahilmgandhi	18:6a4db94011d3	5350	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
sahilmgandhi	18:6a4db94011d3	5351	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5352	* @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
sahilmgandhi	18:6a4db94011d3	5353	* @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
sahilmgandhi	18:6a4db94011d3	5354	* @param ExtTRGFilter: External Trigger Filter.
sahilmgandhi	18:6a4db94011d3	5355	* This parameter must be a value between 0x00 and 0x0F
sahilmgandhi	18:6a4db94011d3	5356	* @retval None
sahilmgandhi	18:6a4db94011d3	5357	*/
sahilmgandhi	18:6a4db94011d3	5358	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
sahilmgandhi	18:6a4db94011d3	5359	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
sahilmgandhi	18:6a4db94011d3	5360	{
sahilmgandhi	18:6a4db94011d3	5361	uint32_t tmpsmcr = 0U;
sahilmgandhi	18:6a4db94011d3	5362
sahilmgandhi	18:6a4db94011d3	5363	tmpsmcr = TIMx->SMCR;
sahilmgandhi	18:6a4db94011d3	5364
sahilmgandhi	18:6a4db94011d3	5365	/* Reset the ETR Bits */
sahilmgandhi	18:6a4db94011d3	5366	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
sahilmgandhi	18:6a4db94011d3	5367
sahilmgandhi	18:6a4db94011d3	5368	/* Set the Prescaler, the Filter value and the Polarity */
sahilmgandhi	18:6a4db94011d3	5369	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8U)));
sahilmgandhi	18:6a4db94011d3	5370
sahilmgandhi	18:6a4db94011d3	5371	/* Write to TIMx SMCR */
sahilmgandhi	18:6a4db94011d3	5372	TIMx->SMCR = tmpsmcr;
sahilmgandhi	18:6a4db94011d3	5373	}
sahilmgandhi	18:6a4db94011d3	5374
sahilmgandhi	18:6a4db94011d3	5375	/**
sahilmgandhi	18:6a4db94011d3	5376	* @}
sahilmgandhi	18:6a4db94011d3	5377	*/
sahilmgandhi	18:6a4db94011d3	5378
sahilmgandhi	18:6a4db94011d3	5379	#endif /* HAL_TIM_MODULE_ENABLED */
sahilmgandhi	18:6a4db94011d3	5380	/**
sahilmgandhi	18:6a4db94011d3	5381	* @}
sahilmgandhi	18:6a4db94011d3	5382	*/
sahilmgandhi	18:6a4db94011d3	5383
sahilmgandhi	18:6a4db94011d3	5384	/**
sahilmgandhi	18:6a4db94011d3	5385	* @}
sahilmgandhi	18:6a4db94011d3	5386	*/
sahilmgandhi	18:6a4db94011d3	5387	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
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The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim.c@18:6a4db94011d3, 2017-05-14 (annotated)

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