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mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_spi.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:: sahilmgandhi
Date:: Sun May 14 23:18:57 2017 +0000
Revision:: 18:6a4db94011d3

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User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f2xx_hal_spi.c
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.1.3
sahilmgandhi	18:6a4db94011d3	6	* @date 29-June-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief SPI HAL module driver.
sahilmgandhi	18:6a4db94011d3	8	* This file provides firmware functions to manage the following
sahilmgandhi	18:6a4db94011d3	9	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
sahilmgandhi	18:6a4db94011d3	10	* + Initialization and de-initialization functions
sahilmgandhi	18:6a4db94011d3	11	* + IO operation functions
sahilmgandhi	18:6a4db94011d3	12	* + Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	13	* + Peripheral State functions
sahilmgandhi	18:6a4db94011d3	14	*
sahilmgandhi	18:6a4db94011d3	15	@verbatim
sahilmgandhi	18:6a4db94011d3	16	==============================================================================
sahilmgandhi	18:6a4db94011d3	17	##### How to use this driver #####
sahilmgandhi	18:6a4db94011d3	18	==============================================================================
sahilmgandhi	18:6a4db94011d3	19	[..]
sahilmgandhi	18:6a4db94011d3	20	The SPI HAL driver can be used as follows:
sahilmgandhi	18:6a4db94011d3	21
sahilmgandhi	18:6a4db94011d3	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
sahilmgandhi	18:6a4db94011d3	23	SPI_HandleTypeDef hspi;
sahilmgandhi	18:6a4db94011d3	24
sahilmgandhi	18:6a4db94011d3	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
sahilmgandhi	18:6a4db94011d3	26	(##) Enable the SPIx interface clock
sahilmgandhi	18:6a4db94011d3	27	(##) SPI pins configuration
sahilmgandhi	18:6a4db94011d3	28	(+++) Enable the clock for the SPI GPIOs
sahilmgandhi	18:6a4db94011d3	29	(+++) Configure these SPI pins as alternate function push-pull
sahilmgandhi	18:6a4db94011d3	30	(##) NVIC configuration if you need to use interrupt process
sahilmgandhi	18:6a4db94011d3	31	(+++) Configure the SPIx interrupt priority
sahilmgandhi	18:6a4db94011d3	32	(+++) Enable the NVIC SPI IRQ handle
sahilmgandhi	18:6a4db94011d3	33	(##) DMA Configuration if you need to use DMA process
sahilmgandhi	18:6a4db94011d3	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
sahilmgandhi	18:6a4db94011d3	35	(+++) Enable the DMAx clock
sahilmgandhi	18:6a4db94011d3	36	(+++) Configure the DMA handle parameters
sahilmgandhi	18:6a4db94011d3	37	(+++) Configure the DMA Tx or Rx stream
sahilmgandhi	18:6a4db94011d3	38	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
sahilmgandhi	18:6a4db94011d3	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx stream
sahilmgandhi	18:6a4db94011d3	40
sahilmgandhi	18:6a4db94011d3	41	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
sahilmgandhi	18:6a4db94011d3	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
sahilmgandhi	18:6a4db94011d3	43
sahilmgandhi	18:6a4db94011d3	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
sahilmgandhi	18:6a4db94011d3	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
sahilmgandhi	18:6a4db94011d3	46	by calling the customized HAL_SPI_MspInit() API.
sahilmgandhi	18:6a4db94011d3	47	[..]
sahilmgandhi	18:6a4db94011d3	48	Circular mode restriction:
sahilmgandhi	18:6a4db94011d3	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
sahilmgandhi	18:6a4db94011d3	50	(##) Master 2Lines RxOnly
sahilmgandhi	18:6a4db94011d3	51	(##) Master 1Line Rx
sahilmgandhi	18:6a4db94011d3	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
sahilmgandhi	18:6a4db94011d3	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
sahilmgandhi	18:6a4db94011d3	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
sahilmgandhi	18:6a4db94011d3	55	[..]
sahilmgandhi	18:6a4db94011d3	56	Master Receive mode restriction:
sahilmgandhi	18:6a4db94011d3	57	(#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
sahilmgandhi	18:6a4db94011d3	58	bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
sahilmgandhi	18:6a4db94011d3	59	does not initiate a new transfer the following procedure has to be respected:
sahilmgandhi	18:6a4db94011d3	60	(##) HAL_SPI_DeInit()
sahilmgandhi	18:6a4db94011d3	61	(##) HAL_SPI_Init()
sahilmgandhi	18:6a4db94011d3	62	[..]
sahilmgandhi	18:6a4db94011d3	63	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
sahilmgandhi	18:6a4db94011d3	64	the following table resume the max SPI frequency reached with data size 8bits/16bits,
sahilmgandhi	18:6a4db94011d3	65	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
sahilmgandhi	18:6a4db94011d3	66
sahilmgandhi	18:6a4db94011d3	67	DataSize = SPI_DATASIZE_8BIT:
sahilmgandhi	18:6a4db94011d3	68	+----------------------------------------------------------------------------------------------+
sahilmgandhi	18:6a4db94011d3	69	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
sahilmgandhi	18:6a4db94011d3	70	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
sahilmgandhi	18:6a4db94011d3	71	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
sahilmgandhi	18:6a4db94011d3	72	\|==============================================================================================\|
sahilmgandhi	18:6a4db94011d3	73	\| T \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
sahilmgandhi	18:6a4db94011d3	74	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	75	\| / \| Interrupt \| Fpclk/4 \| Fpclk/4 \| NA \| NA \| NA \| NA \|
sahilmgandhi	18:6a4db94011d3	76	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	77	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
sahilmgandhi	18:6a4db94011d3	78	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
sahilmgandhi	18:6a4db94011d3	79	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
sahilmgandhi	18:6a4db94011d3	80	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	81	\| R \| Interrupt \| Fpclk/8 \| Fpclk/8 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
sahilmgandhi	18:6a4db94011d3	82	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	83	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/128 \| Fpclk/2 \|
sahilmgandhi	18:6a4db94011d3	84	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
sahilmgandhi	18:6a4db94011d3	85	\| \| Polling \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
sahilmgandhi	18:6a4db94011d3	86	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	87	\| T \| Interrupt \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
sahilmgandhi	18:6a4db94011d3	88	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	89	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/128\|
sahilmgandhi	18:6a4db94011d3	90	+----------------------------------------------------------------------------------------------+
sahilmgandhi	18:6a4db94011d3	91
sahilmgandhi	18:6a4db94011d3	92	DataSize = SPI_DATASIZE_16BIT:
sahilmgandhi	18:6a4db94011d3	93	+----------------------------------------------------------------------------------------------+
sahilmgandhi	18:6a4db94011d3	94	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
sahilmgandhi	18:6a4db94011d3	95	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
sahilmgandhi	18:6a4db94011d3	96	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
sahilmgandhi	18:6a4db94011d3	97	\|==============================================================================================\|
sahilmgandhi	18:6a4db94011d3	98	\| T \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
sahilmgandhi	18:6a4db94011d3	99	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	100	\| / \| Interrupt \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
sahilmgandhi	18:6a4db94011d3	101	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	102	\| X \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| NA \| NA \|
sahilmgandhi	18:6a4db94011d3	103	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
sahilmgandhi	18:6a4db94011d3	104	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/32 \| Fpclk/2 \|
sahilmgandhi	18:6a4db94011d3	105	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	106	\| R \| Interrupt \| Fpclk/4 \| Fpclk/4 \| Fpclk/64 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \|
sahilmgandhi	18:6a4db94011d3	107	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	108	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/64 \| Fpclk/2 \| Fpclk/128 \| Fpclk/2 \|
sahilmgandhi	18:6a4db94011d3	109	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
sahilmgandhi	18:6a4db94011d3	110	\| \| Polling \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/32 \|
sahilmgandhi	18:6a4db94011d3	111	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	112	\| T \| Interrupt \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/64 \|
sahilmgandhi	18:6a4db94011d3	113	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
sahilmgandhi	18:6a4db94011d3	114	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| NA \| NA \| Fpclk/2 \| Fpclk/128\|
sahilmgandhi	18:6a4db94011d3	115	+----------------------------------------------------------------------------------------------+
sahilmgandhi	18:6a4db94011d3	116	@note The max SPI frequency depend on SPI data size (8bits, 16bits),
sahilmgandhi	18:6a4db94011d3	117	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
sahilmgandhi	18:6a4db94011d3	118	@note
sahilmgandhi	18:6a4db94011d3	119	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
sahilmgandhi	18:6a4db94011d3	120	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
sahilmgandhi	18:6a4db94011d3	121	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
sahilmgandhi	18:6a4db94011d3	122
sahilmgandhi	18:6a4db94011d3	123	@endverbatim
sahilmgandhi	18:6a4db94011d3	124	******************************************************************************
sahilmgandhi	18:6a4db94011d3	125	* @attention
sahilmgandhi	18:6a4db94011d3	126	*
sahilmgandhi	18:6a4db94011d3	127	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	128	*
sahilmgandhi	18:6a4db94011d3	129	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	130	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	131	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	132	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	133	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	134	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	135	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	136	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	137	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	138	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	139	*
sahilmgandhi	18:6a4db94011d3	140	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	141	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	142	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	143	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	144	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	145	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	146	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	147	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	148	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	149	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	150	*
sahilmgandhi	18:6a4db94011d3	151	******************************************************************************
sahilmgandhi	18:6a4db94011d3	152	*/
sahilmgandhi	18:6a4db94011d3	153
sahilmgandhi	18:6a4db94011d3	154	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	155	#include "stm32f2xx_hal.h"
sahilmgandhi	18:6a4db94011d3	156
sahilmgandhi	18:6a4db94011d3	157	/** @addtogroup STM32F2xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	158	* @{
sahilmgandhi	18:6a4db94011d3	159	*/
sahilmgandhi	18:6a4db94011d3	160	/** @defgroup SPI SPI
sahilmgandhi	18:6a4db94011d3	161	* @brief SPI HAL module driver
sahilmgandhi	18:6a4db94011d3	162	* @{
sahilmgandhi	18:6a4db94011d3	163	*/
sahilmgandhi	18:6a4db94011d3	164	#ifdef HAL_SPI_MODULE_ENABLED
sahilmgandhi	18:6a4db94011d3	165
sahilmgandhi	18:6a4db94011d3	166	/* Private typedef -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	167	/* Private defines -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	168	/** @defgroup SPI_Private_Constants SPI Private Constants
sahilmgandhi	18:6a4db94011d3	169	* @{
sahilmgandhi	18:6a4db94011d3	170	*/
sahilmgandhi	18:6a4db94011d3	171	#define SPI_DEFAULT_TIMEOUT 100U
sahilmgandhi	18:6a4db94011d3	172	/**
sahilmgandhi	18:6a4db94011d3	173	* @}
sahilmgandhi	18:6a4db94011d3	174	*/
sahilmgandhi	18:6a4db94011d3	175
sahilmgandhi	18:6a4db94011d3	176	/* Private macros ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	177	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	178	/* Private function prototypes -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	179	/** @addtogroup SPI_Private_Functions
sahilmgandhi	18:6a4db94011d3	180	* @{
sahilmgandhi	18:6a4db94011d3	181	*/
sahilmgandhi	18:6a4db94011d3	182	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	183	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	184	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	185	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	186	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	187	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	188	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	189	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	190	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
sahilmgandhi	18:6a4db94011d3	191	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	192	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	193	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	194	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	195	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	196	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	197	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	198	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	199	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	200	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	201	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	202	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	203	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	204	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	205	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	206	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	207	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
sahilmgandhi	18:6a4db94011d3	208	static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
sahilmgandhi	18:6a4db94011d3	209	/**
sahilmgandhi	18:6a4db94011d3	210	* @}
sahilmgandhi	18:6a4db94011d3	211	*/
sahilmgandhi	18:6a4db94011d3	212
sahilmgandhi	18:6a4db94011d3	213	/* Exported functions --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	214	/** @defgroup SPI_Exported_Functions SPI Exported Functions
sahilmgandhi	18:6a4db94011d3	215	* @{
sahilmgandhi	18:6a4db94011d3	216	*/
sahilmgandhi	18:6a4db94011d3	217
sahilmgandhi	18:6a4db94011d3	218	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi	18:6a4db94011d3	219	* @brief Initialization and Configuration functions
sahilmgandhi	18:6a4db94011d3	220	*
sahilmgandhi	18:6a4db94011d3	221	@verbatim
sahilmgandhi	18:6a4db94011d3	222	===============================================================================
sahilmgandhi	18:6a4db94011d3	223	##### Initialization and de-initialization functions #####
sahilmgandhi	18:6a4db94011d3	224	===============================================================================
sahilmgandhi	18:6a4db94011d3	225	[..] This subsection provides a set of functions allowing to initialize and
sahilmgandhi	18:6a4db94011d3	226	de-initialize the SPIx peripheral:
sahilmgandhi	18:6a4db94011d3	227
sahilmgandhi	18:6a4db94011d3	228	(+) User must implement HAL_SPI_MspInit() function in which he configures
sahilmgandhi	18:6a4db94011d3	229	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
sahilmgandhi	18:6a4db94011d3	230
sahilmgandhi	18:6a4db94011d3	231	(+) Call the function HAL_SPI_Init() to configure the selected device with
sahilmgandhi	18:6a4db94011d3	232	the selected configuration:
sahilmgandhi	18:6a4db94011d3	233	(++) Mode
sahilmgandhi	18:6a4db94011d3	234	(++) Direction
sahilmgandhi	18:6a4db94011d3	235	(++) Data Size
sahilmgandhi	18:6a4db94011d3	236	(++) Clock Polarity and Phase
sahilmgandhi	18:6a4db94011d3	237	(++) NSS Management
sahilmgandhi	18:6a4db94011d3	238	(++) BaudRate Prescaler
sahilmgandhi	18:6a4db94011d3	239	(++) FirstBit
sahilmgandhi	18:6a4db94011d3	240	(++) TIMode
sahilmgandhi	18:6a4db94011d3	241	(++) CRC Calculation
sahilmgandhi	18:6a4db94011d3	242	(++) CRC Polynomial if CRC enabled
sahilmgandhi	18:6a4db94011d3	243
sahilmgandhi	18:6a4db94011d3	244	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
sahilmgandhi	18:6a4db94011d3	245	of the selected SPIx peripheral.
sahilmgandhi	18:6a4db94011d3	246
sahilmgandhi	18:6a4db94011d3	247	@endverbatim
sahilmgandhi	18:6a4db94011d3	248	* @{
sahilmgandhi	18:6a4db94011d3	249	*/
sahilmgandhi	18:6a4db94011d3	250
sahilmgandhi	18:6a4db94011d3	251	/**
sahilmgandhi	18:6a4db94011d3	252	* @brief Initialize the SPI according to the specified parameters
sahilmgandhi	18:6a4db94011d3	253	* in the SPI_InitTypeDef and initialize the associated handle.
sahilmgandhi	18:6a4db94011d3	254	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	255	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	256	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	257	*/
sahilmgandhi	18:6a4db94011d3	258	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	259	{
sahilmgandhi	18:6a4db94011d3	260	/* Check the SPI handle allocation */
sahilmgandhi	18:6a4db94011d3	261	if(hspi == NULL)
sahilmgandhi	18:6a4db94011d3	262	{
sahilmgandhi	18:6a4db94011d3	263	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	264	}
sahilmgandhi	18:6a4db94011d3	265
sahilmgandhi	18:6a4db94011d3	266	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	267	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
sahilmgandhi	18:6a4db94011d3	268	assert_param(IS_SPI_MODE(hspi->Init.Mode));
sahilmgandhi	18:6a4db94011d3	269	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
sahilmgandhi	18:6a4db94011d3	270	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
sahilmgandhi	18:6a4db94011d3	271	assert_param(IS_SPI_NSS(hspi->Init.NSS));
sahilmgandhi	18:6a4db94011d3	272	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
sahilmgandhi	18:6a4db94011d3	273	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
sahilmgandhi	18:6a4db94011d3	274	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
sahilmgandhi	18:6a4db94011d3	275	if(hspi->Init.TIMode == SPI_TIMODE_DISABLE)
sahilmgandhi	18:6a4db94011d3	276	{
sahilmgandhi	18:6a4db94011d3	277	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
sahilmgandhi	18:6a4db94011d3	278	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
sahilmgandhi	18:6a4db94011d3	279	}
sahilmgandhi	18:6a4db94011d3	280	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	281	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
sahilmgandhi	18:6a4db94011d3	282	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	283	{
sahilmgandhi	18:6a4db94011d3	284	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
sahilmgandhi	18:6a4db94011d3	285	}
sahilmgandhi	18:6a4db94011d3	286	#else
sahilmgandhi	18:6a4db94011d3	287	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
sahilmgandhi	18:6a4db94011d3	288	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	289
sahilmgandhi	18:6a4db94011d3	290	if(hspi->State == HAL_SPI_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	291	{
sahilmgandhi	18:6a4db94011d3	292	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	293	hspi->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	294
sahilmgandhi	18:6a4db94011d3	295	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
sahilmgandhi	18:6a4db94011d3	296	HAL_SPI_MspInit(hspi);
sahilmgandhi	18:6a4db94011d3	297	}
sahilmgandhi	18:6a4db94011d3	298
sahilmgandhi	18:6a4db94011d3	299	hspi->State = HAL_SPI_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	300
sahilmgandhi	18:6a4db94011d3	301	/* Disable the selected SPI peripheral */
sahilmgandhi	18:6a4db94011d3	302	__HAL_SPI_DISABLE(hspi);
sahilmgandhi	18:6a4db94011d3	303
sahilmgandhi	18:6a4db94011d3	304	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
sahilmgandhi	18:6a4db94011d3	305	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
sahilmgandhi	18:6a4db94011d3	306	Communication speed, First bit and CRC calculation state */
sahilmgandhi	18:6a4db94011d3	307	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
sahilmgandhi	18:6a4db94011d3	308	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
sahilmgandhi	18:6a4db94011d3	309	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
sahilmgandhi	18:6a4db94011d3	310
sahilmgandhi	18:6a4db94011d3	311	/* Configure : NSS management */
sahilmgandhi	18:6a4db94011d3	312	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
sahilmgandhi	18:6a4db94011d3	313
sahilmgandhi	18:6a4db94011d3	314	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	315	/---------------------------- SPIx CRCPOLY Configuration ------------------/
sahilmgandhi	18:6a4db94011d3	316	/* Configure : CRC Polynomial */
sahilmgandhi	18:6a4db94011d3	317	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	318	{
sahilmgandhi	18:6a4db94011d3	319	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
sahilmgandhi	18:6a4db94011d3	320	}
sahilmgandhi	18:6a4db94011d3	321	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	322
sahilmgandhi	18:6a4db94011d3	323	#if defined(SPI_I2SCFGR_I2SMOD)
sahilmgandhi	18:6a4db94011d3	324	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
sahilmgandhi	18:6a4db94011d3	325	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
sahilmgandhi	18:6a4db94011d3	326	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	327
sahilmgandhi	18:6a4db94011d3	328	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	329	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	330
sahilmgandhi	18:6a4db94011d3	331	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	332	}
sahilmgandhi	18:6a4db94011d3	333
sahilmgandhi	18:6a4db94011d3	334	/**
sahilmgandhi	18:6a4db94011d3	335	* @brief De Initialize the SPI peripheral.
sahilmgandhi	18:6a4db94011d3	336	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	337	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	338	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	339	*/
sahilmgandhi	18:6a4db94011d3	340	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	341	{
sahilmgandhi	18:6a4db94011d3	342	/* Check the SPI handle allocation */
sahilmgandhi	18:6a4db94011d3	343	if(hspi == NULL)
sahilmgandhi	18:6a4db94011d3	344	{
sahilmgandhi	18:6a4db94011d3	345	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	346	}
sahilmgandhi	18:6a4db94011d3	347
sahilmgandhi	18:6a4db94011d3	348	/* Check SPI Instance parameter */
sahilmgandhi	18:6a4db94011d3	349	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
sahilmgandhi	18:6a4db94011d3	350
sahilmgandhi	18:6a4db94011d3	351	hspi->State = HAL_SPI_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	352
sahilmgandhi	18:6a4db94011d3	353	/* Disable the SPI Peripheral Clock */
sahilmgandhi	18:6a4db94011d3	354	__HAL_SPI_DISABLE(hspi);
sahilmgandhi	18:6a4db94011d3	355
sahilmgandhi	18:6a4db94011d3	356	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
sahilmgandhi	18:6a4db94011d3	357	HAL_SPI_MspDeInit(hspi);
sahilmgandhi	18:6a4db94011d3	358
sahilmgandhi	18:6a4db94011d3	359	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	360	hspi->State = HAL_SPI_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	361
sahilmgandhi	18:6a4db94011d3	362	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	363	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	364
sahilmgandhi	18:6a4db94011d3	365	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	366	}
sahilmgandhi	18:6a4db94011d3	367
sahilmgandhi	18:6a4db94011d3	368	/**
sahilmgandhi	18:6a4db94011d3	369	* @brief Initialize the SPI MSP.
sahilmgandhi	18:6a4db94011d3	370	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	371	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	372	* @retval None
sahilmgandhi	18:6a4db94011d3	373	*/
sahilmgandhi	18:6a4db94011d3	374	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	375	{
sahilmgandhi	18:6a4db94011d3	376	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	377	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	378	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	379	the HAL_SPI_MspInit should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	380	*/
sahilmgandhi	18:6a4db94011d3	381	}
sahilmgandhi	18:6a4db94011d3	382
sahilmgandhi	18:6a4db94011d3	383	/**
sahilmgandhi	18:6a4db94011d3	384	* @brief De-Initialize the SPI MSP.
sahilmgandhi	18:6a4db94011d3	385	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	386	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	387	* @retval None
sahilmgandhi	18:6a4db94011d3	388	*/
sahilmgandhi	18:6a4db94011d3	389	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	390	{
sahilmgandhi	18:6a4db94011d3	391	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	392	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	393	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	394	the HAL_SPI_MspDeInit should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	395	*/
sahilmgandhi	18:6a4db94011d3	396	}
sahilmgandhi	18:6a4db94011d3	397
sahilmgandhi	18:6a4db94011d3	398	/**
sahilmgandhi	18:6a4db94011d3	399	* @}
sahilmgandhi	18:6a4db94011d3	400	*/
sahilmgandhi	18:6a4db94011d3	401
sahilmgandhi	18:6a4db94011d3	402	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
sahilmgandhi	18:6a4db94011d3	403	* @brief Data transfers functions
sahilmgandhi	18:6a4db94011d3	404	*
sahilmgandhi	18:6a4db94011d3	405	@verbatim
sahilmgandhi	18:6a4db94011d3	406	==============================================================================
sahilmgandhi	18:6a4db94011d3	407	##### IO operation functions #####
sahilmgandhi	18:6a4db94011d3	408	===============================================================================
sahilmgandhi	18:6a4db94011d3	409	[..]
sahilmgandhi	18:6a4db94011d3	410	This subsection provides a set of functions allowing to manage the SPI
sahilmgandhi	18:6a4db94011d3	411	data transfers.
sahilmgandhi	18:6a4db94011d3	412
sahilmgandhi	18:6a4db94011d3	413	[..] The SPI supports master and slave mode :
sahilmgandhi	18:6a4db94011d3	414
sahilmgandhi	18:6a4db94011d3	415	(#) There are two modes of transfer:
sahilmgandhi	18:6a4db94011d3	416	(++) Blocking mode: The communication is performed in polling mode.
sahilmgandhi	18:6a4db94011d3	417	The HAL status of all data processing is returned by the same function
sahilmgandhi	18:6a4db94011d3	418	after finishing transfer.
sahilmgandhi	18:6a4db94011d3	419	(++) No-Blocking mode: The communication is performed using Interrupts
sahilmgandhi	18:6a4db94011d3	420	or DMA, These APIs return the HAL status.
sahilmgandhi	18:6a4db94011d3	421	The end of the data processing will be indicated through the
sahilmgandhi	18:6a4db94011d3	422	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
sahilmgandhi	18:6a4db94011d3	423	using DMA mode.
sahilmgandhi	18:6a4db94011d3	424	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
sahilmgandhi	18:6a4db94011d3	425	will be executed respectively at the end of the transmit or Receive process
sahilmgandhi	18:6a4db94011d3	426	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
sahilmgandhi	18:6a4db94011d3	427
sahilmgandhi	18:6a4db94011d3	428	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
sahilmgandhi	18:6a4db94011d3	429	exist for 1Line (simplex) and 2Lines (full duplex) modes.
sahilmgandhi	18:6a4db94011d3	430
sahilmgandhi	18:6a4db94011d3	431	@endverbatim
sahilmgandhi	18:6a4db94011d3	432	* @{
sahilmgandhi	18:6a4db94011d3	433	*/
sahilmgandhi	18:6a4db94011d3	434
sahilmgandhi	18:6a4db94011d3	435	/**
sahilmgandhi	18:6a4db94011d3	436	* @brief Transmit an amount of data in blocking mode.
sahilmgandhi	18:6a4db94011d3	437	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	438	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	439	* @param pData: pointer to data buffer
sahilmgandhi	18:6a4db94011d3	440	* @param Size: amount of data to be sent
sahilmgandhi	18:6a4db94011d3	441	* @param Timeout: Timeout duration
sahilmgandhi	18:6a4db94011d3	442	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	443	*/
sahilmgandhi	18:6a4db94011d3	444	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
sahilmgandhi	18:6a4db94011d3	445	{
sahilmgandhi	18:6a4db94011d3	446	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	447	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	448
sahilmgandhi	18:6a4db94011d3	449	/* Check Direction parameter */
sahilmgandhi	18:6a4db94011d3	450	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
sahilmgandhi	18:6a4db94011d3	451
sahilmgandhi	18:6a4db94011d3	452	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	453	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	454
sahilmgandhi	18:6a4db94011d3	455	/* Init tickstart for timeout management*/
sahilmgandhi	18:6a4db94011d3	456	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	457
sahilmgandhi	18:6a4db94011d3	458	if(hspi->State != HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	459	{
sahilmgandhi	18:6a4db94011d3	460	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	461	goto error;
sahilmgandhi	18:6a4db94011d3	462	}
sahilmgandhi	18:6a4db94011d3	463
sahilmgandhi	18:6a4db94011d3	464	if((pData == NULL ) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	465	{
sahilmgandhi	18:6a4db94011d3	466	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	467	goto error;
sahilmgandhi	18:6a4db94011d3	468	}
sahilmgandhi	18:6a4db94011d3	469
sahilmgandhi	18:6a4db94011d3	470	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	471	hspi->State = HAL_SPI_STATE_BUSY_TX;
sahilmgandhi	18:6a4db94011d3	472	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	473	hspi->pTxBuffPtr = (uint8_t *)pData;
sahilmgandhi	18:6a4db94011d3	474	hspi->TxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	475	hspi->TxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	476
sahilmgandhi	18:6a4db94011d3	477	/Init field not used in handle to zero /
sahilmgandhi	18:6a4db94011d3	478	hspi->pRxBuffPtr = (uint8_t *)NULL;
sahilmgandhi	18:6a4db94011d3	479	hspi->RxXferSize = 0U;
sahilmgandhi	18:6a4db94011d3	480	hspi->RxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	481	hspi->TxISR = NULL;
sahilmgandhi	18:6a4db94011d3	482	hspi->RxISR = NULL;
sahilmgandhi	18:6a4db94011d3	483
sahilmgandhi	18:6a4db94011d3	484	/* Configure communication direction : 1Line */
sahilmgandhi	18:6a4db94011d3	485	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi	18:6a4db94011d3	486	{
sahilmgandhi	18:6a4db94011d3	487	SPI_1LINE_TX(hspi);
sahilmgandhi	18:6a4db94011d3	488	}
sahilmgandhi	18:6a4db94011d3	489
sahilmgandhi	18:6a4db94011d3	490	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	491	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	492	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	493	{
sahilmgandhi	18:6a4db94011d3	494	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	495	}
sahilmgandhi	18:6a4db94011d3	496	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	497
sahilmgandhi	18:6a4db94011d3	498	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	499	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	500	{
sahilmgandhi	18:6a4db94011d3	501	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	502	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	503	}
sahilmgandhi	18:6a4db94011d3	504
sahilmgandhi	18:6a4db94011d3	505	/* Transmit data in 16 Bit mode */
sahilmgandhi	18:6a4db94011d3	506	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
sahilmgandhi	18:6a4db94011d3	507	{
sahilmgandhi	18:6a4db94011d3	508	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
sahilmgandhi	18:6a4db94011d3	509	{
sahilmgandhi	18:6a4db94011d3	510	hspi->Instance->DR = ((uint16_t )pData);
sahilmgandhi	18:6a4db94011d3	511	pData += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	512	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	513	}
sahilmgandhi	18:6a4db94011d3	514	/* Transmit data in 16 Bit mode */
sahilmgandhi	18:6a4db94011d3	515	while (hspi->TxXferCount > 0U)
sahilmgandhi	18:6a4db94011d3	516	{
sahilmgandhi	18:6a4db94011d3	517	/* Wait until TXE flag is set to send data */
sahilmgandhi	18:6a4db94011d3	518	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
sahilmgandhi	18:6a4db94011d3	519	{
sahilmgandhi	18:6a4db94011d3	520	hspi->Instance->DR = ((uint16_t )pData);
sahilmgandhi	18:6a4db94011d3	521	pData += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	522	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	523	}
sahilmgandhi	18:6a4db94011d3	524	else
sahilmgandhi	18:6a4db94011d3	525	{
sahilmgandhi	18:6a4db94011d3	526	/* Timeout management */
sahilmgandhi	18:6a4db94011d3	527	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
sahilmgandhi	18:6a4db94011d3	528	{
sahilmgandhi	18:6a4db94011d3	529	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	530	goto error;
sahilmgandhi	18:6a4db94011d3	531	}
sahilmgandhi	18:6a4db94011d3	532	}
sahilmgandhi	18:6a4db94011d3	533	}
sahilmgandhi	18:6a4db94011d3	534	}
sahilmgandhi	18:6a4db94011d3	535	/* Transmit data in 8 Bit mode */
sahilmgandhi	18:6a4db94011d3	536	else
sahilmgandhi	18:6a4db94011d3	537	{
sahilmgandhi	18:6a4db94011d3	538	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
sahilmgandhi	18:6a4db94011d3	539	{
sahilmgandhi	18:6a4db94011d3	540	((__IO uint8_t)&hspi->Instance->DR) = (*pData);
sahilmgandhi	18:6a4db94011d3	541	pData += sizeof(uint8_t);
sahilmgandhi	18:6a4db94011d3	542	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	543	}
sahilmgandhi	18:6a4db94011d3	544	while (hspi->TxXferCount > 0U)
sahilmgandhi	18:6a4db94011d3	545	{
sahilmgandhi	18:6a4db94011d3	546	/* Wait until TXE flag is set to send data */
sahilmgandhi	18:6a4db94011d3	547	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
sahilmgandhi	18:6a4db94011d3	548	{
sahilmgandhi	18:6a4db94011d3	549	((__IO uint8_t)&hspi->Instance->DR) = (*pData);
sahilmgandhi	18:6a4db94011d3	550	pData += sizeof(uint8_t);
sahilmgandhi	18:6a4db94011d3	551	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	552	}
sahilmgandhi	18:6a4db94011d3	553	else
sahilmgandhi	18:6a4db94011d3	554	{
sahilmgandhi	18:6a4db94011d3	555	/* Timeout management */
sahilmgandhi	18:6a4db94011d3	556	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
sahilmgandhi	18:6a4db94011d3	557	{
sahilmgandhi	18:6a4db94011d3	558	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	559	goto error;
sahilmgandhi	18:6a4db94011d3	560	}
sahilmgandhi	18:6a4db94011d3	561	}
sahilmgandhi	18:6a4db94011d3	562	}
sahilmgandhi	18:6a4db94011d3	563	}
sahilmgandhi	18:6a4db94011d3	564
sahilmgandhi	18:6a4db94011d3	565	/* Wait until TXE flag */
sahilmgandhi	18:6a4db94011d3	566	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	567	{
sahilmgandhi	18:6a4db94011d3	568	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	569	goto error;
sahilmgandhi	18:6a4db94011d3	570	}
sahilmgandhi	18:6a4db94011d3	571
sahilmgandhi	18:6a4db94011d3	572	/* Check Busy flag */
sahilmgandhi	18:6a4db94011d3	573	if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	574	{
sahilmgandhi	18:6a4db94011d3	575	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	576	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
sahilmgandhi	18:6a4db94011d3	577	goto error;
sahilmgandhi	18:6a4db94011d3	578	}
sahilmgandhi	18:6a4db94011d3	579
sahilmgandhi	18:6a4db94011d3	580	/* Clear overrun flag in 2 Lines communication mode because received is not read */
sahilmgandhi	18:6a4db94011d3	581	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi	18:6a4db94011d3	582	{
sahilmgandhi	18:6a4db94011d3	583	__HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	584	}
sahilmgandhi	18:6a4db94011d3	585	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	586	/* Enable CRC Transmission */
sahilmgandhi	18:6a4db94011d3	587	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	588	{
sahilmgandhi	18:6a4db94011d3	589	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	590	}
sahilmgandhi	18:6a4db94011d3	591	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	592
sahilmgandhi	18:6a4db94011d3	593	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	594	{
sahilmgandhi	18:6a4db94011d3	595	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	596	}
sahilmgandhi	18:6a4db94011d3	597
sahilmgandhi	18:6a4db94011d3	598	error:
sahilmgandhi	18:6a4db94011d3	599	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	600	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	601	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	602	return errorcode;
sahilmgandhi	18:6a4db94011d3	603	}
sahilmgandhi	18:6a4db94011d3	604
sahilmgandhi	18:6a4db94011d3	605	/**
sahilmgandhi	18:6a4db94011d3	606	* @brief Receive an amount of data in blocking mode.
sahilmgandhi	18:6a4db94011d3	607	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	608	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	609	* @param pData: pointer to data buffer
sahilmgandhi	18:6a4db94011d3	610	* @param Size: amount of data to be received
sahilmgandhi	18:6a4db94011d3	611	* @param Timeout: Timeout duration
sahilmgandhi	18:6a4db94011d3	612	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	613	*/
sahilmgandhi	18:6a4db94011d3	614	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
sahilmgandhi	18:6a4db94011d3	615	{
sahilmgandhi	18:6a4db94011d3	616	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	617	__IO uint16_t tmpreg = 0U;
sahilmgandhi	18:6a4db94011d3	618	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	619	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	620	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	621
sahilmgandhi	18:6a4db94011d3	622	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
sahilmgandhi	18:6a4db94011d3	623	{
sahilmgandhi	18:6a4db94011d3	624	hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi	18:6a4db94011d3	625	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
sahilmgandhi	18:6a4db94011d3	626	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
sahilmgandhi	18:6a4db94011d3	627	}
sahilmgandhi	18:6a4db94011d3	628
sahilmgandhi	18:6a4db94011d3	629	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	630	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	631
sahilmgandhi	18:6a4db94011d3	632	/* Init tickstart for timeout management*/
sahilmgandhi	18:6a4db94011d3	633	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	634
sahilmgandhi	18:6a4db94011d3	635	if(hspi->State != HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	636	{
sahilmgandhi	18:6a4db94011d3	637	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	638	goto error;
sahilmgandhi	18:6a4db94011d3	639	}
sahilmgandhi	18:6a4db94011d3	640
sahilmgandhi	18:6a4db94011d3	641	if((pData == NULL ) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	642	{
sahilmgandhi	18:6a4db94011d3	643	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	644	goto error;
sahilmgandhi	18:6a4db94011d3	645	}
sahilmgandhi	18:6a4db94011d3	646
sahilmgandhi	18:6a4db94011d3	647	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	648	hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi	18:6a4db94011d3	649	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	650	hspi->pRxBuffPtr = (uint8_t *)pData;
sahilmgandhi	18:6a4db94011d3	651	hspi->RxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	652	hspi->RxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	653
sahilmgandhi	18:6a4db94011d3	654	/Init field not used in handle to zero /
sahilmgandhi	18:6a4db94011d3	655	hspi->pTxBuffPtr = (uint8_t *)NULL;
sahilmgandhi	18:6a4db94011d3	656	hspi->TxXferSize = 0U;
sahilmgandhi	18:6a4db94011d3	657	hspi->TxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	658	hspi->RxISR = NULL;
sahilmgandhi	18:6a4db94011d3	659	hspi->TxISR = NULL;
sahilmgandhi	18:6a4db94011d3	660
sahilmgandhi	18:6a4db94011d3	661	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	662	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	663	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	664	{
sahilmgandhi	18:6a4db94011d3	665	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	666	/* this is done to handle the CRCNEXT before the latest data */
sahilmgandhi	18:6a4db94011d3	667	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	668	}
sahilmgandhi	18:6a4db94011d3	669	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	670
sahilmgandhi	18:6a4db94011d3	671	/* Configure communication direction: 1Line */
sahilmgandhi	18:6a4db94011d3	672	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi	18:6a4db94011d3	673	{
sahilmgandhi	18:6a4db94011d3	674	SPI_1LINE_RX(hspi);
sahilmgandhi	18:6a4db94011d3	675	}
sahilmgandhi	18:6a4db94011d3	676
sahilmgandhi	18:6a4db94011d3	677	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	678	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	679	{
sahilmgandhi	18:6a4db94011d3	680	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	681	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	682	}
sahilmgandhi	18:6a4db94011d3	683
sahilmgandhi	18:6a4db94011d3	684	/* Receive data in 8 Bit mode */
sahilmgandhi	18:6a4db94011d3	685	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
sahilmgandhi	18:6a4db94011d3	686	{
sahilmgandhi	18:6a4db94011d3	687	/* Transfer loop */
sahilmgandhi	18:6a4db94011d3	688	while(hspi->RxXferCount > 0U)
sahilmgandhi	18:6a4db94011d3	689	{
sahilmgandhi	18:6a4db94011d3	690	/* Check the RXNE flag */
sahilmgandhi	18:6a4db94011d3	691	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
sahilmgandhi	18:6a4db94011d3	692	{
sahilmgandhi	18:6a4db94011d3	693	/* read the received data */
sahilmgandhi	18:6a4db94011d3	694	(* (uint8_t )pData)= (__IO uint8_t *)&hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	695	pData += sizeof(uint8_t);
sahilmgandhi	18:6a4db94011d3	696	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	697	}
sahilmgandhi	18:6a4db94011d3	698	else
sahilmgandhi	18:6a4db94011d3	699	{
sahilmgandhi	18:6a4db94011d3	700	/* Timeout management */
sahilmgandhi	18:6a4db94011d3	701	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
sahilmgandhi	18:6a4db94011d3	702	{
sahilmgandhi	18:6a4db94011d3	703	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	704	goto error;
sahilmgandhi	18:6a4db94011d3	705	}
sahilmgandhi	18:6a4db94011d3	706	}
sahilmgandhi	18:6a4db94011d3	707	}
sahilmgandhi	18:6a4db94011d3	708	}
sahilmgandhi	18:6a4db94011d3	709	else
sahilmgandhi	18:6a4db94011d3	710	{
sahilmgandhi	18:6a4db94011d3	711	/* Transfer loop */
sahilmgandhi	18:6a4db94011d3	712	while(hspi->RxXferCount > 0U)
sahilmgandhi	18:6a4db94011d3	713	{
sahilmgandhi	18:6a4db94011d3	714	/* Check the RXNE flag */
sahilmgandhi	18:6a4db94011d3	715	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
sahilmgandhi	18:6a4db94011d3	716	{
sahilmgandhi	18:6a4db94011d3	717	((uint16_t)pData) = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	718	pData += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	719	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	720	}
sahilmgandhi	18:6a4db94011d3	721	else
sahilmgandhi	18:6a4db94011d3	722	{
sahilmgandhi	18:6a4db94011d3	723	/* Timeout management */
sahilmgandhi	18:6a4db94011d3	724	if((Timeout == 0U) \|\| ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
sahilmgandhi	18:6a4db94011d3	725	{
sahilmgandhi	18:6a4db94011d3	726	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	727	goto error;
sahilmgandhi	18:6a4db94011d3	728	}
sahilmgandhi	18:6a4db94011d3	729	}
sahilmgandhi	18:6a4db94011d3	730	}
sahilmgandhi	18:6a4db94011d3	731	}
sahilmgandhi	18:6a4db94011d3	732
sahilmgandhi	18:6a4db94011d3	733	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	734	/* Handle the CRC Transmission */
sahilmgandhi	18:6a4db94011d3	735	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	736	{
sahilmgandhi	18:6a4db94011d3	737	/* freeze the CRC before the latest data */
sahilmgandhi	18:6a4db94011d3	738	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	739
sahilmgandhi	18:6a4db94011d3	740	/* Read the latest data */
sahilmgandhi	18:6a4db94011d3	741	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	742	{
sahilmgandhi	18:6a4db94011d3	743	/* the latest data has not been received */
sahilmgandhi	18:6a4db94011d3	744	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	745	goto error;
sahilmgandhi	18:6a4db94011d3	746	}
sahilmgandhi	18:6a4db94011d3	747
sahilmgandhi	18:6a4db94011d3	748	/* Receive last data in 16 Bit mode */
sahilmgandhi	18:6a4db94011d3	749	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
sahilmgandhi	18:6a4db94011d3	750	{
sahilmgandhi	18:6a4db94011d3	751	((uint16_t)pData) = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	752	}
sahilmgandhi	18:6a4db94011d3	753	/* Receive last data in 8 Bit mode */
sahilmgandhi	18:6a4db94011d3	754	else
sahilmgandhi	18:6a4db94011d3	755	{
sahilmgandhi	18:6a4db94011d3	756	((uint8_t )pData) = (__IO uint8_t )&hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	757	}
sahilmgandhi	18:6a4db94011d3	758
sahilmgandhi	18:6a4db94011d3	759	/* Wait the CRC data */
sahilmgandhi	18:6a4db94011d3	760	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	761	{
sahilmgandhi	18:6a4db94011d3	762	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	763	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	764	goto error;
sahilmgandhi	18:6a4db94011d3	765	}
sahilmgandhi	18:6a4db94011d3	766
sahilmgandhi	18:6a4db94011d3	767	/* Read CRC to Flush DR and RXNE flag */
sahilmgandhi	18:6a4db94011d3	768	tmpreg = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	769	/* To avoid GCC warning */
sahilmgandhi	18:6a4db94011d3	770	UNUSED(tmpreg);
sahilmgandhi	18:6a4db94011d3	771	}
sahilmgandhi	18:6a4db94011d3	772	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	773
sahilmgandhi	18:6a4db94011d3	774	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
sahilmgandhi	18:6a4db94011d3	775	{
sahilmgandhi	18:6a4db94011d3	776	/* Disable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	777	__HAL_SPI_DISABLE(hspi);
sahilmgandhi	18:6a4db94011d3	778	}
sahilmgandhi	18:6a4db94011d3	779
sahilmgandhi	18:6a4db94011d3	780	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	781	/* Check if CRC error occurred */
sahilmgandhi	18:6a4db94011d3	782	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
sahilmgandhi	18:6a4db94011d3	783	{
sahilmgandhi	18:6a4db94011d3	784	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	785	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	786	}
sahilmgandhi	18:6a4db94011d3	787	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	788
sahilmgandhi	18:6a4db94011d3	789	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	790	{
sahilmgandhi	18:6a4db94011d3	791	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	792	}
sahilmgandhi	18:6a4db94011d3	793
sahilmgandhi	18:6a4db94011d3	794	error :
sahilmgandhi	18:6a4db94011d3	795	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	796	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	797	return errorcode;
sahilmgandhi	18:6a4db94011d3	798	}
sahilmgandhi	18:6a4db94011d3	799
sahilmgandhi	18:6a4db94011d3	800	/**
sahilmgandhi	18:6a4db94011d3	801	* @brief Transmit and Receive an amount of data in blocking mode.
sahilmgandhi	18:6a4db94011d3	802	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	803	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	804	* @param pTxData: pointer to transmission data buffer
sahilmgandhi	18:6a4db94011d3	805	* @param pRxData: pointer to reception data buffer
sahilmgandhi	18:6a4db94011d3	806	* @param Size: amount of data to be sent and received
sahilmgandhi	18:6a4db94011d3	807	* @param Timeout: Timeout duration
sahilmgandhi	18:6a4db94011d3	808	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	809	*/
sahilmgandhi	18:6a4db94011d3	810	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
sahilmgandhi	18:6a4db94011d3	811	{
sahilmgandhi	18:6a4db94011d3	812	uint32_t tmp = 0U, tmp1 = 0U;
sahilmgandhi	18:6a4db94011d3	813	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	814	__IO uint16_t tmpreg1 = 0U;
sahilmgandhi	18:6a4db94011d3	815	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	816	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	817	/* Variable used to alternate Rx and Tx during transfer */
sahilmgandhi	18:6a4db94011d3	818	uint32_t txallowed = 1U;
sahilmgandhi	18:6a4db94011d3	819	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	820
sahilmgandhi	18:6a4db94011d3	821	/* Check Direction parameter */
sahilmgandhi	18:6a4db94011d3	822	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
sahilmgandhi	18:6a4db94011d3	823
sahilmgandhi	18:6a4db94011d3	824	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	825	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	826
sahilmgandhi	18:6a4db94011d3	827	/* Init tickstart for timeout management*/
sahilmgandhi	18:6a4db94011d3	828	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	829
sahilmgandhi	18:6a4db94011d3	830	tmp = hspi->State;
sahilmgandhi	18:6a4db94011d3	831	tmp1 = hspi->Init.Mode;
sahilmgandhi	18:6a4db94011d3	832
sahilmgandhi	18:6a4db94011d3	833	if(!((tmp == HAL_SPI_STATE_READY) \|\| \
sahilmgandhi	18:6a4db94011d3	834	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
sahilmgandhi	18:6a4db94011d3	835	{
sahilmgandhi	18:6a4db94011d3	836	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	837	goto error;
sahilmgandhi	18:6a4db94011d3	838	}
sahilmgandhi	18:6a4db94011d3	839
sahilmgandhi	18:6a4db94011d3	840	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	841	{
sahilmgandhi	18:6a4db94011d3	842	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	843	goto error;
sahilmgandhi	18:6a4db94011d3	844	}
sahilmgandhi	18:6a4db94011d3	845
sahilmgandhi	18:6a4db94011d3	846	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
sahilmgandhi	18:6a4db94011d3	847	if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	848	{
sahilmgandhi	18:6a4db94011d3	849	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
sahilmgandhi	18:6a4db94011d3	850	}
sahilmgandhi	18:6a4db94011d3	851
sahilmgandhi	18:6a4db94011d3	852	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	853	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	854	hspi->pRxBuffPtr = (uint8_t *)pRxData;
sahilmgandhi	18:6a4db94011d3	855	hspi->RxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	856	hspi->RxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	857	hspi->pTxBuffPtr = (uint8_t *)pTxData;
sahilmgandhi	18:6a4db94011d3	858	hspi->TxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	859	hspi->TxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	860
sahilmgandhi	18:6a4db94011d3	861	/Init field not used in handle to zero /
sahilmgandhi	18:6a4db94011d3	862	hspi->RxISR = NULL;
sahilmgandhi	18:6a4db94011d3	863	hspi->TxISR = NULL;
sahilmgandhi	18:6a4db94011d3	864
sahilmgandhi	18:6a4db94011d3	865	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	866	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	867	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	868	{
sahilmgandhi	18:6a4db94011d3	869	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	870	}
sahilmgandhi	18:6a4db94011d3	871	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	872
sahilmgandhi	18:6a4db94011d3	873	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	874	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	875	{
sahilmgandhi	18:6a4db94011d3	876	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	877	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	878	}
sahilmgandhi	18:6a4db94011d3	879
sahilmgandhi	18:6a4db94011d3	880	/* Transmit and Receive data in 16 Bit mode */
sahilmgandhi	18:6a4db94011d3	881	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
sahilmgandhi	18:6a4db94011d3	882	{
sahilmgandhi	18:6a4db94011d3	883	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
sahilmgandhi	18:6a4db94011d3	884	{
sahilmgandhi	18:6a4db94011d3	885	hspi->Instance->DR = ((uint16_t )pTxData);
sahilmgandhi	18:6a4db94011d3	886	pTxData += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	887	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	888	}
sahilmgandhi	18:6a4db94011d3	889	while ((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
sahilmgandhi	18:6a4db94011d3	890	{
sahilmgandhi	18:6a4db94011d3	891	/* Check TXE flag */
sahilmgandhi	18:6a4db94011d3	892	if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
sahilmgandhi	18:6a4db94011d3	893	{
sahilmgandhi	18:6a4db94011d3	894	hspi->Instance->DR = ((uint16_t )pTxData);
sahilmgandhi	18:6a4db94011d3	895	pTxData += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	896	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	897	/* Next Data is a reception (Rx). Tx not allowed */
sahilmgandhi	18:6a4db94011d3	898	txallowed = 0U;
sahilmgandhi	18:6a4db94011d3	899
sahilmgandhi	18:6a4db94011d3	900	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	901	/* Enable CRC Transmission */
sahilmgandhi	18:6a4db94011d3	902	if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi	18:6a4db94011d3	903	{
sahilmgandhi	18:6a4db94011d3	904	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	905	}
sahilmgandhi	18:6a4db94011d3	906	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	907	}
sahilmgandhi	18:6a4db94011d3	908
sahilmgandhi	18:6a4db94011d3	909	/* Check RXNE flag */
sahilmgandhi	18:6a4db94011d3	910	if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
sahilmgandhi	18:6a4db94011d3	911	{
sahilmgandhi	18:6a4db94011d3	912	((uint16_t )pRxData) = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	913	pRxData += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	914	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	915	/* Next Data is a Transmission (Tx). Tx is allowed */
sahilmgandhi	18:6a4db94011d3	916	txallowed = 1U;
sahilmgandhi	18:6a4db94011d3	917	}
sahilmgandhi	18:6a4db94011d3	918	if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
sahilmgandhi	18:6a4db94011d3	919	{
sahilmgandhi	18:6a4db94011d3	920	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	921	goto error;
sahilmgandhi	18:6a4db94011d3	922	}
sahilmgandhi	18:6a4db94011d3	923	}
sahilmgandhi	18:6a4db94011d3	924	}
sahilmgandhi	18:6a4db94011d3	925	/* Transmit and Receive data in 8 Bit mode */
sahilmgandhi	18:6a4db94011d3	926	else
sahilmgandhi	18:6a4db94011d3	927	{
sahilmgandhi	18:6a4db94011d3	928	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
sahilmgandhi	18:6a4db94011d3	929	{
sahilmgandhi	18:6a4db94011d3	930	((__IO uint8_t)&hspi->Instance->DR) = (*pTxData);
sahilmgandhi	18:6a4db94011d3	931	pTxData += sizeof(uint8_t);
sahilmgandhi	18:6a4db94011d3	932	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	933	}
sahilmgandhi	18:6a4db94011d3	934	while((hspi->TxXferCount > 0U) \|\| (hspi->RxXferCount > 0U))
sahilmgandhi	18:6a4db94011d3	935	{
sahilmgandhi	18:6a4db94011d3	936	/* check TXE flag */
sahilmgandhi	18:6a4db94011d3	937	if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
sahilmgandhi	18:6a4db94011d3	938	{
sahilmgandhi	18:6a4db94011d3	939	(__IO uint8_t )&hspi->Instance->DR = (*pTxData++);
sahilmgandhi	18:6a4db94011d3	940	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	941	/* Next Data is a reception (Rx). Tx not allowed */
sahilmgandhi	18:6a4db94011d3	942	txallowed = 0U;
sahilmgandhi	18:6a4db94011d3	943
sahilmgandhi	18:6a4db94011d3	944	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	945	/* Enable CRC Transmission */
sahilmgandhi	18:6a4db94011d3	946	if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi	18:6a4db94011d3	947	{
sahilmgandhi	18:6a4db94011d3	948	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	949	}
sahilmgandhi	18:6a4db94011d3	950	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	951	}
sahilmgandhi	18:6a4db94011d3	952
sahilmgandhi	18:6a4db94011d3	953	/* Wait until RXNE flag is reset */
sahilmgandhi	18:6a4db94011d3	954	if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
sahilmgandhi	18:6a4db94011d3	955	{
sahilmgandhi	18:6a4db94011d3	956	((uint8_t )pRxData++) = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	957	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	958	/* Next Data is a Transmission (Tx). Tx is allowed */
sahilmgandhi	18:6a4db94011d3	959	txallowed = 1U;
sahilmgandhi	18:6a4db94011d3	960	}
sahilmgandhi	18:6a4db94011d3	961	if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
sahilmgandhi	18:6a4db94011d3	962	{
sahilmgandhi	18:6a4db94011d3	963	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	964	goto error;
sahilmgandhi	18:6a4db94011d3	965	}
sahilmgandhi	18:6a4db94011d3	966	}
sahilmgandhi	18:6a4db94011d3	967	}
sahilmgandhi	18:6a4db94011d3	968
sahilmgandhi	18:6a4db94011d3	969	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	970	/* Read CRC from DR to close CRC calculation process */
sahilmgandhi	18:6a4db94011d3	971	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	972	{
sahilmgandhi	18:6a4db94011d3	973	/* Wait until TXE flag */
sahilmgandhi	18:6a4db94011d3	974	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	975	{
sahilmgandhi	18:6a4db94011d3	976	/* Error on the CRC reception */
sahilmgandhi	18:6a4db94011d3	977	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	978	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	979	goto error;
sahilmgandhi	18:6a4db94011d3	980	}
sahilmgandhi	18:6a4db94011d3	981	/* Read CRC */
sahilmgandhi	18:6a4db94011d3	982	tmpreg1 = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	983	/* To avoid GCC warning */
sahilmgandhi	18:6a4db94011d3	984	UNUSED(tmpreg1);
sahilmgandhi	18:6a4db94011d3	985	}
sahilmgandhi	18:6a4db94011d3	986
sahilmgandhi	18:6a4db94011d3	987	/* Check if CRC error occurred */
sahilmgandhi	18:6a4db94011d3	988	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
sahilmgandhi	18:6a4db94011d3	989	{
sahilmgandhi	18:6a4db94011d3	990	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	991	/* Clear CRC Flag */
sahilmgandhi	18:6a4db94011d3	992	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	993
sahilmgandhi	18:6a4db94011d3	994	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	995	}
sahilmgandhi	18:6a4db94011d3	996	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	997
sahilmgandhi	18:6a4db94011d3	998	/* Wait until TXE flag */
sahilmgandhi	18:6a4db94011d3	999	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	1000	{
sahilmgandhi	18:6a4db94011d3	1001	errorcode = HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1002	goto error;
sahilmgandhi	18:6a4db94011d3	1003	}
sahilmgandhi	18:6a4db94011d3	1004
sahilmgandhi	18:6a4db94011d3	1005	/* Check Busy flag */
sahilmgandhi	18:6a4db94011d3	1006	if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	1007	{
sahilmgandhi	18:6a4db94011d3	1008	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1009	hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
sahilmgandhi	18:6a4db94011d3	1010	goto error;
sahilmgandhi	18:6a4db94011d3	1011	}
sahilmgandhi	18:6a4db94011d3	1012
sahilmgandhi	18:6a4db94011d3	1013	/* Clear overrun flag in 2 Lines communication mode because received is not read */
sahilmgandhi	18:6a4db94011d3	1014	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi	18:6a4db94011d3	1015	{
sahilmgandhi	18:6a4db94011d3	1016	__HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	1017	}
sahilmgandhi	18:6a4db94011d3	1018
sahilmgandhi	18:6a4db94011d3	1019	error :
sahilmgandhi	18:6a4db94011d3	1020	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1021	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1022	return errorcode;
sahilmgandhi	18:6a4db94011d3	1023	}
sahilmgandhi	18:6a4db94011d3	1024
sahilmgandhi	18:6a4db94011d3	1025	/**
sahilmgandhi	18:6a4db94011d3	1026	* @brief Transmit an amount of data in non-blocking mode with Interrupt.
sahilmgandhi	18:6a4db94011d3	1027	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1028	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1029	* @param pData: pointer to data buffer
sahilmgandhi	18:6a4db94011d3	1030	* @param Size: amount of data to be sent
sahilmgandhi	18:6a4db94011d3	1031	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1032	*/
sahilmgandhi	18:6a4db94011d3	1033	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
sahilmgandhi	18:6a4db94011d3	1034	{
sahilmgandhi	18:6a4db94011d3	1035	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	1036
sahilmgandhi	18:6a4db94011d3	1037	/* Check Direction parameter */
sahilmgandhi	18:6a4db94011d3	1038	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
sahilmgandhi	18:6a4db94011d3	1039
sahilmgandhi	18:6a4db94011d3	1040	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	1041	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1042
sahilmgandhi	18:6a4db94011d3	1043	if((pData == NULL) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	1044	{
sahilmgandhi	18:6a4db94011d3	1045	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1046	goto error;
sahilmgandhi	18:6a4db94011d3	1047	}
sahilmgandhi	18:6a4db94011d3	1048
sahilmgandhi	18:6a4db94011d3	1049	if(hspi->State != HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	1050	{
sahilmgandhi	18:6a4db94011d3	1051	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	1052	goto error;
sahilmgandhi	18:6a4db94011d3	1053	}
sahilmgandhi	18:6a4db94011d3	1054
sahilmgandhi	18:6a4db94011d3	1055	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	1056	hspi->State = HAL_SPI_STATE_BUSY_TX;
sahilmgandhi	18:6a4db94011d3	1057	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	1058	hspi->pTxBuffPtr = (uint8_t *)pData;
sahilmgandhi	18:6a4db94011d3	1059	hspi->TxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	1060	hspi->TxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	1061
sahilmgandhi	18:6a4db94011d3	1062	/* Init field not used in handle to zero */
sahilmgandhi	18:6a4db94011d3	1063	hspi->pRxBuffPtr = (uint8_t *)NULL;
sahilmgandhi	18:6a4db94011d3	1064	hspi->RxXferSize = 0U;
sahilmgandhi	18:6a4db94011d3	1065	hspi->RxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	1066	hspi->RxISR = NULL;
sahilmgandhi	18:6a4db94011d3	1067
sahilmgandhi	18:6a4db94011d3	1068	/* Set the function for IT treatment */
sahilmgandhi	18:6a4db94011d3	1069	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
sahilmgandhi	18:6a4db94011d3	1070	{
sahilmgandhi	18:6a4db94011d3	1071	hspi->TxISR = SPI_TxISR_16BIT;
sahilmgandhi	18:6a4db94011d3	1072	}
sahilmgandhi	18:6a4db94011d3	1073	else
sahilmgandhi	18:6a4db94011d3	1074	{
sahilmgandhi	18:6a4db94011d3	1075	hspi->TxISR = SPI_TxISR_8BIT;
sahilmgandhi	18:6a4db94011d3	1076	}
sahilmgandhi	18:6a4db94011d3	1077
sahilmgandhi	18:6a4db94011d3	1078	/* Configure communication direction : 1Line */
sahilmgandhi	18:6a4db94011d3	1079	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi	18:6a4db94011d3	1080	{
sahilmgandhi	18:6a4db94011d3	1081	SPI_1LINE_TX(hspi);
sahilmgandhi	18:6a4db94011d3	1082	}
sahilmgandhi	18:6a4db94011d3	1083
sahilmgandhi	18:6a4db94011d3	1084	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1085	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	1086	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	1087	{
sahilmgandhi	18:6a4db94011d3	1088	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	1089	}
sahilmgandhi	18:6a4db94011d3	1090	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1091
sahilmgandhi	18:6a4db94011d3	1092	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi	18:6a4db94011d3	1093	{
sahilmgandhi	18:6a4db94011d3	1094	/* Enable TXE interrupt */
sahilmgandhi	18:6a4db94011d3	1095	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
sahilmgandhi	18:6a4db94011d3	1096	}
sahilmgandhi	18:6a4db94011d3	1097	else
sahilmgandhi	18:6a4db94011d3	1098	{
sahilmgandhi	18:6a4db94011d3	1099	/* Enable TXE and ERR interrupt */
sahilmgandhi	18:6a4db94011d3	1100	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	1101	}
sahilmgandhi	18:6a4db94011d3	1102
sahilmgandhi	18:6a4db94011d3	1103	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	1104	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	1105	{
sahilmgandhi	18:6a4db94011d3	1106	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	1107	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	1108	}
sahilmgandhi	18:6a4db94011d3	1109
sahilmgandhi	18:6a4db94011d3	1110	error :
sahilmgandhi	18:6a4db94011d3	1111	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1112	return errorcode;
sahilmgandhi	18:6a4db94011d3	1113	}
sahilmgandhi	18:6a4db94011d3	1114
sahilmgandhi	18:6a4db94011d3	1115	/**
sahilmgandhi	18:6a4db94011d3	1116	* @brief Receive an amount of data in non-blocking mode with Interrupt.
sahilmgandhi	18:6a4db94011d3	1117	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1118	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1119	* @param pData: pointer to data buffer
sahilmgandhi	18:6a4db94011d3	1120	* @param Size: amount of data to be sent
sahilmgandhi	18:6a4db94011d3	1121	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1122	*/
sahilmgandhi	18:6a4db94011d3	1123	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
sahilmgandhi	18:6a4db94011d3	1124	{
sahilmgandhi	18:6a4db94011d3	1125	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	1126
sahilmgandhi	18:6a4db94011d3	1127	if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
sahilmgandhi	18:6a4db94011d3	1128	{
sahilmgandhi	18:6a4db94011d3	1129	hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi	18:6a4db94011d3	1130	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
sahilmgandhi	18:6a4db94011d3	1131	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
sahilmgandhi	18:6a4db94011d3	1132	}
sahilmgandhi	18:6a4db94011d3	1133
sahilmgandhi	18:6a4db94011d3	1134	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	1135	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1136
sahilmgandhi	18:6a4db94011d3	1137	if(hspi->State != HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	1138	{
sahilmgandhi	18:6a4db94011d3	1139	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	1140	goto error;
sahilmgandhi	18:6a4db94011d3	1141	}
sahilmgandhi	18:6a4db94011d3	1142
sahilmgandhi	18:6a4db94011d3	1143	if((pData == NULL) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	1144	{
sahilmgandhi	18:6a4db94011d3	1145	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1146	goto error;
sahilmgandhi	18:6a4db94011d3	1147	}
sahilmgandhi	18:6a4db94011d3	1148
sahilmgandhi	18:6a4db94011d3	1149	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	1150	hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi	18:6a4db94011d3	1151	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	1152	hspi->pRxBuffPtr = (uint8_t *)pData;
sahilmgandhi	18:6a4db94011d3	1153	hspi->RxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	1154	hspi->RxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	1155
sahilmgandhi	18:6a4db94011d3	1156	/* Init field not used in handle to zero */
sahilmgandhi	18:6a4db94011d3	1157	hspi->pTxBuffPtr = (uint8_t *)NULL;
sahilmgandhi	18:6a4db94011d3	1158	hspi->TxXferSize = 0U;
sahilmgandhi	18:6a4db94011d3	1159	hspi->TxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	1160	hspi->TxISR = NULL;
sahilmgandhi	18:6a4db94011d3	1161
sahilmgandhi	18:6a4db94011d3	1162	/* Set the function for IT treatment */
sahilmgandhi	18:6a4db94011d3	1163	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
sahilmgandhi	18:6a4db94011d3	1164	{
sahilmgandhi	18:6a4db94011d3	1165	hspi->RxISR = SPI_RxISR_16BIT;
sahilmgandhi	18:6a4db94011d3	1166	}
sahilmgandhi	18:6a4db94011d3	1167	else
sahilmgandhi	18:6a4db94011d3	1168	{
sahilmgandhi	18:6a4db94011d3	1169	hspi->RxISR = SPI_RxISR_8BIT;
sahilmgandhi	18:6a4db94011d3	1170	}
sahilmgandhi	18:6a4db94011d3	1171
sahilmgandhi	18:6a4db94011d3	1172	/* Configure communication direction : 1Line */
sahilmgandhi	18:6a4db94011d3	1173	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi	18:6a4db94011d3	1174	{
sahilmgandhi	18:6a4db94011d3	1175	SPI_1LINE_RX(hspi);
sahilmgandhi	18:6a4db94011d3	1176	}
sahilmgandhi	18:6a4db94011d3	1177
sahilmgandhi	18:6a4db94011d3	1178	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1179	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	1180	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	1181	{
sahilmgandhi	18:6a4db94011d3	1182	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	1183	}
sahilmgandhi	18:6a4db94011d3	1184	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1185
sahilmgandhi	18:6a4db94011d3	1186	/* Enable TXE and ERR interrupt */
sahilmgandhi	18:6a4db94011d3	1187	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	1188
sahilmgandhi	18:6a4db94011d3	1189	/* Note : The SPI must be enabled after unlocking current process
sahilmgandhi	18:6a4db94011d3	1190	to avoid the risk of SPI interrupt handle execution before current
sahilmgandhi	18:6a4db94011d3	1191	process unlock */
sahilmgandhi	18:6a4db94011d3	1192
sahilmgandhi	18:6a4db94011d3	1193	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	1194	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	1195	{
sahilmgandhi	18:6a4db94011d3	1196	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	1197	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	1198	}
sahilmgandhi	18:6a4db94011d3	1199
sahilmgandhi	18:6a4db94011d3	1200	error :
sahilmgandhi	18:6a4db94011d3	1201	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1202	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1203	return errorcode;
sahilmgandhi	18:6a4db94011d3	1204	}
sahilmgandhi	18:6a4db94011d3	1205
sahilmgandhi	18:6a4db94011d3	1206	/**
sahilmgandhi	18:6a4db94011d3	1207	* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
sahilmgandhi	18:6a4db94011d3	1208	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1209	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1210	* @param pTxData: pointer to transmission data buffer
sahilmgandhi	18:6a4db94011d3	1211	* @param pRxData: pointer to reception data buffer
sahilmgandhi	18:6a4db94011d3	1212	* @param Size: amount of data to be sent and received
sahilmgandhi	18:6a4db94011d3	1213	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1214	*/
sahilmgandhi	18:6a4db94011d3	1215	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
sahilmgandhi	18:6a4db94011d3	1216	{
sahilmgandhi	18:6a4db94011d3	1217	uint32_t tmp = 0U, tmp1 = 0U;
sahilmgandhi	18:6a4db94011d3	1218	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	1219
sahilmgandhi	18:6a4db94011d3	1220	/* Check Direction parameter */
sahilmgandhi	18:6a4db94011d3	1221	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
sahilmgandhi	18:6a4db94011d3	1222
sahilmgandhi	18:6a4db94011d3	1223	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1224	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1225
sahilmgandhi	18:6a4db94011d3	1226	tmp = hspi->State;
sahilmgandhi	18:6a4db94011d3	1227	tmp1 = hspi->Init.Mode;
sahilmgandhi	18:6a4db94011d3	1228
sahilmgandhi	18:6a4db94011d3	1229	if(!((tmp == HAL_SPI_STATE_READY) \|\| \
sahilmgandhi	18:6a4db94011d3	1230	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
sahilmgandhi	18:6a4db94011d3	1231	{
sahilmgandhi	18:6a4db94011d3	1232	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	1233	goto error;
sahilmgandhi	18:6a4db94011d3	1234	}
sahilmgandhi	18:6a4db94011d3	1235
sahilmgandhi	18:6a4db94011d3	1236	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	1237	{
sahilmgandhi	18:6a4db94011d3	1238	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1239	goto error;
sahilmgandhi	18:6a4db94011d3	1240	}
sahilmgandhi	18:6a4db94011d3	1241
sahilmgandhi	18:6a4db94011d3	1242	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
sahilmgandhi	18:6a4db94011d3	1243	if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	1244	{
sahilmgandhi	18:6a4db94011d3	1245	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
sahilmgandhi	18:6a4db94011d3	1246	}
sahilmgandhi	18:6a4db94011d3	1247
sahilmgandhi	18:6a4db94011d3	1248	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	1249	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	1250	hspi->pTxBuffPtr = (uint8_t *)pTxData;
sahilmgandhi	18:6a4db94011d3	1251	hspi->TxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	1252	hspi->TxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	1253	hspi->pRxBuffPtr = (uint8_t *)pRxData;
sahilmgandhi	18:6a4db94011d3	1254	hspi->RxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	1255	hspi->RxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	1256
sahilmgandhi	18:6a4db94011d3	1257	/* Set the function for IT treatment */
sahilmgandhi	18:6a4db94011d3	1258	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
sahilmgandhi	18:6a4db94011d3	1259	{
sahilmgandhi	18:6a4db94011d3	1260	hspi->RxISR = SPI_2linesRxISR_16BIT;
sahilmgandhi	18:6a4db94011d3	1261	hspi->TxISR = SPI_2linesTxISR_16BIT;
sahilmgandhi	18:6a4db94011d3	1262	}
sahilmgandhi	18:6a4db94011d3	1263	else
sahilmgandhi	18:6a4db94011d3	1264	{
sahilmgandhi	18:6a4db94011d3	1265	hspi->RxISR = SPI_2linesRxISR_8BIT;
sahilmgandhi	18:6a4db94011d3	1266	hspi->TxISR = SPI_2linesTxISR_8BIT;
sahilmgandhi	18:6a4db94011d3	1267	}
sahilmgandhi	18:6a4db94011d3	1268
sahilmgandhi	18:6a4db94011d3	1269	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1270	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	1271	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	1272	{
sahilmgandhi	18:6a4db94011d3	1273	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	1274	}
sahilmgandhi	18:6a4db94011d3	1275	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1276
sahilmgandhi	18:6a4db94011d3	1277	/* Enable TXE, RXNE and ERR interrupt */
sahilmgandhi	18:6a4db94011d3	1278	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	1279
sahilmgandhi	18:6a4db94011d3	1280	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	1281	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	1282	{
sahilmgandhi	18:6a4db94011d3	1283	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	1284	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	1285	}
sahilmgandhi	18:6a4db94011d3	1286
sahilmgandhi	18:6a4db94011d3	1287	error :
sahilmgandhi	18:6a4db94011d3	1288	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1289	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1290	return errorcode;
sahilmgandhi	18:6a4db94011d3	1291	}
sahilmgandhi	18:6a4db94011d3	1292
sahilmgandhi	18:6a4db94011d3	1293	/**
sahilmgandhi	18:6a4db94011d3	1294	* @brief Transmit an amount of data in non-blocking mode with DMA.
sahilmgandhi	18:6a4db94011d3	1295	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1296	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1297	* @param pData: pointer to data buffer
sahilmgandhi	18:6a4db94011d3	1298	* @param Size: amount of data to be sent
sahilmgandhi	18:6a4db94011d3	1299	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1300	*/
sahilmgandhi	18:6a4db94011d3	1301	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
sahilmgandhi	18:6a4db94011d3	1302	{
sahilmgandhi	18:6a4db94011d3	1303	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	1304
sahilmgandhi	18:6a4db94011d3	1305	/* Check Direction parameter */
sahilmgandhi	18:6a4db94011d3	1306	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
sahilmgandhi	18:6a4db94011d3	1307
sahilmgandhi	18:6a4db94011d3	1308	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	1309	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1310
sahilmgandhi	18:6a4db94011d3	1311	if(hspi->State != HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	1312	{
sahilmgandhi	18:6a4db94011d3	1313	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	1314	goto error;
sahilmgandhi	18:6a4db94011d3	1315	}
sahilmgandhi	18:6a4db94011d3	1316
sahilmgandhi	18:6a4db94011d3	1317	if((pData == NULL) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	1318	{
sahilmgandhi	18:6a4db94011d3	1319	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1320	goto error;
sahilmgandhi	18:6a4db94011d3	1321	}
sahilmgandhi	18:6a4db94011d3	1322
sahilmgandhi	18:6a4db94011d3	1323	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	1324	hspi->State = HAL_SPI_STATE_BUSY_TX;
sahilmgandhi	18:6a4db94011d3	1325	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	1326	hspi->pTxBuffPtr = (uint8_t *)pData;
sahilmgandhi	18:6a4db94011d3	1327	hspi->TxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	1328	hspi->TxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	1329
sahilmgandhi	18:6a4db94011d3	1330	/* Init field not used in handle to zero */
sahilmgandhi	18:6a4db94011d3	1331	hspi->pRxBuffPtr = (uint8_t *)NULL;
sahilmgandhi	18:6a4db94011d3	1332	hspi->TxISR = NULL;
sahilmgandhi	18:6a4db94011d3	1333	hspi->RxISR = NULL;
sahilmgandhi	18:6a4db94011d3	1334	hspi->RxXferSize = 0U;
sahilmgandhi	18:6a4db94011d3	1335	hspi->RxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	1336
sahilmgandhi	18:6a4db94011d3	1337	/* Configure communication direction : 1Line */
sahilmgandhi	18:6a4db94011d3	1338	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi	18:6a4db94011d3	1339	{
sahilmgandhi	18:6a4db94011d3	1340	SPI_1LINE_TX(hspi);
sahilmgandhi	18:6a4db94011d3	1341	}
sahilmgandhi	18:6a4db94011d3	1342
sahilmgandhi	18:6a4db94011d3	1343	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1344	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	1345	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	1346	{
sahilmgandhi	18:6a4db94011d3	1347	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	1348	}
sahilmgandhi	18:6a4db94011d3	1349	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1350
sahilmgandhi	18:6a4db94011d3	1351	/* Set the SPI TxDMA Half transfer complete callback */
sahilmgandhi	18:6a4db94011d3	1352	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
sahilmgandhi	18:6a4db94011d3	1353
sahilmgandhi	18:6a4db94011d3	1354	/* Set the SPI TxDMA transfer complete callback */
sahilmgandhi	18:6a4db94011d3	1355	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
sahilmgandhi	18:6a4db94011d3	1356
sahilmgandhi	18:6a4db94011d3	1357	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1358	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
sahilmgandhi	18:6a4db94011d3	1359
sahilmgandhi	18:6a4db94011d3	1360	/* Set the DMA AbortCpltCallback */
sahilmgandhi	18:6a4db94011d3	1361	hspi->hdmatx->XferAbortCallback = NULL;
sahilmgandhi	18:6a4db94011d3	1362
sahilmgandhi	18:6a4db94011d3	1363	/* Enable the Tx DMA Stream */
sahilmgandhi	18:6a4db94011d3	1364	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
sahilmgandhi	18:6a4db94011d3	1365
sahilmgandhi	18:6a4db94011d3	1366	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	1367	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	1368	{
sahilmgandhi	18:6a4db94011d3	1369	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	1370	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	1371	}
sahilmgandhi	18:6a4db94011d3	1372
sahilmgandhi	18:6a4db94011d3	1373	/* Enable the SPI Error Interrupt Bit */
sahilmgandhi	18:6a4db94011d3	1374	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
sahilmgandhi	18:6a4db94011d3	1375
sahilmgandhi	18:6a4db94011d3	1376	/* Enable Tx DMA Request */
sahilmgandhi	18:6a4db94011d3	1377	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi	18:6a4db94011d3	1378
sahilmgandhi	18:6a4db94011d3	1379	error :
sahilmgandhi	18:6a4db94011d3	1380	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1381	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1382	return errorcode;
sahilmgandhi	18:6a4db94011d3	1383	}
sahilmgandhi	18:6a4db94011d3	1384
sahilmgandhi	18:6a4db94011d3	1385	/**
sahilmgandhi	18:6a4db94011d3	1386	* @brief Receive an amount of data in non-blocking mode with DMA.
sahilmgandhi	18:6a4db94011d3	1387	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1388	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1389	* @param pData: pointer to data buffer
sahilmgandhi	18:6a4db94011d3	1390	* @note When the CRC feature is enabled the pData Length must be Size + 1.
sahilmgandhi	18:6a4db94011d3	1391	* @param Size: amount of data to be sent
sahilmgandhi	18:6a4db94011d3	1392	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1393	*/
sahilmgandhi	18:6a4db94011d3	1394	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
sahilmgandhi	18:6a4db94011d3	1395	{
sahilmgandhi	18:6a4db94011d3	1396	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	1397
sahilmgandhi	18:6a4db94011d3	1398	if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
sahilmgandhi	18:6a4db94011d3	1399	{
sahilmgandhi	18:6a4db94011d3	1400	hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi	18:6a4db94011d3	1401	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
sahilmgandhi	18:6a4db94011d3	1402	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
sahilmgandhi	18:6a4db94011d3	1403	}
sahilmgandhi	18:6a4db94011d3	1404
sahilmgandhi	18:6a4db94011d3	1405	/* Process Locked */
sahilmgandhi	18:6a4db94011d3	1406	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1407
sahilmgandhi	18:6a4db94011d3	1408	if(hspi->State != HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	1409	{
sahilmgandhi	18:6a4db94011d3	1410	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	1411	goto error;
sahilmgandhi	18:6a4db94011d3	1412	}
sahilmgandhi	18:6a4db94011d3	1413
sahilmgandhi	18:6a4db94011d3	1414	if((pData == NULL) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	1415	{
sahilmgandhi	18:6a4db94011d3	1416	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1417	goto error;
sahilmgandhi	18:6a4db94011d3	1418	}
sahilmgandhi	18:6a4db94011d3	1419
sahilmgandhi	18:6a4db94011d3	1420	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	1421	hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi	18:6a4db94011d3	1422	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	1423	hspi->pRxBuffPtr = (uint8_t *)pData;
sahilmgandhi	18:6a4db94011d3	1424	hspi->RxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	1425	hspi->RxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	1426
sahilmgandhi	18:6a4db94011d3	1427	/Init field not used in handle to zero /
sahilmgandhi	18:6a4db94011d3	1428	hspi->RxISR = NULL;
sahilmgandhi	18:6a4db94011d3	1429	hspi->TxISR = NULL;
sahilmgandhi	18:6a4db94011d3	1430	hspi->TxXferSize = 0U;
sahilmgandhi	18:6a4db94011d3	1431	hspi->TxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	1432
sahilmgandhi	18:6a4db94011d3	1433	/* Configure communication direction : 1Line */
sahilmgandhi	18:6a4db94011d3	1434	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi	18:6a4db94011d3	1435	{
sahilmgandhi	18:6a4db94011d3	1436	SPI_1LINE_RX(hspi);
sahilmgandhi	18:6a4db94011d3	1437	}
sahilmgandhi	18:6a4db94011d3	1438
sahilmgandhi	18:6a4db94011d3	1439	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1440	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	1441	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	1442	{
sahilmgandhi	18:6a4db94011d3	1443	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	1444	}
sahilmgandhi	18:6a4db94011d3	1445	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1446
sahilmgandhi	18:6a4db94011d3	1447	/* Set the SPI RxDMA Half transfer complete callback */
sahilmgandhi	18:6a4db94011d3	1448	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
sahilmgandhi	18:6a4db94011d3	1449
sahilmgandhi	18:6a4db94011d3	1450	/* Set the SPI Rx DMA transfer complete callback */
sahilmgandhi	18:6a4db94011d3	1451	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
sahilmgandhi	18:6a4db94011d3	1452
sahilmgandhi	18:6a4db94011d3	1453	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1454	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
sahilmgandhi	18:6a4db94011d3	1455
sahilmgandhi	18:6a4db94011d3	1456	/* Set the DMA AbortCpltCallback */
sahilmgandhi	18:6a4db94011d3	1457	hspi->hdmarx->XferAbortCallback = NULL;
sahilmgandhi	18:6a4db94011d3	1458
sahilmgandhi	18:6a4db94011d3	1459	/* Enable the Rx DMA Stream */
sahilmgandhi	18:6a4db94011d3	1460	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
sahilmgandhi	18:6a4db94011d3	1461
sahilmgandhi	18:6a4db94011d3	1462	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	1463	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	1464	{
sahilmgandhi	18:6a4db94011d3	1465	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	1466	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	1467	}
sahilmgandhi	18:6a4db94011d3	1468
sahilmgandhi	18:6a4db94011d3	1469	/* Enable the SPI Error Interrupt Bit */
sahilmgandhi	18:6a4db94011d3	1470	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
sahilmgandhi	18:6a4db94011d3	1471
sahilmgandhi	18:6a4db94011d3	1472	/* Enable Rx DMA Request */
sahilmgandhi	18:6a4db94011d3	1473	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi	18:6a4db94011d3	1474
sahilmgandhi	18:6a4db94011d3	1475	error:
sahilmgandhi	18:6a4db94011d3	1476	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1477	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1478	return errorcode;
sahilmgandhi	18:6a4db94011d3	1479	}
sahilmgandhi	18:6a4db94011d3	1480
sahilmgandhi	18:6a4db94011d3	1481	/**
sahilmgandhi	18:6a4db94011d3	1482	* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
sahilmgandhi	18:6a4db94011d3	1483	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1484	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1485	* @param pTxData: pointer to transmission data buffer
sahilmgandhi	18:6a4db94011d3	1486	* @param pRxData: pointer to reception data buffer
sahilmgandhi	18:6a4db94011d3	1487	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
sahilmgandhi	18:6a4db94011d3	1488	* @param Size: amount of data to be sent
sahilmgandhi	18:6a4db94011d3	1489	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1490	*/
sahilmgandhi	18:6a4db94011d3	1491	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
sahilmgandhi	18:6a4db94011d3	1492	{
sahilmgandhi	18:6a4db94011d3	1493	uint32_t tmp = 0U, tmp1 = 0U;
sahilmgandhi	18:6a4db94011d3	1494	HAL_StatusTypeDef errorcode = HAL_OK;
sahilmgandhi	18:6a4db94011d3	1495
sahilmgandhi	18:6a4db94011d3	1496	/* Check Direction parameter */
sahilmgandhi	18:6a4db94011d3	1497	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
sahilmgandhi	18:6a4db94011d3	1498
sahilmgandhi	18:6a4db94011d3	1499	/* Process locked */
sahilmgandhi	18:6a4db94011d3	1500	__HAL_LOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1501
sahilmgandhi	18:6a4db94011d3	1502	tmp = hspi->State;
sahilmgandhi	18:6a4db94011d3	1503	tmp1 = hspi->Init.Mode;
sahilmgandhi	18:6a4db94011d3	1504	if(!((tmp == HAL_SPI_STATE_READY) \|\|
sahilmgandhi	18:6a4db94011d3	1505	((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
sahilmgandhi	18:6a4db94011d3	1506	{
sahilmgandhi	18:6a4db94011d3	1507	errorcode = HAL_BUSY;
sahilmgandhi	18:6a4db94011d3	1508	goto error;
sahilmgandhi	18:6a4db94011d3	1509	}
sahilmgandhi	18:6a4db94011d3	1510
sahilmgandhi	18:6a4db94011d3	1511	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0U))
sahilmgandhi	18:6a4db94011d3	1512	{
sahilmgandhi	18:6a4db94011d3	1513	errorcode = HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	1514	goto error;
sahilmgandhi	18:6a4db94011d3	1515	}
sahilmgandhi	18:6a4db94011d3	1516
sahilmgandhi	18:6a4db94011d3	1517	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
sahilmgandhi	18:6a4db94011d3	1518	if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi	18:6a4db94011d3	1519	{
sahilmgandhi	18:6a4db94011d3	1520	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
sahilmgandhi	18:6a4db94011d3	1521	}
sahilmgandhi	18:6a4db94011d3	1522
sahilmgandhi	18:6a4db94011d3	1523	/* Set the transaction information */
sahilmgandhi	18:6a4db94011d3	1524	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi	18:6a4db94011d3	1525	hspi->pTxBuffPtr = (uint8_t*)pTxData;
sahilmgandhi	18:6a4db94011d3	1526	hspi->TxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	1527	hspi->TxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	1528	hspi->pRxBuffPtr = (uint8_t*)pRxData;
sahilmgandhi	18:6a4db94011d3	1529	hspi->RxXferSize = Size;
sahilmgandhi	18:6a4db94011d3	1530	hspi->RxXferCount = Size;
sahilmgandhi	18:6a4db94011d3	1531
sahilmgandhi	18:6a4db94011d3	1532	/* Init field not used in handle to zero */
sahilmgandhi	18:6a4db94011d3	1533	hspi->RxISR = NULL;
sahilmgandhi	18:6a4db94011d3	1534	hspi->TxISR = NULL;
sahilmgandhi	18:6a4db94011d3	1535
sahilmgandhi	18:6a4db94011d3	1536	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1537	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	1538	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	1539	{
sahilmgandhi	18:6a4db94011d3	1540	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	1541	}
sahilmgandhi	18:6a4db94011d3	1542	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1543
sahilmgandhi	18:6a4db94011d3	1544	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
sahilmgandhi	18:6a4db94011d3	1545	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
sahilmgandhi	18:6a4db94011d3	1546	{
sahilmgandhi	18:6a4db94011d3	1547	/* Set the SPI Rx DMA Half transfer complete callback */
sahilmgandhi	18:6a4db94011d3	1548	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
sahilmgandhi	18:6a4db94011d3	1549	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
sahilmgandhi	18:6a4db94011d3	1550	}
sahilmgandhi	18:6a4db94011d3	1551	else
sahilmgandhi	18:6a4db94011d3	1552	{
sahilmgandhi	18:6a4db94011d3	1553	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
sahilmgandhi	18:6a4db94011d3	1554	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
sahilmgandhi	18:6a4db94011d3	1555	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
sahilmgandhi	18:6a4db94011d3	1556	}
sahilmgandhi	18:6a4db94011d3	1557
sahilmgandhi	18:6a4db94011d3	1558	/* Set the DMA error callback */
sahilmgandhi	18:6a4db94011d3	1559	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
sahilmgandhi	18:6a4db94011d3	1560
sahilmgandhi	18:6a4db94011d3	1561	/* Set the DMA AbortCpltCallback */
sahilmgandhi	18:6a4db94011d3	1562	hspi->hdmarx->XferAbortCallback = NULL;
sahilmgandhi	18:6a4db94011d3	1563
sahilmgandhi	18:6a4db94011d3	1564	/* Enable the Rx DMA Stream */
sahilmgandhi	18:6a4db94011d3	1565	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
sahilmgandhi	18:6a4db94011d3	1566
sahilmgandhi	18:6a4db94011d3	1567	/* Enable Rx DMA Request */
sahilmgandhi	18:6a4db94011d3	1568	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi	18:6a4db94011d3	1569
sahilmgandhi	18:6a4db94011d3	1570	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
sahilmgandhi	18:6a4db94011d3	1571	is performed in DMA reception complete callback */
sahilmgandhi	18:6a4db94011d3	1572	hspi->hdmatx->XferHalfCpltCallback = NULL;
sahilmgandhi	18:6a4db94011d3	1573	hspi->hdmatx->XferCpltCallback = NULL;
sahilmgandhi	18:6a4db94011d3	1574	hspi->hdmatx->XferErrorCallback = NULL;
sahilmgandhi	18:6a4db94011d3	1575	hspi->hdmatx->XferAbortCallback = NULL;
sahilmgandhi	18:6a4db94011d3	1576
sahilmgandhi	18:6a4db94011d3	1577	/* Enable the Tx DMA Stream */
sahilmgandhi	18:6a4db94011d3	1578	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
sahilmgandhi	18:6a4db94011d3	1579
sahilmgandhi	18:6a4db94011d3	1580	/* Check if the SPI is already enabled */
sahilmgandhi	18:6a4db94011d3	1581	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi	18:6a4db94011d3	1582	{
sahilmgandhi	18:6a4db94011d3	1583	/* Enable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	1584	__HAL_SPI_ENABLE(hspi);
sahilmgandhi	18:6a4db94011d3	1585	}
sahilmgandhi	18:6a4db94011d3	1586	/* Enable the SPI Error Interrupt Bit */
sahilmgandhi	18:6a4db94011d3	1587	SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
sahilmgandhi	18:6a4db94011d3	1588
sahilmgandhi	18:6a4db94011d3	1589	/* Enable Tx DMA Request */
sahilmgandhi	18:6a4db94011d3	1590	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi	18:6a4db94011d3	1591
sahilmgandhi	18:6a4db94011d3	1592	error :
sahilmgandhi	18:6a4db94011d3	1593	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	1594	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	1595	return errorcode;
sahilmgandhi	18:6a4db94011d3	1596	}
sahilmgandhi	18:6a4db94011d3	1597
sahilmgandhi	18:6a4db94011d3	1598	/**
sahilmgandhi	18:6a4db94011d3	1599	* @brief Stop the DMA Transfer.
sahilmgandhi	18:6a4db94011d3	1600	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1601	* the configuration information for the specified SPI module.
sahilmgandhi	18:6a4db94011d3	1602	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1603	*/
sahilmgandhi	18:6a4db94011d3	1604	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1605	{
sahilmgandhi	18:6a4db94011d3	1606	/* The Lock is not implemented on this API to allow the user application
sahilmgandhi	18:6a4db94011d3	1607	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
sahilmgandhi	18:6a4db94011d3	1608	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
sahilmgandhi	18:6a4db94011d3	1609	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
sahilmgandhi	18:6a4db94011d3	1610	*/
sahilmgandhi	18:6a4db94011d3	1611
sahilmgandhi	18:6a4db94011d3	1612	/* Abort the SPI DMA tx Stream */
sahilmgandhi	18:6a4db94011d3	1613	if(hspi->hdmatx != NULL)
sahilmgandhi	18:6a4db94011d3	1614	{
sahilmgandhi	18:6a4db94011d3	1615	HAL_DMA_Abort(hspi->hdmatx);
sahilmgandhi	18:6a4db94011d3	1616	}
sahilmgandhi	18:6a4db94011d3	1617	/* Abort the SPI DMA rx Stream */
sahilmgandhi	18:6a4db94011d3	1618	if(hspi->hdmarx != NULL)
sahilmgandhi	18:6a4db94011d3	1619	{
sahilmgandhi	18:6a4db94011d3	1620	HAL_DMA_Abort(hspi->hdmarx);
sahilmgandhi	18:6a4db94011d3	1621	}
sahilmgandhi	18:6a4db94011d3	1622
sahilmgandhi	18:6a4db94011d3	1623	/* Disable the SPI DMA Tx & Rx requests */
sahilmgandhi	18:6a4db94011d3	1624	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
sahilmgandhi	18:6a4db94011d3	1625	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1626	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1627	}
sahilmgandhi	18:6a4db94011d3	1628
sahilmgandhi	18:6a4db94011d3	1629	/**
sahilmgandhi	18:6a4db94011d3	1630	* @brief Handle SPI interrupt request.
sahilmgandhi	18:6a4db94011d3	1631	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1632	* the configuration information for the specified SPI module.
sahilmgandhi	18:6a4db94011d3	1633	* @retval None
sahilmgandhi	18:6a4db94011d3	1634	*/
sahilmgandhi	18:6a4db94011d3	1635	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1636	{
sahilmgandhi	18:6a4db94011d3	1637	uint32_t itsource = hspi->Instance->CR2;
sahilmgandhi	18:6a4db94011d3	1638	uint32_t itflag = hspi->Instance->SR;
sahilmgandhi	18:6a4db94011d3	1639
sahilmgandhi	18:6a4db94011d3	1640	/* SPI in mode Receiver ----------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1641	if(((itflag & SPI_FLAG_OVR) == RESET) &&
sahilmgandhi	18:6a4db94011d3	1642	((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
sahilmgandhi	18:6a4db94011d3	1643	{
sahilmgandhi	18:6a4db94011d3	1644	hspi->RxISR(hspi);
sahilmgandhi	18:6a4db94011d3	1645	return;
sahilmgandhi	18:6a4db94011d3	1646	}
sahilmgandhi	18:6a4db94011d3	1647
sahilmgandhi	18:6a4db94011d3	1648	/* SPI in mode Transmitter -------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1649	if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
sahilmgandhi	18:6a4db94011d3	1650	{
sahilmgandhi	18:6a4db94011d3	1651	hspi->TxISR(hspi);
sahilmgandhi	18:6a4db94011d3	1652	return;
sahilmgandhi	18:6a4db94011d3	1653	}
sahilmgandhi	18:6a4db94011d3	1654
sahilmgandhi	18:6a4db94011d3	1655	/* SPI in Error Treatment --------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1656	if(((itflag & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
sahilmgandhi	18:6a4db94011d3	1657	{
sahilmgandhi	18:6a4db94011d3	1658	/* SPI Overrun error interrupt occurred ----------------------------------*/
sahilmgandhi	18:6a4db94011d3	1659	if((itflag & SPI_FLAG_OVR) != RESET)
sahilmgandhi	18:6a4db94011d3	1660	{
sahilmgandhi	18:6a4db94011d3	1661	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
sahilmgandhi	18:6a4db94011d3	1662	{
sahilmgandhi	18:6a4db94011d3	1663	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
sahilmgandhi	18:6a4db94011d3	1664	__HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	1665	}
sahilmgandhi	18:6a4db94011d3	1666	else
sahilmgandhi	18:6a4db94011d3	1667	{
sahilmgandhi	18:6a4db94011d3	1668	__HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	1669	return;
sahilmgandhi	18:6a4db94011d3	1670	}
sahilmgandhi	18:6a4db94011d3	1671	}
sahilmgandhi	18:6a4db94011d3	1672
sahilmgandhi	18:6a4db94011d3	1673	/* SPI Mode Fault error interrupt occurred -------------------------------*/
sahilmgandhi	18:6a4db94011d3	1674	if((itflag & SPI_FLAG_MODF) != RESET)
sahilmgandhi	18:6a4db94011d3	1675	{
sahilmgandhi	18:6a4db94011d3	1676	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
sahilmgandhi	18:6a4db94011d3	1677	__HAL_SPI_CLEAR_MODFFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	1678	}
sahilmgandhi	18:6a4db94011d3	1679
sahilmgandhi	18:6a4db94011d3	1680	/* SPI Frame error interrupt occurred ------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1681	if((itflag & SPI_FLAG_FRE) != RESET)
sahilmgandhi	18:6a4db94011d3	1682	{
sahilmgandhi	18:6a4db94011d3	1683	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
sahilmgandhi	18:6a4db94011d3	1684	__HAL_SPI_CLEAR_FREFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	1685	}
sahilmgandhi	18:6a4db94011d3	1686
sahilmgandhi	18:6a4db94011d3	1687	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	1688	{
sahilmgandhi	18:6a4db94011d3	1689	/* Disable all interrupts */
sahilmgandhi	18:6a4db94011d3	1690	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
sahilmgandhi	18:6a4db94011d3	1691
sahilmgandhi	18:6a4db94011d3	1692	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1693	/* Disable the SPI DMA requests if enabled */
sahilmgandhi	18:6a4db94011d3	1694	if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))\|\|(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
sahilmgandhi	18:6a4db94011d3	1695	{
sahilmgandhi	18:6a4db94011d3	1696	CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN));
sahilmgandhi	18:6a4db94011d3	1697
sahilmgandhi	18:6a4db94011d3	1698	/* Abort the SPI DMA Rx channel */
sahilmgandhi	18:6a4db94011d3	1699	if(hspi->hdmarx != NULL)
sahilmgandhi	18:6a4db94011d3	1700	{
sahilmgandhi	18:6a4db94011d3	1701	/* Set the SPI DMA Abort callback :
sahilmgandhi	18:6a4db94011d3	1702	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
sahilmgandhi	18:6a4db94011d3	1703	hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
sahilmgandhi	18:6a4db94011d3	1704	HAL_DMA_Abort_IT(hspi->hdmarx);
sahilmgandhi	18:6a4db94011d3	1705	}
sahilmgandhi	18:6a4db94011d3	1706	/* Abort the SPI DMA Tx channel */
sahilmgandhi	18:6a4db94011d3	1707	if(hspi->hdmatx != NULL)
sahilmgandhi	18:6a4db94011d3	1708	{
sahilmgandhi	18:6a4db94011d3	1709	/* Set the SPI DMA Abort callback :
sahilmgandhi	18:6a4db94011d3	1710	will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
sahilmgandhi	18:6a4db94011d3	1711	hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
sahilmgandhi	18:6a4db94011d3	1712	HAL_DMA_Abort_IT(hspi->hdmatx);
sahilmgandhi	18:6a4db94011d3	1713	}
sahilmgandhi	18:6a4db94011d3	1714	}
sahilmgandhi	18:6a4db94011d3	1715	else
sahilmgandhi	18:6a4db94011d3	1716	{
sahilmgandhi	18:6a4db94011d3	1717	/* Call user error callback */
sahilmgandhi	18:6a4db94011d3	1718	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	1719	}
sahilmgandhi	18:6a4db94011d3	1720	}
sahilmgandhi	18:6a4db94011d3	1721	return;
sahilmgandhi	18:6a4db94011d3	1722	}
sahilmgandhi	18:6a4db94011d3	1723	}
sahilmgandhi	18:6a4db94011d3	1724
sahilmgandhi	18:6a4db94011d3	1725	/**
sahilmgandhi	18:6a4db94011d3	1726	* @brief Tx Transfer completed callback.
sahilmgandhi	18:6a4db94011d3	1727	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1728	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1729	* @retval None
sahilmgandhi	18:6a4db94011d3	1730	*/
sahilmgandhi	18:6a4db94011d3	1731	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1732	{
sahilmgandhi	18:6a4db94011d3	1733	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1734	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	1735	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1736	the HAL_SPI_TxCpltCallback should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1737	*/
sahilmgandhi	18:6a4db94011d3	1738	}
sahilmgandhi	18:6a4db94011d3	1739
sahilmgandhi	18:6a4db94011d3	1740	/**
sahilmgandhi	18:6a4db94011d3	1741	* @brief Rx Transfer completed callback.
sahilmgandhi	18:6a4db94011d3	1742	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1743	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1744	* @retval None
sahilmgandhi	18:6a4db94011d3	1745	*/
sahilmgandhi	18:6a4db94011d3	1746	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1747	{
sahilmgandhi	18:6a4db94011d3	1748	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1749	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	1750	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1751	the HAL_SPI_RxCpltCallback should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1752	*/
sahilmgandhi	18:6a4db94011d3	1753	}
sahilmgandhi	18:6a4db94011d3	1754
sahilmgandhi	18:6a4db94011d3	1755	/**
sahilmgandhi	18:6a4db94011d3	1756	* @brief Tx and Rx Transfer completed callback.
sahilmgandhi	18:6a4db94011d3	1757	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1758	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1759	* @retval None
sahilmgandhi	18:6a4db94011d3	1760	*/
sahilmgandhi	18:6a4db94011d3	1761	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1762	{
sahilmgandhi	18:6a4db94011d3	1763	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1764	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	1765	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1766	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1767	*/
sahilmgandhi	18:6a4db94011d3	1768	}
sahilmgandhi	18:6a4db94011d3	1769
sahilmgandhi	18:6a4db94011d3	1770	/**
sahilmgandhi	18:6a4db94011d3	1771	* @brief Tx Half Transfer completed callback.
sahilmgandhi	18:6a4db94011d3	1772	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1773	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1774	* @retval None
sahilmgandhi	18:6a4db94011d3	1775	*/
sahilmgandhi	18:6a4db94011d3	1776	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1777	{
sahilmgandhi	18:6a4db94011d3	1778	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1779	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	1780	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1781	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1782	*/
sahilmgandhi	18:6a4db94011d3	1783	}
sahilmgandhi	18:6a4db94011d3	1784
sahilmgandhi	18:6a4db94011d3	1785	/**
sahilmgandhi	18:6a4db94011d3	1786	* @brief Rx Half Transfer completed callback.
sahilmgandhi	18:6a4db94011d3	1787	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1788	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1789	* @retval None
sahilmgandhi	18:6a4db94011d3	1790	*/
sahilmgandhi	18:6a4db94011d3	1791	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1792	{
sahilmgandhi	18:6a4db94011d3	1793	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1794	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	1795	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1796	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1797	*/
sahilmgandhi	18:6a4db94011d3	1798	}
sahilmgandhi	18:6a4db94011d3	1799
sahilmgandhi	18:6a4db94011d3	1800	/**
sahilmgandhi	18:6a4db94011d3	1801	* @brief Tx and Rx Half Transfer callback.
sahilmgandhi	18:6a4db94011d3	1802	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1803	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1804	* @retval None
sahilmgandhi	18:6a4db94011d3	1805	*/
sahilmgandhi	18:6a4db94011d3	1806	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1807	{
sahilmgandhi	18:6a4db94011d3	1808	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1809	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	1810	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1811	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1812	*/
sahilmgandhi	18:6a4db94011d3	1813	}
sahilmgandhi	18:6a4db94011d3	1814
sahilmgandhi	18:6a4db94011d3	1815	/**
sahilmgandhi	18:6a4db94011d3	1816	* @brief SPI error callback.
sahilmgandhi	18:6a4db94011d3	1817	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1818	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1819	* @retval None
sahilmgandhi	18:6a4db94011d3	1820	*/
sahilmgandhi	18:6a4db94011d3	1821	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1822	{
sahilmgandhi	18:6a4db94011d3	1823	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1824	UNUSED(hspi);
sahilmgandhi	18:6a4db94011d3	1825	/* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1826	the HAL_SPI_ErrorCallback should be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1827	*/
sahilmgandhi	18:6a4db94011d3	1828	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
sahilmgandhi	18:6a4db94011d3	1829	and user can use HAL_SPI_GetError() API to check the latest error occurred
sahilmgandhi	18:6a4db94011d3	1830	*/
sahilmgandhi	18:6a4db94011d3	1831	}
sahilmgandhi	18:6a4db94011d3	1832
sahilmgandhi	18:6a4db94011d3	1833	/**
sahilmgandhi	18:6a4db94011d3	1834	* @}
sahilmgandhi	18:6a4db94011d3	1835	*/
sahilmgandhi	18:6a4db94011d3	1836
sahilmgandhi	18:6a4db94011d3	1837	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
sahilmgandhi	18:6a4db94011d3	1838	* @brief SPI control functions
sahilmgandhi	18:6a4db94011d3	1839	*
sahilmgandhi	18:6a4db94011d3	1840	@verbatim
sahilmgandhi	18:6a4db94011d3	1841	===============================================================================
sahilmgandhi	18:6a4db94011d3	1842	##### Peripheral State and Errors functions #####
sahilmgandhi	18:6a4db94011d3	1843	===============================================================================
sahilmgandhi	18:6a4db94011d3	1844	[..]
sahilmgandhi	18:6a4db94011d3	1845	This subsection provides a set of functions allowing to control the SPI.
sahilmgandhi	18:6a4db94011d3	1846	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
sahilmgandhi	18:6a4db94011d3	1847	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
sahilmgandhi	18:6a4db94011d3	1848	@endverbatim
sahilmgandhi	18:6a4db94011d3	1849	* @{
sahilmgandhi	18:6a4db94011d3	1850	*/
sahilmgandhi	18:6a4db94011d3	1851
sahilmgandhi	18:6a4db94011d3	1852	/**
sahilmgandhi	18:6a4db94011d3	1853	* @brief Return the SPI handle state.
sahilmgandhi	18:6a4db94011d3	1854	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1855	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1856	* @retval SPI state
sahilmgandhi	18:6a4db94011d3	1857	*/
sahilmgandhi	18:6a4db94011d3	1858	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1859	{
sahilmgandhi	18:6a4db94011d3	1860	/* Return SPI handle state */
sahilmgandhi	18:6a4db94011d3	1861	return hspi->State;
sahilmgandhi	18:6a4db94011d3	1862	}
sahilmgandhi	18:6a4db94011d3	1863
sahilmgandhi	18:6a4db94011d3	1864	/**
sahilmgandhi	18:6a4db94011d3	1865	* @brief Return the SPI error code.
sahilmgandhi	18:6a4db94011d3	1866	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1867	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	1868	* @retval SPI error code in bitmap format
sahilmgandhi	18:6a4db94011d3	1869	*/
sahilmgandhi	18:6a4db94011d3	1870	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	1871	{
sahilmgandhi	18:6a4db94011d3	1872	/* Return SPI ErrorCode */
sahilmgandhi	18:6a4db94011d3	1873	return hspi->ErrorCode;
sahilmgandhi	18:6a4db94011d3	1874	}
sahilmgandhi	18:6a4db94011d3	1875
sahilmgandhi	18:6a4db94011d3	1876	/**
sahilmgandhi	18:6a4db94011d3	1877	* @}
sahilmgandhi	18:6a4db94011d3	1878	*/
sahilmgandhi	18:6a4db94011d3	1879
sahilmgandhi	18:6a4db94011d3	1880	/**
sahilmgandhi	18:6a4db94011d3	1881	* @}
sahilmgandhi	18:6a4db94011d3	1882	*/
sahilmgandhi	18:6a4db94011d3	1883
sahilmgandhi	18:6a4db94011d3	1884	/** @addtogroup SPI_Private_Functions
sahilmgandhi	18:6a4db94011d3	1885	* @brief Private functions
sahilmgandhi	18:6a4db94011d3	1886	* @{
sahilmgandhi	18:6a4db94011d3	1887	*/
sahilmgandhi	18:6a4db94011d3	1888
sahilmgandhi	18:6a4db94011d3	1889	/**
sahilmgandhi	18:6a4db94011d3	1890	* @brief DMA SPI transmit process complete callback.
sahilmgandhi	18:6a4db94011d3	1891	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1892	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	1893	* @retval None
sahilmgandhi	18:6a4db94011d3	1894	*/
sahilmgandhi	18:6a4db94011d3	1895	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	1896	{
sahilmgandhi	18:6a4db94011d3	1897	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	1898	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1899
sahilmgandhi	18:6a4db94011d3	1900	/* Init tickstart for timeout managment*/
sahilmgandhi	18:6a4db94011d3	1901	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1902
sahilmgandhi	18:6a4db94011d3	1903	/* DMA Normal Mode */
sahilmgandhi	18:6a4db94011d3	1904	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
sahilmgandhi	18:6a4db94011d3	1905	{
sahilmgandhi	18:6a4db94011d3	1906	/* Disable Tx DMA Request */
sahilmgandhi	18:6a4db94011d3	1907	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi	18:6a4db94011d3	1908
sahilmgandhi	18:6a4db94011d3	1909	/* Check the end of the transaction */
sahilmgandhi	18:6a4db94011d3	1910	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	1911	{
sahilmgandhi	18:6a4db94011d3	1912	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi	18:6a4db94011d3	1913	}
sahilmgandhi	18:6a4db94011d3	1914
sahilmgandhi	18:6a4db94011d3	1915	/* Clear overrun flag in 2 Lines communication mode because received data is not read */
sahilmgandhi	18:6a4db94011d3	1916	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi	18:6a4db94011d3	1917	{
sahilmgandhi	18:6a4db94011d3	1918	__HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	1919	}
sahilmgandhi	18:6a4db94011d3	1920
sahilmgandhi	18:6a4db94011d3	1921	hspi->TxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	1922	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1923
sahilmgandhi	18:6a4db94011d3	1924	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	1925	{
sahilmgandhi	18:6a4db94011d3	1926	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	1927	return;
sahilmgandhi	18:6a4db94011d3	1928	}
sahilmgandhi	18:6a4db94011d3	1929	}
sahilmgandhi	18:6a4db94011d3	1930	HAL_SPI_TxCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	1931	}
sahilmgandhi	18:6a4db94011d3	1932
sahilmgandhi	18:6a4db94011d3	1933	/**
sahilmgandhi	18:6a4db94011d3	1934	* @brief DMA SPI receive process complete callback.
sahilmgandhi	18:6a4db94011d3	1935	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	1936	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	1937	* @retval None
sahilmgandhi	18:6a4db94011d3	1938	*/
sahilmgandhi	18:6a4db94011d3	1939	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	1940	{
sahilmgandhi	18:6a4db94011d3	1941	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	1942	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1943	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1944	__IO uint16_t tmpreg = 0U;
sahilmgandhi	18:6a4db94011d3	1945
sahilmgandhi	18:6a4db94011d3	1946	/* Init tickstart for timeout management*/
sahilmgandhi	18:6a4db94011d3	1947	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1948	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1949
sahilmgandhi	18:6a4db94011d3	1950	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
sahilmgandhi	18:6a4db94011d3	1951	{
sahilmgandhi	18:6a4db94011d3	1952	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1953	/* CRC handling */
sahilmgandhi	18:6a4db94011d3	1954	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	1955	{
sahilmgandhi	18:6a4db94011d3	1956	/* Wait until RXNE flag */
sahilmgandhi	18:6a4db94011d3	1957	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	1958	{
sahilmgandhi	18:6a4db94011d3	1959	/* Error on the CRC reception */
sahilmgandhi	18:6a4db94011d3	1960	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	1961	}
sahilmgandhi	18:6a4db94011d3	1962	/* Read CRC */
sahilmgandhi	18:6a4db94011d3	1963	tmpreg = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	1964	/* To avoid GCC warning */
sahilmgandhi	18:6a4db94011d3	1965	UNUSED(tmpreg);
sahilmgandhi	18:6a4db94011d3	1966	}
sahilmgandhi	18:6a4db94011d3	1967	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1968
sahilmgandhi	18:6a4db94011d3	1969	/* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
sahilmgandhi	18:6a4db94011d3	1970	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
sahilmgandhi	18:6a4db94011d3	1971
sahilmgandhi	18:6a4db94011d3	1972	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
sahilmgandhi	18:6a4db94011d3	1973	{
sahilmgandhi	18:6a4db94011d3	1974	/* Disable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	1975	__HAL_SPI_DISABLE(hspi);
sahilmgandhi	18:6a4db94011d3	1976	}
sahilmgandhi	18:6a4db94011d3	1977
sahilmgandhi	18:6a4db94011d3	1978	hspi->RxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	1979	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1980
sahilmgandhi	18:6a4db94011d3	1981	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	1982	/* Check if CRC error occurred */
sahilmgandhi	18:6a4db94011d3	1983	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
sahilmgandhi	18:6a4db94011d3	1984	{
sahilmgandhi	18:6a4db94011d3	1985	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	1986	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	1987	}
sahilmgandhi	18:6a4db94011d3	1988	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	1989
sahilmgandhi	18:6a4db94011d3	1990	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	1991	{
sahilmgandhi	18:6a4db94011d3	1992	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	1993	return;
sahilmgandhi	18:6a4db94011d3	1994	}
sahilmgandhi	18:6a4db94011d3	1995	}
sahilmgandhi	18:6a4db94011d3	1996	HAL_SPI_RxCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	1997	}
sahilmgandhi	18:6a4db94011d3	1998
sahilmgandhi	18:6a4db94011d3	1999	/**
sahilmgandhi	18:6a4db94011d3	2000	* @brief DMA SPI transmit receive process complete callback.
sahilmgandhi	18:6a4db94011d3	2001	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2002	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	2003	* @retval None
sahilmgandhi	18:6a4db94011d3	2004	*/
sahilmgandhi	18:6a4db94011d3	2005	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	2006	{
sahilmgandhi	18:6a4db94011d3	2007	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	2008	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	2009	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2010	__IO int16_t tmpreg = 0U;
sahilmgandhi	18:6a4db94011d3	2011	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2012	/* Init tickstart for timeout management*/
sahilmgandhi	18:6a4db94011d3	2013	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2014
sahilmgandhi	18:6a4db94011d3	2015	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
sahilmgandhi	18:6a4db94011d3	2016	{
sahilmgandhi	18:6a4db94011d3	2017	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2018	/* CRC handling */
sahilmgandhi	18:6a4db94011d3	2019	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2020	{
sahilmgandhi	18:6a4db94011d3	2021	/* Wait the CRC data */
sahilmgandhi	18:6a4db94011d3	2022	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	2023	{
sahilmgandhi	18:6a4db94011d3	2024	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	2025	}
sahilmgandhi	18:6a4db94011d3	2026	/* Read CRC to Flush DR and RXNE flag */
sahilmgandhi	18:6a4db94011d3	2027	tmpreg = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	2028	/* To avoid GCC warning */
sahilmgandhi	18:6a4db94011d3	2029	UNUSED(tmpreg);
sahilmgandhi	18:6a4db94011d3	2030	}
sahilmgandhi	18:6a4db94011d3	2031	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2032	/* Check the end of the transaction */
sahilmgandhi	18:6a4db94011d3	2033	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	2034	{
sahilmgandhi	18:6a4db94011d3	2035	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi	18:6a4db94011d3	2036	}
sahilmgandhi	18:6a4db94011d3	2037
sahilmgandhi	18:6a4db94011d3	2038	/* Disable Rx/Tx DMA Request */
sahilmgandhi	18:6a4db94011d3	2039	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
sahilmgandhi	18:6a4db94011d3	2040
sahilmgandhi	18:6a4db94011d3	2041	hspi->TxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	2042	hspi->RxXferCount = 0U;
sahilmgandhi	18:6a4db94011d3	2043	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2044
sahilmgandhi	18:6a4db94011d3	2045	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2046	/* Check if CRC error occurred */
sahilmgandhi	18:6a4db94011d3	2047	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
sahilmgandhi	18:6a4db94011d3	2048	{
sahilmgandhi	18:6a4db94011d3	2049	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	2050	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	2051	}
sahilmgandhi	18:6a4db94011d3	2052	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2053
sahilmgandhi	18:6a4db94011d3	2054	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	2055	{
sahilmgandhi	18:6a4db94011d3	2056	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2057	return;
sahilmgandhi	18:6a4db94011d3	2058	}
sahilmgandhi	18:6a4db94011d3	2059	}
sahilmgandhi	18:6a4db94011d3	2060	HAL_SPI_TxRxCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2061	}
sahilmgandhi	18:6a4db94011d3	2062
sahilmgandhi	18:6a4db94011d3	2063	/**
sahilmgandhi	18:6a4db94011d3	2064	* @brief DMA SPI half transmit process complete callback.
sahilmgandhi	18:6a4db94011d3	2065	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2066	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	2067	* @retval None
sahilmgandhi	18:6a4db94011d3	2068	*/
sahilmgandhi	18:6a4db94011d3	2069	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	2070	{
sahilmgandhi	18:6a4db94011d3	2071	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	2072
sahilmgandhi	18:6a4db94011d3	2073	HAL_SPI_TxHalfCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2074	}
sahilmgandhi	18:6a4db94011d3	2075
sahilmgandhi	18:6a4db94011d3	2076	/**
sahilmgandhi	18:6a4db94011d3	2077	* @brief DMA SPI half receive process complete callback
sahilmgandhi	18:6a4db94011d3	2078	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2079	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	2080	* @retval None
sahilmgandhi	18:6a4db94011d3	2081	*/
sahilmgandhi	18:6a4db94011d3	2082	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	2083	{
sahilmgandhi	18:6a4db94011d3	2084	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	2085
sahilmgandhi	18:6a4db94011d3	2086	HAL_SPI_RxHalfCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2087	}
sahilmgandhi	18:6a4db94011d3	2088
sahilmgandhi	18:6a4db94011d3	2089	/**
sahilmgandhi	18:6a4db94011d3	2090	* @brief DMA SPI half transmit receive process complete callback.
sahilmgandhi	18:6a4db94011d3	2091	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2092	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	2093	* @retval None
sahilmgandhi	18:6a4db94011d3	2094	*/
sahilmgandhi	18:6a4db94011d3	2095	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	2096	{
sahilmgandhi	18:6a4db94011d3	2097	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	2098
sahilmgandhi	18:6a4db94011d3	2099	HAL_SPI_TxRxHalfCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2100	}
sahilmgandhi	18:6a4db94011d3	2101
sahilmgandhi	18:6a4db94011d3	2102	/**
sahilmgandhi	18:6a4db94011d3	2103	* @brief DMA SPI communication error callback.
sahilmgandhi	18:6a4db94011d3	2104	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2105	* the configuration information for the specified DMA module.
sahilmgandhi	18:6a4db94011d3	2106	* @retval None
sahilmgandhi	18:6a4db94011d3	2107	*/
sahilmgandhi	18:6a4db94011d3	2108	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	2109	{
sahilmgandhi	18:6a4db94011d3	2110	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	2111
sahilmgandhi	18:6a4db94011d3	2112	/* Stop the disable DMA transfer on SPI side */
sahilmgandhi	18:6a4db94011d3	2113	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
sahilmgandhi	18:6a4db94011d3	2114
sahilmgandhi	18:6a4db94011d3	2115	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
sahilmgandhi	18:6a4db94011d3	2116	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2117	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2118	}
sahilmgandhi	18:6a4db94011d3	2119
sahilmgandhi	18:6a4db94011d3	2120	/**
sahilmgandhi	18:6a4db94011d3	2121	* @brief DMA SPI communication abort callback, when initiated by HAL services on Error
sahilmgandhi	18:6a4db94011d3	2122	* (To be called at end of DMA Abort procedure following error occurrence).
sahilmgandhi	18:6a4db94011d3	2123	* @param hdma DMA handle.
sahilmgandhi	18:6a4db94011d3	2124	* @retval None
sahilmgandhi	18:6a4db94011d3	2125	*/
sahilmgandhi	18:6a4db94011d3	2126	static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
sahilmgandhi	18:6a4db94011d3	2127	{
sahilmgandhi	18:6a4db94011d3	2128	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi	18:6a4db94011d3	2129	hspi->RxXferCount = 0;
sahilmgandhi	18:6a4db94011d3	2130	hspi->TxXferCount = 0;
sahilmgandhi	18:6a4db94011d3	2131
sahilmgandhi	18:6a4db94011d3	2132	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2133	}
sahilmgandhi	18:6a4db94011d3	2134
sahilmgandhi	18:6a4db94011d3	2135	/**
sahilmgandhi	18:6a4db94011d3	2136	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi	18:6a4db94011d3	2137	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2138	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2139	* @retval None
sahilmgandhi	18:6a4db94011d3	2140	*/
sahilmgandhi	18:6a4db94011d3	2141	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2142	{
sahilmgandhi	18:6a4db94011d3	2143	/* Receive data in 8bit mode */
sahilmgandhi	18:6a4db94011d3	2144	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
sahilmgandhi	18:6a4db94011d3	2145	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	2146
sahilmgandhi	18:6a4db94011d3	2147	/* check end of the reception */
sahilmgandhi	18:6a4db94011d3	2148	if(hspi->RxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2149	{
sahilmgandhi	18:6a4db94011d3	2150	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2151	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2152	{
sahilmgandhi	18:6a4db94011d3	2153	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
sahilmgandhi	18:6a4db94011d3	2154	return;
sahilmgandhi	18:6a4db94011d3	2155	}
sahilmgandhi	18:6a4db94011d3	2156	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2157
sahilmgandhi	18:6a4db94011d3	2158	/* Disable RXNE interrupt */
sahilmgandhi	18:6a4db94011d3	2159	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	2160
sahilmgandhi	18:6a4db94011d3	2161	if(hspi->TxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2162	{
sahilmgandhi	18:6a4db94011d3	2163	SPI_CloseRxTx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2164	}
sahilmgandhi	18:6a4db94011d3	2165	}
sahilmgandhi	18:6a4db94011d3	2166	}
sahilmgandhi	18:6a4db94011d3	2167
sahilmgandhi	18:6a4db94011d3	2168	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2169	/**
sahilmgandhi	18:6a4db94011d3	2170	* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi	18:6a4db94011d3	2171	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2172	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2173	* @retval None
sahilmgandhi	18:6a4db94011d3	2174	*/
sahilmgandhi	18:6a4db94011d3	2175	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2176	{
sahilmgandhi	18:6a4db94011d3	2177	__IO uint8_t tmpreg = 0U;
sahilmgandhi	18:6a4db94011d3	2178
sahilmgandhi	18:6a4db94011d3	2179	/* Read data register to flush CRC */
sahilmgandhi	18:6a4db94011d3	2180	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
sahilmgandhi	18:6a4db94011d3	2181
sahilmgandhi	18:6a4db94011d3	2182	/* To avoid GCC warning */
sahilmgandhi	18:6a4db94011d3	2183
sahilmgandhi	18:6a4db94011d3	2184	UNUSED(tmpreg);
sahilmgandhi	18:6a4db94011d3	2185
sahilmgandhi	18:6a4db94011d3	2186	/* Disable RXNE interrupt */
sahilmgandhi	18:6a4db94011d3	2187	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	2188
sahilmgandhi	18:6a4db94011d3	2189	if(hspi->TxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2190	{
sahilmgandhi	18:6a4db94011d3	2191	SPI_CloseRxTx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2192	}
sahilmgandhi	18:6a4db94011d3	2193	}
sahilmgandhi	18:6a4db94011d3	2194	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2195
sahilmgandhi	18:6a4db94011d3	2196	/**
sahilmgandhi	18:6a4db94011d3	2197	* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi	18:6a4db94011d3	2198	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2199	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2200	* @retval None
sahilmgandhi	18:6a4db94011d3	2201	*/
sahilmgandhi	18:6a4db94011d3	2202	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2203	{
sahilmgandhi	18:6a4db94011d3	2204	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
sahilmgandhi	18:6a4db94011d3	2205	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	2206
sahilmgandhi	18:6a4db94011d3	2207	/* check the end of the transmission */
sahilmgandhi	18:6a4db94011d3	2208	if(hspi->TxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2209	{
sahilmgandhi	18:6a4db94011d3	2210	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2211	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2212	{
sahilmgandhi	18:6a4db94011d3	2213	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	2214	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
sahilmgandhi	18:6a4db94011d3	2215	return;
sahilmgandhi	18:6a4db94011d3	2216	}
sahilmgandhi	18:6a4db94011d3	2217	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2218
sahilmgandhi	18:6a4db94011d3	2219	/* Disable TXE interrupt */
sahilmgandhi	18:6a4db94011d3	2220	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
sahilmgandhi	18:6a4db94011d3	2221
sahilmgandhi	18:6a4db94011d3	2222	if(hspi->RxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2223	{
sahilmgandhi	18:6a4db94011d3	2224	SPI_CloseRxTx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2225	}
sahilmgandhi	18:6a4db94011d3	2226	}
sahilmgandhi	18:6a4db94011d3	2227	}
sahilmgandhi	18:6a4db94011d3	2228
sahilmgandhi	18:6a4db94011d3	2229	/**
sahilmgandhi	18:6a4db94011d3	2230	* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi	18:6a4db94011d3	2231	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2232	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2233	* @retval None
sahilmgandhi	18:6a4db94011d3	2234	*/
sahilmgandhi	18:6a4db94011d3	2235	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2236	{
sahilmgandhi	18:6a4db94011d3	2237	/* Receive data in 16 Bit mode */
sahilmgandhi	18:6a4db94011d3	2238	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	2239	hspi->pRxBuffPtr += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	2240	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	2241
sahilmgandhi	18:6a4db94011d3	2242	if(hspi->RxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2243	{
sahilmgandhi	18:6a4db94011d3	2244	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2245	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2246	{
sahilmgandhi	18:6a4db94011d3	2247	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
sahilmgandhi	18:6a4db94011d3	2248	return;
sahilmgandhi	18:6a4db94011d3	2249	}
sahilmgandhi	18:6a4db94011d3	2250	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2251
sahilmgandhi	18:6a4db94011d3	2252	/* Disable RXNE interrupt */
sahilmgandhi	18:6a4db94011d3	2253	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
sahilmgandhi	18:6a4db94011d3	2254
sahilmgandhi	18:6a4db94011d3	2255	if(hspi->TxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2256	{
sahilmgandhi	18:6a4db94011d3	2257	SPI_CloseRxTx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2258	}
sahilmgandhi	18:6a4db94011d3	2259	}
sahilmgandhi	18:6a4db94011d3	2260	}
sahilmgandhi	18:6a4db94011d3	2261
sahilmgandhi	18:6a4db94011d3	2262	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2263	/**
sahilmgandhi	18:6a4db94011d3	2264	* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
sahilmgandhi	18:6a4db94011d3	2265	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2266	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2267	* @retval None
sahilmgandhi	18:6a4db94011d3	2268	*/
sahilmgandhi	18:6a4db94011d3	2269	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2270	{
sahilmgandhi	18:6a4db94011d3	2271	/* Receive data in 16 Bit mode */
sahilmgandhi	18:6a4db94011d3	2272	__IO uint16_t tmpreg = 0U;
sahilmgandhi	18:6a4db94011d3	2273
sahilmgandhi	18:6a4db94011d3	2274	/* Read data register to flush CRC */
sahilmgandhi	18:6a4db94011d3	2275	tmpreg = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	2276
sahilmgandhi	18:6a4db94011d3	2277	/* To avoid GCC warning */
sahilmgandhi	18:6a4db94011d3	2278	UNUSED(tmpreg);
sahilmgandhi	18:6a4db94011d3	2279
sahilmgandhi	18:6a4db94011d3	2280	/* Disable RXNE interrupt */
sahilmgandhi	18:6a4db94011d3	2281	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
sahilmgandhi	18:6a4db94011d3	2282
sahilmgandhi	18:6a4db94011d3	2283	SPI_CloseRxTx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2284	}
sahilmgandhi	18:6a4db94011d3	2285	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2286
sahilmgandhi	18:6a4db94011d3	2287	/**
sahilmgandhi	18:6a4db94011d3	2288	* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi	18:6a4db94011d3	2289	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2290	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2291	* @retval None
sahilmgandhi	18:6a4db94011d3	2292	*/
sahilmgandhi	18:6a4db94011d3	2293	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2294	{
sahilmgandhi	18:6a4db94011d3	2295	/* Transmit data in 16 Bit mode */
sahilmgandhi	18:6a4db94011d3	2296	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
sahilmgandhi	18:6a4db94011d3	2297	hspi->pTxBuffPtr += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	2298	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	2299
sahilmgandhi	18:6a4db94011d3	2300	/* Enable CRC Transmission */
sahilmgandhi	18:6a4db94011d3	2301	if(hspi->TxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2302	{
sahilmgandhi	18:6a4db94011d3	2303	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2304	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2305	{
sahilmgandhi	18:6a4db94011d3	2306	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	2307	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
sahilmgandhi	18:6a4db94011d3	2308	return;
sahilmgandhi	18:6a4db94011d3	2309	}
sahilmgandhi	18:6a4db94011d3	2310	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2311
sahilmgandhi	18:6a4db94011d3	2312	/* Disable TXE interrupt */
sahilmgandhi	18:6a4db94011d3	2313	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
sahilmgandhi	18:6a4db94011d3	2314
sahilmgandhi	18:6a4db94011d3	2315	if(hspi->RxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2316	{
sahilmgandhi	18:6a4db94011d3	2317	SPI_CloseRxTx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2318	}
sahilmgandhi	18:6a4db94011d3	2319	}
sahilmgandhi	18:6a4db94011d3	2320	}
sahilmgandhi	18:6a4db94011d3	2321
sahilmgandhi	18:6a4db94011d3	2322	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2323	/**
sahilmgandhi	18:6a4db94011d3	2324	* @brief Manage the CRC 8-bit receive in Interrupt context.
sahilmgandhi	18:6a4db94011d3	2325	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2326	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2327	* @retval None
sahilmgandhi	18:6a4db94011d3	2328	*/
sahilmgandhi	18:6a4db94011d3	2329	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2330	{
sahilmgandhi	18:6a4db94011d3	2331	__IO uint8_t tmpreg = 0U;
sahilmgandhi	18:6a4db94011d3	2332
sahilmgandhi	18:6a4db94011d3	2333	/* Read data register to flush CRC */
sahilmgandhi	18:6a4db94011d3	2334	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
sahilmgandhi	18:6a4db94011d3	2335
sahilmgandhi	18:6a4db94011d3	2336	/* To avoid GCC warning */
sahilmgandhi	18:6a4db94011d3	2337	UNUSED(tmpreg);
sahilmgandhi	18:6a4db94011d3	2338
sahilmgandhi	18:6a4db94011d3	2339	SPI_CloseRx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2340	}
sahilmgandhi	18:6a4db94011d3	2341	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2342
sahilmgandhi	18:6a4db94011d3	2343	/**
sahilmgandhi	18:6a4db94011d3	2344	* @brief Manage the receive 8-bit in Interrupt context.
sahilmgandhi	18:6a4db94011d3	2345	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2346	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2347	* @retval None
sahilmgandhi	18:6a4db94011d3	2348	*/
sahilmgandhi	18:6a4db94011d3	2349	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2350	{
sahilmgandhi	18:6a4db94011d3	2351	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
sahilmgandhi	18:6a4db94011d3	2352	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	2353
sahilmgandhi	18:6a4db94011d3	2354	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2355	/* Enable CRC Transmission */
sahilmgandhi	18:6a4db94011d3	2356	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi	18:6a4db94011d3	2357	{
sahilmgandhi	18:6a4db94011d3	2358	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	2359	}
sahilmgandhi	18:6a4db94011d3	2360	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2361
sahilmgandhi	18:6a4db94011d3	2362	if(hspi->RxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2363	{
sahilmgandhi	18:6a4db94011d3	2364	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2365	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2366	{
sahilmgandhi	18:6a4db94011d3	2367	hspi->RxISR = SPI_RxISR_8BITCRC;
sahilmgandhi	18:6a4db94011d3	2368	return;
sahilmgandhi	18:6a4db94011d3	2369	}
sahilmgandhi	18:6a4db94011d3	2370	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2371	SPI_CloseRx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2372	}
sahilmgandhi	18:6a4db94011d3	2373	}
sahilmgandhi	18:6a4db94011d3	2374
sahilmgandhi	18:6a4db94011d3	2375	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2376	/**
sahilmgandhi	18:6a4db94011d3	2377	* @brief Manage the CRC 16-bit receive in Interrupt context.
sahilmgandhi	18:6a4db94011d3	2378	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2379	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2380	* @retval None
sahilmgandhi	18:6a4db94011d3	2381	*/
sahilmgandhi	18:6a4db94011d3	2382	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2383	{
sahilmgandhi	18:6a4db94011d3	2384	__IO uint16_t tmpreg = 0U;
sahilmgandhi	18:6a4db94011d3	2385
sahilmgandhi	18:6a4db94011d3	2386	/* Read data register to flush CRC */
sahilmgandhi	18:6a4db94011d3	2387	tmpreg = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	2388
sahilmgandhi	18:6a4db94011d3	2389	/* To avoid GCC warning */
sahilmgandhi	18:6a4db94011d3	2390	UNUSED(tmpreg);
sahilmgandhi	18:6a4db94011d3	2391
sahilmgandhi	18:6a4db94011d3	2392	/* Disable RXNE and ERR interrupt */
sahilmgandhi	18:6a4db94011d3	2393	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	2394
sahilmgandhi	18:6a4db94011d3	2395	SPI_CloseRx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2396	}
sahilmgandhi	18:6a4db94011d3	2397	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2398
sahilmgandhi	18:6a4db94011d3	2399	/**
sahilmgandhi	18:6a4db94011d3	2400	* @brief Manage the 16-bit receive in Interrupt context.
sahilmgandhi	18:6a4db94011d3	2401	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2402	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2403	* @retval None
sahilmgandhi	18:6a4db94011d3	2404	*/
sahilmgandhi	18:6a4db94011d3	2405	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2406	{
sahilmgandhi	18:6a4db94011d3	2407	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi	18:6a4db94011d3	2408	hspi->pRxBuffPtr += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	2409	hspi->RxXferCount--;
sahilmgandhi	18:6a4db94011d3	2410
sahilmgandhi	18:6a4db94011d3	2411	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2412	/* Enable CRC Transmission */
sahilmgandhi	18:6a4db94011d3	2413	if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi	18:6a4db94011d3	2414	{
sahilmgandhi	18:6a4db94011d3	2415	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	2416	}
sahilmgandhi	18:6a4db94011d3	2417	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2418
sahilmgandhi	18:6a4db94011d3	2419	if(hspi->RxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2420	{
sahilmgandhi	18:6a4db94011d3	2421	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2422	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2423	{
sahilmgandhi	18:6a4db94011d3	2424	hspi->RxISR = SPI_RxISR_16BITCRC;
sahilmgandhi	18:6a4db94011d3	2425	return;
sahilmgandhi	18:6a4db94011d3	2426	}
sahilmgandhi	18:6a4db94011d3	2427	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2428	SPI_CloseRx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2429	}
sahilmgandhi	18:6a4db94011d3	2430	}
sahilmgandhi	18:6a4db94011d3	2431
sahilmgandhi	18:6a4db94011d3	2432	/**
sahilmgandhi	18:6a4db94011d3	2433	* @brief Handle the data 8-bit transmit in Interrupt mode.
sahilmgandhi	18:6a4db94011d3	2434	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2435	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2436	* @retval None
sahilmgandhi	18:6a4db94011d3	2437	*/
sahilmgandhi	18:6a4db94011d3	2438	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2439	{
sahilmgandhi	18:6a4db94011d3	2440	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
sahilmgandhi	18:6a4db94011d3	2441	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	2442
sahilmgandhi	18:6a4db94011d3	2443	if(hspi->TxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2444	{
sahilmgandhi	18:6a4db94011d3	2445	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2446	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2447	{
sahilmgandhi	18:6a4db94011d3	2448	/* Enable CRC Transmission */
sahilmgandhi	18:6a4db94011d3	2449	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	2450	}
sahilmgandhi	18:6a4db94011d3	2451	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2452	SPI_CloseTx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2453	}
sahilmgandhi	18:6a4db94011d3	2454	}
sahilmgandhi	18:6a4db94011d3	2455
sahilmgandhi	18:6a4db94011d3	2456	/**
sahilmgandhi	18:6a4db94011d3	2457	* @brief Handle the data 16-bit transmit in Interrupt mode.
sahilmgandhi	18:6a4db94011d3	2458	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2459	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2460	* @retval None
sahilmgandhi	18:6a4db94011d3	2461	*/
sahilmgandhi	18:6a4db94011d3	2462	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2463	{
sahilmgandhi	18:6a4db94011d3	2464	/* Transmit data in 16 Bit mode */
sahilmgandhi	18:6a4db94011d3	2465	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
sahilmgandhi	18:6a4db94011d3	2466	hspi->pTxBuffPtr += sizeof(uint16_t);
sahilmgandhi	18:6a4db94011d3	2467	hspi->TxXferCount--;
sahilmgandhi	18:6a4db94011d3	2468
sahilmgandhi	18:6a4db94011d3	2469	if(hspi->TxXferCount == 0U)
sahilmgandhi	18:6a4db94011d3	2470	{
sahilmgandhi	18:6a4db94011d3	2471	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2472	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2473	{
sahilmgandhi	18:6a4db94011d3	2474	/* Enable CRC Transmission */
sahilmgandhi	18:6a4db94011d3	2475	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi	18:6a4db94011d3	2476	}
sahilmgandhi	18:6a4db94011d3	2477	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2478	SPI_CloseTx_ISR(hspi);
sahilmgandhi	18:6a4db94011d3	2479	}
sahilmgandhi	18:6a4db94011d3	2480	}
sahilmgandhi	18:6a4db94011d3	2481
sahilmgandhi	18:6a4db94011d3	2482	/**
sahilmgandhi	18:6a4db94011d3	2483	* @brief Handle SPI Communication Timeout.
sahilmgandhi	18:6a4db94011d3	2484	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2485	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2486	* @param Flag: SPI flag to check
sahilmgandhi	18:6a4db94011d3	2487	* @param State: flag state to check
sahilmgandhi	18:6a4db94011d3	2488	* @param Timeout: Timeout duration
sahilmgandhi	18:6a4db94011d3	2489	* @param Tickstart: tick start value
sahilmgandhi	18:6a4db94011d3	2490	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2491	*/
sahilmgandhi	18:6a4db94011d3	2492	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
sahilmgandhi	18:6a4db94011d3	2493	{
sahilmgandhi	18:6a4db94011d3	2494	while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)
sahilmgandhi	18:6a4db94011d3	2495	{
sahilmgandhi	18:6a4db94011d3	2496	if(Timeout != HAL_MAX_DELAY)
sahilmgandhi	18:6a4db94011d3	2497	{
sahilmgandhi	18:6a4db94011d3	2498	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) >= Timeout))
sahilmgandhi	18:6a4db94011d3	2499	{
sahilmgandhi	18:6a4db94011d3	2500	/* Disable the SPI and reset the CRC: the CRC value should be cleared
sahilmgandhi	18:6a4db94011d3	2501	on both master and slave sides in order to resynchronize the master
sahilmgandhi	18:6a4db94011d3	2502	and slave for their respective CRC calculation */
sahilmgandhi	18:6a4db94011d3	2503
sahilmgandhi	18:6a4db94011d3	2504	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
sahilmgandhi	18:6a4db94011d3	2505	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	2506
sahilmgandhi	18:6a4db94011d3	2507	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
sahilmgandhi	18:6a4db94011d3	2508	{
sahilmgandhi	18:6a4db94011d3	2509	/* Disable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	2510	__HAL_SPI_DISABLE(hspi);
sahilmgandhi	18:6a4db94011d3	2511	}
sahilmgandhi	18:6a4db94011d3	2512
sahilmgandhi	18:6a4db94011d3	2513	/* Reset CRC Calculation */
sahilmgandhi	18:6a4db94011d3	2514	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi	18:6a4db94011d3	2515	{
sahilmgandhi	18:6a4db94011d3	2516	SPI_RESET_CRC(hspi);
sahilmgandhi	18:6a4db94011d3	2517	}
sahilmgandhi	18:6a4db94011d3	2518
sahilmgandhi	18:6a4db94011d3	2519	hspi->State= HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2520
sahilmgandhi	18:6a4db94011d3	2521	/* Process Unlocked */
sahilmgandhi	18:6a4db94011d3	2522	__HAL_UNLOCK(hspi);
sahilmgandhi	18:6a4db94011d3	2523
sahilmgandhi	18:6a4db94011d3	2524	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2525	}
sahilmgandhi	18:6a4db94011d3	2526	}
sahilmgandhi	18:6a4db94011d3	2527	}
sahilmgandhi	18:6a4db94011d3	2528
sahilmgandhi	18:6a4db94011d3	2529	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2530	}
sahilmgandhi	18:6a4db94011d3	2531	/**
sahilmgandhi	18:6a4db94011d3	2532	* @brief Handle to check BSY flag before start a new transaction.
sahilmgandhi	18:6a4db94011d3	2533	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2534	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2535	* @param Timeout: Timeout duration
sahilmgandhi	18:6a4db94011d3	2536	* @param Tickstart: tick start value
sahilmgandhi	18:6a4db94011d3	2537	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2538	*/
sahilmgandhi	18:6a4db94011d3	2539	static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
sahilmgandhi	18:6a4db94011d3	2540	{
sahilmgandhi	18:6a4db94011d3	2541	/* Control the BSY flag */
sahilmgandhi	18:6a4db94011d3	2542	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	2543	{
sahilmgandhi	18:6a4db94011d3	2544	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi	18:6a4db94011d3	2545	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2546	}
sahilmgandhi	18:6a4db94011d3	2547	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2548	}
sahilmgandhi	18:6a4db94011d3	2549
sahilmgandhi	18:6a4db94011d3	2550	/**
sahilmgandhi	18:6a4db94011d3	2551	* @brief Handle the end of the RXTX transaction.
sahilmgandhi	18:6a4db94011d3	2552	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2553	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2554	* @retval None
sahilmgandhi	18:6a4db94011d3	2555	*/
sahilmgandhi	18:6a4db94011d3	2556	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2557	{
sahilmgandhi	18:6a4db94011d3	2558	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	2559	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
sahilmgandhi	18:6a4db94011d3	2560	/* Init tickstart for timeout managment*/
sahilmgandhi	18:6a4db94011d3	2561	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2562
sahilmgandhi	18:6a4db94011d3	2563	/* Disable ERR interrupt */
sahilmgandhi	18:6a4db94011d3	2564	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
sahilmgandhi	18:6a4db94011d3	2565
sahilmgandhi	18:6a4db94011d3	2566	/* Wait until TXE flag is set */
sahilmgandhi	18:6a4db94011d3	2567	do
sahilmgandhi	18:6a4db94011d3	2568	{
sahilmgandhi	18:6a4db94011d3	2569	if(count-- == 0)
sahilmgandhi	18:6a4db94011d3	2570	{
sahilmgandhi	18:6a4db94011d3	2571	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi	18:6a4db94011d3	2572	break;
sahilmgandhi	18:6a4db94011d3	2573	}
sahilmgandhi	18:6a4db94011d3	2574	}
sahilmgandhi	18:6a4db94011d3	2575	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
sahilmgandhi	18:6a4db94011d3	2576
sahilmgandhi	18:6a4db94011d3	2577	/* Check the end of the transaction */
sahilmgandhi	18:6a4db94011d3	2578	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
sahilmgandhi	18:6a4db94011d3	2579	{
sahilmgandhi	18:6a4db94011d3	2580	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi	18:6a4db94011d3	2581	}
sahilmgandhi	18:6a4db94011d3	2582
sahilmgandhi	18:6a4db94011d3	2583	/* Clear overrun flag in 2 Lines communication mode because received is not read */
sahilmgandhi	18:6a4db94011d3	2584	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi	18:6a4db94011d3	2585	{
sahilmgandhi	18:6a4db94011d3	2586	__HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	2587	}
sahilmgandhi	18:6a4db94011d3	2588
sahilmgandhi	18:6a4db94011d3	2589	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2590	/* Check if CRC error occurred */
sahilmgandhi	18:6a4db94011d3	2591	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
sahilmgandhi	18:6a4db94011d3	2592	{
sahilmgandhi	18:6a4db94011d3	2593	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2594	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	2595	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	2596	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2597	}
sahilmgandhi	18:6a4db94011d3	2598	else
sahilmgandhi	18:6a4db94011d3	2599	{
sahilmgandhi	18:6a4db94011d3	2600	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2601	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	2602	{
sahilmgandhi	18:6a4db94011d3	2603	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
sahilmgandhi	18:6a4db94011d3	2604	{
sahilmgandhi	18:6a4db94011d3	2605	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2606	HAL_SPI_RxCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2607	}
sahilmgandhi	18:6a4db94011d3	2608	else
sahilmgandhi	18:6a4db94011d3	2609	{
sahilmgandhi	18:6a4db94011d3	2610	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2611	HAL_SPI_TxRxCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2612	}
sahilmgandhi	18:6a4db94011d3	2613	}
sahilmgandhi	18:6a4db94011d3	2614	else
sahilmgandhi	18:6a4db94011d3	2615	{
sahilmgandhi	18:6a4db94011d3	2616	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2617	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2618	}
sahilmgandhi	18:6a4db94011d3	2619	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2620	}
sahilmgandhi	18:6a4db94011d3	2621	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2622	}
sahilmgandhi	18:6a4db94011d3	2623
sahilmgandhi	18:6a4db94011d3	2624	/**
sahilmgandhi	18:6a4db94011d3	2625	* @brief Handle the end of the RX transaction.
sahilmgandhi	18:6a4db94011d3	2626	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2627	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2628	* @retval None
sahilmgandhi	18:6a4db94011d3	2629	*/
sahilmgandhi	18:6a4db94011d3	2630	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2631	{
sahilmgandhi	18:6a4db94011d3	2632	/* Disable RXNE and ERR interrupt */
sahilmgandhi	18:6a4db94011d3	2633	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	2634
sahilmgandhi	18:6a4db94011d3	2635	/* Check the end of the transaction */
sahilmgandhi	18:6a4db94011d3	2636	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
sahilmgandhi	18:6a4db94011d3	2637	{
sahilmgandhi	18:6a4db94011d3	2638	/* Disable SPI peripheral */
sahilmgandhi	18:6a4db94011d3	2639	__HAL_SPI_DISABLE(hspi);
sahilmgandhi	18:6a4db94011d3	2640	}
sahilmgandhi	18:6a4db94011d3	2641
sahilmgandhi	18:6a4db94011d3	2642	/* Clear overrun flag in 2 Lines communication mode because received is not read */
sahilmgandhi	18:6a4db94011d3	2643	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi	18:6a4db94011d3	2644	{
sahilmgandhi	18:6a4db94011d3	2645	__HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	2646	}
sahilmgandhi	18:6a4db94011d3	2647	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2648
sahilmgandhi	18:6a4db94011d3	2649	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2650	/* Check if CRC error occurred */
sahilmgandhi	18:6a4db94011d3	2651	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
sahilmgandhi	18:6a4db94011d3	2652	{
sahilmgandhi	18:6a4db94011d3	2653	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi	18:6a4db94011d3	2654	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	2655	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2656	}
sahilmgandhi	18:6a4db94011d3	2657	else
sahilmgandhi	18:6a4db94011d3	2658	{
sahilmgandhi	18:6a4db94011d3	2659	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2660	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	2661	{
sahilmgandhi	18:6a4db94011d3	2662	HAL_SPI_RxCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2663	}
sahilmgandhi	18:6a4db94011d3	2664	else
sahilmgandhi	18:6a4db94011d3	2665	{
sahilmgandhi	18:6a4db94011d3	2666	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2667	}
sahilmgandhi	18:6a4db94011d3	2668	#if (USE_SPI_CRC != 0U)
sahilmgandhi	18:6a4db94011d3	2669	}
sahilmgandhi	18:6a4db94011d3	2670	#endif /* USE_SPI_CRC */
sahilmgandhi	18:6a4db94011d3	2671	}
sahilmgandhi	18:6a4db94011d3	2672
sahilmgandhi	18:6a4db94011d3	2673	/**
sahilmgandhi	18:6a4db94011d3	2674	* @brief Handle the end of the TX transaction.
sahilmgandhi	18:6a4db94011d3	2675	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi	18:6a4db94011d3	2676	* the configuration information for SPI module.
sahilmgandhi	18:6a4db94011d3	2677	* @retval None
sahilmgandhi	18:6a4db94011d3	2678	*/
sahilmgandhi	18:6a4db94011d3	2679	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
sahilmgandhi	18:6a4db94011d3	2680	{
sahilmgandhi	18:6a4db94011d3	2681	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	2682	__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
sahilmgandhi	18:6a4db94011d3	2683
sahilmgandhi	18:6a4db94011d3	2684	/* Init tickstart for timeout management*/
sahilmgandhi	18:6a4db94011d3	2685	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2686
sahilmgandhi	18:6a4db94011d3	2687	/* Wait until TXE flag is set */
sahilmgandhi	18:6a4db94011d3	2688	do
sahilmgandhi	18:6a4db94011d3	2689	{
sahilmgandhi	18:6a4db94011d3	2690	if(count-- == 0)
sahilmgandhi	18:6a4db94011d3	2691	{
sahilmgandhi	18:6a4db94011d3	2692	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi	18:6a4db94011d3	2693	break;
sahilmgandhi	18:6a4db94011d3	2694	}
sahilmgandhi	18:6a4db94011d3	2695	}
sahilmgandhi	18:6a4db94011d3	2696	while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
sahilmgandhi	18:6a4db94011d3	2697
sahilmgandhi	18:6a4db94011d3	2698	/* Disable TXE and ERR interrupt */
sahilmgandhi	18:6a4db94011d3	2699	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
sahilmgandhi	18:6a4db94011d3	2700
sahilmgandhi	18:6a4db94011d3	2701	/* Check Busy flag */
sahilmgandhi	18:6a4db94011d3	2702	if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
sahilmgandhi	18:6a4db94011d3	2703	{
sahilmgandhi	18:6a4db94011d3	2704	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi	18:6a4db94011d3	2705	}
sahilmgandhi	18:6a4db94011d3	2706
sahilmgandhi	18:6a4db94011d3	2707	/* Clear overrun flag in 2 Lines communication mode because received is not read */
sahilmgandhi	18:6a4db94011d3	2708	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi	18:6a4db94011d3	2709	{
sahilmgandhi	18:6a4db94011d3	2710	__HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi	18:6a4db94011d3	2711	}
sahilmgandhi	18:6a4db94011d3	2712
sahilmgandhi	18:6a4db94011d3	2713	hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi	18:6a4db94011d3	2714	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi	18:6a4db94011d3	2715	{
sahilmgandhi	18:6a4db94011d3	2716	HAL_SPI_ErrorCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2717	}
sahilmgandhi	18:6a4db94011d3	2718	else
sahilmgandhi	18:6a4db94011d3	2719	{
sahilmgandhi	18:6a4db94011d3	2720	HAL_SPI_TxCpltCallback(hspi);
sahilmgandhi	18:6a4db94011d3	2721	}
sahilmgandhi	18:6a4db94011d3	2722	}
sahilmgandhi	18:6a4db94011d3	2723
sahilmgandhi	18:6a4db94011d3	2724	/**
sahilmgandhi	18:6a4db94011d3	2725	* @}
sahilmgandhi	18:6a4db94011d3	2726	*/
sahilmgandhi	18:6a4db94011d3	2727
sahilmgandhi	18:6a4db94011d3	2728	#endif /* HAL_SPI_MODULE_ENABLED */
sahilmgandhi	18:6a4db94011d3	2729
sahilmgandhi	18:6a4db94011d3	2730	/**
sahilmgandhi	18:6a4db94011d3	2731	* @}
sahilmgandhi	18:6a4db94011d3	2732	*/
sahilmgandhi	18:6a4db94011d3	2733
sahilmgandhi	18:6a4db94011d3	2734	/**
sahilmgandhi	18:6a4db94011d3	2735	* @}
sahilmgandhi	18:6a4db94011d3	2736	*/
sahilmgandhi	18:6a4db94011d3	2737
sahilmgandhi	18:6a4db94011d3	2738	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_spi.c@18:6a4db94011d3, 2017-05-14 (annotated)

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