MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2006-2013 ARM Limited
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sahilmgandhi 18:6a4db94011d3 5 * you may not use this file except in compliance with the License.
sahilmgandhi 18:6a4db94011d3 6 * You may obtain a copy of the License at
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * http://www.apache.org/licenses/LICENSE-2.0
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Unless required by applicable law or agreed to in writing, software
sahilmgandhi 18:6a4db94011d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sahilmgandhi 18:6a4db94011d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sahilmgandhi 18:6a4db94011d3 13 * See the License for the specific language governing permissions and
sahilmgandhi 18:6a4db94011d3 14 * limitations under the License.
sahilmgandhi 18:6a4db94011d3 15 */
sahilmgandhi 18:6a4db94011d3 16 #include <string.h>
sahilmgandhi 18:6a4db94011d3 17 #include "ethernet_api.h"
sahilmgandhi 18:6a4db94011d3 18 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 19 #include "mbed_interface.h"
sahilmgandhi 18:6a4db94011d3 20 #include "mbed_toolchain.h"
sahilmgandhi 18:6a4db94011d3 21 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 22 #include "ether_iodefine.h"
sahilmgandhi 18:6a4db94011d3 23 #include "ethernetext_api.h"
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 /* Descriptor info */
sahilmgandhi 18:6a4db94011d3 26 #define NUM_OF_TX_DESCRIPTOR (16)
sahilmgandhi 18:6a4db94011d3 27 #define NUM_OF_RX_DESCRIPTOR (16)
sahilmgandhi 18:6a4db94011d3 28 #define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
sahilmgandhi 18:6a4db94011d3 29 #define MAX_SEND_SIZE (1514)
sahilmgandhi 18:6a4db94011d3 30 /* Ethernet Descriptor Value Define */
sahilmgandhi 18:6a4db94011d3 31 #define TD0_TFP_TOP_BOTTOM (0x30000000)
sahilmgandhi 18:6a4db94011d3 32 #define TD0_TACT (0x80000000)
sahilmgandhi 18:6a4db94011d3 33 #define TD0_TDLE (0x40000000)
sahilmgandhi 18:6a4db94011d3 34 #define RD0_RACT (0x80000000)
sahilmgandhi 18:6a4db94011d3 35 #define RD0_RDLE (0x40000000)
sahilmgandhi 18:6a4db94011d3 36 #define RD0_RFE (0x08000000)
sahilmgandhi 18:6a4db94011d3 37 #define RD0_RCSE (0x04000000)
sahilmgandhi 18:6a4db94011d3 38 #define RD0_RFS (0x03FF0000)
sahilmgandhi 18:6a4db94011d3 39 #define RD0_RCS (0x0000FFFF)
sahilmgandhi 18:6a4db94011d3 40 #define RD0_RFS_RFOF (0x02000000)
sahilmgandhi 18:6a4db94011d3 41 #define RD0_RFS_RUAF (0x00400000)
sahilmgandhi 18:6a4db94011d3 42 #define RD0_RFS_RRF (0x00100000)
sahilmgandhi 18:6a4db94011d3 43 #define RD0_RFS_RTLF (0x00080000)
sahilmgandhi 18:6a4db94011d3 44 #define RD0_RFS_RTSF (0x00040000)
sahilmgandhi 18:6a4db94011d3 45 #define RD0_RFS_PRE (0x00020000)
sahilmgandhi 18:6a4db94011d3 46 #define RD0_RFS_CERF (0x00010000)
sahilmgandhi 18:6a4db94011d3 47 #define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
sahilmgandhi 18:6a4db94011d3 48 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
sahilmgandhi 18:6a4db94011d3 49 #define RD1_RDL_MSK (0x0000FFFF)
sahilmgandhi 18:6a4db94011d3 50 /* PHY Register */
sahilmgandhi 18:6a4db94011d3 51 #define BASIC_MODE_CONTROL_REG (0)
sahilmgandhi 18:6a4db94011d3 52 #define BASIC_MODE_STATUS_REG (1)
sahilmgandhi 18:6a4db94011d3 53 #define PHY_IDENTIFIER1_REG (2)
sahilmgandhi 18:6a4db94011d3 54 #define PHY_IDENTIFIER2_REG (3)
sahilmgandhi 18:6a4db94011d3 55 #define PHY_SP_CTL_STS_REG (31)
sahilmgandhi 18:6a4db94011d3 56 /* MII management interface access */
sahilmgandhi 18:6a4db94011d3 57 #define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
sahilmgandhi 18:6a4db94011d3 58 #define PHY_ST (1)
sahilmgandhi 18:6a4db94011d3 59 #define PHY_WRITE (1)
sahilmgandhi 18:6a4db94011d3 60 #define PHY_READ (2)
sahilmgandhi 18:6a4db94011d3 61 #define MDC_WAIT (6) /* 400ns/4 */
sahilmgandhi 18:6a4db94011d3 62 #define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
sahilmgandhi 18:6a4db94011d3 63 #define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */
sahilmgandhi 18:6a4db94011d3 64 #define M_PHY_ID (0xFFFFFFF0)
sahilmgandhi 18:6a4db94011d3 65 #define PHY_ID_LAN8710A (0x0007C0F0)
sahilmgandhi 18:6a4db94011d3 66 /* ETHERPIR0 */
sahilmgandhi 18:6a4db94011d3 67 #define PIR0_MDI (0x00000008)
sahilmgandhi 18:6a4db94011d3 68 #define PIR0_MDO (0x00000004)
sahilmgandhi 18:6a4db94011d3 69 #define PIR0_MMD (0x00000002)
sahilmgandhi 18:6a4db94011d3 70 #define PIR0_MDC (0x00000001)
sahilmgandhi 18:6a4db94011d3 71 #define PIR0_MDC_HIGH (0x00000001)
sahilmgandhi 18:6a4db94011d3 72 #define PIR0_MDC_LOW (0x00000000)
sahilmgandhi 18:6a4db94011d3 73 /* ETHEREDRRR0 */
sahilmgandhi 18:6a4db94011d3 74 #define EDRRR0_RR (0x00000001)
sahilmgandhi 18:6a4db94011d3 75 /* ETHEREDTRR0 */
sahilmgandhi 18:6a4db94011d3 76 #define EDTRR0_TR (0x00000003)
sahilmgandhi 18:6a4db94011d3 77 /* software wait */
sahilmgandhi 18:6a4db94011d3 78 #define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 #define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
sahilmgandhi 18:6a4db94011d3 81 /* 0x00040000 : Detect frame reception */
sahilmgandhi 18:6a4db94011d3 82 /* 0x00010000 : Receive FIFO overflow */
sahilmgandhi 18:6a4db94011d3 83 /* 0x00000010 : Residual bit frame reception */
sahilmgandhi 18:6a4db94011d3 84 /* 0x00000008 : Long frame reception */
sahilmgandhi 18:6a4db94011d3 85 /* 0x00000004 : Short frame reception */
sahilmgandhi 18:6a4db94011d3 86 /* 0x00000002 : PHY-LSI reception error */
sahilmgandhi 18:6a4db94011d3 87 /* 0x00000001 : Receive frame CRC error */
sahilmgandhi 18:6a4db94011d3 88 #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 /* Send descriptor */
sahilmgandhi 18:6a4db94011d3 91 typedef struct tag_edmac_send_desc {
sahilmgandhi 18:6a4db94011d3 92 uint32_t td0;
sahilmgandhi 18:6a4db94011d3 93 uint32_t td1;
sahilmgandhi 18:6a4db94011d3 94 uint8_t *td2;
sahilmgandhi 18:6a4db94011d3 95 uint32_t padding4;
sahilmgandhi 18:6a4db94011d3 96 } edmac_send_desc_t;
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /* Receive descriptor */
sahilmgandhi 18:6a4db94011d3 99 typedef struct tag_edmac_recv_desc {
sahilmgandhi 18:6a4db94011d3 100 uint32_t rd0;
sahilmgandhi 18:6a4db94011d3 101 uint32_t rd1;
sahilmgandhi 18:6a4db94011d3 102 uint8_t *rd2;
sahilmgandhi 18:6a4db94011d3 103 uint32_t padding4;
sahilmgandhi 18:6a4db94011d3 104 } edmac_recv_desc_t;
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 /* memory */
sahilmgandhi 18:6a4db94011d3 107 /* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
sahilmgandhi 18:6a4db94011d3 108 /* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
sahilmgandhi 18:6a4db94011d3 109 #if defined(__ICCARM__)
sahilmgandhi 18:6a4db94011d3 110 #pragma data_alignment=16
sahilmgandhi 18:6a4db94011d3 111 static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
sahilmgandhi 18:6a4db94011d3 112 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
sahilmgandhi 18:6a4db94011d3 113 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
sahilmgandhi 18:6a4db94011d3 114 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned!
sahilmgandhi 18:6a4db94011d3 115 @ ".mirrorram";
sahilmgandhi 18:6a4db94011d3 116 #else
sahilmgandhi 18:6a4db94011d3 117 static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
sahilmgandhi 18:6a4db94011d3 118 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
sahilmgandhi 18:6a4db94011d3 119 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
sahilmgandhi 18:6a4db94011d3 120 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
sahilmgandhi 18:6a4db94011d3 121 __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
sahilmgandhi 18:6a4db94011d3 122 #endif
sahilmgandhi 18:6a4db94011d3 123 static int32_t rx_read_offset; /* read offset */
sahilmgandhi 18:6a4db94011d3 124 static int32_t tx_wite_offset; /* write offset */
sahilmgandhi 18:6a4db94011d3 125 static uint32_t send_top_index;
sahilmgandhi 18:6a4db94011d3 126 static uint32_t recv_top_index;
sahilmgandhi 18:6a4db94011d3 127 static int32_t Interrupt_priority;
sahilmgandhi 18:6a4db94011d3 128 static edmac_send_desc_t *p_eth_desc_dsend = NULL;
sahilmgandhi 18:6a4db94011d3 129 static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
sahilmgandhi 18:6a4db94011d3 130 static edmac_recv_desc_t *p_recv_end_desc = NULL;
sahilmgandhi 18:6a4db94011d3 131 static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
sahilmgandhi 18:6a4db94011d3 132 static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
sahilmgandhi 18:6a4db94011d3 133 static uint32_t phy_id = 0;
sahilmgandhi 18:6a4db94011d3 134 static uint32_t start_stop = 1; /* 0:stop 1:start */
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 /* function */
sahilmgandhi 18:6a4db94011d3 137 static void lan_reg_reset(void);
sahilmgandhi 18:6a4db94011d3 138 static void lan_desc_create(void);
sahilmgandhi 18:6a4db94011d3 139 static void lan_reg_set(int32_t link);
sahilmgandhi 18:6a4db94011d3 140 static uint16_t phy_reg_read(uint16_t reg_addr);
sahilmgandhi 18:6a4db94011d3 141 static void phy_reg_write(uint16_t reg_addr, uint16_t data);
sahilmgandhi 18:6a4db94011d3 142 static void mii_preamble(void);
sahilmgandhi 18:6a4db94011d3 143 static void mii_cmd(uint16_t reg_addr, uint32_t option);
sahilmgandhi 18:6a4db94011d3 144 static void mii_reg_read(uint16_t *data);
sahilmgandhi 18:6a4db94011d3 145 static void mii_reg_write(uint16_t data);
sahilmgandhi 18:6a4db94011d3 146 static void mii_z(void);
sahilmgandhi 18:6a4db94011d3 147 static void mii_write_1(void);
sahilmgandhi 18:6a4db94011d3 148 static void mii_write_0(void);
sahilmgandhi 18:6a4db94011d3 149 static void set_ether_pir(uint32_t set_data);
sahilmgandhi 18:6a4db94011d3 150 static void wait_100us(int32_t wait_cnt);
sahilmgandhi 18:6a4db94011d3 151
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
sahilmgandhi 18:6a4db94011d3 154 int32_t i;
sahilmgandhi 18:6a4db94011d3 155 uint16_t val;
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 /* -->4F<-- P1_14(ET_COL) */
sahilmgandhi 18:6a4db94011d3 160 GPIOPMC1 |= 0x4000;
sahilmgandhi 18:6a4db94011d3 161 GPIOPFCAE1 &= ~0x4000;
sahilmgandhi 18:6a4db94011d3 162 GPIOPFCE1 |= 0x4000;
sahilmgandhi 18:6a4db94011d3 163 GPIOPFC1 |= 0x4000;
sahilmgandhi 18:6a4db94011d3 164 GPIOPIPC1 |= 0x4000;
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0),
sahilmgandhi 18:6a4db94011d3 167 P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */
sahilmgandhi 18:6a4db94011d3 168 GPIOPMC2 |= 0x0FFF;
sahilmgandhi 18:6a4db94011d3 169 GPIOPFCAE2 &= ~0x0FFF;
sahilmgandhi 18:6a4db94011d3 170 GPIOPFCE2 &= ~0x0FFF;
sahilmgandhi 18:6a4db94011d3 171 GPIOPFC2 |= 0x0FFF;
sahilmgandhi 18:6a4db94011d3 172 GPIOPIPC2 |= 0x0FFF;
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
sahilmgandhi 18:6a4db94011d3 175 GPIOPMC3 |= 0x0078;
sahilmgandhi 18:6a4db94011d3 176 GPIOPFCAE3 &= ~0x0078;
sahilmgandhi 18:6a4db94011d3 177 GPIOPFCE3 &= ~0x0078;
sahilmgandhi 18:6a4db94011d3 178 GPIOPFC3 |= 0x0078;
sahilmgandhi 18:6a4db94011d3 179 GPIOPIPC3 |= 0x0078;
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 /* -->3F<-- P7_0(ET_MDC) */
sahilmgandhi 18:6a4db94011d3 182 GPIOPMC7 |= 0x0001;
sahilmgandhi 18:6a4db94011d3 183 GPIOPFCAE7 &= ~0x0001;
sahilmgandhi 18:6a4db94011d3 184 GPIOPFCE7 |= 0x0001;
sahilmgandhi 18:6a4db94011d3 185 GPIOPFC7 &= ~0x0001;
sahilmgandhi 18:6a4db94011d3 186 GPIOPIPC7 |= 0x0001;
sahilmgandhi 18:6a4db94011d3 187
sahilmgandhi 18:6a4db94011d3 188 /* Resets the E-MAC,E-DMAC */
sahilmgandhi 18:6a4db94011d3 189 lan_reg_reset();
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 /* Resets the PHY-LSI */
sahilmgandhi 18:6a4db94011d3 192 phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
sahilmgandhi 18:6a4db94011d3 193 for (i = 10000; i > 0; i--) {
sahilmgandhi 18:6a4db94011d3 194 val = phy_reg_read(BASIC_MODE_CONTROL_REG);
sahilmgandhi 18:6a4db94011d3 195 if (((uint32_t)val & 0x8000uL) == 0) {
sahilmgandhi 18:6a4db94011d3 196 break; /* Reset complete */
sahilmgandhi 18:6a4db94011d3 197 }
sahilmgandhi 18:6a4db94011d3 198 }
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
sahilmgandhi 18:6a4db94011d3 201 | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 Interrupt_priority = p_ethcfg->int_priority;
sahilmgandhi 18:6a4db94011d3 204 p_recv_cb_fnc = p_ethcfg->recv_cb;
sahilmgandhi 18:6a4db94011d3 205 start_stop = 1;
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 if (p_ethcfg->ether_mac != NULL) {
sahilmgandhi 18:6a4db94011d3 208 (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
sahilmgandhi 18:6a4db94011d3 209 } else {
sahilmgandhi 18:6a4db94011d3 210 ethernet_address(mac_addr); /* Get MAC Address */
sahilmgandhi 18:6a4db94011d3 211 }
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 return 0;
sahilmgandhi 18:6a4db94011d3 214 }
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 void ethernetext_start_stop(int32_t mode) {
sahilmgandhi 18:6a4db94011d3 217 if (mode == 1) {
sahilmgandhi 18:6a4db94011d3 218 /* start */
sahilmgandhi 18:6a4db94011d3 219 ETHEREDTRR0 |= EDTRR0_TR;
sahilmgandhi 18:6a4db94011d3 220 ETHEREDRRR0 |= EDRRR0_RR;
sahilmgandhi 18:6a4db94011d3 221 start_stop = 1;
sahilmgandhi 18:6a4db94011d3 222 } else {
sahilmgandhi 18:6a4db94011d3 223 /* stop */
sahilmgandhi 18:6a4db94011d3 224 ETHEREDTRR0 &= ~EDTRR0_TR;
sahilmgandhi 18:6a4db94011d3 225 ETHEREDRRR0 &= ~EDRRR0_RR;
sahilmgandhi 18:6a4db94011d3 226 start_stop = 0;
sahilmgandhi 18:6a4db94011d3 227 }
sahilmgandhi 18:6a4db94011d3 228 }
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 int ethernetext_chk_link_mode(void) {
sahilmgandhi 18:6a4db94011d3 231 int32_t link;
sahilmgandhi 18:6a4db94011d3 232 uint16_t data;
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
sahilmgandhi 18:6a4db94011d3 235 data = phy_reg_read(PHY_SP_CTL_STS_REG);
sahilmgandhi 18:6a4db94011d3 236 switch (((uint32_t)data >> 2) & 0x00000007) {
sahilmgandhi 18:6a4db94011d3 237 case 0x0001:
sahilmgandhi 18:6a4db94011d3 238 link = HALF_10M;
sahilmgandhi 18:6a4db94011d3 239 break;
sahilmgandhi 18:6a4db94011d3 240 case 0x0005:
sahilmgandhi 18:6a4db94011d3 241 link = FULL_10M;
sahilmgandhi 18:6a4db94011d3 242 break;
sahilmgandhi 18:6a4db94011d3 243 case 0x0002:
sahilmgandhi 18:6a4db94011d3 244 link = HALF_TX;
sahilmgandhi 18:6a4db94011d3 245 break;
sahilmgandhi 18:6a4db94011d3 246 case 0x0006:
sahilmgandhi 18:6a4db94011d3 247 link = FULL_TX;
sahilmgandhi 18:6a4db94011d3 248 break;
sahilmgandhi 18:6a4db94011d3 249 default:
sahilmgandhi 18:6a4db94011d3 250 link = NEGO_FAIL;
sahilmgandhi 18:6a4db94011d3 251 break;
sahilmgandhi 18:6a4db94011d3 252 }
sahilmgandhi 18:6a4db94011d3 253 } else {
sahilmgandhi 18:6a4db94011d3 254 link = NEGO_FAIL;
sahilmgandhi 18:6a4db94011d3 255 }
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 return link;
sahilmgandhi 18:6a4db94011d3 258 }
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 void ethernetext_set_link_mode(int32_t link) {
sahilmgandhi 18:6a4db94011d3 261 lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
sahilmgandhi 18:6a4db94011d3 262 lan_desc_create(); /* Initialize of buffer memory */
sahilmgandhi 18:6a4db94011d3 263 lan_reg_set(link); /* E-DMAC, E-MAC initialization */
sahilmgandhi 18:6a4db94011d3 264 }
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 int ethernet_init() {
sahilmgandhi 18:6a4db94011d3 267 ethernet_cfg_t ethcfg;
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 ethcfg.int_priority = 5;
sahilmgandhi 18:6a4db94011d3 270 ethcfg.recv_cb = NULL;
sahilmgandhi 18:6a4db94011d3 271 ethcfg.ether_mac = NULL;
sahilmgandhi 18:6a4db94011d3 272 ethernetext_init(&ethcfg);
sahilmgandhi 18:6a4db94011d3 273 ethernet_set_link(-1, 0); /* Auto-Negotiation */
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 return 0;
sahilmgandhi 18:6a4db94011d3 276 }
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 void ethernet_free() {
sahilmgandhi 18:6a4db94011d3 279 ETHERARSTR |= 0x00000001; /* ETHER software reset */
sahilmgandhi 18:6a4db94011d3 280 CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
sahilmgandhi 18:6a4db94011d3 281 }
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 int ethernet_write(const char *data, int slen) {
sahilmgandhi 18:6a4db94011d3 284 edmac_send_desc_t *p_send_desc;
sahilmgandhi 18:6a4db94011d3 285 int32_t copy_size;
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
sahilmgandhi 18:6a4db94011d3 288 || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
sahilmgandhi 18:6a4db94011d3 289 copy_size = 0;
sahilmgandhi 18:6a4db94011d3 290 } else {
sahilmgandhi 18:6a4db94011d3 291 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
sahilmgandhi 18:6a4db94011d3 292 if ((p_send_desc->td0 & TD0_TACT) != 0) {
sahilmgandhi 18:6a4db94011d3 293 copy_size = 0;
sahilmgandhi 18:6a4db94011d3 294 } else {
sahilmgandhi 18:6a4db94011d3 295 copy_size = MAX_SEND_SIZE - tx_wite_offset;
sahilmgandhi 18:6a4db94011d3 296 if (copy_size > slen) {
sahilmgandhi 18:6a4db94011d3 297 copy_size = slen;
sahilmgandhi 18:6a4db94011d3 298 }
sahilmgandhi 18:6a4db94011d3 299 (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
sahilmgandhi 18:6a4db94011d3 300 tx_wite_offset += copy_size;
sahilmgandhi 18:6a4db94011d3 301 }
sahilmgandhi 18:6a4db94011d3 302 }
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 return copy_size;
sahilmgandhi 18:6a4db94011d3 305 }
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 int ethernet_send() {
sahilmgandhi 18:6a4db94011d3 308 edmac_send_desc_t *p_send_desc;
sahilmgandhi 18:6a4db94011d3 309 int32_t ret;
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
sahilmgandhi 18:6a4db94011d3 312 ret = 0;
sahilmgandhi 18:6a4db94011d3 313 } else {
sahilmgandhi 18:6a4db94011d3 314 /* Transfer 1 frame */
sahilmgandhi 18:6a4db94011d3 315 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /* Sets the frame length */
sahilmgandhi 18:6a4db94011d3 318 p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
sahilmgandhi 18:6a4db94011d3 319 tx_wite_offset = 0;
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 /* Sets the transmit descriptor to transmit again */
sahilmgandhi 18:6a4db94011d3 322 p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
sahilmgandhi 18:6a4db94011d3 323 p_send_desc->td0 |= TD0_TACT;
sahilmgandhi 18:6a4db94011d3 324 if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
sahilmgandhi 18:6a4db94011d3 325 ETHEREDTRR0 |= EDTRR0_TR;
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /* Update the current descriptor */
sahilmgandhi 18:6a4db94011d3 329 send_top_index++;
sahilmgandhi 18:6a4db94011d3 330 if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
sahilmgandhi 18:6a4db94011d3 331 send_top_index = 0;
sahilmgandhi 18:6a4db94011d3 332 }
sahilmgandhi 18:6a4db94011d3 333 ret = 1;
sahilmgandhi 18:6a4db94011d3 334 }
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 return ret;
sahilmgandhi 18:6a4db94011d3 337 }
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 int ethernet_receive() {
sahilmgandhi 18:6a4db94011d3 340 edmac_recv_desc_t *p_recv_desc;
sahilmgandhi 18:6a4db94011d3 341 int32_t receive_size = 0;
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 if (p_eth_desc_drecv != NULL) {
sahilmgandhi 18:6a4db94011d3 344 if (p_recv_end_desc != NULL) {
sahilmgandhi 18:6a4db94011d3 345 /* Sets the receive descriptor to receive again */
sahilmgandhi 18:6a4db94011d3 346 p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
sahilmgandhi 18:6a4db94011d3 347 p_recv_end_desc->rd0 |= RD0_RACT;
sahilmgandhi 18:6a4db94011d3 348 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
sahilmgandhi 18:6a4db94011d3 349 ETHEREDRRR0 |= EDRRR0_RR;
sahilmgandhi 18:6a4db94011d3 350 }
sahilmgandhi 18:6a4db94011d3 351 p_recv_end_desc = NULL;
sahilmgandhi 18:6a4db94011d3 352 }
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
sahilmgandhi 18:6a4db94011d3 355 if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
sahilmgandhi 18:6a4db94011d3 356 /* Receives 1 frame */
sahilmgandhi 18:6a4db94011d3 357 if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
sahilmgandhi 18:6a4db94011d3 358 /* Receive frame error */
sahilmgandhi 18:6a4db94011d3 359 /* Sets the receive descriptor to receive again */
sahilmgandhi 18:6a4db94011d3 360 p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
sahilmgandhi 18:6a4db94011d3 361 p_recv_desc->rd0 |= RD0_RACT;
sahilmgandhi 18:6a4db94011d3 362 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
sahilmgandhi 18:6a4db94011d3 363 ETHEREDRRR0 |= EDRRR0_RR;
sahilmgandhi 18:6a4db94011d3 364 }
sahilmgandhi 18:6a4db94011d3 365 } else {
sahilmgandhi 18:6a4db94011d3 366 /* Copies the received frame */
sahilmgandhi 18:6a4db94011d3 367 rx_read_offset = 0;
sahilmgandhi 18:6a4db94011d3 368 p_recv_end_desc = p_recv_desc;
sahilmgandhi 18:6a4db94011d3 369 receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
sahilmgandhi 18:6a4db94011d3 370 }
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 /* Update the current descriptor */
sahilmgandhi 18:6a4db94011d3 373 recv_top_index++;
sahilmgandhi 18:6a4db94011d3 374 if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
sahilmgandhi 18:6a4db94011d3 375 recv_top_index = 0;
sahilmgandhi 18:6a4db94011d3 376 }
sahilmgandhi 18:6a4db94011d3 377 }
sahilmgandhi 18:6a4db94011d3 378 }
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 return receive_size;
sahilmgandhi 18:6a4db94011d3 381 }
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383 int ethernet_read(char *data, int dlen) {
sahilmgandhi 18:6a4db94011d3 384 edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
sahilmgandhi 18:6a4db94011d3 385 int32_t copy_size;
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
sahilmgandhi 18:6a4db94011d3 388 copy_size = 0;
sahilmgandhi 18:6a4db94011d3 389 } else {
sahilmgandhi 18:6a4db94011d3 390 copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
sahilmgandhi 18:6a4db94011d3 391 if (copy_size > dlen) {
sahilmgandhi 18:6a4db94011d3 392 copy_size = dlen;
sahilmgandhi 18:6a4db94011d3 393 }
sahilmgandhi 18:6a4db94011d3 394 (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
sahilmgandhi 18:6a4db94011d3 395 rx_read_offset += copy_size;
sahilmgandhi 18:6a4db94011d3 396 }
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 return copy_size;
sahilmgandhi 18:6a4db94011d3 399 }
sahilmgandhi 18:6a4db94011d3 400
sahilmgandhi 18:6a4db94011d3 401 void ethernet_address(char *mac) {
sahilmgandhi 18:6a4db94011d3 402 if (mac != NULL) {
sahilmgandhi 18:6a4db94011d3 403 mbed_mac_address(mac); /* Get MAC Address */
sahilmgandhi 18:6a4db94011d3 404 }
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 int ethernet_link(void) {
sahilmgandhi 18:6a4db94011d3 408 int32_t ret;
sahilmgandhi 18:6a4db94011d3 409 uint16_t data;
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 data = phy_reg_read(BASIC_MODE_STATUS_REG);
sahilmgandhi 18:6a4db94011d3 412 if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
sahilmgandhi 18:6a4db94011d3 413 ret = 1;
sahilmgandhi 18:6a4db94011d3 414 } else {
sahilmgandhi 18:6a4db94011d3 415 ret = 0;
sahilmgandhi 18:6a4db94011d3 416 }
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 return ret;
sahilmgandhi 18:6a4db94011d3 419 }
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 void ethernet_set_link(int speed, int duplex) {
sahilmgandhi 18:6a4db94011d3 422 uint16_t data;
sahilmgandhi 18:6a4db94011d3 423 int32_t i;
sahilmgandhi 18:6a4db94011d3 424 int32_t link;
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426 if ((speed < 0) || (speed > 1)) {
sahilmgandhi 18:6a4db94011d3 427 data = 0x1000; /* Auto-Negotiation Enable */
sahilmgandhi 18:6a4db94011d3 428 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
sahilmgandhi 18:6a4db94011d3 429 for (i = 0; i < 1000; i++) {
sahilmgandhi 18:6a4db94011d3 430 data = phy_reg_read(BASIC_MODE_STATUS_REG);
sahilmgandhi 18:6a4db94011d3 431 if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
sahilmgandhi 18:6a4db94011d3 432 break;
sahilmgandhi 18:6a4db94011d3 433 }
sahilmgandhi 18:6a4db94011d3 434 wait_100us(10);
sahilmgandhi 18:6a4db94011d3 435 }
sahilmgandhi 18:6a4db94011d3 436 } else {
sahilmgandhi 18:6a4db94011d3 437 data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
sahilmgandhi 18:6a4db94011d3 438 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
sahilmgandhi 18:6a4db94011d3 439 wait_100us(1);
sahilmgandhi 18:6a4db94011d3 440 }
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 link = ethernetext_chk_link_mode();
sahilmgandhi 18:6a4db94011d3 443 ethernetext_set_link_mode(link);
sahilmgandhi 18:6a4db94011d3 444 }
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 void INT_Ether(void) {
sahilmgandhi 18:6a4db94011d3 447 uint32_t stat_edmac;
sahilmgandhi 18:6a4db94011d3 448 uint32_t stat_etherc;
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 /* Clear the interrupt request flag */
sahilmgandhi 18:6a4db94011d3 451 stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
sahilmgandhi 18:6a4db94011d3 452 ETHEREESR0 = stat_edmac;
sahilmgandhi 18:6a4db94011d3 453 /* Reception-related */
sahilmgandhi 18:6a4db94011d3 454 if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
sahilmgandhi 18:6a4db94011d3 455 if (p_recv_cb_fnc != NULL) {
sahilmgandhi 18:6a4db94011d3 456 p_recv_cb_fnc();
sahilmgandhi 18:6a4db94011d3 457 }
sahilmgandhi 18:6a4db94011d3 458 }
sahilmgandhi 18:6a4db94011d3 459 /* E-MAC-related */
sahilmgandhi 18:6a4db94011d3 460 if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
sahilmgandhi 18:6a4db94011d3 461 /* Clear the interrupt request flag */
sahilmgandhi 18:6a4db94011d3 462 stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
sahilmgandhi 18:6a4db94011d3 463 ETHERECSR0 = stat_etherc;
sahilmgandhi 18:6a4db94011d3 464 }
sahilmgandhi 18:6a4db94011d3 465 }
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 static void lan_reg_reset(void) {
sahilmgandhi 18:6a4db94011d3 468 volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 ETHERARSTR |= 0x00000001; /* ETHER software reset */
sahilmgandhi 18:6a4db94011d3 471 while (j--) {
sahilmgandhi 18:6a4db94011d3 472 /* Do Nothing */
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
sahilmgandhi 18:6a4db94011d3 476 ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 /* Check clear software reset */
sahilmgandhi 18:6a4db94011d3 479 while ((ETHEREDMR0 & 0x00000003) != 0) {
sahilmgandhi 18:6a4db94011d3 480 /* Do Nothing */
sahilmgandhi 18:6a4db94011d3 481 }
sahilmgandhi 18:6a4db94011d3 482 }
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 static void lan_desc_create(void) {
sahilmgandhi 18:6a4db94011d3 485 int32_t i;
sahilmgandhi 18:6a4db94011d3 486 uint8_t *p_memory_top;
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
sahilmgandhi 18:6a4db94011d3 489 p_memory_top = ethernet_nc_memory;
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 /* Descriptor area configuration */
sahilmgandhi 18:6a4db94011d3 492 p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
sahilmgandhi 18:6a4db94011d3 493 p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
sahilmgandhi 18:6a4db94011d3 494 p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
sahilmgandhi 18:6a4db94011d3 495 p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /* Transmit descriptor */
sahilmgandhi 18:6a4db94011d3 498 for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
sahilmgandhi 18:6a4db94011d3 499 p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
sahilmgandhi 18:6a4db94011d3 500 p_memory_top += SIZE_OF_BUFFER;
sahilmgandhi 18:6a4db94011d3 501 p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
sahilmgandhi 18:6a4db94011d3 502 p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
sahilmgandhi 18:6a4db94011d3 503 }
sahilmgandhi 18:6a4db94011d3 504 p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /* Receive descriptor */
sahilmgandhi 18:6a4db94011d3 507 for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
sahilmgandhi 18:6a4db94011d3 508 p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
sahilmgandhi 18:6a4db94011d3 509 p_memory_top += SIZE_OF_BUFFER;
sahilmgandhi 18:6a4db94011d3 510 p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
sahilmgandhi 18:6a4db94011d3 511 p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
sahilmgandhi 18:6a4db94011d3 512 }
sahilmgandhi 18:6a4db94011d3 513 p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 /* Initialize descriptor management information */
sahilmgandhi 18:6a4db94011d3 516 send_top_index = 0;
sahilmgandhi 18:6a4db94011d3 517 recv_top_index = 0;
sahilmgandhi 18:6a4db94011d3 518 rx_read_offset = 0;
sahilmgandhi 18:6a4db94011d3 519 tx_wite_offset = 0;
sahilmgandhi 18:6a4db94011d3 520 p_recv_end_desc = NULL;
sahilmgandhi 18:6a4db94011d3 521 }
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 static void lan_reg_set(int32_t link) {
sahilmgandhi 18:6a4db94011d3 524 /* MAC address setting */
sahilmgandhi 18:6a4db94011d3 525 ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
sahilmgandhi 18:6a4db94011d3 526 | ((uint32_t)mac_addr[1] << 16)
sahilmgandhi 18:6a4db94011d3 527 | ((uint32_t)mac_addr[2] << 8)
sahilmgandhi 18:6a4db94011d3 528 | (uint32_t)mac_addr[3];
sahilmgandhi 18:6a4db94011d3 529 ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
sahilmgandhi 18:6a4db94011d3 530 | (uint32_t)mac_addr[5];
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 /* E-DMAC */
sahilmgandhi 18:6a4db94011d3 533 ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
sahilmgandhi 18:6a4db94011d3 534 ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
sahilmgandhi 18:6a4db94011d3 535 ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
sahilmgandhi 18:6a4db94011d3 536 ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
sahilmgandhi 18:6a4db94011d3 537 ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
sahilmgandhi 18:6a4db94011d3 538 ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
sahilmgandhi 18:6a4db94011d3 539 ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
sahilmgandhi 18:6a4db94011d3 540 ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
sahilmgandhi 18:6a4db94011d3 541 ETHEREDMR0 |= 0x00000040; /* Little endian */
sahilmgandhi 18:6a4db94011d3 542 ETHERTRSCER0 &= ~0x0003009F; /* All clear */
sahilmgandhi 18:6a4db94011d3 543 ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
sahilmgandhi 18:6a4db94011d3 544 ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
sahilmgandhi 18:6a4db94011d3 545 ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
sahilmgandhi 18:6a4db94011d3 546 ETHERFCFTR0 &= ~0x001F00FF;
sahilmgandhi 18:6a4db94011d3 547 ETHERFCFTR0 |= 0x00070007;
sahilmgandhi 18:6a4db94011d3 548 ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
sahilmgandhi 18:6a4db94011d3 549
sahilmgandhi 18:6a4db94011d3 550 /* E-MAC */
sahilmgandhi 18:6a4db94011d3 551 ETHERECMR0 &= ~0x04BF2063; /* All clear */
sahilmgandhi 18:6a4db94011d3 552 ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
sahilmgandhi 18:6a4db94011d3 553 ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
sahilmgandhi 18:6a4db94011d3 554 ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
sahilmgandhi 18:6a4db94011d3 555 ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
sahilmgandhi 18:6a4db94011d3 556 ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
sahilmgandhi 18:6a4db94011d3 557 if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
sahilmgandhi 18:6a4db94011d3 558 ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
sahilmgandhi 18:6a4db94011d3 559 } else {
sahilmgandhi 18:6a4db94011d3 560 ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
sahilmgandhi 18:6a4db94011d3 561 }
sahilmgandhi 18:6a4db94011d3 562
sahilmgandhi 18:6a4db94011d3 563 /* Interrupt-related */
sahilmgandhi 18:6a4db94011d3 564 if (p_recv_cb_fnc != NULL) {
sahilmgandhi 18:6a4db94011d3 565 ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
sahilmgandhi 18:6a4db94011d3 566 ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
sahilmgandhi 18:6a4db94011d3 567 ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
sahilmgandhi 18:6a4db94011d3 568 ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
sahilmgandhi 18:6a4db94011d3 569 InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
sahilmgandhi 18:6a4db94011d3 570 GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
sahilmgandhi 18:6a4db94011d3 571 GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
sahilmgandhi 18:6a4db94011d3 572 }
sahilmgandhi 18:6a4db94011d3 573
sahilmgandhi 18:6a4db94011d3 574 ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 /* Enable transmission/reception */
sahilmgandhi 18:6a4db94011d3 577 if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
sahilmgandhi 18:6a4db94011d3 578 ETHEREDRRR0 |= 0x00000001; /* RR */
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580 }
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 static uint16_t phy_reg_read(uint16_t reg_addr) {
sahilmgandhi 18:6a4db94011d3 583 uint16_t data;
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 mii_preamble();
sahilmgandhi 18:6a4db94011d3 586 mii_cmd(reg_addr, PHY_READ);
sahilmgandhi 18:6a4db94011d3 587 mii_z();
sahilmgandhi 18:6a4db94011d3 588 mii_reg_read(&data);
sahilmgandhi 18:6a4db94011d3 589 mii_z();
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 return data;
sahilmgandhi 18:6a4db94011d3 592 }
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
sahilmgandhi 18:6a4db94011d3 595 mii_preamble();
sahilmgandhi 18:6a4db94011d3 596 mii_cmd(reg_addr, PHY_WRITE);
sahilmgandhi 18:6a4db94011d3 597 mii_write_1();
sahilmgandhi 18:6a4db94011d3 598 mii_write_0();
sahilmgandhi 18:6a4db94011d3 599 mii_reg_write(data);
sahilmgandhi 18:6a4db94011d3 600 mii_z();
sahilmgandhi 18:6a4db94011d3 601 }
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 static void mii_preamble(void) {
sahilmgandhi 18:6a4db94011d3 604 int32_t i = 32;
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 for (i = 32; i > 0; i--) {
sahilmgandhi 18:6a4db94011d3 607 /* 1 is output via the MII (Media Independent Interface) block. */
sahilmgandhi 18:6a4db94011d3 608 mii_write_1();
sahilmgandhi 18:6a4db94011d3 609 }
sahilmgandhi 18:6a4db94011d3 610 }
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 static void mii_cmd(uint16_t reg_addr, uint32_t option) {
sahilmgandhi 18:6a4db94011d3 613 int32_t i;
sahilmgandhi 18:6a4db94011d3 614 uint16_t data = 0;
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 data |= (PHY_ST << 14); /* ST code */
sahilmgandhi 18:6a4db94011d3 617 data |= (option << 12); /* OP code */
sahilmgandhi 18:6a4db94011d3 618 data |= (PHY_ADDR << 7); /* PHY Address */
sahilmgandhi 18:6a4db94011d3 619 data |= (uint16_t)(reg_addr << 2); /* Reg Address */
sahilmgandhi 18:6a4db94011d3 620 for (i = 14; i > 0; i--) {
sahilmgandhi 18:6a4db94011d3 621 if ((data & 0x8000) == 0) {
sahilmgandhi 18:6a4db94011d3 622 mii_write_0();
sahilmgandhi 18:6a4db94011d3 623 } else {
sahilmgandhi 18:6a4db94011d3 624 mii_write_1();
sahilmgandhi 18:6a4db94011d3 625 }
sahilmgandhi 18:6a4db94011d3 626 data <<= 1;
sahilmgandhi 18:6a4db94011d3 627 }
sahilmgandhi 18:6a4db94011d3 628 }
sahilmgandhi 18:6a4db94011d3 629
sahilmgandhi 18:6a4db94011d3 630 static void mii_reg_read(uint16_t *data) {
sahilmgandhi 18:6a4db94011d3 631 int32_t i;
sahilmgandhi 18:6a4db94011d3 632 uint16_t reg_data = 0;
sahilmgandhi 18:6a4db94011d3 633
sahilmgandhi 18:6a4db94011d3 634 /* Data are read in one bit at a time */
sahilmgandhi 18:6a4db94011d3 635 for (i = 16; i > 0; i--) {
sahilmgandhi 18:6a4db94011d3 636 set_ether_pir(PIR0_MDC_LOW);
sahilmgandhi 18:6a4db94011d3 637 set_ether_pir(PIR0_MDC_HIGH);
sahilmgandhi 18:6a4db94011d3 638 reg_data <<= 1;
sahilmgandhi 18:6a4db94011d3 639 reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
sahilmgandhi 18:6a4db94011d3 640 set_ether_pir(PIR0_MDC_HIGH);
sahilmgandhi 18:6a4db94011d3 641 set_ether_pir(PIR0_MDC_LOW);
sahilmgandhi 18:6a4db94011d3 642 }
sahilmgandhi 18:6a4db94011d3 643 *data = reg_data;
sahilmgandhi 18:6a4db94011d3 644 }
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 static void mii_reg_write(uint16_t data) {
sahilmgandhi 18:6a4db94011d3 647 int32_t i;
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 /* Data are written one bit at a time */
sahilmgandhi 18:6a4db94011d3 650 for (i = 16; i > 0; i--) {
sahilmgandhi 18:6a4db94011d3 651 if ((data & 0x8000) == 0) {
sahilmgandhi 18:6a4db94011d3 652 mii_write_0();
sahilmgandhi 18:6a4db94011d3 653 } else {
sahilmgandhi 18:6a4db94011d3 654 mii_write_1();
sahilmgandhi 18:6a4db94011d3 655 }
sahilmgandhi 18:6a4db94011d3 656 data <<= 1;
sahilmgandhi 18:6a4db94011d3 657 }
sahilmgandhi 18:6a4db94011d3 658 }
sahilmgandhi 18:6a4db94011d3 659
sahilmgandhi 18:6a4db94011d3 660 static void mii_z(void) {
sahilmgandhi 18:6a4db94011d3 661 set_ether_pir(PIR0_MDC_LOW);
sahilmgandhi 18:6a4db94011d3 662 set_ether_pir(PIR0_MDC_HIGH);
sahilmgandhi 18:6a4db94011d3 663 set_ether_pir(PIR0_MDC_HIGH);
sahilmgandhi 18:6a4db94011d3 664 set_ether_pir(PIR0_MDC_LOW);
sahilmgandhi 18:6a4db94011d3 665 }
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 static void mii_write_1(void) {
sahilmgandhi 18:6a4db94011d3 668 set_ether_pir(PIR0_MDO | PIR0_MMD);
sahilmgandhi 18:6a4db94011d3 669 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
sahilmgandhi 18:6a4db94011d3 670 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
sahilmgandhi 18:6a4db94011d3 671 set_ether_pir(PIR0_MDO | PIR0_MMD);
sahilmgandhi 18:6a4db94011d3 672 }
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 static void mii_write_0(void) {
sahilmgandhi 18:6a4db94011d3 675 set_ether_pir(PIR0_MMD);
sahilmgandhi 18:6a4db94011d3 676 set_ether_pir(PIR0_MMD | PIR0_MDC);
sahilmgandhi 18:6a4db94011d3 677 set_ether_pir(PIR0_MMD | PIR0_MDC);
sahilmgandhi 18:6a4db94011d3 678 set_ether_pir(PIR0_MMD);
sahilmgandhi 18:6a4db94011d3 679 }
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 static void set_ether_pir(uint32_t set_data) {
sahilmgandhi 18:6a4db94011d3 682 int32_t i;
sahilmgandhi 18:6a4db94011d3 683
sahilmgandhi 18:6a4db94011d3 684 for (i = MDC_WAIT; i > 0; i--) {
sahilmgandhi 18:6a4db94011d3 685 ETHERPIR0 = set_data;
sahilmgandhi 18:6a4db94011d3 686 }
sahilmgandhi 18:6a4db94011d3 687 }
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 static void wait_100us(int32_t wait_cnt) {
sahilmgandhi 18:6a4db94011d3 690 volatile int32_t j = LOOP_100us * wait_cnt;
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692 while (--j) {
sahilmgandhi 18:6a4db94011d3 693 /* Do Nothing */
sahilmgandhi 18:6a4db94011d3 694 }
sahilmgandhi 18:6a4db94011d3 695 }