MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11XX/device/system_LPC11xx.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file system_LPC11xx.c
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
sahilmgandhi 18:6a4db94011d3 4 * for the NXP LPC11xx/LPC11Cxx Devices
sahilmgandhi 18:6a4db94011d3 5 * @version V1.10
sahilmgandhi 18:6a4db94011d3 6 * @date 24. November 2010
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * @par
sahilmgandhi 18:6a4db94011d3 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
sahilmgandhi 18:6a4db94011d3 13 * processor based microcontrollers. This file can be freely distributed
sahilmgandhi 18:6a4db94011d3 14 * within development tools that are supporting such ARM based processors.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * @par
sahilmgandhi 18:6a4db94011d3 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
sahilmgandhi 18:6a4db94011d3 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
sahilmgandhi 18:6a4db94011d3 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
sahilmgandhi 18:6a4db94011d3 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 #include <stdint.h>
sahilmgandhi 18:6a4db94011d3 27 #include "LPC11xx.h"
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /*
sahilmgandhi 18:6a4db94011d3 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
sahilmgandhi 18:6a4db94011d3 31 */
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /*--------------------- Clock Configuration ----------------------------------
sahilmgandhi 18:6a4db94011d3 34 //
sahilmgandhi 18:6a4db94011d3 35 // <e> Clock Configuration
sahilmgandhi 18:6a4db94011d3 36 // <h> System Oscillator Control Register (SYSOSCCTRL)
sahilmgandhi 18:6a4db94011d3 37 // <o1.0> BYPASS: System Oscillator Bypass Enable
sahilmgandhi 18:6a4db94011d3 38 // <i> If enabled then PLL input (sys_osc_clk) is fed
sahilmgandhi 18:6a4db94011d3 39 // <i> directly from XTALIN and XTALOUT pins.
sahilmgandhi 18:6a4db94011d3 40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
sahilmgandhi 18:6a4db94011d3 41 // <i> Determines frequency range for Low-power oscillator.
sahilmgandhi 18:6a4db94011d3 42 // <0=> 1 - 20 MHz
sahilmgandhi 18:6a4db94011d3 43 // <1=> 15 - 25 MHz
sahilmgandhi 18:6a4db94011d3 44 // </h>
sahilmgandhi 18:6a4db94011d3 45 //
sahilmgandhi 18:6a4db94011d3 46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
sahilmgandhi 18:6a4db94011d3 47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
sahilmgandhi 18:6a4db94011d3 48 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
sahilmgandhi 18:6a4db94011d3 49 // <0-31>
sahilmgandhi 18:6a4db94011d3 50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
sahilmgandhi 18:6a4db94011d3 51 // <0=> Undefined
sahilmgandhi 18:6a4db94011d3 52 // <1=> 0.5 MHz
sahilmgandhi 18:6a4db94011d3 53 // <2=> 0.8 MHz
sahilmgandhi 18:6a4db94011d3 54 // <3=> 1.1 MHz
sahilmgandhi 18:6a4db94011d3 55 // <4=> 1.4 MHz
sahilmgandhi 18:6a4db94011d3 56 // <5=> 1.6 MHz
sahilmgandhi 18:6a4db94011d3 57 // <6=> 1.8 MHz
sahilmgandhi 18:6a4db94011d3 58 // <7=> 2.0 MHz
sahilmgandhi 18:6a4db94011d3 59 // <8=> 2.2 MHz
sahilmgandhi 18:6a4db94011d3 60 // <9=> 2.4 MHz
sahilmgandhi 18:6a4db94011d3 61 // <10=> 2.6 MHz
sahilmgandhi 18:6a4db94011d3 62 // <11=> 2.7 MHz
sahilmgandhi 18:6a4db94011d3 63 // <12=> 2.9 MHz
sahilmgandhi 18:6a4db94011d3 64 // <13=> 3.1 MHz
sahilmgandhi 18:6a4db94011d3 65 // <14=> 3.2 MHz
sahilmgandhi 18:6a4db94011d3 66 // <15=> 3.4 MHz
sahilmgandhi 18:6a4db94011d3 67 // </h>
sahilmgandhi 18:6a4db94011d3 68 //
sahilmgandhi 18:6a4db94011d3 69 // <h> System PLL Control Register (SYSPLLCTRL)
sahilmgandhi 18:6a4db94011d3 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
sahilmgandhi 18:6a4db94011d3 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
sahilmgandhi 18:6a4db94011d3 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
sahilmgandhi 18:6a4db94011d3 73 // <o3.0..4> MSEL: Feedback Divider Selection
sahilmgandhi 18:6a4db94011d3 74 // <i> M = MSEL + 1
sahilmgandhi 18:6a4db94011d3 75 // <0-31>
sahilmgandhi 18:6a4db94011d3 76 // <o3.5..6> PSEL: Post Divider Selection
sahilmgandhi 18:6a4db94011d3 77 // <0=> P = 1
sahilmgandhi 18:6a4db94011d3 78 // <1=> P = 2
sahilmgandhi 18:6a4db94011d3 79 // <2=> P = 4
sahilmgandhi 18:6a4db94011d3 80 // <3=> P = 8
sahilmgandhi 18:6a4db94011d3 81 // </h>
sahilmgandhi 18:6a4db94011d3 82 //
sahilmgandhi 18:6a4db94011d3 83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
sahilmgandhi 18:6a4db94011d3 84 // <o4.0..1> SEL: System PLL Clock Source
sahilmgandhi 18:6a4db94011d3 85 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 86 // <1=> System Oscillator
sahilmgandhi 18:6a4db94011d3 87 // <2=> Reserved
sahilmgandhi 18:6a4db94011d3 88 // <3=> Reserved
sahilmgandhi 18:6a4db94011d3 89 // </h>
sahilmgandhi 18:6a4db94011d3 90 //
sahilmgandhi 18:6a4db94011d3 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
sahilmgandhi 18:6a4db94011d3 92 // <o5.0..1> SEL: Clock Source for Main Clock
sahilmgandhi 18:6a4db94011d3 93 // <0=> IRC Oscillator
sahilmgandhi 18:6a4db94011d3 94 // <1=> Input Clock to System PLL
sahilmgandhi 18:6a4db94011d3 95 // <2=> WDT Oscillator
sahilmgandhi 18:6a4db94011d3 96 // <3=> System PLL Clock Out
sahilmgandhi 18:6a4db94011d3 97 // </h>
sahilmgandhi 18:6a4db94011d3 98 //
sahilmgandhi 18:6a4db94011d3 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
sahilmgandhi 18:6a4db94011d3 100 // <o6.0..7> DIV: System AHB Clock Divider
sahilmgandhi 18:6a4db94011d3 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
sahilmgandhi 18:6a4db94011d3 102 // <i> 0 = is disabled
sahilmgandhi 18:6a4db94011d3 103 // <0-255>
sahilmgandhi 18:6a4db94011d3 104 // </h>
sahilmgandhi 18:6a4db94011d3 105 // </e>
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107 #define CLOCK_SETUP 1
sahilmgandhi 18:6a4db94011d3 108 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 109 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 110 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
sahilmgandhi 18:6a4db94011d3 111 #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 // Define as using IRC
sahilmgandhi 18:6a4db94011d3 112 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 // Define as using System PLL clock out
sahilmgandhi 18:6a4db94011d3 113 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /*
sahilmgandhi 18:6a4db94011d3 116 //-------- <<< end of configuration section >>> ------------------------------
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 120 Check the register settings
sahilmgandhi 18:6a4db94011d3 121 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 122 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
sahilmgandhi 18:6a4db94011d3 123 #define CHECK_RSVD(val, mask) (val & mask)
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 /* Clock Configuration -------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 126 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
sahilmgandhi 18:6a4db94011d3 127 #error "SYSOSCCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 128 #endif
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
sahilmgandhi 18:6a4db94011d3 131 #error "WDTOSCCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 132 #endif
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
sahilmgandhi 18:6a4db94011d3 135 #error "SYSPLLCLKSEL: Value out of range!"
sahilmgandhi 18:6a4db94011d3 136 #endif
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
sahilmgandhi 18:6a4db94011d3 139 #error "SYSPLLCTRL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 140 #endif
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
sahilmgandhi 18:6a4db94011d3 143 #error "MAINCLKSEL: Invalid values of reserved bits!"
sahilmgandhi 18:6a4db94011d3 144 #endif
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
sahilmgandhi 18:6a4db94011d3 147 #error "SYSAHBCLKDIV: Value out of range!"
sahilmgandhi 18:6a4db94011d3 148 #endif
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 152 DEFINES
sahilmgandhi 18:6a4db94011d3 153 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 156 Define clocks
sahilmgandhi 18:6a4db94011d3 157 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 158 #define __XTAL (12000000UL) /* Oscillator frequency */
sahilmgandhi 18:6a4db94011d3 159 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
sahilmgandhi 18:6a4db94011d3 160 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
sahilmgandhi 18:6a4db94011d3 164 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 167 #if (__FREQSEL == 0)
sahilmgandhi 18:6a4db94011d3 168 #define __WDT_OSC_CLK ( 0) /* undefined */
sahilmgandhi 18:6a4db94011d3 169 #elif (__FREQSEL == 1)
sahilmgandhi 18:6a4db94011d3 170 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 171 #elif (__FREQSEL == 2)
sahilmgandhi 18:6a4db94011d3 172 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 173 #elif (__FREQSEL == 3)
sahilmgandhi 18:6a4db94011d3 174 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 175 #elif (__FREQSEL == 4)
sahilmgandhi 18:6a4db94011d3 176 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 177 #elif (__FREQSEL == 5)
sahilmgandhi 18:6a4db94011d3 178 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 179 #elif (__FREQSEL == 6)
sahilmgandhi 18:6a4db94011d3 180 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 181 #elif (__FREQSEL == 7)
sahilmgandhi 18:6a4db94011d3 182 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 183 #elif (__FREQSEL == 8)
sahilmgandhi 18:6a4db94011d3 184 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 185 #elif (__FREQSEL == 9)
sahilmgandhi 18:6a4db94011d3 186 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 187 #elif (__FREQSEL == 10)
sahilmgandhi 18:6a4db94011d3 188 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 189 #elif (__FREQSEL == 11)
sahilmgandhi 18:6a4db94011d3 190 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 191 #elif (__FREQSEL == 12)
sahilmgandhi 18:6a4db94011d3 192 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 193 #elif (__FREQSEL == 13)
sahilmgandhi 18:6a4db94011d3 194 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 195 #elif (__FREQSEL == 14)
sahilmgandhi 18:6a4db94011d3 196 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 197 #else
sahilmgandhi 18:6a4db94011d3 198 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
sahilmgandhi 18:6a4db94011d3 199 #endif
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 /* sys_pllclkin calculation */
sahilmgandhi 18:6a4db94011d3 202 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 203 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 204 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 205 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 206 #else
sahilmgandhi 18:6a4db94011d3 207 #define __SYS_PLLCLKIN (0)
sahilmgandhi 18:6a4db94011d3 208 #endif
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 /* main clock calculation */
sahilmgandhi 18:6a4db94011d3 213 #if ((MAINCLKSEL_Val & 0x03) == 0)
sahilmgandhi 18:6a4db94011d3 214 #define __MAIN_CLOCK (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 215 #elif ((MAINCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 216 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
sahilmgandhi 18:6a4db94011d3 217 #elif ((MAINCLKSEL_Val & 0x03) == 2)
sahilmgandhi 18:6a4db94011d3 218 #if (__FREQSEL == 0)
sahilmgandhi 18:6a4db94011d3 219 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
sahilmgandhi 18:6a4db94011d3 220 #else
sahilmgandhi 18:6a4db94011d3 221 #define __MAIN_CLOCK (__WDT_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 222 #endif
sahilmgandhi 18:6a4db94011d3 223 #elif ((MAINCLKSEL_Val & 0x03) == 3)
sahilmgandhi 18:6a4db94011d3 224 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
sahilmgandhi 18:6a4db94011d3 225 #else
sahilmgandhi 18:6a4db94011d3 226 #define __MAIN_CLOCK (0)
sahilmgandhi 18:6a4db94011d3 227 #endif
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 #else
sahilmgandhi 18:6a4db94011d3 232 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
sahilmgandhi 18:6a4db94011d3 233 #endif // CLOCK_SETUP
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 237 Clock Variable definitions
sahilmgandhi 18:6a4db94011d3 238 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 239 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 /*----------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 243 Clock functions
sahilmgandhi 18:6a4db94011d3 244 *----------------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 245 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
sahilmgandhi 18:6a4db94011d3 246 {
sahilmgandhi 18:6a4db94011d3 247 uint32_t wdt_osc = 0;
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 /* Determine clock frequency according to clock register values */
sahilmgandhi 18:6a4db94011d3 250 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
sahilmgandhi 18:6a4db94011d3 251 case 0: wdt_osc = 0; break;
sahilmgandhi 18:6a4db94011d3 252 case 1: wdt_osc = 500000; break;
sahilmgandhi 18:6a4db94011d3 253 case 2: wdt_osc = 800000; break;
sahilmgandhi 18:6a4db94011d3 254 case 3: wdt_osc = 1100000; break;
sahilmgandhi 18:6a4db94011d3 255 case 4: wdt_osc = 1400000; break;
sahilmgandhi 18:6a4db94011d3 256 case 5: wdt_osc = 1600000; break;
sahilmgandhi 18:6a4db94011d3 257 case 6: wdt_osc = 1800000; break;
sahilmgandhi 18:6a4db94011d3 258 case 7: wdt_osc = 2000000; break;
sahilmgandhi 18:6a4db94011d3 259 case 8: wdt_osc = 2200000; break;
sahilmgandhi 18:6a4db94011d3 260 case 9: wdt_osc = 2400000; break;
sahilmgandhi 18:6a4db94011d3 261 case 10: wdt_osc = 2600000; break;
sahilmgandhi 18:6a4db94011d3 262 case 11: wdt_osc = 2700000; break;
sahilmgandhi 18:6a4db94011d3 263 case 12: wdt_osc = 2900000; break;
sahilmgandhi 18:6a4db94011d3 264 case 13: wdt_osc = 3100000; break;
sahilmgandhi 18:6a4db94011d3 265 case 14: wdt_osc = 3200000; break;
sahilmgandhi 18:6a4db94011d3 266 case 15: wdt_osc = 3400000; break;
sahilmgandhi 18:6a4db94011d3 267 }
sahilmgandhi 18:6a4db94011d3 268 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 271 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 272 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 273 break;
sahilmgandhi 18:6a4db94011d3 274 case 1: /* Input Clock to System PLL */
sahilmgandhi 18:6a4db94011d3 275 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 276 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 277 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 278 break;
sahilmgandhi 18:6a4db94011d3 279 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 280 SystemCoreClock = __SYS_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 281 break;
sahilmgandhi 18:6a4db94011d3 282 case 2: /* Reserved */
sahilmgandhi 18:6a4db94011d3 283 case 3: /* Reserved */
sahilmgandhi 18:6a4db94011d3 284 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 285 break;
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287 break;
sahilmgandhi 18:6a4db94011d3 288 case 2: /* WDT Oscillator */
sahilmgandhi 18:6a4db94011d3 289 SystemCoreClock = wdt_osc;
sahilmgandhi 18:6a4db94011d3 290 break;
sahilmgandhi 18:6a4db94011d3 291 case 3: /* System PLL Clock Out */
sahilmgandhi 18:6a4db94011d3 292 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
sahilmgandhi 18:6a4db94011d3 293 case 0: /* Internal RC oscillator */
sahilmgandhi 18:6a4db94011d3 294 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
sahilmgandhi 18:6a4db94011d3 295 SystemCoreClock = __IRC_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 296 } else {
sahilmgandhi 18:6a4db94011d3 297 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 298 }
sahilmgandhi 18:6a4db94011d3 299 break;
sahilmgandhi 18:6a4db94011d3 300 case 1: /* System oscillator */
sahilmgandhi 18:6a4db94011d3 301 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
sahilmgandhi 18:6a4db94011d3 302 SystemCoreClock = __SYS_OSC_CLK;
sahilmgandhi 18:6a4db94011d3 303 } else {
sahilmgandhi 18:6a4db94011d3 304 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
sahilmgandhi 18:6a4db94011d3 305 }
sahilmgandhi 18:6a4db94011d3 306 break;
sahilmgandhi 18:6a4db94011d3 307 case 2: /* Reserved */
sahilmgandhi 18:6a4db94011d3 308 case 3: /* Reserved */
sahilmgandhi 18:6a4db94011d3 309 SystemCoreClock = 0;
sahilmgandhi 18:6a4db94011d3 310 break;
sahilmgandhi 18:6a4db94011d3 311 }
sahilmgandhi 18:6a4db94011d3 312 break;
sahilmgandhi 18:6a4db94011d3 313 }
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 }
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 /**
sahilmgandhi 18:6a4db94011d3 320 * Initialize the system
sahilmgandhi 18:6a4db94011d3 321 *
sahilmgandhi 18:6a4db94011d3 322 * @param none
sahilmgandhi 18:6a4db94011d3 323 * @return none
sahilmgandhi 18:6a4db94011d3 324 *
sahilmgandhi 18:6a4db94011d3 325 * @brief Setup the microcontroller system.
sahilmgandhi 18:6a4db94011d3 326 * Initialize the System.
sahilmgandhi 18:6a4db94011d3 327 */
sahilmgandhi 18:6a4db94011d3 328 void SystemInit (void) {
sahilmgandhi 18:6a4db94011d3 329 volatile uint32_t i;
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 #if (CLOCK_SETUP) /* Clock Setup */
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
sahilmgandhi 18:6a4db94011d3 334 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
sahilmgandhi 18:6a4db94011d3 335 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
sahilmgandhi 18:6a4db94011d3 336 for (i = 0; i < 200; i++) __NOP();
sahilmgandhi 18:6a4db94011d3 337 #endif
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
sahilmgandhi 18:6a4db94011d3 340 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
sahilmgandhi 18:6a4db94011d3 341 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
sahilmgandhi 18:6a4db94011d3 342 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
sahilmgandhi 18:6a4db94011d3 343 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 344 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
sahilmgandhi 18:6a4db94011d3 345 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
sahilmgandhi 18:6a4db94011d3 346 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
sahilmgandhi 18:6a4db94011d3 347 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
sahilmgandhi 18:6a4db94011d3 348 #endif
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 #if (((MAINCLKSEL_Val & 0x03) == 2) )
sahilmgandhi 18:6a4db94011d3 351 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
sahilmgandhi 18:6a4db94011d3 352 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
sahilmgandhi 18:6a4db94011d3 353 for (i = 0; i < 200; i++) __NOP();
sahilmgandhi 18:6a4db94011d3 354 #endif
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
sahilmgandhi 18:6a4db94011d3 357 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
sahilmgandhi 18:6a4db94011d3 358 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
sahilmgandhi 18:6a4db94011d3 359 LPC_SYSCON->MAINCLKUEN = 0x01;
sahilmgandhi 18:6a4db94011d3 360 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
sahilmgandhi 18:6a4db94011d3 363 #endif
sahilmgandhi 18:6a4db94011d3 364 /* System clock to the IOCON needs to be enabled or
sahilmgandhi 18:6a4db94011d3 365 most of the I/O related peripherals won't work. */
sahilmgandhi 18:6a4db94011d3 366 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
sahilmgandhi 18:6a4db94011d3 367 }