Mouse code for the MacroRat
mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | #! armcc -E |
sahilmgandhi | 18:6a4db94011d3 | 2 | |
sahilmgandhi | 18:6a4db94011d3 | 3 | #if !defined(MBED_APP_START) |
sahilmgandhi | 18:6a4db94011d3 | 4 | #define MBED_APP_START 0x00000000 |
sahilmgandhi | 18:6a4db94011d3 | 5 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 6 | |
sahilmgandhi | 18:6a4db94011d3 | 7 | #if !defined(MBED_APP_SIZE) |
sahilmgandhi | 18:6a4db94011d3 | 8 | #define MBED_APP_SIZE 0x00080000 |
sahilmgandhi | 18:6a4db94011d3 | 9 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 10 | |
sahilmgandhi | 18:6a4db94011d3 | 11 | LR_IROM1 MBED_APP_START { |
sahilmgandhi | 18:6a4db94011d3 | 12 | ER_IROM1 MBED_APP_START { ; load address = execution address |
sahilmgandhi | 18:6a4db94011d3 | 13 | *(RESET, +First) |
sahilmgandhi | 18:6a4db94011d3 | 14 | *(InRoot$$Sections) |
sahilmgandhi | 18:6a4db94011d3 | 15 | .ANY (+RO) |
sahilmgandhi | 18:6a4db94011d3 | 16 | } |
sahilmgandhi | 18:6a4db94011d3 | 17 | |
sahilmgandhi | 18:6a4db94011d3 | 18 | ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned |
sahilmgandhi | 18:6a4db94011d3 | 19 | ; uvisor-lib.a (+RW +ZI) |
sahilmgandhi | 18:6a4db94011d3 | 20 | ;} |
sahilmgandhi | 18:6a4db94011d3 | 21 | |
sahilmgandhi | 18:6a4db94011d3 | 22 | ARM_LIB_STACK 0x20000000 EMPTY 0x800 { |
sahilmgandhi | 18:6a4db94011d3 | 23 | } |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors |
sahilmgandhi | 18:6a4db94011d3 | 26 | } |
sahilmgandhi | 18:6a4db94011d3 | 27 | |
sahilmgandhi | 18:6a4db94011d3 | 28 | RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned |
sahilmgandhi | 18:6a4db94011d3 | 29 | .ANY (+RW +ZI) |
sahilmgandhi | 18:6a4db94011d3 | 30 | } |
sahilmgandhi | 18:6a4db94011d3 | 31 | |
sahilmgandhi | 18:6a4db94011d3 | 32 | ; Extern SRAM for HEAP |
sahilmgandhi | 18:6a4db94011d3 | 33 | ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { |
sahilmgandhi | 18:6a4db94011d3 | 34 | } |
sahilmgandhi | 18:6a4db94011d3 | 35 | } |
sahilmgandhi | 18:6a4db94011d3 | 36 | ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ; 512 KB APROM |
sahilmgandhi | 18:6a4db94011d3 | 37 | ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal) |
sahilmgandhi | 18:6a4db94011d3 | 38 |