MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_adc.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file adc.h
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 22 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 14/10/06 5:51p $
sahilmgandhi 18:6a4db94011d3 6 * @brief NUC472/NUC442 ADC driver header file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #ifndef __ADC_H__
sahilmgandhi 18:6a4db94011d3 12 #define __ADC_H__
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 15 extern "C"
sahilmgandhi 18:6a4db94011d3 16 {
sahilmgandhi 18:6a4db94011d3 17 #endif
sahilmgandhi 18:6a4db94011d3 18
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
sahilmgandhi 18:6a4db94011d3 21 @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 /** @addtogroup NUC472_442_ADC_Driver ADC Driver
sahilmgandhi 18:6a4db94011d3 25 @{
sahilmgandhi 18:6a4db94011d3 26 */
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 /** @addtogroup NUC472_442_ADC_EXPORTED_CONSTANTS ADC Exported Constants
sahilmgandhi 18:6a4db94011d3 29 @{
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #define ADC_CH_0_MASK (1UL << 0) /*!< ADC channel 0 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 33 #define ADC_CH_1_MASK (1UL << 1) /*!< ADC channel 1 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 34 #define ADC_CH_2_MASK (1UL << 2) /*!< ADC channel 2 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 35 #define ADC_CH_3_MASK (1UL << 3) /*!< ADC channel 3 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 36 #define ADC_CH_4_MASK (1UL << 4) /*!< ADC channel 4 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 37 #define ADC_CH_5_MASK (1UL << 5) /*!< ADC channel 5 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 38 #define ADC_CH_6_MASK (1UL << 6) /*!< ADC channel 6 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 39 #define ADC_CH_7_MASK (1UL << 7) /*!< ADC channel 7 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 40 #define ADC_CH_8_MASK (1UL << 8) /*!< ADC channel 8 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 41 #define ADC_CH_9_MASK (1UL << 9) /*!< ADC channel 9 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 42 #define ADC_CH_10_MASK (1UL << 10) /*!< ADC channel 10 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 43 #define ADC_CH_11_MASK (1UL << 11) /*!< ADC channel 11 mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 44 #define ADC_CH_BG_MASK (1UL << 16) /*!< ADC channel 12 (band-gap ) mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 45 #define ADC_CH_TS_MASK (1UL << 17) /*!< ADC channel 13 (temperature sensor) mask \hideinitializer */
sahilmgandhi 18:6a4db94011d3 46 #define ADC_CMP_LESS_THAN (0UL) /*!< ADC compare condition less than \hideinitializer */
sahilmgandhi 18:6a4db94011d3 47 #define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMP0_CMPCOND_Msk) /*!< ADC compare condition greater or equal to \hideinitializer */
sahilmgandhi 18:6a4db94011d3 48 #define ADC_TRIGGER_BY_EXT_PIN (0UL) /*!< ADC trigger by STADC pin \hideinitializer */
sahilmgandhi 18:6a4db94011d3 49 #define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk) /*!< ADC trigger by PWM events \hideinitializer */
sahilmgandhi 18:6a4db94011d3 50 #define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin low level trigger ADC \hideinitializer */
sahilmgandhi 18:6a4db94011d3 51 #define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin high level trigger ADC \hideinitializer */
sahilmgandhi 18:6a4db94011d3 52 #define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin falling edge trigger ADC \hideinitializer */
sahilmgandhi 18:6a4db94011d3 53 #define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin rising edge trigger ADC \hideinitializer */
sahilmgandhi 18:6a4db94011d3 54 #define ADC_ADF_INT (ADC_STATUS0_ADIF_Msk) /*!< ADC convert complete interrupt \hideinitializer */
sahilmgandhi 18:6a4db94011d3 55 #define ADC_CMP0_INT (ADC_STATUS0_ADCMPF0_Msk) /*!< ADC comparator 0 interrupt \hideinitializer */
sahilmgandhi 18:6a4db94011d3 56 #define ADC_CMP1_INT (ADC_STATUS0_ADCMPF1_Msk) /*!< ADC comparator 1 interrupt \hideinitializer */
sahilmgandhi 18:6a4db94011d3 57 #define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CTL_DIFFEN_Pos) /*!< ADC input mode set to single end \hideinitializer */
sahilmgandhi 18:6a4db94011d3 58 #define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CTL_DIFFEN_Pos) /*!< ADC input mode set to differential \hideinitializer */
sahilmgandhi 18:6a4db94011d3 59 #define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CTL_OPMODE_Pos) /*!< ADC operation mode set to single conversion \hideinitializer */
sahilmgandhi 18:6a4db94011d3 60 #define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CTL_OPMODE_Pos) /*!< ADC operation mode set to single cycle scan \hideinitializer */
sahilmgandhi 18:6a4db94011d3 61 #define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CTL_OPMODE_Pos) /*!< ADC operation mode set to continuous scan \hideinitializer */
sahilmgandhi 18:6a4db94011d3 62 #define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CTL_OPMODE_Pos) /*!< ADC differential mode output format with unsigned \hideinitializer */
sahilmgandhi 18:6a4db94011d3 63 #define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CTL_OPMODE_Pos) /*!< ADC differential mode output format with 2's complement \hideinitializer */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /*@}*/ /* end of group NUC472_442_ADC_EXPORTED_CONSTANTS */
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 /** @addtogroup NUC472_442_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
sahilmgandhi 18:6a4db94011d3 69 @{
sahilmgandhi 18:6a4db94011d3 70 */
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 /**
sahilmgandhi 18:6a4db94011d3 73 * @brief Get the latest ADC conversion data
sahilmgandhi 18:6a4db94011d3 74 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 75 * @param[in] u32ChNum Channel number
sahilmgandhi 18:6a4db94011d3 76 * @return Latest ADC conversion data
sahilmgandhi 18:6a4db94011d3 77 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79 #define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ( ADC->DAT[u32ChNum] & ADC_DAT0_RESULT_Msk)
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /**
sahilmgandhi 18:6a4db94011d3 82 * @brief Return the user-specified interrupt flags
sahilmgandhi 18:6a4db94011d3 83 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 84 * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
sahilmgandhi 18:6a4db94011d3 85 * - \ref ADC_ADF_INT
sahilmgandhi 18:6a4db94011d3 86 * - \ref ADC_CMP0_INT
sahilmgandhi 18:6a4db94011d3 87 * - \ref ADC_CMP1_INT
sahilmgandhi 18:6a4db94011d3 88 * @return User specified interrupt flags
sahilmgandhi 18:6a4db94011d3 89 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 90 */
sahilmgandhi 18:6a4db94011d3 91 #define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->STATUS0 & (u32Mask))
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /**
sahilmgandhi 18:6a4db94011d3 94 * @brief This macro clear the selected interrupt status bits
sahilmgandhi 18:6a4db94011d3 95 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 96 * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
sahilmgandhi 18:6a4db94011d3 97 * - \ref ADC_ADF_INT
sahilmgandhi 18:6a4db94011d3 98 * - \ref ADC_CMP0_INT
sahilmgandhi 18:6a4db94011d3 99 * - \ref ADC_CMP1_INT
sahilmgandhi 18:6a4db94011d3 100 * @return None
sahilmgandhi 18:6a4db94011d3 101 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103 #define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->STATUS0 = (ADC->STATUS0 & ~(ADC_STATUS0_ADIF_Msk | \
sahilmgandhi 18:6a4db94011d3 104 ADC_STATUS0_ADCMPF0_Msk | \
sahilmgandhi 18:6a4db94011d3 105 ADC_STATUS0_ADCMPF1_Msk)) | (u32Mask))
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 /**
sahilmgandhi 18:6a4db94011d3 108 * @brief Get the busy state of ADC
sahilmgandhi 18:6a4db94011d3 109 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 110 * @return busy state of ADC
sahilmgandhi 18:6a4db94011d3 111 * @retval 0 ADC is not busy
sahilmgandhi 18:6a4db94011d3 112 * @retval 1 ADC is busy
sahilmgandhi 18:6a4db94011d3 113 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 114 */
sahilmgandhi 18:6a4db94011d3 115 #define ADC_IS_BUSY(adc) (ADC->STATUS0 & ADC_STATUS0_BUSY_Msk ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 /**
sahilmgandhi 18:6a4db94011d3 118 * @brief Check if the ADC conversion data is over written or not
sahilmgandhi 18:6a4db94011d3 119 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 120 * @param[in] u32ChNum Currently not used
sahilmgandhi 18:6a4db94011d3 121 * @return Over run state of ADC data
sahilmgandhi 18:6a4db94011d3 122 * @retval 0 ADC data is not overrun
sahilmgandhi 18:6a4db94011d3 123 * @retval 1 ADC data us overrun
sahilmgandhi 18:6a4db94011d3 124 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 125 */
sahilmgandhi 18:6a4db94011d3 126 #define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->STATUS1 & ( 1 << (ADC_STATUS1_OV_Pos + u32ChNum)) ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /**
sahilmgandhi 18:6a4db94011d3 129 * @brief Check if the ADC conversion data is valid or not
sahilmgandhi 18:6a4db94011d3 130 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 131 * @param[in] u32ChNum Currently not used
sahilmgandhi 18:6a4db94011d3 132 * @return Valid state of ADC data
sahilmgandhi 18:6a4db94011d3 133 * @retval 0 ADC data is not valid
sahilmgandhi 18:6a4db94011d3 134 * @retval 1 ADC data us valid
sahilmgandhi 18:6a4db94011d3 135 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 136 */
sahilmgandhi 18:6a4db94011d3 137 #define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->STATUS1 & ( 1 << (ADC_STATUS1_VALID_Pos + u32ChNum)) ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /**
sahilmgandhi 18:6a4db94011d3 140 * @brief Power down ADC module
sahilmgandhi 18:6a4db94011d3 141 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 142 * @return None
sahilmgandhi 18:6a4db94011d3 143 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145 #define ADC_POWER_DOWN(adc) (ADC->CTL &= ~ADC_CTL_ADCEN_Msk)
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 /**
sahilmgandhi 18:6a4db94011d3 148 * @brief Power on ADC module
sahilmgandhi 18:6a4db94011d3 149 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 150 * @return None
sahilmgandhi 18:6a4db94011d3 151 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 152 */
sahilmgandhi 18:6a4db94011d3 153 #define ADC_POWER_ON(adc) (ADC->CTL |= ADC_CTL_ADCEN_Msk)
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 /**
sahilmgandhi 18:6a4db94011d3 156 * @brief Configure the comparator 0 and enable it
sahilmgandhi 18:6a4db94011d3 157 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 158 * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
sahilmgandhi 18:6a4db94011d3 159 * @param[in] u32Condition Specifies the compare condition
sahilmgandhi 18:6a4db94011d3 160 * - \ref ADC_CMP_LESS_THAN
sahilmgandhi 18:6a4db94011d3 161 * - \ref ADC_CMP_GREATER_OR_EQUAL_TO
sahilmgandhi 18:6a4db94011d3 162 * @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
sahilmgandhi 18:6a4db94011d3 163 * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
sahilmgandhi 18:6a4db94011d3 164 * @return None
sahilmgandhi 18:6a4db94011d3 165 * @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
sahilmgandhi 18:6a4db94011d3 166 * Means ADC will assert comparator 0 flag if channel 5 conversion result is
sahilmgandhi 18:6a4db94011d3 167 * greater or equal to 0x800 for 10 times continuously.
sahilmgandhi 18:6a4db94011d3 168 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 169 */
sahilmgandhi 18:6a4db94011d3 170 #define ADC_ENABLE_CMP0(adc, \
sahilmgandhi 18:6a4db94011d3 171 u32ChNum, \
sahilmgandhi 18:6a4db94011d3 172 u32Condition, \
sahilmgandhi 18:6a4db94011d3 173 u32Data, \
sahilmgandhi 18:6a4db94011d3 174 u32MatchCount) (ADC->CMP[0] = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | \
sahilmgandhi 18:6a4db94011d3 175 (u32Condition) | \
sahilmgandhi 18:6a4db94011d3 176 ((u32Data) << ADC_CMP0_CMPDAT_Pos) | \
sahilmgandhi 18:6a4db94011d3 177 (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) |\
sahilmgandhi 18:6a4db94011d3 178 ADC_CMP0_ADCMPEN_Msk)
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 /**
sahilmgandhi 18:6a4db94011d3 181 * @brief Disable comparator 0
sahilmgandhi 18:6a4db94011d3 182 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 183 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 184 */
sahilmgandhi 18:6a4db94011d3 185 #define ADC_DISABLE_CMP0(adc) (ADC->CMP[0] = 0)
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /**
sahilmgandhi 18:6a4db94011d3 188 * @brief Configure the comparator 1 and enable it
sahilmgandhi 18:6a4db94011d3 189 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 190 * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
sahilmgandhi 18:6a4db94011d3 191 * @param[in] u32Condition Specifies the compare condition
sahilmgandhi 18:6a4db94011d3 192 * - \ref ADC_CMP_LESS_THAN
sahilmgandhi 18:6a4db94011d3 193 * - \ref ADC_CMP_GREATER_OR_EQUAL_TO
sahilmgandhi 18:6a4db94011d3 194 * @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
sahilmgandhi 18:6a4db94011d3 195 * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
sahilmgandhi 18:6a4db94011d3 196 * @return None
sahilmgandhi 18:6a4db94011d3 197 * @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
sahilmgandhi 18:6a4db94011d3 198 * Means ADC will assert comparator 1 flag if channel 5 conversion result is
sahilmgandhi 18:6a4db94011d3 199 * greater or equal to 0x800 for 10 times continuously.
sahilmgandhi 18:6a4db94011d3 200 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 201 */
sahilmgandhi 18:6a4db94011d3 202 #define ADC_ENABLE_CMP1(adc, \
sahilmgandhi 18:6a4db94011d3 203 u32ChNum, \
sahilmgandhi 18:6a4db94011d3 204 u32Condition, \
sahilmgandhi 18:6a4db94011d3 205 u32Data, \
sahilmgandhi 18:6a4db94011d3 206 u32MatchCount) (ADC->CMP[1] = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | \
sahilmgandhi 18:6a4db94011d3 207 (u32Condition) | \
sahilmgandhi 18:6a4db94011d3 208 ((u32Data) << ADC_CMP1_CMPDAT_Pos) | \
sahilmgandhi 18:6a4db94011d3 209 ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) |\
sahilmgandhi 18:6a4db94011d3 210 ADC_CMP1_ADCMPEN_Msk)
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 /**
sahilmgandhi 18:6a4db94011d3 213 * @brief Disable comparator 1
sahilmgandhi 18:6a4db94011d3 214 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 215 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 216 */
sahilmgandhi 18:6a4db94011d3 217 #define ADC_DISABLE_CMP1(adc) (ADC->CMP[1] = 0)
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /**
sahilmgandhi 18:6a4db94011d3 220 * @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
sahilmgandhi 18:6a4db94011d3 221 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 222 * @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
sahilmgandhi 18:6a4db94011d3 223 * @return None
sahilmgandhi 18:6a4db94011d3 224 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 225 */
sahilmgandhi 18:6a4db94011d3 226 #define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN_Msk) | (u32Mask))
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /**
sahilmgandhi 18:6a4db94011d3 229 * @brief Start the A/D conversion.
sahilmgandhi 18:6a4db94011d3 230 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 231 * @return None
sahilmgandhi 18:6a4db94011d3 232 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 233 */
sahilmgandhi 18:6a4db94011d3 234 #define ADC_START_CONV(adc) (ADC->CTL |= ADC_CTL_SWTRG_Msk)
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 /**
sahilmgandhi 18:6a4db94011d3 237 * @brief Stop the A/D conversion.
sahilmgandhi 18:6a4db94011d3 238 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 239 * @return None
sahilmgandhi 18:6a4db94011d3 240 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 241 */
sahilmgandhi 18:6a4db94011d3 242 #define ADC_STOP_CONV(adc) (ADC->CTL &= ~ADC_CTL_SWTRG_Msk)
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /**
sahilmgandhi 18:6a4db94011d3 245 * @brief Set the output format in differential input mode.
sahilmgandhi 18:6a4db94011d3 246 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 247 * @param[in] u32Format Differential input mode output format. Valid values are:
sahilmgandhi 18:6a4db94011d3 248 * - \ref ADC_DMODE_OUT_FORMAT_UNSIGNED
sahilmgandhi 18:6a4db94011d3 249 * - \ref ADC_DMODE_OUT_FORMAT_2COMPLEMENT
sahilmgandhi 18:6a4db94011d3 250 * @return None
sahilmgandhi 18:6a4db94011d3 251 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 252 */
sahilmgandhi 18:6a4db94011d3 253 #define ADC_SET_DMOF(adc, u32Format) (ADC->CTL = (ADC->CTL & ~ADC_CTL_DMOF_Msk) | u32Format)
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /**
sahilmgandhi 18:6a4db94011d3 256 * @brief Enable PDMA transfer.
sahilmgandhi 18:6a4db94011d3 257 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 258 * @return None
sahilmgandhi 18:6a4db94011d3 259 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 260 */
sahilmgandhi 18:6a4db94011d3 261 #define ADC_ENABLE_PDMA(adc) (ADC->CTL |= ADC_CTL_PDMAEN_Msk)
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 /**
sahilmgandhi 18:6a4db94011d3 264 * @brief Disable PDMA transfer.
sahilmgandhi 18:6a4db94011d3 265 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 266 * @return None
sahilmgandhi 18:6a4db94011d3 267 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 268 */
sahilmgandhi 18:6a4db94011d3 269 #define ADC_DISABLE_PDMA(adc) (ADC->CTL &= ~ADC_CTL_PDMAEN_Msk)
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 /**
sahilmgandhi 18:6a4db94011d3 272 * @brief Get PDMA current transfer data
sahilmgandhi 18:6a4db94011d3 273 * @param[in] adc Base address of ADC module
sahilmgandhi 18:6a4db94011d3 274 * @return PDMA current transfer data
sahilmgandhi 18:6a4db94011d3 275 * \hideinitializer
sahilmgandhi 18:6a4db94011d3 276 */
sahilmgandhi 18:6a4db94011d3 277 #define ADC_GET_PDMA_DATA(adc) ( ADC->CURDAT & ADC_CURDAT_CURDAT_Msk)
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 void ADC_Open(ADC_T *adc,
sahilmgandhi 18:6a4db94011d3 280 uint32_t u32InputMode,
sahilmgandhi 18:6a4db94011d3 281 uint32_t u32OpMode,
sahilmgandhi 18:6a4db94011d3 282 uint32_t u32ChMask);
sahilmgandhi 18:6a4db94011d3 283 void ADC_Close(ADC_T *adc);
sahilmgandhi 18:6a4db94011d3 284 void ADC_EnableHWTrigger(ADC_T *adc,
sahilmgandhi 18:6a4db94011d3 285 uint32_t u32Source,
sahilmgandhi 18:6a4db94011d3 286 uint32_t u32Param);
sahilmgandhi 18:6a4db94011d3 287 void ADC_DisableHWTrigger(ADC_T *adc);
sahilmgandhi 18:6a4db94011d3 288 void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 289 void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 /*@}*/ /* end of group NUC472_442_ADC_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /*@}*/ /* end of group NUC472_442_ADC_Driver */
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 /*@}*/ /* end of group NUC472_442_Device_Driver */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301 #endif
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 #endif //__ADC_H__
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/