Mouse code for the MacroRat
mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @file spi.c |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @version V3.00 |
sahilmgandhi | 18:6a4db94011d3 | 4 | * $Revision: 11 $ |
sahilmgandhi | 18:6a4db94011d3 | 5 | * $Date: 15/08/11 10:26a $ |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @brief M451 series SPI driver source file |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * @note |
sahilmgandhi | 18:6a4db94011d3 | 9 | * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 10 | *****************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 11 | #include "M451Series.h" |
sahilmgandhi | 18:6a4db94011d3 | 12 | /** @addtogroup Standard_Driver Standard Driver |
sahilmgandhi | 18:6a4db94011d3 | 13 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 14 | */ |
sahilmgandhi | 18:6a4db94011d3 | 15 | |
sahilmgandhi | 18:6a4db94011d3 | 16 | /** @addtogroup SPI_Driver SPI Driver |
sahilmgandhi | 18:6a4db94011d3 | 17 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 18 | */ |
sahilmgandhi | 18:6a4db94011d3 | 19 | |
sahilmgandhi | 18:6a4db94011d3 | 20 | |
sahilmgandhi | 18:6a4db94011d3 | 21 | /** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions |
sahilmgandhi | 18:6a4db94011d3 | 22 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 23 | */ |
sahilmgandhi | 18:6a4db94011d3 | 24 | |
sahilmgandhi | 18:6a4db94011d3 | 25 | /** |
sahilmgandhi | 18:6a4db94011d3 | 26 | * @brief This function make SPI module be ready to transfer. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 28 | * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) |
sahilmgandhi | 18:6a4db94011d3 | 29 | * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) |
sahilmgandhi | 18:6a4db94011d3 | 30 | * @param[in] u32DataWidth Decides the data width of a SPI transaction. |
sahilmgandhi | 18:6a4db94011d3 | 31 | * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. |
sahilmgandhi | 18:6a4db94011d3 | 32 | * @return Actual frequency of SPI peripheral clock. |
sahilmgandhi | 18:6a4db94011d3 | 33 | * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic |
sahilmgandhi | 18:6a4db94011d3 | 34 | * slave selection function is disabled. |
sahilmgandhi | 18:6a4db94011d3 | 35 | * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. |
sahilmgandhi | 18:6a4db94011d3 | 36 | * The actual clock rate may be different from the target SPI clock rate. |
sahilmgandhi | 18:6a4db94011d3 | 37 | * For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the |
sahilmgandhi | 18:6a4db94011d3 | 38 | * actual SPI clock rate will be 6MHz. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. |
sahilmgandhi | 18:6a4db94011d3 | 40 | * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. |
sahilmgandhi | 18:6a4db94011d3 | 41 | * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. |
sahilmgandhi | 18:6a4db94011d3 | 42 | * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. |
sahilmgandhi | 18:6a4db94011d3 | 43 | */ |
sahilmgandhi | 18:6a4db94011d3 | 44 | uint32_t SPI_Open(SPI_T *spi, |
sahilmgandhi | 18:6a4db94011d3 | 45 | uint32_t u32MasterSlave, |
sahilmgandhi | 18:6a4db94011d3 | 46 | uint32_t u32SPIMode, |
sahilmgandhi | 18:6a4db94011d3 | 47 | uint32_t u32DataWidth, |
sahilmgandhi | 18:6a4db94011d3 | 48 | uint32_t u32BusClock) |
sahilmgandhi | 18:6a4db94011d3 | 49 | { |
sahilmgandhi | 18:6a4db94011d3 | 50 | uint32_t u32ClkSrc = 0, u32Div, u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | if((spi == SPI1) || (spi == SPI2)) |
sahilmgandhi | 18:6a4db94011d3 | 53 | /* Disable I2S mode */ |
sahilmgandhi | 18:6a4db94011d3 | 54 | spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 55 | |
sahilmgandhi | 18:6a4db94011d3 | 56 | if(u32DataWidth == 32) |
sahilmgandhi | 18:6a4db94011d3 | 57 | u32DataWidth = 0; |
sahilmgandhi | 18:6a4db94011d3 | 58 | |
sahilmgandhi | 18:6a4db94011d3 | 59 | /* Get system clock frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | u32HCLKFreq = CLK_GetHCLKFreq(); |
sahilmgandhi | 18:6a4db94011d3 | 61 | |
sahilmgandhi | 18:6a4db94011d3 | 62 | if(u32MasterSlave == SPI_MASTER) |
sahilmgandhi | 18:6a4db94011d3 | 63 | { |
sahilmgandhi | 18:6a4db94011d3 | 64 | /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ |
sahilmgandhi | 18:6a4db94011d3 | 65 | spi->SSCTL = SPI_SS_ACTIVE_LOW; |
sahilmgandhi | 18:6a4db94011d3 | 66 | |
sahilmgandhi | 18:6a4db94011d3 | 67 | /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 69 | |
sahilmgandhi | 18:6a4db94011d3 | 70 | if(u32BusClock >= u32HCLKFreq) |
sahilmgandhi | 18:6a4db94011d3 | 71 | { |
sahilmgandhi | 18:6a4db94011d3 | 72 | /* Select PCLK as the clock source of SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | if(spi == SPI0) |
sahilmgandhi | 18:6a4db94011d3 | 74 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0; |
sahilmgandhi | 18:6a4db94011d3 | 75 | else if(spi == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 76 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1; |
sahilmgandhi | 18:6a4db94011d3 | 77 | else |
sahilmgandhi | 18:6a4db94011d3 | 78 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0; |
sahilmgandhi | 18:6a4db94011d3 | 79 | } |
sahilmgandhi | 18:6a4db94011d3 | 80 | |
sahilmgandhi | 18:6a4db94011d3 | 81 | /* Check clock source of SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | if(spi == SPI0) |
sahilmgandhi | 18:6a4db94011d3 | 83 | { |
sahilmgandhi | 18:6a4db94011d3 | 84 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 85 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 86 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 87 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0) |
sahilmgandhi | 18:6a4db94011d3 | 89 | { |
sahilmgandhi | 18:6a4db94011d3 | 90 | /* Clock source is PCLK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 92 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 93 | else |
sahilmgandhi | 18:6a4db94011d3 | 94 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 95 | } |
sahilmgandhi | 18:6a4db94011d3 | 96 | else |
sahilmgandhi | 18:6a4db94011d3 | 97 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 98 | } |
sahilmgandhi | 18:6a4db94011d3 | 99 | else if(spi == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 100 | { |
sahilmgandhi | 18:6a4db94011d3 | 101 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 102 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 103 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 104 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1) |
sahilmgandhi | 18:6a4db94011d3 | 106 | { |
sahilmgandhi | 18:6a4db94011d3 | 107 | /* Clock source is PCLK1 */ |
sahilmgandhi | 18:6a4db94011d3 | 108 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 109 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 110 | else |
sahilmgandhi | 18:6a4db94011d3 | 111 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 112 | } |
sahilmgandhi | 18:6a4db94011d3 | 113 | else |
sahilmgandhi | 18:6a4db94011d3 | 114 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 115 | } |
sahilmgandhi | 18:6a4db94011d3 | 116 | else |
sahilmgandhi | 18:6a4db94011d3 | 117 | { |
sahilmgandhi | 18:6a4db94011d3 | 118 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 119 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 121 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 122 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0) |
sahilmgandhi | 18:6a4db94011d3 | 123 | { |
sahilmgandhi | 18:6a4db94011d3 | 124 | /* Clock source is PCLK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 125 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 126 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 127 | else |
sahilmgandhi | 18:6a4db94011d3 | 128 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 129 | } |
sahilmgandhi | 18:6a4db94011d3 | 130 | else |
sahilmgandhi | 18:6a4db94011d3 | 131 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | } |
sahilmgandhi | 18:6a4db94011d3 | 133 | |
sahilmgandhi | 18:6a4db94011d3 | 134 | if(u32BusClock >= u32HCLKFreq) |
sahilmgandhi | 18:6a4db94011d3 | 135 | { |
sahilmgandhi | 18:6a4db94011d3 | 136 | /* Set DIVIDER = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 137 | spi->CLKDIV = 0; |
sahilmgandhi | 18:6a4db94011d3 | 138 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 139 | return u32ClkSrc; |
sahilmgandhi | 18:6a4db94011d3 | 140 | } |
sahilmgandhi | 18:6a4db94011d3 | 141 | else if(u32BusClock >= u32ClkSrc) |
sahilmgandhi | 18:6a4db94011d3 | 142 | { |
sahilmgandhi | 18:6a4db94011d3 | 143 | /* Set DIVIDER = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 144 | spi->CLKDIV = 0; |
sahilmgandhi | 18:6a4db94011d3 | 145 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | return u32ClkSrc; |
sahilmgandhi | 18:6a4db94011d3 | 147 | } |
sahilmgandhi | 18:6a4db94011d3 | 148 | else if(u32BusClock == 0) |
sahilmgandhi | 18:6a4db94011d3 | 149 | { |
sahilmgandhi | 18:6a4db94011d3 | 150 | /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ |
sahilmgandhi | 18:6a4db94011d3 | 151 | spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 152 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 153 | return (u32ClkSrc / (0xFF + 1)); |
sahilmgandhi | 18:6a4db94011d3 | 154 | } |
sahilmgandhi | 18:6a4db94011d3 | 155 | else |
sahilmgandhi | 18:6a4db94011d3 | 156 | { |
sahilmgandhi | 18:6a4db94011d3 | 157 | u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */ |
sahilmgandhi | 18:6a4db94011d3 | 158 | if(u32Div > 0xFF) |
sahilmgandhi | 18:6a4db94011d3 | 159 | { |
sahilmgandhi | 18:6a4db94011d3 | 160 | u32Div = 0xFF; |
sahilmgandhi | 18:6a4db94011d3 | 161 | spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 162 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | return (u32ClkSrc / (0xFF + 1)); |
sahilmgandhi | 18:6a4db94011d3 | 164 | } |
sahilmgandhi | 18:6a4db94011d3 | 165 | else |
sahilmgandhi | 18:6a4db94011d3 | 166 | { |
sahilmgandhi | 18:6a4db94011d3 | 167 | spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); |
sahilmgandhi | 18:6a4db94011d3 | 168 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | return (u32ClkSrc / (u32Div + 1)); |
sahilmgandhi | 18:6a4db94011d3 | 170 | } |
sahilmgandhi | 18:6a4db94011d3 | 171 | } |
sahilmgandhi | 18:6a4db94011d3 | 172 | } |
sahilmgandhi | 18:6a4db94011d3 | 173 | else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | { |
sahilmgandhi | 18:6a4db94011d3 | 175 | /* Default setting: slave selection signal is low level active. */ |
sahilmgandhi | 18:6a4db94011d3 | 176 | spi->SSCTL = SPI_SS_ACTIVE_LOW; |
sahilmgandhi | 18:6a4db94011d3 | 177 | |
sahilmgandhi | 18:6a4db94011d3 | 178 | /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 179 | spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 180 | |
sahilmgandhi | 18:6a4db94011d3 | 181 | /* Set DIVIDER = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 182 | spi->CLKDIV = 0; |
sahilmgandhi | 18:6a4db94011d3 | 183 | |
sahilmgandhi | 18:6a4db94011d3 | 184 | /* Select PCLK as the clock source of SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 185 | if(spi == SPI0) |
sahilmgandhi | 18:6a4db94011d3 | 186 | { |
sahilmgandhi | 18:6a4db94011d3 | 187 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0; |
sahilmgandhi | 18:6a4db94011d3 | 188 | /* Return slave peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 190 | return (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 191 | else |
sahilmgandhi | 18:6a4db94011d3 | 192 | return u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 193 | } |
sahilmgandhi | 18:6a4db94011d3 | 194 | else if(spi == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 195 | { |
sahilmgandhi | 18:6a4db94011d3 | 196 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1; |
sahilmgandhi | 18:6a4db94011d3 | 197 | /* Return slave peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 198 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 199 | return (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 200 | else |
sahilmgandhi | 18:6a4db94011d3 | 201 | return u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 202 | } |
sahilmgandhi | 18:6a4db94011d3 | 203 | else |
sahilmgandhi | 18:6a4db94011d3 | 204 | { |
sahilmgandhi | 18:6a4db94011d3 | 205 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0; |
sahilmgandhi | 18:6a4db94011d3 | 206 | /* Return slave peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 208 | return (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 209 | else |
sahilmgandhi | 18:6a4db94011d3 | 210 | return u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 211 | } |
sahilmgandhi | 18:6a4db94011d3 | 212 | } |
sahilmgandhi | 18:6a4db94011d3 | 213 | } |
sahilmgandhi | 18:6a4db94011d3 | 214 | |
sahilmgandhi | 18:6a4db94011d3 | 215 | /** |
sahilmgandhi | 18:6a4db94011d3 | 216 | * @brief Disable SPI controller. |
sahilmgandhi | 18:6a4db94011d3 | 217 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 218 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 219 | * @details This function will reset SPI controller. |
sahilmgandhi | 18:6a4db94011d3 | 220 | */ |
sahilmgandhi | 18:6a4db94011d3 | 221 | void SPI_Close(SPI_T *spi) |
sahilmgandhi | 18:6a4db94011d3 | 222 | { |
sahilmgandhi | 18:6a4db94011d3 | 223 | if(spi == SPI0) |
sahilmgandhi | 18:6a4db94011d3 | 224 | { |
sahilmgandhi | 18:6a4db94011d3 | 225 | /* Reset SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 226 | SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 227 | SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 228 | } |
sahilmgandhi | 18:6a4db94011d3 | 229 | else if(spi == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 230 | { |
sahilmgandhi | 18:6a4db94011d3 | 231 | /* Reset SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 232 | SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 233 | SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 234 | } |
sahilmgandhi | 18:6a4db94011d3 | 235 | else |
sahilmgandhi | 18:6a4db94011d3 | 236 | { |
sahilmgandhi | 18:6a4db94011d3 | 237 | /* Reset SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 238 | SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 239 | SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 240 | } |
sahilmgandhi | 18:6a4db94011d3 | 241 | } |
sahilmgandhi | 18:6a4db94011d3 | 242 | |
sahilmgandhi | 18:6a4db94011d3 | 243 | /** |
sahilmgandhi | 18:6a4db94011d3 | 244 | * @brief Clear RX FIFO buffer. |
sahilmgandhi | 18:6a4db94011d3 | 245 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 246 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 247 | * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. |
sahilmgandhi | 18:6a4db94011d3 | 248 | */ |
sahilmgandhi | 18:6a4db94011d3 | 249 | void SPI_ClearRxFIFO(SPI_T *spi) |
sahilmgandhi | 18:6a4db94011d3 | 250 | { |
sahilmgandhi | 18:6a4db94011d3 | 251 | spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 252 | } |
sahilmgandhi | 18:6a4db94011d3 | 253 | |
sahilmgandhi | 18:6a4db94011d3 | 254 | /** |
sahilmgandhi | 18:6a4db94011d3 | 255 | * @brief Clear TX FIFO buffer. |
sahilmgandhi | 18:6a4db94011d3 | 256 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 257 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 258 | * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. |
sahilmgandhi | 18:6a4db94011d3 | 259 | * @note The TX shift register will not be cleared. |
sahilmgandhi | 18:6a4db94011d3 | 260 | */ |
sahilmgandhi | 18:6a4db94011d3 | 261 | void SPI_ClearTxFIFO(SPI_T *spi) |
sahilmgandhi | 18:6a4db94011d3 | 262 | { |
sahilmgandhi | 18:6a4db94011d3 | 263 | spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 264 | } |
sahilmgandhi | 18:6a4db94011d3 | 265 | |
sahilmgandhi | 18:6a4db94011d3 | 266 | /** |
sahilmgandhi | 18:6a4db94011d3 | 267 | * @brief Disable the automatic slave selection function. |
sahilmgandhi | 18:6a4db94011d3 | 268 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 269 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 270 | * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. |
sahilmgandhi | 18:6a4db94011d3 | 271 | */ |
sahilmgandhi | 18:6a4db94011d3 | 272 | void SPI_DisableAutoSS(SPI_T *spi) |
sahilmgandhi | 18:6a4db94011d3 | 273 | { |
sahilmgandhi | 18:6a4db94011d3 | 274 | spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 275 | } |
sahilmgandhi | 18:6a4db94011d3 | 276 | |
sahilmgandhi | 18:6a4db94011d3 | 277 | /** |
sahilmgandhi | 18:6a4db94011d3 | 278 | * @brief Enable the automatic slave selection function. |
sahilmgandhi | 18:6a4db94011d3 | 279 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 280 | * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) |
sahilmgandhi | 18:6a4db94011d3 | 281 | * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) |
sahilmgandhi | 18:6a4db94011d3 | 282 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 283 | * @details This function will enable the automatic slave selection function. Only available in Master mode. |
sahilmgandhi | 18:6a4db94011d3 | 284 | * The slave selection pin and the active level will be set in this function. |
sahilmgandhi | 18:6a4db94011d3 | 285 | */ |
sahilmgandhi | 18:6a4db94011d3 | 286 | void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) |
sahilmgandhi | 18:6a4db94011d3 | 287 | { |
sahilmgandhi | 18:6a4db94011d3 | 288 | spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 289 | } |
sahilmgandhi | 18:6a4db94011d3 | 290 | |
sahilmgandhi | 18:6a4db94011d3 | 291 | /** |
sahilmgandhi | 18:6a4db94011d3 | 292 | * @brief Set the SPI bus clock. |
sahilmgandhi | 18:6a4db94011d3 | 293 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 294 | * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. |
sahilmgandhi | 18:6a4db94011d3 | 295 | * @return Actual frequency of SPI bus clock. |
sahilmgandhi | 18:6a4db94011d3 | 296 | * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. |
sahilmgandhi | 18:6a4db94011d3 | 297 | * For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the actual SPI bus clock |
sahilmgandhi | 18:6a4db94011d3 | 298 | * rate will be 6MHz. |
sahilmgandhi | 18:6a4db94011d3 | 299 | * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. |
sahilmgandhi | 18:6a4db94011d3 | 300 | * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. |
sahilmgandhi | 18:6a4db94011d3 | 301 | * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. |
sahilmgandhi | 18:6a4db94011d3 | 302 | */ |
sahilmgandhi | 18:6a4db94011d3 | 303 | uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) |
sahilmgandhi | 18:6a4db94011d3 | 304 | { |
sahilmgandhi | 18:6a4db94011d3 | 305 | uint32_t u32ClkSrc, u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 306 | uint32_t u32Div; |
sahilmgandhi | 18:6a4db94011d3 | 307 | |
sahilmgandhi | 18:6a4db94011d3 | 308 | /* Get system clock frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 309 | u32HCLKFreq = CLK_GetHCLKFreq(); |
sahilmgandhi | 18:6a4db94011d3 | 310 | |
sahilmgandhi | 18:6a4db94011d3 | 311 | if(u32BusClock >= u32HCLKFreq) |
sahilmgandhi | 18:6a4db94011d3 | 312 | { |
sahilmgandhi | 18:6a4db94011d3 | 313 | /* Select PCLK as the clock source of SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 314 | if(spi == SPI0) |
sahilmgandhi | 18:6a4db94011d3 | 315 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0; |
sahilmgandhi | 18:6a4db94011d3 | 316 | else if(spi == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 317 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1; |
sahilmgandhi | 18:6a4db94011d3 | 318 | else |
sahilmgandhi | 18:6a4db94011d3 | 319 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0; |
sahilmgandhi | 18:6a4db94011d3 | 320 | } |
sahilmgandhi | 18:6a4db94011d3 | 321 | |
sahilmgandhi | 18:6a4db94011d3 | 322 | /* Check clock source of SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | if(spi == SPI0) |
sahilmgandhi | 18:6a4db94011d3 | 324 | { |
sahilmgandhi | 18:6a4db94011d3 | 325 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 326 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 327 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 328 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 329 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0) |
sahilmgandhi | 18:6a4db94011d3 | 330 | { |
sahilmgandhi | 18:6a4db94011d3 | 331 | /* Clock source is PCLK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 332 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 333 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 334 | else |
sahilmgandhi | 18:6a4db94011d3 | 335 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 336 | } |
sahilmgandhi | 18:6a4db94011d3 | 337 | else |
sahilmgandhi | 18:6a4db94011d3 | 338 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 339 | } |
sahilmgandhi | 18:6a4db94011d3 | 340 | else if(spi == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 341 | { |
sahilmgandhi | 18:6a4db94011d3 | 342 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 343 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 344 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 345 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 346 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1) |
sahilmgandhi | 18:6a4db94011d3 | 347 | { |
sahilmgandhi | 18:6a4db94011d3 | 348 | /* Clock source is PCLK1 */ |
sahilmgandhi | 18:6a4db94011d3 | 349 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 350 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 351 | else |
sahilmgandhi | 18:6a4db94011d3 | 352 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 353 | } |
sahilmgandhi | 18:6a4db94011d3 | 354 | else |
sahilmgandhi | 18:6a4db94011d3 | 355 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 356 | } |
sahilmgandhi | 18:6a4db94011d3 | 357 | else |
sahilmgandhi | 18:6a4db94011d3 | 358 | { |
sahilmgandhi | 18:6a4db94011d3 | 359 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 360 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 361 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 362 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 363 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0) |
sahilmgandhi | 18:6a4db94011d3 | 364 | { |
sahilmgandhi | 18:6a4db94011d3 | 365 | /* Clock source is PCLK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 366 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 367 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 368 | else |
sahilmgandhi | 18:6a4db94011d3 | 369 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 370 | } |
sahilmgandhi | 18:6a4db94011d3 | 371 | else |
sahilmgandhi | 18:6a4db94011d3 | 372 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 373 | } |
sahilmgandhi | 18:6a4db94011d3 | 374 | |
sahilmgandhi | 18:6a4db94011d3 | 375 | if(u32BusClock >= u32HCLKFreq) |
sahilmgandhi | 18:6a4db94011d3 | 376 | { |
sahilmgandhi | 18:6a4db94011d3 | 377 | /* Set DIVIDER = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 378 | spi->CLKDIV = 0; |
sahilmgandhi | 18:6a4db94011d3 | 379 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 380 | return u32ClkSrc; |
sahilmgandhi | 18:6a4db94011d3 | 381 | } |
sahilmgandhi | 18:6a4db94011d3 | 382 | else if(u32BusClock >= u32ClkSrc) |
sahilmgandhi | 18:6a4db94011d3 | 383 | { |
sahilmgandhi | 18:6a4db94011d3 | 384 | /* Set DIVIDER = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 385 | spi->CLKDIV = 0; |
sahilmgandhi | 18:6a4db94011d3 | 386 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 387 | return u32ClkSrc; |
sahilmgandhi | 18:6a4db94011d3 | 388 | } |
sahilmgandhi | 18:6a4db94011d3 | 389 | else if(u32BusClock == 0) |
sahilmgandhi | 18:6a4db94011d3 | 390 | { |
sahilmgandhi | 18:6a4db94011d3 | 391 | /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ |
sahilmgandhi | 18:6a4db94011d3 | 392 | spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 393 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 394 | return (u32ClkSrc / (0xFF + 1)); |
sahilmgandhi | 18:6a4db94011d3 | 395 | } |
sahilmgandhi | 18:6a4db94011d3 | 396 | else |
sahilmgandhi | 18:6a4db94011d3 | 397 | { |
sahilmgandhi | 18:6a4db94011d3 | 398 | u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */ |
sahilmgandhi | 18:6a4db94011d3 | 399 | if(u32Div > 0xFF) |
sahilmgandhi | 18:6a4db94011d3 | 400 | { |
sahilmgandhi | 18:6a4db94011d3 | 401 | u32Div = 0xFF; |
sahilmgandhi | 18:6a4db94011d3 | 402 | spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 403 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 404 | return (u32ClkSrc / (0xFF + 1)); |
sahilmgandhi | 18:6a4db94011d3 | 405 | } |
sahilmgandhi | 18:6a4db94011d3 | 406 | else |
sahilmgandhi | 18:6a4db94011d3 | 407 | { |
sahilmgandhi | 18:6a4db94011d3 | 408 | spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); |
sahilmgandhi | 18:6a4db94011d3 | 409 | /* Return master peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 410 | return (u32ClkSrc / (u32Div + 1)); |
sahilmgandhi | 18:6a4db94011d3 | 411 | } |
sahilmgandhi | 18:6a4db94011d3 | 412 | } |
sahilmgandhi | 18:6a4db94011d3 | 413 | } |
sahilmgandhi | 18:6a4db94011d3 | 414 | |
sahilmgandhi | 18:6a4db94011d3 | 415 | /** |
sahilmgandhi | 18:6a4db94011d3 | 416 | * @brief Configure FIFO threshold setting. |
sahilmgandhi | 18:6a4db94011d3 | 417 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 418 | * @param[in] u32TxThreshold Decides the TX FIFO threshold. For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3. |
sahilmgandhi | 18:6a4db94011d3 | 419 | * @param[in] u32RxThreshold Decides the RX FIFO threshold. For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3. |
sahilmgandhi | 18:6a4db94011d3 | 420 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 421 | * @details Set TX FIFO threshold and RX FIFO threshold configurations. |
sahilmgandhi | 18:6a4db94011d3 | 422 | */ |
sahilmgandhi | 18:6a4db94011d3 | 423 | void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) |
sahilmgandhi | 18:6a4db94011d3 | 424 | { |
sahilmgandhi | 18:6a4db94011d3 | 425 | spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) | |
sahilmgandhi | 18:6a4db94011d3 | 426 | (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | |
sahilmgandhi | 18:6a4db94011d3 | 427 | (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos)); |
sahilmgandhi | 18:6a4db94011d3 | 428 | } |
sahilmgandhi | 18:6a4db94011d3 | 429 | |
sahilmgandhi | 18:6a4db94011d3 | 430 | /** |
sahilmgandhi | 18:6a4db94011d3 | 431 | * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. |
sahilmgandhi | 18:6a4db94011d3 | 432 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 433 | * @return Actual SPI bus clock frequency in Hz. |
sahilmgandhi | 18:6a4db94011d3 | 434 | * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode. |
sahilmgandhi | 18:6a4db94011d3 | 435 | */ |
sahilmgandhi | 18:6a4db94011d3 | 436 | uint32_t SPI_GetBusClock(SPI_T *spi) |
sahilmgandhi | 18:6a4db94011d3 | 437 | { |
sahilmgandhi | 18:6a4db94011d3 | 438 | uint32_t u32Div; |
sahilmgandhi | 18:6a4db94011d3 | 439 | uint32_t u32ClkSrc, u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 440 | |
sahilmgandhi | 18:6a4db94011d3 | 441 | /* Get DIVIDER setting */ |
sahilmgandhi | 18:6a4db94011d3 | 442 | u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; |
sahilmgandhi | 18:6a4db94011d3 | 443 | |
sahilmgandhi | 18:6a4db94011d3 | 444 | /* Get system clock frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 445 | u32HCLKFreq = CLK_GetHCLKFreq(); |
sahilmgandhi | 18:6a4db94011d3 | 446 | |
sahilmgandhi | 18:6a4db94011d3 | 447 | /* Check clock source of SPI */ |
sahilmgandhi | 18:6a4db94011d3 | 448 | if(spi == SPI0) |
sahilmgandhi | 18:6a4db94011d3 | 449 | { |
sahilmgandhi | 18:6a4db94011d3 | 450 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 451 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 452 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 453 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 454 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0) |
sahilmgandhi | 18:6a4db94011d3 | 455 | { |
sahilmgandhi | 18:6a4db94011d3 | 456 | /* Clock source is PCLK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 457 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 458 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 459 | else |
sahilmgandhi | 18:6a4db94011d3 | 460 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 461 | } |
sahilmgandhi | 18:6a4db94011d3 | 462 | else |
sahilmgandhi | 18:6a4db94011d3 | 463 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 464 | } |
sahilmgandhi | 18:6a4db94011d3 | 465 | else if(spi == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 466 | { |
sahilmgandhi | 18:6a4db94011d3 | 467 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 468 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 469 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 470 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 471 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1) |
sahilmgandhi | 18:6a4db94011d3 | 472 | { |
sahilmgandhi | 18:6a4db94011d3 | 473 | /* Clock source is PCLK1 */ |
sahilmgandhi | 18:6a4db94011d3 | 474 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 475 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 476 | else |
sahilmgandhi | 18:6a4db94011d3 | 477 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 478 | } |
sahilmgandhi | 18:6a4db94011d3 | 479 | else |
sahilmgandhi | 18:6a4db94011d3 | 480 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 481 | } |
sahilmgandhi | 18:6a4db94011d3 | 482 | else |
sahilmgandhi | 18:6a4db94011d3 | 483 | { |
sahilmgandhi | 18:6a4db94011d3 | 484 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 485 | u32ClkSrc = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 486 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 487 | u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 488 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0) |
sahilmgandhi | 18:6a4db94011d3 | 489 | { |
sahilmgandhi | 18:6a4db94011d3 | 490 | /* Clock source is PCLK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 491 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 492 | u32ClkSrc = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 493 | else |
sahilmgandhi | 18:6a4db94011d3 | 494 | u32ClkSrc = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 495 | } |
sahilmgandhi | 18:6a4db94011d3 | 496 | else |
sahilmgandhi | 18:6a4db94011d3 | 497 | u32ClkSrc = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 498 | } |
sahilmgandhi | 18:6a4db94011d3 | 499 | |
sahilmgandhi | 18:6a4db94011d3 | 500 | /* Return SPI bus clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 501 | return (u32ClkSrc / (u32Div + 1)); |
sahilmgandhi | 18:6a4db94011d3 | 502 | } |
sahilmgandhi | 18:6a4db94011d3 | 503 | |
sahilmgandhi | 18:6a4db94011d3 | 504 | /** |
sahilmgandhi | 18:6a4db94011d3 | 505 | * @brief Enable interrupt function. |
sahilmgandhi | 18:6a4db94011d3 | 506 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 507 | * @param[in] u32Mask The combination of all related interrupt enable bits. |
sahilmgandhi | 18:6a4db94011d3 | 508 | * Each bit corresponds to a interrupt enable bit. |
sahilmgandhi | 18:6a4db94011d3 | 509 | * This parameter decides which interrupts will be enabled. It is combination of: |
sahilmgandhi | 18:6a4db94011d3 | 510 | * - \ref SPI_UNIT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 511 | * - \ref SPI_SSACT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 512 | * - \ref SPI_SSINACT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 513 | * - \ref SPI_SLVUR_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 514 | * - \ref SPI_SLVBE_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 515 | * - \ref SPI_SLVTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 516 | * - \ref SPI_TXUF_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 517 | * - \ref SPI_FIFO_TXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 518 | * - \ref SPI_FIFO_RXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 519 | * - \ref SPI_FIFO_RXOV_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 520 | * - \ref SPI_FIFO_RXTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 521 | * |
sahilmgandhi | 18:6a4db94011d3 | 522 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 523 | * @details Enable SPI related interrupts specified by u32Mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 524 | */ |
sahilmgandhi | 18:6a4db94011d3 | 525 | void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) |
sahilmgandhi | 18:6a4db94011d3 | 526 | { |
sahilmgandhi | 18:6a4db94011d3 | 527 | /* Enable unit transfer interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 528 | if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 529 | spi->CTL |= SPI_CTL_UNITIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 530 | |
sahilmgandhi | 18:6a4db94011d3 | 531 | /* Enable slave selection signal active interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 532 | if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 533 | spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 534 | |
sahilmgandhi | 18:6a4db94011d3 | 535 | /* Enable slave selection signal inactive interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 536 | if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 537 | spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 538 | |
sahilmgandhi | 18:6a4db94011d3 | 539 | /* Enable slave TX under run interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 540 | if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 541 | spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 542 | |
sahilmgandhi | 18:6a4db94011d3 | 543 | /* Enable slave bit count error interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 544 | if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 545 | spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 546 | |
sahilmgandhi | 18:6a4db94011d3 | 547 | /* Enable slave time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 548 | if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 549 | spi->SSCTL |= SPI_SSCTL_SLVTOIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 550 | |
sahilmgandhi | 18:6a4db94011d3 | 551 | /* Enable slave TX underflow interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 552 | if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 553 | spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 554 | |
sahilmgandhi | 18:6a4db94011d3 | 555 | /* Enable TX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 556 | if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 557 | spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 558 | |
sahilmgandhi | 18:6a4db94011d3 | 559 | /* Enable RX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 560 | if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 561 | spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 562 | |
sahilmgandhi | 18:6a4db94011d3 | 563 | /* Enable RX overrun interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 564 | if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 565 | spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 566 | |
sahilmgandhi | 18:6a4db94011d3 | 567 | /* Enable RX time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 568 | if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 569 | spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 570 | } |
sahilmgandhi | 18:6a4db94011d3 | 571 | |
sahilmgandhi | 18:6a4db94011d3 | 572 | /** |
sahilmgandhi | 18:6a4db94011d3 | 573 | * @brief Disable interrupt function. |
sahilmgandhi | 18:6a4db94011d3 | 574 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 575 | * @param[in] u32Mask The combination of all related interrupt enable bits. |
sahilmgandhi | 18:6a4db94011d3 | 576 | * Each bit corresponds to a interrupt bit. |
sahilmgandhi | 18:6a4db94011d3 | 577 | * This parameter decides which interrupts will be disabled. It is combination of: |
sahilmgandhi | 18:6a4db94011d3 | 578 | * - \ref SPI_UNIT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 579 | * - \ref SPI_SSACT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 580 | * - \ref SPI_SSINACT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 581 | * - \ref SPI_SLVUR_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 582 | * - \ref SPI_SLVBE_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 583 | * - \ref SPI_SLVTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 584 | * - \ref SPI_TXUF_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 585 | * - \ref SPI_FIFO_TXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 586 | * - \ref SPI_FIFO_RXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 587 | * - \ref SPI_FIFO_RXOV_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 588 | * - \ref SPI_FIFO_RXTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 589 | * |
sahilmgandhi | 18:6a4db94011d3 | 590 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 591 | * @details Disable SPI related interrupts specified by u32Mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 592 | */ |
sahilmgandhi | 18:6a4db94011d3 | 593 | void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) |
sahilmgandhi | 18:6a4db94011d3 | 594 | { |
sahilmgandhi | 18:6a4db94011d3 | 595 | /* Disable unit transfer interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 596 | if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 597 | spi->CTL &= ~SPI_CTL_UNITIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 598 | |
sahilmgandhi | 18:6a4db94011d3 | 599 | /* Disable slave selection signal active interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 600 | if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 601 | spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 602 | |
sahilmgandhi | 18:6a4db94011d3 | 603 | /* Disable slave selection signal inactive interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 604 | if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 605 | spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 606 | |
sahilmgandhi | 18:6a4db94011d3 | 607 | /* Disable slave TX under run interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 608 | if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 609 | spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 610 | |
sahilmgandhi | 18:6a4db94011d3 | 611 | /* Disable slave bit count error interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 612 | if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 613 | spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 614 | |
sahilmgandhi | 18:6a4db94011d3 | 615 | /* Disable slave time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 616 | if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 617 | spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 618 | |
sahilmgandhi | 18:6a4db94011d3 | 619 | /* Disable slave TX underflow interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 620 | if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 621 | spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 622 | |
sahilmgandhi | 18:6a4db94011d3 | 623 | /* Disable TX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 624 | if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 625 | spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 626 | |
sahilmgandhi | 18:6a4db94011d3 | 627 | /* Disable RX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 628 | if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 629 | spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 630 | |
sahilmgandhi | 18:6a4db94011d3 | 631 | /* Disable RX overrun interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 632 | if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 633 | spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 634 | |
sahilmgandhi | 18:6a4db94011d3 | 635 | /* Disable RX time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 636 | if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 637 | spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 638 | } |
sahilmgandhi | 18:6a4db94011d3 | 639 | |
sahilmgandhi | 18:6a4db94011d3 | 640 | /** |
sahilmgandhi | 18:6a4db94011d3 | 641 | * @brief Get interrupt flag. |
sahilmgandhi | 18:6a4db94011d3 | 642 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 643 | * @param[in] u32Mask The combination of all related interrupt sources. |
sahilmgandhi | 18:6a4db94011d3 | 644 | * Each bit corresponds to a interrupt source. |
sahilmgandhi | 18:6a4db94011d3 | 645 | * This parameter decides which interrupt flags will be read. It is combination of: |
sahilmgandhi | 18:6a4db94011d3 | 646 | * - \ref SPI_UNIT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 647 | * - \ref SPI_SSACT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 648 | * - \ref SPI_SSINACT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 649 | * - \ref SPI_SLVUR_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 650 | * - \ref SPI_SLVBE_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 651 | * - \ref SPI_SLVTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 652 | * - \ref SPI_TXUF_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 653 | * - \ref SPI_FIFO_TXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 654 | * - \ref SPI_FIFO_RXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 655 | * - \ref SPI_FIFO_RXOV_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 656 | * - \ref SPI_FIFO_RXTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 657 | * |
sahilmgandhi | 18:6a4db94011d3 | 658 | * @return Interrupt flags of selected sources. |
sahilmgandhi | 18:6a4db94011d3 | 659 | * @details Get SPI related interrupt flags specified by u32Mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 660 | */ |
sahilmgandhi | 18:6a4db94011d3 | 661 | uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) |
sahilmgandhi | 18:6a4db94011d3 | 662 | { |
sahilmgandhi | 18:6a4db94011d3 | 663 | uint32_t u32IntFlag = 0; |
sahilmgandhi | 18:6a4db94011d3 | 664 | |
sahilmgandhi | 18:6a4db94011d3 | 665 | /* Check unit transfer interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 666 | if((u32Mask & SPI_UNIT_INT_MASK) && (spi->STATUS & SPI_STATUS_UNITIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 667 | u32IntFlag |= SPI_UNIT_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 668 | |
sahilmgandhi | 18:6a4db94011d3 | 669 | /* Check slave selection signal active interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 670 | if((u32Mask & SPI_SSACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSACTIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 671 | u32IntFlag |= SPI_SSACT_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 672 | |
sahilmgandhi | 18:6a4db94011d3 | 673 | /* Check slave selection signal inactive interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 674 | if((u32Mask & SPI_SSINACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSINAIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 675 | u32IntFlag |= SPI_SSINACT_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 676 | |
sahilmgandhi | 18:6a4db94011d3 | 677 | /* Check slave TX under run interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 678 | if((u32Mask & SPI_SLVUR_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVURIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 679 | u32IntFlag |= SPI_SLVUR_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 680 | |
sahilmgandhi | 18:6a4db94011d3 | 681 | /* Check slave bit count error interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 682 | if((u32Mask & SPI_SLVBE_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVBEIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 683 | u32IntFlag |= SPI_SLVBE_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 684 | |
sahilmgandhi | 18:6a4db94011d3 | 685 | /* Check slave time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 686 | if((u32Mask & SPI_SLVTO_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVTOIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 687 | u32IntFlag |= SPI_SLVTO_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 688 | |
sahilmgandhi | 18:6a4db94011d3 | 689 | /* Check slave TX underflow interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 690 | if((u32Mask & SPI_TXUF_INT_MASK) && (spi->STATUS & SPI_STATUS_TXUFIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 691 | u32IntFlag |= SPI_TXUF_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 692 | |
sahilmgandhi | 18:6a4db94011d3 | 693 | /* Check TX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 694 | if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_TXTHIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 695 | u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 696 | |
sahilmgandhi | 18:6a4db94011d3 | 697 | /* Check RX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 698 | if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTHIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 699 | u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 700 | |
sahilmgandhi | 18:6a4db94011d3 | 701 | /* Check RX overrun interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 702 | if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (spi->STATUS & SPI_STATUS_RXOVIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 703 | u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 704 | |
sahilmgandhi | 18:6a4db94011d3 | 705 | /* Check RX time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 706 | if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTOIF_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 707 | u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 708 | |
sahilmgandhi | 18:6a4db94011d3 | 709 | return u32IntFlag; |
sahilmgandhi | 18:6a4db94011d3 | 710 | } |
sahilmgandhi | 18:6a4db94011d3 | 711 | |
sahilmgandhi | 18:6a4db94011d3 | 712 | /** |
sahilmgandhi | 18:6a4db94011d3 | 713 | * @brief Clear interrupt flag. |
sahilmgandhi | 18:6a4db94011d3 | 714 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 715 | * @param[in] u32Mask The combination of all related interrupt sources. |
sahilmgandhi | 18:6a4db94011d3 | 716 | * Each bit corresponds to a interrupt source. |
sahilmgandhi | 18:6a4db94011d3 | 717 | * This parameter decides which interrupt flags will be cleared. It could be the combination of: |
sahilmgandhi | 18:6a4db94011d3 | 718 | * - \ref SPI_UNIT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 719 | * - \ref SPI_SSACT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 720 | * - \ref SPI_SSINACT_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 721 | * - \ref SPI_SLVUR_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 722 | * - \ref SPI_SLVBE_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 723 | * - \ref SPI_SLVTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 724 | * - \ref SPI_TXUF_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 725 | * - \ref SPI_FIFO_RXOV_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 726 | * - \ref SPI_FIFO_RXTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 727 | * |
sahilmgandhi | 18:6a4db94011d3 | 728 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 729 | * @details Clear SPI related interrupt flags specified by u32Mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 730 | */ |
sahilmgandhi | 18:6a4db94011d3 | 731 | void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) |
sahilmgandhi | 18:6a4db94011d3 | 732 | { |
sahilmgandhi | 18:6a4db94011d3 | 733 | if(u32Mask & SPI_UNIT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 734 | spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 735 | |
sahilmgandhi | 18:6a4db94011d3 | 736 | if(u32Mask & SPI_SSACT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 737 | spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 738 | |
sahilmgandhi | 18:6a4db94011d3 | 739 | if(u32Mask & SPI_SSINACT_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 740 | spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 741 | |
sahilmgandhi | 18:6a4db94011d3 | 742 | if(u32Mask & SPI_SLVUR_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 743 | spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 744 | |
sahilmgandhi | 18:6a4db94011d3 | 745 | if(u32Mask & SPI_SLVBE_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 746 | spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 747 | |
sahilmgandhi | 18:6a4db94011d3 | 748 | if(u32Mask & SPI_SLVTO_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 749 | spi->STATUS = SPI_STATUS_SLVTOIF_Msk; /* Clear slave time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 750 | |
sahilmgandhi | 18:6a4db94011d3 | 751 | if(u32Mask & SPI_TXUF_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 752 | spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 753 | |
sahilmgandhi | 18:6a4db94011d3 | 754 | if(u32Mask & SPI_FIFO_RXOV_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 755 | spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 756 | |
sahilmgandhi | 18:6a4db94011d3 | 757 | if(u32Mask & SPI_FIFO_RXTO_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 758 | spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 759 | } |
sahilmgandhi | 18:6a4db94011d3 | 760 | |
sahilmgandhi | 18:6a4db94011d3 | 761 | /** |
sahilmgandhi | 18:6a4db94011d3 | 762 | * @brief Get SPI status. |
sahilmgandhi | 18:6a4db94011d3 | 763 | * @param[in] spi The pointer of the specified SPI module. |
sahilmgandhi | 18:6a4db94011d3 | 764 | * @param[in] u32Mask The combination of all related sources. |
sahilmgandhi | 18:6a4db94011d3 | 765 | * Each bit corresponds to a source. |
sahilmgandhi | 18:6a4db94011d3 | 766 | * This parameter decides which flags will be read. It is combination of: |
sahilmgandhi | 18:6a4db94011d3 | 767 | * - \ref SPI_BUSY_MASK |
sahilmgandhi | 18:6a4db94011d3 | 768 | * - \ref SPI_RX_EMPTY_MASK |
sahilmgandhi | 18:6a4db94011d3 | 769 | * - \ref SPI_RX_FULL_MASK |
sahilmgandhi | 18:6a4db94011d3 | 770 | * - \ref SPI_TX_EMPTY_MASK |
sahilmgandhi | 18:6a4db94011d3 | 771 | * - \ref SPI_TX_FULL_MASK |
sahilmgandhi | 18:6a4db94011d3 | 772 | * - \ref SPI_TXRX_RESET_MASK |
sahilmgandhi | 18:6a4db94011d3 | 773 | * - \ref SPI_SPIEN_STS_MASK |
sahilmgandhi | 18:6a4db94011d3 | 774 | * - \ref SPI_SSLINE_STS_MASK |
sahilmgandhi | 18:6a4db94011d3 | 775 | * |
sahilmgandhi | 18:6a4db94011d3 | 776 | * @return Flags of selected sources. |
sahilmgandhi | 18:6a4db94011d3 | 777 | * @details Get SPI related status specified by u32Mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 778 | */ |
sahilmgandhi | 18:6a4db94011d3 | 779 | uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) |
sahilmgandhi | 18:6a4db94011d3 | 780 | { |
sahilmgandhi | 18:6a4db94011d3 | 781 | uint32_t u32Flag = 0; |
sahilmgandhi | 18:6a4db94011d3 | 782 | |
sahilmgandhi | 18:6a4db94011d3 | 783 | /* Check busy status */ |
sahilmgandhi | 18:6a4db94011d3 | 784 | if((u32Mask & SPI_BUSY_MASK) && (spi->STATUS & SPI_STATUS_BUSY_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 785 | u32Flag |= SPI_BUSY_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 786 | |
sahilmgandhi | 18:6a4db94011d3 | 787 | /* Check RX empty flag */ |
sahilmgandhi | 18:6a4db94011d3 | 788 | if((u32Mask & SPI_RX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_RXEMPTY_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 789 | u32Flag |= SPI_RX_EMPTY_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 790 | |
sahilmgandhi | 18:6a4db94011d3 | 791 | /* Check RX full flag */ |
sahilmgandhi | 18:6a4db94011d3 | 792 | if((u32Mask & SPI_RX_FULL_MASK) && (spi->STATUS & SPI_STATUS_RXFULL_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 793 | u32Flag |= SPI_RX_FULL_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 794 | |
sahilmgandhi | 18:6a4db94011d3 | 795 | /* Check TX empty flag */ |
sahilmgandhi | 18:6a4db94011d3 | 796 | if((u32Mask & SPI_TX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_TXEMPTY_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 797 | u32Flag |= SPI_TX_EMPTY_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 798 | |
sahilmgandhi | 18:6a4db94011d3 | 799 | /* Check TX full flag */ |
sahilmgandhi | 18:6a4db94011d3 | 800 | if((u32Mask & SPI_TX_FULL_MASK) && (spi->STATUS & SPI_STATUS_TXFULL_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 801 | u32Flag |= SPI_TX_FULL_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 802 | |
sahilmgandhi | 18:6a4db94011d3 | 803 | /* Check TX/RX reset flag */ |
sahilmgandhi | 18:6a4db94011d3 | 804 | if((u32Mask & SPI_TXRX_RESET_MASK) && (spi->STATUS & SPI_STATUS_TXRXRST_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 805 | u32Flag |= SPI_TXRX_RESET_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 806 | |
sahilmgandhi | 18:6a4db94011d3 | 807 | /* Check SPIEN flag */ |
sahilmgandhi | 18:6a4db94011d3 | 808 | if((u32Mask & SPI_SPIEN_STS_MASK) && (spi->STATUS & SPI_STATUS_SPIENSTS_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 809 | u32Flag |= SPI_SPIEN_STS_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 810 | |
sahilmgandhi | 18:6a4db94011d3 | 811 | /* Check SPIn_SS line status */ |
sahilmgandhi | 18:6a4db94011d3 | 812 | if((u32Mask & SPI_SSLINE_STS_MASK) && (spi->STATUS & SPI_STATUS_SSLINE_Msk)) |
sahilmgandhi | 18:6a4db94011d3 | 813 | u32Flag |= SPI_SSLINE_STS_MASK; |
sahilmgandhi | 18:6a4db94011d3 | 814 | |
sahilmgandhi | 18:6a4db94011d3 | 815 | return u32Flag; |
sahilmgandhi | 18:6a4db94011d3 | 816 | } |
sahilmgandhi | 18:6a4db94011d3 | 817 | |
sahilmgandhi | 18:6a4db94011d3 | 818 | |
sahilmgandhi | 18:6a4db94011d3 | 819 | /** |
sahilmgandhi | 18:6a4db94011d3 | 820 | * @brief This function is used to get I2S source clock frequency. |
sahilmgandhi | 18:6a4db94011d3 | 821 | * @param[in] i2s The pointer of the specified I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 822 | * @return I2S source clock frequency (Hz). |
sahilmgandhi | 18:6a4db94011d3 | 823 | * @details Return the source clock frequency according to the setting of SPI1SEL (CLKSEL2[5:4]) or SPI2SEL (CLKSEL2[7:6]). |
sahilmgandhi | 18:6a4db94011d3 | 824 | * @note Only SPI1 and SPI2 support I2S mode. |
sahilmgandhi | 18:6a4db94011d3 | 825 | */ |
sahilmgandhi | 18:6a4db94011d3 | 826 | static uint32_t I2S_GetSourceClockFreq(SPI_T *i2s) |
sahilmgandhi | 18:6a4db94011d3 | 827 | { |
sahilmgandhi | 18:6a4db94011d3 | 828 | uint32_t u32Freq, u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 829 | |
sahilmgandhi | 18:6a4db94011d3 | 830 | if(i2s == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 831 | { |
sahilmgandhi | 18:6a4db94011d3 | 832 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 833 | u32Freq = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 834 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 835 | u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 836 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1) |
sahilmgandhi | 18:6a4db94011d3 | 837 | { |
sahilmgandhi | 18:6a4db94011d3 | 838 | /* Get system clock frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 839 | u32HCLKFreq = CLK_GetHCLKFreq(); |
sahilmgandhi | 18:6a4db94011d3 | 840 | /* Clock source is PCLK1 */ |
sahilmgandhi | 18:6a4db94011d3 | 841 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 842 | u32Freq = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 843 | else |
sahilmgandhi | 18:6a4db94011d3 | 844 | u32Freq = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 845 | } |
sahilmgandhi | 18:6a4db94011d3 | 846 | else |
sahilmgandhi | 18:6a4db94011d3 | 847 | u32Freq = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 848 | } |
sahilmgandhi | 18:6a4db94011d3 | 849 | else |
sahilmgandhi | 18:6a4db94011d3 | 850 | { |
sahilmgandhi | 18:6a4db94011d3 | 851 | if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT) |
sahilmgandhi | 18:6a4db94011d3 | 852 | u32Freq = __HXT; /* Clock source is HXT */ |
sahilmgandhi | 18:6a4db94011d3 | 853 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL) |
sahilmgandhi | 18:6a4db94011d3 | 854 | u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ |
sahilmgandhi | 18:6a4db94011d3 | 855 | else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0) |
sahilmgandhi | 18:6a4db94011d3 | 856 | { |
sahilmgandhi | 18:6a4db94011d3 | 857 | /* Get system clock frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 858 | u32HCLKFreq = CLK_GetHCLKFreq(); |
sahilmgandhi | 18:6a4db94011d3 | 859 | /* Clock source is PCLK0 */ |
sahilmgandhi | 18:6a4db94011d3 | 860 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 861 | u32Freq = (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 862 | else |
sahilmgandhi | 18:6a4db94011d3 | 863 | u32Freq = u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 864 | } |
sahilmgandhi | 18:6a4db94011d3 | 865 | else |
sahilmgandhi | 18:6a4db94011d3 | 866 | u32Freq = __HIRC; /* Clock source is HIRC */ |
sahilmgandhi | 18:6a4db94011d3 | 867 | } |
sahilmgandhi | 18:6a4db94011d3 | 868 | |
sahilmgandhi | 18:6a4db94011d3 | 869 | return u32Freq; |
sahilmgandhi | 18:6a4db94011d3 | 870 | } |
sahilmgandhi | 18:6a4db94011d3 | 871 | |
sahilmgandhi | 18:6a4db94011d3 | 872 | /** |
sahilmgandhi | 18:6a4db94011d3 | 873 | * @brief This function configures some parameters of I2S interface for general purpose use. |
sahilmgandhi | 18:6a4db94011d3 | 874 | * @param[in] i2s The pointer of the specified I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 875 | * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. |
sahilmgandhi | 18:6a4db94011d3 | 876 | * - \ref I2S_MODE_MASTER |
sahilmgandhi | 18:6a4db94011d3 | 877 | * - \ref I2S_MODE_SLAVE |
sahilmgandhi | 18:6a4db94011d3 | 878 | * @param[in] u32SampleRate Sample rate |
sahilmgandhi | 18:6a4db94011d3 | 879 | * @param[in] u32WordWidth Data length. Valid values are listed below. |
sahilmgandhi | 18:6a4db94011d3 | 880 | * - \ref I2S_DATABIT_8 |
sahilmgandhi | 18:6a4db94011d3 | 881 | * - \ref I2S_DATABIT_16 |
sahilmgandhi | 18:6a4db94011d3 | 882 | * - \ref I2S_DATABIT_24 |
sahilmgandhi | 18:6a4db94011d3 | 883 | * - \ref I2S_DATABIT_32 |
sahilmgandhi | 18:6a4db94011d3 | 884 | * @param[in] u32Channels Audio format. Valid values are listed below. |
sahilmgandhi | 18:6a4db94011d3 | 885 | * - \ref I2S_MONO |
sahilmgandhi | 18:6a4db94011d3 | 886 | * - \ref I2S_STEREO |
sahilmgandhi | 18:6a4db94011d3 | 887 | * @param[in] u32DataFormat Data format. Valid values are listed below. |
sahilmgandhi | 18:6a4db94011d3 | 888 | * - \ref I2S_FORMAT_I2S |
sahilmgandhi | 18:6a4db94011d3 | 889 | * - \ref I2S_FORMAT_MSB |
sahilmgandhi | 18:6a4db94011d3 | 890 | * - \ref I2S_FORMAT_PCMA |
sahilmgandhi | 18:6a4db94011d3 | 891 | * - \ref I2S_FORMAT_PCMB |
sahilmgandhi | 18:6a4db94011d3 | 892 | * @return Real sample rate of master mode or peripheral clock rate of slave mode. |
sahilmgandhi | 18:6a4db94011d3 | 893 | * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. |
sahilmgandhi | 18:6a4db94011d3 | 894 | * Set TX and RX FIFO threshold to middle value. Both the TX and RX functions will be enabled. |
sahilmgandhi | 18:6a4db94011d3 | 895 | * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. |
sahilmgandhi | 18:6a4db94011d3 | 896 | * @note Only SPI1 and SPI2 support I2S mode. |
sahilmgandhi | 18:6a4db94011d3 | 897 | * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. |
sahilmgandhi | 18:6a4db94011d3 | 898 | */ |
sahilmgandhi | 18:6a4db94011d3 | 899 | uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) |
sahilmgandhi | 18:6a4db94011d3 | 900 | { |
sahilmgandhi | 18:6a4db94011d3 | 901 | uint32_t u32Divider; |
sahilmgandhi | 18:6a4db94011d3 | 902 | uint32_t u32BitRate, u32SrcClk; |
sahilmgandhi | 18:6a4db94011d3 | 903 | uint32_t u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 904 | |
sahilmgandhi | 18:6a4db94011d3 | 905 | /* Reset SPI/I2S */ |
sahilmgandhi | 18:6a4db94011d3 | 906 | if(i2s == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 907 | { |
sahilmgandhi | 18:6a4db94011d3 | 908 | SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 909 | SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 910 | } |
sahilmgandhi | 18:6a4db94011d3 | 911 | else |
sahilmgandhi | 18:6a4db94011d3 | 912 | { |
sahilmgandhi | 18:6a4db94011d3 | 913 | SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 914 | SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 915 | } |
sahilmgandhi | 18:6a4db94011d3 | 916 | |
sahilmgandhi | 18:6a4db94011d3 | 917 | /* Configure I2S controller */ |
sahilmgandhi | 18:6a4db94011d3 | 918 | i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; |
sahilmgandhi | 18:6a4db94011d3 | 919 | /* Set TX and RX FIFO threshold to middle value */ |
sahilmgandhi | 18:6a4db94011d3 | 920 | i2s->FIFOCTL = I2S_FIFO_TX_LEVEL_WORD_2 | I2S_FIFO_RX_LEVEL_WORD_2; |
sahilmgandhi | 18:6a4db94011d3 | 921 | |
sahilmgandhi | 18:6a4db94011d3 | 922 | if(u32MasterSlave == SPI_MASTER) |
sahilmgandhi | 18:6a4db94011d3 | 923 | { |
sahilmgandhi | 18:6a4db94011d3 | 924 | /* Get the source clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 925 | u32SrcClk = I2S_GetSourceClockFreq(i2s); |
sahilmgandhi | 18:6a4db94011d3 | 926 | |
sahilmgandhi | 18:6a4db94011d3 | 927 | /* Calculate the bit clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 928 | u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16; |
sahilmgandhi | 18:6a4db94011d3 | 929 | u32Divider = ((u32SrcClk / u32BitRate) >> 1) - 1; |
sahilmgandhi | 18:6a4db94011d3 | 930 | /* Set BCLKDIV setting */ |
sahilmgandhi | 18:6a4db94011d3 | 931 | i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); |
sahilmgandhi | 18:6a4db94011d3 | 932 | |
sahilmgandhi | 18:6a4db94011d3 | 933 | /* Calculate bit clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 934 | u32BitRate = u32SrcClk / ((u32Divider + 1) * 2); |
sahilmgandhi | 18:6a4db94011d3 | 935 | /* Calculate real sample rate */ |
sahilmgandhi | 18:6a4db94011d3 | 936 | u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16); |
sahilmgandhi | 18:6a4db94011d3 | 937 | |
sahilmgandhi | 18:6a4db94011d3 | 938 | /* Enable TX function, RX function and I2S mode. */ |
sahilmgandhi | 18:6a4db94011d3 | 939 | i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 940 | |
sahilmgandhi | 18:6a4db94011d3 | 941 | /* Return the real sample rate */ |
sahilmgandhi | 18:6a4db94011d3 | 942 | return u32SampleRate; |
sahilmgandhi | 18:6a4db94011d3 | 943 | } |
sahilmgandhi | 18:6a4db94011d3 | 944 | else |
sahilmgandhi | 18:6a4db94011d3 | 945 | { |
sahilmgandhi | 18:6a4db94011d3 | 946 | /* Set BCLKDIV = 0 */ |
sahilmgandhi | 18:6a4db94011d3 | 947 | i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 948 | /* Get system clock frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 949 | u32HCLKFreq = CLK_GetHCLKFreq(); |
sahilmgandhi | 18:6a4db94011d3 | 950 | |
sahilmgandhi | 18:6a4db94011d3 | 951 | if(i2s == SPI1) |
sahilmgandhi | 18:6a4db94011d3 | 952 | { |
sahilmgandhi | 18:6a4db94011d3 | 953 | /* Set the peripheral clock rate to equal APB clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 954 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1; |
sahilmgandhi | 18:6a4db94011d3 | 955 | /* Enable TX function, RX function and I2S mode. */ |
sahilmgandhi | 18:6a4db94011d3 | 956 | i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 957 | /* Return slave peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 958 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 959 | return (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 960 | else |
sahilmgandhi | 18:6a4db94011d3 | 961 | return u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 962 | } |
sahilmgandhi | 18:6a4db94011d3 | 963 | else |
sahilmgandhi | 18:6a4db94011d3 | 964 | { |
sahilmgandhi | 18:6a4db94011d3 | 965 | /* Set the peripheral clock rate to equal APB clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 966 | CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0; |
sahilmgandhi | 18:6a4db94011d3 | 967 | /* Enable TX function, RX function and I2S mode. */ |
sahilmgandhi | 18:6a4db94011d3 | 968 | i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 969 | /* Return slave peripheral clock rate */ |
sahilmgandhi | 18:6a4db94011d3 | 970 | if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2) |
sahilmgandhi | 18:6a4db94011d3 | 971 | return (u32HCLKFreq / 2); |
sahilmgandhi | 18:6a4db94011d3 | 972 | else |
sahilmgandhi | 18:6a4db94011d3 | 973 | return u32HCLKFreq; |
sahilmgandhi | 18:6a4db94011d3 | 974 | } |
sahilmgandhi | 18:6a4db94011d3 | 975 | } |
sahilmgandhi | 18:6a4db94011d3 | 976 | } |
sahilmgandhi | 18:6a4db94011d3 | 977 | |
sahilmgandhi | 18:6a4db94011d3 | 978 | /** |
sahilmgandhi | 18:6a4db94011d3 | 979 | * @brief Disable I2S function. |
sahilmgandhi | 18:6a4db94011d3 | 980 | * @param[in] i2s The pointer of the specified I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 981 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 982 | * @details Disable I2S function. |
sahilmgandhi | 18:6a4db94011d3 | 983 | * @note Only SPI1 and SPI2 support I2S mode. |
sahilmgandhi | 18:6a4db94011d3 | 984 | */ |
sahilmgandhi | 18:6a4db94011d3 | 985 | void I2S_Close(SPI_T *i2s) |
sahilmgandhi | 18:6a4db94011d3 | 986 | { |
sahilmgandhi | 18:6a4db94011d3 | 987 | i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 988 | } |
sahilmgandhi | 18:6a4db94011d3 | 989 | |
sahilmgandhi | 18:6a4db94011d3 | 990 | /** |
sahilmgandhi | 18:6a4db94011d3 | 991 | * @brief Enable interrupt function. |
sahilmgandhi | 18:6a4db94011d3 | 992 | * @param[in] i2s The pointer of the specified I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 993 | * @param[in] u32Mask The combination of all related interrupt enable bits. |
sahilmgandhi | 18:6a4db94011d3 | 994 | * Each bit corresponds to a interrupt source. Valid values are listed below. |
sahilmgandhi | 18:6a4db94011d3 | 995 | * - \ref I2S_FIFO_TXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 996 | * - \ref I2S_FIFO_RXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 997 | * - \ref I2S_FIFO_RXOV_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 998 | * - \ref I2S_FIFO_RXTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 999 | * - \ref I2S_TXUF_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1000 | * - \ref I2S_RIGHT_ZC_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1001 | * - \ref I2S_LEFT_ZC_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1002 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 1003 | * @details This function enables the interrupt according to the u32Mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 1004 | * @note Only SPI1 and SPI2 support I2S mode. |
sahilmgandhi | 18:6a4db94011d3 | 1005 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1006 | void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) |
sahilmgandhi | 18:6a4db94011d3 | 1007 | { |
sahilmgandhi | 18:6a4db94011d3 | 1008 | /* Enable TX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1009 | if((u32Mask & I2S_FIFO_TXTH_INT_MASK) == I2S_FIFO_TXTH_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1010 | i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1011 | |
sahilmgandhi | 18:6a4db94011d3 | 1012 | /* Enable RX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1013 | if((u32Mask & I2S_FIFO_RXTH_INT_MASK) == I2S_FIFO_RXTH_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1014 | i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1015 | |
sahilmgandhi | 18:6a4db94011d3 | 1016 | /* Enable RX overrun interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1017 | if((u32Mask & I2S_FIFO_RXOV_INT_MASK) == I2S_FIFO_RXOV_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1018 | i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1019 | |
sahilmgandhi | 18:6a4db94011d3 | 1020 | /* Enable RX time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1021 | if((u32Mask & I2S_FIFO_RXTO_INT_MASK) == I2S_FIFO_RXTO_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1022 | i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1023 | |
sahilmgandhi | 18:6a4db94011d3 | 1024 | /* Enable TX underflow interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1025 | if((u32Mask & I2S_TXUF_INT_MASK) == I2S_TXUF_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1026 | i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1027 | |
sahilmgandhi | 18:6a4db94011d3 | 1028 | /* Enable right channel zero cross interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1029 | if((u32Mask & I2S_RIGHT_ZC_INT_MASK) == I2S_RIGHT_ZC_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1030 | i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1031 | |
sahilmgandhi | 18:6a4db94011d3 | 1032 | /* Enable left channel zero cross interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1033 | if((u32Mask & I2S_LEFT_ZC_INT_MASK) == I2S_LEFT_ZC_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1034 | i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1035 | } |
sahilmgandhi | 18:6a4db94011d3 | 1036 | |
sahilmgandhi | 18:6a4db94011d3 | 1037 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1038 | * @brief Disable interrupt function. |
sahilmgandhi | 18:6a4db94011d3 | 1039 | * @param[in] i2s The pointer of the specified I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 1040 | * @param[in] u32Mask The combination of all related interrupt enable bits. |
sahilmgandhi | 18:6a4db94011d3 | 1041 | * Each bit corresponds to a interrupt source. Valid values are listed below. |
sahilmgandhi | 18:6a4db94011d3 | 1042 | * - \ref I2S_FIFO_TXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1043 | * - \ref I2S_FIFO_RXTH_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1044 | * - \ref I2S_FIFO_RXOV_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1045 | * - \ref I2S_FIFO_RXTO_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1046 | * - \ref I2S_TXUF_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1047 | * - \ref I2S_RIGHT_ZC_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1048 | * - \ref I2S_LEFT_ZC_INT_MASK |
sahilmgandhi | 18:6a4db94011d3 | 1049 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 1050 | * @details This function disables the interrupt according to the u32Mask parameter. |
sahilmgandhi | 18:6a4db94011d3 | 1051 | * @note Only SPI1 and SPI2 support I2S mode. |
sahilmgandhi | 18:6a4db94011d3 | 1052 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1053 | void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) |
sahilmgandhi | 18:6a4db94011d3 | 1054 | { |
sahilmgandhi | 18:6a4db94011d3 | 1055 | /* Disable TX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1056 | if((u32Mask & I2S_FIFO_TXTH_INT_MASK) == I2S_FIFO_TXTH_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1057 | i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1058 | |
sahilmgandhi | 18:6a4db94011d3 | 1059 | /* Disable RX threshold interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1060 | if((u32Mask & I2S_FIFO_RXTH_INT_MASK) == I2S_FIFO_RXTH_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1061 | i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1062 | |
sahilmgandhi | 18:6a4db94011d3 | 1063 | /* Disable RX overrun interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1064 | if((u32Mask & I2S_FIFO_RXOV_INT_MASK) == I2S_FIFO_RXOV_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1065 | i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1066 | |
sahilmgandhi | 18:6a4db94011d3 | 1067 | /* Disable RX time-out interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1068 | if((u32Mask & I2S_FIFO_RXTO_INT_MASK) == I2S_FIFO_RXTO_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1069 | i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1070 | |
sahilmgandhi | 18:6a4db94011d3 | 1071 | /* Disable TX underflow interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1072 | if((u32Mask & I2S_TXUF_INT_MASK) == I2S_TXUF_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1073 | i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1074 | |
sahilmgandhi | 18:6a4db94011d3 | 1075 | /* Disable right channel zero cross interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1076 | if((u32Mask & I2S_RIGHT_ZC_INT_MASK) == I2S_RIGHT_ZC_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1077 | i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1078 | |
sahilmgandhi | 18:6a4db94011d3 | 1079 | /* Disable left channel zero cross interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1080 | if((u32Mask & I2S_LEFT_ZC_INT_MASK) == I2S_LEFT_ZC_INT_MASK) |
sahilmgandhi | 18:6a4db94011d3 | 1081 | i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1082 | } |
sahilmgandhi | 18:6a4db94011d3 | 1083 | |
sahilmgandhi | 18:6a4db94011d3 | 1084 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1085 | * @brief Enable master clock (MCLK). |
sahilmgandhi | 18:6a4db94011d3 | 1086 | * @param[in] i2s The pointer of the specified I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 1087 | * @param[in] u32BusClock The target MCLK clock rate. |
sahilmgandhi | 18:6a4db94011d3 | 1088 | * @return Actual MCLK clock rate |
sahilmgandhi | 18:6a4db94011d3 | 1089 | * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. |
sahilmgandhi | 18:6a4db94011d3 | 1090 | * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. |
sahilmgandhi | 18:6a4db94011d3 | 1091 | * @note Only SPI1 and SPI2 support I2S mode. |
sahilmgandhi | 18:6a4db94011d3 | 1092 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1093 | uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) |
sahilmgandhi | 18:6a4db94011d3 | 1094 | { |
sahilmgandhi | 18:6a4db94011d3 | 1095 | uint32_t u32Divider; |
sahilmgandhi | 18:6a4db94011d3 | 1096 | uint32_t u32SrcClk; |
sahilmgandhi | 18:6a4db94011d3 | 1097 | |
sahilmgandhi | 18:6a4db94011d3 | 1098 | u32SrcClk = I2S_GetSourceClockFreq(i2s); |
sahilmgandhi | 18:6a4db94011d3 | 1099 | if(u32BusClock == u32SrcClk) |
sahilmgandhi | 18:6a4db94011d3 | 1100 | u32Divider = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1101 | else |
sahilmgandhi | 18:6a4db94011d3 | 1102 | { |
sahilmgandhi | 18:6a4db94011d3 | 1103 | u32Divider = (u32SrcClk / u32BusClock) >> 1; |
sahilmgandhi | 18:6a4db94011d3 | 1104 | /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */ |
sahilmgandhi | 18:6a4db94011d3 | 1105 | if(u32Divider > 0x3F) |
sahilmgandhi | 18:6a4db94011d3 | 1106 | u32Divider = 0x3F; |
sahilmgandhi | 18:6a4db94011d3 | 1107 | } |
sahilmgandhi | 18:6a4db94011d3 | 1108 | |
sahilmgandhi | 18:6a4db94011d3 | 1109 | /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */ |
sahilmgandhi | 18:6a4db94011d3 | 1110 | i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); |
sahilmgandhi | 18:6a4db94011d3 | 1111 | |
sahilmgandhi | 18:6a4db94011d3 | 1112 | /* Enable MCLK output */ |
sahilmgandhi | 18:6a4db94011d3 | 1113 | i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1114 | |
sahilmgandhi | 18:6a4db94011d3 | 1115 | if(u32Divider == 0) |
sahilmgandhi | 18:6a4db94011d3 | 1116 | return u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ |
sahilmgandhi | 18:6a4db94011d3 | 1117 | else |
sahilmgandhi | 18:6a4db94011d3 | 1118 | return ((u32SrcClk >> 1) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ |
sahilmgandhi | 18:6a4db94011d3 | 1119 | } |
sahilmgandhi | 18:6a4db94011d3 | 1120 | |
sahilmgandhi | 18:6a4db94011d3 | 1121 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1122 | * @brief Disable master clock (MCLK). |
sahilmgandhi | 18:6a4db94011d3 | 1123 | * @param[in] i2s The pointer of the specified I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 1124 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 1125 | * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. |
sahilmgandhi | 18:6a4db94011d3 | 1126 | * @note Only SPI1 and SPI2 support I2S mode. |
sahilmgandhi | 18:6a4db94011d3 | 1127 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1128 | void I2S_DisableMCLK(SPI_T *i2s) |
sahilmgandhi | 18:6a4db94011d3 | 1129 | { |
sahilmgandhi | 18:6a4db94011d3 | 1130 | i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 1131 | } |
sahilmgandhi | 18:6a4db94011d3 | 1132 | |
sahilmgandhi | 18:6a4db94011d3 | 1133 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1134 | * @brief Configure FIFO threshold setting. |
sahilmgandhi | 18:6a4db94011d3 | 1135 | * @param[in] i2s The pointer of the specified I2S module. |
sahilmgandhi | 18:6a4db94011d3 | 1136 | * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. |
sahilmgandhi | 18:6a4db94011d3 | 1137 | * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. |
sahilmgandhi | 18:6a4db94011d3 | 1138 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 1139 | * @details Set TX FIFO threshold and RX FIFO threshold configurations. |
sahilmgandhi | 18:6a4db94011d3 | 1140 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1141 | void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) |
sahilmgandhi | 18:6a4db94011d3 | 1142 | { |
sahilmgandhi | 18:6a4db94011d3 | 1143 | i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) | |
sahilmgandhi | 18:6a4db94011d3 | 1144 | (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | |
sahilmgandhi | 18:6a4db94011d3 | 1145 | (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos)); |
sahilmgandhi | 18:6a4db94011d3 | 1146 | } |
sahilmgandhi | 18:6a4db94011d3 | 1147 | |
sahilmgandhi | 18:6a4db94011d3 | 1148 | /*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ |
sahilmgandhi | 18:6a4db94011d3 | 1149 | |
sahilmgandhi | 18:6a4db94011d3 | 1150 | /*@}*/ /* end of group SPI_Driver */ |
sahilmgandhi | 18:6a4db94011d3 | 1151 | |
sahilmgandhi | 18:6a4db94011d3 | 1152 | /*@}*/ /* end of group Standard_Driver */ |
sahilmgandhi | 18:6a4db94011d3 | 1153 | |
sahilmgandhi | 18:6a4db94011d3 | 1154 | /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/ |