MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pdma.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file pdma.c
sahilmgandhi 18:6a4db94011d3 3 * @version V1.00
sahilmgandhi 18:6a4db94011d3 4 * $Revision: 12 $
sahilmgandhi 18:6a4db94011d3 5 * $Date: 15/08/11 10:26a $
sahilmgandhi 18:6a4db94011d3 6 * @brief M451 series PDMA driver source file
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * @note
sahilmgandhi 18:6a4db94011d3 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
sahilmgandhi 18:6a4db94011d3 10 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 11 #include "M451Series.h"
sahilmgandhi 18:6a4db94011d3 12
sahilmgandhi 18:6a4db94011d3 13
sahilmgandhi 18:6a4db94011d3 14 static uint8_t u32ChSelect[PDMA_CH_MAX];
sahilmgandhi 18:6a4db94011d3 15
sahilmgandhi 18:6a4db94011d3 16 /** @addtogroup Standard_Driver Standard Driver
sahilmgandhi 18:6a4db94011d3 17 @{
sahilmgandhi 18:6a4db94011d3 18 */
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 /** @addtogroup PDMA_Driver PDMA Driver
sahilmgandhi 18:6a4db94011d3 21 @{
sahilmgandhi 18:6a4db94011d3 22 */
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 /** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
sahilmgandhi 18:6a4db94011d3 26 @{
sahilmgandhi 18:6a4db94011d3 27 */
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 /**
sahilmgandhi 18:6a4db94011d3 30 * @brief PDMA Open
sahilmgandhi 18:6a4db94011d3 31 *
sahilmgandhi 18:6a4db94011d3 32 * @param[in] u32Mask Channel enable bits.
sahilmgandhi 18:6a4db94011d3 33 *
sahilmgandhi 18:6a4db94011d3 34 * @return None
sahilmgandhi 18:6a4db94011d3 35 *
sahilmgandhi 18:6a4db94011d3 36 * @details This function enable the PDMA channels.
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38 void PDMA_Open(uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 39 {
sahilmgandhi 18:6a4db94011d3 40 int volatile i;
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 for(i = 0; i < PDMA_CH_MAX; i++)
sahilmgandhi 18:6a4db94011d3 43 {
sahilmgandhi 18:6a4db94011d3 44 PDMA->DSCT[i].CTL = 0;
sahilmgandhi 18:6a4db94011d3 45 u32ChSelect[i] = 0x1f;
sahilmgandhi 18:6a4db94011d3 46 }
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 PDMA->CHCTL |= u32Mask;
sahilmgandhi 18:6a4db94011d3 49 }
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /**
sahilmgandhi 18:6a4db94011d3 52 * @brief PDMA Close
sahilmgandhi 18:6a4db94011d3 53 *
sahilmgandhi 18:6a4db94011d3 54 * @param None
sahilmgandhi 18:6a4db94011d3 55 *
sahilmgandhi 18:6a4db94011d3 56 * @return None
sahilmgandhi 18:6a4db94011d3 57 *
sahilmgandhi 18:6a4db94011d3 58 * @details This function disable all PDMA channels.
sahilmgandhi 18:6a4db94011d3 59 */
sahilmgandhi 18:6a4db94011d3 60 void PDMA_Close(void)
sahilmgandhi 18:6a4db94011d3 61 {
sahilmgandhi 18:6a4db94011d3 62 PDMA->CHCTL = 0;
sahilmgandhi 18:6a4db94011d3 63 }
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /**
sahilmgandhi 18:6a4db94011d3 66 * @brief Set PDMA Transfer Count
sahilmgandhi 18:6a4db94011d3 67 *
sahilmgandhi 18:6a4db94011d3 68 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 69 * @param[in] u32Width Data width. Valid values are
sahilmgandhi 18:6a4db94011d3 70 * - \ref PDMA_WIDTH_8
sahilmgandhi 18:6a4db94011d3 71 * - \ref PDMA_WIDTH_16
sahilmgandhi 18:6a4db94011d3 72 * - \ref PDMA_WIDTH_32
sahilmgandhi 18:6a4db94011d3 73 * @param[in] u32TransCount Transfer count
sahilmgandhi 18:6a4db94011d3 74 *
sahilmgandhi 18:6a4db94011d3 75 * @return None
sahilmgandhi 18:6a4db94011d3 76 *
sahilmgandhi 18:6a4db94011d3 77 * @details This function set the selected channel data width and transfer count.
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79 void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
sahilmgandhi 18:6a4db94011d3 80 {
sahilmgandhi 18:6a4db94011d3 81 PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
sahilmgandhi 18:6a4db94011d3 82 PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1) << PDMA_DSCT_CTL_TXCNT_Pos));
sahilmgandhi 18:6a4db94011d3 83 }
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /**
sahilmgandhi 18:6a4db94011d3 86 * @brief Set PDMA Transfer Address
sahilmgandhi 18:6a4db94011d3 87 *
sahilmgandhi 18:6a4db94011d3 88 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 89 * @param[in] u32SrcAddr Source address
sahilmgandhi 18:6a4db94011d3 90 * @param[in] u32SrcCtrl Source control attribute. Valid values are
sahilmgandhi 18:6a4db94011d3 91 * - \ref PDMA_SAR_INC
sahilmgandhi 18:6a4db94011d3 92 * - \ref PDMA_SAR_FIX
sahilmgandhi 18:6a4db94011d3 93 * @param[in] u32DstAddr destination address
sahilmgandhi 18:6a4db94011d3 94 * @param[in] u32DstCtrl destination control attribute. Valid values are
sahilmgandhi 18:6a4db94011d3 95 * - \ref PDMA_DAR_INC
sahilmgandhi 18:6a4db94011d3 96 * - \ref PDMA_DAR_FIX
sahilmgandhi 18:6a4db94011d3 97 *
sahilmgandhi 18:6a4db94011d3 98 * @return None
sahilmgandhi 18:6a4db94011d3 99 *
sahilmgandhi 18:6a4db94011d3 100 * @details This function set the selected channel source/destination address and attribute.
sahilmgandhi 18:6a4db94011d3 101 */
sahilmgandhi 18:6a4db94011d3 102 void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
sahilmgandhi 18:6a4db94011d3 103 {
sahilmgandhi 18:6a4db94011d3 104 PDMA->DSCT[u32Ch].SA = u32SrcAddr;
sahilmgandhi 18:6a4db94011d3 105 PDMA->DSCT[u32Ch].DA = u32DstAddr;
sahilmgandhi 18:6a4db94011d3 106 PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
sahilmgandhi 18:6a4db94011d3 107 PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
sahilmgandhi 18:6a4db94011d3 108 }
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /**
sahilmgandhi 18:6a4db94011d3 111 * @brief Set PDMA Transfer Mode
sahilmgandhi 18:6a4db94011d3 112 *
sahilmgandhi 18:6a4db94011d3 113 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 114 * @param[in] u32Peripheral The selected peripheral. Valid values are
sahilmgandhi 18:6a4db94011d3 115 * - \ref PDMA_SPI0_TX
sahilmgandhi 18:6a4db94011d3 116 * - \ref PDMA_SPI1_TX
sahilmgandhi 18:6a4db94011d3 117 * - \ref PDMA_SPI2_TX
sahilmgandhi 18:6a4db94011d3 118 * - \ref PDMA_UART0_TX
sahilmgandhi 18:6a4db94011d3 119 * - \ref PDMA_UART1_TX
sahilmgandhi 18:6a4db94011d3 120 * - \ref PDMA_UART2_TX
sahilmgandhi 18:6a4db94011d3 121 * - \ref PDMA_UART3_TX
sahilmgandhi 18:6a4db94011d3 122 * - \ref PDMA_DAC_TX
sahilmgandhi 18:6a4db94011d3 123 * - \ref PDMA_ADC_RX
sahilmgandhi 18:6a4db94011d3 124 * - \ref PDMA_PWM0_P1_RX
sahilmgandhi 18:6a4db94011d3 125 * - \ref PDMA_PWM0_P2_RX
sahilmgandhi 18:6a4db94011d3 126 * - \ref PDMA_PWM0_P3_RX
sahilmgandhi 18:6a4db94011d3 127 * - \ref PDMA_PWM1_P1_RX
sahilmgandhi 18:6a4db94011d3 128 * - \ref PDMA_PWM1_P2_RX
sahilmgandhi 18:6a4db94011d3 129 * - \ref PDMA_PWM1_P3_RX
sahilmgandhi 18:6a4db94011d3 130 * - \ref PDMA_SPI0_RX
sahilmgandhi 18:6a4db94011d3 131 * - \ref PDMA_SPI1_RX
sahilmgandhi 18:6a4db94011d3 132 * - \ref PDMA_SPI2_RX
sahilmgandhi 18:6a4db94011d3 133 * - \ref PDMA_UART0_RX
sahilmgandhi 18:6a4db94011d3 134 * - \ref PDMA_UART1_RX
sahilmgandhi 18:6a4db94011d3 135 * - \ref PDMA_UART2_RX
sahilmgandhi 18:6a4db94011d3 136 * - \ref PDMA_UART3_RX
sahilmgandhi 18:6a4db94011d3 137 * - \ref PDMA_MEM
sahilmgandhi 18:6a4db94011d3 138 * @param[in] u32ScatterEn Scatter-gather mode enable
sahilmgandhi 18:6a4db94011d3 139 * @param[in] u32DescAddr Scatter-gather descriptor address
sahilmgandhi 18:6a4db94011d3 140 *
sahilmgandhi 18:6a4db94011d3 141 * @return None
sahilmgandhi 18:6a4db94011d3 142 *
sahilmgandhi 18:6a4db94011d3 143 * @details This function set the selected channel transfer mode. Include peripheral setting.
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145 void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
sahilmgandhi 18:6a4db94011d3 146 {
sahilmgandhi 18:6a4db94011d3 147 u32ChSelect[u32Ch] = u32Peripheral;
sahilmgandhi 18:6a4db94011d3 148 switch(u32Ch)
sahilmgandhi 18:6a4db94011d3 149 {
sahilmgandhi 18:6a4db94011d3 150 case 0:
sahilmgandhi 18:6a4db94011d3 151 PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
sahilmgandhi 18:6a4db94011d3 152 break;
sahilmgandhi 18:6a4db94011d3 153 case 1:
sahilmgandhi 18:6a4db94011d3 154 PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
sahilmgandhi 18:6a4db94011d3 155 break;
sahilmgandhi 18:6a4db94011d3 156 case 2:
sahilmgandhi 18:6a4db94011d3 157 PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
sahilmgandhi 18:6a4db94011d3 158 break;
sahilmgandhi 18:6a4db94011d3 159 case 3:
sahilmgandhi 18:6a4db94011d3 160 PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
sahilmgandhi 18:6a4db94011d3 161 break;
sahilmgandhi 18:6a4db94011d3 162 case 4:
sahilmgandhi 18:6a4db94011d3 163 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
sahilmgandhi 18:6a4db94011d3 164 break;
sahilmgandhi 18:6a4db94011d3 165 case 5:
sahilmgandhi 18:6a4db94011d3 166 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
sahilmgandhi 18:6a4db94011d3 167 break;
sahilmgandhi 18:6a4db94011d3 168 case 6:
sahilmgandhi 18:6a4db94011d3 169 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
sahilmgandhi 18:6a4db94011d3 170 break;
sahilmgandhi 18:6a4db94011d3 171 case 7:
sahilmgandhi 18:6a4db94011d3 172 PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
sahilmgandhi 18:6a4db94011d3 173 break;
sahilmgandhi 18:6a4db94011d3 174 case 8:
sahilmgandhi 18:6a4db94011d3 175 PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
sahilmgandhi 18:6a4db94011d3 176 break;
sahilmgandhi 18:6a4db94011d3 177 case 9:
sahilmgandhi 18:6a4db94011d3 178 PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
sahilmgandhi 18:6a4db94011d3 179 break;
sahilmgandhi 18:6a4db94011d3 180 case 10:
sahilmgandhi 18:6a4db94011d3 181 PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
sahilmgandhi 18:6a4db94011d3 182 break;
sahilmgandhi 18:6a4db94011d3 183 case 11:
sahilmgandhi 18:6a4db94011d3 184 PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
sahilmgandhi 18:6a4db94011d3 185 break;
sahilmgandhi 18:6a4db94011d3 186 default:
sahilmgandhi 18:6a4db94011d3 187 ;
sahilmgandhi 18:6a4db94011d3 188 }
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 if(u32ScatterEn)
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
sahilmgandhi 18:6a4db94011d3 193 PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
sahilmgandhi 18:6a4db94011d3 194 }
sahilmgandhi 18:6a4db94011d3 195 else
sahilmgandhi 18:6a4db94011d3 196 PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
sahilmgandhi 18:6a4db94011d3 197 }
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /**
sahilmgandhi 18:6a4db94011d3 200 * @brief Set PDMA Burst Type and Size
sahilmgandhi 18:6a4db94011d3 201 *
sahilmgandhi 18:6a4db94011d3 202 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 203 * @param[in] u32BurstType Burst mode or single mode. Valid values are
sahilmgandhi 18:6a4db94011d3 204 * - \ref PDMA_REQ_SINGLE
sahilmgandhi 18:6a4db94011d3 205 * - \ref PDMA_REQ_BURST
sahilmgandhi 18:6a4db94011d3 206 * @param[in] u32BurstSize Set the size of burst mode. Valid values are
sahilmgandhi 18:6a4db94011d3 207 * - \ref PDMA_BURST_128
sahilmgandhi 18:6a4db94011d3 208 * - \ref PDMA_BURST_64
sahilmgandhi 18:6a4db94011d3 209 * - \ref PDMA_BURST_32
sahilmgandhi 18:6a4db94011d3 210 * - \ref PDMA_BURST_16
sahilmgandhi 18:6a4db94011d3 211 * - \ref PDMA_BURST_8
sahilmgandhi 18:6a4db94011d3 212 * - \ref PDMA_BURST_4
sahilmgandhi 18:6a4db94011d3 213 * - \ref PDMA_BURST_2
sahilmgandhi 18:6a4db94011d3 214 * - \ref PDMA_BURST_1
sahilmgandhi 18:6a4db94011d3 215 *
sahilmgandhi 18:6a4db94011d3 216 * @return None
sahilmgandhi 18:6a4db94011d3 217 *
sahilmgandhi 18:6a4db94011d3 218 * @details This function set the selected channel burst type and size.
sahilmgandhi 18:6a4db94011d3 219 */
sahilmgandhi 18:6a4db94011d3 220 void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
sahilmgandhi 18:6a4db94011d3 221 {
sahilmgandhi 18:6a4db94011d3 222 PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
sahilmgandhi 18:6a4db94011d3 223 PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
sahilmgandhi 18:6a4db94011d3 224 }
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /**
sahilmgandhi 18:6a4db94011d3 227 * @brief Enable timeout function
sahilmgandhi 18:6a4db94011d3 228 *
sahilmgandhi 18:6a4db94011d3 229 * @param[in] u32Mask Channel enable bits.
sahilmgandhi 18:6a4db94011d3 230 *
sahilmgandhi 18:6a4db94011d3 231 * @return None
sahilmgandhi 18:6a4db94011d3 232 *
sahilmgandhi 18:6a4db94011d3 233 * @details This function enable timeout function of the selected channel(s).
sahilmgandhi 18:6a4db94011d3 234 * @note This function is only supported in M45xD/M45xC.
sahilmgandhi 18:6a4db94011d3 235 */
sahilmgandhi 18:6a4db94011d3 236 void PDMA_EnableTimeout(uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 237 {
sahilmgandhi 18:6a4db94011d3 238 PDMA->TOUTEN |= u32Mask;
sahilmgandhi 18:6a4db94011d3 239 }
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 /**
sahilmgandhi 18:6a4db94011d3 242 * @brief Disable timeout function
sahilmgandhi 18:6a4db94011d3 243 *
sahilmgandhi 18:6a4db94011d3 244 * @param[in] u32Mask Channel enable bits.
sahilmgandhi 18:6a4db94011d3 245 *
sahilmgandhi 18:6a4db94011d3 246 * @return None
sahilmgandhi 18:6a4db94011d3 247 *
sahilmgandhi 18:6a4db94011d3 248 * @details This function disable timeout function of the selected channel(s).
sahilmgandhi 18:6a4db94011d3 249 * @note This function is only supported in M45xD/M45xC.
sahilmgandhi 18:6a4db94011d3 250 */
sahilmgandhi 18:6a4db94011d3 251 void PDMA_DisableTimeout(uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 252 {
sahilmgandhi 18:6a4db94011d3 253 PDMA->TOUTEN &= ~u32Mask;
sahilmgandhi 18:6a4db94011d3 254 }
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 /**
sahilmgandhi 18:6a4db94011d3 257 * @brief Set PDMA Timeout Count
sahilmgandhi 18:6a4db94011d3 258 *
sahilmgandhi 18:6a4db94011d3 259 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 260 * @param[in] u32OnOff Enable/disable time out function
sahilmgandhi 18:6a4db94011d3 261 * @param[in] u32TimeOutCnt Timeout count
sahilmgandhi 18:6a4db94011d3 262 *
sahilmgandhi 18:6a4db94011d3 263 * @return None
sahilmgandhi 18:6a4db94011d3 264 *
sahilmgandhi 18:6a4db94011d3 265 * @details This function set the timeout count.
sahilmgandhi 18:6a4db94011d3 266 * @note This function is only supported in M45xD/M45xC.
sahilmgandhi 18:6a4db94011d3 267 */
sahilmgandhi 18:6a4db94011d3 268 void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
sahilmgandhi 18:6a4db94011d3 269 {
sahilmgandhi 18:6a4db94011d3 270 switch(u32Ch)
sahilmgandhi 18:6a4db94011d3 271 {
sahilmgandhi 18:6a4db94011d3 272 case 0:
sahilmgandhi 18:6a4db94011d3 273 PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 274 break;
sahilmgandhi 18:6a4db94011d3 275 case 1:
sahilmgandhi 18:6a4db94011d3 276 PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
sahilmgandhi 18:6a4db94011d3 277 break;
sahilmgandhi 18:6a4db94011d3 278 case 2:
sahilmgandhi 18:6a4db94011d3 279 PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 280 break;
sahilmgandhi 18:6a4db94011d3 281 case 3:
sahilmgandhi 18:6a4db94011d3 282 PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos);
sahilmgandhi 18:6a4db94011d3 283 break;
sahilmgandhi 18:6a4db94011d3 284 case 4:
sahilmgandhi 18:6a4db94011d3 285 PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 286 break;
sahilmgandhi 18:6a4db94011d3 287 case 5:
sahilmgandhi 18:6a4db94011d3 288 PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
sahilmgandhi 18:6a4db94011d3 289 break;
sahilmgandhi 18:6a4db94011d3 290 case 6:
sahilmgandhi 18:6a4db94011d3 291 PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
sahilmgandhi 18:6a4db94011d3 292 break;
sahilmgandhi 18:6a4db94011d3 293 case 7:
sahilmgandhi 18:6a4db94011d3 294 PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
sahilmgandhi 18:6a4db94011d3 295 break;
sahilmgandhi 18:6a4db94011d3 296
sahilmgandhi 18:6a4db94011d3 297 default:
sahilmgandhi 18:6a4db94011d3 298 ;
sahilmgandhi 18:6a4db94011d3 299 }
sahilmgandhi 18:6a4db94011d3 300 }
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /**
sahilmgandhi 18:6a4db94011d3 303 * @brief Trigger PDMA
sahilmgandhi 18:6a4db94011d3 304 *
sahilmgandhi 18:6a4db94011d3 305 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 306 *
sahilmgandhi 18:6a4db94011d3 307 * @return None
sahilmgandhi 18:6a4db94011d3 308 *
sahilmgandhi 18:6a4db94011d3 309 * @details This function trigger the selected channel.
sahilmgandhi 18:6a4db94011d3 310 */
sahilmgandhi 18:6a4db94011d3 311 void PDMA_Trigger(uint32_t u32Ch)
sahilmgandhi 18:6a4db94011d3 312 {
sahilmgandhi 18:6a4db94011d3 313 if(u32ChSelect[u32Ch] == PDMA_MEM)
sahilmgandhi 18:6a4db94011d3 314 PDMA->SWREQ = (1 << u32Ch);
sahilmgandhi 18:6a4db94011d3 315 }
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /**
sahilmgandhi 18:6a4db94011d3 318 * @brief Enable Interrupt
sahilmgandhi 18:6a4db94011d3 319 *
sahilmgandhi 18:6a4db94011d3 320 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 321 * @param[in] u32Mask The Interrupt Type. Valid values are
sahilmgandhi 18:6a4db94011d3 322 * - \ref PDMA_INT_TRANS_DONE
sahilmgandhi 18:6a4db94011d3 323 * - \ref PDMA_INT_TEMPTY
sahilmgandhi 18:6a4db94011d3 324 * - \ref PDMA_INT_TIMEOUT
sahilmgandhi 18:6a4db94011d3 325 *
sahilmgandhi 18:6a4db94011d3 326 * @return None
sahilmgandhi 18:6a4db94011d3 327 *
sahilmgandhi 18:6a4db94011d3 328 * @details This function enable the selected channel interrupt.
sahilmgandhi 18:6a4db94011d3 329 * @note PDMA_INT_TIMEOUT is only supported in M45xD/M45xC.
sahilmgandhi 18:6a4db94011d3 330 */
sahilmgandhi 18:6a4db94011d3 331 void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 332 {
sahilmgandhi 18:6a4db94011d3 333 switch(u32Mask)
sahilmgandhi 18:6a4db94011d3 334 {
sahilmgandhi 18:6a4db94011d3 335 case PDMA_INT_TRANS_DONE:
sahilmgandhi 18:6a4db94011d3 336 PDMA->INTEN |= (1 << u32Ch);
sahilmgandhi 18:6a4db94011d3 337 break;
sahilmgandhi 18:6a4db94011d3 338 case PDMA_INT_TEMPTY:
sahilmgandhi 18:6a4db94011d3 339 PDMA->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
sahilmgandhi 18:6a4db94011d3 340 break;
sahilmgandhi 18:6a4db94011d3 341 case PDMA_INT_TIMEOUT:
sahilmgandhi 18:6a4db94011d3 342 PDMA->TOUTIEN |= (1 << u32Ch);
sahilmgandhi 18:6a4db94011d3 343 break;
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 default:
sahilmgandhi 18:6a4db94011d3 346 ;
sahilmgandhi 18:6a4db94011d3 347 }
sahilmgandhi 18:6a4db94011d3 348 }
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /**
sahilmgandhi 18:6a4db94011d3 351 * @brief Disable Interrupt
sahilmgandhi 18:6a4db94011d3 352 *
sahilmgandhi 18:6a4db94011d3 353 * @param[in] u32Ch The selected channel
sahilmgandhi 18:6a4db94011d3 354 * @param[in] u32Mask The Interrupt Type. Valid values are
sahilmgandhi 18:6a4db94011d3 355 * - \ref PDMA_INT_TRANS_DONE
sahilmgandhi 18:6a4db94011d3 356 * - \ref PDMA_INT_TEMPTY
sahilmgandhi 18:6a4db94011d3 357 * - \ref PDMA_INT_TIMEOUT
sahilmgandhi 18:6a4db94011d3 358 *
sahilmgandhi 18:6a4db94011d3 359 * @return None
sahilmgandhi 18:6a4db94011d3 360 *
sahilmgandhi 18:6a4db94011d3 361 * @details This function disable the selected channel interrupt.
sahilmgandhi 18:6a4db94011d3 362 * @note PDMA_INT_TIMEOUT is only supported in M45xD/M45xC.
sahilmgandhi 18:6a4db94011d3 363 */
sahilmgandhi 18:6a4db94011d3 364 void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
sahilmgandhi 18:6a4db94011d3 365 {
sahilmgandhi 18:6a4db94011d3 366 switch(u32Mask)
sahilmgandhi 18:6a4db94011d3 367 {
sahilmgandhi 18:6a4db94011d3 368 case PDMA_INT_TRANS_DONE:
sahilmgandhi 18:6a4db94011d3 369 PDMA->INTEN &= ~(1 << u32Ch);
sahilmgandhi 18:6a4db94011d3 370 break;
sahilmgandhi 18:6a4db94011d3 371 case PDMA_INT_TEMPTY:
sahilmgandhi 18:6a4db94011d3 372 PDMA->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
sahilmgandhi 18:6a4db94011d3 373 break;
sahilmgandhi 18:6a4db94011d3 374 case PDMA_INT_TIMEOUT:
sahilmgandhi 18:6a4db94011d3 375 PDMA->TOUTIEN &= ~(1 << u32Ch);
sahilmgandhi 18:6a4db94011d3 376 break;
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 default:
sahilmgandhi 18:6a4db94011d3 379 ;
sahilmgandhi 18:6a4db94011d3 380 }
sahilmgandhi 18:6a4db94011d3 381 }
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383 /*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /*@}*/ /* end of group PDMA_Driver */
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 /*@}*/ /* end of group Standard_Driver */
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/