Mouse code for the MacroRat
mbed-dev/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_fmc.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /**************************************************************************//** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * @file FMC.h |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @version V2.1 |
sahilmgandhi | 18:6a4db94011d3 | 4 | * $Revision: 19 $ |
sahilmgandhi | 18:6a4db94011d3 | 5 | * $Date: 15/08/11 10:26a $ |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @brief M451 Series Flash Memory Controller Driver Header File |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * @note |
sahilmgandhi | 18:6a4db94011d3 | 9 | * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 10 | * |
sahilmgandhi | 18:6a4db94011d3 | 11 | ******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 12 | #ifndef __FMC_H__ |
sahilmgandhi | 18:6a4db94011d3 | 13 | #define __FMC_H__ |
sahilmgandhi | 18:6a4db94011d3 | 14 | |
sahilmgandhi | 18:6a4db94011d3 | 15 | #include "M451Series.h" |
sahilmgandhi | 18:6a4db94011d3 | 16 | |
sahilmgandhi | 18:6a4db94011d3 | 17 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 18 | extern "C" |
sahilmgandhi | 18:6a4db94011d3 | 19 | { |
sahilmgandhi | 18:6a4db94011d3 | 20 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 21 | |
sahilmgandhi | 18:6a4db94011d3 | 22 | |
sahilmgandhi | 18:6a4db94011d3 | 23 | /** @addtogroup Standard_Driver Standard Driver |
sahilmgandhi | 18:6a4db94011d3 | 24 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 25 | */ |
sahilmgandhi | 18:6a4db94011d3 | 26 | |
sahilmgandhi | 18:6a4db94011d3 | 27 | /** @addtogroup FMC_Driver FMC Driver |
sahilmgandhi | 18:6a4db94011d3 | 28 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 29 | */ |
sahilmgandhi | 18:6a4db94011d3 | 30 | |
sahilmgandhi | 18:6a4db94011d3 | 31 | /** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants |
sahilmgandhi | 18:6a4db94011d3 | 32 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 33 | */ |
sahilmgandhi | 18:6a4db94011d3 | 34 | |
sahilmgandhi | 18:6a4db94011d3 | 35 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 36 | /* Global constant definitions */ |
sahilmgandhi | 18:6a4db94011d3 | 37 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 38 | #define ISBEN 0 |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 41 | /* Define Base Address */ |
sahilmgandhi | 18:6a4db94011d3 | 42 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 43 | #define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */ |
sahilmgandhi | 18:6a4db94011d3 | 44 | #define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */ |
sahilmgandhi | 18:6a4db94011d3 | 45 | #define FMC_SPROM_BASE 0x00200000UL /*!< SPROM Base Address */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | #define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */ |
sahilmgandhi | 18:6a4db94011d3 | 47 | |
sahilmgandhi | 18:6a4db94011d3 | 48 | #define FMC_CONFIG0_ADDR (FMC_CONFIG_BASE) /*!< CONFIG 0 Address */ |
sahilmgandhi | 18:6a4db94011d3 | 49 | #define FMC_CONFIG1_ADDR (FMC_CONFIG_BASE + 4) /*!< CONFIG 1 Address */ |
sahilmgandhi | 18:6a4db94011d3 | 50 | |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | #define FMC_FLASH_PAGE_SIZE 0x800 /*!< Flash Page Size (2048 Bytes) */ |
sahilmgandhi | 18:6a4db94011d3 | 53 | #define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4 kBytes) */ |
sahilmgandhi | 18:6a4db94011d3 | 54 | |
sahilmgandhi | 18:6a4db94011d3 | 55 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 56 | /* ISPCTL constant definitions */ |
sahilmgandhi | 18:6a4db94011d3 | 57 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 58 | #define FMC_ISPCTL_BS_LDROM 0x2 /*!< ISPCTL setting to select to boot from LDROM */ |
sahilmgandhi | 18:6a4db94011d3 | 59 | #define FMC_ISPCTL_BS_APROM 0x0 /*!< ISPCTL setting to select to boot from APROM */ |
sahilmgandhi | 18:6a4db94011d3 | 60 | |
sahilmgandhi | 18:6a4db94011d3 | 61 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 62 | /* ISPCMD constant definitions */ |
sahilmgandhi | 18:6a4db94011d3 | 63 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 64 | #define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */ |
sahilmgandhi | 18:6a4db94011d3 | 65 | #define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: 32-bit Program Flash */ |
sahilmgandhi | 18:6a4db94011d3 | 66 | #define FMC_ISPCMD_WRITE_8 0x61 /*!< ISP Command: 64-bit program Flash */ |
sahilmgandhi | 18:6a4db94011d3 | 67 | #define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */ |
sahilmgandhi | 18:6a4db94011d3 | 68 | #define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | #define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */ |
sahilmgandhi | 18:6a4db94011d3 | 70 | #define FMC_ISPCMD_READ_DID 0x0C /*!< ISP Command: Read Device ID */ |
sahilmgandhi | 18:6a4db94011d3 | 71 | #define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Set vector mapping */ |
sahilmgandhi | 18:6a4db94011d3 | 72 | #define FMC_ISPCMD_CHECKSUM 0x0D /*!< ISP Command: Read Checksum */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | #define FMC_ISPCMD_CAL_CHECKSUM 0x2D /*!< ISP Command: Run Check Calculation */ |
sahilmgandhi | 18:6a4db94011d3 | 74 | #define FMC_ISPCMD_MULTI_PROG 0x27 /*!< ISP Command: Flash Multi-Word Program */ |
sahilmgandhi | 18:6a4db94011d3 | 75 | |
sahilmgandhi | 18:6a4db94011d3 | 76 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 77 | /* FTCTL constant definitions */ |
sahilmgandhi | 18:6a4db94011d3 | 78 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 79 | #define FMC_FTCTL_OPTIMIZE_DISABLE 0x00 /*!< Frequency Optimize Mode disable */ |
sahilmgandhi | 18:6a4db94011d3 | 80 | #define FMC_FTCTL_OPTIMIZE_12MHZ 0x01 /*!< Frequency Optimize Mode <= 12Mhz */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | #define FMC_FTCTL_OPTIMIZE_36MHZ 0x02 /*!< Frequency Optimize Mode <= 36Mhz */ |
sahilmgandhi | 18:6a4db94011d3 | 82 | #define FMC_FTCTL_OPTIMIZE_60MHZ 0x04 /*!< Frequency Optimize Mode <= 60Mhz */ |
sahilmgandhi | 18:6a4db94011d3 | 83 | #define FMC_FTCTL_OPTIMIZE_72MHZ 0x05 /*!< Frequency Optimize Mode <= 72Mhz */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | |
sahilmgandhi | 18:6a4db94011d3 | 85 | /*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ |
sahilmgandhi | 18:6a4db94011d3 | 86 | |
sahilmgandhi | 18:6a4db94011d3 | 87 | /** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions |
sahilmgandhi | 18:6a4db94011d3 | 88 | @{ |
sahilmgandhi | 18:6a4db94011d3 | 89 | */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | |
sahilmgandhi | 18:6a4db94011d3 | 91 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 92 | /* FMC Macro Definitions */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 94 | /** |
sahilmgandhi | 18:6a4db94011d3 | 95 | * @brief Enable ISP Function |
sahilmgandhi | 18:6a4db94011d3 | 96 | * |
sahilmgandhi | 18:6a4db94011d3 | 97 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 98 | * |
sahilmgandhi | 18:6a4db94011d3 | 99 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 100 | * |
sahilmgandhi | 18:6a4db94011d3 | 101 | * @details This function will set ISPEN bit of ISPCTL control register to enable ISP function. |
sahilmgandhi | 18:6a4db94011d3 | 102 | * |
sahilmgandhi | 18:6a4db94011d3 | 103 | */ |
sahilmgandhi | 18:6a4db94011d3 | 104 | #define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | |
sahilmgandhi | 18:6a4db94011d3 | 106 | /** |
sahilmgandhi | 18:6a4db94011d3 | 107 | * @brief Disable ISP Function |
sahilmgandhi | 18:6a4db94011d3 | 108 | * |
sahilmgandhi | 18:6a4db94011d3 | 109 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 110 | * |
sahilmgandhi | 18:6a4db94011d3 | 111 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 112 | * |
sahilmgandhi | 18:6a4db94011d3 | 113 | * @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function. |
sahilmgandhi | 18:6a4db94011d3 | 114 | * |
sahilmgandhi | 18:6a4db94011d3 | 115 | */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | #define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | |
sahilmgandhi | 18:6a4db94011d3 | 118 | /** |
sahilmgandhi | 18:6a4db94011d3 | 119 | * @brief Enable LDROM Update Function |
sahilmgandhi | 18:6a4db94011d3 | 120 | * |
sahilmgandhi | 18:6a4db94011d3 | 121 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 122 | * |
sahilmgandhi | 18:6a4db94011d3 | 123 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 124 | * |
sahilmgandhi | 18:6a4db94011d3 | 125 | * @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function. |
sahilmgandhi | 18:6a4db94011d3 | 126 | * User needs to set LDUEN bit before they can update LDROM. |
sahilmgandhi | 18:6a4db94011d3 | 127 | * |
sahilmgandhi | 18:6a4db94011d3 | 128 | */ |
sahilmgandhi | 18:6a4db94011d3 | 129 | #define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */ |
sahilmgandhi | 18:6a4db94011d3 | 130 | |
sahilmgandhi | 18:6a4db94011d3 | 131 | /** |
sahilmgandhi | 18:6a4db94011d3 | 132 | * @brief Disable LDROM Update Function |
sahilmgandhi | 18:6a4db94011d3 | 133 | * |
sahilmgandhi | 18:6a4db94011d3 | 134 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 135 | * |
sahilmgandhi | 18:6a4db94011d3 | 136 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 137 | * |
sahilmgandhi | 18:6a4db94011d3 | 138 | * @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function. |
sahilmgandhi | 18:6a4db94011d3 | 139 | * |
sahilmgandhi | 18:6a4db94011d3 | 140 | */ |
sahilmgandhi | 18:6a4db94011d3 | 141 | #define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */ |
sahilmgandhi | 18:6a4db94011d3 | 142 | |
sahilmgandhi | 18:6a4db94011d3 | 143 | /** |
sahilmgandhi | 18:6a4db94011d3 | 144 | * @brief Enable User Configuration Update Function |
sahilmgandhi | 18:6a4db94011d3 | 145 | * |
sahilmgandhi | 18:6a4db94011d3 | 146 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 147 | * |
sahilmgandhi | 18:6a4db94011d3 | 148 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 149 | * |
sahilmgandhi | 18:6a4db94011d3 | 150 | * @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function. |
sahilmgandhi | 18:6a4db94011d3 | 151 | * User needs to set CFGUEN bit before they can update User Configuration area. |
sahilmgandhi | 18:6a4db94011d3 | 152 | * |
sahilmgandhi | 18:6a4db94011d3 | 153 | */ |
sahilmgandhi | 18:6a4db94011d3 | 154 | #define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */ |
sahilmgandhi | 18:6a4db94011d3 | 155 | |
sahilmgandhi | 18:6a4db94011d3 | 156 | /** |
sahilmgandhi | 18:6a4db94011d3 | 157 | * @brief Disable User Configuration Update Function |
sahilmgandhi | 18:6a4db94011d3 | 158 | * |
sahilmgandhi | 18:6a4db94011d3 | 159 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 160 | * |
sahilmgandhi | 18:6a4db94011d3 | 161 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 162 | * |
sahilmgandhi | 18:6a4db94011d3 | 163 | * @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function. |
sahilmgandhi | 18:6a4db94011d3 | 164 | * |
sahilmgandhi | 18:6a4db94011d3 | 165 | */ |
sahilmgandhi | 18:6a4db94011d3 | 166 | #define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */ |
sahilmgandhi | 18:6a4db94011d3 | 167 | |
sahilmgandhi | 18:6a4db94011d3 | 168 | |
sahilmgandhi | 18:6a4db94011d3 | 169 | /** |
sahilmgandhi | 18:6a4db94011d3 | 170 | * @brief Enable APROM Update Function |
sahilmgandhi | 18:6a4db94011d3 | 171 | * |
sahilmgandhi | 18:6a4db94011d3 | 172 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 173 | * |
sahilmgandhi | 18:6a4db94011d3 | 174 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 175 | * |
sahilmgandhi | 18:6a4db94011d3 | 176 | * @details This function will set APUEN bit of ISPCTL control register to enable APROM update function. |
sahilmgandhi | 18:6a4db94011d3 | 177 | * User needs to set APUEN bit before they can update APROM in APROM boot mode. |
sahilmgandhi | 18:6a4db94011d3 | 178 | * |
sahilmgandhi | 18:6a4db94011d3 | 179 | */ |
sahilmgandhi | 18:6a4db94011d3 | 180 | #define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */ |
sahilmgandhi | 18:6a4db94011d3 | 181 | |
sahilmgandhi | 18:6a4db94011d3 | 182 | /** |
sahilmgandhi | 18:6a4db94011d3 | 183 | * @brief Disable APROM Update Function |
sahilmgandhi | 18:6a4db94011d3 | 184 | * |
sahilmgandhi | 18:6a4db94011d3 | 185 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 186 | * |
sahilmgandhi | 18:6a4db94011d3 | 187 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 188 | * |
sahilmgandhi | 18:6a4db94011d3 | 189 | * @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function. |
sahilmgandhi | 18:6a4db94011d3 | 190 | * |
sahilmgandhi | 18:6a4db94011d3 | 191 | */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | #define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */ |
sahilmgandhi | 18:6a4db94011d3 | 193 | |
sahilmgandhi | 18:6a4db94011d3 | 194 | /** |
sahilmgandhi | 18:6a4db94011d3 | 195 | * @brief Next Booting Selection function |
sahilmgandhi | 18:6a4db94011d3 | 196 | * |
sahilmgandhi | 18:6a4db94011d3 | 197 | * @param[in] x Booting from APROM(0)/LDROM(1) |
sahilmgandhi | 18:6a4db94011d3 | 198 | * |
sahilmgandhi | 18:6a4db94011d3 | 199 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 200 | * |
sahilmgandhi | 18:6a4db94011d3 | 201 | * @details This function will set MCU next booting from LDROM/APROM. |
sahilmgandhi | 18:6a4db94011d3 | 202 | * |
sahilmgandhi | 18:6a4db94011d3 | 203 | * @note When use this macro, the Boot Loader booting selection MBS(CONFIG0[5]) must be set. |
sahilmgandhi | 18:6a4db94011d3 | 204 | * |
sahilmgandhi | 18:6a4db94011d3 | 205 | */ |
sahilmgandhi | 18:6a4db94011d3 | 206 | #define FMC_SELECT_NEXT_BOOT(x) (FMC->ISPCTL = (FMC->ISPCTL & ~FMC_ISPCTL_BS_Msk) | ((x) << FMC_ISPCTL_BS_Pos)) /*!< Select Next Booting, x = 0 or 1 */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | |
sahilmgandhi | 18:6a4db94011d3 | 208 | /** |
sahilmgandhi | 18:6a4db94011d3 | 209 | * @brief Get MCU Booting Status |
sahilmgandhi | 18:6a4db94011d3 | 210 | * |
sahilmgandhi | 18:6a4db94011d3 | 211 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 212 | * |
sahilmgandhi | 18:6a4db94011d3 | 213 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 214 | * |
sahilmgandhi | 18:6a4db94011d3 | 215 | * @details This function will get status of chip next booting from LDROM/APROM. |
sahilmgandhi | 18:6a4db94011d3 | 216 | * |
sahilmgandhi | 18:6a4db94011d3 | 217 | */ |
sahilmgandhi | 18:6a4db94011d3 | 218 | #define FMC_GET_BOOT_STATUS() ((FMC->ISPCTL & FMC_ISPCTL_BS_Msk)?1:0) /*!< Get MCU Booting Status */ |
sahilmgandhi | 18:6a4db94011d3 | 219 | |
sahilmgandhi | 18:6a4db94011d3 | 220 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 221 | /* inline functions */ |
sahilmgandhi | 18:6a4db94011d3 | 222 | /*---------------------------------------------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 223 | /** |
sahilmgandhi | 18:6a4db94011d3 | 224 | * @brief Program 32-bit data into specified address of flash |
sahilmgandhi | 18:6a4db94011d3 | 225 | * |
sahilmgandhi | 18:6a4db94011d3 | 226 | * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG |
sahilmgandhi | 18:6a4db94011d3 | 227 | * @param[in] u32Data 32-bit Data to program |
sahilmgandhi | 18:6a4db94011d3 | 228 | * |
sahilmgandhi | 18:6a4db94011d3 | 229 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 230 | * |
sahilmgandhi | 18:6a4db94011d3 | 231 | * @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG. |
sahilmgandhi | 18:6a4db94011d3 | 232 | * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual. |
sahilmgandhi | 18:6a4db94011d3 | 233 | * |
sahilmgandhi | 18:6a4db94011d3 | 234 | */ |
sahilmgandhi | 18:6a4db94011d3 | 235 | static __INLINE void FMC_Write(uint32_t u32Addr, uint32_t u32Data) |
sahilmgandhi | 18:6a4db94011d3 | 236 | { |
sahilmgandhi | 18:6a4db94011d3 | 237 | FMC->ISPCMD = FMC_ISPCMD_PROGRAM; |
sahilmgandhi | 18:6a4db94011d3 | 238 | FMC->ISPADDR = u32Addr; |
sahilmgandhi | 18:6a4db94011d3 | 239 | FMC->ISPDAT = u32Data; |
sahilmgandhi | 18:6a4db94011d3 | 240 | FMC->ISPTRG = 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 241 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 242 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 243 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 244 | while(FMC->ISPTRG); |
sahilmgandhi | 18:6a4db94011d3 | 245 | } |
sahilmgandhi | 18:6a4db94011d3 | 246 | |
sahilmgandhi | 18:6a4db94011d3 | 247 | /** |
sahilmgandhi | 18:6a4db94011d3 | 248 | * @brief Program 64-bit data into specified address of flash |
sahilmgandhi | 18:6a4db94011d3 | 249 | * |
sahilmgandhi | 18:6a4db94011d3 | 250 | * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG |
sahilmgandhi | 18:6a4db94011d3 | 251 | * @param[in] u32Data0 32-bit Data to program |
sahilmgandhi | 18:6a4db94011d3 | 252 | * @param[in] u32Data1 32-bit Data to program |
sahilmgandhi | 18:6a4db94011d3 | 253 | * |
sahilmgandhi | 18:6a4db94011d3 | 254 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 255 | * |
sahilmgandhi | 18:6a4db94011d3 | 256 | * @details To program two words data into Flash include APROM, LDROM, Data Flash, and CONFIG. |
sahilmgandhi | 18:6a4db94011d3 | 257 | * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual. |
sahilmgandhi | 18:6a4db94011d3 | 258 | * |
sahilmgandhi | 18:6a4db94011d3 | 259 | */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | static __INLINE void FMC_Write8(uint32_t u32Addr, uint32_t u32Data0, uint32_t u32Data1) |
sahilmgandhi | 18:6a4db94011d3 | 261 | { |
sahilmgandhi | 18:6a4db94011d3 | 262 | FMC->ISPCMD = FMC_ISPCMD_WRITE_8; |
sahilmgandhi | 18:6a4db94011d3 | 263 | FMC->ISPADDR = u32Addr; |
sahilmgandhi | 18:6a4db94011d3 | 264 | FMC->MPDAT0 = u32Data0; |
sahilmgandhi | 18:6a4db94011d3 | 265 | FMC->MPDAT1 = u32Data1; |
sahilmgandhi | 18:6a4db94011d3 | 266 | FMC->ISPTRG = 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 267 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 268 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 269 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 270 | while(FMC->ISPTRG); |
sahilmgandhi | 18:6a4db94011d3 | 271 | } |
sahilmgandhi | 18:6a4db94011d3 | 272 | |
sahilmgandhi | 18:6a4db94011d3 | 273 | |
sahilmgandhi | 18:6a4db94011d3 | 274 | /** |
sahilmgandhi | 18:6a4db94011d3 | 275 | * @brief Read 32-bit Data from specified address of flash |
sahilmgandhi | 18:6a4db94011d3 | 276 | * |
sahilmgandhi | 18:6a4db94011d3 | 277 | * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG |
sahilmgandhi | 18:6a4db94011d3 | 278 | * |
sahilmgandhi | 18:6a4db94011d3 | 279 | * @return The data of specified address |
sahilmgandhi | 18:6a4db94011d3 | 280 | * |
sahilmgandhi | 18:6a4db94011d3 | 281 | * @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG. |
sahilmgandhi | 18:6a4db94011d3 | 282 | * |
sahilmgandhi | 18:6a4db94011d3 | 283 | */ |
sahilmgandhi | 18:6a4db94011d3 | 284 | static __INLINE uint32_t FMC_Read(uint32_t u32Addr) |
sahilmgandhi | 18:6a4db94011d3 | 285 | { |
sahilmgandhi | 18:6a4db94011d3 | 286 | FMC->ISPCMD = FMC_ISPCMD_READ; |
sahilmgandhi | 18:6a4db94011d3 | 287 | FMC->ISPADDR = u32Addr; |
sahilmgandhi | 18:6a4db94011d3 | 288 | FMC->ISPDAT = 0; |
sahilmgandhi | 18:6a4db94011d3 | 289 | FMC->ISPTRG = 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 290 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 291 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 292 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 293 | while(FMC->ISPTRG); |
sahilmgandhi | 18:6a4db94011d3 | 294 | |
sahilmgandhi | 18:6a4db94011d3 | 295 | return FMC->ISPDAT; |
sahilmgandhi | 18:6a4db94011d3 | 296 | } |
sahilmgandhi | 18:6a4db94011d3 | 297 | |
sahilmgandhi | 18:6a4db94011d3 | 298 | /** |
sahilmgandhi | 18:6a4db94011d3 | 299 | * @brief Flash page erase |
sahilmgandhi | 18:6a4db94011d3 | 300 | * |
sahilmgandhi | 18:6a4db94011d3 | 301 | * @param[in] u32Addr Flash address including APROM, LDROM, Data Flash, and CONFIG |
sahilmgandhi | 18:6a4db94011d3 | 302 | * |
sahilmgandhi | 18:6a4db94011d3 | 303 | * @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG. |
sahilmgandhi | 18:6a4db94011d3 | 304 | * The page size is 2048 bytes. |
sahilmgandhi | 18:6a4db94011d3 | 305 | * |
sahilmgandhi | 18:6a4db94011d3 | 306 | * @retval 0 Success |
sahilmgandhi | 18:6a4db94011d3 | 307 | * @retval -1 Erase failed |
sahilmgandhi | 18:6a4db94011d3 | 308 | * |
sahilmgandhi | 18:6a4db94011d3 | 309 | */ |
sahilmgandhi | 18:6a4db94011d3 | 310 | static __INLINE int32_t FMC_Erase(uint32_t u32Addr) |
sahilmgandhi | 18:6a4db94011d3 | 311 | { |
sahilmgandhi | 18:6a4db94011d3 | 312 | FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; |
sahilmgandhi | 18:6a4db94011d3 | 313 | FMC->ISPADDR = u32Addr; |
sahilmgandhi | 18:6a4db94011d3 | 314 | FMC->ISPTRG = 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 315 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 316 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 317 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 318 | while(FMC->ISPTRG); |
sahilmgandhi | 18:6a4db94011d3 | 319 | |
sahilmgandhi | 18:6a4db94011d3 | 320 | /* Check ISPFF flag to know whether erase OK or fail. */ |
sahilmgandhi | 18:6a4db94011d3 | 321 | if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) |
sahilmgandhi | 18:6a4db94011d3 | 322 | { |
sahilmgandhi | 18:6a4db94011d3 | 323 | FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 324 | return -1; |
sahilmgandhi | 18:6a4db94011d3 | 325 | } |
sahilmgandhi | 18:6a4db94011d3 | 326 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 327 | } |
sahilmgandhi | 18:6a4db94011d3 | 328 | |
sahilmgandhi | 18:6a4db94011d3 | 329 | /** |
sahilmgandhi | 18:6a4db94011d3 | 330 | * @brief Read Unique ID |
sahilmgandhi | 18:6a4db94011d3 | 331 | * |
sahilmgandhi | 18:6a4db94011d3 | 332 | * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] |
sahilmgandhi | 18:6a4db94011d3 | 333 | * |
sahilmgandhi | 18:6a4db94011d3 | 334 | * @return The 32-bit unique ID data of specified UID index. |
sahilmgandhi | 18:6a4db94011d3 | 335 | * |
sahilmgandhi | 18:6a4db94011d3 | 336 | * @details To read out 96-bit Unique ID. |
sahilmgandhi | 18:6a4db94011d3 | 337 | * |
sahilmgandhi | 18:6a4db94011d3 | 338 | */ |
sahilmgandhi | 18:6a4db94011d3 | 339 | static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index) |
sahilmgandhi | 18:6a4db94011d3 | 340 | { |
sahilmgandhi | 18:6a4db94011d3 | 341 | FMC->ISPCMD = FMC_ISPCMD_READ_UID; |
sahilmgandhi | 18:6a4db94011d3 | 342 | FMC->ISPADDR = (u8Index << 2); |
sahilmgandhi | 18:6a4db94011d3 | 343 | FMC->ISPDAT = 0; |
sahilmgandhi | 18:6a4db94011d3 | 344 | FMC->ISPTRG = 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 345 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 346 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 347 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 348 | while(FMC->ISPTRG); |
sahilmgandhi | 18:6a4db94011d3 | 349 | |
sahilmgandhi | 18:6a4db94011d3 | 350 | return FMC->ISPDAT; |
sahilmgandhi | 18:6a4db94011d3 | 351 | } |
sahilmgandhi | 18:6a4db94011d3 | 352 | |
sahilmgandhi | 18:6a4db94011d3 | 353 | /** |
sahilmgandhi | 18:6a4db94011d3 | 354 | * @brief Read company ID |
sahilmgandhi | 18:6a4db94011d3 | 355 | * |
sahilmgandhi | 18:6a4db94011d3 | 356 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 357 | * |
sahilmgandhi | 18:6a4db94011d3 | 358 | * @return The company ID (32-bit) |
sahilmgandhi | 18:6a4db94011d3 | 359 | * |
sahilmgandhi | 18:6a4db94011d3 | 360 | * @details The company ID of Nuvoton is fixed to be 0xDA |
sahilmgandhi | 18:6a4db94011d3 | 361 | * |
sahilmgandhi | 18:6a4db94011d3 | 362 | */ |
sahilmgandhi | 18:6a4db94011d3 | 363 | static __INLINE uint32_t FMC_ReadCID(void) |
sahilmgandhi | 18:6a4db94011d3 | 364 | { |
sahilmgandhi | 18:6a4db94011d3 | 365 | FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ |
sahilmgandhi | 18:6a4db94011d3 | 366 | FMC->ISPADDR = 0x0; /* Must keep 0x0 when read CID */ |
sahilmgandhi | 18:6a4db94011d3 | 367 | FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ |
sahilmgandhi | 18:6a4db94011d3 | 368 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 369 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 370 | #endif /* To make sure ISP/CPU be Synchronized */ |
sahilmgandhi | 18:6a4db94011d3 | 371 | while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ; /* Waiting for ISP Done */ |
sahilmgandhi | 18:6a4db94011d3 | 372 | |
sahilmgandhi | 18:6a4db94011d3 | 373 | return FMC->ISPDAT; |
sahilmgandhi | 18:6a4db94011d3 | 374 | } |
sahilmgandhi | 18:6a4db94011d3 | 375 | |
sahilmgandhi | 18:6a4db94011d3 | 376 | /** |
sahilmgandhi | 18:6a4db94011d3 | 377 | * @brief Read product ID |
sahilmgandhi | 18:6a4db94011d3 | 378 | * |
sahilmgandhi | 18:6a4db94011d3 | 379 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 380 | * |
sahilmgandhi | 18:6a4db94011d3 | 381 | * @return The product ID (32-bit) |
sahilmgandhi | 18:6a4db94011d3 | 382 | * |
sahilmgandhi | 18:6a4db94011d3 | 383 | * @details This function is used to read product ID. |
sahilmgandhi | 18:6a4db94011d3 | 384 | * |
sahilmgandhi | 18:6a4db94011d3 | 385 | */ |
sahilmgandhi | 18:6a4db94011d3 | 386 | static __INLINE uint32_t FMC_ReadPID(void) |
sahilmgandhi | 18:6a4db94011d3 | 387 | { |
sahilmgandhi | 18:6a4db94011d3 | 388 | FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ |
sahilmgandhi | 18:6a4db94011d3 | 389 | FMC->ISPADDR = 0x04; /* Must keep 0x4 when read PID */ |
sahilmgandhi | 18:6a4db94011d3 | 390 | FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ |
sahilmgandhi | 18:6a4db94011d3 | 391 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 392 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 393 | #endif /* To make sure ISP/CPU be Synchronized */ |
sahilmgandhi | 18:6a4db94011d3 | 394 | while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */ |
sahilmgandhi | 18:6a4db94011d3 | 395 | |
sahilmgandhi | 18:6a4db94011d3 | 396 | return FMC->ISPDAT; |
sahilmgandhi | 18:6a4db94011d3 | 397 | } |
sahilmgandhi | 18:6a4db94011d3 | 398 | |
sahilmgandhi | 18:6a4db94011d3 | 399 | /** |
sahilmgandhi | 18:6a4db94011d3 | 400 | * @brief To read UCID |
sahilmgandhi | 18:6a4db94011d3 | 401 | * |
sahilmgandhi | 18:6a4db94011d3 | 402 | * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. |
sahilmgandhi | 18:6a4db94011d3 | 403 | * |
sahilmgandhi | 18:6a4db94011d3 | 404 | * @return The UCID of specified index |
sahilmgandhi | 18:6a4db94011d3 | 405 | * |
sahilmgandhi | 18:6a4db94011d3 | 406 | * @details This function is used to read unique chip ID (UCID). |
sahilmgandhi | 18:6a4db94011d3 | 407 | * |
sahilmgandhi | 18:6a4db94011d3 | 408 | */ |
sahilmgandhi | 18:6a4db94011d3 | 409 | static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) |
sahilmgandhi | 18:6a4db94011d3 | 410 | { |
sahilmgandhi | 18:6a4db94011d3 | 411 | FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ |
sahilmgandhi | 18:6a4db94011d3 | 412 | FMC->ISPADDR = (0x04 * u32Index) + 0x10; /* The UCID is at offset 0x10 with word alignment. */ |
sahilmgandhi | 18:6a4db94011d3 | 413 | FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ |
sahilmgandhi | 18:6a4db94011d3 | 414 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 415 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 416 | #endif /* To make sure ISP/CPU be Synchronized */ |
sahilmgandhi | 18:6a4db94011d3 | 417 | while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */ |
sahilmgandhi | 18:6a4db94011d3 | 418 | |
sahilmgandhi | 18:6a4db94011d3 | 419 | return FMC->ISPDAT; |
sahilmgandhi | 18:6a4db94011d3 | 420 | } |
sahilmgandhi | 18:6a4db94011d3 | 421 | |
sahilmgandhi | 18:6a4db94011d3 | 422 | /** |
sahilmgandhi | 18:6a4db94011d3 | 423 | * @brief Set vector mapping address |
sahilmgandhi | 18:6a4db94011d3 | 424 | * |
sahilmgandhi | 18:6a4db94011d3 | 425 | * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. |
sahilmgandhi | 18:6a4db94011d3 | 426 | * |
sahilmgandhi | 18:6a4db94011d3 | 427 | * @return To set VECMAP to remap specified page address to 0x0. |
sahilmgandhi | 18:6a4db94011d3 | 428 | * |
sahilmgandhi | 18:6a4db94011d3 | 429 | * @details This function is used to set VECMAP to map specified page to vector page (0x0). |
sahilmgandhi | 18:6a4db94011d3 | 430 | * |
sahilmgandhi | 18:6a4db94011d3 | 431 | * @note |
sahilmgandhi | 18:6a4db94011d3 | 432 | * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) |
sahilmgandhi | 18:6a4db94011d3 | 433 | * |
sahilmgandhi | 18:6a4db94011d3 | 434 | */ |
sahilmgandhi | 18:6a4db94011d3 | 435 | static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) |
sahilmgandhi | 18:6a4db94011d3 | 436 | { |
sahilmgandhi | 18:6a4db94011d3 | 437 | FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ |
sahilmgandhi | 18:6a4db94011d3 | 438 | FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ |
sahilmgandhi | 18:6a4db94011d3 | 439 | FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */ |
sahilmgandhi | 18:6a4db94011d3 | 440 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 441 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 442 | #endif /* To make sure ISP/CPU be Synchronized */ |
sahilmgandhi | 18:6a4db94011d3 | 443 | while(FMC->ISPTRG); /* Waiting for ISP Done */ |
sahilmgandhi | 18:6a4db94011d3 | 444 | } |
sahilmgandhi | 18:6a4db94011d3 | 445 | |
sahilmgandhi | 18:6a4db94011d3 | 446 | /** |
sahilmgandhi | 18:6a4db94011d3 | 447 | * @brief Get current vector mapping address. |
sahilmgandhi | 18:6a4db94011d3 | 448 | * |
sahilmgandhi | 18:6a4db94011d3 | 449 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 450 | * |
sahilmgandhi | 18:6a4db94011d3 | 451 | * @return The current vector mapping address. |
sahilmgandhi | 18:6a4db94011d3 | 452 | * |
sahilmgandhi | 18:6a4db94011d3 | 453 | * @details To get VECMAP value which is the page address for remapping to vector page (0x0). |
sahilmgandhi | 18:6a4db94011d3 | 454 | * |
sahilmgandhi | 18:6a4db94011d3 | 455 | * @note |
sahilmgandhi | 18:6a4db94011d3 | 456 | * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) |
sahilmgandhi | 18:6a4db94011d3 | 457 | * |
sahilmgandhi | 18:6a4db94011d3 | 458 | */ |
sahilmgandhi | 18:6a4db94011d3 | 459 | static __INLINE uint32_t FMC_GetVECMAP(void) |
sahilmgandhi | 18:6a4db94011d3 | 460 | { |
sahilmgandhi | 18:6a4db94011d3 | 461 | return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 462 | } |
sahilmgandhi | 18:6a4db94011d3 | 463 | |
sahilmgandhi | 18:6a4db94011d3 | 464 | /** |
sahilmgandhi | 18:6a4db94011d3 | 465 | * @brief Get Flash Checksum |
sahilmgandhi | 18:6a4db94011d3 | 466 | * |
sahilmgandhi | 18:6a4db94011d3 | 467 | * @param[in] u32Addr Specific flash start address |
sahilmgandhi | 18:6a4db94011d3 | 468 | * @param[in] i32Size Specific a size of Flash area |
sahilmgandhi | 18:6a4db94011d3 | 469 | * |
sahilmgandhi | 18:6a4db94011d3 | 470 | * @return A checksum value of a flash block. |
sahilmgandhi | 18:6a4db94011d3 | 471 | * |
sahilmgandhi | 18:6a4db94011d3 | 472 | * @details To get VECMAP value which is the page address for remapping to vector page (0x0). |
sahilmgandhi | 18:6a4db94011d3 | 473 | * |
sahilmgandhi | 18:6a4db94011d3 | 474 | */ |
sahilmgandhi | 18:6a4db94011d3 | 475 | static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size) |
sahilmgandhi | 18:6a4db94011d3 | 476 | { |
sahilmgandhi | 18:6a4db94011d3 | 477 | FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM; |
sahilmgandhi | 18:6a4db94011d3 | 478 | FMC->ISPADDR = u32Addr; |
sahilmgandhi | 18:6a4db94011d3 | 479 | FMC->ISPDAT = i32Size; |
sahilmgandhi | 18:6a4db94011d3 | 480 | FMC->ISPTRG = 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 481 | #if ISBEN |
sahilmgandhi | 18:6a4db94011d3 | 482 | __ISB(); |
sahilmgandhi | 18:6a4db94011d3 | 483 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 484 | while(FMC->ISPTRG); |
sahilmgandhi | 18:6a4db94011d3 | 485 | |
sahilmgandhi | 18:6a4db94011d3 | 486 | FMC->ISPCMD = FMC_ISPCMD_CHECKSUM; |
sahilmgandhi | 18:6a4db94011d3 | 487 | FMC->ISPTRG = 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 488 | while(FMC->ISPTRG); |
sahilmgandhi | 18:6a4db94011d3 | 489 | |
sahilmgandhi | 18:6a4db94011d3 | 490 | return FMC->ISPDAT; |
sahilmgandhi | 18:6a4db94011d3 | 491 | } |
sahilmgandhi | 18:6a4db94011d3 | 492 | |
sahilmgandhi | 18:6a4db94011d3 | 493 | /** |
sahilmgandhi | 18:6a4db94011d3 | 494 | * @brief Program Multi-Word data into specified address of flash |
sahilmgandhi | 18:6a4db94011d3 | 495 | * |
sahilmgandhi | 18:6a4db94011d3 | 496 | * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG |
sahilmgandhi | 18:6a4db94011d3 | 497 | * @param[in] pu32Buf A data pointer is point to a data buffer start address; |
sahilmgandhi | 18:6a4db94011d3 | 498 | * |
sahilmgandhi | 18:6a4db94011d3 | 499 | * @return None |
sahilmgandhi | 18:6a4db94011d3 | 500 | * |
sahilmgandhi | 18:6a4db94011d3 | 501 | * @details To program multi-words data into Flash include APROM, LDROM, Data Flash, and CONFIG. |
sahilmgandhi | 18:6a4db94011d3 | 502 | * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual. |
sahilmgandhi | 18:6a4db94011d3 | 503 | * |
sahilmgandhi | 18:6a4db94011d3 | 504 | */ |
sahilmgandhi | 18:6a4db94011d3 | 505 | static __INLINE void FMC_Write256(uint32_t u32Addr, uint32_t *pu32Buf) |
sahilmgandhi | 18:6a4db94011d3 | 506 | { |
sahilmgandhi | 18:6a4db94011d3 | 507 | int32_t i, idx; |
sahilmgandhi | 18:6a4db94011d3 | 508 | volatile uint32_t *pu32IspData; |
sahilmgandhi | 18:6a4db94011d3 | 509 | //int32_t i32Err; |
sahilmgandhi | 18:6a4db94011d3 | 510 | |
sahilmgandhi | 18:6a4db94011d3 | 511 | //i32Err = 0; |
sahilmgandhi | 18:6a4db94011d3 | 512 | idx = 0; |
sahilmgandhi | 18:6a4db94011d3 | 513 | FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG; |
sahilmgandhi | 18:6a4db94011d3 | 514 | FMC->ISPADDR = u32Addr; |
sahilmgandhi | 18:6a4db94011d3 | 515 | |
sahilmgandhi | 18:6a4db94011d3 | 516 | retrigger: |
sahilmgandhi | 18:6a4db94011d3 | 517 | |
sahilmgandhi | 18:6a4db94011d3 | 518 | //if(i32Err) |
sahilmgandhi | 18:6a4db94011d3 | 519 | // printf("idx=%d ISPADDR = 0x%08x\n",idx, FMC->ISPADDR); |
sahilmgandhi | 18:6a4db94011d3 | 520 | |
sahilmgandhi | 18:6a4db94011d3 | 521 | FMC->MPDAT0 = pu32Buf[idx + 0]; |
sahilmgandhi | 18:6a4db94011d3 | 522 | FMC->MPDAT1 = pu32Buf[idx + 1]; |
sahilmgandhi | 18:6a4db94011d3 | 523 | FMC->MPDAT2 = pu32Buf[idx + 2]; |
sahilmgandhi | 18:6a4db94011d3 | 524 | FMC->MPDAT3 = pu32Buf[idx + 3]; |
sahilmgandhi | 18:6a4db94011d3 | 525 | |
sahilmgandhi | 18:6a4db94011d3 | 526 | |
sahilmgandhi | 18:6a4db94011d3 | 527 | |
sahilmgandhi | 18:6a4db94011d3 | 528 | FMC->ISPTRG = 0x1; |
sahilmgandhi | 18:6a4db94011d3 | 529 | |
sahilmgandhi | 18:6a4db94011d3 | 530 | pu32IspData = &FMC->MPDAT0; |
sahilmgandhi | 18:6a4db94011d3 | 531 | idx += 4; |
sahilmgandhi | 18:6a4db94011d3 | 532 | |
sahilmgandhi | 18:6a4db94011d3 | 533 | for(i = idx; i < 256 / 4; i += 4) // Max data length is 256 bytes (256/4 words) |
sahilmgandhi | 18:6a4db94011d3 | 534 | { |
sahilmgandhi | 18:6a4db94011d3 | 535 | |
sahilmgandhi | 18:6a4db94011d3 | 536 | __set_PRIMASK(1); // Mask interrupt to avoid status check coherence error |
sahilmgandhi | 18:6a4db94011d3 | 537 | do |
sahilmgandhi | 18:6a4db94011d3 | 538 | { |
sahilmgandhi | 18:6a4db94011d3 | 539 | if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0) |
sahilmgandhi | 18:6a4db94011d3 | 540 | { |
sahilmgandhi | 18:6a4db94011d3 | 541 | __set_PRIMASK(0); |
sahilmgandhi | 18:6a4db94011d3 | 542 | //printf("%d %x\n", i, FMC->MPADDR); |
sahilmgandhi | 18:6a4db94011d3 | 543 | FMC->ISPADDR = FMC->MPADDR & (~0xful); |
sahilmgandhi | 18:6a4db94011d3 | 544 | idx = (FMC->ISPADDR - u32Addr) / 4; |
sahilmgandhi | 18:6a4db94011d3 | 545 | //i32Err = -1; |
sahilmgandhi | 18:6a4db94011d3 | 546 | goto retrigger; |
sahilmgandhi | 18:6a4db94011d3 | 547 | } |
sahilmgandhi | 18:6a4db94011d3 | 548 | } |
sahilmgandhi | 18:6a4db94011d3 | 549 | while(FMC->MPSTS & (3 << FMC_MPSTS_D0_Pos)); |
sahilmgandhi | 18:6a4db94011d3 | 550 | |
sahilmgandhi | 18:6a4db94011d3 | 551 | // Update new data for D0 |
sahilmgandhi | 18:6a4db94011d3 | 552 | pu32IspData[0] = pu32Buf[i ]; |
sahilmgandhi | 18:6a4db94011d3 | 553 | pu32IspData[1] = pu32Buf[i + 1]; |
sahilmgandhi | 18:6a4db94011d3 | 554 | |
sahilmgandhi | 18:6a4db94011d3 | 555 | do |
sahilmgandhi | 18:6a4db94011d3 | 556 | { |
sahilmgandhi | 18:6a4db94011d3 | 557 | if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0) |
sahilmgandhi | 18:6a4db94011d3 | 558 | { |
sahilmgandhi | 18:6a4db94011d3 | 559 | __set_PRIMASK(0); |
sahilmgandhi | 18:6a4db94011d3 | 560 | //printf("%d %x\n", i, FMC->MPADDR); |
sahilmgandhi | 18:6a4db94011d3 | 561 | FMC->ISPADDR = FMC->MPADDR & (~0xful); |
sahilmgandhi | 18:6a4db94011d3 | 562 | idx = (FMC->ISPADDR - u32Addr) / 4; |
sahilmgandhi | 18:6a4db94011d3 | 563 | //i32Err = -1; |
sahilmgandhi | 18:6a4db94011d3 | 564 | goto retrigger; |
sahilmgandhi | 18:6a4db94011d3 | 565 | } |
sahilmgandhi | 18:6a4db94011d3 | 566 | } |
sahilmgandhi | 18:6a4db94011d3 | 567 | while(FMC->MPSTS & (3 << FMC_MPSTS_D2_Pos)); |
sahilmgandhi | 18:6a4db94011d3 | 568 | |
sahilmgandhi | 18:6a4db94011d3 | 569 | // Update new data for D2 |
sahilmgandhi | 18:6a4db94011d3 | 570 | pu32IspData[2] = pu32Buf[i + 2]; |
sahilmgandhi | 18:6a4db94011d3 | 571 | pu32IspData[3] = pu32Buf[i + 3]; |
sahilmgandhi | 18:6a4db94011d3 | 572 | __set_PRIMASK(0); |
sahilmgandhi | 18:6a4db94011d3 | 573 | } |
sahilmgandhi | 18:6a4db94011d3 | 574 | |
sahilmgandhi | 18:6a4db94011d3 | 575 | while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk); |
sahilmgandhi | 18:6a4db94011d3 | 576 | } |
sahilmgandhi | 18:6a4db94011d3 | 577 | |
sahilmgandhi | 18:6a4db94011d3 | 578 | void FMC_Open(void); |
sahilmgandhi | 18:6a4db94011d3 | 579 | void FMC_Close(void); |
sahilmgandhi | 18:6a4db94011d3 | 580 | void FMC_EnableAPUpdate(void); |
sahilmgandhi | 18:6a4db94011d3 | 581 | void FMC_DisableAPUpdate(void); |
sahilmgandhi | 18:6a4db94011d3 | 582 | void FMC_EnableConfigUpdate(void); |
sahilmgandhi | 18:6a4db94011d3 | 583 | void FMC_DisableConfigUpdate(void); |
sahilmgandhi | 18:6a4db94011d3 | 584 | void FMC_EnableLDUpdate(void); |
sahilmgandhi | 18:6a4db94011d3 | 585 | void FMC_DisableLDUpdate(void); |
sahilmgandhi | 18:6a4db94011d3 | 586 | int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count); |
sahilmgandhi | 18:6a4db94011d3 | 587 | int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count); |
sahilmgandhi | 18:6a4db94011d3 | 588 | void FMC_SetBootSource(int32_t i32BootSrc); |
sahilmgandhi | 18:6a4db94011d3 | 589 | int32_t FMC_GetBootSource(void); |
sahilmgandhi | 18:6a4db94011d3 | 590 | uint32_t FMC_ReadDataFlashBaseAddr(void); |
sahilmgandhi | 18:6a4db94011d3 | 591 | void FMC_EnableFreqOptimizeMode(uint32_t u32Mode); |
sahilmgandhi | 18:6a4db94011d3 | 592 | void FMC_DisableFreqOptimizeMode(void); |
sahilmgandhi | 18:6a4db94011d3 | 593 | /*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ |
sahilmgandhi | 18:6a4db94011d3 | 594 | |
sahilmgandhi | 18:6a4db94011d3 | 595 | /*@}*/ /* end of group FMC_Driver */ |
sahilmgandhi | 18:6a4db94011d3 | 596 | |
sahilmgandhi | 18:6a4db94011d3 | 597 | /*@}*/ /* end of group Standard_Driver */ |
sahilmgandhi | 18:6a4db94011d3 | 598 | |
sahilmgandhi | 18:6a4db94011d3 | 599 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 600 | } |
sahilmgandhi | 18:6a4db94011d3 | 601 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 602 | |
sahilmgandhi | 18:6a4db94011d3 | 603 | |
sahilmgandhi | 18:6a4db94011d3 | 604 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 605 |