MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/nrf_drv_config.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

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sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015 Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 3 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 6 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * 1. Redistributions of source code must retain the above copyright notice, this list
sahilmgandhi 18:6a4db94011d3 9 * of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
sahilmgandhi 18:6a4db94011d3 12 * integrated circuit in a product or a software update for such product, must reproduce
sahilmgandhi 18:6a4db94011d3 13 * the above copyright notice, this list of conditions and the following disclaimer in
sahilmgandhi 18:6a4db94011d3 14 * the documentation and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
sahilmgandhi 18:6a4db94011d3 17 * used to endorse or promote products derived from this software without specific prior
sahilmgandhi 18:6a4db94011d3 18 * written permission.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * 4. This software, with or without modification, must only be used with a
sahilmgandhi 18:6a4db94011d3 21 * Nordic Semiconductor ASA integrated circuit.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * 5. Any software provided in binary or object form under this license must not be reverse
sahilmgandhi 18:6a4db94011d3 24 * engineered, decompiled, modified and/or disassembled.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
sahilmgandhi 18:6a4db94011d3 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 36 *
sahilmgandhi 18:6a4db94011d3 37 */
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 #ifndef NRF_DRV_CONFIG_H
sahilmgandhi 18:6a4db94011d3 41 #define NRF_DRV_CONFIG_H
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 /**
sahilmgandhi 18:6a4db94011d3 44 * Provide a non-zero value here in applications that need to use several
sahilmgandhi 18:6a4db94011d3 45 * peripherals with the same ID that are sharing certain resources
sahilmgandhi 18:6a4db94011d3 46 * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
sahilmgandhi 18:6a4db94011d3 47 * simultaneously. Therefore, this definition allows to initialize the driver
sahilmgandhi 18:6a4db94011d3 48 * for another peripheral from a given group only after the previously used one
sahilmgandhi 18:6a4db94011d3 49 * is uninitialized. Normally, this is not possible, because interrupt handlers
sahilmgandhi 18:6a4db94011d3 50 * are implemented in individual drivers.
sahilmgandhi 18:6a4db94011d3 51 * This functionality requires a more complicated interrupt handling and driver
sahilmgandhi 18:6a4db94011d3 52 * initialization, hence it is not always desirable to use it.
sahilmgandhi 18:6a4db94011d3 53 */
sahilmgandhi 18:6a4db94011d3 54 #define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 /* CLOCK */
sahilmgandhi 18:6a4db94011d3 57 #define CLOCK_ENABLED 1
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 #if (CLOCK_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 60 #define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
sahilmgandhi 18:6a4db94011d3 61 #define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
sahilmgandhi 18:6a4db94011d3 62 #define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 63 #endif
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /* GPIOTE */
sahilmgandhi 18:6a4db94011d3 66 #define GPIOTE_ENABLED 1
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 #if (GPIOTE_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 69 #define GPIOTE_CONFIG_USE_SWI_EGU false
sahilmgandhi 18:6a4db94011d3 70 #define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 71 #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8
sahilmgandhi 18:6a4db94011d3 72 #endif
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* TIMER */
sahilmgandhi 18:6a4db94011d3 75 #ifdef SOFTDEVICE_PRESENT
sahilmgandhi 18:6a4db94011d3 76 #define TIMER0_ENABLED 0
sahilmgandhi 18:6a4db94011d3 77 #else
sahilmgandhi 18:6a4db94011d3 78 #define TIMER0_ENABLED 1
sahilmgandhi 18:6a4db94011d3 79 #endif
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 #if (TIMER0_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 82 #define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
sahilmgandhi 18:6a4db94011d3 83 #define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
sahilmgandhi 18:6a4db94011d3 84 #define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
sahilmgandhi 18:6a4db94011d3 85 #define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 #define TIMER0_INSTANCE_INDEX 0
sahilmgandhi 18:6a4db94011d3 88 #endif
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 #define TIMER1_ENABLED 1
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 #if (TIMER1_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 93 #define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
sahilmgandhi 18:6a4db94011d3 94 #define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
sahilmgandhi 18:6a4db94011d3 95 #define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
sahilmgandhi 18:6a4db94011d3 96 #define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 #define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
sahilmgandhi 18:6a4db94011d3 99 #endif
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 #define TIMER2_ENABLED 1
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 #if (TIMER2_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 104 #define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
sahilmgandhi 18:6a4db94011d3 105 #define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
sahilmgandhi 18:6a4db94011d3 106 #define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
sahilmgandhi 18:6a4db94011d3 107 #define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 #define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
sahilmgandhi 18:6a4db94011d3 110 #endif
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 #define TIMER3_ENABLED 0
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 #if (TIMER3_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 115 #define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
sahilmgandhi 18:6a4db94011d3 116 #define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
sahilmgandhi 18:6a4db94011d3 117 #define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
sahilmgandhi 18:6a4db94011d3 118 #define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 #define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
sahilmgandhi 18:6a4db94011d3 121 #endif
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 #define TIMER4_ENABLED 0
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 #if (TIMER4_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 126 #define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
sahilmgandhi 18:6a4db94011d3 127 #define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
sahilmgandhi 18:6a4db94011d3 128 #define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
sahilmgandhi 18:6a4db94011d3 129 #define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 #define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
sahilmgandhi 18:6a4db94011d3 132 #endif
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 #define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 /* RTC */
sahilmgandhi 18:6a4db94011d3 138 #define RTC0_ENABLED 0
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 #if (RTC0_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 141 #define RTC0_CONFIG_FREQUENCY 32678
sahilmgandhi 18:6a4db94011d3 142 #define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 143 #define RTC0_CONFIG_RELIABLE false
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 #define RTC0_INSTANCE_INDEX 0
sahilmgandhi 18:6a4db94011d3 146 #endif
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 #define RTC1_ENABLED 0
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 #if (RTC1_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 151 #define RTC1_CONFIG_FREQUENCY 32768
sahilmgandhi 18:6a4db94011d3 152 #define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 153 #define RTC1_CONFIG_RELIABLE false
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 #define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
sahilmgandhi 18:6a4db94011d3 156 #endif
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 #define RTC2_ENABLED 0
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 #if (RTC2_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 161 #define RTC2_CONFIG_FREQUENCY 32768
sahilmgandhi 18:6a4db94011d3 162 #define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 163 #define RTC2_CONFIG_RELIABLE false
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 #define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
sahilmgandhi 18:6a4db94011d3 166 #endif
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 #define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 #define NRF_MAXIMUM_LATENCY_US 2000
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /* RNG */
sahilmgandhi 18:6a4db94011d3 174 #define RNG_ENABLED 0
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 #if (RNG_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 177 #define RNG_CONFIG_ERROR_CORRECTION true
sahilmgandhi 18:6a4db94011d3 178 #define RNG_CONFIG_POOL_SIZE 8
sahilmgandhi 18:6a4db94011d3 179 #define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 180 #endif
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 /* PWM */
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 #define PWM0_ENABLED 0
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 #if (PWM0_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 187 #define PWM0_CONFIG_OUT0_PIN 2
sahilmgandhi 18:6a4db94011d3 188 #define PWM0_CONFIG_OUT1_PIN 3
sahilmgandhi 18:6a4db94011d3 189 #define PWM0_CONFIG_OUT2_PIN 4
sahilmgandhi 18:6a4db94011d3 190 #define PWM0_CONFIG_OUT3_PIN 5
sahilmgandhi 18:6a4db94011d3 191 #define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 192 #define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
sahilmgandhi 18:6a4db94011d3 193 #define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
sahilmgandhi 18:6a4db94011d3 194 #define PWM0_CONFIG_TOP_VALUE 1000
sahilmgandhi 18:6a4db94011d3 195 #define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
sahilmgandhi 18:6a4db94011d3 196 #define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 #define PWM0_INSTANCE_INDEX 0
sahilmgandhi 18:6a4db94011d3 199 #endif
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 #define PWM1_ENABLED 0
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 #if (PWM1_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 204 #define PWM1_CONFIG_OUT0_PIN 2
sahilmgandhi 18:6a4db94011d3 205 #define PWM1_CONFIG_OUT1_PIN 3
sahilmgandhi 18:6a4db94011d3 206 #define PWM1_CONFIG_OUT2_PIN 4
sahilmgandhi 18:6a4db94011d3 207 #define PWM1_CONFIG_OUT3_PIN 5
sahilmgandhi 18:6a4db94011d3 208 #define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 209 #define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
sahilmgandhi 18:6a4db94011d3 210 #define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
sahilmgandhi 18:6a4db94011d3 211 #define PWM1_CONFIG_TOP_VALUE 1000
sahilmgandhi 18:6a4db94011d3 212 #define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
sahilmgandhi 18:6a4db94011d3 213 #define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 #define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
sahilmgandhi 18:6a4db94011d3 216 #endif
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 #define PWM2_ENABLED 0
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 #if (PWM2_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 221 #define PWM2_CONFIG_OUT0_PIN 2
sahilmgandhi 18:6a4db94011d3 222 #define PWM2_CONFIG_OUT1_PIN 3
sahilmgandhi 18:6a4db94011d3 223 #define PWM2_CONFIG_OUT2_PIN 4
sahilmgandhi 18:6a4db94011d3 224 #define PWM2_CONFIG_OUT3_PIN 5
sahilmgandhi 18:6a4db94011d3 225 #define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 226 #define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
sahilmgandhi 18:6a4db94011d3 227 #define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
sahilmgandhi 18:6a4db94011d3 228 #define PWM2_CONFIG_TOP_VALUE 1000
sahilmgandhi 18:6a4db94011d3 229 #define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
sahilmgandhi 18:6a4db94011d3 230 #define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 #define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
sahilmgandhi 18:6a4db94011d3 233 #endif
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 #define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /* SPI */
sahilmgandhi 18:6a4db94011d3 238 #define SPI0_ENABLED 0
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 #if (SPI0_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 241 #define SPI0_USE_EASY_DMA 0
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 #define SPI0_CONFIG_SCK_PIN 2
sahilmgandhi 18:6a4db94011d3 244 #define SPI0_CONFIG_MOSI_PIN 3
sahilmgandhi 18:6a4db94011d3 245 #define SPI0_CONFIG_MISO_PIN 4
sahilmgandhi 18:6a4db94011d3 246 #define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 #define SPI0_INSTANCE_INDEX 0
sahilmgandhi 18:6a4db94011d3 249 #endif
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 #define SPI1_ENABLED 1
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 #if (SPI1_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 254 #define SPI1_USE_EASY_DMA 0
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 #define SPI1_CONFIG_SCK_PIN 2
sahilmgandhi 18:6a4db94011d3 257 #define SPI1_CONFIG_MOSI_PIN 3
sahilmgandhi 18:6a4db94011d3 258 #define SPI1_CONFIG_MISO_PIN 4
sahilmgandhi 18:6a4db94011d3 259 #define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 #define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
sahilmgandhi 18:6a4db94011d3 262 #endif
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 #define SPI2_ENABLED 0
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 #if (SPI2_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 267 #define SPI2_USE_EASY_DMA 0
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 #define SPI2_CONFIG_SCK_PIN 2
sahilmgandhi 18:6a4db94011d3 270 #define SPI2_CONFIG_MOSI_PIN 3
sahilmgandhi 18:6a4db94011d3 271 #define SPI2_CONFIG_MISO_PIN 4
sahilmgandhi 18:6a4db94011d3 272 #define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 #define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
sahilmgandhi 18:6a4db94011d3 275 #endif
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 #define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /* SPIS */
sahilmgandhi 18:6a4db94011d3 280 #define SPIS0_ENABLED 0
sahilmgandhi 18:6a4db94011d3 281
sahilmgandhi 18:6a4db94011d3 282 #if (SPIS0_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 283 #define SPIS0_CONFIG_SCK_PIN 2
sahilmgandhi 18:6a4db94011d3 284 #define SPIS0_CONFIG_MOSI_PIN 3
sahilmgandhi 18:6a4db94011d3 285 #define SPIS0_CONFIG_MISO_PIN 4
sahilmgandhi 18:6a4db94011d3 286 #define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 #define SPIS0_INSTANCE_INDEX 0
sahilmgandhi 18:6a4db94011d3 289 #endif
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 #define SPIS1_ENABLED 1
sahilmgandhi 18:6a4db94011d3 292
sahilmgandhi 18:6a4db94011d3 293 #if (SPIS1_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 294 #define SPIS1_CONFIG_SCK_PIN 2
sahilmgandhi 18:6a4db94011d3 295 #define SPIS1_CONFIG_MOSI_PIN 3
sahilmgandhi 18:6a4db94011d3 296 #define SPIS1_CONFIG_MISO_PIN 4
sahilmgandhi 18:6a4db94011d3 297 #define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 #define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
sahilmgandhi 18:6a4db94011d3 300 #endif
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 #define SPIS2_ENABLED 0
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 #if (SPIS2_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 305 #define SPIS2_CONFIG_SCK_PIN 2
sahilmgandhi 18:6a4db94011d3 306 #define SPIS2_CONFIG_MOSI_PIN 3
sahilmgandhi 18:6a4db94011d3 307 #define SPIS2_CONFIG_MISO_PIN 4
sahilmgandhi 18:6a4db94011d3 308 #define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 #define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
sahilmgandhi 18:6a4db94011d3 311 #endif
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 #define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 /* UART */
sahilmgandhi 18:6a4db94011d3 316 #define UART0_ENABLED 1
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 #if (UART0_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 319 #define UART0_CONFIG_HWFC NRF_UART_HWFC_ENABLED
sahilmgandhi 18:6a4db94011d3 320 #define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
sahilmgandhi 18:6a4db94011d3 321 #define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_9600
sahilmgandhi 18:6a4db94011d3 322 #define UART0_CONFIG_PSEL_TXD 9
sahilmgandhi 18:6a4db94011d3 323 #define UART0_CONFIG_PSEL_RXD 11
sahilmgandhi 18:6a4db94011d3 324 #define UART0_CONFIG_PSEL_CTS 10
sahilmgandhi 18:6a4db94011d3 325 #define UART0_CONFIG_PSEL_RTS 8
sahilmgandhi 18:6a4db94011d3 326 #define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
sahilmgandhi 18:6a4db94011d3 327 #ifdef NRF52
sahilmgandhi 18:6a4db94011d3 328 #define UART0_CONFIG_USE_EASY_DMA false
sahilmgandhi 18:6a4db94011d3 329 //Compile time flag
sahilmgandhi 18:6a4db94011d3 330 #define UART_EASY_DMA_SUPPORT 1
sahilmgandhi 18:6a4db94011d3 331 #define UART_LEGACY_SUPPORT 1
sahilmgandhi 18:6a4db94011d3 332 #endif //NRF52
sahilmgandhi 18:6a4db94011d3 333 #endif
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 #define TWI0_ENABLED 1
sahilmgandhi 18:6a4db94011d3 336
sahilmgandhi 18:6a4db94011d3 337 #if (TWI0_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 338 #define TWI0_USE_EASY_DMA 0
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 #define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
sahilmgandhi 18:6a4db94011d3 341 #define TWI0_CONFIG_SCL 0
sahilmgandhi 18:6a4db94011d3 342 #define TWI0_CONFIG_SDA 1
sahilmgandhi 18:6a4db94011d3 343 #define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 #define TWI0_INSTANCE_INDEX 0
sahilmgandhi 18:6a4db94011d3 346 #endif
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 #define TWI1_ENABLED 1
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 #if (TWI1_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 351 #define TWI1_USE_EASY_DMA 0
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 #define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
sahilmgandhi 18:6a4db94011d3 354 #define TWI1_CONFIG_SCL 0
sahilmgandhi 18:6a4db94011d3 355 #define TWI1_CONFIG_SDA 1
sahilmgandhi 18:6a4db94011d3 356 #define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 #define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
sahilmgandhi 18:6a4db94011d3 359 #endif
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 #define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 /* TWIS */
sahilmgandhi 18:6a4db94011d3 364 #define TWIS0_ENABLED 0
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 #if (TWIS0_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 367 #define TWIS0_CONFIG_ADDR0 0
sahilmgandhi 18:6a4db94011d3 368 #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
sahilmgandhi 18:6a4db94011d3 369 #define TWIS0_CONFIG_SCL 0
sahilmgandhi 18:6a4db94011d3 370 #define TWIS0_CONFIG_SDA 1
sahilmgandhi 18:6a4db94011d3 371 #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 #define TWIS0_INSTANCE_INDEX 0
sahilmgandhi 18:6a4db94011d3 374 #endif
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 #define TWIS1_ENABLED 0
sahilmgandhi 18:6a4db94011d3 377
sahilmgandhi 18:6a4db94011d3 378 #if (TWIS1_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 379 #define TWIS1_CONFIG_ADDR0 0
sahilmgandhi 18:6a4db94011d3 380 #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
sahilmgandhi 18:6a4db94011d3 381 #define TWIS1_CONFIG_SCL 0
sahilmgandhi 18:6a4db94011d3 382 #define TWIS1_CONFIG_SDA 1
sahilmgandhi 18:6a4db94011d3 383 #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
sahilmgandhi 18:6a4db94011d3 386 #endif
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 #define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
sahilmgandhi 18:6a4db94011d3 389 /* For more documentation see nrf_drv_twis.h file */
sahilmgandhi 18:6a4db94011d3 390 #define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
sahilmgandhi 18:6a4db94011d3 391 /* For more documentation see nrf_drv_twis.h file */
sahilmgandhi 18:6a4db94011d3 392 #define TWIS_NO_SYNC_MODE 0
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 /* QDEC */
sahilmgandhi 18:6a4db94011d3 395 #define QDEC_ENABLED 0
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 #if (QDEC_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 398 #define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
sahilmgandhi 18:6a4db94011d3 399 #define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
sahilmgandhi 18:6a4db94011d3 400 #define QDEC_CONFIG_PIO_A 1
sahilmgandhi 18:6a4db94011d3 401 #define QDEC_CONFIG_PIO_B 2
sahilmgandhi 18:6a4db94011d3 402 #define QDEC_CONFIG_PIO_LED 3
sahilmgandhi 18:6a4db94011d3 403 #define QDEC_CONFIG_LEDPRE 511
sahilmgandhi 18:6a4db94011d3 404 #define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
sahilmgandhi 18:6a4db94011d3 405 #define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 406 #define QDEC_CONFIG_DBFEN false
sahilmgandhi 18:6a4db94011d3 407 #define QDEC_CONFIG_SAMPLE_INTEN false
sahilmgandhi 18:6a4db94011d3 408 #endif
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 /* ADC */
sahilmgandhi 18:6a4db94011d3 411 #define ADC_ENABLED 1
sahilmgandhi 18:6a4db94011d3 412
sahilmgandhi 18:6a4db94011d3 413 #if (ADC_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 414 #define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 415 #endif
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 /* SAADC */
sahilmgandhi 18:6a4db94011d3 419 #define SAADC_ENABLED 0
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 #if (SAADC_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 422 #define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
sahilmgandhi 18:6a4db94011d3 423 #define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
sahilmgandhi 18:6a4db94011d3 424 #define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 425 #endif
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /* PDM */
sahilmgandhi 18:6a4db94011d3 428 #define PDM_ENABLED 0
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 #if (PDM_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 431 #define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
sahilmgandhi 18:6a4db94011d3 432 #define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
sahilmgandhi 18:6a4db94011d3 433 #define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
sahilmgandhi 18:6a4db94011d3 434 #define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 435 #endif
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /* COMP */
sahilmgandhi 18:6a4db94011d3 438 #define COMP_ENABLED 0
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 #if (COMP_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 441 #define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
sahilmgandhi 18:6a4db94011d3 442 #define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
sahilmgandhi 18:6a4db94011d3 443 #define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
sahilmgandhi 18:6a4db94011d3 444 #define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
sahilmgandhi 18:6a4db94011d3 445 #define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
sahilmgandhi 18:6a4db94011d3 446 #define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 447 #define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
sahilmgandhi 18:6a4db94011d3 448 #endif
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 /* LPCOMP */
sahilmgandhi 18:6a4db94011d3 451 #define LPCOMP_ENABLED 0
sahilmgandhi 18:6a4db94011d3 452
sahilmgandhi 18:6a4db94011d3 453 #if (LPCOMP_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 454 #define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
sahilmgandhi 18:6a4db94011d3 455 #define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
sahilmgandhi 18:6a4db94011d3 456 #define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
sahilmgandhi 18:6a4db94011d3 457 #define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
sahilmgandhi 18:6a4db94011d3 458 #endif
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 /* WDT */
sahilmgandhi 18:6a4db94011d3 461 #define WDT_ENABLED 0
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 #if (WDT_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 464 #define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
sahilmgandhi 18:6a4db94011d3 465 #define WDT_CONFIG_RELOAD_VALUE 2000
sahilmgandhi 18:6a4db94011d3 466 #define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
sahilmgandhi 18:6a4db94011d3 467 #endif
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 /* SWI EGU */
sahilmgandhi 18:6a4db94011d3 470 #ifdef NRF52
sahilmgandhi 18:6a4db94011d3 471 #define EGU_ENABLED 0
sahilmgandhi 18:6a4db94011d3 472 #endif
sahilmgandhi 18:6a4db94011d3 473
sahilmgandhi 18:6a4db94011d3 474 /* I2S */
sahilmgandhi 18:6a4db94011d3 475 #define I2S_ENABLED 0
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 #if (I2S_ENABLED == 1)
sahilmgandhi 18:6a4db94011d3 478 #define I2S_CONFIG_SCK_PIN 22
sahilmgandhi 18:6a4db94011d3 479 #define I2S_CONFIG_LRCK_PIN 23
sahilmgandhi 18:6a4db94011d3 480 #define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
sahilmgandhi 18:6a4db94011d3 481 #define I2S_CONFIG_SDOUT_PIN 24
sahilmgandhi 18:6a4db94011d3 482 #define I2S_CONFIG_SDIN_PIN 25
sahilmgandhi 18:6a4db94011d3 483 #define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
sahilmgandhi 18:6a4db94011d3 484 #define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
sahilmgandhi 18:6a4db94011d3 485 #define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
sahilmgandhi 18:6a4db94011d3 486 #define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
sahilmgandhi 18:6a4db94011d3 487 #define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
sahilmgandhi 18:6a4db94011d3 488 #define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
sahilmgandhi 18:6a4db94011d3 489 #define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
sahilmgandhi 18:6a4db94011d3 490 #define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
sahilmgandhi 18:6a4db94011d3 491 #endif
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 #include "nrf_drv_config_validation.h"
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 #endif // NRF_DRV_CONFIG_H