Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 * \file
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver
sahilmgandhi 18:6a4db94011d3 5 * for SAM.
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * \asf_license_start
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * \page License
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 14 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 17 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 20 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 21 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 22 *
sahilmgandhi 18:6a4db94011d3 23 * 3. The name of Atmel may not be used to endorse or promote products derived
sahilmgandhi 18:6a4db94011d3 24 * from this software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * 4. This software may only be redistributed and used in connection with an
sahilmgandhi 18:6a4db94011d3 27 * Atmel microcontroller product.
sahilmgandhi 18:6a4db94011d3 28 *
sahilmgandhi 18:6a4db94011d3 29 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
sahilmgandhi 18:6a4db94011d3 30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
sahilmgandhi 18:6a4db94011d3 32 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 33 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
sahilmgandhi 18:6a4db94011d3 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
sahilmgandhi 18:6a4db94011d3 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
sahilmgandhi 18:6a4db94011d3 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
sahilmgandhi 18:6a4db94011d3 38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
sahilmgandhi 18:6a4db94011d3 39 * POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 40 *
sahilmgandhi 18:6a4db94011d3 41 * \asf_license_stop
sahilmgandhi 18:6a4db94011d3 42 *
sahilmgandhi 18:6a4db94011d3 43 */
sahilmgandhi 18:6a4db94011d3 44 /*
sahilmgandhi 18:6a4db94011d3 45 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
sahilmgandhi 18:6a4db94011d3 46 */
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 #ifndef USART_H_INCLUDED
sahilmgandhi 18:6a4db94011d3 49 #define USART_H_INCLUDED
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 #include "compiler.h"
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /**
sahilmgandhi 18:6a4db94011d3 54 * \defgroup group_sam_drivers_usart Universal Synchronous Asynchronous Receiver
sahilmgandhi 18:6a4db94011d3 55 * Transmitter (USART).
sahilmgandhi 18:6a4db94011d3 56 *
sahilmgandhi 18:6a4db94011d3 57 * See \ref sam_usart_quickstart.
sahilmgandhi 18:6a4db94011d3 58 *
sahilmgandhi 18:6a4db94011d3 59 * This is a low-level driver implementation for the SAM Universal
sahilmgandhi 18:6a4db94011d3 60 * Synchronous/Asynchronous Receiver/Transmitter.
sahilmgandhi 18:6a4db94011d3 61 *
sahilmgandhi 18:6a4db94011d3 62 * @{
sahilmgandhi 18:6a4db94011d3 63 */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /// @cond 0
sahilmgandhi 18:6a4db94011d3 66 /**INDENT-OFF**/
sahilmgandhi 18:6a4db94011d3 67 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 68 extern "C" {
sahilmgandhi 18:6a4db94011d3 69 #endif
sahilmgandhi 18:6a4db94011d3 70 /**INDENT-ON**/
sahilmgandhi 18:6a4db94011d3 71 /// @endcond
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 /** Clock phase. */
sahilmgandhi 18:6a4db94011d3 74 #define SPI_CPHA (1 << 0)
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 /** Clock polarity. */
sahilmgandhi 18:6a4db94011d3 77 #define SPI_CPOL (1 << 1)
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /** SPI mode definition. */
sahilmgandhi 18:6a4db94011d3 80 #define SPI_MODE_0 0
sahilmgandhi 18:6a4db94011d3 81 #define SPI_MODE_1 (SPI_CPHA)
sahilmgandhi 18:6a4db94011d3 82 #define SPI_MODE_2 (SPI_CPOL)
sahilmgandhi 18:6a4db94011d3 83 #define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /**micro definition for LIN mode of SAMV71*/
sahilmgandhi 18:6a4db94011d3 86 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 87 #define US_MR_USART_MODE_LIN_MASTER 0x0A
sahilmgandhi 18:6a4db94011d3 88 #define US_MR_USART_MODE_LIN_SLAVE 0x0B
sahilmgandhi 18:6a4db94011d3 89 #endif
sahilmgandhi 18:6a4db94011d3 90 /* Input parameters when initializing RS232 and similar modes. */
sahilmgandhi 18:6a4db94011d3 91 typedef struct {
sahilmgandhi 18:6a4db94011d3 92 /* Set baud rate of the USART (unused in slave modes). */
sahilmgandhi 18:6a4db94011d3 93 uint32_t baudrate;
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /*
sahilmgandhi 18:6a4db94011d3 96 * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,
sahilmgandhi 18:6a4db94011d3 97 * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or
sahilmgandhi 18:6a4db94011d3 98 * US_MR_MODE9.
sahilmgandhi 18:6a4db94011d3 99 */
sahilmgandhi 18:6a4db94011d3 100 uint32_t char_length;
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /*
sahilmgandhi 18:6a4db94011d3 103 * Parity type, which should be one of the following: US_MR_PAR_EVEN,
sahilmgandhi 18:6a4db94011d3 104 * US_MR_PAR_ODD, US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO
sahilmgandhi 18:6a4db94011d3 105 * or US_MR_PAR_MULTIDROP.
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107 uint32_t parity_type;
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 /*
sahilmgandhi 18:6a4db94011d3 110 * Number of stop bits between two characters: US_MR_NBSTOP_1_BIT,
sahilmgandhi 18:6a4db94011d3 111 * US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT.
sahilmgandhi 18:6a4db94011d3 112 * \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only.
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114 uint32_t stop_bits;
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 /*
sahilmgandhi 18:6a4db94011d3 117 * Run the channel in test mode, which should be one of following:
sahilmgandhi 18:6a4db94011d3 118 * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC,
sahilmgandhi 18:6a4db94011d3 119 * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK.
sahilmgandhi 18:6a4db94011d3 120 */
sahilmgandhi 18:6a4db94011d3 121 uint32_t channel_mode;
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /* Filter of IrDA mode, useless in other modes. */
sahilmgandhi 18:6a4db94011d3 124 uint32_t irda_filter;
sahilmgandhi 18:6a4db94011d3 125 } sam_usart_opt_t;
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 /* Input parameters when initializing ISO7816 mode. */
sahilmgandhi 18:6a4db94011d3 128 typedef struct {
sahilmgandhi 18:6a4db94011d3 129 /* Set the frequency of the ISO7816 clock. */
sahilmgandhi 18:6a4db94011d3 130 uint32_t iso7816_hz;
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /*
sahilmgandhi 18:6a4db94011d3 133 * The number of ISO7816 clock ticks in every bit period (1 to 2047,
sahilmgandhi 18:6a4db94011d3 134 * 0 = disable clock). Baudrate rate = iso7816_hz / fidi_ratio.
sahilmgandhi 18:6a4db94011d3 135 */
sahilmgandhi 18:6a4db94011d3 136 uint32_t fidi_ratio;
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 /*
sahilmgandhi 18:6a4db94011d3 139 * How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or
sahilmgandhi 18:6a4db94011d3 140 * US_MR_PAR_ODD for inverse mode.
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142 uint32_t parity_type;
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /*
sahilmgandhi 18:6a4db94011d3 145 * Inhibit Non Acknowledge:
sahilmgandhi 18:6a4db94011d3 146 * - 0: the NACK is generated;
sahilmgandhi 18:6a4db94011d3 147 * - 1: the NACK is not generated.
sahilmgandhi 18:6a4db94011d3 148 *
sahilmgandhi 18:6a4db94011d3 149 * \note This bit will be used only in ISO7816 mode, protocol T = 0
sahilmgandhi 18:6a4db94011d3 150 * receiver.
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152 uint32_t inhibit_nack;
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /*
sahilmgandhi 18:6a4db94011d3 155 * Disable successive NACKs.
sahilmgandhi 18:6a4db94011d3 156 * - 0: NACK is sent on the ISO line as soon as a parity error occurs
sahilmgandhi 18:6a4db94011d3 157 * in the received character. Successive parity errors are counted up to
sahilmgandhi 18:6a4db94011d3 158 * the value in the max_iterations field. These parity errors generate
sahilmgandhi 18:6a4db94011d3 159 * a NACK on the ISO line. As soon as this value is reached, no additional
sahilmgandhi 18:6a4db94011d3 160 * NACK is sent on the ISO line. The ITERATION flag is asserted.
sahilmgandhi 18:6a4db94011d3 161 */
sahilmgandhi 18:6a4db94011d3 162 uint32_t dis_suc_nack;
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 /* Max number of repetitions (0 to 7). */
sahilmgandhi 18:6a4db94011d3 165 uint32_t max_iterations;
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /*
sahilmgandhi 18:6a4db94011d3 168 * Bit order in transmitted characters:
sahilmgandhi 18:6a4db94011d3 169 * - 0: LSB first;
sahilmgandhi 18:6a4db94011d3 170 * - 1: MSB first.
sahilmgandhi 18:6a4db94011d3 171 */
sahilmgandhi 18:6a4db94011d3 172 uint32_t bit_order;
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /*
sahilmgandhi 18:6a4db94011d3 175 * Which protocol is used:
sahilmgandhi 18:6a4db94011d3 176 * - 0: T = 0;
sahilmgandhi 18:6a4db94011d3 177 * - 1: T = 1.
sahilmgandhi 18:6a4db94011d3 178 */
sahilmgandhi 18:6a4db94011d3 179 uint32_t protocol_type;
sahilmgandhi 18:6a4db94011d3 180 } usart_iso7816_opt_t;
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 /* Input parameters when initializing SPI mode. */
sahilmgandhi 18:6a4db94011d3 183 typedef struct {
sahilmgandhi 18:6a4db94011d3 184 /* Set the frequency of the SPI clock (unused in slave mode). */
sahilmgandhi 18:6a4db94011d3 185 uint32_t baudrate;
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /*
sahilmgandhi 18:6a4db94011d3 188 * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT,
sahilmgandhi 18:6a4db94011d3 189 * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or
sahilmgandhi 18:6a4db94011d3 190 * US_MR_MODE9.
sahilmgandhi 18:6a4db94011d3 191 */
sahilmgandhi 18:6a4db94011d3 192 uint32_t char_length;
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /*
sahilmgandhi 18:6a4db94011d3 195 * Which SPI mode to use, which should be one of the following:
sahilmgandhi 18:6a4db94011d3 196 * SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3.
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198 uint32_t spi_mode;
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /*
sahilmgandhi 18:6a4db94011d3 201 * Run the channel in test mode, which should be one of following:
sahilmgandhi 18:6a4db94011d3 202 * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC,
sahilmgandhi 18:6a4db94011d3 203 * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK.
sahilmgandhi 18:6a4db94011d3 204 */
sahilmgandhi 18:6a4db94011d3 205 uint32_t channel_mode;
sahilmgandhi 18:6a4db94011d3 206 } usart_spi_opt_t;
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 void usart_reset(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 209 uint32_t usart_set_async_baudrate(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 210 uint32_t baudrate, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 211 uint32_t usart_init_rs232(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 212 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 213 uint32_t usart_init_hw_handshaking(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 214 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 215 #if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
sahilmgandhi 18:6a4db94011d3 216 uint32_t usart_init_modem(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 217 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 218 #endif
sahilmgandhi 18:6a4db94011d3 219 uint32_t usart_init_sync_master(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 220 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 221 uint32_t usart_init_sync_slave(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 222 const sam_usart_opt_t *p_usart_opt);
sahilmgandhi 18:6a4db94011d3 223 uint32_t usart_init_rs485(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 224 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 225 #if (!SAMG55 && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
sahilmgandhi 18:6a4db94011d3 226 uint32_t usart_init_irda(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 227 const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 228 #endif
sahilmgandhi 18:6a4db94011d3 229 #if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
sahilmgandhi 18:6a4db94011d3 230 uint32_t usart_init_iso7816(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 231 const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 232 void usart_reset_iterations(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 233 void usart_reset_nack(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 234 uint32_t usart_is_rx_buf_end(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 235 uint32_t usart_is_tx_buf_end(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 236 uint32_t usart_is_rx_buf_full(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 237 uint32_t usart_is_tx_buf_empty(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 238 uint8_t usart_get_error_number(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 239 #endif
sahilmgandhi 18:6a4db94011d3 240 uint32_t usart_init_spi_master(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 241 const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 242 uint32_t usart_init_spi_slave(Usart *p_usart,
sahilmgandhi 18:6a4db94011d3 243 const usart_spi_opt_t *p_usart_opt);
sahilmgandhi 18:6a4db94011d3 244 #if (SAM3XA || SAM4L || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 245 uint32_t usart_init_lin_master(Usart *p_usart, uint32_t ul_baudrate,
sahilmgandhi 18:6a4db94011d3 246 uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 247 uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate,
sahilmgandhi 18:6a4db94011d3 248 uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 249 void usart_lin_abort_tx(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 250 void usart_lin_send_wakeup_signal(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 251 void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action);
sahilmgandhi 18:6a4db94011d3 252 void usart_lin_disable_parity(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 253 void usart_lin_enable_parity(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 254 void usart_lin_disable_checksum(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 255 void usart_lin_enable_checksum(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 256 void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type);
sahilmgandhi 18:6a4db94011d3 257 void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode);
sahilmgandhi 18:6a4db94011d3 258 void usart_lin_disable_frame_slot(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 259 void usart_lin_enable_frame_slot(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 260 void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type);
sahilmgandhi 18:6a4db94011d3 261 void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len);
sahilmgandhi 18:6a4db94011d3 262 void usart_lin_disable_pdc_mode(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 263 void usart_lin_enable_pdc_mode(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 264 void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id);
sahilmgandhi 18:6a4db94011d3 265 uint8_t usart_lin_read_identifier(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 266 uint8_t usart_lin_get_data_length(Usart *usart);
sahilmgandhi 18:6a4db94011d3 267 #endif
sahilmgandhi 18:6a4db94011d3 268 #if (SAMV71 || SAMV70 || SAME70 || SAMS70)
sahilmgandhi 18:6a4db94011d3 269 uint8_t usart_lin_identifier_send_complete(Usart *usart);
sahilmgandhi 18:6a4db94011d3 270 uint8_t usart_lin_identifier_reception_complete(Usart *usart);
sahilmgandhi 18:6a4db94011d3 271 uint8_t usart_lin_tx_complete(Usart *usart);
sahilmgandhi 18:6a4db94011d3 272 uint32_t usart_init_lon(Usart *p_usart, uint32_t ul_baudrate, uint32_t ul_mck);
sahilmgandhi 18:6a4db94011d3 273 void usart_lon_set_comm_type(Usart *p_usart, uint8_t uc_type);
sahilmgandhi 18:6a4db94011d3 274 void usart_lon_disable_coll_detection(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 275 void usart_lon_enable_coll_detection(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 276 void usart_lon_set_tcol(Usart *p_usart, uint8_t uc_type);
sahilmgandhi 18:6a4db94011d3 277 void usart_lon_set_cdtail(Usart *p_usart, uint8_t uc_type);
sahilmgandhi 18:6a4db94011d3 278 void usart_lon_set_dmam(Usart *p_usart, uint8_t uc_type);
sahilmgandhi 18:6a4db94011d3 279 void usart_lon_set_beta1_tx_len(Usart *p_usart, uint32_t ul_len);
sahilmgandhi 18:6a4db94011d3 280 void usart_lon_set_beta1_rx_len(Usart *p_usart, uint32_t ul_len);
sahilmgandhi 18:6a4db94011d3 281 void usart_lon_set_priority(Usart *p_usart, uint8_t uc_psnb, uint8_t uc_nps);
sahilmgandhi 18:6a4db94011d3 282 void usart_lon_set_tx_idt(Usart *p_usart, uint32_t ul_time);
sahilmgandhi 18:6a4db94011d3 283 void usart_lon_set_rx_idt(Usart *p_usart, uint32_t ul_time);
sahilmgandhi 18:6a4db94011d3 284 void usart_lon_set_pre_len(Usart *p_usart, uint32_t ul_len);
sahilmgandhi 18:6a4db94011d3 285 void usart_lon_set_data_len(Usart *p_usart, uint8_t uc_len);
sahilmgandhi 18:6a4db94011d3 286 void usart_lon_set_l2hdr(Usart *p_usart, uint8_t uc_bli, uint8_t uc_altp, uint8_t uc_pb);
sahilmgandhi 18:6a4db94011d3 287 uint32_t usart_lon_is_tx_end(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 288 uint32_t usart_lon_is_rx_end(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 289 #endif
sahilmgandhi 18:6a4db94011d3 290 void usart_enable_tx(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 291 void usart_disable_tx(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 292 void usart_reset_tx(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 293 void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard);
sahilmgandhi 18:6a4db94011d3 294 void usart_enable_rx(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 295 void usart_disable_rx(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 296 void usart_reset_rx(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 297 void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout);
sahilmgandhi 18:6a4db94011d3 298 void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources);
sahilmgandhi 18:6a4db94011d3 299 void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources);
sahilmgandhi 18:6a4db94011d3 300 uint32_t usart_get_interrupt_mask(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 301 uint32_t usart_get_status(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 302 void usart_reset_status(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 303 void usart_start_tx_break(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 304 void usart_stop_tx_break(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 305 void usart_start_rx_timeout(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 306 uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr);
sahilmgandhi 18:6a4db94011d3 307 void usart_restart_rx_timeout(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 308 #if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E)
sahilmgandhi 18:6a4db94011d3 309 void usart_drive_DTR_pin_low(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 310 void usart_drive_DTR_pin_high(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 311 #endif
sahilmgandhi 18:6a4db94011d3 312 void usart_drive_RTS_pin_low(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 313 void usart_drive_RTS_pin_high(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 314 void usart_spi_force_chip_select(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 315 void usart_spi_release_chip_select(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 316 uint32_t usart_is_tx_ready(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 317 uint32_t usart_is_tx_empty(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 318 uint32_t usart_is_rx_ready(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 319 uint32_t usart_write(Usart *p_usart, uint32_t c);
sahilmgandhi 18:6a4db94011d3 320 uint32_t usart_putchar(Usart *p_usart, uint32_t c);
sahilmgandhi 18:6a4db94011d3 321 void usart_write_line(Usart *p_usart, const char *string);
sahilmgandhi 18:6a4db94011d3 322 uint32_t usart_read(Usart *p_usart, uint32_t *c);
sahilmgandhi 18:6a4db94011d3 323 uint32_t usart_getchar(Usart *p_usart, uint32_t *c);
sahilmgandhi 18:6a4db94011d3 324 #if (SAM3XA || SAM3U)
sahilmgandhi 18:6a4db94011d3 325 uint32_t *usart_get_tx_access(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 326 uint32_t *usart_get_rx_access(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 327 #endif
sahilmgandhi 18:6a4db94011d3 328 #if (!SAM4L && !SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
sahilmgandhi 18:6a4db94011d3 329 Pdc *usart_get_pdc_base(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 330 #endif
sahilmgandhi 18:6a4db94011d3 331 void usart_enable_writeprotect(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 332 void usart_disable_writeprotect(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 333 uint32_t usart_get_writeprotect_status(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 334 #if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E || SAM4C || SAM4CP || SAM4CM || SAMV70 || SAMV71 || SAMS70 || SAME70)
sahilmgandhi 18:6a4db94011d3 335 void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len);
sahilmgandhi 18:6a4db94011d3 336 void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);
sahilmgandhi 18:6a4db94011d3 337 void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity);
sahilmgandhi 18:6a4db94011d3 338 void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len);
sahilmgandhi 18:6a4db94011d3 339 void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern);
sahilmgandhi 18:6a4db94011d3 340 void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity);
sahilmgandhi 18:6a4db94011d3 341 void usart_man_enable_drift_compensation(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 342 void usart_man_disable_drift_compensation(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 343 #endif
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 #if SAM4L
sahilmgandhi 18:6a4db94011d3 346 uint32_t usart_get_version(Usart *p_usart);
sahilmgandhi 18:6a4db94011d3 347 #endif
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 #if SAMG55
sahilmgandhi 18:6a4db94011d3 350 void usart_set_sleepwalking(Usart *p_uart, uint8_t ul_low_value,
sahilmgandhi 18:6a4db94011d3 351 bool cmpmode, bool cmppar, uint8_t ul_high_value);
sahilmgandhi 18:6a4db94011d3 352 #endif
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 /// @cond 0
sahilmgandhi 18:6a4db94011d3 355 /**INDENT-OFF**/
sahilmgandhi 18:6a4db94011d3 356 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358 #endif
sahilmgandhi 18:6a4db94011d3 359 /**INDENT-ON**/
sahilmgandhi 18:6a4db94011d3 360 /// @endcond
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 //! @}
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 /**
sahilmgandhi 18:6a4db94011d3 365 * \page sam_usart_quickstart Quick start guide for the SAM USART module
sahilmgandhi 18:6a4db94011d3 366 *
sahilmgandhi 18:6a4db94011d3 367 * This is the quick start guide for the \ref group_sam_drivers_usart
sahilmgandhi 18:6a4db94011d3 368 * "USART module", with step-by-step instructions on how to configure and
sahilmgandhi 18:6a4db94011d3 369 * use the driver in a selection of use cases.
sahilmgandhi 18:6a4db94011d3 370 *
sahilmgandhi 18:6a4db94011d3 371 * The use cases contain several code fragments. The code fragments in the
sahilmgandhi 18:6a4db94011d3 372 * steps for setup can be copied into a custom initialization function, while
sahilmgandhi 18:6a4db94011d3 373 * the steps for usage can be copied into, e.g., the main application function.
sahilmgandhi 18:6a4db94011d3 374 *
sahilmgandhi 18:6a4db94011d3 375 * \note Some SAM devices contain both USART and UART modules, with the latter
sahilmgandhi 18:6a4db94011d3 376 * being a subset in functionality of the former but physically separate
sahilmgandhi 18:6a4db94011d3 377 * peripherals. UART modules are compatible with the USART driver, but
sahilmgandhi 18:6a4db94011d3 378 * only for the functions and modes supported by the base UART driver.
sahilmgandhi 18:6a4db94011d3 379 *
sahilmgandhi 18:6a4db94011d3 380 * \section usart_use_cases USART use cases
sahilmgandhi 18:6a4db94011d3 381 * - \ref usart_basic_use_case
sahilmgandhi 18:6a4db94011d3 382 * - \subpage usart_use_case_1
sahilmgandhi 18:6a4db94011d3 383 * - \subpage usart_use_case_2
sahilmgandhi 18:6a4db94011d3 384 *
sahilmgandhi 18:6a4db94011d3 385 * \note The USART pins configuration are not included here. Please refer
sahilmgandhi 18:6a4db94011d3 386 * the related code in board_init() function.
sahilmgandhi 18:6a4db94011d3 387 *
sahilmgandhi 18:6a4db94011d3 388 * \section usart_basic_use_case Basic use case - transmit a character
sahilmgandhi 18:6a4db94011d3 389 * In this use case, the USART module is configured for:
sahilmgandhi 18:6a4db94011d3 390 * - Using USART0
sahilmgandhi 18:6a4db94011d3 391 * - Baudrate: 9600
sahilmgandhi 18:6a4db94011d3 392 * - Character length: 8 bit
sahilmgandhi 18:6a4db94011d3 393 * - Parity mode: Disabled
sahilmgandhi 18:6a4db94011d3 394 * - Stop bit: None
sahilmgandhi 18:6a4db94011d3 395 * - RS232 mode
sahilmgandhi 18:6a4db94011d3 396 *
sahilmgandhi 18:6a4db94011d3 397 * \section usart_basic_use_case_setup Setup steps
sahilmgandhi 18:6a4db94011d3 398 *
sahilmgandhi 18:6a4db94011d3 399 * \subsection usart_basic_use_case_setup_prereq Prerequisites
sahilmgandhi 18:6a4db94011d3 400 * -# \ref sysclk_group "System Clock Management (sysclock)"
sahilmgandhi 18:6a4db94011d3 401 * -# \ref ioport_group "Common IOPORT API (ioport)"
sahilmgandhi 18:6a4db94011d3 402 *
sahilmgandhi 18:6a4db94011d3 403 * \subsection usart_basic_use_case_setup_code Example code
sahilmgandhi 18:6a4db94011d3 404 * The following configuration must be added to the project (typically to a
sahilmgandhi 18:6a4db94011d3 405 * conf_usart.h file, but it can also be added to your main application file.)
sahilmgandhi 18:6a4db94011d3 406 * \code
sahilmgandhi 18:6a4db94011d3 407 #define USART_SERIAL USART0
sahilmgandhi 18:6a4db94011d3 408 #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l
sahilmgandhi 18:6a4db94011d3 409 #define USART_SERIAL_BAUDRATE 9600
sahilmgandhi 18:6a4db94011d3 410 #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT
sahilmgandhi 18:6a4db94011d3 411 #define USART_SERIAL_PARITY US_MR_PAR_NO
sahilmgandhi 18:6a4db94011d3 412 #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT
sahilmgandhi 18:6a4db94011d3 413 \endcode
sahilmgandhi 18:6a4db94011d3 414 *
sahilmgandhi 18:6a4db94011d3 415 * Add to application initialization:
sahilmgandhi 18:6a4db94011d3 416 * \code
sahilmgandhi 18:6a4db94011d3 417 sysclk_init();
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 board_init();
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 const sam_usart_opt_t usart_console_settings = {
sahilmgandhi 18:6a4db94011d3 422 USART_SERIAL_BAUDRATE,
sahilmgandhi 18:6a4db94011d3 423 USART_SERIAL_CHAR_LENGTH,
sahilmgandhi 18:6a4db94011d3 424 USART_SERIAL_PARITY,
sahilmgandhi 18:6a4db94011d3 425 USART_SERIAL_STOP_BIT,
sahilmgandhi 18:6a4db94011d3 426 US_MR_CHMODE_NORMAL
sahilmgandhi 18:6a4db94011d3 427 };
sahilmgandhi 18:6a4db94011d3 428 #if SAM4L
sahilmgandhi 18:6a4db94011d3 429 sysclk_enable_peripheral_clock(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 430 #else
sahilmgandhi 18:6a4db94011d3 431 sysclk_enable_peripheral_clock(USART_SERIAL_ID);
sahilmgandhi 18:6a4db94011d3 432 #endif
sahilmgandhi 18:6a4db94011d3 433 usart_init_rs232(USART_SERIAL, &usart_console_settings,
sahilmgandhi 18:6a4db94011d3 434 sysclk_get_main_hz());
sahilmgandhi 18:6a4db94011d3 435 usart_enable_tx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 436 usart_enable_rx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 437 \endcode
sahilmgandhi 18:6a4db94011d3 438 *
sahilmgandhi 18:6a4db94011d3 439 * \subsection usart_basic_use_case_setup_flow Workflow
sahilmgandhi 18:6a4db94011d3 440 * -# Initialize system clock:
sahilmgandhi 18:6a4db94011d3 441 * \code
sahilmgandhi 18:6a4db94011d3 442 sysclk_init();
sahilmgandhi 18:6a4db94011d3 443 \endcode
sahilmgandhi 18:6a4db94011d3 444 * -# Configure the USART Tx and Rx pins by call the board init function:
sahilmgandhi 18:6a4db94011d3 445 * \code
sahilmgandhi 18:6a4db94011d3 446 board_init();
sahilmgandhi 18:6a4db94011d3 447 \endcode
sahilmgandhi 18:6a4db94011d3 448 * \note Set the following define in conf_board.h file to enable COM port,it will be used in
sahilmgandhi 18:6a4db94011d3 449 * board_init() function to set up IOPorts for the USART pins.
sahilmgandhi 18:6a4db94011d3 450 * For SAM4L:
sahilmgandhi 18:6a4db94011d3 451 * \code
sahilmgandhi 18:6a4db94011d3 452 #define CONF_BOARD_COM_PORT
sahilmgandhi 18:6a4db94011d3 453 \endcode
sahilmgandhi 18:6a4db94011d3 454 * For other SAM devices:
sahilmgandhi 18:6a4db94011d3 455 * \code
sahilmgandhi 18:6a4db94011d3 456 #define CONF_BOARD_UART_CONSOLE
sahilmgandhi 18:6a4db94011d3 457 \endcode
sahilmgandhi 18:6a4db94011d3 458 * -# Create USART options struct:
sahilmgandhi 18:6a4db94011d3 459 * \code
sahilmgandhi 18:6a4db94011d3 460 const sam_usart_opt_t usart_console_settings = {
sahilmgandhi 18:6a4db94011d3 461 USART_SERIAL_BAUDRATE,
sahilmgandhi 18:6a4db94011d3 462 USART_SERIAL_CHAR_LENGTH,
sahilmgandhi 18:6a4db94011d3 463 USART_SERIAL_PARITY,
sahilmgandhi 18:6a4db94011d3 464 USART_SERIAL_STOP_BIT,
sahilmgandhi 18:6a4db94011d3 465 US_MR_CHMODE_NORMAL
sahilmgandhi 18:6a4db94011d3 466 };
sahilmgandhi 18:6a4db94011d3 467 \endcode
sahilmgandhi 18:6a4db94011d3 468 * -# Enable the clock to the USART module:
sahilmgandhi 18:6a4db94011d3 469 * \code
sahilmgandhi 18:6a4db94011d3 470 #if SAM4L
sahilmgandhi 18:6a4db94011d3 471 sysclk_enable_peripheral_clock(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 472 #else
sahilmgandhi 18:6a4db94011d3 473 sysclk_enable_peripheral_clock(USART_SERIAL_ID);
sahilmgandhi 18:6a4db94011d3 474 #endif
sahilmgandhi 18:6a4db94011d3 475 \endcode
sahilmgandhi 18:6a4db94011d3 476 * -# Initialize the USART module in RS232 mode:
sahilmgandhi 18:6a4db94011d3 477 * \code
sahilmgandhi 18:6a4db94011d3 478 usart_init_rs232(USART_SERIAL, &usart_console_settings,
sahilmgandhi 18:6a4db94011d3 479 sysclk_get_main_hz());
sahilmgandhi 18:6a4db94011d3 480 \endcode
sahilmgandhi 18:6a4db94011d3 481 * -# Enable the Rx and Tx modes of the USART module:
sahilmgandhi 18:6a4db94011d3 482 * \code
sahilmgandhi 18:6a4db94011d3 483 usart_enable_tx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 484 usart_enable_rx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 485 \endcode
sahilmgandhi 18:6a4db94011d3 486 *
sahilmgandhi 18:6a4db94011d3 487 * \section usart_basic_use_case_usage Usage steps
sahilmgandhi 18:6a4db94011d3 488 *
sahilmgandhi 18:6a4db94011d3 489 * \subsection usart_basic_use_case_usage_code Example code
sahilmgandhi 18:6a4db94011d3 490 * Add to application C-file:
sahilmgandhi 18:6a4db94011d3 491 * \code
sahilmgandhi 18:6a4db94011d3 492 usart_putchar(USART_SERIAL, 'a');
sahilmgandhi 18:6a4db94011d3 493 \endcode
sahilmgandhi 18:6a4db94011d3 494 *
sahilmgandhi 18:6a4db94011d3 495 * \subsection usart_basic_use_case_usage_flow Workflow
sahilmgandhi 18:6a4db94011d3 496 * -# Send an 'a' character via USART
sahilmgandhi 18:6a4db94011d3 497 * \code usart_putchar(USART_SERIAL, 'a'); \endcode
sahilmgandhi 18:6a4db94011d3 498 */
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 /**
sahilmgandhi 18:6a4db94011d3 501 * \page usart_use_case_1 USART receive character and echo back
sahilmgandhi 18:6a4db94011d3 502 *
sahilmgandhi 18:6a4db94011d3 503 * In this use case, the USART module is configured for:
sahilmgandhi 18:6a4db94011d3 504 * - Using USART0
sahilmgandhi 18:6a4db94011d3 505 * - Baudrate: 9600
sahilmgandhi 18:6a4db94011d3 506 * - Character length: 8 bit
sahilmgandhi 18:6a4db94011d3 507 * - Parity mode: Disabled
sahilmgandhi 18:6a4db94011d3 508 * - Stop bit: None
sahilmgandhi 18:6a4db94011d3 509 * - RS232 mode
sahilmgandhi 18:6a4db94011d3 510 *
sahilmgandhi 18:6a4db94011d3 511 * The use case waits for a received character on the configured USART and
sahilmgandhi 18:6a4db94011d3 512 * echoes the character back to the same USART.
sahilmgandhi 18:6a4db94011d3 513 *
sahilmgandhi 18:6a4db94011d3 514 * \section usart_use_case_1_setup Setup steps
sahilmgandhi 18:6a4db94011d3 515 *
sahilmgandhi 18:6a4db94011d3 516 * \subsection usart_use_case_1_setup_prereq Prerequisites
sahilmgandhi 18:6a4db94011d3 517 * -# \ref sysclk_group "System Clock Management (sysclock)"
sahilmgandhi 18:6a4db94011d3 518 * -# \ref ioport_group "Common IOPORT API (ioport)"
sahilmgandhi 18:6a4db94011d3 519 *
sahilmgandhi 18:6a4db94011d3 520 * \subsection usart_use_case_1_setup_code Example code
sahilmgandhi 18:6a4db94011d3 521 * The following configuration must be added to the project (typically to a
sahilmgandhi 18:6a4db94011d3 522 * conf_usart.h file, but it can also be added to your main application file.):
sahilmgandhi 18:6a4db94011d3 523 * \code
sahilmgandhi 18:6a4db94011d3 524 #define USART_SERIAL USART0
sahilmgandhi 18:6a4db94011d3 525 #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l
sahilmgandhi 18:6a4db94011d3 526 #define USART_SERIAL_BAUDRATE 9600
sahilmgandhi 18:6a4db94011d3 527 #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT
sahilmgandhi 18:6a4db94011d3 528 #define USART_SERIAL_PARITY US_MR_PAR_NO
sahilmgandhi 18:6a4db94011d3 529 #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT
sahilmgandhi 18:6a4db94011d3 530 \endcode
sahilmgandhi 18:6a4db94011d3 531 *
sahilmgandhi 18:6a4db94011d3 532 * A variable for the received byte must be added:
sahilmgandhi 18:6a4db94011d3 533 * \code
sahilmgandhi 18:6a4db94011d3 534 uint32_t received_byte;
sahilmgandhi 18:6a4db94011d3 535 \endcode
sahilmgandhi 18:6a4db94011d3 536 *
sahilmgandhi 18:6a4db94011d3 537 * Add to application initialization:
sahilmgandhi 18:6a4db94011d3 538 * \code
sahilmgandhi 18:6a4db94011d3 539 sysclk_init();
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 board_init();
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 const sam_usart_opt_t usart_console_settings = {
sahilmgandhi 18:6a4db94011d3 544 USART_SERIAL_BAUDRATE,
sahilmgandhi 18:6a4db94011d3 545 USART_SERIAL_CHAR_LENGTH,
sahilmgandhi 18:6a4db94011d3 546 USART_SERIAL_PARITY,
sahilmgandhi 18:6a4db94011d3 547 USART_SERIAL_STOP_BIT,
sahilmgandhi 18:6a4db94011d3 548 US_MR_CHMODE_NORMAL
sahilmgandhi 18:6a4db94011d3 549 };
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 #if SAM4L
sahilmgandhi 18:6a4db94011d3 552 sysclk_enable_peripheral_clock(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 553 #else
sahilmgandhi 18:6a4db94011d3 554 sysclk_enable_peripheral_clock(USART_SERIAL_ID);
sahilmgandhi 18:6a4db94011d3 555 #endif
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557 usart_init_rs232(USART_SERIAL, &usart_console_settings,
sahilmgandhi 18:6a4db94011d3 558 sysclk_get_main_hz());
sahilmgandhi 18:6a4db94011d3 559 usart_enable_tx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 560 usart_enable_rx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 561 \endcode
sahilmgandhi 18:6a4db94011d3 562 *
sahilmgandhi 18:6a4db94011d3 563 * \subsection usart_use_case_1_setup_flow Workflow
sahilmgandhi 18:6a4db94011d3 564 * -# Initialize system clock:
sahilmgandhi 18:6a4db94011d3 565 * \code
sahilmgandhi 18:6a4db94011d3 566 sysclk_init();
sahilmgandhi 18:6a4db94011d3 567 \endcode
sahilmgandhi 18:6a4db94011d3 568 * -# Configure the USART Tx and Rx pins by call the board init function:
sahilmgandhi 18:6a4db94011d3 569 * \code
sahilmgandhi 18:6a4db94011d3 570 board_init();
sahilmgandhi 18:6a4db94011d3 571 \endcode
sahilmgandhi 18:6a4db94011d3 572 * \note Set the following define in conf_board.h file to enable COM port,it will be used in
sahilmgandhi 18:6a4db94011d3 573 * board_init() function to set up IOPorts for the USART pins.
sahilmgandhi 18:6a4db94011d3 574 * For SAM4L:
sahilmgandhi 18:6a4db94011d3 575 * \code
sahilmgandhi 18:6a4db94011d3 576 #define CONF_BOARD_COM_PORT
sahilmgandhi 18:6a4db94011d3 577 \endcode
sahilmgandhi 18:6a4db94011d3 578 * For other SAM devices:
sahilmgandhi 18:6a4db94011d3 579 * \code
sahilmgandhi 18:6a4db94011d3 580 #define CONF_BOARD_UART_CONSOLE
sahilmgandhi 18:6a4db94011d3 581 \endcode
sahilmgandhi 18:6a4db94011d3 582 * -# Create USART options struct:
sahilmgandhi 18:6a4db94011d3 583 * \code
sahilmgandhi 18:6a4db94011d3 584 const sam_usart_opt_t usart_console_settings = {
sahilmgandhi 18:6a4db94011d3 585 USART_SERIAL_BAUDRATE,
sahilmgandhi 18:6a4db94011d3 586 USART_SERIAL_CHAR_LENGTH,
sahilmgandhi 18:6a4db94011d3 587 USART_SERIAL_PARITY,
sahilmgandhi 18:6a4db94011d3 588 USART_SERIAL_STOP_BIT,
sahilmgandhi 18:6a4db94011d3 589 US_MR_CHMODE_NORMAL
sahilmgandhi 18:6a4db94011d3 590 };
sahilmgandhi 18:6a4db94011d3 591 \endcode
sahilmgandhi 18:6a4db94011d3 592 * -# Enable the clock to the USART module:
sahilmgandhi 18:6a4db94011d3 593 * \code
sahilmgandhi 18:6a4db94011d3 594 #if SAM4L
sahilmgandhi 18:6a4db94011d3 595 sysclk_enable_peripheral_clock(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 596 #else
sahilmgandhi 18:6a4db94011d3 597 sysclk_enable_peripheral_clock(USART_SERIAL_ID);
sahilmgandhi 18:6a4db94011d3 598 #endif
sahilmgandhi 18:6a4db94011d3 599 \endcode
sahilmgandhi 18:6a4db94011d3 600 * -# Initialize the USART module in RS232 mode:
sahilmgandhi 18:6a4db94011d3 601 * \code
sahilmgandhi 18:6a4db94011d3 602 usart_init_rs232(USART_SERIAL, &usart_console_settings,
sahilmgandhi 18:6a4db94011d3 603 sysclk_get_main_hz());
sahilmgandhi 18:6a4db94011d3 604 \endcode
sahilmgandhi 18:6a4db94011d3 605 * -# Enable the Rx and Tx modes of the USART module:
sahilmgandhi 18:6a4db94011d3 606 * \code
sahilmgandhi 18:6a4db94011d3 607 usart_enable_tx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 608 usart_enable_rx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 609 \endcode
sahilmgandhi 18:6a4db94011d3 610 *
sahilmgandhi 18:6a4db94011d3 611 * \section usart_use_case_1_usage Usage steps
sahilmgandhi 18:6a4db94011d3 612 *
sahilmgandhi 18:6a4db94011d3 613 * \subsection usart_use_case_1_usage_code Example code
sahilmgandhi 18:6a4db94011d3 614 * Add to, e.g., main loop in application C-file:
sahilmgandhi 18:6a4db94011d3 615 * \code
sahilmgandhi 18:6a4db94011d3 616 received_byte = usart_getchar(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 617 usart_putchar(USART_SERIAL, received_byte);
sahilmgandhi 18:6a4db94011d3 618 \endcode
sahilmgandhi 18:6a4db94011d3 619 *
sahilmgandhi 18:6a4db94011d3 620 * \subsection usart_use_case_1_usage_flow Workflow
sahilmgandhi 18:6a4db94011d3 621 * -# Wait for reception of a character:
sahilmgandhi 18:6a4db94011d3 622 * \code usart_getchar(USART_SERIAL, &received_byte); \endcode
sahilmgandhi 18:6a4db94011d3 623 * -# Echo the character back:
sahilmgandhi 18:6a4db94011d3 624 * \code usart_putchar(USART_SERIAL, received_byte); \endcode
sahilmgandhi 18:6a4db94011d3 625 */
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 /**
sahilmgandhi 18:6a4db94011d3 628 * \page usart_use_case_2 USART receive character and echo back via interrupts
sahilmgandhi 18:6a4db94011d3 629 *
sahilmgandhi 18:6a4db94011d3 630 * In this use case, the USART module is configured for:
sahilmgandhi 18:6a4db94011d3 631 * - Using USART0
sahilmgandhi 18:6a4db94011d3 632 * - Baudrate: 9600
sahilmgandhi 18:6a4db94011d3 633 * - Character length: 8 bit
sahilmgandhi 18:6a4db94011d3 634 * - Parity mode: Disabled
sahilmgandhi 18:6a4db94011d3 635 * - Stop bit: None
sahilmgandhi 18:6a4db94011d3 636 * - RS232 mode
sahilmgandhi 18:6a4db94011d3 637 *
sahilmgandhi 18:6a4db94011d3 638 * The use case waits for a received character on the configured USART and
sahilmgandhi 18:6a4db94011d3 639 * echoes the character back to the same USART. The character reception is
sahilmgandhi 18:6a4db94011d3 640 * performed via an interrupt handler, rather than the polling method used
sahilmgandhi 18:6a4db94011d3 641 * in \ref usart_use_case_1.
sahilmgandhi 18:6a4db94011d3 642 *
sahilmgandhi 18:6a4db94011d3 643 * \section usart_use_case_2_setup Setup steps
sahilmgandhi 18:6a4db94011d3 644 *
sahilmgandhi 18:6a4db94011d3 645 * \subsection usart_use_case_2_setup_prereq Prerequisites
sahilmgandhi 18:6a4db94011d3 646 * -# \ref sysclk_group "System Clock Management (sysclock)"
sahilmgandhi 18:6a4db94011d3 647 * -# \ref pio_group "Parallel Input/Output Controller (pio)"
sahilmgandhi 18:6a4db94011d3 648 * -# \ref pmc_group "Power Management Controller (pmc)"
sahilmgandhi 18:6a4db94011d3 649 *
sahilmgandhi 18:6a4db94011d3 650 * \subsection usart_use_case_2_setup_code Example code
sahilmgandhi 18:6a4db94011d3 651 * The following configuration must be added to the project (typically to a
sahilmgandhi 18:6a4db94011d3 652 * conf_usart.h file, but it can also be added to your main application file.):
sahilmgandhi 18:6a4db94011d3 653 * \code
sahilmgandhi 18:6a4db94011d3 654 #define USART_SERIAL USART0
sahilmgandhi 18:6a4db94011d3 655 #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l
sahilmgandhi 18:6a4db94011d3 656 #define USART_SERIAL_ISR_HANDLER USART0_Handler
sahilmgandhi 18:6a4db94011d3 657 #define USART_SERIAL_BAUDRATE 9600
sahilmgandhi 18:6a4db94011d3 658 #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT
sahilmgandhi 18:6a4db94011d3 659 #define USART_SERIAL_PARITY US_MR_PAR_NO
sahilmgandhi 18:6a4db94011d3 660 #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT
sahilmgandhi 18:6a4db94011d3 661 \endcode
sahilmgandhi 18:6a4db94011d3 662 *
sahilmgandhi 18:6a4db94011d3 663 * A variable for the received byte must be added:
sahilmgandhi 18:6a4db94011d3 664 * \code
sahilmgandhi 18:6a4db94011d3 665 uint32_t received_byte;
sahilmgandhi 18:6a4db94011d3 666 \endcode
sahilmgandhi 18:6a4db94011d3 667 *
sahilmgandhi 18:6a4db94011d3 668 * Add to application initialization:
sahilmgandhi 18:6a4db94011d3 669 * \code
sahilmgandhi 18:6a4db94011d3 670 sysclk_init();
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672 board_init();
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 const sam_usart_opt_t usart_console_settings = {
sahilmgandhi 18:6a4db94011d3 675 USART_SERIAL_BAUDRATE,
sahilmgandhi 18:6a4db94011d3 676 USART_SERIAL_CHAR_LENGTH,
sahilmgandhi 18:6a4db94011d3 677 USART_SERIAL_PARITY,
sahilmgandhi 18:6a4db94011d3 678 USART_SERIAL_STOP_BIT,
sahilmgandhi 18:6a4db94011d3 679 US_MR_CHMODE_NORMAL
sahilmgandhi 18:6a4db94011d3 680 };
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 #if SAM4L
sahilmgandhi 18:6a4db94011d3 683 sysclk_enable_peripheral_clock(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 684 #else
sahilmgandhi 18:6a4db94011d3 685 sysclk_enable_peripheral_clock(USART_SERIAL_ID);
sahilmgandhi 18:6a4db94011d3 686 #endif
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 usart_init_rs232(USART_SERIAL, &usart_console_settings,
sahilmgandhi 18:6a4db94011d3 689 sysclk_get_main_hz());
sahilmgandhi 18:6a4db94011d3 690 usart_enable_tx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 691 usart_enable_rx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 692
sahilmgandhi 18:6a4db94011d3 693 usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);
sahilmgandhi 18:6a4db94011d3 694 NVIC_EnableIRQ(USART_SERIAL_IRQ);
sahilmgandhi 18:6a4db94011d3 695 \endcode
sahilmgandhi 18:6a4db94011d3 696 *
sahilmgandhi 18:6a4db94011d3 697 * \subsection usart_use_case_2_setup_flow Workflow
sahilmgandhi 18:6a4db94011d3 698 * -# Initialize system clock:
sahilmgandhi 18:6a4db94011d3 699 * \code
sahilmgandhi 18:6a4db94011d3 700 sysclk_init();
sahilmgandhi 18:6a4db94011d3 701 \endcode
sahilmgandhi 18:6a4db94011d3 702 * -# Configure the USART Tx and Rx pins by call the board init function:
sahilmgandhi 18:6a4db94011d3 703 * \code
sahilmgandhi 18:6a4db94011d3 704 board_init();
sahilmgandhi 18:6a4db94011d3 705 \endcode
sahilmgandhi 18:6a4db94011d3 706 * \note Set the following define in conf_board.h file to enable COM port,it will be used in
sahilmgandhi 18:6a4db94011d3 707 * board_init() function to set up IOPorts for the USART pins.
sahilmgandhi 18:6a4db94011d3 708 * For SAM4L:
sahilmgandhi 18:6a4db94011d3 709 * \code
sahilmgandhi 18:6a4db94011d3 710 #define CONF_BOARD_COM_PORT
sahilmgandhi 18:6a4db94011d3 711 \endcode
sahilmgandhi 18:6a4db94011d3 712 * For other SAM devices:
sahilmgandhi 18:6a4db94011d3 713 * \code
sahilmgandhi 18:6a4db94011d3 714 #define CONF_BOARD_UART_CONSOLE
sahilmgandhi 18:6a4db94011d3 715 \endcode
sahilmgandhi 18:6a4db94011d3 716 * -# Create USART options struct:
sahilmgandhi 18:6a4db94011d3 717 * \code
sahilmgandhi 18:6a4db94011d3 718 const sam_usart_opt_t usart_console_settings = {
sahilmgandhi 18:6a4db94011d3 719 USART_SERIAL_BAUDRATE,
sahilmgandhi 18:6a4db94011d3 720 USART_SERIAL_CHAR_LENGTH,
sahilmgandhi 18:6a4db94011d3 721 USART_SERIAL_PARITY,
sahilmgandhi 18:6a4db94011d3 722 USART_SERIAL_STOP_BIT,
sahilmgandhi 18:6a4db94011d3 723 US_MR_CHMODE_NORMAL
sahilmgandhi 18:6a4db94011d3 724 };
sahilmgandhi 18:6a4db94011d3 725 \endcode
sahilmgandhi 18:6a4db94011d3 726 * -# Enable the clock to the USART module:
sahilmgandhi 18:6a4db94011d3 727 * \code
sahilmgandhi 18:6a4db94011d3 728 #if SAM4L
sahilmgandhi 18:6a4db94011d3 729 sysclk_enable_peripheral_clock(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 730 #else
sahilmgandhi 18:6a4db94011d3 731 sysclk_enable_peripheral_clock(USART_SERIAL_ID);
sahilmgandhi 18:6a4db94011d3 732 #endif
sahilmgandhi 18:6a4db94011d3 733 \endcode
sahilmgandhi 18:6a4db94011d3 734 * -# Initialize the USART module in RS232 mode:
sahilmgandhi 18:6a4db94011d3 735 * \code
sahilmgandhi 18:6a4db94011d3 736 usart_init_rs232(USART_SERIAL, &usart_console_settings,
sahilmgandhi 18:6a4db94011d3 737 sysclk_get_main_hz());
sahilmgandhi 18:6a4db94011d3 738 \endcode
sahilmgandhi 18:6a4db94011d3 739 * -# Enable the Rx and Tx modes of the USART module:
sahilmgandhi 18:6a4db94011d3 740 * \code
sahilmgandhi 18:6a4db94011d3 741 usart_enable_tx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 742 usart_enable_rx(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 743 \endcode
sahilmgandhi 18:6a4db94011d3 744 * -# Enable the USART character reception interrupt, and general interrupts
sahilmgandhi 18:6a4db94011d3 745 * for the USART module.
sahilmgandhi 18:6a4db94011d3 746 * \code
sahilmgandhi 18:6a4db94011d3 747 usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY);
sahilmgandhi 18:6a4db94011d3 748 NVIC_EnableIRQ(USART_SERIAL_IRQ);
sahilmgandhi 18:6a4db94011d3 749 \endcode
sahilmgandhi 18:6a4db94011d3 750 * \section usart_use_case_2_usage Usage steps
sahilmgandhi 18:6a4db94011d3 751 *
sahilmgandhi 18:6a4db94011d3 752 * \subsection usart_use_case_2_usage_code Example code
sahilmgandhi 18:6a4db94011d3 753 * Add to your main application C-file the USART interrupt handler:
sahilmgandhi 18:6a4db94011d3 754 * \code
sahilmgandhi 18:6a4db94011d3 755 void USART_SERIAL_ISR_HANDLER(void)
sahilmgandhi 18:6a4db94011d3 756 {
sahilmgandhi 18:6a4db94011d3 757 uint32_t dw_status = usart_get_status(USART_SERIAL);
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 if (dw_status & US_CSR_RXRDY) {
sahilmgandhi 18:6a4db94011d3 760 uint32_t received_byte;
sahilmgandhi 18:6a4db94011d3 761
sahilmgandhi 18:6a4db94011d3 762 usart_read(USART_SERIAL, &received_byte);
sahilmgandhi 18:6a4db94011d3 763 usart_write(USART_SERIAL, received_byte);
sahilmgandhi 18:6a4db94011d3 764 }
sahilmgandhi 18:6a4db94011d3 765 }
sahilmgandhi 18:6a4db94011d3 766 \endcode
sahilmgandhi 18:6a4db94011d3 767 *
sahilmgandhi 18:6a4db94011d3 768 * \subsection usart_use_case_2_usage_flow Workflow
sahilmgandhi 18:6a4db94011d3 769 * -# When the USART ISR fires, retrieve the USART module interrupt flags:
sahilmgandhi 18:6a4db94011d3 770 * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode
sahilmgandhi 18:6a4db94011d3 771 * -# Check if the USART Receive Character interrupt has fired:
sahilmgandhi 18:6a4db94011d3 772 * \code if (dw_status & US_CSR_RXRDY) \endcode
sahilmgandhi 18:6a4db94011d3 773 * -# If a character has been received, fetch it into a temporary variable:
sahilmgandhi 18:6a4db94011d3 774 * \code usart_read(USART_SERIAL, &received_byte); \endcode
sahilmgandhi 18:6a4db94011d3 775 * -# Echo the character back:
sahilmgandhi 18:6a4db94011d3 776 * \code usart_write(USART_SERIAL, received_byte); \endcode
sahilmgandhi 18:6a4db94011d3 777 */
sahilmgandhi 18:6a4db94011d3 778
sahilmgandhi 18:6a4db94011d3 779 #endif /* USART_H_INCLUDED */