Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tc/tc.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief SAM TC - Timer Counter Driver |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | #ifndef TC_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 48 | #define TC_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 49 | |
sahilmgandhi | 18:6a4db94011d3 | 50 | /** |
sahilmgandhi | 18:6a4db94011d3 | 51 | * \defgroup asfdoc_sam0_tc_group SAM Timer/Counter Driver (TC) |
sahilmgandhi | 18:6a4db94011d3 | 52 | * |
sahilmgandhi | 18:6a4db94011d3 | 53 | * This driver for Atmel® | SMART SAM devices provides an interface for the configuration |
sahilmgandhi | 18:6a4db94011d3 | 54 | * and management of the timer modules within the device, for waveform |
sahilmgandhi | 18:6a4db94011d3 | 55 | * generation and timing operations. The following driver API modes are covered |
sahilmgandhi | 18:6a4db94011d3 | 56 | * by this manual: |
sahilmgandhi | 18:6a4db94011d3 | 57 | * |
sahilmgandhi | 18:6a4db94011d3 | 58 | * - Polled APIs |
sahilmgandhi | 18:6a4db94011d3 | 59 | * \if TC_CALLBACK_MODE |
sahilmgandhi | 18:6a4db94011d3 | 60 | * - Callback APIs |
sahilmgandhi | 18:6a4db94011d3 | 61 | * \endif |
sahilmgandhi | 18:6a4db94011d3 | 62 | * |
sahilmgandhi | 18:6a4db94011d3 | 63 | * |
sahilmgandhi | 18:6a4db94011d3 | 64 | * The following peripherals are used by this module: |
sahilmgandhi | 18:6a4db94011d3 | 65 | * - TC (Timer/Counter) |
sahilmgandhi | 18:6a4db94011d3 | 66 | * |
sahilmgandhi | 18:6a4db94011d3 | 67 | * The following devices can use this module: |
sahilmgandhi | 18:6a4db94011d3 | 68 | * - Atmel | SMART SAM D20/D21 |
sahilmgandhi | 18:6a4db94011d3 | 69 | * - Atmel | SMART SAM R21 |
sahilmgandhi | 18:6a4db94011d3 | 70 | * - Atmel | SMART SAM D10/D11 |
sahilmgandhi | 18:6a4db94011d3 | 71 | * - Atmel | SMART SAM L21 |
sahilmgandhi | 18:6a4db94011d3 | 72 | * - Atmel | SMART SAM DAx |
sahilmgandhi | 18:6a4db94011d3 | 73 | * - Atmel | SMART SAM C20/C21 |
sahilmgandhi | 18:6a4db94011d3 | 74 | * |
sahilmgandhi | 18:6a4db94011d3 | 75 | * The outline of this documentation is as follows: |
sahilmgandhi | 18:6a4db94011d3 | 76 | * - \ref asfdoc_sam0_tc_prerequisites |
sahilmgandhi | 18:6a4db94011d3 | 77 | * - \ref asfdoc_sam0_tc_module_overview |
sahilmgandhi | 18:6a4db94011d3 | 78 | * - \ref asfdoc_sam0_tc_special_considerations |
sahilmgandhi | 18:6a4db94011d3 | 79 | * - \ref asfdoc_sam0_tc_extra_info |
sahilmgandhi | 18:6a4db94011d3 | 80 | * - \ref asfdoc_sam0_tc_examples |
sahilmgandhi | 18:6a4db94011d3 | 81 | * - \ref asfdoc_sam0_tc_api_overview |
sahilmgandhi | 18:6a4db94011d3 | 82 | * |
sahilmgandhi | 18:6a4db94011d3 | 83 | * |
sahilmgandhi | 18:6a4db94011d3 | 84 | * \section asfdoc_sam0_tc_prerequisites Prerequisites |
sahilmgandhi | 18:6a4db94011d3 | 85 | * |
sahilmgandhi | 18:6a4db94011d3 | 86 | * There are no prerequisites for this module. |
sahilmgandhi | 18:6a4db94011d3 | 87 | * |
sahilmgandhi | 18:6a4db94011d3 | 88 | * |
sahilmgandhi | 18:6a4db94011d3 | 89 | * \section asfdoc_sam0_tc_module_overview Module Overview |
sahilmgandhi | 18:6a4db94011d3 | 90 | * |
sahilmgandhi | 18:6a4db94011d3 | 91 | * The Timer/Counter (TC) module provides a set of timing and counting related |
sahilmgandhi | 18:6a4db94011d3 | 92 | * functionality, such as the generation of periodic waveforms, the capturing |
sahilmgandhi | 18:6a4db94011d3 | 93 | * of a periodic waveform's frequency/duty cycle, and software timekeeping for |
sahilmgandhi | 18:6a4db94011d3 | 94 | * periodic operations. TC modules can be configured to use an 8-, 16-, or |
sahilmgandhi | 18:6a4db94011d3 | 95 | * 32-bit counter size. |
sahilmgandhi | 18:6a4db94011d3 | 96 | * |
sahilmgandhi | 18:6a4db94011d3 | 97 | * This TC module for the SAM is capable of the following functions: |
sahilmgandhi | 18:6a4db94011d3 | 98 | * |
sahilmgandhi | 18:6a4db94011d3 | 99 | * - Generation of PWM signals |
sahilmgandhi | 18:6a4db94011d3 | 100 | * - Generation of timestamps for events |
sahilmgandhi | 18:6a4db94011d3 | 101 | * - General time counting |
sahilmgandhi | 18:6a4db94011d3 | 102 | * - Waveform period capture |
sahilmgandhi | 18:6a4db94011d3 | 103 | * - Waveform frequency capture |
sahilmgandhi | 18:6a4db94011d3 | 104 | * |
sahilmgandhi | 18:6a4db94011d3 | 105 | * \ref asfdoc_sam0_tc_block_diagram "The diagram below" shows the overview |
sahilmgandhi | 18:6a4db94011d3 | 106 | * of the TC module design. |
sahilmgandhi | 18:6a4db94011d3 | 107 | * |
sahilmgandhi | 18:6a4db94011d3 | 108 | * \anchor asfdoc_sam0_tc_block_diagram |
sahilmgandhi | 18:6a4db94011d3 | 109 | * \image html overview.svg "Basic Overview of the TC Module" |
sahilmgandhi | 18:6a4db94011d3 | 110 | * |
sahilmgandhi | 18:6a4db94011d3 | 111 | * |
sahilmgandhi | 18:6a4db94011d3 | 112 | * \subsection asfdoc_sam0_tc_features Driver Feature Macro Definition |
sahilmgandhi | 18:6a4db94011d3 | 113 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 114 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 115 | * <th>Driver Feature Macro</th> |
sahilmgandhi | 18:6a4db94011d3 | 116 | * <th>Supported devices</th> |
sahilmgandhi | 18:6a4db94011d3 | 117 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 118 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 119 | * <td>FEATURE_TC_DOUBLE_BUFFERED</td> |
sahilmgandhi | 18:6a4db94011d3 | 120 | * <td>SAML21/C20/C21</td> |
sahilmgandhi | 18:6a4db94011d3 | 121 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 122 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 123 | * <td>FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2</td> |
sahilmgandhi | 18:6a4db94011d3 | 124 | * <td>SAML21/C20/C21</td> |
sahilmgandhi | 18:6a4db94011d3 | 125 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 126 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 127 | * <td>FEATURE_TC_STAMP_PW_CAPTURE</td> |
sahilmgandhi | 18:6a4db94011d3 | 128 | * <td>SAML21/C20/C21</td> |
sahilmgandhi | 18:6a4db94011d3 | 129 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 130 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 131 | * <td>FEATURE_TC_READ_SYNC</td> |
sahilmgandhi | 18:6a4db94011d3 | 132 | * <td>SAML21/C20/C21</td> |
sahilmgandhi | 18:6a4db94011d3 | 133 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 134 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 135 | * <td>FEATURE_TC_IO_CAPTURE</td> |
sahilmgandhi | 18:6a4db94011d3 | 136 | * <td>SAML21/C20/C21</td> |
sahilmgandhi | 18:6a4db94011d3 | 137 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 138 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 139 | * <td>FEATURE_TC_GENERATE_DMA_TRIGGER</td> |
sahilmgandhi | 18:6a4db94011d3 | 140 | * <td>SAML21</td> |
sahilmgandhi | 18:6a4db94011d3 | 141 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 142 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 143 | * \note The specific features are only available in the driver when the |
sahilmgandhi | 18:6a4db94011d3 | 144 | * selected device supports those features. |
sahilmgandhi | 18:6a4db94011d3 | 145 | * |
sahilmgandhi | 18:6a4db94011d3 | 146 | * \subsection asfdoc_sam0_tc_module_overview_func_desc Functional Description |
sahilmgandhi | 18:6a4db94011d3 | 147 | * Independent of the configured counter size, each TC module can be set up |
sahilmgandhi | 18:6a4db94011d3 | 148 | * in one of two different modes; capture and compare. |
sahilmgandhi | 18:6a4db94011d3 | 149 | * |
sahilmgandhi | 18:6a4db94011d3 | 150 | * In capture mode, the counter value is stored when a configurable event |
sahilmgandhi | 18:6a4db94011d3 | 151 | * occurs. This mode can be used to generate timestamps used in event capture, |
sahilmgandhi | 18:6a4db94011d3 | 152 | * or it can be used for the measurement of a periodic input signal's |
sahilmgandhi | 18:6a4db94011d3 | 153 | * frequency/duty cycle. |
sahilmgandhi | 18:6a4db94011d3 | 154 | * |
sahilmgandhi | 18:6a4db94011d3 | 155 | * In compare mode, the counter value is compared against one or more of the |
sahilmgandhi | 18:6a4db94011d3 | 156 | * configured channel compare values. When the counter value coincides with a |
sahilmgandhi | 18:6a4db94011d3 | 157 | * compare value an action can be taken automatically by the module, such as |
sahilmgandhi | 18:6a4db94011d3 | 158 | * generating an output event or toggling a pin when used for frequency or PWM |
sahilmgandhi | 18:6a4db94011d3 | 159 | * signal generation. |
sahilmgandhi | 18:6a4db94011d3 | 160 | * |
sahilmgandhi | 18:6a4db94011d3 | 161 | * \note The connection of events between modules requires the use of the |
sahilmgandhi | 18:6a4db94011d3 | 162 | * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" |
sahilmgandhi | 18:6a4db94011d3 | 163 | * to route output event of one module to the input event of another. |
sahilmgandhi | 18:6a4db94011d3 | 164 | * For more information on event routing, refer to the event driver |
sahilmgandhi | 18:6a4db94011d3 | 165 | * documentation. |
sahilmgandhi | 18:6a4db94011d3 | 166 | * |
sahilmgandhi | 18:6a4db94011d3 | 167 | * \subsection asfdoc_sam0_tc_module_overview_tc_size Timer/Counter Size |
sahilmgandhi | 18:6a4db94011d3 | 168 | * Each timer module can be configured in one of three different counter |
sahilmgandhi | 18:6a4db94011d3 | 169 | * sizes; 8-, 16-, and 32-bit. The size of the counter determines the maximum |
sahilmgandhi | 18:6a4db94011d3 | 170 | * value it can count to before an overflow occurs and the count is reset back |
sahilmgandhi | 18:6a4db94011d3 | 171 | * to zero. \ref asfdoc_sam0_tc_count_size_vs_top "The table below" shows the |
sahilmgandhi | 18:6a4db94011d3 | 172 | * maximum values for each of the possible counter sizes. |
sahilmgandhi | 18:6a4db94011d3 | 173 | * |
sahilmgandhi | 18:6a4db94011d3 | 174 | * \anchor asfdoc_sam0_tc_count_size_vs_top |
sahilmgandhi | 18:6a4db94011d3 | 175 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 176 | * <caption>Timer Counter Sizes and Their Maximum Count Values</caption> |
sahilmgandhi | 18:6a4db94011d3 | 177 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 178 | * <th>Counter size</th> |
sahilmgandhi | 18:6a4db94011d3 | 179 | * <th>Max. (hexadecimal)</th> |
sahilmgandhi | 18:6a4db94011d3 | 180 | * <th>Max. (decimal)</th> |
sahilmgandhi | 18:6a4db94011d3 | 181 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 182 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 183 | * <td>8-bit</td> |
sahilmgandhi | 18:6a4db94011d3 | 184 | * <td>0xFF</td> |
sahilmgandhi | 18:6a4db94011d3 | 185 | * <td>255</td> |
sahilmgandhi | 18:6a4db94011d3 | 186 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 187 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 188 | * <td>16-bit</td> |
sahilmgandhi | 18:6a4db94011d3 | 189 | * <td>0xFFFF</td> |
sahilmgandhi | 18:6a4db94011d3 | 190 | * <td>65,535</td> |
sahilmgandhi | 18:6a4db94011d3 | 191 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 192 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 193 | * <td>32-bit</td> |
sahilmgandhi | 18:6a4db94011d3 | 194 | * <td>0xFFFFFFFF</td> |
sahilmgandhi | 18:6a4db94011d3 | 195 | * <td>4,294,967,295</td> |
sahilmgandhi | 18:6a4db94011d3 | 196 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 197 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 198 | * |
sahilmgandhi | 18:6a4db94011d3 | 199 | * When using the counter in 16- or 32-bit count mode, Compare Capture |
sahilmgandhi | 18:6a4db94011d3 | 200 | * register 0 (CC0) is used to store the period value when running in PWM |
sahilmgandhi | 18:6a4db94011d3 | 201 | * generation match mode. |
sahilmgandhi | 18:6a4db94011d3 | 202 | * |
sahilmgandhi | 18:6a4db94011d3 | 203 | * When using 32-bit counter size, two 16-bit counters are chained together |
sahilmgandhi | 18:6a4db94011d3 | 204 | * in a cascade formation. Except in SAM D10/D11, Even numbered TC modules |
sahilmgandhi | 18:6a4db94011d3 | 205 | * (e.g. TC0, TC2) can be configured as 32-bit counters. The odd numbered |
sahilmgandhi | 18:6a4db94011d3 | 206 | * counters will act as slaves to the even numbered masters, and will not |
sahilmgandhi | 18:6a4db94011d3 | 207 | * be reconfigurable until the master timer is disabled. The pairing of timer |
sahilmgandhi | 18:6a4db94011d3 | 208 | * modules for 32-bit mode is shown in \ref asfdoc_sam0_tc_module_ms_pairs |
sahilmgandhi | 18:6a4db94011d3 | 209 | * "the table below". |
sahilmgandhi | 18:6a4db94011d3 | 210 | * |
sahilmgandhi | 18:6a4db94011d3 | 211 | * \anchor asfdoc_sam0_tc_module_ms_pairs |
sahilmgandhi | 18:6a4db94011d3 | 212 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 213 | * <caption>TC Master and Slave Module Pairings</caption> |
sahilmgandhi | 18:6a4db94011d3 | 214 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 215 | * <th>Master TC Module</th> |
sahilmgandhi | 18:6a4db94011d3 | 216 | * <th>Slave TC Module</th> |
sahilmgandhi | 18:6a4db94011d3 | 217 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 218 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 219 | * <td>TC0</td> |
sahilmgandhi | 18:6a4db94011d3 | 220 | * <td>TC1</td> |
sahilmgandhi | 18:6a4db94011d3 | 221 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 222 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 223 | * <td>TC2</td> |
sahilmgandhi | 18:6a4db94011d3 | 224 | * <td>TC3</td> |
sahilmgandhi | 18:6a4db94011d3 | 225 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 226 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 227 | * <td>...</td> |
sahilmgandhi | 18:6a4db94011d3 | 228 | * <td>...</td> |
sahilmgandhi | 18:6a4db94011d3 | 229 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 230 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 231 | * <td>TCn-1</td> |
sahilmgandhi | 18:6a4db94011d3 | 232 | * <td>TCn</td> |
sahilmgandhi | 18:6a4db94011d3 | 233 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 234 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 235 | * |
sahilmgandhi | 18:6a4db94011d3 | 236 | * In SAMD10/D11, odd numbered TC modules (e.g. TC1) can be configured as 32-bit |
sahilmgandhi | 18:6a4db94011d3 | 237 | * counters. The even numbered(e.g. TC2) counters will act as slaves to the odd |
sahilmgandhi | 18:6a4db94011d3 | 238 | * numbered masters. |
sahilmgandhi | 18:6a4db94011d3 | 239 | * |
sahilmgandhi | 18:6a4db94011d3 | 240 | * \subsection asfdoc_sam0_tc_module_overview_clock Clock Settings |
sahilmgandhi | 18:6a4db94011d3 | 241 | * |
sahilmgandhi | 18:6a4db94011d3 | 242 | * \subsubsection asfdoc_sam0_tc_module_overview_clock_selection Clock Selection |
sahilmgandhi | 18:6a4db94011d3 | 243 | * Each TC peripheral is clocked asynchronously to the system clock by a GCLK |
sahilmgandhi | 18:6a4db94011d3 | 244 | * (Generic Clock) channel. The GCLK channel connects to any of the GCLK |
sahilmgandhi | 18:6a4db94011d3 | 245 | * generators. The GCLK generators are configured to use one of the available |
sahilmgandhi | 18:6a4db94011d3 | 246 | * clock sources on the system such as internal oscillator, external crystals, |
sahilmgandhi | 18:6a4db94011d3 | 247 | * etc. see the \ref asfdoc_sam0_system_clock_group "Generic Clock driver" |
sahilmgandhi | 18:6a4db94011d3 | 248 | *for |
sahilmgandhi | 18:6a4db94011d3 | 249 | * more information. |
sahilmgandhi | 18:6a4db94011d3 | 250 | * |
sahilmgandhi | 18:6a4db94011d3 | 251 | * \subsubsection asfdoc_sam0_tc_module_overview_clock_prescaler Prescaler |
sahilmgandhi | 18:6a4db94011d3 | 252 | * Each TC module in the SAM has its own individual clock prescaler, which |
sahilmgandhi | 18:6a4db94011d3 | 253 | * can be used to divide the input clock frequency used in the counter. This |
sahilmgandhi | 18:6a4db94011d3 | 254 | * prescaler only scales the clock used to provide clock pulses for the counter |
sahilmgandhi | 18:6a4db94011d3 | 255 | * to count, and does not affect the digital register interface portion of |
sahilmgandhi | 18:6a4db94011d3 | 256 | * the module, thus the timer registers will synchronize to the raw GCLK |
sahilmgandhi | 18:6a4db94011d3 | 257 | * frequency input to the module. |
sahilmgandhi | 18:6a4db94011d3 | 258 | * |
sahilmgandhi | 18:6a4db94011d3 | 259 | * As a result of this, when selecting a GCLK frequency and timer prescaler |
sahilmgandhi | 18:6a4db94011d3 | 260 | * value the user application should consider both the timer resolution |
sahilmgandhi | 18:6a4db94011d3 | 261 | * required and the synchronization frequency, to avoid lengthy |
sahilmgandhi | 18:6a4db94011d3 | 262 | * synchronization times of the module if a very slow GCLK frequency is fed |
sahilmgandhi | 18:6a4db94011d3 | 263 | * into the TC module. It is preferable to use a higher module GCLK frequency |
sahilmgandhi | 18:6a4db94011d3 | 264 | * as the input to the timer, and prescale this down as much as possible to |
sahilmgandhi | 18:6a4db94011d3 | 265 | * obtain a suitable counter frequency in latency-sensitive applications. |
sahilmgandhi | 18:6a4db94011d3 | 266 | * |
sahilmgandhi | 18:6a4db94011d3 | 267 | * \subsubsection asfdoc_sam0_tc_module_overview_clock_reloading Reloading |
sahilmgandhi | 18:6a4db94011d3 | 268 | * Timer modules also contain a configurable reload action, used when a |
sahilmgandhi | 18:6a4db94011d3 | 269 | * re-trigger event occurs. Examples of a re-trigger event are the counter |
sahilmgandhi | 18:6a4db94011d3 | 270 | * reaching the maximum value when counting up, or when an event from the event |
sahilmgandhi | 18:6a4db94011d3 | 271 | * system tells the counter to re-trigger. The reload action determines if the |
sahilmgandhi | 18:6a4db94011d3 | 272 | * prescaler should be reset, and when this should happen. The counter will |
sahilmgandhi | 18:6a4db94011d3 | 273 | * always be reloaded with the value it is set to start counting from. The user |
sahilmgandhi | 18:6a4db94011d3 | 274 | * can choose between three different reload actions, described in |
sahilmgandhi | 18:6a4db94011d3 | 275 | * \ref asfdoc_sam0_tc_module_reload_act "the table below". |
sahilmgandhi | 18:6a4db94011d3 | 276 | * |
sahilmgandhi | 18:6a4db94011d3 | 277 | * \anchor asfdoc_sam0_tc_module_reload_act |
sahilmgandhi | 18:6a4db94011d3 | 278 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 279 | * <caption>TC Module Reload Actions</caption> |
sahilmgandhi | 18:6a4db94011d3 | 280 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 281 | * <th>Reload action</th> |
sahilmgandhi | 18:6a4db94011d3 | 282 | * <th>Description</th> |
sahilmgandhi | 18:6a4db94011d3 | 283 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 284 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 285 | * <td>\ref TC_RELOAD_ACTION_GCLK </td> |
sahilmgandhi | 18:6a4db94011d3 | 286 | * <td>Reload TC counter value on next GCLK cycle. Leave prescaler |
sahilmgandhi | 18:6a4db94011d3 | 287 | * as-is.</td> |
sahilmgandhi | 18:6a4db94011d3 | 288 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 289 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 290 | * <td>\ref TC_RELOAD_ACTION_PRESC </td> |
sahilmgandhi | 18:6a4db94011d3 | 291 | * <td>Reloads TC counter value on next prescaler clock. Leave prescaler |
sahilmgandhi | 18:6a4db94011d3 | 292 | * as-is.</td> |
sahilmgandhi | 18:6a4db94011d3 | 293 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 294 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 295 | * <td> \ref TC_RELOAD_ACTION_RESYNC </td> |
sahilmgandhi | 18:6a4db94011d3 | 296 | * <td>Reload TC counter value on next GCLK cycle. Clear prescaler to |
sahilmgandhi | 18:6a4db94011d3 | 297 | * zero.</td> |
sahilmgandhi | 18:6a4db94011d3 | 298 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 299 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 300 | * |
sahilmgandhi | 18:6a4db94011d3 | 301 | * The reload action to use will depend on the specific application being |
sahilmgandhi | 18:6a4db94011d3 | 302 | * implemented. One example is when an external trigger for a reload occurs; if |
sahilmgandhi | 18:6a4db94011d3 | 303 | * the TC uses the prescaler, the counter in the prescaler should not have a |
sahilmgandhi | 18:6a4db94011d3 | 304 | * value between zero and the division factor. The TC counter and the counter |
sahilmgandhi | 18:6a4db94011d3 | 305 | * in the prescaler should both start at zero. When the counter is set to |
sahilmgandhi | 18:6a4db94011d3 | 306 | * re-trigger when it reaches the maximum value on the other hand, this is not the |
sahilmgandhi | 18:6a4db94011d3 | 307 | * right option to use. In such a case it would be better if the prescaler is |
sahilmgandhi | 18:6a4db94011d3 | 308 | * left unaltered when the re-trigger happens, letting the counter reset on the |
sahilmgandhi | 18:6a4db94011d3 | 309 | * next GCLK cycle. |
sahilmgandhi | 18:6a4db94011d3 | 310 | * |
sahilmgandhi | 18:6a4db94011d3 | 311 | * \subsection asfdoc_sam0_tc_module_overview_compare_match Compare Match Operations |
sahilmgandhi | 18:6a4db94011d3 | 312 | * In compare match operation, Compare/Capture registers are used in comparison |
sahilmgandhi | 18:6a4db94011d3 | 313 | * with the counter value. When the timer's count value matches the value of a |
sahilmgandhi | 18:6a4db94011d3 | 314 | * compare channel, a user defined action can be taken. |
sahilmgandhi | 18:6a4db94011d3 | 315 | * |
sahilmgandhi | 18:6a4db94011d3 | 316 | * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_timer Basic Timer |
sahilmgandhi | 18:6a4db94011d3 | 317 | * |
sahilmgandhi | 18:6a4db94011d3 | 318 | * A Basic Timer is a simple application where compare match operations is used |
sahilmgandhi | 18:6a4db94011d3 | 319 | * to determine when a specific period has elapsed. In Basic Timer operations, |
sahilmgandhi | 18:6a4db94011d3 | 320 | * one or more values in the module's Compare/Capture registers are used to |
sahilmgandhi | 18:6a4db94011d3 | 321 | * specify the time (as a number of prescaled GCLK cycles) when an action should |
sahilmgandhi | 18:6a4db94011d3 | 322 | * be taken by the microcontroller. This can be an Interrupt Service Routine |
sahilmgandhi | 18:6a4db94011d3 | 323 | * (ISR), event generator via the event system, or a software flag that is |
sahilmgandhi | 18:6a4db94011d3 | 324 | * polled via the user application. |
sahilmgandhi | 18:6a4db94011d3 | 325 | * |
sahilmgandhi | 18:6a4db94011d3 | 326 | * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg Waveform Generation |
sahilmgandhi | 18:6a4db94011d3 | 327 | * |
sahilmgandhi | 18:6a4db94011d3 | 328 | * Waveform generation enables the TC module to generate square waves, or if |
sahilmgandhi | 18:6a4db94011d3 | 329 | * combined with an external passive low-pass filter; analog waveforms. |
sahilmgandhi | 18:6a4db94011d3 | 330 | * |
sahilmgandhi | 18:6a4db94011d3 | 331 | * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_pwm Waveform Generation - PWM |
sahilmgandhi | 18:6a4db94011d3 | 332 | * |
sahilmgandhi | 18:6a4db94011d3 | 333 | * Pulse width modulation is a form of waveform generation and a signalling |
sahilmgandhi | 18:6a4db94011d3 | 334 | * technique that can be useful in many situations. When PWM mode is used, |
sahilmgandhi | 18:6a4db94011d3 | 335 | * a digital pulse train with a configurable frequency and duty cycle can be |
sahilmgandhi | 18:6a4db94011d3 | 336 | * generated by the TC module and output to a GPIO pin of the device. |
sahilmgandhi | 18:6a4db94011d3 | 337 | * |
sahilmgandhi | 18:6a4db94011d3 | 338 | * Often PWM is used to communicate a control or information parameter to an |
sahilmgandhi | 18:6a4db94011d3 | 339 | * external circuit or component. Differing impedances of the source generator |
sahilmgandhi | 18:6a4db94011d3 | 340 | * and sink receiver circuits is less of an issue when using PWM compared to |
sahilmgandhi | 18:6a4db94011d3 | 341 | * using an analog voltage value, as noise will not generally affect the |
sahilmgandhi | 18:6a4db94011d3 | 342 | * signal's integrity to a meaningful extent. |
sahilmgandhi | 18:6a4db94011d3 | 343 | * |
sahilmgandhi | 18:6a4db94011d3 | 344 | * \ref asfdoc_sam0_tc_module_pwm_normal_diag "The figure below" illustrates |
sahilmgandhi | 18:6a4db94011d3 | 345 | * operations and different states of the counter and its output when running |
sahilmgandhi | 18:6a4db94011d3 | 346 | * the counter in PWM normal mode. As can be seen, the TOP value is unchanged |
sahilmgandhi | 18:6a4db94011d3 | 347 | * and is set to MAX. The compare match value is changed at several points to |
sahilmgandhi | 18:6a4db94011d3 | 348 | * illustrate the resulting waveform output changes. The PWM output is set to |
sahilmgandhi | 18:6a4db94011d3 | 349 | * normal (i.e. non-inverted) output mode. |
sahilmgandhi | 18:6a4db94011d3 | 350 | * |
sahilmgandhi | 18:6a4db94011d3 | 351 | * \anchor asfdoc_sam0_tc_module_pwm_normal_diag |
sahilmgandhi | 18:6a4db94011d3 | 352 | * \image html pwm_normal_ex.svg "Example of PWM in Normal Mode, and Different Counter Operations" |
sahilmgandhi | 18:6a4db94011d3 | 353 | * |
sahilmgandhi | 18:6a4db94011d3 | 354 | * |
sahilmgandhi | 18:6a4db94011d3 | 355 | * In \ref asfdoc_sam0_tc_module_pwm_match_diag "the figure below", the |
sahilmgandhi | 18:6a4db94011d3 | 356 | * counter is set to generate PWM in Match mode. The PWM output is inverted via |
sahilmgandhi | 18:6a4db94011d3 | 357 | * the appropriate configuration option in the TC driver configuration |
sahilmgandhi | 18:6a4db94011d3 | 358 | * structure. In this example, the counter value is changed once, but the |
sahilmgandhi | 18:6a4db94011d3 | 359 | * compare match value is kept unchanged. As can be seen, it is possible to |
sahilmgandhi | 18:6a4db94011d3 | 360 | * change the TOP value when running in PWM match mode. |
sahilmgandhi | 18:6a4db94011d3 | 361 | * |
sahilmgandhi | 18:6a4db94011d3 | 362 | * \anchor asfdoc_sam0_tc_module_pwm_match_diag |
sahilmgandhi | 18:6a4db94011d3 | 363 | * \image html pwm_match_ex.svg "Example of PWM in Match Mode, and Different Counter Operations" |
sahilmgandhi | 18:6a4db94011d3 | 364 | * |
sahilmgandhi | 18:6a4db94011d3 | 365 | * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_freq Waveform Generation - Frequency |
sahilmgandhi | 18:6a4db94011d3 | 366 | * |
sahilmgandhi | 18:6a4db94011d3 | 367 | * Frequency Generation mode is in many ways identical to PWM |
sahilmgandhi | 18:6a4db94011d3 | 368 | * generation. However, in Frequency Generation a toggle only occurs |
sahilmgandhi | 18:6a4db94011d3 | 369 | * on the output when a match on a capture channels occurs. When the |
sahilmgandhi | 18:6a4db94011d3 | 370 | * match is made, the timer value is reset, resulting in a variable |
sahilmgandhi | 18:6a4db94011d3 | 371 | * frequency square wave with a fixed 50% duty cycle. |
sahilmgandhi | 18:6a4db94011d3 | 372 | * |
sahilmgandhi | 18:6a4db94011d3 | 373 | * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt Capture Operations |
sahilmgandhi | 18:6a4db94011d3 | 374 | * |
sahilmgandhi | 18:6a4db94011d3 | 375 | * In capture operations, any event from the event system or a pin change can |
sahilmgandhi | 18:6a4db94011d3 | 376 | * trigger a capture of the counter value. This captured counter value can be |
sahilmgandhi | 18:6a4db94011d3 | 377 | * used as a timestamp for the event, or it can be used in frequency and pulse |
sahilmgandhi | 18:6a4db94011d3 | 378 | * width capture. |
sahilmgandhi | 18:6a4db94011d3 | 379 | * |
sahilmgandhi | 18:6a4db94011d3 | 380 | * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_event_capture Capture Operations - Event |
sahilmgandhi | 18:6a4db94011d3 | 381 | * |
sahilmgandhi | 18:6a4db94011d3 | 382 | * Event capture is a simple use of the capture functionality, |
sahilmgandhi | 18:6a4db94011d3 | 383 | * designed to create timestamps for specific events. When the TC |
sahilmgandhi | 18:6a4db94011d3 | 384 | * module's input capture pin is externally toggled, the current timer |
sahilmgandhi | 18:6a4db94011d3 | 385 | * count value is copied into a buffered register which can then be |
sahilmgandhi | 18:6a4db94011d3 | 386 | * read out by the user application. |
sahilmgandhi | 18:6a4db94011d3 | 387 | * |
sahilmgandhi | 18:6a4db94011d3 | 388 | * Note that when performing any capture operation, there is a risk that the |
sahilmgandhi | 18:6a4db94011d3 | 389 | * counter reaches its top value (MAX) when counting up, or the bottom value |
sahilmgandhi | 18:6a4db94011d3 | 390 | * (zero) when counting down, before the capture event occurs. This can distort |
sahilmgandhi | 18:6a4db94011d3 | 391 | * the result, making event timestamps to appear shorter than reality; the |
sahilmgandhi | 18:6a4db94011d3 | 392 | * user application should check for timer overflow when reading a capture |
sahilmgandhi | 18:6a4db94011d3 | 393 | * result in order to detect this situation and perform an appropriate |
sahilmgandhi | 18:6a4db94011d3 | 394 | * adjustment. |
sahilmgandhi | 18:6a4db94011d3 | 395 | * |
sahilmgandhi | 18:6a4db94011d3 | 396 | * Before checking for a new capture, \ref TC_STATUS_COUNT_OVERFLOW |
sahilmgandhi | 18:6a4db94011d3 | 397 | * should be checked. The response to an overflow error is left to the user |
sahilmgandhi | 18:6a4db94011d3 | 398 | * application, however it may be necessary to clear both the capture overflow |
sahilmgandhi | 18:6a4db94011d3 | 399 | * flag and the capture flag upon each capture reading. |
sahilmgandhi | 18:6a4db94011d3 | 400 | * |
sahilmgandhi | 18:6a4db94011d3 | 401 | * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_pwc Capture Operations - Pulse Width |
sahilmgandhi | 18:6a4db94011d3 | 402 | * |
sahilmgandhi | 18:6a4db94011d3 | 403 | * Pulse Width Capture mode makes it possible to measure the pulse width and |
sahilmgandhi | 18:6a4db94011d3 | 404 | * period of PWM signals. This mode uses two capture channels of the counter. |
sahilmgandhi | 18:6a4db94011d3 | 405 | * This means that the counter module used for Pulse Width Capture can not be |
sahilmgandhi | 18:6a4db94011d3 | 406 | * used for any other purpose. There are two modes for pulse width capture; |
sahilmgandhi | 18:6a4db94011d3 | 407 | * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture |
sahilmgandhi | 18:6a4db94011d3 | 408 | * channel 0 is used for storing the pulse width and capture channel 1 stores |
sahilmgandhi | 18:6a4db94011d3 | 409 | * the observed period. While in PPW mode, the roles of the two capture channels |
sahilmgandhi | 18:6a4db94011d3 | 410 | * is reversed. |
sahilmgandhi | 18:6a4db94011d3 | 411 | * |
sahilmgandhi | 18:6a4db94011d3 | 412 | * As in the above example it is necessary to poll on interrupt flags to see |
sahilmgandhi | 18:6a4db94011d3 | 413 | * if a new capture has happened and check that a capture overflow error has |
sahilmgandhi | 18:6a4db94011d3 | 414 | * not occurred. |
sahilmgandhi | 18:6a4db94011d3 | 415 | * |
sahilmgandhi | 18:6a4db94011d3 | 416 | * \subsection asfdoc_sam0_tc_module_overview_oneshot One-shot Mode |
sahilmgandhi | 18:6a4db94011d3 | 417 | * |
sahilmgandhi | 18:6a4db94011d3 | 418 | * TC modules can be configured into a one-shot mode. When configured in this |
sahilmgandhi | 18:6a4db94011d3 | 419 | * manner, starting the timer will cause it to count until the next overflow |
sahilmgandhi | 18:6a4db94011d3 | 420 | * or underflow condition before automatically halting, waiting to be manually |
sahilmgandhi | 18:6a4db94011d3 | 421 | * triggered by the user application software or an event signal from the event |
sahilmgandhi | 18:6a4db94011d3 | 422 | * system. |
sahilmgandhi | 18:6a4db94011d3 | 423 | * |
sahilmgandhi | 18:6a4db94011d3 | 424 | * \subsubsection asfdoc_sam0_tc_module_overview_inversion Wave Generation Output Inversion |
sahilmgandhi | 18:6a4db94011d3 | 425 | * |
sahilmgandhi | 18:6a4db94011d3 | 426 | * The output of the wave generation can be inverted by hardware if desired, |
sahilmgandhi | 18:6a4db94011d3 | 427 | * resulting in the logically inverted value being output to the configured |
sahilmgandhi | 18:6a4db94011d3 | 428 | * device GPIO pin. |
sahilmgandhi | 18:6a4db94011d3 | 429 | * |
sahilmgandhi | 18:6a4db94011d3 | 430 | * |
sahilmgandhi | 18:6a4db94011d3 | 431 | * \section asfdoc_sam0_tc_special_considerations Special Considerations |
sahilmgandhi | 18:6a4db94011d3 | 432 | * |
sahilmgandhi | 18:6a4db94011d3 | 433 | * The number of capture compare registers in each TC module is dependent on |
sahilmgandhi | 18:6a4db94011d3 | 434 | * the specific SAM device being used, and in some cases the counter size. |
sahilmgandhi | 18:6a4db94011d3 | 435 | * |
sahilmgandhi | 18:6a4db94011d3 | 436 | * The maximum amount of capture compare registers available in any SAM |
sahilmgandhi | 18:6a4db94011d3 | 437 | * device is two when running in 32-bit mode and four in 8- and 16-bit modes. |
sahilmgandhi | 18:6a4db94011d3 | 438 | * |
sahilmgandhi | 18:6a4db94011d3 | 439 | * |
sahilmgandhi | 18:6a4db94011d3 | 440 | * \section asfdoc_sam0_tc_extra_info Extra Information |
sahilmgandhi | 18:6a4db94011d3 | 441 | * |
sahilmgandhi | 18:6a4db94011d3 | 442 | * For extra information, see \ref asfdoc_sam0_tc_extra. This includes: |
sahilmgandhi | 18:6a4db94011d3 | 443 | * - \ref asfdoc_sam0_tc_extra_acronyms |
sahilmgandhi | 18:6a4db94011d3 | 444 | * - \ref asfdoc_sam0_tc_extra_dependencies |
sahilmgandhi | 18:6a4db94011d3 | 445 | * - \ref asfdoc_sam0_tc_extra_errata |
sahilmgandhi | 18:6a4db94011d3 | 446 | * - \ref asfdoc_sam0_tc_extra_history |
sahilmgandhi | 18:6a4db94011d3 | 447 | * |
sahilmgandhi | 18:6a4db94011d3 | 448 | * |
sahilmgandhi | 18:6a4db94011d3 | 449 | * \section asfdoc_sam0_tc_examples Examples |
sahilmgandhi | 18:6a4db94011d3 | 450 | * |
sahilmgandhi | 18:6a4db94011d3 | 451 | * For a list of examples related to this driver, see |
sahilmgandhi | 18:6a4db94011d3 | 452 | * \ref asfdoc_sam0_tc_exqsg. |
sahilmgandhi | 18:6a4db94011d3 | 453 | * |
sahilmgandhi | 18:6a4db94011d3 | 454 | * \section asfdoc_sam0_tc_api_overview API Overview |
sahilmgandhi | 18:6a4db94011d3 | 455 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 456 | */ |
sahilmgandhi | 18:6a4db94011d3 | 457 | |
sahilmgandhi | 18:6a4db94011d3 | 458 | #include <compiler.h> |
sahilmgandhi | 18:6a4db94011d3 | 459 | #include <clock.h> |
sahilmgandhi | 18:6a4db94011d3 | 460 | #include <gclk.h> |
sahilmgandhi | 18:6a4db94011d3 | 461 | #include <pinmux.h> |
sahilmgandhi | 18:6a4db94011d3 | 462 | |
sahilmgandhi | 18:6a4db94011d3 | 463 | /** |
sahilmgandhi | 18:6a4db94011d3 | 464 | * Define port features set according to different device family |
sahilmgandhi | 18:6a4db94011d3 | 465 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 466 | */ |
sahilmgandhi | 18:6a4db94011d3 | 467 | #if (SAML21) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 468 | /** TC double buffered. */ |
sahilmgandhi | 18:6a4db94011d3 | 469 | # define FEATURE_TC_DOUBLE_BUFFERED |
sahilmgandhi | 18:6a4db94011d3 | 470 | /** SYNCBUSY scheme version 2. */ |
sahilmgandhi | 18:6a4db94011d3 | 471 | # define FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2 |
sahilmgandhi | 18:6a4db94011d3 | 472 | /** TC time stamp capture and pulse width capture. */ |
sahilmgandhi | 18:6a4db94011d3 | 473 | # define FEATURE_TC_STAMP_PW_CAPTURE |
sahilmgandhi | 18:6a4db94011d3 | 474 | /** Read synchronization of COUNT. */ |
sahilmgandhi | 18:6a4db94011d3 | 475 | # define FEATURE_TC_READ_SYNC |
sahilmgandhi | 18:6a4db94011d3 | 476 | /** IO pin edge capture. */ |
sahilmgandhi | 18:6a4db94011d3 | 477 | # define FEATURE_TC_IO_CAPTURE |
sahilmgandhi | 18:6a4db94011d3 | 478 | /** Generate DMA triggers. */ |
sahilmgandhi | 18:6a4db94011d3 | 479 | # define FEATURE_TC_GENERATE_DMA_TRIGGER |
sahilmgandhi | 18:6a4db94011d3 | 480 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 481 | /*@}*/ |
sahilmgandhi | 18:6a4db94011d3 | 482 | |
sahilmgandhi | 18:6a4db94011d3 | 483 | #if !defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 484 | #if SAMD20 || SAML21 || SAMC20 || SAMC21 |
sahilmgandhi | 18:6a4db94011d3 | 485 | # define TC_INSTANCE_OFFSET 0 |
sahilmgandhi | 18:6a4db94011d3 | 486 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 487 | #if SAMD21 || SAMR21 || SAMDA1 |
sahilmgandhi | 18:6a4db94011d3 | 488 | # define TC_INSTANCE_OFFSET 3 |
sahilmgandhi | 18:6a4db94011d3 | 489 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 490 | #if SAMD10 || SAMD11 |
sahilmgandhi | 18:6a4db94011d3 | 491 | # define TC_INSTANCE_OFFSET 1 |
sahilmgandhi | 18:6a4db94011d3 | 492 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 493 | |
sahilmgandhi | 18:6a4db94011d3 | 494 | #if SAMD20 |
sahilmgandhi | 18:6a4db94011d3 | 495 | # define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC8_NUM |
sahilmgandhi | 18:6a4db94011d3 | 496 | #elif SAML21 || SAMC20 || SAMC21 |
sahilmgandhi | 18:6a4db94011d3 | 497 | # define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC_NUM |
sahilmgandhi | 18:6a4db94011d3 | 498 | #elif SAMD10 || SAMD11 |
sahilmgandhi | 18:6a4db94011d3 | 499 | # define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC1_CC8_NUM |
sahilmgandhi | 18:6a4db94011d3 | 500 | #else |
sahilmgandhi | 18:6a4db94011d3 | 501 | # define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC3_CC8_NUM |
sahilmgandhi | 18:6a4db94011d3 | 502 | /* Same number for 8-, 16- and 32-bit TC and all TC instances */ |
sahilmgandhi | 18:6a4db94011d3 | 503 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 504 | |
sahilmgandhi | 18:6a4db94011d3 | 505 | /** TC Instance MAX ID Number. */ |
sahilmgandhi | 18:6a4db94011d3 | 506 | #if SAMD20E || SAMD21G || SAMD21E || SAMR21 |
sahilmgandhi | 18:6a4db94011d3 | 507 | #define TC_INST_MAX_ID 5 |
sahilmgandhi | 18:6a4db94011d3 | 508 | #elif SAML21 || SAMC20 || SAMC21 |
sahilmgandhi | 18:6a4db94011d3 | 509 | #define TC_INST_MAX_ID 4 |
sahilmgandhi | 18:6a4db94011d3 | 510 | #elif SAMD10 || SAMD11 |
sahilmgandhi | 18:6a4db94011d3 | 511 | #define TC_INST_MAX_ID 2 |
sahilmgandhi | 18:6a4db94011d3 | 512 | #else |
sahilmgandhi | 18:6a4db94011d3 | 513 | #define TC_INST_MAX_ID 7 |
sahilmgandhi | 18:6a4db94011d3 | 514 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 515 | |
sahilmgandhi | 18:6a4db94011d3 | 516 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 517 | |
sahilmgandhi | 18:6a4db94011d3 | 518 | #if TC_ASYNC == true |
sahilmgandhi | 18:6a4db94011d3 | 519 | # include <system_interrupt.h> |
sahilmgandhi | 18:6a4db94011d3 | 520 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 521 | |
sahilmgandhi | 18:6a4db94011d3 | 522 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 523 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 524 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 525 | |
sahilmgandhi | 18:6a4db94011d3 | 526 | #if TC_ASYNC == true |
sahilmgandhi | 18:6a4db94011d3 | 527 | /** Enum for the possible callback types for the TC module. */ |
sahilmgandhi | 18:6a4db94011d3 | 528 | enum tc_callback { |
sahilmgandhi | 18:6a4db94011d3 | 529 | /** Callback for TC overflow. */ |
sahilmgandhi | 18:6a4db94011d3 | 530 | TC_CALLBACK_OVERFLOW, |
sahilmgandhi | 18:6a4db94011d3 | 531 | /** Callback for capture overflow error. */ |
sahilmgandhi | 18:6a4db94011d3 | 532 | TC_CALLBACK_ERROR, |
sahilmgandhi | 18:6a4db94011d3 | 533 | /** Callback for capture compare channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 534 | TC_CALLBACK_CC_CHANNEL0, |
sahilmgandhi | 18:6a4db94011d3 | 535 | /** Callback for capture compare channel 1. */ |
sahilmgandhi | 18:6a4db94011d3 | 536 | TC_CALLBACK_CC_CHANNEL1, |
sahilmgandhi | 18:6a4db94011d3 | 537 | # if !defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 538 | /** Number of available callbacks. */ |
sahilmgandhi | 18:6a4db94011d3 | 539 | TC_CALLBACK_N, |
sahilmgandhi | 18:6a4db94011d3 | 540 | # endif |
sahilmgandhi | 18:6a4db94011d3 | 541 | }; |
sahilmgandhi | 18:6a4db94011d3 | 542 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 543 | |
sahilmgandhi | 18:6a4db94011d3 | 544 | /** |
sahilmgandhi | 18:6a4db94011d3 | 545 | * \name Module Status Flags |
sahilmgandhi | 18:6a4db94011d3 | 546 | * |
sahilmgandhi | 18:6a4db94011d3 | 547 | * TC status flags, returned by \ref tc_get_status() and cleared by |
sahilmgandhi | 18:6a4db94011d3 | 548 | * \ref tc_clear_status(). |
sahilmgandhi | 18:6a4db94011d3 | 549 | * |
sahilmgandhi | 18:6a4db94011d3 | 550 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 551 | */ |
sahilmgandhi | 18:6a4db94011d3 | 552 | |
sahilmgandhi | 18:6a4db94011d3 | 553 | /** Timer channel 0 has matched against its compare value, or has captured a |
sahilmgandhi | 18:6a4db94011d3 | 554 | * new value. |
sahilmgandhi | 18:6a4db94011d3 | 555 | */ |
sahilmgandhi | 18:6a4db94011d3 | 556 | #define TC_STATUS_CHANNEL_0_MATCH (1UL << 0) |
sahilmgandhi | 18:6a4db94011d3 | 557 | |
sahilmgandhi | 18:6a4db94011d3 | 558 | /** Timer channel 1 has matched against its compare value, or has captured a |
sahilmgandhi | 18:6a4db94011d3 | 559 | * new value. |
sahilmgandhi | 18:6a4db94011d3 | 560 | */ |
sahilmgandhi | 18:6a4db94011d3 | 561 | #define TC_STATUS_CHANNEL_1_MATCH (1UL << 1) |
sahilmgandhi | 18:6a4db94011d3 | 562 | |
sahilmgandhi | 18:6a4db94011d3 | 563 | /** Timer register synchronization has completed, and the synchronized count |
sahilmgandhi | 18:6a4db94011d3 | 564 | * value may be read. |
sahilmgandhi | 18:6a4db94011d3 | 565 | */ |
sahilmgandhi | 18:6a4db94011d3 | 566 | #define TC_STATUS_SYNC_READY (1UL << 2) |
sahilmgandhi | 18:6a4db94011d3 | 567 | |
sahilmgandhi | 18:6a4db94011d3 | 568 | /** A new value was captured before the previous value was read, resulting in |
sahilmgandhi | 18:6a4db94011d3 | 569 | * lost data. |
sahilmgandhi | 18:6a4db94011d3 | 570 | */ |
sahilmgandhi | 18:6a4db94011d3 | 571 | #define TC_STATUS_CAPTURE_OVERFLOW (1UL << 3) |
sahilmgandhi | 18:6a4db94011d3 | 572 | |
sahilmgandhi | 18:6a4db94011d3 | 573 | /** The timer count value has overflowed from its maximum value to its minimum |
sahilmgandhi | 18:6a4db94011d3 | 574 | * when counting upward, or from its minimum value to its maximum when |
sahilmgandhi | 18:6a4db94011d3 | 575 | * counting downward. |
sahilmgandhi | 18:6a4db94011d3 | 576 | */ |
sahilmgandhi | 18:6a4db94011d3 | 577 | #define TC_STATUS_COUNT_OVERFLOW (1UL << 4) |
sahilmgandhi | 18:6a4db94011d3 | 578 | |
sahilmgandhi | 18:6a4db94011d3 | 579 | #ifdef FEATURE_TC_DOUBLE_BUFFERED |
sahilmgandhi | 18:6a4db94011d3 | 580 | /** Channel 0 compare or capture buffer valid. */ |
sahilmgandhi | 18:6a4db94011d3 | 581 | #define TC_STATUS_CHN0_BUFFER_VALID (1UL << 5) |
sahilmgandhi | 18:6a4db94011d3 | 582 | /** Channel 1 compare or capture buffer valid. */ |
sahilmgandhi | 18:6a4db94011d3 | 583 | #define TC_STATUS_CHN1_BUFFER_VALID (1UL << 6) |
sahilmgandhi | 18:6a4db94011d3 | 584 | /** Period buffer valid. */ |
sahilmgandhi | 18:6a4db94011d3 | 585 | #define TC_STATUS_PERIOD_BUFFER_VALID (1UL << 7) |
sahilmgandhi | 18:6a4db94011d3 | 586 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 587 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 588 | |
sahilmgandhi | 18:6a4db94011d3 | 589 | /** |
sahilmgandhi | 18:6a4db94011d3 | 590 | * \brief Index of the compare capture channels. |
sahilmgandhi | 18:6a4db94011d3 | 591 | * |
sahilmgandhi | 18:6a4db94011d3 | 592 | * This enum is used to specify which capture/compare channel to do |
sahilmgandhi | 18:6a4db94011d3 | 593 | * operations on. |
sahilmgandhi | 18:6a4db94011d3 | 594 | */ |
sahilmgandhi | 18:6a4db94011d3 | 595 | enum tc_compare_capture_channel { |
sahilmgandhi | 18:6a4db94011d3 | 596 | /** Index of compare capture channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 597 | TC_COMPARE_CAPTURE_CHANNEL_0, |
sahilmgandhi | 18:6a4db94011d3 | 598 | /** Index of compare capture channel 1. */ |
sahilmgandhi | 18:6a4db94011d3 | 599 | TC_COMPARE_CAPTURE_CHANNEL_1, |
sahilmgandhi | 18:6a4db94011d3 | 600 | }; |
sahilmgandhi | 18:6a4db94011d3 | 601 | |
sahilmgandhi | 18:6a4db94011d3 | 602 | /** TC wave generation mode. */ |
sahilmgandhi | 18:6a4db94011d3 | 603 | #if SAML21 || SAMC20 || SAMC21 |
sahilmgandhi | 18:6a4db94011d3 | 604 | #define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_WAVE_WAVEGEN_NFRQ |
sahilmgandhi | 18:6a4db94011d3 | 605 | #define TC_WAVE_GENERATION_MATCH_FREQ_MODE TC_WAVE_WAVEGEN_MFRQ |
sahilmgandhi | 18:6a4db94011d3 | 606 | #define TC_WAVE_GENERATION_NORMAL_PWM_MODE TC_WAVE_WAVEGEN_NPWM |
sahilmgandhi | 18:6a4db94011d3 | 607 | #define TC_WAVE_GENERATION_MATCH_PWM_MODE TC_WAVE_WAVEGEN_MPWM |
sahilmgandhi | 18:6a4db94011d3 | 608 | #else |
sahilmgandhi | 18:6a4db94011d3 | 609 | #define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_CTRLA_WAVEGEN_NFRQ |
sahilmgandhi | 18:6a4db94011d3 | 610 | #define TC_WAVE_GENERATION_MATCH_FREQ_MODE TC_CTRLA_WAVEGEN_MFRQ |
sahilmgandhi | 18:6a4db94011d3 | 611 | #define TC_WAVE_GENERATION_NORMAL_PWM_MODE TC_CTRLA_WAVEGEN_NPWM |
sahilmgandhi | 18:6a4db94011d3 | 612 | #define TC_WAVE_GENERATION_MATCH_PWM_MODE TC_CTRLA_WAVEGEN_MPWM |
sahilmgandhi | 18:6a4db94011d3 | 613 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 614 | |
sahilmgandhi | 18:6a4db94011d3 | 615 | /** |
sahilmgandhi | 18:6a4db94011d3 | 616 | * \brief TC wave generation mode enum. |
sahilmgandhi | 18:6a4db94011d3 | 617 | * |
sahilmgandhi | 18:6a4db94011d3 | 618 | * This enum is used to select which mode to run the wave |
sahilmgandhi | 18:6a4db94011d3 | 619 | * generation in. |
sahilmgandhi | 18:6a4db94011d3 | 620 | * |
sahilmgandhi | 18:6a4db94011d3 | 621 | */ |
sahilmgandhi | 18:6a4db94011d3 | 622 | enum tc_wave_generation { |
sahilmgandhi | 18:6a4db94011d3 | 623 | /** Top is maximum, except in 8-bit counter size where it is the PER |
sahilmgandhi | 18:6a4db94011d3 | 624 | * register. |
sahilmgandhi | 18:6a4db94011d3 | 625 | */ |
sahilmgandhi | 18:6a4db94011d3 | 626 | TC_WAVE_GENERATION_NORMAL_FREQ = TC_WAVE_GENERATION_NORMAL_FREQ_MODE, |
sahilmgandhi | 18:6a4db94011d3 | 627 | |
sahilmgandhi | 18:6a4db94011d3 | 628 | /** Top is CC0, except in 8-bit counter size where it is the PER |
sahilmgandhi | 18:6a4db94011d3 | 629 | * register. |
sahilmgandhi | 18:6a4db94011d3 | 630 | */ |
sahilmgandhi | 18:6a4db94011d3 | 631 | TC_WAVE_GENERATION_MATCH_FREQ = TC_WAVE_GENERATION_MATCH_FREQ_MODE, |
sahilmgandhi | 18:6a4db94011d3 | 632 | |
sahilmgandhi | 18:6a4db94011d3 | 633 | /** Top is maximum, except in 8-bit counter size where it is the PER |
sahilmgandhi | 18:6a4db94011d3 | 634 | * register. |
sahilmgandhi | 18:6a4db94011d3 | 635 | */ |
sahilmgandhi | 18:6a4db94011d3 | 636 | TC_WAVE_GENERATION_NORMAL_PWM = TC_WAVE_GENERATION_NORMAL_PWM_MODE, |
sahilmgandhi | 18:6a4db94011d3 | 637 | |
sahilmgandhi | 18:6a4db94011d3 | 638 | /** Top is CC0, except in 8-bit counter size where it is the PER |
sahilmgandhi | 18:6a4db94011d3 | 639 | * register. |
sahilmgandhi | 18:6a4db94011d3 | 640 | */ |
sahilmgandhi | 18:6a4db94011d3 | 641 | TC_WAVE_GENERATION_MATCH_PWM = TC_WAVE_GENERATION_MATCH_PWM_MODE, |
sahilmgandhi | 18:6a4db94011d3 | 642 | }; |
sahilmgandhi | 18:6a4db94011d3 | 643 | |
sahilmgandhi | 18:6a4db94011d3 | 644 | /** |
sahilmgandhi | 18:6a4db94011d3 | 645 | * \brief Specifies if the counter is 8-, 16-, or 32-bit. |
sahilmgandhi | 18:6a4db94011d3 | 646 | * |
sahilmgandhi | 18:6a4db94011d3 | 647 | * This enum specifies the maximum value it is possible to count to. |
sahilmgandhi | 18:6a4db94011d3 | 648 | */ |
sahilmgandhi | 18:6a4db94011d3 | 649 | enum tc_counter_size { |
sahilmgandhi | 18:6a4db94011d3 | 650 | /** The counter's maximum value is 0xFF, the period register is |
sahilmgandhi | 18:6a4db94011d3 | 651 | * available to be used as top value. |
sahilmgandhi | 18:6a4db94011d3 | 652 | */ |
sahilmgandhi | 18:6a4db94011d3 | 653 | TC_COUNTER_SIZE_8BIT = TC_CTRLA_MODE_COUNT8, |
sahilmgandhi | 18:6a4db94011d3 | 654 | |
sahilmgandhi | 18:6a4db94011d3 | 655 | /** The counter's maximum value is 0xFFFF. There is no separate |
sahilmgandhi | 18:6a4db94011d3 | 656 | * period register, to modify top one of the capture compare |
sahilmgandhi | 18:6a4db94011d3 | 657 | * registers has to be used. This limits the amount of |
sahilmgandhi | 18:6a4db94011d3 | 658 | * available channels. |
sahilmgandhi | 18:6a4db94011d3 | 659 | */ |
sahilmgandhi | 18:6a4db94011d3 | 660 | TC_COUNTER_SIZE_16BIT = TC_CTRLA_MODE_COUNT16, |
sahilmgandhi | 18:6a4db94011d3 | 661 | |
sahilmgandhi | 18:6a4db94011d3 | 662 | /** The counter's maximum value is 0xFFFFFFFF. There is no separate |
sahilmgandhi | 18:6a4db94011d3 | 663 | * period register, to modify top one of the capture compare |
sahilmgandhi | 18:6a4db94011d3 | 664 | * registers has to be used. This limits the amount of |
sahilmgandhi | 18:6a4db94011d3 | 665 | * available channels. |
sahilmgandhi | 18:6a4db94011d3 | 666 | */ |
sahilmgandhi | 18:6a4db94011d3 | 667 | TC_COUNTER_SIZE_32BIT = TC_CTRLA_MODE_COUNT32, |
sahilmgandhi | 18:6a4db94011d3 | 668 | }; |
sahilmgandhi | 18:6a4db94011d3 | 669 | |
sahilmgandhi | 18:6a4db94011d3 | 670 | /** |
sahilmgandhi | 18:6a4db94011d3 | 671 | * \brief TC Counter reload action enum. |
sahilmgandhi | 18:6a4db94011d3 | 672 | * |
sahilmgandhi | 18:6a4db94011d3 | 673 | * This enum specify how the counter and prescaler should reload. |
sahilmgandhi | 18:6a4db94011d3 | 674 | */ |
sahilmgandhi | 18:6a4db94011d3 | 675 | enum tc_reload_action { |
sahilmgandhi | 18:6a4db94011d3 | 676 | /** The counter is reloaded/reset on the next GCLK and starts |
sahilmgandhi | 18:6a4db94011d3 | 677 | * counting on the prescaler clock. |
sahilmgandhi | 18:6a4db94011d3 | 678 | */ |
sahilmgandhi | 18:6a4db94011d3 | 679 | TC_RELOAD_ACTION_GCLK = TC_CTRLA_PRESCSYNC_GCLK, |
sahilmgandhi | 18:6a4db94011d3 | 680 | |
sahilmgandhi | 18:6a4db94011d3 | 681 | /** The counter is reloaded/reset on the next prescaler clock. |
sahilmgandhi | 18:6a4db94011d3 | 682 | */ |
sahilmgandhi | 18:6a4db94011d3 | 683 | TC_RELOAD_ACTION_PRESC = TC_CTRLA_PRESCSYNC_PRESC, |
sahilmgandhi | 18:6a4db94011d3 | 684 | |
sahilmgandhi | 18:6a4db94011d3 | 685 | /** The counter is reloaded/reset on the next GCLK, and the |
sahilmgandhi | 18:6a4db94011d3 | 686 | * prescaler is restarted as well. |
sahilmgandhi | 18:6a4db94011d3 | 687 | */ |
sahilmgandhi | 18:6a4db94011d3 | 688 | TC_RELOAD_ACTION_RESYNC = TC_CTRLA_PRESCSYNC_RESYNC, |
sahilmgandhi | 18:6a4db94011d3 | 689 | }; |
sahilmgandhi | 18:6a4db94011d3 | 690 | |
sahilmgandhi | 18:6a4db94011d3 | 691 | /** |
sahilmgandhi | 18:6a4db94011d3 | 692 | * \brief TC clock prescaler values. |
sahilmgandhi | 18:6a4db94011d3 | 693 | * |
sahilmgandhi | 18:6a4db94011d3 | 694 | * This enum is used to choose the clock prescaler |
sahilmgandhi | 18:6a4db94011d3 | 695 | * configuration. The prescaler divides the clock frequency of the TC |
sahilmgandhi | 18:6a4db94011d3 | 696 | * module to make the counter count slower. |
sahilmgandhi | 18:6a4db94011d3 | 697 | */ |
sahilmgandhi | 18:6a4db94011d3 | 698 | enum tc_clock_prescaler { |
sahilmgandhi | 18:6a4db94011d3 | 699 | /** Divide clock by 1. */ |
sahilmgandhi | 18:6a4db94011d3 | 700 | TC_CLOCK_PRESCALER_DIV1 = TC_CTRLA_PRESCALER(0), |
sahilmgandhi | 18:6a4db94011d3 | 701 | /** Divide clock by 2. */ |
sahilmgandhi | 18:6a4db94011d3 | 702 | TC_CLOCK_PRESCALER_DIV2 = TC_CTRLA_PRESCALER(1), |
sahilmgandhi | 18:6a4db94011d3 | 703 | /** Divide clock by 4. */ |
sahilmgandhi | 18:6a4db94011d3 | 704 | TC_CLOCK_PRESCALER_DIV4 = TC_CTRLA_PRESCALER(2), |
sahilmgandhi | 18:6a4db94011d3 | 705 | /** Divide clock by 8. */ |
sahilmgandhi | 18:6a4db94011d3 | 706 | TC_CLOCK_PRESCALER_DIV8 = TC_CTRLA_PRESCALER(3), |
sahilmgandhi | 18:6a4db94011d3 | 707 | /** Divide clock by 16. */ |
sahilmgandhi | 18:6a4db94011d3 | 708 | TC_CLOCK_PRESCALER_DIV16 = TC_CTRLA_PRESCALER(4), |
sahilmgandhi | 18:6a4db94011d3 | 709 | /** Divide clock by 64. */ |
sahilmgandhi | 18:6a4db94011d3 | 710 | TC_CLOCK_PRESCALER_DIV64 = TC_CTRLA_PRESCALER(5), |
sahilmgandhi | 18:6a4db94011d3 | 711 | /** Divide clock by 256. */ |
sahilmgandhi | 18:6a4db94011d3 | 712 | TC_CLOCK_PRESCALER_DIV256 = TC_CTRLA_PRESCALER(6), |
sahilmgandhi | 18:6a4db94011d3 | 713 | /** Divide clock by 1024. */ |
sahilmgandhi | 18:6a4db94011d3 | 714 | TC_CLOCK_PRESCALER_DIV1024 = TC_CTRLA_PRESCALER(7), |
sahilmgandhi | 18:6a4db94011d3 | 715 | }; |
sahilmgandhi | 18:6a4db94011d3 | 716 | |
sahilmgandhi | 18:6a4db94011d3 | 717 | /** |
sahilmgandhi | 18:6a4db94011d3 | 718 | * \brief TC module count direction. |
sahilmgandhi | 18:6a4db94011d3 | 719 | * |
sahilmgandhi | 18:6a4db94011d3 | 720 | * Timer/Counter count direction. |
sahilmgandhi | 18:6a4db94011d3 | 721 | */ |
sahilmgandhi | 18:6a4db94011d3 | 722 | enum tc_count_direction { |
sahilmgandhi | 18:6a4db94011d3 | 723 | /** Timer should count upward from zero to MAX. */ |
sahilmgandhi | 18:6a4db94011d3 | 724 | TC_COUNT_DIRECTION_UP, |
sahilmgandhi | 18:6a4db94011d3 | 725 | |
sahilmgandhi | 18:6a4db94011d3 | 726 | /** Timer should count downward to zero from MAX. */ |
sahilmgandhi | 18:6a4db94011d3 | 727 | TC_COUNT_DIRECTION_DOWN, |
sahilmgandhi | 18:6a4db94011d3 | 728 | }; |
sahilmgandhi | 18:6a4db94011d3 | 729 | |
sahilmgandhi | 18:6a4db94011d3 | 730 | /** Waveform inversion mode. */ |
sahilmgandhi | 18:6a4db94011d3 | 731 | #if SAML21 || SAMC20 || SAMC21 |
sahilmgandhi | 18:6a4db94011d3 | 732 | #define TC_WAVEFORM_INVERT_CC0_MODE TC_DRVCTRL_INVEN(1) |
sahilmgandhi | 18:6a4db94011d3 | 733 | #define TC_WAVEFORM_INVERT_CC1_MODE TC_DRVCTRL_INVEN(2) |
sahilmgandhi | 18:6a4db94011d3 | 734 | #else |
sahilmgandhi | 18:6a4db94011d3 | 735 | #define TC_WAVEFORM_INVERT_CC0_MODE TC_CTRLC_INVEN(1) |
sahilmgandhi | 18:6a4db94011d3 | 736 | #define TC_WAVEFORM_INVERT_CC1_MODE TC_CTRLC_INVEN(2) |
sahilmgandhi | 18:6a4db94011d3 | 737 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 738 | |
sahilmgandhi | 18:6a4db94011d3 | 739 | /** |
sahilmgandhi | 18:6a4db94011d3 | 740 | * \brief Waveform inversion mode. |
sahilmgandhi | 18:6a4db94011d3 | 741 | * |
sahilmgandhi | 18:6a4db94011d3 | 742 | * Output waveform inversion mode. |
sahilmgandhi | 18:6a4db94011d3 | 743 | */ |
sahilmgandhi | 18:6a4db94011d3 | 744 | enum tc_waveform_invert_output { |
sahilmgandhi | 18:6a4db94011d3 | 745 | /** No inversion of the waveform output. */ |
sahilmgandhi | 18:6a4db94011d3 | 746 | TC_WAVEFORM_INVERT_OUTPUT_NONE = 0, |
sahilmgandhi | 18:6a4db94011d3 | 747 | /** Invert output from compare channel 0. */ |
sahilmgandhi | 18:6a4db94011d3 | 748 | TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE, |
sahilmgandhi | 18:6a4db94011d3 | 749 | /** Invert output from compare channel 1. */ |
sahilmgandhi | 18:6a4db94011d3 | 750 | TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE, |
sahilmgandhi | 18:6a4db94011d3 | 751 | }; |
sahilmgandhi | 18:6a4db94011d3 | 752 | |
sahilmgandhi | 18:6a4db94011d3 | 753 | /** |
sahilmgandhi | 18:6a4db94011d3 | 754 | * \brief Action to perform when the TC module is triggered by an event. |
sahilmgandhi | 18:6a4db94011d3 | 755 | * |
sahilmgandhi | 18:6a4db94011d3 | 756 | * Event action to perform when the module is triggered by an event. |
sahilmgandhi | 18:6a4db94011d3 | 757 | */ |
sahilmgandhi | 18:6a4db94011d3 | 758 | enum tc_event_action { |
sahilmgandhi | 18:6a4db94011d3 | 759 | /** No event action. */ |
sahilmgandhi | 18:6a4db94011d3 | 760 | TC_EVENT_ACTION_OFF = TC_EVCTRL_EVACT_OFF, |
sahilmgandhi | 18:6a4db94011d3 | 761 | /** Re-trigger on event. */ |
sahilmgandhi | 18:6a4db94011d3 | 762 | TC_EVENT_ACTION_RETRIGGER = TC_EVCTRL_EVACT_RETRIGGER, |
sahilmgandhi | 18:6a4db94011d3 | 763 | /** Increment counter on event. */ |
sahilmgandhi | 18:6a4db94011d3 | 764 | TC_EVENT_ACTION_INCREMENT_COUNTER = TC_EVCTRL_EVACT_COUNT, |
sahilmgandhi | 18:6a4db94011d3 | 765 | /** Start counter on event. */ |
sahilmgandhi | 18:6a4db94011d3 | 766 | TC_EVENT_ACTION_START = TC_EVCTRL_EVACT_START, |
sahilmgandhi | 18:6a4db94011d3 | 767 | |
sahilmgandhi | 18:6a4db94011d3 | 768 | /** Store period in capture register 0, pulse width in capture |
sahilmgandhi | 18:6a4db94011d3 | 769 | * register 1. |
sahilmgandhi | 18:6a4db94011d3 | 770 | */ |
sahilmgandhi | 18:6a4db94011d3 | 771 | TC_EVENT_ACTION_PPW = TC_EVCTRL_EVACT_PPW, |
sahilmgandhi | 18:6a4db94011d3 | 772 | |
sahilmgandhi | 18:6a4db94011d3 | 773 | /** Store pulse width in capture register 0, period in capture |
sahilmgandhi | 18:6a4db94011d3 | 774 | * register 1. |
sahilmgandhi | 18:6a4db94011d3 | 775 | */ |
sahilmgandhi | 18:6a4db94011d3 | 776 | TC_EVENT_ACTION_PWP = TC_EVCTRL_EVACT_PWP, |
sahilmgandhi | 18:6a4db94011d3 | 777 | #ifdef FEATURE_TC_STAMP_PW_CAPTURE |
sahilmgandhi | 18:6a4db94011d3 | 778 | /** Time stamp capture. */ |
sahilmgandhi | 18:6a4db94011d3 | 779 | TC_EVENT_ACTION_STAMP = TC_EVCTRL_EVACT_STAMP, |
sahilmgandhi | 18:6a4db94011d3 | 780 | /** Pulse width capture. */ |
sahilmgandhi | 18:6a4db94011d3 | 781 | TC_EVENT_ACTION_PW = TC_EVCTRL_EVACT_PW, |
sahilmgandhi | 18:6a4db94011d3 | 782 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 783 | }; |
sahilmgandhi | 18:6a4db94011d3 | 784 | |
sahilmgandhi | 18:6a4db94011d3 | 785 | /** |
sahilmgandhi | 18:6a4db94011d3 | 786 | * \brief TC event enable/disable structure. |
sahilmgandhi | 18:6a4db94011d3 | 787 | * |
sahilmgandhi | 18:6a4db94011d3 | 788 | * Event flags for the \ref tc_enable_events() and \ref tc_disable_events(). |
sahilmgandhi | 18:6a4db94011d3 | 789 | */ |
sahilmgandhi | 18:6a4db94011d3 | 790 | struct tc_events { |
sahilmgandhi | 18:6a4db94011d3 | 791 | /** Generate an output event on a compare channel match. */ |
sahilmgandhi | 18:6a4db94011d3 | 792 | bool generate_event_on_compare_channel |
sahilmgandhi | 18:6a4db94011d3 | 793 | [NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; |
sahilmgandhi | 18:6a4db94011d3 | 794 | /** Generate an output event on counter overflow. */ |
sahilmgandhi | 18:6a4db94011d3 | 795 | bool generate_event_on_overflow; |
sahilmgandhi | 18:6a4db94011d3 | 796 | /** Perform the configured event action when an incoming event is signalled. */ |
sahilmgandhi | 18:6a4db94011d3 | 797 | bool on_event_perform_action; |
sahilmgandhi | 18:6a4db94011d3 | 798 | /** Specifies if the input event source is inverted, when used in PWP or |
sahilmgandhi | 18:6a4db94011d3 | 799 | * PPW event action modes. |
sahilmgandhi | 18:6a4db94011d3 | 800 | */ |
sahilmgandhi | 18:6a4db94011d3 | 801 | bool invert_event_input; |
sahilmgandhi | 18:6a4db94011d3 | 802 | /** Specifies which event to trigger if an event is triggered. */ |
sahilmgandhi | 18:6a4db94011d3 | 803 | enum tc_event_action event_action; |
sahilmgandhi | 18:6a4db94011d3 | 804 | }; |
sahilmgandhi | 18:6a4db94011d3 | 805 | |
sahilmgandhi | 18:6a4db94011d3 | 806 | /** |
sahilmgandhi | 18:6a4db94011d3 | 807 | * \brief Configuration struct for TC module in 8-bit size counter mode. |
sahilmgandhi | 18:6a4db94011d3 | 808 | */ |
sahilmgandhi | 18:6a4db94011d3 | 809 | struct tc_8bit_config { |
sahilmgandhi | 18:6a4db94011d3 | 810 | /** Initial timer count value. */ |
sahilmgandhi | 18:6a4db94011d3 | 811 | uint8_t value; |
sahilmgandhi | 18:6a4db94011d3 | 812 | /** Where to count to or from depending on the direction on the counter. */ |
sahilmgandhi | 18:6a4db94011d3 | 813 | uint8_t period; |
sahilmgandhi | 18:6a4db94011d3 | 814 | /** Value to be used for compare match on each channel. */ |
sahilmgandhi | 18:6a4db94011d3 | 815 | uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; |
sahilmgandhi | 18:6a4db94011d3 | 816 | }; |
sahilmgandhi | 18:6a4db94011d3 | 817 | |
sahilmgandhi | 18:6a4db94011d3 | 818 | /** |
sahilmgandhi | 18:6a4db94011d3 | 819 | * \brief Configuration struct for TC module in 16-bit size counter mode. |
sahilmgandhi | 18:6a4db94011d3 | 820 | */ |
sahilmgandhi | 18:6a4db94011d3 | 821 | struct tc_16bit_config { |
sahilmgandhi | 18:6a4db94011d3 | 822 | /** Initial timer count value. */ |
sahilmgandhi | 18:6a4db94011d3 | 823 | uint16_t value; |
sahilmgandhi | 18:6a4db94011d3 | 824 | /** Value to be used for compare match on each channel. */ |
sahilmgandhi | 18:6a4db94011d3 | 825 | uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; |
sahilmgandhi | 18:6a4db94011d3 | 826 | }; |
sahilmgandhi | 18:6a4db94011d3 | 827 | |
sahilmgandhi | 18:6a4db94011d3 | 828 | /** |
sahilmgandhi | 18:6a4db94011d3 | 829 | * \brief Configuration struct for TC module in 32-bit size counter mode. |
sahilmgandhi | 18:6a4db94011d3 | 830 | */ |
sahilmgandhi | 18:6a4db94011d3 | 831 | struct tc_32bit_config { |
sahilmgandhi | 18:6a4db94011d3 | 832 | /** Initial timer count value. */ |
sahilmgandhi | 18:6a4db94011d3 | 833 | uint32_t value; |
sahilmgandhi | 18:6a4db94011d3 | 834 | /** Value to be used for compare match on each channel. */ |
sahilmgandhi | 18:6a4db94011d3 | 835 | uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; |
sahilmgandhi | 18:6a4db94011d3 | 836 | }; |
sahilmgandhi | 18:6a4db94011d3 | 837 | |
sahilmgandhi | 18:6a4db94011d3 | 838 | /** |
sahilmgandhi | 18:6a4db94011d3 | 839 | * \brief Configuration struct for TC module in 32-bit size counter mode. |
sahilmgandhi | 18:6a4db94011d3 | 840 | */ |
sahilmgandhi | 18:6a4db94011d3 | 841 | struct tc_pwm_channel { |
sahilmgandhi | 18:6a4db94011d3 | 842 | /** When \c true, PWM output for the given channel is enabled. */ |
sahilmgandhi | 18:6a4db94011d3 | 843 | bool enabled; |
sahilmgandhi | 18:6a4db94011d3 | 844 | /** Specifies pin output for each channel. */ |
sahilmgandhi | 18:6a4db94011d3 | 845 | uint32_t pin_out; |
sahilmgandhi | 18:6a4db94011d3 | 846 | /** Specifies MUX setting for each output channel pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 847 | uint32_t pin_mux; |
sahilmgandhi | 18:6a4db94011d3 | 848 | }; |
sahilmgandhi | 18:6a4db94011d3 | 849 | |
sahilmgandhi | 18:6a4db94011d3 | 850 | /** |
sahilmgandhi | 18:6a4db94011d3 | 851 | * \brief TC configuration structure. |
sahilmgandhi | 18:6a4db94011d3 | 852 | * |
sahilmgandhi | 18:6a4db94011d3 | 853 | * Configuration struct for a TC instance. This structure should be |
sahilmgandhi | 18:6a4db94011d3 | 854 | * initialized by the \ref tc_get_config_defaults function before being |
sahilmgandhi | 18:6a4db94011d3 | 855 | * modified by the user application. |
sahilmgandhi | 18:6a4db94011d3 | 856 | */ |
sahilmgandhi | 18:6a4db94011d3 | 857 | struct tc_config { |
sahilmgandhi | 18:6a4db94011d3 | 858 | /** GCLK generator used to clock the peripheral. */ |
sahilmgandhi | 18:6a4db94011d3 | 859 | enum gclk_generator clock_source; |
sahilmgandhi | 18:6a4db94011d3 | 860 | |
sahilmgandhi | 18:6a4db94011d3 | 861 | /** When \c true the module is enabled during standby. */ |
sahilmgandhi | 18:6a4db94011d3 | 862 | bool run_in_standby; |
sahilmgandhi | 18:6a4db94011d3 | 863 | #if (SAML21) || (SAMC20) || (SAMC21) |
sahilmgandhi | 18:6a4db94011d3 | 864 | /** Run on demand. */ |
sahilmgandhi | 18:6a4db94011d3 | 865 | bool on_demand; |
sahilmgandhi | 18:6a4db94011d3 | 866 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 867 | /** Specifies either 8-, 16-, or 32-bit counter size. */ |
sahilmgandhi | 18:6a4db94011d3 | 868 | enum tc_counter_size counter_size; |
sahilmgandhi | 18:6a4db94011d3 | 869 | /** Specifies the prescaler value for GCLK_TC. */ |
sahilmgandhi | 18:6a4db94011d3 | 870 | enum tc_clock_prescaler clock_prescaler; |
sahilmgandhi | 18:6a4db94011d3 | 871 | /** Specifies which waveform generation mode to use. */ |
sahilmgandhi | 18:6a4db94011d3 | 872 | enum tc_wave_generation wave_generation; |
sahilmgandhi | 18:6a4db94011d3 | 873 | |
sahilmgandhi | 18:6a4db94011d3 | 874 | /** Specifies the reload or reset time of the counter and prescaler |
sahilmgandhi | 18:6a4db94011d3 | 875 | * resynchronization on a re-trigger event for the TC. |
sahilmgandhi | 18:6a4db94011d3 | 876 | */ |
sahilmgandhi | 18:6a4db94011d3 | 877 | enum tc_reload_action reload_action; |
sahilmgandhi | 18:6a4db94011d3 | 878 | |
sahilmgandhi | 18:6a4db94011d3 | 879 | /** Specifies which channel(s) to invert the waveform on. |
sahilmgandhi | 18:6a4db94011d3 | 880 | For SAML21/C20/C21, it's also used to invert IO input pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 881 | uint8_t waveform_invert_output; |
sahilmgandhi | 18:6a4db94011d3 | 882 | |
sahilmgandhi | 18:6a4db94011d3 | 883 | /** Specifies which channel(s) to enable channel capture |
sahilmgandhi | 18:6a4db94011d3 | 884 | * operation on. |
sahilmgandhi | 18:6a4db94011d3 | 885 | */ |
sahilmgandhi | 18:6a4db94011d3 | 886 | bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; |
sahilmgandhi | 18:6a4db94011d3 | 887 | #ifdef FEATURE_TC_IO_CAPTURE |
sahilmgandhi | 18:6a4db94011d3 | 888 | /** Specifies which channel(s) to enable I/O capture |
sahilmgandhi | 18:6a4db94011d3 | 889 | * operation on. |
sahilmgandhi | 18:6a4db94011d3 | 890 | */ |
sahilmgandhi | 18:6a4db94011d3 | 891 | bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; |
sahilmgandhi | 18:6a4db94011d3 | 892 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 893 | |
sahilmgandhi | 18:6a4db94011d3 | 894 | /** When \c true, one-shot will stop the TC on next hardware or software |
sahilmgandhi | 18:6a4db94011d3 | 895 | * re-trigger event or overflow/underflow. |
sahilmgandhi | 18:6a4db94011d3 | 896 | */ |
sahilmgandhi | 18:6a4db94011d3 | 897 | bool oneshot; |
sahilmgandhi | 18:6a4db94011d3 | 898 | |
sahilmgandhi | 18:6a4db94011d3 | 899 | /** Specifies the direction for the TC to count. */ |
sahilmgandhi | 18:6a4db94011d3 | 900 | enum tc_count_direction count_direction; |
sahilmgandhi | 18:6a4db94011d3 | 901 | |
sahilmgandhi | 18:6a4db94011d3 | 902 | /** Specifies the PWM channel for TC. */ |
sahilmgandhi | 18:6a4db94011d3 | 903 | struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; |
sahilmgandhi | 18:6a4db94011d3 | 904 | |
sahilmgandhi | 18:6a4db94011d3 | 905 | /** Access the different counter size settings though this configuration member. */ |
sahilmgandhi | 18:6a4db94011d3 | 906 | union { |
sahilmgandhi | 18:6a4db94011d3 | 907 | /** Struct for 8-bit specific timer configuration. */ |
sahilmgandhi | 18:6a4db94011d3 | 908 | struct tc_8bit_config counter_8_bit; |
sahilmgandhi | 18:6a4db94011d3 | 909 | /** Struct for 16-bit specific timer configuration. */ |
sahilmgandhi | 18:6a4db94011d3 | 910 | struct tc_16bit_config counter_16_bit; |
sahilmgandhi | 18:6a4db94011d3 | 911 | /** Struct for 32-bit specific timer configuration. */ |
sahilmgandhi | 18:6a4db94011d3 | 912 | struct tc_32bit_config counter_32_bit; |
sahilmgandhi | 18:6a4db94011d3 | 913 | }; |
sahilmgandhi | 18:6a4db94011d3 | 914 | |
sahilmgandhi | 18:6a4db94011d3 | 915 | #ifdef FEATURE_TC_DOUBLE_BUFFERED |
sahilmgandhi | 18:6a4db94011d3 | 916 | /** Set to \c true to enable double buffering write. When enabled any write |
sahilmgandhi | 18:6a4db94011d3 | 917 | * through \ref tc_set_top_value(), \ref tc_set_compare_value() and |
sahilmgandhi | 18:6a4db94011d3 | 918 | * will direct to the buffer register as buffered |
sahilmgandhi | 18:6a4db94011d3 | 919 | * value, and the buffered value will be committed to effective register |
sahilmgandhi | 18:6a4db94011d3 | 920 | * on UPDATE condition, if update is not locked. |
sahilmgandhi | 18:6a4db94011d3 | 921 | */ |
sahilmgandhi | 18:6a4db94011d3 | 922 | bool double_buffering_enabled; |
sahilmgandhi | 18:6a4db94011d3 | 923 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 924 | }; |
sahilmgandhi | 18:6a4db94011d3 | 925 | |
sahilmgandhi | 18:6a4db94011d3 | 926 | #if TC_ASYNC == true |
sahilmgandhi | 18:6a4db94011d3 | 927 | /* Forward Declaration for the device instance. */ |
sahilmgandhi | 18:6a4db94011d3 | 928 | struct tc_module; |
sahilmgandhi | 18:6a4db94011d3 | 929 | |
sahilmgandhi | 18:6a4db94011d3 | 930 | /* Type of the callback functions. */ |
sahilmgandhi | 18:6a4db94011d3 | 931 | typedef void (*tc_callback_t)(struct tc_module *const module); |
sahilmgandhi | 18:6a4db94011d3 | 932 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 933 | |
sahilmgandhi | 18:6a4db94011d3 | 934 | /** |
sahilmgandhi | 18:6a4db94011d3 | 935 | * \brief TC software device instance structure. |
sahilmgandhi | 18:6a4db94011d3 | 936 | * |
sahilmgandhi | 18:6a4db94011d3 | 937 | * TC software instance structure, used to retain software state information |
sahilmgandhi | 18:6a4db94011d3 | 938 | * of an associated hardware module instance. |
sahilmgandhi | 18:6a4db94011d3 | 939 | * |
sahilmgandhi | 18:6a4db94011d3 | 940 | * \note The fields of this structure should not be altered by the user |
sahilmgandhi | 18:6a4db94011d3 | 941 | * application; they are reserved for module-internal use only. |
sahilmgandhi | 18:6a4db94011d3 | 942 | */ |
sahilmgandhi | 18:6a4db94011d3 | 943 | struct tc_module { |
sahilmgandhi | 18:6a4db94011d3 | 944 | #if !defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 945 | /** Hardware module pointer of the associated Timer/Counter peripheral. */ |
sahilmgandhi | 18:6a4db94011d3 | 946 | Tc *hw; |
sahilmgandhi | 18:6a4db94011d3 | 947 | |
sahilmgandhi | 18:6a4db94011d3 | 948 | /** Size of the initialized Timer/Counter module configuration. */ |
sahilmgandhi | 18:6a4db94011d3 | 949 | enum tc_counter_size counter_size; |
sahilmgandhi | 18:6a4db94011d3 | 950 | # if TC_ASYNC == true |
sahilmgandhi | 18:6a4db94011d3 | 951 | /** Array of callbacks. */ |
sahilmgandhi | 18:6a4db94011d3 | 952 | tc_callback_t callback[TC_CALLBACK_N]; |
sahilmgandhi | 18:6a4db94011d3 | 953 | /** Bit mask for callbacks registered. */ |
sahilmgandhi | 18:6a4db94011d3 | 954 | uint8_t register_callback_mask; |
sahilmgandhi | 18:6a4db94011d3 | 955 | /** Bit mask for callbacks enabled. */ |
sahilmgandhi | 18:6a4db94011d3 | 956 | uint8_t enable_callback_mask; |
sahilmgandhi | 18:6a4db94011d3 | 957 | # endif |
sahilmgandhi | 18:6a4db94011d3 | 958 | #ifdef FEATURE_TC_DOUBLE_BUFFERED |
sahilmgandhi | 18:6a4db94011d3 | 959 | /** Set to \c true to enable double buffering write. */ |
sahilmgandhi | 18:6a4db94011d3 | 960 | bool double_buffering_enabled; |
sahilmgandhi | 18:6a4db94011d3 | 961 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 962 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 963 | }; |
sahilmgandhi | 18:6a4db94011d3 | 964 | |
sahilmgandhi | 18:6a4db94011d3 | 965 | #if !defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 966 | uint8_t _tc_get_inst_index( |
sahilmgandhi | 18:6a4db94011d3 | 967 | Tc *const hw); |
sahilmgandhi | 18:6a4db94011d3 | 968 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 969 | |
sahilmgandhi | 18:6a4db94011d3 | 970 | /** |
sahilmgandhi | 18:6a4db94011d3 | 971 | * \name Driver Initialization and Configuration |
sahilmgandhi | 18:6a4db94011d3 | 972 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 973 | */ |
sahilmgandhi | 18:6a4db94011d3 | 974 | |
sahilmgandhi | 18:6a4db94011d3 | 975 | /** |
sahilmgandhi | 18:6a4db94011d3 | 976 | * \brief Determines if the hardware module(s) are currently synchronizing to |
sahilmgandhi | 18:6a4db94011d3 | 977 | *the bus. |
sahilmgandhi | 18:6a4db94011d3 | 978 | * |
sahilmgandhi | 18:6a4db94011d3 | 979 | * Checks to see if the underlying hardware peripheral module(s) are currently |
sahilmgandhi | 18:6a4db94011d3 | 980 | * synchronizing across multiple clock domains to the hardware bus. This |
sahilmgandhi | 18:6a4db94011d3 | 981 | * function can be used to delay further operations on a module until such time |
sahilmgandhi | 18:6a4db94011d3 | 982 | * that it is ready, to prevent blocking delays for synchronization in the |
sahilmgandhi | 18:6a4db94011d3 | 983 | * user application. |
sahilmgandhi | 18:6a4db94011d3 | 984 | * |
sahilmgandhi | 18:6a4db94011d3 | 985 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 986 | * |
sahilmgandhi | 18:6a4db94011d3 | 987 | * \return Synchronization status of the underlying hardware module(s). |
sahilmgandhi | 18:6a4db94011d3 | 988 | * |
sahilmgandhi | 18:6a4db94011d3 | 989 | * \retval false If the module has completed synchronization |
sahilmgandhi | 18:6a4db94011d3 | 990 | * \retval true If the module synchronization is ongoing |
sahilmgandhi | 18:6a4db94011d3 | 991 | */ |
sahilmgandhi | 18:6a4db94011d3 | 992 | static inline bool tc_is_syncing( |
sahilmgandhi | 18:6a4db94011d3 | 993 | const struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 994 | { |
sahilmgandhi | 18:6a4db94011d3 | 995 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 996 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 997 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 998 | |
sahilmgandhi | 18:6a4db94011d3 | 999 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1000 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1001 | |
sahilmgandhi | 18:6a4db94011d3 | 1002 | #if (SAML21) || (SAMC20) || (SAMC21) |
sahilmgandhi | 18:6a4db94011d3 | 1003 | return (tc_module->SYNCBUSY.reg); |
sahilmgandhi | 18:6a4db94011d3 | 1004 | #else |
sahilmgandhi | 18:6a4db94011d3 | 1005 | return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY); |
sahilmgandhi | 18:6a4db94011d3 | 1006 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1007 | } |
sahilmgandhi | 18:6a4db94011d3 | 1008 | |
sahilmgandhi | 18:6a4db94011d3 | 1009 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1010 | * \brief Initializes config with predefined default values. |
sahilmgandhi | 18:6a4db94011d3 | 1011 | * |
sahilmgandhi | 18:6a4db94011d3 | 1012 | * This function will initialize a given TC configuration structure to |
sahilmgandhi | 18:6a4db94011d3 | 1013 | * a set of known default values. This function should be called on |
sahilmgandhi | 18:6a4db94011d3 | 1014 | * any new instance of the configuration structures before being |
sahilmgandhi | 18:6a4db94011d3 | 1015 | * modified by the user application. |
sahilmgandhi | 18:6a4db94011d3 | 1016 | * |
sahilmgandhi | 18:6a4db94011d3 | 1017 | * The default configuration is as follows: |
sahilmgandhi | 18:6a4db94011d3 | 1018 | * \li GCLK generator 0 (GCLK main) clock source |
sahilmgandhi | 18:6a4db94011d3 | 1019 | * \li 16-bit counter size on the counter |
sahilmgandhi | 18:6a4db94011d3 | 1020 | * \li No prescaler |
sahilmgandhi | 18:6a4db94011d3 | 1021 | * \li Normal frequency wave generation |
sahilmgandhi | 18:6a4db94011d3 | 1022 | * \li GCLK reload action |
sahilmgandhi | 18:6a4db94011d3 | 1023 | * \li Don't run in standby |
sahilmgandhi | 18:6a4db94011d3 | 1024 | * \li Don't run on demand for SAML21/C20/C21 |
sahilmgandhi | 18:6a4db94011d3 | 1025 | * \li No inversion of waveform output |
sahilmgandhi | 18:6a4db94011d3 | 1026 | * \li No capture enabled |
sahilmgandhi | 18:6a4db94011d3 | 1027 | * \li No I/O capture enabled for SAML21/C20/C21 |
sahilmgandhi | 18:6a4db94011d3 | 1028 | * \li No event input enabled |
sahilmgandhi | 18:6a4db94011d3 | 1029 | * \li Count upward |
sahilmgandhi | 18:6a4db94011d3 | 1030 | * \li Don't perform one-shot operations |
sahilmgandhi | 18:6a4db94011d3 | 1031 | * \li No event action |
sahilmgandhi | 18:6a4db94011d3 | 1032 | * \li No channel 0 PWM output |
sahilmgandhi | 18:6a4db94011d3 | 1033 | * \li No channel 1 PWM output |
sahilmgandhi | 18:6a4db94011d3 | 1034 | * \li Counter starts on 0 |
sahilmgandhi | 18:6a4db94011d3 | 1035 | * \li Capture compare channel 0 set to 0 |
sahilmgandhi | 18:6a4db94011d3 | 1036 | * \li Capture compare channel 1 set to 0 |
sahilmgandhi | 18:6a4db94011d3 | 1037 | * \li No PWM pin output enabled |
sahilmgandhi | 18:6a4db94011d3 | 1038 | * \li Pin and MUX configuration not set |
sahilmgandhi | 18:6a4db94011d3 | 1039 | * \li Double buffer disabled (if have this feature) |
sahilmgandhi | 18:6a4db94011d3 | 1040 | * |
sahilmgandhi | 18:6a4db94011d3 | 1041 | * \param[out] config Pointer to a TC module configuration structure to set |
sahilmgandhi | 18:6a4db94011d3 | 1042 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1043 | static inline void tc_get_config_defaults( |
sahilmgandhi | 18:6a4db94011d3 | 1044 | struct tc_config *const config) |
sahilmgandhi | 18:6a4db94011d3 | 1045 | { |
sahilmgandhi | 18:6a4db94011d3 | 1046 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1047 | Assert(config); |
sahilmgandhi | 18:6a4db94011d3 | 1048 | |
sahilmgandhi | 18:6a4db94011d3 | 1049 | /* Write default config to config struct */ |
sahilmgandhi | 18:6a4db94011d3 | 1050 | config->clock_source = GCLK_GENERATOR_0; |
sahilmgandhi | 18:6a4db94011d3 | 1051 | config->counter_size = TC_COUNTER_SIZE_16BIT; |
sahilmgandhi | 18:6a4db94011d3 | 1052 | config->clock_prescaler = TC_CLOCK_PRESCALER_DIV1; |
sahilmgandhi | 18:6a4db94011d3 | 1053 | config->wave_generation = TC_WAVE_GENERATION_NORMAL_FREQ; |
sahilmgandhi | 18:6a4db94011d3 | 1054 | config->reload_action = TC_RELOAD_ACTION_GCLK; |
sahilmgandhi | 18:6a4db94011d3 | 1055 | config->run_in_standby = false; |
sahilmgandhi | 18:6a4db94011d3 | 1056 | #if (SAML21) || (SAMC20) || (SAMC21) |
sahilmgandhi | 18:6a4db94011d3 | 1057 | config->on_demand = false; |
sahilmgandhi | 18:6a4db94011d3 | 1058 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1059 | config->waveform_invert_output = TC_WAVEFORM_INVERT_OUTPUT_NONE; |
sahilmgandhi | 18:6a4db94011d3 | 1060 | config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false; |
sahilmgandhi | 18:6a4db94011d3 | 1061 | config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false; |
sahilmgandhi | 18:6a4db94011d3 | 1062 | #ifdef FEATURE_TC_IO_CAPTURE |
sahilmgandhi | 18:6a4db94011d3 | 1063 | config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false; |
sahilmgandhi | 18:6a4db94011d3 | 1064 | config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false; |
sahilmgandhi | 18:6a4db94011d3 | 1065 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1066 | |
sahilmgandhi | 18:6a4db94011d3 | 1067 | config->count_direction = TC_COUNT_DIRECTION_UP; |
sahilmgandhi | 18:6a4db94011d3 | 1068 | config->oneshot = false; |
sahilmgandhi | 18:6a4db94011d3 | 1069 | |
sahilmgandhi | 18:6a4db94011d3 | 1070 | config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false; |
sahilmgandhi | 18:6a4db94011d3 | 1071 | config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1072 | config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1073 | |
sahilmgandhi | 18:6a4db94011d3 | 1074 | config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false; |
sahilmgandhi | 18:6a4db94011d3 | 1075 | config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1076 | config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1077 | |
sahilmgandhi | 18:6a4db94011d3 | 1078 | config->counter_16_bit.value = 0x0000; |
sahilmgandhi | 18:6a4db94011d3 | 1079 | config->counter_16_bit.compare_capture_channel\ |
sahilmgandhi | 18:6a4db94011d3 | 1080 | [TC_COMPARE_CAPTURE_CHANNEL_0] = 0x0000; |
sahilmgandhi | 18:6a4db94011d3 | 1081 | config->counter_16_bit.compare_capture_channel\ |
sahilmgandhi | 18:6a4db94011d3 | 1082 | [TC_COMPARE_CAPTURE_CHANNEL_1] = 0x0000; |
sahilmgandhi | 18:6a4db94011d3 | 1083 | #ifdef FEATURE_TC_DOUBLE_BUFFERED |
sahilmgandhi | 18:6a4db94011d3 | 1084 | config->double_buffering_enabled = false; |
sahilmgandhi | 18:6a4db94011d3 | 1085 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1086 | |
sahilmgandhi | 18:6a4db94011d3 | 1087 | } |
sahilmgandhi | 18:6a4db94011d3 | 1088 | |
sahilmgandhi | 18:6a4db94011d3 | 1089 | enum status_code tc_init( |
sahilmgandhi | 18:6a4db94011d3 | 1090 | struct tc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 1091 | Tc *const hw, |
sahilmgandhi | 18:6a4db94011d3 | 1092 | const struct tc_config *const config); |
sahilmgandhi | 18:6a4db94011d3 | 1093 | |
sahilmgandhi | 18:6a4db94011d3 | 1094 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1095 | |
sahilmgandhi | 18:6a4db94011d3 | 1096 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1097 | * \name Event Management |
sahilmgandhi | 18:6a4db94011d3 | 1098 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1099 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1100 | |
sahilmgandhi | 18:6a4db94011d3 | 1101 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1102 | * \brief Enables a TC module event input or output. |
sahilmgandhi | 18:6a4db94011d3 | 1103 | * |
sahilmgandhi | 18:6a4db94011d3 | 1104 | * Enables one or more input or output events to or from the TC module. |
sahilmgandhi | 18:6a4db94011d3 | 1105 | * See \ref tc_events for a list of events this module supports. |
sahilmgandhi | 18:6a4db94011d3 | 1106 | * |
sahilmgandhi | 18:6a4db94011d3 | 1107 | * \note Events cannot be altered while the module is enabled. |
sahilmgandhi | 18:6a4db94011d3 | 1108 | * |
sahilmgandhi | 18:6a4db94011d3 | 1109 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1110 | * \param[in] events Struct containing flags of events to enable |
sahilmgandhi | 18:6a4db94011d3 | 1111 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1112 | static inline void tc_enable_events( |
sahilmgandhi | 18:6a4db94011d3 | 1113 | struct tc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 1114 | struct tc_events *const events) |
sahilmgandhi | 18:6a4db94011d3 | 1115 | { |
sahilmgandhi | 18:6a4db94011d3 | 1116 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1117 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1118 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1119 | Assert(events); |
sahilmgandhi | 18:6a4db94011d3 | 1120 | |
sahilmgandhi | 18:6a4db94011d3 | 1121 | Tc *const tc_module = module_inst->hw; |
sahilmgandhi | 18:6a4db94011d3 | 1122 | |
sahilmgandhi | 18:6a4db94011d3 | 1123 | uint32_t event_mask = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1124 | |
sahilmgandhi | 18:6a4db94011d3 | 1125 | if (events->invert_event_input == true) { |
sahilmgandhi | 18:6a4db94011d3 | 1126 | event_mask |= TC_EVCTRL_TCINV; |
sahilmgandhi | 18:6a4db94011d3 | 1127 | } |
sahilmgandhi | 18:6a4db94011d3 | 1128 | |
sahilmgandhi | 18:6a4db94011d3 | 1129 | if (events->on_event_perform_action == true) { |
sahilmgandhi | 18:6a4db94011d3 | 1130 | event_mask |= TC_EVCTRL_TCEI; |
sahilmgandhi | 18:6a4db94011d3 | 1131 | } |
sahilmgandhi | 18:6a4db94011d3 | 1132 | |
sahilmgandhi | 18:6a4db94011d3 | 1133 | if (events->generate_event_on_overflow == true) { |
sahilmgandhi | 18:6a4db94011d3 | 1134 | event_mask |= TC_EVCTRL_OVFEO; |
sahilmgandhi | 18:6a4db94011d3 | 1135 | } |
sahilmgandhi | 18:6a4db94011d3 | 1136 | |
sahilmgandhi | 18:6a4db94011d3 | 1137 | for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { |
sahilmgandhi | 18:6a4db94011d3 | 1138 | if (events->generate_event_on_compare_channel[i] == true) { |
sahilmgandhi | 18:6a4db94011d3 | 1139 | event_mask |= (TC_EVCTRL_MCEO(1) << i); |
sahilmgandhi | 18:6a4db94011d3 | 1140 | } |
sahilmgandhi | 18:6a4db94011d3 | 1141 | } |
sahilmgandhi | 18:6a4db94011d3 | 1142 | |
sahilmgandhi | 18:6a4db94011d3 | 1143 | tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action; |
sahilmgandhi | 18:6a4db94011d3 | 1144 | } |
sahilmgandhi | 18:6a4db94011d3 | 1145 | |
sahilmgandhi | 18:6a4db94011d3 | 1146 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1147 | * \brief Disables a TC module event input or output. |
sahilmgandhi | 18:6a4db94011d3 | 1148 | * |
sahilmgandhi | 18:6a4db94011d3 | 1149 | * Disables one or more input or output events to or from the TC module. |
sahilmgandhi | 18:6a4db94011d3 | 1150 | * See \ref tc_events for a list of events this module supports. |
sahilmgandhi | 18:6a4db94011d3 | 1151 | * |
sahilmgandhi | 18:6a4db94011d3 | 1152 | * \note Events cannot be altered while the module is enabled. |
sahilmgandhi | 18:6a4db94011d3 | 1153 | * |
sahilmgandhi | 18:6a4db94011d3 | 1154 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1155 | * \param[in] events Struct containing flags of events to disable |
sahilmgandhi | 18:6a4db94011d3 | 1156 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1157 | static inline void tc_disable_events( |
sahilmgandhi | 18:6a4db94011d3 | 1158 | struct tc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 1159 | struct tc_events *const events) |
sahilmgandhi | 18:6a4db94011d3 | 1160 | { |
sahilmgandhi | 18:6a4db94011d3 | 1161 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1162 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1163 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1164 | Assert(events); |
sahilmgandhi | 18:6a4db94011d3 | 1165 | |
sahilmgandhi | 18:6a4db94011d3 | 1166 | Tc *const tc_module = module_inst->hw; |
sahilmgandhi | 18:6a4db94011d3 | 1167 | |
sahilmgandhi | 18:6a4db94011d3 | 1168 | uint32_t event_mask = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1169 | |
sahilmgandhi | 18:6a4db94011d3 | 1170 | if (events->invert_event_input == true) { |
sahilmgandhi | 18:6a4db94011d3 | 1171 | event_mask |= TC_EVCTRL_TCINV; |
sahilmgandhi | 18:6a4db94011d3 | 1172 | } |
sahilmgandhi | 18:6a4db94011d3 | 1173 | |
sahilmgandhi | 18:6a4db94011d3 | 1174 | if (events->on_event_perform_action == true) { |
sahilmgandhi | 18:6a4db94011d3 | 1175 | event_mask |= TC_EVCTRL_TCEI; |
sahilmgandhi | 18:6a4db94011d3 | 1176 | } |
sahilmgandhi | 18:6a4db94011d3 | 1177 | |
sahilmgandhi | 18:6a4db94011d3 | 1178 | if (events->generate_event_on_overflow == true) { |
sahilmgandhi | 18:6a4db94011d3 | 1179 | event_mask |= TC_EVCTRL_OVFEO; |
sahilmgandhi | 18:6a4db94011d3 | 1180 | } |
sahilmgandhi | 18:6a4db94011d3 | 1181 | |
sahilmgandhi | 18:6a4db94011d3 | 1182 | for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { |
sahilmgandhi | 18:6a4db94011d3 | 1183 | if (events->generate_event_on_compare_channel[i] == true) { |
sahilmgandhi | 18:6a4db94011d3 | 1184 | event_mask |= (TC_EVCTRL_MCEO(1) << i); |
sahilmgandhi | 18:6a4db94011d3 | 1185 | } |
sahilmgandhi | 18:6a4db94011d3 | 1186 | } |
sahilmgandhi | 18:6a4db94011d3 | 1187 | |
sahilmgandhi | 18:6a4db94011d3 | 1188 | tc_module->COUNT8.EVCTRL.reg &= ~event_mask; |
sahilmgandhi | 18:6a4db94011d3 | 1189 | } |
sahilmgandhi | 18:6a4db94011d3 | 1190 | |
sahilmgandhi | 18:6a4db94011d3 | 1191 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1192 | |
sahilmgandhi | 18:6a4db94011d3 | 1193 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1194 | * \name Enable/Disable/Reset |
sahilmgandhi | 18:6a4db94011d3 | 1195 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1196 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1197 | |
sahilmgandhi | 18:6a4db94011d3 | 1198 | enum status_code tc_reset( |
sahilmgandhi | 18:6a4db94011d3 | 1199 | const struct tc_module *const module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1200 | |
sahilmgandhi | 18:6a4db94011d3 | 1201 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1202 | * \brief Enable the TC module. |
sahilmgandhi | 18:6a4db94011d3 | 1203 | * |
sahilmgandhi | 18:6a4db94011d3 | 1204 | * Enables a TC module that has been previously initialized. The counter will |
sahilmgandhi | 18:6a4db94011d3 | 1205 | * start when the counter is enabled. |
sahilmgandhi | 18:6a4db94011d3 | 1206 | * |
sahilmgandhi | 18:6a4db94011d3 | 1207 | * \note When the counter is configured to re-trigger on an event, the counter |
sahilmgandhi | 18:6a4db94011d3 | 1208 | * will not start until the start function is used. |
sahilmgandhi | 18:6a4db94011d3 | 1209 | * |
sahilmgandhi | 18:6a4db94011d3 | 1210 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1211 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1212 | static inline void tc_enable( |
sahilmgandhi | 18:6a4db94011d3 | 1213 | const struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 1214 | { |
sahilmgandhi | 18:6a4db94011d3 | 1215 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1216 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1217 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1218 | |
sahilmgandhi | 18:6a4db94011d3 | 1219 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1220 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1221 | |
sahilmgandhi | 18:6a4db94011d3 | 1222 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1223 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1224 | } |
sahilmgandhi | 18:6a4db94011d3 | 1225 | |
sahilmgandhi | 18:6a4db94011d3 | 1226 | /* Enable TC module */ |
sahilmgandhi | 18:6a4db94011d3 | 1227 | tc_module->CTRLA.reg |= TC_CTRLA_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 1228 | } |
sahilmgandhi | 18:6a4db94011d3 | 1229 | |
sahilmgandhi | 18:6a4db94011d3 | 1230 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1231 | * \brief Disables the TC module. |
sahilmgandhi | 18:6a4db94011d3 | 1232 | * |
sahilmgandhi | 18:6a4db94011d3 | 1233 | * Disables a TC module and stops the counter. |
sahilmgandhi | 18:6a4db94011d3 | 1234 | * |
sahilmgandhi | 18:6a4db94011d3 | 1235 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1236 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1237 | static inline void tc_disable( |
sahilmgandhi | 18:6a4db94011d3 | 1238 | const struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 1239 | { |
sahilmgandhi | 18:6a4db94011d3 | 1240 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1241 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1242 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1243 | |
sahilmgandhi | 18:6a4db94011d3 | 1244 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1245 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1246 | |
sahilmgandhi | 18:6a4db94011d3 | 1247 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1248 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1249 | } |
sahilmgandhi | 18:6a4db94011d3 | 1250 | |
sahilmgandhi | 18:6a4db94011d3 | 1251 | /* Disable TC module */ |
sahilmgandhi | 18:6a4db94011d3 | 1252 | tc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; |
sahilmgandhi | 18:6a4db94011d3 | 1253 | } |
sahilmgandhi | 18:6a4db94011d3 | 1254 | |
sahilmgandhi | 18:6a4db94011d3 | 1255 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1256 | |
sahilmgandhi | 18:6a4db94011d3 | 1257 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1258 | * \name Get/Set Count Value |
sahilmgandhi | 18:6a4db94011d3 | 1259 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1260 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1261 | |
sahilmgandhi | 18:6a4db94011d3 | 1262 | uint32_t tc_get_count_value( |
sahilmgandhi | 18:6a4db94011d3 | 1263 | const struct tc_module *const module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1264 | |
sahilmgandhi | 18:6a4db94011d3 | 1265 | enum status_code tc_set_count_value( |
sahilmgandhi | 18:6a4db94011d3 | 1266 | const struct tc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 1267 | const uint32_t count); |
sahilmgandhi | 18:6a4db94011d3 | 1268 | |
sahilmgandhi | 18:6a4db94011d3 | 1269 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1270 | |
sahilmgandhi | 18:6a4db94011d3 | 1271 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1272 | * \name Start/Stop Counter |
sahilmgandhi | 18:6a4db94011d3 | 1273 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1274 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1275 | |
sahilmgandhi | 18:6a4db94011d3 | 1276 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1277 | * \brief Stops the counter. |
sahilmgandhi | 18:6a4db94011d3 | 1278 | * |
sahilmgandhi | 18:6a4db94011d3 | 1279 | * This function will stop the counter. When the counter is stopped |
sahilmgandhi | 18:6a4db94011d3 | 1280 | * the value in the count value is set to 0 if the counter was |
sahilmgandhi | 18:6a4db94011d3 | 1281 | * counting up, or maximum if the counter was counting |
sahilmgandhi | 18:6a4db94011d3 | 1282 | * down when stopped. |
sahilmgandhi | 18:6a4db94011d3 | 1283 | * |
sahilmgandhi | 18:6a4db94011d3 | 1284 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1285 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1286 | static inline void tc_stop_counter( |
sahilmgandhi | 18:6a4db94011d3 | 1287 | const struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 1288 | { |
sahilmgandhi | 18:6a4db94011d3 | 1289 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1290 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1291 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1292 | |
sahilmgandhi | 18:6a4db94011d3 | 1293 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1294 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1295 | |
sahilmgandhi | 18:6a4db94011d3 | 1296 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1297 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1298 | } |
sahilmgandhi | 18:6a4db94011d3 | 1299 | |
sahilmgandhi | 18:6a4db94011d3 | 1300 | /* Write command to execute */ |
sahilmgandhi | 18:6a4db94011d3 | 1301 | tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_STOP_Val); |
sahilmgandhi | 18:6a4db94011d3 | 1302 | } |
sahilmgandhi | 18:6a4db94011d3 | 1303 | |
sahilmgandhi | 18:6a4db94011d3 | 1304 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1305 | * \brief Starts the counter. |
sahilmgandhi | 18:6a4db94011d3 | 1306 | * |
sahilmgandhi | 18:6a4db94011d3 | 1307 | * Starts or restarts an initialized TC module's counter. |
sahilmgandhi | 18:6a4db94011d3 | 1308 | * |
sahilmgandhi | 18:6a4db94011d3 | 1309 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1310 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1311 | static inline void tc_start_counter( |
sahilmgandhi | 18:6a4db94011d3 | 1312 | const struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 1313 | { |
sahilmgandhi | 18:6a4db94011d3 | 1314 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1315 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1316 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1317 | |
sahilmgandhi | 18:6a4db94011d3 | 1318 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1319 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1320 | |
sahilmgandhi | 18:6a4db94011d3 | 1321 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1322 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1323 | } |
sahilmgandhi | 18:6a4db94011d3 | 1324 | |
sahilmgandhi | 18:6a4db94011d3 | 1325 | /* Make certain that there are no conflicting commands in the register */ |
sahilmgandhi | 18:6a4db94011d3 | 1326 | tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; |
sahilmgandhi | 18:6a4db94011d3 | 1327 | |
sahilmgandhi | 18:6a4db94011d3 | 1328 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1329 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1330 | } |
sahilmgandhi | 18:6a4db94011d3 | 1331 | |
sahilmgandhi | 18:6a4db94011d3 | 1332 | /* Write command to execute */ |
sahilmgandhi | 18:6a4db94011d3 | 1333 | tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_RETRIGGER_Val); |
sahilmgandhi | 18:6a4db94011d3 | 1334 | } |
sahilmgandhi | 18:6a4db94011d3 | 1335 | |
sahilmgandhi | 18:6a4db94011d3 | 1336 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1337 | |
sahilmgandhi | 18:6a4db94011d3 | 1338 | #ifdef FEATURE_TC_DOUBLE_BUFFERED |
sahilmgandhi | 18:6a4db94011d3 | 1339 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1340 | * \name Double Buffering |
sahilmgandhi | 18:6a4db94011d3 | 1341 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1342 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1343 | |
sahilmgandhi | 18:6a4db94011d3 | 1344 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1345 | * \brief Update double buffer. |
sahilmgandhi | 18:6a4db94011d3 | 1346 | * |
sahilmgandhi | 18:6a4db94011d3 | 1347 | * Update double buffer. |
sahilmgandhi | 18:6a4db94011d3 | 1348 | * |
sahilmgandhi | 18:6a4db94011d3 | 1349 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1350 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1351 | static inline void tc_update_double_buffer( |
sahilmgandhi | 18:6a4db94011d3 | 1352 | const struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 1353 | { |
sahilmgandhi | 18:6a4db94011d3 | 1354 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1355 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1356 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1357 | |
sahilmgandhi | 18:6a4db94011d3 | 1358 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1359 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1360 | |
sahilmgandhi | 18:6a4db94011d3 | 1361 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1362 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1363 | } |
sahilmgandhi | 18:6a4db94011d3 | 1364 | |
sahilmgandhi | 18:6a4db94011d3 | 1365 | /* Make certain that there are no conflicting commands in the register */ |
sahilmgandhi | 18:6a4db94011d3 | 1366 | tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; |
sahilmgandhi | 18:6a4db94011d3 | 1367 | |
sahilmgandhi | 18:6a4db94011d3 | 1368 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1369 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1370 | } |
sahilmgandhi | 18:6a4db94011d3 | 1371 | |
sahilmgandhi | 18:6a4db94011d3 | 1372 | /* Write command to execute */ |
sahilmgandhi | 18:6a4db94011d3 | 1373 | tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_UPDATE_Val); |
sahilmgandhi | 18:6a4db94011d3 | 1374 | } |
sahilmgandhi | 18:6a4db94011d3 | 1375 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1376 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1377 | |
sahilmgandhi | 18:6a4db94011d3 | 1378 | #ifdef FEATURE_TC_READ_SYNC |
sahilmgandhi | 18:6a4db94011d3 | 1379 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1380 | * \name Count Read Synchronization |
sahilmgandhi | 18:6a4db94011d3 | 1381 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1382 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1383 | |
sahilmgandhi | 18:6a4db94011d3 | 1384 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1385 | * \brief Read synchronization of COUNT. |
sahilmgandhi | 18:6a4db94011d3 | 1386 | * |
sahilmgandhi | 18:6a4db94011d3 | 1387 | * Read synchronization of COUNT. |
sahilmgandhi | 18:6a4db94011d3 | 1388 | * |
sahilmgandhi | 18:6a4db94011d3 | 1389 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1390 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1391 | static inline void tc_sync_read_count( |
sahilmgandhi | 18:6a4db94011d3 | 1392 | const struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 1393 | { |
sahilmgandhi | 18:6a4db94011d3 | 1394 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1395 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1396 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1397 | |
sahilmgandhi | 18:6a4db94011d3 | 1398 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1399 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1400 | |
sahilmgandhi | 18:6a4db94011d3 | 1401 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1402 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1403 | } |
sahilmgandhi | 18:6a4db94011d3 | 1404 | |
sahilmgandhi | 18:6a4db94011d3 | 1405 | /* Make certain that there are no conflicting commands in the register */ |
sahilmgandhi | 18:6a4db94011d3 | 1406 | tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; |
sahilmgandhi | 18:6a4db94011d3 | 1407 | |
sahilmgandhi | 18:6a4db94011d3 | 1408 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1409 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1410 | } |
sahilmgandhi | 18:6a4db94011d3 | 1411 | |
sahilmgandhi | 18:6a4db94011d3 | 1412 | /* Write command to execute */ |
sahilmgandhi | 18:6a4db94011d3 | 1413 | tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_READSYNC_Val); |
sahilmgandhi | 18:6a4db94011d3 | 1414 | } |
sahilmgandhi | 18:6a4db94011d3 | 1415 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1416 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1417 | |
sahilmgandhi | 18:6a4db94011d3 | 1418 | #ifdef FEATURE_TC_GENERATE_DMA_TRIGGER |
sahilmgandhi | 18:6a4db94011d3 | 1419 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1420 | * \name Generate TC DMA Triggers command |
sahilmgandhi | 18:6a4db94011d3 | 1421 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1422 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1423 | |
sahilmgandhi | 18:6a4db94011d3 | 1424 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1425 | * \brief TC DMA Trigger. |
sahilmgandhi | 18:6a4db94011d3 | 1426 | * |
sahilmgandhi | 18:6a4db94011d3 | 1427 | * TC DMA trigger command. |
sahilmgandhi | 18:6a4db94011d3 | 1428 | * |
sahilmgandhi | 18:6a4db94011d3 | 1429 | * \param[in] module_inst Pointer to the software module instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1430 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1431 | static inline void tc_dma_trigger_command( |
sahilmgandhi | 18:6a4db94011d3 | 1432 | const struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 1433 | { |
sahilmgandhi | 18:6a4db94011d3 | 1434 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1435 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1436 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1437 | |
sahilmgandhi | 18:6a4db94011d3 | 1438 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1439 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1440 | |
sahilmgandhi | 18:6a4db94011d3 | 1441 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1442 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1443 | } |
sahilmgandhi | 18:6a4db94011d3 | 1444 | |
sahilmgandhi | 18:6a4db94011d3 | 1445 | /* Make certain that there are no conflicting commands in the register */ |
sahilmgandhi | 18:6a4db94011d3 | 1446 | tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; |
sahilmgandhi | 18:6a4db94011d3 | 1447 | |
sahilmgandhi | 18:6a4db94011d3 | 1448 | while (tc_is_syncing(module_inst)) { |
sahilmgandhi | 18:6a4db94011d3 | 1449 | /* Wait for sync */ |
sahilmgandhi | 18:6a4db94011d3 | 1450 | } |
sahilmgandhi | 18:6a4db94011d3 | 1451 | |
sahilmgandhi | 18:6a4db94011d3 | 1452 | #if SAML21 |
sahilmgandhi | 18:6a4db94011d3 | 1453 | /* Write command to execute */ |
sahilmgandhi | 18:6a4db94011d3 | 1454 | tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_DMATRG_Val); |
sahilmgandhi | 18:6a4db94011d3 | 1455 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1456 | #if (SAMC20) || (SAMC21) |
sahilmgandhi | 18:6a4db94011d3 | 1457 | /* Write command to execute */ |
sahilmgandhi | 18:6a4db94011d3 | 1458 | tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_DMAOS_Val); |
sahilmgandhi | 18:6a4db94011d3 | 1459 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1460 | } |
sahilmgandhi | 18:6a4db94011d3 | 1461 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1462 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1463 | |
sahilmgandhi | 18:6a4db94011d3 | 1464 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1465 | * \name Get Capture Set Compare |
sahilmgandhi | 18:6a4db94011d3 | 1466 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1467 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1468 | |
sahilmgandhi | 18:6a4db94011d3 | 1469 | uint32_t tc_get_capture_value( |
sahilmgandhi | 18:6a4db94011d3 | 1470 | const struct tc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 1471 | const enum tc_compare_capture_channel channel_index); |
sahilmgandhi | 18:6a4db94011d3 | 1472 | |
sahilmgandhi | 18:6a4db94011d3 | 1473 | enum status_code tc_set_compare_value( |
sahilmgandhi | 18:6a4db94011d3 | 1474 | const struct tc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 1475 | const enum tc_compare_capture_channel channel_index, |
sahilmgandhi | 18:6a4db94011d3 | 1476 | const uint32_t compare_value); |
sahilmgandhi | 18:6a4db94011d3 | 1477 | |
sahilmgandhi | 18:6a4db94011d3 | 1478 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1479 | |
sahilmgandhi | 18:6a4db94011d3 | 1480 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1481 | * \name Set Top Value |
sahilmgandhi | 18:6a4db94011d3 | 1482 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1483 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1484 | |
sahilmgandhi | 18:6a4db94011d3 | 1485 | enum status_code tc_set_top_value( |
sahilmgandhi | 18:6a4db94011d3 | 1486 | const struct tc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 1487 | const uint32_t top_value); |
sahilmgandhi | 18:6a4db94011d3 | 1488 | |
sahilmgandhi | 18:6a4db94011d3 | 1489 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1490 | |
sahilmgandhi | 18:6a4db94011d3 | 1491 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1492 | * \name Status Management |
sahilmgandhi | 18:6a4db94011d3 | 1493 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 1494 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1495 | |
sahilmgandhi | 18:6a4db94011d3 | 1496 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1497 | * \brief Retrieves the current module status. |
sahilmgandhi | 18:6a4db94011d3 | 1498 | * |
sahilmgandhi | 18:6a4db94011d3 | 1499 | * Retrieves the status of the module, giving overall state information. |
sahilmgandhi | 18:6a4db94011d3 | 1500 | * |
sahilmgandhi | 18:6a4db94011d3 | 1501 | * \param[in] module_inst Pointer to the TC software instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1502 | * |
sahilmgandhi | 18:6a4db94011d3 | 1503 | * \return Bitmask of \c TC_STATUS_* flags. |
sahilmgandhi | 18:6a4db94011d3 | 1504 | * |
sahilmgandhi | 18:6a4db94011d3 | 1505 | * \retval TC_STATUS_CHANNEL_0_MATCH Timer channel 0 compare/capture match |
sahilmgandhi | 18:6a4db94011d3 | 1506 | * \retval TC_STATUS_CHANNEL_1_MATCH Timer channel 1 compare/capture match |
sahilmgandhi | 18:6a4db94011d3 | 1507 | * \retval TC_STATUS_SYNC_READY Timer read synchronization has completed |
sahilmgandhi | 18:6a4db94011d3 | 1508 | * \retval TC_STATUS_CAPTURE_OVERFLOW Timer capture data has overflowed |
sahilmgandhi | 18:6a4db94011d3 | 1509 | * \retval TC_STATUS_COUNT_OVERFLOW Timer count value has overflowed |
sahilmgandhi | 18:6a4db94011d3 | 1510 | * \retval TC_STATUS_CHN0_BUFFER_VALID Timer count channel 0 compare/capture buffer valid |
sahilmgandhi | 18:6a4db94011d3 | 1511 | * \retval TC_STATUS_CHN1_BUFFER_VALID Timer count channel 1 compare/capture buffer valid |
sahilmgandhi | 18:6a4db94011d3 | 1512 | * \retval TC_STATUS_PERIOD_BUFFER_VALID Timer count period buffer valid |
sahilmgandhi | 18:6a4db94011d3 | 1513 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1514 | static inline uint32_t tc_get_status( |
sahilmgandhi | 18:6a4db94011d3 | 1515 | struct tc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 1516 | { |
sahilmgandhi | 18:6a4db94011d3 | 1517 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1518 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1519 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1520 | |
sahilmgandhi | 18:6a4db94011d3 | 1521 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1522 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1523 | |
sahilmgandhi | 18:6a4db94011d3 | 1524 | uint32_t int_flags = tc_module->INTFLAG.reg; |
sahilmgandhi | 18:6a4db94011d3 | 1525 | |
sahilmgandhi | 18:6a4db94011d3 | 1526 | uint32_t status_flags = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1527 | |
sahilmgandhi | 18:6a4db94011d3 | 1528 | /* Check for TC channel 0 match */ |
sahilmgandhi | 18:6a4db94011d3 | 1529 | if (int_flags & TC_INTFLAG_MC(1)) { |
sahilmgandhi | 18:6a4db94011d3 | 1530 | status_flags |= TC_STATUS_CHANNEL_0_MATCH; |
sahilmgandhi | 18:6a4db94011d3 | 1531 | } |
sahilmgandhi | 18:6a4db94011d3 | 1532 | |
sahilmgandhi | 18:6a4db94011d3 | 1533 | /* Check for TC channel 1 match */ |
sahilmgandhi | 18:6a4db94011d3 | 1534 | if (int_flags & TC_INTFLAG_MC(2)) { |
sahilmgandhi | 18:6a4db94011d3 | 1535 | status_flags |= TC_STATUS_CHANNEL_1_MATCH; |
sahilmgandhi | 18:6a4db94011d3 | 1536 | } |
sahilmgandhi | 18:6a4db94011d3 | 1537 | |
sahilmgandhi | 18:6a4db94011d3 | 1538 | #if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2) |
sahilmgandhi | 18:6a4db94011d3 | 1539 | /* Check for TC read synchronization ready */ |
sahilmgandhi | 18:6a4db94011d3 | 1540 | if (int_flags & TC_INTFLAG_SYNCRDY) { |
sahilmgandhi | 18:6a4db94011d3 | 1541 | status_flags |= TC_STATUS_SYNC_READY; |
sahilmgandhi | 18:6a4db94011d3 | 1542 | } |
sahilmgandhi | 18:6a4db94011d3 | 1543 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1544 | |
sahilmgandhi | 18:6a4db94011d3 | 1545 | /* Check for TC capture overflow */ |
sahilmgandhi | 18:6a4db94011d3 | 1546 | if (int_flags & TC_INTFLAG_ERR) { |
sahilmgandhi | 18:6a4db94011d3 | 1547 | status_flags |= TC_STATUS_CAPTURE_OVERFLOW; |
sahilmgandhi | 18:6a4db94011d3 | 1548 | } |
sahilmgandhi | 18:6a4db94011d3 | 1549 | |
sahilmgandhi | 18:6a4db94011d3 | 1550 | /* Check for TC count overflow */ |
sahilmgandhi | 18:6a4db94011d3 | 1551 | if (int_flags & TC_INTFLAG_OVF) { |
sahilmgandhi | 18:6a4db94011d3 | 1552 | status_flags |= TC_STATUS_COUNT_OVERFLOW; |
sahilmgandhi | 18:6a4db94011d3 | 1553 | } |
sahilmgandhi | 18:6a4db94011d3 | 1554 | #ifdef FEATURE_TC_DOUBLE_BUFFERED |
sahilmgandhi | 18:6a4db94011d3 | 1555 | uint8_t double_buffer_valid_status = tc_module->STATUS.reg; |
sahilmgandhi | 18:6a4db94011d3 | 1556 | |
sahilmgandhi | 18:6a4db94011d3 | 1557 | /* Check channel 0 compare or capture buffer valid */ |
sahilmgandhi | 18:6a4db94011d3 | 1558 | if (double_buffer_valid_status & TC_STATUS_CCBUFV0) { |
sahilmgandhi | 18:6a4db94011d3 | 1559 | status_flags |= TC_STATUS_CHN0_BUFFER_VALID; |
sahilmgandhi | 18:6a4db94011d3 | 1560 | } |
sahilmgandhi | 18:6a4db94011d3 | 1561 | /* Check channel 0 compare or capture buffer valid */ |
sahilmgandhi | 18:6a4db94011d3 | 1562 | if (double_buffer_valid_status & TC_STATUS_CCBUFV1) { |
sahilmgandhi | 18:6a4db94011d3 | 1563 | status_flags |= TC_STATUS_CHN1_BUFFER_VALID; |
sahilmgandhi | 18:6a4db94011d3 | 1564 | } |
sahilmgandhi | 18:6a4db94011d3 | 1565 | /* Check period buffer valid */ |
sahilmgandhi | 18:6a4db94011d3 | 1566 | if (double_buffer_valid_status & TC_STATUS_PERBUFV) { |
sahilmgandhi | 18:6a4db94011d3 | 1567 | status_flags |= TC_STATUS_PERIOD_BUFFER_VALID; |
sahilmgandhi | 18:6a4db94011d3 | 1568 | } |
sahilmgandhi | 18:6a4db94011d3 | 1569 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1570 | |
sahilmgandhi | 18:6a4db94011d3 | 1571 | return status_flags; |
sahilmgandhi | 18:6a4db94011d3 | 1572 | } |
sahilmgandhi | 18:6a4db94011d3 | 1573 | |
sahilmgandhi | 18:6a4db94011d3 | 1574 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1575 | * \brief Clears a module status flag. |
sahilmgandhi | 18:6a4db94011d3 | 1576 | * |
sahilmgandhi | 18:6a4db94011d3 | 1577 | * Clears the given status flag of the module. |
sahilmgandhi | 18:6a4db94011d3 | 1578 | * |
sahilmgandhi | 18:6a4db94011d3 | 1579 | * \param[in] module_inst Pointer to the TC software instance struct |
sahilmgandhi | 18:6a4db94011d3 | 1580 | * \param[in] status_flags Bitmask of \c TC_STATUS_* flags to clear |
sahilmgandhi | 18:6a4db94011d3 | 1581 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1582 | static inline void tc_clear_status( |
sahilmgandhi | 18:6a4db94011d3 | 1583 | struct tc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 1584 | const uint32_t status_flags) |
sahilmgandhi | 18:6a4db94011d3 | 1585 | { |
sahilmgandhi | 18:6a4db94011d3 | 1586 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 1587 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 1588 | Assert(module_inst->hw); |
sahilmgandhi | 18:6a4db94011d3 | 1589 | |
sahilmgandhi | 18:6a4db94011d3 | 1590 | /* Get a pointer to the module's hardware instance */ |
sahilmgandhi | 18:6a4db94011d3 | 1591 | TcCount8 *const tc_module = &(module_inst->hw->COUNT8); |
sahilmgandhi | 18:6a4db94011d3 | 1592 | |
sahilmgandhi | 18:6a4db94011d3 | 1593 | uint32_t int_flags = 0; |
sahilmgandhi | 18:6a4db94011d3 | 1594 | |
sahilmgandhi | 18:6a4db94011d3 | 1595 | /* Check for TC channel 0 match */ |
sahilmgandhi | 18:6a4db94011d3 | 1596 | if (status_flags & TC_STATUS_CHANNEL_0_MATCH) { |
sahilmgandhi | 18:6a4db94011d3 | 1597 | int_flags |= TC_INTFLAG_MC(1); |
sahilmgandhi | 18:6a4db94011d3 | 1598 | } |
sahilmgandhi | 18:6a4db94011d3 | 1599 | |
sahilmgandhi | 18:6a4db94011d3 | 1600 | /* Check for TC channel 1 match */ |
sahilmgandhi | 18:6a4db94011d3 | 1601 | if (status_flags & TC_STATUS_CHANNEL_1_MATCH) { |
sahilmgandhi | 18:6a4db94011d3 | 1602 | int_flags |= TC_INTFLAG_MC(2); |
sahilmgandhi | 18:6a4db94011d3 | 1603 | } |
sahilmgandhi | 18:6a4db94011d3 | 1604 | |
sahilmgandhi | 18:6a4db94011d3 | 1605 | #if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2) |
sahilmgandhi | 18:6a4db94011d3 | 1606 | /* Check for TC read synchronization ready */ |
sahilmgandhi | 18:6a4db94011d3 | 1607 | if (status_flags & TC_STATUS_SYNC_READY) { |
sahilmgandhi | 18:6a4db94011d3 | 1608 | int_flags |= TC_INTFLAG_SYNCRDY; |
sahilmgandhi | 18:6a4db94011d3 | 1609 | } |
sahilmgandhi | 18:6a4db94011d3 | 1610 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1611 | |
sahilmgandhi | 18:6a4db94011d3 | 1612 | /* Check for TC capture overflow */ |
sahilmgandhi | 18:6a4db94011d3 | 1613 | if (status_flags & TC_STATUS_CAPTURE_OVERFLOW) { |
sahilmgandhi | 18:6a4db94011d3 | 1614 | int_flags |= TC_INTFLAG_ERR; |
sahilmgandhi | 18:6a4db94011d3 | 1615 | } |
sahilmgandhi | 18:6a4db94011d3 | 1616 | |
sahilmgandhi | 18:6a4db94011d3 | 1617 | /* Check for TC count overflow */ |
sahilmgandhi | 18:6a4db94011d3 | 1618 | if (status_flags & TC_STATUS_COUNT_OVERFLOW) { |
sahilmgandhi | 18:6a4db94011d3 | 1619 | int_flags |= TC_INTFLAG_OVF; |
sahilmgandhi | 18:6a4db94011d3 | 1620 | } |
sahilmgandhi | 18:6a4db94011d3 | 1621 | |
sahilmgandhi | 18:6a4db94011d3 | 1622 | /* Clear interrupt flag */ |
sahilmgandhi | 18:6a4db94011d3 | 1623 | tc_module->INTFLAG.reg = int_flags; |
sahilmgandhi | 18:6a4db94011d3 | 1624 | } |
sahilmgandhi | 18:6a4db94011d3 | 1625 | |
sahilmgandhi | 18:6a4db94011d3 | 1626 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1627 | |
sahilmgandhi | 18:6a4db94011d3 | 1628 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 1629 | |
sahilmgandhi | 18:6a4db94011d3 | 1630 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 1631 | } |
sahilmgandhi | 18:6a4db94011d3 | 1632 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 1633 | |
sahilmgandhi | 18:6a4db94011d3 | 1634 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1635 | * \page asfdoc_sam0_tc_extra Extra Information for TC Driver |
sahilmgandhi | 18:6a4db94011d3 | 1636 | * |
sahilmgandhi | 18:6a4db94011d3 | 1637 | * \section asfdoc_sam0_tc_extra_acronyms Acronyms |
sahilmgandhi | 18:6a4db94011d3 | 1638 | * The table below presents the acronyms used in this module: |
sahilmgandhi | 18:6a4db94011d3 | 1639 | * |
sahilmgandhi | 18:6a4db94011d3 | 1640 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 1641 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1642 | * <th>Acronym</th> |
sahilmgandhi | 18:6a4db94011d3 | 1643 | * <th>Description</th> |
sahilmgandhi | 18:6a4db94011d3 | 1644 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1645 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1646 | * <td>DMA</td> |
sahilmgandhi | 18:6a4db94011d3 | 1647 | * <td>Direct Memory Access</td> |
sahilmgandhi | 18:6a4db94011d3 | 1648 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1649 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1650 | * <td>TC</td> |
sahilmgandhi | 18:6a4db94011d3 | 1651 | * <td>Timer Counter</td> |
sahilmgandhi | 18:6a4db94011d3 | 1652 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1653 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1654 | * <td>PWM</td> |
sahilmgandhi | 18:6a4db94011d3 | 1655 | * <td>Pulse Width Modulation</td> |
sahilmgandhi | 18:6a4db94011d3 | 1656 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1657 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1658 | * <td>PWP</td> |
sahilmgandhi | 18:6a4db94011d3 | 1659 | * <td>Pulse Width Period</td> |
sahilmgandhi | 18:6a4db94011d3 | 1660 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1661 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1662 | * <td>PPW</td> |
sahilmgandhi | 18:6a4db94011d3 | 1663 | * <td>Period Pulse Width</td> |
sahilmgandhi | 18:6a4db94011d3 | 1664 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1665 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 1666 | * |
sahilmgandhi | 18:6a4db94011d3 | 1667 | * |
sahilmgandhi | 18:6a4db94011d3 | 1668 | * \section asfdoc_sam0_tc_extra_dependencies Dependencies |
sahilmgandhi | 18:6a4db94011d3 | 1669 | * This driver has the following dependencies: |
sahilmgandhi | 18:6a4db94011d3 | 1670 | * |
sahilmgandhi | 18:6a4db94011d3 | 1671 | * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" |
sahilmgandhi | 18:6a4db94011d3 | 1672 | * |
sahilmgandhi | 18:6a4db94011d3 | 1673 | * |
sahilmgandhi | 18:6a4db94011d3 | 1674 | * \section asfdoc_sam0_tc_extra_errata Errata |
sahilmgandhi | 18:6a4db94011d3 | 1675 | * There are no errata related to this driver. |
sahilmgandhi | 18:6a4db94011d3 | 1676 | * |
sahilmgandhi | 18:6a4db94011d3 | 1677 | * |
sahilmgandhi | 18:6a4db94011d3 | 1678 | * \section asfdoc_sam0_tc_extra_history Module History |
sahilmgandhi | 18:6a4db94011d3 | 1679 | * An overview of the module history is presented in the table below, with |
sahilmgandhi | 18:6a4db94011d3 | 1680 | * details on the enhancements and fixes made to the module since its first |
sahilmgandhi | 18:6a4db94011d3 | 1681 | * release. The current version of this corresponds to the newest version in |
sahilmgandhi | 18:6a4db94011d3 | 1682 | * the table. |
sahilmgandhi | 18:6a4db94011d3 | 1683 | * |
sahilmgandhi | 18:6a4db94011d3 | 1684 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 1685 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1686 | * <th>Changelog</th> |
sahilmgandhi | 18:6a4db94011d3 | 1687 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1688 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1689 | * <td>Added support for SAMD21 and do some modifications as below: |
sahilmgandhi | 18:6a4db94011d3 | 1690 | * \li Clean up in the configuration structure, the counter size |
sahilmgandhi | 18:6a4db94011d3 | 1691 | * setting specific registers is accessed through the counter_8_bit, |
sahilmgandhi | 18:6a4db94011d3 | 1692 | * counter_16_bit and counter_32_bit structures |
sahilmgandhi | 18:6a4db94011d3 | 1693 | * \li All event related settings moved into the tc_event structure </td> |
sahilmgandhi | 18:6a4db94011d3 | 1694 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1695 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1696 | * <td>Added automatic digital clock interface enable for the slave TC |
sahilmgandhi | 18:6a4db94011d3 | 1697 | * module when a timer is initialized in 32-bit mode</td> |
sahilmgandhi | 18:6a4db94011d3 | 1698 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1699 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1700 | * <td>Initial Release</td> |
sahilmgandhi | 18:6a4db94011d3 | 1701 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1702 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 1703 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1704 | |
sahilmgandhi | 18:6a4db94011d3 | 1705 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1706 | * \page asfdoc_sam0_tc_exqsg Examples for TC Driver |
sahilmgandhi | 18:6a4db94011d3 | 1707 | * |
sahilmgandhi | 18:6a4db94011d3 | 1708 | * This is a list of the available Quick Start guides (QSGs) and example |
sahilmgandhi | 18:6a4db94011d3 | 1709 | * applications for \ref asfdoc_sam0_tc_group. QSGs are simple examples with |
sahilmgandhi | 18:6a4db94011d3 | 1710 | * step-by-step instructions to configure and use this driver in a selection of |
sahilmgandhi | 18:6a4db94011d3 | 1711 | * use cases. Note that QSGs can be compiled as a standalone application or be |
sahilmgandhi | 18:6a4db94011d3 | 1712 | * added to the user application. |
sahilmgandhi | 18:6a4db94011d3 | 1713 | * |
sahilmgandhi | 18:6a4db94011d3 | 1714 | * - \subpage asfdoc_sam0_tc_basic_use_case |
sahilmgandhi | 18:6a4db94011d3 | 1715 | * - \subpage asfdoc_sam0_tc_macth_freq_use_case |
sahilmgandhi | 18:6a4db94011d3 | 1716 | * \if TC_CALLBACK_MODE |
sahilmgandhi | 18:6a4db94011d3 | 1717 | * - \subpage asfdoc_sam0_tc_timer_use_case |
sahilmgandhi | 18:6a4db94011d3 | 1718 | * - \subpage asfdoc_sam0_tc_callback_use_case |
sahilmgandhi | 18:6a4db94011d3 | 1719 | * \endif |
sahilmgandhi | 18:6a4db94011d3 | 1720 | * - \subpage asfdoc_sam0_tc_dma_use_case |
sahilmgandhi | 18:6a4db94011d3 | 1721 | * |
sahilmgandhi | 18:6a4db94011d3 | 1722 | * \page asfdoc_sam0_tc_document_revision_history Document Revision History |
sahilmgandhi | 18:6a4db94011d3 | 1723 | * |
sahilmgandhi | 18:6a4db94011d3 | 1724 | * <table> |
sahilmgandhi | 18:6a4db94011d3 | 1725 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1726 | * <th>Doc. Rev.</td> |
sahilmgandhi | 18:6a4db94011d3 | 1727 | * <th>Date</td> |
sahilmgandhi | 18:6a4db94011d3 | 1728 | * <th>Comments</td> |
sahilmgandhi | 18:6a4db94011d3 | 1729 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1730 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1731 | * <td>F</td> |
sahilmgandhi | 18:6a4db94011d3 | 1732 | * <td>12/2014</td> |
sahilmgandhi | 18:6a4db94011d3 | 1733 | * <td>Added support for SAMC21.</td> |
sahilmgandhi | 18:6a4db94011d3 | 1734 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1735 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1736 | * <td>E</td> |
sahilmgandhi | 18:6a4db94011d3 | 1737 | * <td>04/2015</td> |
sahilmgandhi | 18:6a4db94011d3 | 1738 | * <td>Added support for SAML21 and SAMDAx.</td> |
sahilmgandhi | 18:6a4db94011d3 | 1739 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1740 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1741 | * <td>D</td> |
sahilmgandhi | 18:6a4db94011d3 | 1742 | * <td>12/2014</td> |
sahilmgandhi | 18:6a4db94011d3 | 1743 | * <td>Added timer use case. |
sahilmgandhi | 18:6a4db94011d3 | 1744 | * Added support for SAMR21 and SAMD10/D11.</td> |
sahilmgandhi | 18:6a4db94011d3 | 1745 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1746 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1747 | * <td>C</td> |
sahilmgandhi | 18:6a4db94011d3 | 1748 | * <td>01/2014</td> |
sahilmgandhi | 18:6a4db94011d3 | 1749 | * <td>Added support for SAMD21.</td> |
sahilmgandhi | 18:6a4db94011d3 | 1750 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1751 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1752 | * <td>B</td> |
sahilmgandhi | 18:6a4db94011d3 | 1753 | * <td>06/2013</td> |
sahilmgandhi | 18:6a4db94011d3 | 1754 | * <td>Corrected documentation typos.</td> |
sahilmgandhi | 18:6a4db94011d3 | 1755 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1756 | * <tr> |
sahilmgandhi | 18:6a4db94011d3 | 1757 | * <td>A</td> |
sahilmgandhi | 18:6a4db94011d3 | 1758 | * <td>06/2013</td> |
sahilmgandhi | 18:6a4db94011d3 | 1759 | * <td>Initial release</td> |
sahilmgandhi | 18:6a4db94011d3 | 1760 | * </tr> |
sahilmgandhi | 18:6a4db94011d3 | 1761 | * </table> |
sahilmgandhi | 18:6a4db94011d3 | 1762 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1763 | |
sahilmgandhi | 18:6a4db94011d3 | 1764 | #endif /* TC_H_INCLUDED */ |