Mouse code for the MacroRat
mbed-dev/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc_feature.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | * \file |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * \brief SAM ADC functionality |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * \asf_license_start |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * \page License |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 13 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 17 | * |
sahilmgandhi | 18:6a4db94011d3 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 19 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 20 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 21 | * |
sahilmgandhi | 18:6a4db94011d3 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
sahilmgandhi | 18:6a4db94011d3 | 23 | * from this software without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 24 | * |
sahilmgandhi | 18:6a4db94011d3 | 25 | * 4. This software may only be redistributed and used in connection with an |
sahilmgandhi | 18:6a4db94011d3 | 26 | * Atmel microcontroller product. |
sahilmgandhi | 18:6a4db94011d3 | 27 | * |
sahilmgandhi | 18:6a4db94011d3 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
sahilmgandhi | 18:6a4db94011d3 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
sahilmgandhi | 18:6a4db94011d3 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
sahilmgandhi | 18:6a4db94011d3 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
sahilmgandhi | 18:6a4db94011d3 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
sahilmgandhi | 18:6a4db94011d3 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
sahilmgandhi | 18:6a4db94011d3 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
sahilmgandhi | 18:6a4db94011d3 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
sahilmgandhi | 18:6a4db94011d3 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 39 | * |
sahilmgandhi | 18:6a4db94011d3 | 40 | * \asf_license_stop |
sahilmgandhi | 18:6a4db94011d3 | 41 | * |
sahilmgandhi | 18:6a4db94011d3 | 42 | */ |
sahilmgandhi | 18:6a4db94011d3 | 43 | /* |
sahilmgandhi | 18:6a4db94011d3 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
sahilmgandhi | 18:6a4db94011d3 | 45 | */ |
sahilmgandhi | 18:6a4db94011d3 | 46 | #ifndef ADC_FEATURE_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 47 | #define ADC_FEATURE_H_INCLUDED |
sahilmgandhi | 18:6a4db94011d3 | 48 | |
sahilmgandhi | 18:6a4db94011d3 | 49 | /** |
sahilmgandhi | 18:6a4db94011d3 | 50 | * \addtogroup asfdoc_sam0_adc_group |
sahilmgandhi | 18:6a4db94011d3 | 51 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 52 | */ |
sahilmgandhi | 18:6a4db94011d3 | 53 | |
sahilmgandhi | 18:6a4db94011d3 | 54 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 55 | extern "C" { |
sahilmgandhi | 18:6a4db94011d3 | 56 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 57 | |
sahilmgandhi | 18:6a4db94011d3 | 58 | /*@{*/ |
sahilmgandhi | 18:6a4db94011d3 | 59 | #if (SAMC20) || (SAMC21) || defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 60 | /** Output Driver Strength Selection feature support. */ |
sahilmgandhi | 18:6a4db94011d3 | 61 | # define FEATURE_ADC_SUPPORT_MASTER_SLAVE |
sahilmgandhi | 18:6a4db94011d3 | 62 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 63 | /*@}*/ |
sahilmgandhi | 18:6a4db94011d3 | 64 | |
sahilmgandhi | 18:6a4db94011d3 | 65 | #if ADC_CALLBACK_MODE == true |
sahilmgandhi | 18:6a4db94011d3 | 66 | # include <system_interrupt.h> |
sahilmgandhi | 18:6a4db94011d3 | 67 | |
sahilmgandhi | 18:6a4db94011d3 | 68 | #if !defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 69 | extern struct adc_module *_adc_instances[ADC_INST_NUM]; |
sahilmgandhi | 18:6a4db94011d3 | 70 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 71 | |
sahilmgandhi | 18:6a4db94011d3 | 72 | /** Forward definition of the device instance. */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | struct adc_module; |
sahilmgandhi | 18:6a4db94011d3 | 74 | |
sahilmgandhi | 18:6a4db94011d3 | 75 | /** Type of the callback functions. */ |
sahilmgandhi | 18:6a4db94011d3 | 76 | typedef void (*adc_callback_t)(struct adc_module *const module); |
sahilmgandhi | 18:6a4db94011d3 | 77 | |
sahilmgandhi | 18:6a4db94011d3 | 78 | /** |
sahilmgandhi | 18:6a4db94011d3 | 79 | * \brief ADC callback enum. |
sahilmgandhi | 18:6a4db94011d3 | 80 | * |
sahilmgandhi | 18:6a4db94011d3 | 81 | * Callback types for ADC callback driver. |
sahilmgandhi | 18:6a4db94011d3 | 82 | * |
sahilmgandhi | 18:6a4db94011d3 | 83 | */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | enum adc_callback { |
sahilmgandhi | 18:6a4db94011d3 | 85 | /** Callback for buffer received */ |
sahilmgandhi | 18:6a4db94011d3 | 86 | ADC_CALLBACK_READ_BUFFER, |
sahilmgandhi | 18:6a4db94011d3 | 87 | /** Callback when window is hit */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | ADC_CALLBACK_WINDOW, |
sahilmgandhi | 18:6a4db94011d3 | 89 | /** Callback for error */ |
sahilmgandhi | 18:6a4db94011d3 | 90 | ADC_CALLBACK_ERROR, |
sahilmgandhi | 18:6a4db94011d3 | 91 | # if !defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 92 | /** Number of available callbacks */ |
sahilmgandhi | 18:6a4db94011d3 | 93 | ADC_CALLBACK_N, |
sahilmgandhi | 18:6a4db94011d3 | 94 | # endif |
sahilmgandhi | 18:6a4db94011d3 | 95 | }; |
sahilmgandhi | 18:6a4db94011d3 | 96 | |
sahilmgandhi | 18:6a4db94011d3 | 97 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 98 | |
sahilmgandhi | 18:6a4db94011d3 | 99 | /** |
sahilmgandhi | 18:6a4db94011d3 | 100 | * \brief ADC reference voltage enum. |
sahilmgandhi | 18:6a4db94011d3 | 101 | * |
sahilmgandhi | 18:6a4db94011d3 | 102 | * Enum for the possible reference voltages for the ADC. |
sahilmgandhi | 18:6a4db94011d3 | 103 | * |
sahilmgandhi | 18:6a4db94011d3 | 104 | */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | enum adc_reference { |
sahilmgandhi | 18:6a4db94011d3 | 106 | /** Internal Bandgap Reference */ |
sahilmgandhi | 18:6a4db94011d3 | 107 | ADC_REFERENCE_INTREF = ADC_REFCTRL_REFSEL_INTREF, |
sahilmgandhi | 18:6a4db94011d3 | 108 | /** 1/1.48V<SUB>CC</SUB> reference */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, |
sahilmgandhi | 18:6a4db94011d3 | 110 | /** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */ |
sahilmgandhi | 18:6a4db94011d3 | 111 | ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, |
sahilmgandhi | 18:6a4db94011d3 | 112 | /** External reference A */ |
sahilmgandhi | 18:6a4db94011d3 | 113 | ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, |
sahilmgandhi | 18:6a4db94011d3 | 114 | #if (SAML21) |
sahilmgandhi | 18:6a4db94011d3 | 115 | /** External reference B. */ |
sahilmgandhi | 18:6a4db94011d3 | 116 | ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, |
sahilmgandhi | 18:6a4db94011d3 | 117 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 118 | #if (SAMC20) || (SAMC21) |
sahilmgandhi | 18:6a4db94011d3 | 119 | /** DAC. */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | ADC_REFERENCE_DAC = ADC_REFCTRL_REFSEL_DAC, |
sahilmgandhi | 18:6a4db94011d3 | 121 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 122 | /** VDDANA. */ |
sahilmgandhi | 18:6a4db94011d3 | 123 | ADC_REFERENCE_INTVCC2 = ADC_REFCTRL_REFSEL_INTVCC2, |
sahilmgandhi | 18:6a4db94011d3 | 124 | }; |
sahilmgandhi | 18:6a4db94011d3 | 125 | |
sahilmgandhi | 18:6a4db94011d3 | 126 | /** |
sahilmgandhi | 18:6a4db94011d3 | 127 | * \brief ADC clock prescaler enum. |
sahilmgandhi | 18:6a4db94011d3 | 128 | * |
sahilmgandhi | 18:6a4db94011d3 | 129 | * Enum for the possible clock prescaler values for the ADC. |
sahilmgandhi | 18:6a4db94011d3 | 130 | * |
sahilmgandhi | 18:6a4db94011d3 | 131 | */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | enum adc_clock_prescaler { |
sahilmgandhi | 18:6a4db94011d3 | 133 | /** ADC clock division factor 2 */ |
sahilmgandhi | 18:6a4db94011d3 | 134 | ADC_CLOCK_PRESCALER_DIV2 = ADC_CTRLB_PRESCALER_DIV2, |
sahilmgandhi | 18:6a4db94011d3 | 135 | /** ADC clock division factor 4 */ |
sahilmgandhi | 18:6a4db94011d3 | 136 | ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, |
sahilmgandhi | 18:6a4db94011d3 | 137 | /** ADC clock division factor 8 */ |
sahilmgandhi | 18:6a4db94011d3 | 138 | ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, |
sahilmgandhi | 18:6a4db94011d3 | 139 | /** ADC clock division factor 16 */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, |
sahilmgandhi | 18:6a4db94011d3 | 141 | /** ADC clock division factor 32 */ |
sahilmgandhi | 18:6a4db94011d3 | 142 | ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, |
sahilmgandhi | 18:6a4db94011d3 | 143 | /** ADC clock division factor 64 */ |
sahilmgandhi | 18:6a4db94011d3 | 144 | ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, |
sahilmgandhi | 18:6a4db94011d3 | 145 | /** ADC clock division factor 128 */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, |
sahilmgandhi | 18:6a4db94011d3 | 147 | /** ADC clock division factor 256 */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, |
sahilmgandhi | 18:6a4db94011d3 | 149 | }; |
sahilmgandhi | 18:6a4db94011d3 | 150 | |
sahilmgandhi | 18:6a4db94011d3 | 151 | /** |
sahilmgandhi | 18:6a4db94011d3 | 152 | * \brief ADC resolution enum. |
sahilmgandhi | 18:6a4db94011d3 | 153 | * |
sahilmgandhi | 18:6a4db94011d3 | 154 | * Enum for the possible resolution values for the ADC. |
sahilmgandhi | 18:6a4db94011d3 | 155 | * |
sahilmgandhi | 18:6a4db94011d3 | 156 | */ |
sahilmgandhi | 18:6a4db94011d3 | 157 | enum adc_resolution { |
sahilmgandhi | 18:6a4db94011d3 | 158 | /** ADC 12-bit resolution */ |
sahilmgandhi | 18:6a4db94011d3 | 159 | ADC_RESOLUTION_12BIT = ADC_CTRLC_RESSEL_12BIT, |
sahilmgandhi | 18:6a4db94011d3 | 160 | /** ADC 16-bit resolution using oversampling and decimation */ |
sahilmgandhi | 18:6a4db94011d3 | 161 | ADC_RESOLUTION_16BIT = ADC_CTRLC_RESSEL_16BIT, |
sahilmgandhi | 18:6a4db94011d3 | 162 | /** ADC 10-bit resolution */ |
sahilmgandhi | 18:6a4db94011d3 | 163 | ADC_RESOLUTION_10BIT = ADC_CTRLC_RESSEL_10BIT, |
sahilmgandhi | 18:6a4db94011d3 | 164 | /** ADC 8-bit resolution */ |
sahilmgandhi | 18:6a4db94011d3 | 165 | ADC_RESOLUTION_8BIT = ADC_CTRLC_RESSEL_8BIT, |
sahilmgandhi | 18:6a4db94011d3 | 166 | /** ADC 13-bit resolution using oversampling and decimation */ |
sahilmgandhi | 18:6a4db94011d3 | 167 | ADC_RESOLUTION_13BIT, |
sahilmgandhi | 18:6a4db94011d3 | 168 | /** ADC 14-bit resolution using oversampling and decimation */ |
sahilmgandhi | 18:6a4db94011d3 | 169 | ADC_RESOLUTION_14BIT, |
sahilmgandhi | 18:6a4db94011d3 | 170 | /** ADC 15-bit resolution using oversampling and decimation */ |
sahilmgandhi | 18:6a4db94011d3 | 171 | ADC_RESOLUTION_15BIT, |
sahilmgandhi | 18:6a4db94011d3 | 172 | /** ADC 16-bit result register for use with averaging. When using this mode |
sahilmgandhi | 18:6a4db94011d3 | 173 | * the ADC result register will be set to 16-bit wide, and the number of |
sahilmgandhi | 18:6a4db94011d3 | 174 | * samples to accumulate and the division factor is configured by the |
sahilmgandhi | 18:6a4db94011d3 | 175 | * \ref adc_config.accumulate_samples and \ref adc_config.divide_result |
sahilmgandhi | 18:6a4db94011d3 | 176 | * members in the configuration struct. |
sahilmgandhi | 18:6a4db94011d3 | 177 | */ |
sahilmgandhi | 18:6a4db94011d3 | 178 | ADC_RESOLUTION_CUSTOM, |
sahilmgandhi | 18:6a4db94011d3 | 179 | }; |
sahilmgandhi | 18:6a4db94011d3 | 180 | |
sahilmgandhi | 18:6a4db94011d3 | 181 | /** |
sahilmgandhi | 18:6a4db94011d3 | 182 | * \brief ADC window monitor mode enum. |
sahilmgandhi | 18:6a4db94011d3 | 183 | * |
sahilmgandhi | 18:6a4db94011d3 | 184 | * Enum for the possible window monitor modes for the ADC. |
sahilmgandhi | 18:6a4db94011d3 | 185 | * |
sahilmgandhi | 18:6a4db94011d3 | 186 | */ |
sahilmgandhi | 18:6a4db94011d3 | 187 | enum adc_window_mode { |
sahilmgandhi | 18:6a4db94011d3 | 188 | /** No window mode */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | ADC_WINDOW_MODE_DISABLE = ADC_CTRLC_WINMODE_DISABLE, |
sahilmgandhi | 18:6a4db94011d3 | 190 | /** RESULT > WINLT */ |
sahilmgandhi | 18:6a4db94011d3 | 191 | ADC_WINDOW_MODE_ABOVE_LOWER = ADC_CTRLC_WINMODE_MODE1, |
sahilmgandhi | 18:6a4db94011d3 | 192 | /** RESULT < WINUT */ |
sahilmgandhi | 18:6a4db94011d3 | 193 | ADC_WINDOW_MODE_BELOW_UPPER = ADC_CTRLC_WINMODE_MODE2, |
sahilmgandhi | 18:6a4db94011d3 | 194 | /** WINLT < RESULT < WINUT */ |
sahilmgandhi | 18:6a4db94011d3 | 195 | ADC_WINDOW_MODE_BETWEEN = ADC_CTRLC_WINMODE_MODE3, |
sahilmgandhi | 18:6a4db94011d3 | 196 | /** !(WINLT < RESULT < WINUT) */ |
sahilmgandhi | 18:6a4db94011d3 | 197 | ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_CTRLC_WINMODE_MODE4, |
sahilmgandhi | 18:6a4db94011d3 | 198 | }; |
sahilmgandhi | 18:6a4db94011d3 | 199 | |
sahilmgandhi | 18:6a4db94011d3 | 200 | /** |
sahilmgandhi | 18:6a4db94011d3 | 201 | * \brief ADC event action enum. |
sahilmgandhi | 18:6a4db94011d3 | 202 | * |
sahilmgandhi | 18:6a4db94011d3 | 203 | * Enum for the possible actions to take on an incoming event. |
sahilmgandhi | 18:6a4db94011d3 | 204 | * |
sahilmgandhi | 18:6a4db94011d3 | 205 | */ |
sahilmgandhi | 18:6a4db94011d3 | 206 | enum adc_event_action { |
sahilmgandhi | 18:6a4db94011d3 | 207 | /** Event action disabled */ |
sahilmgandhi | 18:6a4db94011d3 | 208 | ADC_EVENT_ACTION_DISABLED = 0, |
sahilmgandhi | 18:6a4db94011d3 | 209 | /** Flush ADC and start conversion */ |
sahilmgandhi | 18:6a4db94011d3 | 210 | ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_FLUSHEI, |
sahilmgandhi | 18:6a4db94011d3 | 211 | /** Start conversion */ |
sahilmgandhi | 18:6a4db94011d3 | 212 | ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, |
sahilmgandhi | 18:6a4db94011d3 | 213 | }; |
sahilmgandhi | 18:6a4db94011d3 | 214 | |
sahilmgandhi | 18:6a4db94011d3 | 215 | /** |
sahilmgandhi | 18:6a4db94011d3 | 216 | * \brief ADC positive MUX input selection enum. |
sahilmgandhi | 18:6a4db94011d3 | 217 | * |
sahilmgandhi | 18:6a4db94011d3 | 218 | * Enum for the possible positive MUX input selections for the ADC. |
sahilmgandhi | 18:6a4db94011d3 | 219 | * |
sahilmgandhi | 18:6a4db94011d3 | 220 | */ |
sahilmgandhi | 18:6a4db94011d3 | 221 | enum adc_positive_input { |
sahilmgandhi | 18:6a4db94011d3 | 222 | /** ADC0 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 223 | ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_AIN0, |
sahilmgandhi | 18:6a4db94011d3 | 224 | /** ADC1 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 225 | ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_AIN1, |
sahilmgandhi | 18:6a4db94011d3 | 226 | /** ADC2 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 227 | ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_AIN2, |
sahilmgandhi | 18:6a4db94011d3 | 228 | /** ADC3 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 229 | ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_AIN3, |
sahilmgandhi | 18:6a4db94011d3 | 230 | /** ADC4 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 231 | ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_AIN4, |
sahilmgandhi | 18:6a4db94011d3 | 232 | /** ADC5 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 233 | ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_AIN5, |
sahilmgandhi | 18:6a4db94011d3 | 234 | /** ADC6 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 235 | ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_AIN6, |
sahilmgandhi | 18:6a4db94011d3 | 236 | /** ADC7 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 237 | ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_AIN7, |
sahilmgandhi | 18:6a4db94011d3 | 238 | /** ADC8 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 239 | ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_AIN8, |
sahilmgandhi | 18:6a4db94011d3 | 240 | /** ADC9 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 241 | ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_AIN9, |
sahilmgandhi | 18:6a4db94011d3 | 242 | /** ADC10 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 243 | ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_AIN10, |
sahilmgandhi | 18:6a4db94011d3 | 244 | /** ADC11 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 245 | ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_AIN11, |
sahilmgandhi | 18:6a4db94011d3 | 246 | #if !(SAMC20) && !(SAMC21) |
sahilmgandhi | 18:6a4db94011d3 | 247 | /** ADC12 pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 248 | ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_AIN12, |
sahilmgandhi | 18:6a4db94011d3 | 249 | /** ADC13 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 250 | ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_AIN13, |
sahilmgandhi | 18:6a4db94011d3 | 251 | /** ADC14 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 252 | ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_AIN14, |
sahilmgandhi | 18:6a4db94011d3 | 253 | /** ADC15 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 254 | ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_AIN15, |
sahilmgandhi | 18:6a4db94011d3 | 255 | /** ADC16 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 256 | ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_AIN16, |
sahilmgandhi | 18:6a4db94011d3 | 257 | /** ADC17 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 258 | ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_AIN17, |
sahilmgandhi | 18:6a4db94011d3 | 259 | /** ADC18 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 260 | ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_AIN18, |
sahilmgandhi | 18:6a4db94011d3 | 261 | /** ADC19 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 262 | ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_AIN19, |
sahilmgandhi | 18:6a4db94011d3 | 263 | /** ADC20 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 264 | ADC_POSITIVE_INPUT_PIN20 = ADC_INPUTCTRL_MUXPOS_AIN20, |
sahilmgandhi | 18:6a4db94011d3 | 265 | /** ADC21 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 266 | ADC_POSITIVE_INPUT_PIN21 = ADC_INPUTCTRL_MUXPOS_AIN21, |
sahilmgandhi | 18:6a4db94011d3 | 267 | /** ADC22 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 268 | ADC_POSITIVE_INPUT_PIN22 = ADC_INPUTCTRL_MUXPOS_AIN22, |
sahilmgandhi | 18:6a4db94011d3 | 269 | /** ADC23 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 270 | ADC_POSITIVE_INPUT_PIN23 = ADC_INPUTCTRL_MUXPOS_AIN23, |
sahilmgandhi | 18:6a4db94011d3 | 271 | /** Temperature reference */ |
sahilmgandhi | 18:6a4db94011d3 | 272 | ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, |
sahilmgandhi | 18:6a4db94011d3 | 273 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 274 | /** Bandgap voltage. */ |
sahilmgandhi | 18:6a4db94011d3 | 275 | ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, |
sahilmgandhi | 18:6a4db94011d3 | 276 | /** 1/4 scaled core supply */ |
sahilmgandhi | 18:6a4db94011d3 | 277 | ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, |
sahilmgandhi | 18:6a4db94011d3 | 278 | /** 1/4 scaled I/O supply */ |
sahilmgandhi | 18:6a4db94011d3 | 279 | ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, |
sahilmgandhi | 18:6a4db94011d3 | 280 | /** DAC input */ |
sahilmgandhi | 18:6a4db94011d3 | 281 | ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, |
sahilmgandhi | 18:6a4db94011d3 | 282 | #if !(SAMC20) && !(SAMC21) |
sahilmgandhi | 18:6a4db94011d3 | 283 | /** SCALEDVBAT. */ |
sahilmgandhi | 18:6a4db94011d3 | 284 | ADC_POSITIVE_INPUT_SCALEDVBAT = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT, |
sahilmgandhi | 18:6a4db94011d3 | 285 | /** OPAMP01 */ |
sahilmgandhi | 18:6a4db94011d3 | 286 | ADC_POSITIVE_INPUT_OPAMP01 = ADC_INPUTCTRL_MUXPOS_OPAMP01, |
sahilmgandhi | 18:6a4db94011d3 | 287 | /** OPAMP02 */ |
sahilmgandhi | 18:6a4db94011d3 | 288 | ADC_POSITIVE_INPUT_OPAMP2 = ADC_INPUTCTRL_MUXPOS_OPAMP2, |
sahilmgandhi | 18:6a4db94011d3 | 289 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 290 | }; |
sahilmgandhi | 18:6a4db94011d3 | 291 | |
sahilmgandhi | 18:6a4db94011d3 | 292 | /** |
sahilmgandhi | 18:6a4db94011d3 | 293 | * \brief ADC negative MUX input selection enum. |
sahilmgandhi | 18:6a4db94011d3 | 294 | * |
sahilmgandhi | 18:6a4db94011d3 | 295 | * Enum for the possible negative MUX input selections for the ADC. |
sahilmgandhi | 18:6a4db94011d3 | 296 | * |
sahilmgandhi | 18:6a4db94011d3 | 297 | */ |
sahilmgandhi | 18:6a4db94011d3 | 298 | enum adc_negative_input { |
sahilmgandhi | 18:6a4db94011d3 | 299 | /** ADC0 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 300 | ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_AIN0, |
sahilmgandhi | 18:6a4db94011d3 | 301 | /** ADC1 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 302 | ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_AIN1, |
sahilmgandhi | 18:6a4db94011d3 | 303 | /** ADC2 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 304 | ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_AIN2, |
sahilmgandhi | 18:6a4db94011d3 | 305 | /** ADC3 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 306 | ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_AIN3, |
sahilmgandhi | 18:6a4db94011d3 | 307 | /** ADC4 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 308 | ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_AIN4, |
sahilmgandhi | 18:6a4db94011d3 | 309 | /** ADC5 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 310 | ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_AIN5, |
sahilmgandhi | 18:6a4db94011d3 | 311 | #if !(SAMC20) && !(SAMC21) |
sahilmgandhi | 18:6a4db94011d3 | 312 | /** ADC6 pin. */ |
sahilmgandhi | 18:6a4db94011d3 | 313 | ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_AIN6, |
sahilmgandhi | 18:6a4db94011d3 | 314 | /** ADC7 pin */ |
sahilmgandhi | 18:6a4db94011d3 | 315 | ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_AIN7, |
sahilmgandhi | 18:6a4db94011d3 | 316 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 317 | /** Internal ground. */ |
sahilmgandhi | 18:6a4db94011d3 | 318 | ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG(0x18u), |
sahilmgandhi | 18:6a4db94011d3 | 319 | }; |
sahilmgandhi | 18:6a4db94011d3 | 320 | |
sahilmgandhi | 18:6a4db94011d3 | 321 | /** |
sahilmgandhi | 18:6a4db94011d3 | 322 | * \brief ADC number of accumulated samples enum. |
sahilmgandhi | 18:6a4db94011d3 | 323 | * |
sahilmgandhi | 18:6a4db94011d3 | 324 | * Enum for the possible numbers of ADC samples to accumulate. |
sahilmgandhi | 18:6a4db94011d3 | 325 | * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM |
sahilmgandhi | 18:6a4db94011d3 | 326 | * resolution setting is used. |
sahilmgandhi | 18:6a4db94011d3 | 327 | * |
sahilmgandhi | 18:6a4db94011d3 | 328 | */ |
sahilmgandhi | 18:6a4db94011d3 | 329 | enum adc_accumulate_samples { |
sahilmgandhi | 18:6a4db94011d3 | 330 | /** No averaging */ |
sahilmgandhi | 18:6a4db94011d3 | 331 | ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, |
sahilmgandhi | 18:6a4db94011d3 | 332 | /** Average 2 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 333 | ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, |
sahilmgandhi | 18:6a4db94011d3 | 334 | /** Average 4 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 335 | ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, |
sahilmgandhi | 18:6a4db94011d3 | 336 | /** Average 8 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 337 | ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, |
sahilmgandhi | 18:6a4db94011d3 | 338 | /** Average 16 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 339 | ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, |
sahilmgandhi | 18:6a4db94011d3 | 340 | /** Average 32 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 341 | ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, |
sahilmgandhi | 18:6a4db94011d3 | 342 | /** Average 64 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 343 | ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, |
sahilmgandhi | 18:6a4db94011d3 | 344 | /** Average 128 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 345 | ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, |
sahilmgandhi | 18:6a4db94011d3 | 346 | /** Average 256 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 347 | ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, |
sahilmgandhi | 18:6a4db94011d3 | 348 | /** Average 512 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 349 | ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, |
sahilmgandhi | 18:6a4db94011d3 | 350 | /** Average 1024 samples */ |
sahilmgandhi | 18:6a4db94011d3 | 351 | ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, |
sahilmgandhi | 18:6a4db94011d3 | 352 | }; |
sahilmgandhi | 18:6a4db94011d3 | 353 | |
sahilmgandhi | 18:6a4db94011d3 | 354 | /** |
sahilmgandhi | 18:6a4db94011d3 | 355 | * \brief ADC possible dividers for the result register. |
sahilmgandhi | 18:6a4db94011d3 | 356 | * |
sahilmgandhi | 18:6a4db94011d3 | 357 | * Enum for the possible division factors to use when accumulating |
sahilmgandhi | 18:6a4db94011d3 | 358 | * multiple samples. To keep the same resolution for the averaged |
sahilmgandhi | 18:6a4db94011d3 | 359 | * result and the actual input value, the division factor must |
sahilmgandhi | 18:6a4db94011d3 | 360 | * be equal to the number of samples accumulated. This setting is only |
sahilmgandhi | 18:6a4db94011d3 | 361 | * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used. |
sahilmgandhi | 18:6a4db94011d3 | 362 | */ |
sahilmgandhi | 18:6a4db94011d3 | 363 | enum adc_divide_result { |
sahilmgandhi | 18:6a4db94011d3 | 364 | /** Don't divide result register after accumulation */ |
sahilmgandhi | 18:6a4db94011d3 | 365 | ADC_DIVIDE_RESULT_DISABLE = 0, |
sahilmgandhi | 18:6a4db94011d3 | 366 | /** Divide result register by 2 after accumulation */ |
sahilmgandhi | 18:6a4db94011d3 | 367 | ADC_DIVIDE_RESULT_2 = 1, |
sahilmgandhi | 18:6a4db94011d3 | 368 | /** Divide result register by 4 after accumulation */ |
sahilmgandhi | 18:6a4db94011d3 | 369 | ADC_DIVIDE_RESULT_4 = 2, |
sahilmgandhi | 18:6a4db94011d3 | 370 | /** Divide result register by 8 after accumulation */ |
sahilmgandhi | 18:6a4db94011d3 | 371 | ADC_DIVIDE_RESULT_8 = 3, |
sahilmgandhi | 18:6a4db94011d3 | 372 | /** Divide result register by 16 after accumulation */ |
sahilmgandhi | 18:6a4db94011d3 | 373 | ADC_DIVIDE_RESULT_16 = 4, |
sahilmgandhi | 18:6a4db94011d3 | 374 | /** Divide result register by 32 after accumulation */ |
sahilmgandhi | 18:6a4db94011d3 | 375 | ADC_DIVIDE_RESULT_32 = 5, |
sahilmgandhi | 18:6a4db94011d3 | 376 | /** Divide result register by 64 after accumulation */ |
sahilmgandhi | 18:6a4db94011d3 | 377 | ADC_DIVIDE_RESULT_64 = 6, |
sahilmgandhi | 18:6a4db94011d3 | 378 | /** Divide result register by 128 after accumulation */ |
sahilmgandhi | 18:6a4db94011d3 | 379 | ADC_DIVIDE_RESULT_128 = 7, |
sahilmgandhi | 18:6a4db94011d3 | 380 | }; |
sahilmgandhi | 18:6a4db94011d3 | 381 | |
sahilmgandhi | 18:6a4db94011d3 | 382 | #if ADC_CALLBACK_MODE == true |
sahilmgandhi | 18:6a4db94011d3 | 383 | /** |
sahilmgandhi | 18:6a4db94011d3 | 384 | * Enum for the possible ADC interrupt flags. |
sahilmgandhi | 18:6a4db94011d3 | 385 | */ |
sahilmgandhi | 18:6a4db94011d3 | 386 | enum adc_interrupt_flag { |
sahilmgandhi | 18:6a4db94011d3 | 387 | /** ADC result ready */ |
sahilmgandhi | 18:6a4db94011d3 | 388 | ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, |
sahilmgandhi | 18:6a4db94011d3 | 389 | /** Window monitor match */ |
sahilmgandhi | 18:6a4db94011d3 | 390 | ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, |
sahilmgandhi | 18:6a4db94011d3 | 391 | /** ADC result overwritten before read */ |
sahilmgandhi | 18:6a4db94011d3 | 392 | ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, |
sahilmgandhi | 18:6a4db94011d3 | 393 | }; |
sahilmgandhi | 18:6a4db94011d3 | 394 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 395 | |
sahilmgandhi | 18:6a4db94011d3 | 396 | /** |
sahilmgandhi | 18:6a4db94011d3 | 397 | * \brief ADC oversampling and decimation enum. |
sahilmgandhi | 18:6a4db94011d3 | 398 | * |
sahilmgandhi | 18:6a4db94011d3 | 399 | * Enum for the possible numbers of bits resolution can be increased by when |
sahilmgandhi | 18:6a4db94011d3 | 400 | * using oversampling and decimation. |
sahilmgandhi | 18:6a4db94011d3 | 401 | * |
sahilmgandhi | 18:6a4db94011d3 | 402 | */ |
sahilmgandhi | 18:6a4db94011d3 | 403 | enum adc_oversampling_and_decimation { |
sahilmgandhi | 18:6a4db94011d3 | 404 | /** Don't use oversampling and decimation mode */ |
sahilmgandhi | 18:6a4db94011d3 | 405 | ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, |
sahilmgandhi | 18:6a4db94011d3 | 406 | /** 1 bit resolution increase */ |
sahilmgandhi | 18:6a4db94011d3 | 407 | ADC_OVERSAMPLING_AND_DECIMATION_1BIT, |
sahilmgandhi | 18:6a4db94011d3 | 408 | /** 2 bits resolution increase */ |
sahilmgandhi | 18:6a4db94011d3 | 409 | ADC_OVERSAMPLING_AND_DECIMATION_2BIT, |
sahilmgandhi | 18:6a4db94011d3 | 410 | /** 3 bits resolution increase */ |
sahilmgandhi | 18:6a4db94011d3 | 411 | ADC_OVERSAMPLING_AND_DECIMATION_3BIT, |
sahilmgandhi | 18:6a4db94011d3 | 412 | /** 4 bits resolution increase */ |
sahilmgandhi | 18:6a4db94011d3 | 413 | ADC_OVERSAMPLING_AND_DECIMATION_4BIT |
sahilmgandhi | 18:6a4db94011d3 | 414 | }; |
sahilmgandhi | 18:6a4db94011d3 | 415 | |
sahilmgandhi | 18:6a4db94011d3 | 416 | #ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE |
sahilmgandhi | 18:6a4db94011d3 | 417 | /** |
sahilmgandhi | 18:6a4db94011d3 | 418 | * Enum for the trigger selection in dual mode. |
sahilmgandhi | 18:6a4db94011d3 | 419 | */ |
sahilmgandhi | 18:6a4db94011d3 | 420 | enum adc_dual_mode_trigger_selection { |
sahilmgandhi | 18:6a4db94011d3 | 421 | /** Start event or software trigger will start a conversion on both ADCs. */ |
sahilmgandhi | 18:6a4db94011d3 | 422 | ADC_DUAL_MODE_BOTH = ADC_CTRLC_DUALSEL_BOTH, |
sahilmgandhi | 18:6a4db94011d3 | 423 | /** START event or software trigger will alternatingly start a conversion on ADC0 and ADC1. */ |
sahilmgandhi | 18:6a4db94011d3 | 424 | ADC_DUAL_MODE_INTERLEAVE = ADC_CTRLC_DUALSEL_INTERLEAVE, |
sahilmgandhi | 18:6a4db94011d3 | 425 | }; |
sahilmgandhi | 18:6a4db94011d3 | 426 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 427 | |
sahilmgandhi | 18:6a4db94011d3 | 428 | /** |
sahilmgandhi | 18:6a4db94011d3 | 429 | * \brief Window monitor configuration structure. |
sahilmgandhi | 18:6a4db94011d3 | 430 | * |
sahilmgandhi | 18:6a4db94011d3 | 431 | * Window monitor configuration structure. |
sahilmgandhi | 18:6a4db94011d3 | 432 | */ |
sahilmgandhi | 18:6a4db94011d3 | 433 | struct adc_window_config { |
sahilmgandhi | 18:6a4db94011d3 | 434 | /** Selected window mode */ |
sahilmgandhi | 18:6a4db94011d3 | 435 | enum adc_window_mode window_mode; |
sahilmgandhi | 18:6a4db94011d3 | 436 | /** Lower window value */ |
sahilmgandhi | 18:6a4db94011d3 | 437 | int32_t window_lower_value; |
sahilmgandhi | 18:6a4db94011d3 | 438 | /** Upper window value */ |
sahilmgandhi | 18:6a4db94011d3 | 439 | int32_t window_upper_value; |
sahilmgandhi | 18:6a4db94011d3 | 440 | }; |
sahilmgandhi | 18:6a4db94011d3 | 441 | |
sahilmgandhi | 18:6a4db94011d3 | 442 | /** |
sahilmgandhi | 18:6a4db94011d3 | 443 | * \brief ADC event enable/disable structure. |
sahilmgandhi | 18:6a4db94011d3 | 444 | * |
sahilmgandhi | 18:6a4db94011d3 | 445 | * Event flags for the ADC module. This is used to enable and |
sahilmgandhi | 18:6a4db94011d3 | 446 | * disable events via \ref adc_enable_events() and \ref adc_disable_events(). |
sahilmgandhi | 18:6a4db94011d3 | 447 | */ |
sahilmgandhi | 18:6a4db94011d3 | 448 | struct adc_events { |
sahilmgandhi | 18:6a4db94011d3 | 449 | /** Enable event generation on conversion done */ |
sahilmgandhi | 18:6a4db94011d3 | 450 | bool generate_event_on_conversion_done; |
sahilmgandhi | 18:6a4db94011d3 | 451 | /** Enable event generation on window monitor */ |
sahilmgandhi | 18:6a4db94011d3 | 452 | bool generate_event_on_window_monitor; |
sahilmgandhi | 18:6a4db94011d3 | 453 | }; |
sahilmgandhi | 18:6a4db94011d3 | 454 | |
sahilmgandhi | 18:6a4db94011d3 | 455 | /** |
sahilmgandhi | 18:6a4db94011d3 | 456 | * \brief Gain and offset correction configuration structure. |
sahilmgandhi | 18:6a4db94011d3 | 457 | * |
sahilmgandhi | 18:6a4db94011d3 | 458 | * Gain and offset correction configuration structure. |
sahilmgandhi | 18:6a4db94011d3 | 459 | * Part of the \ref adc_config struct and will be initialized by |
sahilmgandhi | 18:6a4db94011d3 | 460 | * \ref adc_get_config_defaults. |
sahilmgandhi | 18:6a4db94011d3 | 461 | */ |
sahilmgandhi | 18:6a4db94011d3 | 462 | struct adc_correction_config { |
sahilmgandhi | 18:6a4db94011d3 | 463 | /** |
sahilmgandhi | 18:6a4db94011d3 | 464 | * Enables correction for gain and offset based on values of gain_correction and |
sahilmgandhi | 18:6a4db94011d3 | 465 | * offset_correction if set to true |
sahilmgandhi | 18:6a4db94011d3 | 466 | */ |
sahilmgandhi | 18:6a4db94011d3 | 467 | bool correction_enable; |
sahilmgandhi | 18:6a4db94011d3 | 468 | /** |
sahilmgandhi | 18:6a4db94011d3 | 469 | * This value defines how the ADC conversion result is compensated for gain |
sahilmgandhi | 18:6a4db94011d3 | 470 | * error before written to the result register. This is a fractional value, |
sahilmgandhi | 18:6a4db94011d3 | 471 | * 1-bit integer plus an 11-bit fraction, therefore |
sahilmgandhi | 18:6a4db94011d3 | 472 | * 1/2 ¡Ü gain_correction < 2. Valid \c gain_correction values ranges from |
sahilmgandhi | 18:6a4db94011d3 | 473 | * \c 0b010000000000 to \c 0b111111111111. |
sahilmgandhi | 18:6a4db94011d3 | 474 | */ |
sahilmgandhi | 18:6a4db94011d3 | 475 | uint16_t gain_correction; |
sahilmgandhi | 18:6a4db94011d3 | 476 | /** |
sahilmgandhi | 18:6a4db94011d3 | 477 | * This value defines how the ADC conversion result is compensated for |
sahilmgandhi | 18:6a4db94011d3 | 478 | * offset error before written to the result register. This is a 12-bit |
sahilmgandhi | 18:6a4db94011d3 | 479 | * value in two's complement format. |
sahilmgandhi | 18:6a4db94011d3 | 480 | */ |
sahilmgandhi | 18:6a4db94011d3 | 481 | int16_t offset_correction; |
sahilmgandhi | 18:6a4db94011d3 | 482 | }; |
sahilmgandhi | 18:6a4db94011d3 | 483 | |
sahilmgandhi | 18:6a4db94011d3 | 484 | /** |
sahilmgandhi | 18:6a4db94011d3 | 485 | * \brief ADC configuration structure. |
sahilmgandhi | 18:6a4db94011d3 | 486 | * |
sahilmgandhi | 18:6a4db94011d3 | 487 | * Configuration structure for an ADC instance. This structure should be |
sahilmgandhi | 18:6a4db94011d3 | 488 | * initialized by the \ref adc_get_config_defaults() |
sahilmgandhi | 18:6a4db94011d3 | 489 | * function before being modified by the user application. |
sahilmgandhi | 18:6a4db94011d3 | 490 | */ |
sahilmgandhi | 18:6a4db94011d3 | 491 | struct adc_config { |
sahilmgandhi | 18:6a4db94011d3 | 492 | /** GCLK generator used to clock the peripheral */ |
sahilmgandhi | 18:6a4db94011d3 | 493 | enum gclk_generator clock_source; |
sahilmgandhi | 18:6a4db94011d3 | 494 | /** Voltage reference */ |
sahilmgandhi | 18:6a4db94011d3 | 495 | enum adc_reference reference; |
sahilmgandhi | 18:6a4db94011d3 | 496 | /** Clock prescaler */ |
sahilmgandhi | 18:6a4db94011d3 | 497 | enum adc_clock_prescaler clock_prescaler; |
sahilmgandhi | 18:6a4db94011d3 | 498 | /** Result resolution */ |
sahilmgandhi | 18:6a4db94011d3 | 499 | enum adc_resolution resolution; |
sahilmgandhi | 18:6a4db94011d3 | 500 | /** Positive MUX input */ |
sahilmgandhi | 18:6a4db94011d3 | 501 | enum adc_positive_input positive_input; |
sahilmgandhi | 18:6a4db94011d3 | 502 | /** Negative MUX input */ |
sahilmgandhi | 18:6a4db94011d3 | 503 | enum adc_negative_input negative_input; |
sahilmgandhi | 18:6a4db94011d3 | 504 | /** Number of ADC samples to accumulate when using the |
sahilmgandhi | 18:6a4db94011d3 | 505 | * \c ADC_RESOLUTION_CUSTOM mode |
sahilmgandhi | 18:6a4db94011d3 | 506 | */ |
sahilmgandhi | 18:6a4db94011d3 | 507 | enum adc_accumulate_samples accumulate_samples; |
sahilmgandhi | 18:6a4db94011d3 | 508 | /** Division ration when using the ADC_RESOLUTION_CUSTOM mode */ |
sahilmgandhi | 18:6a4db94011d3 | 509 | enum adc_divide_result divide_result; |
sahilmgandhi | 18:6a4db94011d3 | 510 | /** Left adjusted result */ |
sahilmgandhi | 18:6a4db94011d3 | 511 | bool left_adjust; |
sahilmgandhi | 18:6a4db94011d3 | 512 | /** Enables differential mode if true */ |
sahilmgandhi | 18:6a4db94011d3 | 513 | bool differential_mode; |
sahilmgandhi | 18:6a4db94011d3 | 514 | /** Enables free running mode if true */ |
sahilmgandhi | 18:6a4db94011d3 | 515 | bool freerunning; |
sahilmgandhi | 18:6a4db94011d3 | 516 | /** ADC run in standby control */ |
sahilmgandhi | 18:6a4db94011d3 | 517 | bool run_in_standby; |
sahilmgandhi | 18:6a4db94011d3 | 518 | /** ADC On demand control */ |
sahilmgandhi | 18:6a4db94011d3 | 519 | bool on_demand; |
sahilmgandhi | 18:6a4db94011d3 | 520 | /** |
sahilmgandhi | 18:6a4db94011d3 | 521 | * Enables sampling period offset compensation if true |
sahilmgandhi | 18:6a4db94011d3 | 522 | */ |
sahilmgandhi | 18:6a4db94011d3 | 523 | bool sampling_time_compensation_enable; |
sahilmgandhi | 18:6a4db94011d3 | 524 | /** |
sahilmgandhi | 18:6a4db94011d3 | 525 | * Positive input enabled mask for conversion sequence. |
sahilmgandhi | 18:6a4db94011d3 | 526 | * The sequence start from the lowest input, and go to the next enabled input |
sahilmgandhi | 18:6a4db94011d3 | 527 | * automatically when the conversion is done. If no bits are set the |
sahilmgandhi | 18:6a4db94011d3 | 528 | * sequence is disabled. |
sahilmgandhi | 18:6a4db94011d3 | 529 | */ |
sahilmgandhi | 18:6a4db94011d3 | 530 | uint32_t positive_input_sequence_mask_enable; |
sahilmgandhi | 18:6a4db94011d3 | 531 | /** |
sahilmgandhi | 18:6a4db94011d3 | 532 | * Enables reference buffer offset compensation if true. |
sahilmgandhi | 18:6a4db94011d3 | 533 | * This will increase the accuracy of the gain stage, but decreases the input |
sahilmgandhi | 18:6a4db94011d3 | 534 | * impedance; therefore the startup time of the reference must be increased. |
sahilmgandhi | 18:6a4db94011d3 | 535 | */ |
sahilmgandhi | 18:6a4db94011d3 | 536 | bool reference_compensation_enable; |
sahilmgandhi | 18:6a4db94011d3 | 537 | /** |
sahilmgandhi | 18:6a4db94011d3 | 538 | * This value (0-63) control the ADC sampling time in number of half ADC |
sahilmgandhi | 18:6a4db94011d3 | 539 | * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus |
sahilmgandhi | 18:6a4db94011d3 | 540 | * controlling the ADC input impedance. Sampling time is set according to |
sahilmgandhi | 18:6a4db94011d3 | 541 | * the formula: |
sahilmgandhi | 18:6a4db94011d3 | 542 | * Sample time = (sample_length+1) * (ADCclk / 2). |
sahilmgandhi | 18:6a4db94011d3 | 543 | */ |
sahilmgandhi | 18:6a4db94011d3 | 544 | uint8_t sample_length; |
sahilmgandhi | 18:6a4db94011d3 | 545 | /** Window monitor configuration structure */ |
sahilmgandhi | 18:6a4db94011d3 | 546 | struct adc_window_config window; |
sahilmgandhi | 18:6a4db94011d3 | 547 | /** Gain and offset correction configuration structure */ |
sahilmgandhi | 18:6a4db94011d3 | 548 | struct adc_correction_config correction; |
sahilmgandhi | 18:6a4db94011d3 | 549 | /** Event action to take on incoming event */ |
sahilmgandhi | 18:6a4db94011d3 | 550 | enum adc_event_action event_action; |
sahilmgandhi | 18:6a4db94011d3 | 551 | }; |
sahilmgandhi | 18:6a4db94011d3 | 552 | |
sahilmgandhi | 18:6a4db94011d3 | 553 | /** |
sahilmgandhi | 18:6a4db94011d3 | 554 | * \brief ADC software device instance structure. |
sahilmgandhi | 18:6a4db94011d3 | 555 | * |
sahilmgandhi | 18:6a4db94011d3 | 556 | * ADC software instance structure, used to retain software state information |
sahilmgandhi | 18:6a4db94011d3 | 557 | * of an associated hardware module instance. |
sahilmgandhi | 18:6a4db94011d3 | 558 | * |
sahilmgandhi | 18:6a4db94011d3 | 559 | * \note The fields of this structure should not be altered by the user |
sahilmgandhi | 18:6a4db94011d3 | 560 | * application; they are reserved for module-internal use only. |
sahilmgandhi | 18:6a4db94011d3 | 561 | */ |
sahilmgandhi | 18:6a4db94011d3 | 562 | struct adc_module { |
sahilmgandhi | 18:6a4db94011d3 | 563 | #if !defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 564 | /** Pointer to ADC hardware module */ |
sahilmgandhi | 18:6a4db94011d3 | 565 | Adc *hw; |
sahilmgandhi | 18:6a4db94011d3 | 566 | /** Keep reference configuration so we know when enable is called */ |
sahilmgandhi | 18:6a4db94011d3 | 567 | enum adc_reference reference; |
sahilmgandhi | 18:6a4db94011d3 | 568 | # if ADC_CALLBACK_MODE == true |
sahilmgandhi | 18:6a4db94011d3 | 569 | /** Array to store callback functions */ |
sahilmgandhi | 18:6a4db94011d3 | 570 | adc_callback_t callback[ADC_CALLBACK_N]; |
sahilmgandhi | 18:6a4db94011d3 | 571 | /** Pointer to buffer used for ADC results */ |
sahilmgandhi | 18:6a4db94011d3 | 572 | volatile uint16_t *job_buffer; |
sahilmgandhi | 18:6a4db94011d3 | 573 | /** Remaining number of conversions in current job */ |
sahilmgandhi | 18:6a4db94011d3 | 574 | volatile uint16_t remaining_conversions; |
sahilmgandhi | 18:6a4db94011d3 | 575 | /** Bit mask for callbacks registered */ |
sahilmgandhi | 18:6a4db94011d3 | 576 | uint8_t registered_callback_mask; |
sahilmgandhi | 18:6a4db94011d3 | 577 | /** Bit mask for callbacks enabled */ |
sahilmgandhi | 18:6a4db94011d3 | 578 | uint8_t enabled_callback_mask; |
sahilmgandhi | 18:6a4db94011d3 | 579 | /** Holds the status of the ongoing or last conversion job */ |
sahilmgandhi | 18:6a4db94011d3 | 580 | volatile enum status_code job_status; |
sahilmgandhi | 18:6a4db94011d3 | 581 | /** If software triggering is needed */ |
sahilmgandhi | 18:6a4db94011d3 | 582 | bool software_trigger; |
sahilmgandhi | 18:6a4db94011d3 | 583 | # endif |
sahilmgandhi | 18:6a4db94011d3 | 584 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 585 | }; |
sahilmgandhi | 18:6a4db94011d3 | 586 | |
sahilmgandhi | 18:6a4db94011d3 | 587 | #if !defined(__DOXYGEN__) |
sahilmgandhi | 18:6a4db94011d3 | 588 | |
sahilmgandhi | 18:6a4db94011d3 | 589 | /** |
sahilmgandhi | 18:6a4db94011d3 | 590 | * \brief Determines if the hardware module(s) are currently synchronizing to the bus. |
sahilmgandhi | 18:6a4db94011d3 | 591 | * |
sahilmgandhi | 18:6a4db94011d3 | 592 | * Checks to see if the underlying hardware peripheral module(s) are currently |
sahilmgandhi | 18:6a4db94011d3 | 593 | * synchronizing across multiple clock domains to the hardware bus. This |
sahilmgandhi | 18:6a4db94011d3 | 594 | * function can be used to delay further operations on a module until such time |
sahilmgandhi | 18:6a4db94011d3 | 595 | * that it is ready, to prevent blocking delays for synchronization in the |
sahilmgandhi | 18:6a4db94011d3 | 596 | * user application. |
sahilmgandhi | 18:6a4db94011d3 | 597 | * |
sahilmgandhi | 18:6a4db94011d3 | 598 | * \param[in] module_inst Pointer to the ADC software instance struct |
sahilmgandhi | 18:6a4db94011d3 | 599 | * |
sahilmgandhi | 18:6a4db94011d3 | 600 | * \return Synchronization status of the underlying hardware module(s). |
sahilmgandhi | 18:6a4db94011d3 | 601 | * |
sahilmgandhi | 18:6a4db94011d3 | 602 | * \retval true if the module synchronization is ongoing |
sahilmgandhi | 18:6a4db94011d3 | 603 | * \retval false if the module has completed synchronization |
sahilmgandhi | 18:6a4db94011d3 | 604 | */ |
sahilmgandhi | 18:6a4db94011d3 | 605 | static inline bool adc_is_syncing( |
sahilmgandhi | 18:6a4db94011d3 | 606 | struct adc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 607 | { |
sahilmgandhi | 18:6a4db94011d3 | 608 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 609 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 610 | |
sahilmgandhi | 18:6a4db94011d3 | 611 | Adc *const adc_module = module_inst->hw; |
sahilmgandhi | 18:6a4db94011d3 | 612 | |
sahilmgandhi | 18:6a4db94011d3 | 613 | if (adc_module->SYNCBUSY.reg) { |
sahilmgandhi | 18:6a4db94011d3 | 614 | return true; |
sahilmgandhi | 18:6a4db94011d3 | 615 | } |
sahilmgandhi | 18:6a4db94011d3 | 616 | |
sahilmgandhi | 18:6a4db94011d3 | 617 | return false; |
sahilmgandhi | 18:6a4db94011d3 | 618 | } |
sahilmgandhi | 18:6a4db94011d3 | 619 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 620 | |
sahilmgandhi | 18:6a4db94011d3 | 621 | /** |
sahilmgandhi | 18:6a4db94011d3 | 622 | * \name Positive Input Sequence |
sahilmgandhi | 18:6a4db94011d3 | 623 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 624 | */ |
sahilmgandhi | 18:6a4db94011d3 | 625 | |
sahilmgandhi | 18:6a4db94011d3 | 626 | /** |
sahilmgandhi | 18:6a4db94011d3 | 627 | * \brief Enable positive input sequence mask for conversion. |
sahilmgandhi | 18:6a4db94011d3 | 628 | * |
sahilmgandhi | 18:6a4db94011d3 | 629 | * The sequence start from the lowest input, and go to the next enabled input |
sahilmgandhi | 18:6a4db94011d3 | 630 | * automatically when the conversion is done. If no bits are set the |
sahilmgandhi | 18:6a4db94011d3 | 631 | * sequence is disabled. |
sahilmgandhi | 18:6a4db94011d3 | 632 | * |
sahilmgandhi | 18:6a4db94011d3 | 633 | * \param[in] module_inst Pointer to the ADC software instance struct |
sahilmgandhi | 18:6a4db94011d3 | 634 | * \param[in] eanble_seq_mask Sequence mask |
sahilmgandhi | 18:6a4db94011d3 | 635 | */ |
sahilmgandhi | 18:6a4db94011d3 | 636 | static inline void adc_enable_positive_input_sequence( |
sahilmgandhi | 18:6a4db94011d3 | 637 | struct adc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 638 | uint32_t positive_input_sequence_mask_enable) |
sahilmgandhi | 18:6a4db94011d3 | 639 | { |
sahilmgandhi | 18:6a4db94011d3 | 640 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 641 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 642 | |
sahilmgandhi | 18:6a4db94011d3 | 643 | Adc *const adc_module = module_inst->hw; |
sahilmgandhi | 18:6a4db94011d3 | 644 | adc_module->SEQCTRL.reg = positive_input_sequence_mask_enable; |
sahilmgandhi | 18:6a4db94011d3 | 645 | } |
sahilmgandhi | 18:6a4db94011d3 | 646 | |
sahilmgandhi | 18:6a4db94011d3 | 647 | /** |
sahilmgandhi | 18:6a4db94011d3 | 648 | * \brief Disable positive input in the sequence. |
sahilmgandhi | 18:6a4db94011d3 | 649 | * |
sahilmgandhi | 18:6a4db94011d3 | 650 | * Disable positive input in the sequence. |
sahilmgandhi | 18:6a4db94011d3 | 651 | * |
sahilmgandhi | 18:6a4db94011d3 | 652 | * \param[in] module_inst Pointer to the ADC software instance struct |
sahilmgandhi | 18:6a4db94011d3 | 653 | */ |
sahilmgandhi | 18:6a4db94011d3 | 654 | static inline void adc_disable_positive_input_sequence( |
sahilmgandhi | 18:6a4db94011d3 | 655 | struct adc_module *const module_inst) |
sahilmgandhi | 18:6a4db94011d3 | 656 | { |
sahilmgandhi | 18:6a4db94011d3 | 657 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 658 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 659 | |
sahilmgandhi | 18:6a4db94011d3 | 660 | Adc *const adc_module = module_inst->hw; |
sahilmgandhi | 18:6a4db94011d3 | 661 | adc_module->SEQCTRL.reg = 0; |
sahilmgandhi | 18:6a4db94011d3 | 662 | } |
sahilmgandhi | 18:6a4db94011d3 | 663 | |
sahilmgandhi | 18:6a4db94011d3 | 664 | /** |
sahilmgandhi | 18:6a4db94011d3 | 665 | * \brief Get ADC sequence status. |
sahilmgandhi | 18:6a4db94011d3 | 666 | * |
sahilmgandhi | 18:6a4db94011d3 | 667 | * Check if a sequence is done and get last conversion done in the sequence. |
sahilmgandhi | 18:6a4db94011d3 | 668 | * |
sahilmgandhi | 18:6a4db94011d3 | 669 | * \param[in] module_inst Pointer to the ADC software instance struct |
sahilmgandhi | 18:6a4db94011d3 | 670 | * \param[out] is_sequence_busy Sequence busy status |
sahilmgandhi | 18:6a4db94011d3 | 671 | * \param[out] sequence_state This value identifies the last conversion |
sahilmgandhi | 18:6a4db94011d3 | 672 | * done in the sequence |
sahilmgandhi | 18:6a4db94011d3 | 673 | */ |
sahilmgandhi | 18:6a4db94011d3 | 674 | static inline void adc_get_sequence_status( |
sahilmgandhi | 18:6a4db94011d3 | 675 | struct adc_module *const module_inst, |
sahilmgandhi | 18:6a4db94011d3 | 676 | bool * is_sequence_busy, |
sahilmgandhi | 18:6a4db94011d3 | 677 | uint8_t *sequence_state) |
sahilmgandhi | 18:6a4db94011d3 | 678 | { |
sahilmgandhi | 18:6a4db94011d3 | 679 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 680 | Assert(module_inst); |
sahilmgandhi | 18:6a4db94011d3 | 681 | uint8_t temp = false; |
sahilmgandhi | 18:6a4db94011d3 | 682 | Adc *const adc_module = module_inst->hw; |
sahilmgandhi | 18:6a4db94011d3 | 683 | temp = adc_module->SEQSTATUS.reg; |
sahilmgandhi | 18:6a4db94011d3 | 684 | if(temp & ADC_SEQSTATUS_SEQBUSY) { |
sahilmgandhi | 18:6a4db94011d3 | 685 | *is_sequence_busy = true; |
sahilmgandhi | 18:6a4db94011d3 | 686 | } |
sahilmgandhi | 18:6a4db94011d3 | 687 | *sequence_state = temp & ADC_SEQSTATUS_SEQSTATE_Msk; |
sahilmgandhi | 18:6a4db94011d3 | 688 | } |
sahilmgandhi | 18:6a4db94011d3 | 689 | |
sahilmgandhi | 18:6a4db94011d3 | 690 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 691 | |
sahilmgandhi | 18:6a4db94011d3 | 692 | #ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE |
sahilmgandhi | 18:6a4db94011d3 | 693 | /** |
sahilmgandhi | 18:6a4db94011d3 | 694 | * \brief Set ADC master and slave mode. |
sahilmgandhi | 18:6a4db94011d3 | 695 | * |
sahilmgandhi | 18:6a4db94011d3 | 696 | * Enable ADC module Master-Slave Operation and select dual mode trigger. |
sahilmgandhi | 18:6a4db94011d3 | 697 | * |
sahilmgandhi | 18:6a4db94011d3 | 698 | * \param[in] master_inst Pointer to the master ADC software instance struct |
sahilmgandhi | 18:6a4db94011d3 | 699 | * \param[in] slave_inst Pointer to the slave ADC software instance struct |
sahilmgandhi | 18:6a4db94011d3 | 700 | * \param[in] dualsel Dual mode trigger selection |
sahilmgandhi | 18:6a4db94011d3 | 701 | * |
sahilmgandhi | 18:6a4db94011d3 | 702 | */ |
sahilmgandhi | 18:6a4db94011d3 | 703 | static inline void adc_set_master_slave_mode( |
sahilmgandhi | 18:6a4db94011d3 | 704 | struct adc_module *const master_inst, |
sahilmgandhi | 18:6a4db94011d3 | 705 | struct adc_module *const slave_inst, |
sahilmgandhi | 18:6a4db94011d3 | 706 | enum adc_dual_mode_trigger_selection dualsel) |
sahilmgandhi | 18:6a4db94011d3 | 707 | { |
sahilmgandhi | 18:6a4db94011d3 | 708 | /* Sanity check arguments */ |
sahilmgandhi | 18:6a4db94011d3 | 709 | Assert(master_inst); |
sahilmgandhi | 18:6a4db94011d3 | 710 | Assert(slave_inst); |
sahilmgandhi | 18:6a4db94011d3 | 711 | |
sahilmgandhi | 18:6a4db94011d3 | 712 | slave_inst->hw->CTRLA.reg |= ADC_CTRLA_SLAVEEN; |
sahilmgandhi | 18:6a4db94011d3 | 713 | master_inst->hw->CTRLC.reg |= dualsel; |
sahilmgandhi | 18:6a4db94011d3 | 714 | |
sahilmgandhi | 18:6a4db94011d3 | 715 | }; |
sahilmgandhi | 18:6a4db94011d3 | 716 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 717 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 718 | |
sahilmgandhi | 18:6a4db94011d3 | 719 | #ifdef __cplusplus |
sahilmgandhi | 18:6a4db94011d3 | 720 | } |
sahilmgandhi | 18:6a4db94011d3 | 721 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 722 | |
sahilmgandhi | 18:6a4db94011d3 | 723 | /** @} */ |
sahilmgandhi | 18:6a4db94011d3 | 724 | |
sahilmgandhi | 18:6a4db94011d3 | 725 | #endif /* ADC_FEATURE_H_INCLUDED */ |
sahilmgandhi | 18:6a4db94011d3 | 726 |