Mouse code for the MacroRat
mbed-dev/targets/TARGET_ARM_SSG/TARGET_MPS2/spi_def.h@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2006-2015 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | * ---------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 16 | * File: apspi.h |
sahilmgandhi | 18:6a4db94011d3 | 17 | * Release: Version 2.0 |
sahilmgandhi | 18:6a4db94011d3 | 18 | * ---------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 19 | * |
sahilmgandhi | 18:6a4db94011d3 | 20 | * SSP interface Support |
sahilmgandhi | 18:6a4db94011d3 | 21 | * ===================== |
sahilmgandhi | 18:6a4db94011d3 | 22 | */ |
sahilmgandhi | 18:6a4db94011d3 | 23 | |
sahilmgandhi | 18:6a4db94011d3 | 24 | #define SSPCS_BASE (0x4002804C) // SSP chip select register |
sahilmgandhi | 18:6a4db94011d3 | 25 | #define SSP_BASE (0x40020000) // SSP Prime Cell |
sahilmgandhi | 18:6a4db94011d3 | 26 | |
sahilmgandhi | 18:6a4db94011d3 | 27 | #define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00)) |
sahilmgandhi | 18:6a4db94011d3 | 28 | #define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04)) |
sahilmgandhi | 18:6a4db94011d3 | 29 | #define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08)) |
sahilmgandhi | 18:6a4db94011d3 | 30 | #define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C)) |
sahilmgandhi | 18:6a4db94011d3 | 31 | #define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10)) |
sahilmgandhi | 18:6a4db94011d3 | 32 | #define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14)) |
sahilmgandhi | 18:6a4db94011d3 | 33 | #define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18)) |
sahilmgandhi | 18:6a4db94011d3 | 34 | #define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C)) |
sahilmgandhi | 18:6a4db94011d3 | 35 | #define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20)) |
sahilmgandhi | 18:6a4db94011d3 | 36 | #define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24)) |
sahilmgandhi | 18:6a4db94011d3 | 37 | #define SSPCS ((volatile unsigned int *)(SSPCS_BASE)) |
sahilmgandhi | 18:6a4db94011d3 | 38 | |
sahilmgandhi | 18:6a4db94011d3 | 39 | // SSPCR0 Control register 0 |
sahilmgandhi | 18:6a4db94011d3 | 40 | #define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3 |
sahilmgandhi | 18:6a4db94011d3 | 41 | #define SSPCR0_SPH 0x0080 // SSPCLKOUT phase |
sahilmgandhi | 18:6a4db94011d3 | 42 | #define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity |
sahilmgandhi | 18:6a4db94011d3 | 43 | #define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola |
sahilmgandhi | 18:6a4db94011d3 | 44 | #define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits |
sahilmgandhi | 18:6a4db94011d3 | 45 | #define SSPCR0_DSS_16 0x000F // Data packet size, 16bits |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | // SSPCR1 Control register 1 |
sahilmgandhi | 18:6a4db94011d3 | 48 | #define SSPCR1_SOD 0x0008 // Slave Output mode Disable |
sahilmgandhi | 18:6a4db94011d3 | 49 | #define SSPCR1_MS 0x0004 // Master or Slave mode |
sahilmgandhi | 18:6a4db94011d3 | 50 | #define SSPCR1_SSE 0x0002 // Serial port enable |
sahilmgandhi | 18:6a4db94011d3 | 51 | #define SSPCR1_LBM 0x0001 // Loop Back Mode |
sahilmgandhi | 18:6a4db94011d3 | 52 | |
sahilmgandhi | 18:6a4db94011d3 | 53 | // SSPSR Status register |
sahilmgandhi | 18:6a4db94011d3 | 54 | #define SSPSR_BSY 0x0010 // Busy |
sahilmgandhi | 18:6a4db94011d3 | 55 | #define SSPSR_RFF 0x0008 // Receive FIFO full |
sahilmgandhi | 18:6a4db94011d3 | 56 | #define SSPSR_RNE 0x0004 // Receive FIFO not empty |
sahilmgandhi | 18:6a4db94011d3 | 57 | #define SSPSR_TNF 0x0002 // Transmit FIFO not full |
sahilmgandhi | 18:6a4db94011d3 | 58 | #define SSPSR_TFE 0x0001 // Transmit FIFO empty |
sahilmgandhi | 18:6a4db94011d3 | 59 | |
sahilmgandhi | 18:6a4db94011d3 | 60 | // SSPCPSR Clock prescale register |
sahilmgandhi | 18:6a4db94011d3 | 61 | #define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8 |
sahilmgandhi | 18:6a4db94011d3 | 62 | |
sahilmgandhi | 18:6a4db94011d3 | 63 | // SSPIMSC Interrupt mask set and clear register |
sahilmgandhi | 18:6a4db94011d3 | 64 | #define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked |
sahilmgandhi | 18:6a4db94011d3 | 65 | #define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked |
sahilmgandhi | 18:6a4db94011d3 | 66 | #define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked |
sahilmgandhi | 18:6a4db94011d3 | 67 | #define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked |
sahilmgandhi | 18:6a4db94011d3 | 68 | |
sahilmgandhi | 18:6a4db94011d3 | 69 | // SSPRIS Raw interrupt status register |
sahilmgandhi | 18:6a4db94011d3 | 70 | #define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 71 | #define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 72 | #define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 73 | #define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 74 | |
sahilmgandhi | 18:6a4db94011d3 | 75 | // SSPMIS Masked interrupt status register |
sahilmgandhi | 18:6a4db94011d3 | 76 | #define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 77 | #define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 78 | #define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 79 | #define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 80 | |
sahilmgandhi | 18:6a4db94011d3 | 81 | // SSPICR Interrupt clear register |
sahilmgandhi | 18:6a4db94011d3 | 82 | #define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 83 | #define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag |
sahilmgandhi | 18:6a4db94011d3 | 84 | |
sahilmgandhi | 18:6a4db94011d3 | 85 | // SSPDMACR DMA control register |
sahilmgandhi | 18:6a4db94011d3 | 86 | #define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA |
sahilmgandhi | 18:6a4db94011d3 | 87 | #define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA |
sahilmgandhi | 18:6a4db94011d3 | 88 | |
sahilmgandhi | 18:6a4db94011d3 | 89 | // SPICS register (0=Chip Select low) |
sahilmgandhi | 18:6a4db94011d3 | 90 | #define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS) |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | // SPI defaults |
sahilmgandhi | 18:6a4db94011d3 | 93 | #define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS) |
sahilmgandhi | 18:6a4db94011d3 | 94 | |
sahilmgandhi | 18:6a4db94011d3 | 95 | // EEPROM instruction set |
sahilmgandhi | 18:6a4db94011d3 | 96 | #define EEWRSR 0x0001 // Write status |
sahilmgandhi | 18:6a4db94011d3 | 97 | #define EEWRITE 0x0002 // Write data |
sahilmgandhi | 18:6a4db94011d3 | 98 | #define EEREAD 0x0003 // Read data |
sahilmgandhi | 18:6a4db94011d3 | 99 | #define EEWDI 0x0004 // Write disable |
sahilmgandhi | 18:6a4db94011d3 | 100 | #define EEWREN 0x0006 // Write enable |
sahilmgandhi | 18:6a4db94011d3 | 101 | #define EERDSR 0x0005 // Read status |
sahilmgandhi | 18:6a4db94011d3 | 102 | |
sahilmgandhi | 18:6a4db94011d3 | 103 | // EEPROM status register flags |
sahilmgandhi | 18:6a4db94011d3 | 104 | #define EERDSR_WIP 0x0001 // Write in process |
sahilmgandhi | 18:6a4db94011d3 | 105 | #define EERDSR_WEL 0x0002 // Write enable latch |
sahilmgandhi | 18:6a4db94011d3 | 106 | #define EERDSR_BP0 0x0004 // Block protect 0 |
sahilmgandhi | 18:6a4db94011d3 | 107 | #define EERDSR_BP1 0x0008 // Block protect 1 |
sahilmgandhi | 18:6a4db94011d3 | 108 | #define EERDSR_WPEN 0x0080 // Write protect enable |
sahilmgandhi | 18:6a4db94011d3 | 109 | |
sahilmgandhi | 18:6a4db94011d3 | 110 | /* ---------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 111 | * |
sahilmgandhi | 18:6a4db94011d3 | 112 | * Color LCD Support |
sahilmgandhi | 18:6a4db94011d3 | 113 | * ================= |
sahilmgandhi | 18:6a4db94011d3 | 114 | */ |
sahilmgandhi | 18:6a4db94011d3 | 115 | |
sahilmgandhi | 18:6a4db94011d3 | 116 | // Color LCD Controller Internal Register addresses |
sahilmgandhi | 18:6a4db94011d3 | 117 | #define LSSPCS_BASE (0x4002804C) // LSSP chip select register |
sahilmgandhi | 18:6a4db94011d3 | 118 | #define LSSP_BASE (0x40021000) // LSSP Prime Cell |
sahilmgandhi | 18:6a4db94011d3 | 119 | |
sahilmgandhi | 18:6a4db94011d3 | 120 | #define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00)) |
sahilmgandhi | 18:6a4db94011d3 | 121 | #define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04)) |
sahilmgandhi | 18:6a4db94011d3 | 122 | #define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08)) |
sahilmgandhi | 18:6a4db94011d3 | 123 | #define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C)) |
sahilmgandhi | 18:6a4db94011d3 | 124 | #define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10)) |
sahilmgandhi | 18:6a4db94011d3 | 125 | #define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14)) |
sahilmgandhi | 18:6a4db94011d3 | 126 | #define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18)) |
sahilmgandhi | 18:6a4db94011d3 | 127 | #define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C)) |
sahilmgandhi | 18:6a4db94011d3 | 128 | #define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20)) |
sahilmgandhi | 18:6a4db94011d3 | 129 | #define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24)) |
sahilmgandhi | 18:6a4db94011d3 | 130 | #define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE)) |
sahilmgandhi | 18:6a4db94011d3 | 131 | |
sahilmgandhi | 18:6a4db94011d3 | 132 | // LSSPCR0 Control register 0 |
sahilmgandhi | 18:6a4db94011d3 | 133 | #define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR)) |
sahilmgandhi | 18:6a4db94011d3 | 134 | #define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase |
sahilmgandhi | 18:6a4db94011d3 | 135 | #define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity |
sahilmgandhi | 18:6a4db94011d3 | 136 | #define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola |
sahilmgandhi | 18:6a4db94011d3 | 137 | #define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits |
sahilmgandhi | 18:6a4db94011d3 | 138 | #define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits |
sahilmgandhi | 18:6a4db94011d3 | 139 | |
sahilmgandhi | 18:6a4db94011d3 | 140 | // LSSPCR1 Control register 1 |
sahilmgandhi | 18:6a4db94011d3 | 141 | #define LSSPCR1_SOD 0x0008 // Slave Output mode Disable |
sahilmgandhi | 18:6a4db94011d3 | 142 | #define LSSPCR1_MS 0x0004 // Master or Slave mode |
sahilmgandhi | 18:6a4db94011d3 | 143 | #define LSSPCR1_SSE 0x0002 // Serial port enable |
sahilmgandhi | 18:6a4db94011d3 | 144 | #define LSSPCR1_LBM 0x0001 // Loop Back Mode |
sahilmgandhi | 18:6a4db94011d3 | 145 | |
sahilmgandhi | 18:6a4db94011d3 | 146 | // LSSPSR Status register |
sahilmgandhi | 18:6a4db94011d3 | 147 | #define LSSPSR_BSY 0x0010 // Busy |
sahilmgandhi | 18:6a4db94011d3 | 148 | #define LSSPSR_RFF 0x0008 // Receive FIFO full |
sahilmgandhi | 18:6a4db94011d3 | 149 | #define LSSPSR_RNE 0x0004 // Receive FIFO not empty |
sahilmgandhi | 18:6a4db94011d3 | 150 | #define LSSPSR_TNF 0x0002 // Transmit FIFO not full |
sahilmgandhi | 18:6a4db94011d3 | 151 | #define LSSPSR_TFE 0x0001 // Transmit FIFO empty |
sahilmgandhi | 18:6a4db94011d3 | 152 | |
sahilmgandhi | 18:6a4db94011d3 | 153 | // LSSPCPSR Clock prescale register |
sahilmgandhi | 18:6a4db94011d3 | 154 | #define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR) |
sahilmgandhi | 18:6a4db94011d3 | 155 | |
sahilmgandhi | 18:6a4db94011d3 | 156 | // SPICS register |
sahilmgandhi | 18:6a4db94011d3 | 157 | #define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS) |
sahilmgandhi | 18:6a4db94011d3 | 158 | #define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS) |
sahilmgandhi | 18:6a4db94011d3 | 159 | #define LCD_RESET 0x0008 // RESET (CLCD_RESET) |
sahilmgandhi | 18:6a4db94011d3 | 160 | #define LCD_RS 0x0010 // RS (CLCD_RS) |
sahilmgandhi | 18:6a4db94011d3 | 161 | #define LCD_RD 0x0020 // RD (CLCD_RD) |
sahilmgandhi | 18:6a4db94011d3 | 162 | #define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL) |
sahilmgandhi | 18:6a4db94011d3 | 163 | |
sahilmgandhi | 18:6a4db94011d3 | 164 | // SPI defaults |
sahilmgandhi | 18:6a4db94011d3 | 165 | #define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS) |
sahilmgandhi | 18:6a4db94011d3 | 166 | #define LSPI_START (0x70) // Start byte for SPI transfer |
sahilmgandhi | 18:6a4db94011d3 | 167 | #define LSPI_RD (0x01) // WR bit 1 within start |
sahilmgandhi | 18:6a4db94011d3 | 168 | #define LSPI_WR (0x00) // WR bit 0 within start |
sahilmgandhi | 18:6a4db94011d3 | 169 | #define LSPI_DATA (0x02) // RS bit 1 within start byte |
sahilmgandhi | 18:6a4db94011d3 | 170 | #define LSPI_INDEX (0x00) // RS bit 0 within start byte |
sahilmgandhi | 18:6a4db94011d3 | 171 | |
sahilmgandhi | 18:6a4db94011d3 | 172 | // Screen size |
sahilmgandhi | 18:6a4db94011d3 | 173 | #define LCD_WIDTH 320 // Screen Width (in pixels) |
sahilmgandhi | 18:6a4db94011d3 | 174 | #define LCD_HEIGHT 240 // Screen Height (in pixels) |