Mouse code for the MacroRat
mbed-dev/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/cmsis_nvic.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* MPS2 CMSIS Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * |
sahilmgandhi | 18:6a4db94011d3 | 3 | * Copyright (c) 2006-2016 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 4 | * All rights reserved. |
sahilmgandhi | 18:6a4db94011d3 | 5 | * |
sahilmgandhi | 18:6a4db94011d3 | 6 | * Redistribution and use in source and binary forms, with or without |
sahilmgandhi | 18:6a4db94011d3 | 7 | * modification, are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 10 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 11 | * |
sahilmgandhi | 18:6a4db94011d3 | 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 13 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 14 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 15 | * |
sahilmgandhi | 18:6a4db94011d3 | 16 | * 3. Neither the name of the copyright holder nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 17 | * may be used to endorse or promote products derived from this software without |
sahilmgandhi | 18:6a4db94011d3 | 18 | * specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 19 | * |
sahilmgandhi | 18:6a4db94011d3 | 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 21 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
sahilmgandhi | 18:6a4db94011d3 | 23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
sahilmgandhi | 18:6a4db94011d3 | 24 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
sahilmgandhi | 18:6a4db94011d3 | 25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
sahilmgandhi | 18:6a4db94011d3 | 26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
sahilmgandhi | 18:6a4db94011d3 | 27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
sahilmgandhi | 18:6a4db94011d3 | 28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
sahilmgandhi | 18:6a4db94011d3 | 29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
sahilmgandhi | 18:6a4db94011d3 | 30 | * POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 31 | ******************************************************************************* |
sahilmgandhi | 18:6a4db94011d3 | 32 | * CMSIS-style functionality to support dynamic vectors |
sahilmgandhi | 18:6a4db94011d3 | 33 | *******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 34 | #include "cmsis_nvic.h" |
sahilmgandhi | 18:6a4db94011d3 | 35 | |
sahilmgandhi | 18:6a4db94011d3 | 36 | #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM |
sahilmgandhi | 18:6a4db94011d3 | 37 | #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash |
sahilmgandhi | 18:6a4db94011d3 | 38 | |
sahilmgandhi | 18:6a4db94011d3 | 39 | void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { |
sahilmgandhi | 18:6a4db94011d3 | 40 | uint32_t *vectors = (uint32_t*)SCB->VTOR; |
sahilmgandhi | 18:6a4db94011d3 | 41 | uint32_t i; |
sahilmgandhi | 18:6a4db94011d3 | 42 | |
sahilmgandhi | 18:6a4db94011d3 | 43 | // Copy and switch to dynamic vectors if the first time called |
sahilmgandhi | 18:6a4db94011d3 | 44 | if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { |
sahilmgandhi | 18:6a4db94011d3 | 45 | uint32_t *old_vectors = vectors; |
sahilmgandhi | 18:6a4db94011d3 | 46 | vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; |
sahilmgandhi | 18:6a4db94011d3 | 47 | for (i=0; i<NVIC_NUM_VECTORS; i++) { |
sahilmgandhi | 18:6a4db94011d3 | 48 | vectors[i] = old_vectors[i]; |
sahilmgandhi | 18:6a4db94011d3 | 49 | } |
sahilmgandhi | 18:6a4db94011d3 | 50 | SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; |
sahilmgandhi | 18:6a4db94011d3 | 51 | } |
sahilmgandhi | 18:6a4db94011d3 | 52 | vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
sahilmgandhi | 18:6a4db94011d3 | 53 | } |
sahilmgandhi | 18:6a4db94011d3 | 54 | |
sahilmgandhi | 18:6a4db94011d3 | 55 | uint32_t NVIC_GetVector(IRQn_Type IRQn) { |
sahilmgandhi | 18:6a4db94011d3 | 56 | uint32_t *vectors = (uint32_t*)SCB->VTOR; |
sahilmgandhi | 18:6a4db94011d3 | 57 | return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; |
sahilmgandhi | 18:6a4db94011d3 | 58 | } |