Mouse code for the MacroRat
mbed-dev/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/cmsis_nvic.c@18:6a4db94011d3, 2017-05-14 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sun May 14 23:18:57 2017 +0000
- Revision:
- 18:6a4db94011d3
Publishing again
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /* mbed Microcontroller Library |
sahilmgandhi | 18:6a4db94011d3 | 2 | * Copyright (c) 2015-2016 ARM Limited |
sahilmgandhi | 18:6a4db94011d3 | 3 | * |
sahilmgandhi | 18:6a4db94011d3 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
sahilmgandhi | 18:6a4db94011d3 | 5 | * you may not use this file except in compliance with the License. |
sahilmgandhi | 18:6a4db94011d3 | 6 | * You may obtain a copy of the License at |
sahilmgandhi | 18:6a4db94011d3 | 7 | * |
sahilmgandhi | 18:6a4db94011d3 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
sahilmgandhi | 18:6a4db94011d3 | 9 | * |
sahilmgandhi | 18:6a4db94011d3 | 10 | * Unless required by applicable law or agreed to in writing, software |
sahilmgandhi | 18:6a4db94011d3 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
sahilmgandhi | 18:6a4db94011d3 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
sahilmgandhi | 18:6a4db94011d3 | 13 | * See the License for the specific language governing permissions and |
sahilmgandhi | 18:6a4db94011d3 | 14 | * limitations under the License. |
sahilmgandhi | 18:6a4db94011d3 | 15 | */ |
sahilmgandhi | 18:6a4db94011d3 | 16 | /* |
sahilmgandhi | 18:6a4db94011d3 | 17 | * CMSIS-style functionality to support dynamic vectors |
sahilmgandhi | 18:6a4db94011d3 | 18 | */ |
sahilmgandhi | 18:6a4db94011d3 | 19 | #include "cmsis_nvic.h" |
sahilmgandhi | 18:6a4db94011d3 | 20 | |
sahilmgandhi | 18:6a4db94011d3 | 21 | #define NVIC_RAM_VECTOR_ADDRESS (0x20000000) //Location of vectors in RAM |
sahilmgandhi | 18:6a4db94011d3 | 22 | #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) //Initial vector position in flash |
sahilmgandhi | 18:6a4db94011d3 | 23 | |
sahilmgandhi | 18:6a4db94011d3 | 24 | void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { |
sahilmgandhi | 18:6a4db94011d3 | 25 | uint32_t *vectors = (uint32_t*)SCB->VTOR; |
sahilmgandhi | 18:6a4db94011d3 | 26 | uint32_t i; |
sahilmgandhi | 18:6a4db94011d3 | 27 | |
sahilmgandhi | 18:6a4db94011d3 | 28 | // Copy and switch to dynamic vectors if the first time called |
sahilmgandhi | 18:6a4db94011d3 | 29 | if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { |
sahilmgandhi | 18:6a4db94011d3 | 30 | uint32_t *old_vectors = vectors; |
sahilmgandhi | 18:6a4db94011d3 | 31 | vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; |
sahilmgandhi | 18:6a4db94011d3 | 32 | for (i=0; i<NVIC_NUM_VECTORS; i++) { |
sahilmgandhi | 18:6a4db94011d3 | 33 | vectors[i] = old_vectors[i]; |
sahilmgandhi | 18:6a4db94011d3 | 34 | } |
sahilmgandhi | 18:6a4db94011d3 | 35 | SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; |
sahilmgandhi | 18:6a4db94011d3 | 36 | } |
sahilmgandhi | 18:6a4db94011d3 | 37 | vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
sahilmgandhi | 18:6a4db94011d3 | 38 | } |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | uint32_t __NVIC_GetVector(IRQn_Type IRQn) { |
sahilmgandhi | 18:6a4db94011d3 | 41 | uint32_t *vectors = (uint32_t*)SCB->VTOR; |
sahilmgandhi | 18:6a4db94011d3 | 42 | return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; |
sahilmgandhi | 18:6a4db94011d3 | 43 | } |