MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_rtcc.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file efr32mg1p_rtcc.h
sahilmgandhi 18:6a4db94011d3 3 * @brief EFR32MG1P_RTCC register and bit field definitions
sahilmgandhi 18:6a4db94011d3 4 * @version 5.1.2
sahilmgandhi 18:6a4db94011d3 5 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 6 * @section License
sahilmgandhi 18:6a4db94011d3 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Permission is granted to anyone to use this software for any purpose,
sahilmgandhi 18:6a4db94011d3 11 * including commercial applications, and to alter it and redistribute it
sahilmgandhi 18:6a4db94011d3 12 * freely, subject to the following restrictions:
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * 1. The origin of this software must not be misrepresented; you must not
sahilmgandhi 18:6a4db94011d3 15 * claim that you wrote the original software.@n
sahilmgandhi 18:6a4db94011d3 16 * 2. Altered source versions must be plainly marked as such, and must not be
sahilmgandhi 18:6a4db94011d3 17 * misrepresented as being the original software.@n
sahilmgandhi 18:6a4db94011d3 18 * 3. This notice may not be removed or altered from any source distribution.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
sahilmgandhi 18:6a4db94011d3 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
sahilmgandhi 18:6a4db94011d3 22 * providing the Software "AS IS", with no express or implied warranties of any
sahilmgandhi 18:6a4db94011d3 23 * kind, including, but not limited to, any implied warranties of
sahilmgandhi 18:6a4db94011d3 24 * merchantability or fitness for any particular purpose or warranties against
sahilmgandhi 18:6a4db94011d3 25 * infringement of any proprietary rights of a third party.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
sahilmgandhi 18:6a4db94011d3 28 * incidental, or special damages, or any other relief, or for any claim by
sahilmgandhi 18:6a4db94011d3 29 * any third party, arising from your use of this Software.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 32 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 33 * @addtogroup Parts
sahilmgandhi 18:6a4db94011d3 34 * @{
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 36 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 37 * @defgroup EFR32MG1P_RTCC
sahilmgandhi 18:6a4db94011d3 38 * @{
sahilmgandhi 18:6a4db94011d3 39 * @brief EFR32MG1P_RTCC Register Declaration
sahilmgandhi 18:6a4db94011d3 40 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 41 typedef struct
sahilmgandhi 18:6a4db94011d3 42 {
sahilmgandhi 18:6a4db94011d3 43 __IOM uint32_t CTRL; /**< Control Register */
sahilmgandhi 18:6a4db94011d3 44 __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */
sahilmgandhi 18:6a4db94011d3 45 __IOM uint32_t CNT; /**< Counter Value Register */
sahilmgandhi 18:6a4db94011d3 46 __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */
sahilmgandhi 18:6a4db94011d3 47 __IOM uint32_t TIME; /**< Time of day register */
sahilmgandhi 18:6a4db94011d3 48 __IOM uint32_t DATE; /**< Date register */
sahilmgandhi 18:6a4db94011d3 49 __IM uint32_t IF; /**< RTCC Interrupt Flags */
sahilmgandhi 18:6a4db94011d3 50 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
sahilmgandhi 18:6a4db94011d3 51 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
sahilmgandhi 18:6a4db94011d3 52 __IOM uint32_t IEN; /**< Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 53 __IM uint32_t STATUS; /**< Status register */
sahilmgandhi 18:6a4db94011d3 54 __IOM uint32_t CMD; /**< Command Register */
sahilmgandhi 18:6a4db94011d3 55 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
sahilmgandhi 18:6a4db94011d3 56 __IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */
sahilmgandhi 18:6a4db94011d3 57 __IOM uint32_t LOCK; /**< Configuration Lock Register */
sahilmgandhi 18:6a4db94011d3 58 __IOM uint32_t EM4WUEN; /**< Wake Up Enable */
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 uint32_t RESERVED0[37]; /**< Reserved registers */
sahilmgandhi 18:6a4db94011d3 63 RTCC_RET_TypeDef RET[32]; /**< RetentionReg */
sahilmgandhi 18:6a4db94011d3 64 } RTCC_TypeDef; /** @} */
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 67 * @defgroup EFR32MG1P_RTCC_BitFields
sahilmgandhi 18:6a4db94011d3 68 * @{
sahilmgandhi 18:6a4db94011d3 69 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /* Bit fields for RTCC CTRL */
sahilmgandhi 18:6a4db94011d3 72 #define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 73 #define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 74 #define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */
sahilmgandhi 18:6a4db94011d3 75 #define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */
sahilmgandhi 18:6a4db94011d3 76 #define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */
sahilmgandhi 18:6a4db94011d3 77 #define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 78 #define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 79 #define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */
sahilmgandhi 18:6a4db94011d3 80 #define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */
sahilmgandhi 18:6a4db94011d3 81 #define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */
sahilmgandhi 18:6a4db94011d3 82 #define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 83 #define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 84 #define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */
sahilmgandhi 18:6a4db94011d3 85 #define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */
sahilmgandhi 18:6a4db94011d3 86 #define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */
sahilmgandhi 18:6a4db94011d3 87 #define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 88 #define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 89 #define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */
sahilmgandhi 18:6a4db94011d3 90 #define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */
sahilmgandhi 18:6a4db94011d3 91 #define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */
sahilmgandhi 18:6a4db94011d3 92 #define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 93 #define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 94 #define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */
sahilmgandhi 18:6a4db94011d3 95 #define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */
sahilmgandhi 18:6a4db94011d3 96 #define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 97 #define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 98 #define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 99 #define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 100 #define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 101 #define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 102 #define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 103 #define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 104 #define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 105 #define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 106 #define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 107 #define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 108 #define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 109 #define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 110 #define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 111 #define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 112 #define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 113 #define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 114 #define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 115 #define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 116 #define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 117 #define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 118 #define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 119 #define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 120 #define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 121 #define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 122 #define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 123 #define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 124 #define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 125 #define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 126 #define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 127 #define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 128 #define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 129 #define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 130 #define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */
sahilmgandhi 18:6a4db94011d3 131 #define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 132 #define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 133 #define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 134 #define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 135 #define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 136 #define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 137 #define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 138 #define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 139 #define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */
sahilmgandhi 18:6a4db94011d3 140 #define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */
sahilmgandhi 18:6a4db94011d3 141 #define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */
sahilmgandhi 18:6a4db94011d3 142 #define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 143 #define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 144 #define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */
sahilmgandhi 18:6a4db94011d3 145 #define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */
sahilmgandhi 18:6a4db94011d3 146 #define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */
sahilmgandhi 18:6a4db94011d3 147 #define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 148 #define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 149 #define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 150 #define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 151 #define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 152 #define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 153 #define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */
sahilmgandhi 18:6a4db94011d3 154 #define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */
sahilmgandhi 18:6a4db94011d3 155 #define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */
sahilmgandhi 18:6a4db94011d3 156 #define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 157 #define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 /* Bit fields for RTCC PRECNT */
sahilmgandhi 18:6a4db94011d3 160 #define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */
sahilmgandhi 18:6a4db94011d3 161 #define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */
sahilmgandhi 18:6a4db94011d3 162 #define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
sahilmgandhi 18:6a4db94011d3 163 #define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
sahilmgandhi 18:6a4db94011d3 164 #define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */
sahilmgandhi 18:6a4db94011d3 165 #define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /* Bit fields for RTCC CNT */
sahilmgandhi 18:6a4db94011d3 168 #define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */
sahilmgandhi 18:6a4db94011d3 169 #define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */
sahilmgandhi 18:6a4db94011d3 170 #define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */
sahilmgandhi 18:6a4db94011d3 171 #define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */
sahilmgandhi 18:6a4db94011d3 172 #define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */
sahilmgandhi 18:6a4db94011d3 173 #define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /* Bit fields for RTCC COMBCNT */
sahilmgandhi 18:6a4db94011d3 176 #define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */
sahilmgandhi 18:6a4db94011d3 177 #define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */
sahilmgandhi 18:6a4db94011d3 178 #define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */
sahilmgandhi 18:6a4db94011d3 179 #define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */
sahilmgandhi 18:6a4db94011d3 180 #define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
sahilmgandhi 18:6a4db94011d3 181 #define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
sahilmgandhi 18:6a4db94011d3 182 #define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */
sahilmgandhi 18:6a4db94011d3 183 #define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */
sahilmgandhi 18:6a4db94011d3 184 #define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */
sahilmgandhi 18:6a4db94011d3 185 #define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /* Bit fields for RTCC TIME */
sahilmgandhi 18:6a4db94011d3 188 #define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 189 #define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 190 #define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */
sahilmgandhi 18:6a4db94011d3 191 #define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */
sahilmgandhi 18:6a4db94011d3 192 #define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 193 #define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 194 #define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */
sahilmgandhi 18:6a4db94011d3 195 #define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */
sahilmgandhi 18:6a4db94011d3 196 #define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 197 #define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 198 #define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */
sahilmgandhi 18:6a4db94011d3 199 #define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */
sahilmgandhi 18:6a4db94011d3 200 #define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 201 #define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 202 #define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */
sahilmgandhi 18:6a4db94011d3 203 #define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */
sahilmgandhi 18:6a4db94011d3 204 #define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 205 #define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 206 #define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */
sahilmgandhi 18:6a4db94011d3 207 #define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */
sahilmgandhi 18:6a4db94011d3 208 #define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 209 #define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 210 #define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */
sahilmgandhi 18:6a4db94011d3 211 #define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */
sahilmgandhi 18:6a4db94011d3 212 #define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 213 #define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 /* Bit fields for RTCC DATE */
sahilmgandhi 18:6a4db94011d3 216 #define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 217 #define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 218 #define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */
sahilmgandhi 18:6a4db94011d3 219 #define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */
sahilmgandhi 18:6a4db94011d3 220 #define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 221 #define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 222 #define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */
sahilmgandhi 18:6a4db94011d3 223 #define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */
sahilmgandhi 18:6a4db94011d3 224 #define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 225 #define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 226 #define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */
sahilmgandhi 18:6a4db94011d3 227 #define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */
sahilmgandhi 18:6a4db94011d3 228 #define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 229 #define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 230 #define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
sahilmgandhi 18:6a4db94011d3 231 #define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */
sahilmgandhi 18:6a4db94011d3 232 #define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */
sahilmgandhi 18:6a4db94011d3 233 #define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 234 #define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 235 #define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */
sahilmgandhi 18:6a4db94011d3 236 #define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */
sahilmgandhi 18:6a4db94011d3 237 #define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 238 #define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 239 #define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */
sahilmgandhi 18:6a4db94011d3 240 #define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */
sahilmgandhi 18:6a4db94011d3 241 #define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 242 #define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 243 #define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */
sahilmgandhi 18:6a4db94011d3 244 #define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */
sahilmgandhi 18:6a4db94011d3 245 #define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 246 #define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /* Bit fields for RTCC IF */
sahilmgandhi 18:6a4db94011d3 249 #define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 250 #define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 251 #define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 252 #define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */
sahilmgandhi 18:6a4db94011d3 253 #define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
sahilmgandhi 18:6a4db94011d3 254 #define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 255 #define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 256 #define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 257 #define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
sahilmgandhi 18:6a4db94011d3 258 #define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
sahilmgandhi 18:6a4db94011d3 259 #define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 260 #define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 261 #define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 262 #define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
sahilmgandhi 18:6a4db94011d3 263 #define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
sahilmgandhi 18:6a4db94011d3 264 #define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 265 #define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 266 #define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 267 #define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
sahilmgandhi 18:6a4db94011d3 268 #define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
sahilmgandhi 18:6a4db94011d3 269 #define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 270 #define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 271 #define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 272 #define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
sahilmgandhi 18:6a4db94011d3 273 #define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
sahilmgandhi 18:6a4db94011d3 274 #define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 275 #define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 276 #define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */
sahilmgandhi 18:6a4db94011d3 277 #define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 278 #define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 279 #define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 280 #define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 281 #define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */
sahilmgandhi 18:6a4db94011d3 282 #define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
sahilmgandhi 18:6a4db94011d3 283 #define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
sahilmgandhi 18:6a4db94011d3 284 #define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 285 #define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 286 #define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */
sahilmgandhi 18:6a4db94011d3 287 #define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
sahilmgandhi 18:6a4db94011d3 288 #define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
sahilmgandhi 18:6a4db94011d3 289 #define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 290 #define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 291 #define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */
sahilmgandhi 18:6a4db94011d3 292 #define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
sahilmgandhi 18:6a4db94011d3 293 #define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
sahilmgandhi 18:6a4db94011d3 294 #define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 295 #define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 296 #define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */
sahilmgandhi 18:6a4db94011d3 297 #define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
sahilmgandhi 18:6a4db94011d3 298 #define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
sahilmgandhi 18:6a4db94011d3 299 #define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 300 #define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 301 #define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */
sahilmgandhi 18:6a4db94011d3 302 #define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
sahilmgandhi 18:6a4db94011d3 303 #define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
sahilmgandhi 18:6a4db94011d3 304 #define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 305 #define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Bit fields for RTCC IFS */
sahilmgandhi 18:6a4db94011d3 308 #define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 309 #define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 310 #define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 311 #define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */
sahilmgandhi 18:6a4db94011d3 312 #define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
sahilmgandhi 18:6a4db94011d3 313 #define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 314 #define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 315 #define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 316 #define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
sahilmgandhi 18:6a4db94011d3 317 #define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
sahilmgandhi 18:6a4db94011d3 318 #define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 319 #define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 320 #define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 321 #define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
sahilmgandhi 18:6a4db94011d3 322 #define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
sahilmgandhi 18:6a4db94011d3 323 #define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 324 #define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 325 #define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 326 #define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
sahilmgandhi 18:6a4db94011d3 327 #define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
sahilmgandhi 18:6a4db94011d3 328 #define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 329 #define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 330 #define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 331 #define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
sahilmgandhi 18:6a4db94011d3 332 #define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
sahilmgandhi 18:6a4db94011d3 333 #define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 334 #define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 335 #define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 336 #define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 337 #define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 338 #define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 339 #define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 340 #define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 341 #define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
sahilmgandhi 18:6a4db94011d3 342 #define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
sahilmgandhi 18:6a4db94011d3 343 #define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 344 #define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 345 #define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 346 #define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
sahilmgandhi 18:6a4db94011d3 347 #define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
sahilmgandhi 18:6a4db94011d3 348 #define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 349 #define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 350 #define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 351 #define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
sahilmgandhi 18:6a4db94011d3 352 #define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
sahilmgandhi 18:6a4db94011d3 353 #define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 354 #define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 355 #define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 356 #define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
sahilmgandhi 18:6a4db94011d3 357 #define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
sahilmgandhi 18:6a4db94011d3 358 #define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 359 #define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 360 #define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 361 #define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
sahilmgandhi 18:6a4db94011d3 362 #define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
sahilmgandhi 18:6a4db94011d3 363 #define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 364 #define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /* Bit fields for RTCC IFC */
sahilmgandhi 18:6a4db94011d3 367 #define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 368 #define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 369 #define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 370 #define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */
sahilmgandhi 18:6a4db94011d3 371 #define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
sahilmgandhi 18:6a4db94011d3 372 #define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 373 #define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 374 #define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 375 #define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
sahilmgandhi 18:6a4db94011d3 376 #define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
sahilmgandhi 18:6a4db94011d3 377 #define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 378 #define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 379 #define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 380 #define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
sahilmgandhi 18:6a4db94011d3 381 #define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
sahilmgandhi 18:6a4db94011d3 382 #define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 383 #define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 384 #define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 385 #define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
sahilmgandhi 18:6a4db94011d3 386 #define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
sahilmgandhi 18:6a4db94011d3 387 #define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 388 #define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 389 #define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 390 #define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
sahilmgandhi 18:6a4db94011d3 391 #define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
sahilmgandhi 18:6a4db94011d3 392 #define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 393 #define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 394 #define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 395 #define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 396 #define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 397 #define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 398 #define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 399 #define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 400 #define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
sahilmgandhi 18:6a4db94011d3 401 #define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
sahilmgandhi 18:6a4db94011d3 402 #define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 403 #define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 404 #define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 405 #define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
sahilmgandhi 18:6a4db94011d3 406 #define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
sahilmgandhi 18:6a4db94011d3 407 #define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 408 #define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 409 #define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 410 #define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
sahilmgandhi 18:6a4db94011d3 411 #define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
sahilmgandhi 18:6a4db94011d3 412 #define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 413 #define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 414 #define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 415 #define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
sahilmgandhi 18:6a4db94011d3 416 #define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
sahilmgandhi 18:6a4db94011d3 417 #define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 418 #define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 419 #define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 420 #define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
sahilmgandhi 18:6a4db94011d3 421 #define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
sahilmgandhi 18:6a4db94011d3 422 #define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 423 #define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 /* Bit fields for RTCC IEN */
sahilmgandhi 18:6a4db94011d3 426 #define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 427 #define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 428 #define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 429 #define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */
sahilmgandhi 18:6a4db94011d3 430 #define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */
sahilmgandhi 18:6a4db94011d3 431 #define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 432 #define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 433 #define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 434 #define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */
sahilmgandhi 18:6a4db94011d3 435 #define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */
sahilmgandhi 18:6a4db94011d3 436 #define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 437 #define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 438 #define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 439 #define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */
sahilmgandhi 18:6a4db94011d3 440 #define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */
sahilmgandhi 18:6a4db94011d3 441 #define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 442 #define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 443 #define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 444 #define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */
sahilmgandhi 18:6a4db94011d3 445 #define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */
sahilmgandhi 18:6a4db94011d3 446 #define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 447 #define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 448 #define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 449 #define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */
sahilmgandhi 18:6a4db94011d3 450 #define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */
sahilmgandhi 18:6a4db94011d3 451 #define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 452 #define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 453 #define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 454 #define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 455 #define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */
sahilmgandhi 18:6a4db94011d3 456 #define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 457 #define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 458 #define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 459 #define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */
sahilmgandhi 18:6a4db94011d3 460 #define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */
sahilmgandhi 18:6a4db94011d3 461 #define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 462 #define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 463 #define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 464 #define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */
sahilmgandhi 18:6a4db94011d3 465 #define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */
sahilmgandhi 18:6a4db94011d3 466 #define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 467 #define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 468 #define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 469 #define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */
sahilmgandhi 18:6a4db94011d3 470 #define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */
sahilmgandhi 18:6a4db94011d3 471 #define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 472 #define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 473 #define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 474 #define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */
sahilmgandhi 18:6a4db94011d3 475 #define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */
sahilmgandhi 18:6a4db94011d3 476 #define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 477 #define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 478 #define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 479 #define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */
sahilmgandhi 18:6a4db94011d3 480 #define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */
sahilmgandhi 18:6a4db94011d3 481 #define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 482 #define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 /* Bit fields for RTCC STATUS */
sahilmgandhi 18:6a4db94011d3 485 #define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */
sahilmgandhi 18:6a4db94011d3 486 #define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 /* Bit fields for RTCC CMD */
sahilmgandhi 18:6a4db94011d3 489 #define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */
sahilmgandhi 18:6a4db94011d3 490 #define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */
sahilmgandhi 18:6a4db94011d3 491 #define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */
sahilmgandhi 18:6a4db94011d3 492 #define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */
sahilmgandhi 18:6a4db94011d3 493 #define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */
sahilmgandhi 18:6a4db94011d3 494 #define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */
sahilmgandhi 18:6a4db94011d3 495 #define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /* Bit fields for RTCC SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 498 #define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 499 #define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 500 #define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */
sahilmgandhi 18:6a4db94011d3 501 #define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */
sahilmgandhi 18:6a4db94011d3 502 #define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */
sahilmgandhi 18:6a4db94011d3 503 #define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 504 #define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /* Bit fields for RTCC POWERDOWN */
sahilmgandhi 18:6a4db94011d3 507 #define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */
sahilmgandhi 18:6a4db94011d3 508 #define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */
sahilmgandhi 18:6a4db94011d3 509 #define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */
sahilmgandhi 18:6a4db94011d3 510 #define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */
sahilmgandhi 18:6a4db94011d3 511 #define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */
sahilmgandhi 18:6a4db94011d3 512 #define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */
sahilmgandhi 18:6a4db94011d3 513 #define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */
sahilmgandhi 18:6a4db94011d3 514
sahilmgandhi 18:6a4db94011d3 515 /* Bit fields for RTCC LOCK */
sahilmgandhi 18:6a4db94011d3 516 #define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 517 #define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 518 #define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 519 #define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 520 #define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 521 #define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 522 #define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 523 #define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 524 #define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 525 #define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 526 #define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 527 #define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 528 #define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 529 #define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 /* Bit fields for RTCC EM4WUEN */
sahilmgandhi 18:6a4db94011d3 532 #define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */
sahilmgandhi 18:6a4db94011d3 533 #define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */
sahilmgandhi 18:6a4db94011d3 534 #define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */
sahilmgandhi 18:6a4db94011d3 535 #define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */
sahilmgandhi 18:6a4db94011d3 536 #define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */
sahilmgandhi 18:6a4db94011d3 537 #define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */
sahilmgandhi 18:6a4db94011d3 538 #define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */
sahilmgandhi 18:6a4db94011d3 539
sahilmgandhi 18:6a4db94011d3 540 /* Bit fields for RTCC CC_CTRL */
sahilmgandhi 18:6a4db94011d3 541 #define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 542 #define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 543 #define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */
sahilmgandhi 18:6a4db94011d3 544 #define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */
sahilmgandhi 18:6a4db94011d3 545 #define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 546 #define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 547 #define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 548 #define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 549 #define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 550 #define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 551 #define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 552 #define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 553 #define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */
sahilmgandhi 18:6a4db94011d3 554 #define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */
sahilmgandhi 18:6a4db94011d3 555 #define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 556 #define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 557 #define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 558 #define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 559 #define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 560 #define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 561 #define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 562 #define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 563 #define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 564 #define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 565 #define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */
sahilmgandhi 18:6a4db94011d3 566 #define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */
sahilmgandhi 18:6a4db94011d3 567 #define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 568 #define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 569 #define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 570 #define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 571 #define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 572 #define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 573 #define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 574 #define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 575 #define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 576 #define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 577 #define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */
sahilmgandhi 18:6a4db94011d3 578 #define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */
sahilmgandhi 18:6a4db94011d3 579 #define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 580 #define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 581 #define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 582 #define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 583 #define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 584 #define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 585 #define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 586 #define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 587 #define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 588 #define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 589 #define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 590 #define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 591 #define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 592 #define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 593 #define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 594 #define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 595 #define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 596 #define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 597 #define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 598 #define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 599 #define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 600 #define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 601 #define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 602 #define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 603 #define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 604 #define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 605 #define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */
sahilmgandhi 18:6a4db94011d3 606 #define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */
sahilmgandhi 18:6a4db94011d3 607 #define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */
sahilmgandhi 18:6a4db94011d3 608 #define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 609 #define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 610 #define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 611 #define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 612 #define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 613 #define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 614 #define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */
sahilmgandhi 18:6a4db94011d3 615 #define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */
sahilmgandhi 18:6a4db94011d3 616 #define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 617 #define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 618 #define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */
sahilmgandhi 18:6a4db94011d3 619 #define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */
sahilmgandhi 18:6a4db94011d3 620 #define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */
sahilmgandhi 18:6a4db94011d3 621 #define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 622 #define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 623 #define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 624 #define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 625 #define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 626 #define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */
sahilmgandhi 18:6a4db94011d3 627
sahilmgandhi 18:6a4db94011d3 628 /* Bit fields for RTCC CC_CCV */
sahilmgandhi 18:6a4db94011d3 629 #define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */
sahilmgandhi 18:6a4db94011d3 630 #define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */
sahilmgandhi 18:6a4db94011d3 631 #define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */
sahilmgandhi 18:6a4db94011d3 632 #define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */
sahilmgandhi 18:6a4db94011d3 633 #define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */
sahilmgandhi 18:6a4db94011d3 634 #define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */
sahilmgandhi 18:6a4db94011d3 635
sahilmgandhi 18:6a4db94011d3 636 /* Bit fields for RTCC CC_TIME */
sahilmgandhi 18:6a4db94011d3 637 #define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 638 #define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 639 #define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */
sahilmgandhi 18:6a4db94011d3 640 #define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */
sahilmgandhi 18:6a4db94011d3 641 #define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 642 #define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 643 #define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */
sahilmgandhi 18:6a4db94011d3 644 #define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */
sahilmgandhi 18:6a4db94011d3 645 #define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 646 #define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 647 #define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */
sahilmgandhi 18:6a4db94011d3 648 #define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */
sahilmgandhi 18:6a4db94011d3 649 #define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 650 #define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 651 #define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */
sahilmgandhi 18:6a4db94011d3 652 #define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */
sahilmgandhi 18:6a4db94011d3 653 #define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 654 #define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 655 #define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */
sahilmgandhi 18:6a4db94011d3 656 #define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */
sahilmgandhi 18:6a4db94011d3 657 #define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 658 #define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 659 #define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */
sahilmgandhi 18:6a4db94011d3 660 #define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */
sahilmgandhi 18:6a4db94011d3 661 #define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 662 #define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 /* Bit fields for RTCC CC_DATE */
sahilmgandhi 18:6a4db94011d3 665 #define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 666 #define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 667 #define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */
sahilmgandhi 18:6a4db94011d3 668 #define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */
sahilmgandhi 18:6a4db94011d3 669 #define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 670 #define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 671 #define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */
sahilmgandhi 18:6a4db94011d3 672 #define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */
sahilmgandhi 18:6a4db94011d3 673 #define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 674 #define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 675 #define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */
sahilmgandhi 18:6a4db94011d3 676 #define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */
sahilmgandhi 18:6a4db94011d3 677 #define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 678 #define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 679 #define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */
sahilmgandhi 18:6a4db94011d3 680 #define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */
sahilmgandhi 18:6a4db94011d3 681 #define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */
sahilmgandhi 18:6a4db94011d3 682 #define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 683 #define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 /* Bit fields for RTCC RET_REG */
sahilmgandhi 18:6a4db94011d3 686 #define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */
sahilmgandhi 18:6a4db94011d3 687 #define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */
sahilmgandhi 18:6a4db94011d3 688 #define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */
sahilmgandhi 18:6a4db94011d3 689 #define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */
sahilmgandhi 18:6a4db94011d3 690 #define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */
sahilmgandhi 18:6a4db94011d3 691 #define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */
sahilmgandhi 18:6a4db94011d3 692
sahilmgandhi 18:6a4db94011d3 693 /** @} End of group EFR32MG1P_RTCC */
sahilmgandhi 18:6a4db94011d3 694 /** @} End of group Parts */
sahilmgandhi 18:6a4db94011d3 695