MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_emu.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file efr32mg1p_emu.h
sahilmgandhi 18:6a4db94011d3 3 * @brief EFR32MG1P_EMU register and bit field definitions
sahilmgandhi 18:6a4db94011d3 4 * @version 5.1.2
sahilmgandhi 18:6a4db94011d3 5 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 6 * @section License
sahilmgandhi 18:6a4db94011d3 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Permission is granted to anyone to use this software for any purpose,
sahilmgandhi 18:6a4db94011d3 11 * including commercial applications, and to alter it and redistribute it
sahilmgandhi 18:6a4db94011d3 12 * freely, subject to the following restrictions:
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * 1. The origin of this software must not be misrepresented; you must not
sahilmgandhi 18:6a4db94011d3 15 * claim that you wrote the original software.@n
sahilmgandhi 18:6a4db94011d3 16 * 2. Altered source versions must be plainly marked as such, and must not be
sahilmgandhi 18:6a4db94011d3 17 * misrepresented as being the original software.@n
sahilmgandhi 18:6a4db94011d3 18 * 3. This notice may not be removed or altered from any source distribution.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
sahilmgandhi 18:6a4db94011d3 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
sahilmgandhi 18:6a4db94011d3 22 * providing the Software "AS IS", with no express or implied warranties of any
sahilmgandhi 18:6a4db94011d3 23 * kind, including, but not limited to, any implied warranties of
sahilmgandhi 18:6a4db94011d3 24 * merchantability or fitness for any particular purpose or warranties against
sahilmgandhi 18:6a4db94011d3 25 * infringement of any proprietary rights of a third party.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
sahilmgandhi 18:6a4db94011d3 28 * incidental, or special damages, or any other relief, or for any claim by
sahilmgandhi 18:6a4db94011d3 29 * any third party, arising from your use of this Software.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 32 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 33 * @addtogroup Parts
sahilmgandhi 18:6a4db94011d3 34 * @{
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 36 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 37 * @defgroup EFR32MG1P_EMU
sahilmgandhi 18:6a4db94011d3 38 * @{
sahilmgandhi 18:6a4db94011d3 39 * @brief EFR32MG1P_EMU Register Declaration
sahilmgandhi 18:6a4db94011d3 40 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 41 typedef struct
sahilmgandhi 18:6a4db94011d3 42 {
sahilmgandhi 18:6a4db94011d3 43 __IOM uint32_t CTRL; /**< Control Register */
sahilmgandhi 18:6a4db94011d3 44 __IM uint32_t STATUS; /**< Status Register */
sahilmgandhi 18:6a4db94011d3 45 __IOM uint32_t LOCK; /**< Configuration Lock Register */
sahilmgandhi 18:6a4db94011d3 46 __IOM uint32_t RAM0CTRL; /**< Memory Control Register */
sahilmgandhi 18:6a4db94011d3 47 __IOM uint32_t CMD; /**< Command Register */
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 uint32_t RESERVED0[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 50 __IOM uint32_t EM4CTRL; /**< EM4 Control Register */
sahilmgandhi 18:6a4db94011d3 51 __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */
sahilmgandhi 18:6a4db94011d3 52 __IM uint32_t TEMP; /**< Value of last temperature measurement */
sahilmgandhi 18:6a4db94011d3 53 __IM uint32_t IF; /**< Interrupt Flag Register */
sahilmgandhi 18:6a4db94011d3 54 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
sahilmgandhi 18:6a4db94011d3 55 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
sahilmgandhi 18:6a4db94011d3 56 __IOM uint32_t IEN; /**< Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 57 __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */
sahilmgandhi 18:6a4db94011d3 58 __IOM uint32_t PWRCFG; /**< Power Configuration Register */
sahilmgandhi 18:6a4db94011d3 59 __IOM uint32_t PWRCTRL; /**< Power Control Register. */
sahilmgandhi 18:6a4db94011d3 60 __IOM uint32_t DCDCCTRL; /**< DCDC Control */
sahilmgandhi 18:6a4db94011d3 61
sahilmgandhi 18:6a4db94011d3 62 uint32_t RESERVED1[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 63 __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */
sahilmgandhi 18:6a4db94011d3 64 __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */
sahilmgandhi 18:6a4db94011d3 65 __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */
sahilmgandhi 18:6a4db94011d3 66 __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */
sahilmgandhi 18:6a4db94011d3 67 __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */
sahilmgandhi 18:6a4db94011d3 68 __IOM uint32_t DCDCTIMING; /**< DCDC Controller Timing Value Register */
sahilmgandhi 18:6a4db94011d3 69 __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 uint32_t RESERVED2[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 72 __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */
sahilmgandhi 18:6a4db94011d3 73 __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 uint32_t RESERVED3[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 76 __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 uint32_t RESERVED4[5]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 79 __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */
sahilmgandhi 18:6a4db94011d3 80 __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */
sahilmgandhi 18:6a4db94011d3 81 __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */
sahilmgandhi 18:6a4db94011d3 82 __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 uint32_t RESERVED5[49]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 85 __IOM uint32_t BIASCONF; /**< Configurations Related to the Bias */
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 uint32_t RESERVED6[10]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 88 __IOM uint32_t TESTLOCK; /**< Test Lock Register */
sahilmgandhi 18:6a4db94011d3 89
sahilmgandhi 18:6a4db94011d3 90 uint32_t RESERVED7[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 91 __IOM uint32_t BIASTESTCTRL; /**< Test Control Register for regulator and BIAS */
sahilmgandhi 18:6a4db94011d3 92 } EMU_TypeDef; /** @} */
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 95 * @defgroup EFR32MG1P_EMU_BitFields
sahilmgandhi 18:6a4db94011d3 96 * @{
sahilmgandhi 18:6a4db94011d3 97 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 /* Bit fields for EMU CTRL */
sahilmgandhi 18:6a4db94011d3 100 #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
sahilmgandhi 18:6a4db94011d3 101 #define _EMU_CTRL_MASK 0x00000002UL /**< Mask for EMU_CTRL */
sahilmgandhi 18:6a4db94011d3 102 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
sahilmgandhi 18:6a4db94011d3 103 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
sahilmgandhi 18:6a4db94011d3 104 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
sahilmgandhi 18:6a4db94011d3 105 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
sahilmgandhi 18:6a4db94011d3 106 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /* Bit fields for EMU STATUS */
sahilmgandhi 18:6a4db94011d3 109 #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 110 #define _EMU_STATUS_MASK 0x0010011FUL /**< Mask for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 111 #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */
sahilmgandhi 18:6a4db94011d3 112 #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */
sahilmgandhi 18:6a4db94011d3 113 #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */
sahilmgandhi 18:6a4db94011d3 114 #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 115 #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 116 #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */
sahilmgandhi 18:6a4db94011d3 117 #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */
sahilmgandhi 18:6a4db94011d3 118 #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */
sahilmgandhi 18:6a4db94011d3 119 #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 120 #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 121 #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */
sahilmgandhi 18:6a4db94011d3 122 #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */
sahilmgandhi 18:6a4db94011d3 123 #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */
sahilmgandhi 18:6a4db94011d3 124 #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 125 #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 126 #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */
sahilmgandhi 18:6a4db94011d3 127 #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */
sahilmgandhi 18:6a4db94011d3 128 #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */
sahilmgandhi 18:6a4db94011d3 129 #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 130 #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 131 #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */
sahilmgandhi 18:6a4db94011d3 132 #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */
sahilmgandhi 18:6a4db94011d3 133 #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */
sahilmgandhi 18:6a4db94011d3 134 #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 135 #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 136 #define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */
sahilmgandhi 18:6a4db94011d3 137 #define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */
sahilmgandhi 18:6a4db94011d3 138 #define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */
sahilmgandhi 18:6a4db94011d3 139 #define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 140 #define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 141 #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */
sahilmgandhi 18:6a4db94011d3 142 #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */
sahilmgandhi 18:6a4db94011d3 143 #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */
sahilmgandhi 18:6a4db94011d3 144 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 145 #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 146 #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 147 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 148 #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 149 #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /* Bit fields for EMU LOCK */
sahilmgandhi 18:6a4db94011d3 152 #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 153 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 154 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 155 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 156 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 157 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 158 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 159 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 160 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 161 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 162 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 163 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 164 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 165 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 /* Bit fields for EMU RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 168 #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 169 #define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 170 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
sahilmgandhi 18:6a4db94011d3 171 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */
sahilmgandhi 18:6a4db94011d3 172 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 173 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 174 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 175 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 176 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 177 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 178 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 179 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 180 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 181 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 182 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 183 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */
sahilmgandhi 18:6a4db94011d3 184
sahilmgandhi 18:6a4db94011d3 185 /* Bit fields for EMU CMD */
sahilmgandhi 18:6a4db94011d3 186 #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */
sahilmgandhi 18:6a4db94011d3 187 #define _EMU_CMD_MASK 0x00000001UL /**< Mask for EMU_CMD */
sahilmgandhi 18:6a4db94011d3 188 #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */
sahilmgandhi 18:6a4db94011d3 189 #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */
sahilmgandhi 18:6a4db94011d3 190 #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */
sahilmgandhi 18:6a4db94011d3 191 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
sahilmgandhi 18:6a4db94011d3 192 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /* Bit fields for EMU EM4CTRL */
sahilmgandhi 18:6a4db94011d3 195 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 196 #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 197 #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */
sahilmgandhi 18:6a4db94011d3 198 #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */
sahilmgandhi 18:6a4db94011d3 199 #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */
sahilmgandhi 18:6a4db94011d3 200 #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 201 #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 202 #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 203 #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 204 #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 205 #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 206 #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */
sahilmgandhi 18:6a4db94011d3 207 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */
sahilmgandhi 18:6a4db94011d3 208 #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */
sahilmgandhi 18:6a4db94011d3 209 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 210 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 211 #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */
sahilmgandhi 18:6a4db94011d3 212 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */
sahilmgandhi 18:6a4db94011d3 213 #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */
sahilmgandhi 18:6a4db94011d3 214 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 215 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 216 #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */
sahilmgandhi 18:6a4db94011d3 217 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */
sahilmgandhi 18:6a4db94011d3 218 #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */
sahilmgandhi 18:6a4db94011d3 219 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 220 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 221 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */
sahilmgandhi 18:6a4db94011d3 222 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */
sahilmgandhi 18:6a4db94011d3 223 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 224 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 225 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 226 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 227 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 228 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 229 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 230 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 231 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */
sahilmgandhi 18:6a4db94011d3 232 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */
sahilmgandhi 18:6a4db94011d3 233 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 234 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 /* Bit fields for EMU TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 237 #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 238 #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 239 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 240 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 241 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 242 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 243 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 244 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 245 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 246 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 247 #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */
sahilmgandhi 18:6a4db94011d3 248 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */
sahilmgandhi 18:6a4db94011d3 249 #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */
sahilmgandhi 18:6a4db94011d3 250 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 251 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 /* Bit fields for EMU TEMP */
sahilmgandhi 18:6a4db94011d3 254 #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 255 #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 256 #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 257 #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 258 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 259 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 /* Bit fields for EMU IF */
sahilmgandhi 18:6a4db94011d3 262 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
sahilmgandhi 18:6a4db94011d3 263 #define _EMU_IF_MASK 0xE11FC0FFUL /**< Mask for EMU_IF */
sahilmgandhi 18:6a4db94011d3 264 #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */
sahilmgandhi 18:6a4db94011d3 265 #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
sahilmgandhi 18:6a4db94011d3 266 #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
sahilmgandhi 18:6a4db94011d3 267 #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 268 #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 269 #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */
sahilmgandhi 18:6a4db94011d3 270 #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
sahilmgandhi 18:6a4db94011d3 271 #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
sahilmgandhi 18:6a4db94011d3 272 #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 273 #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 274 #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */
sahilmgandhi 18:6a4db94011d3 275 #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
sahilmgandhi 18:6a4db94011d3 276 #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
sahilmgandhi 18:6a4db94011d3 277 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 278 #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 279 #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */
sahilmgandhi 18:6a4db94011d3 280 #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
sahilmgandhi 18:6a4db94011d3 281 #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
sahilmgandhi 18:6a4db94011d3 282 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 283 #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 284 #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */
sahilmgandhi 18:6a4db94011d3 285 #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
sahilmgandhi 18:6a4db94011d3 286 #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
sahilmgandhi 18:6a4db94011d3 287 #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 288 #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 289 #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */
sahilmgandhi 18:6a4db94011d3 290 #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
sahilmgandhi 18:6a4db94011d3 291 #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
sahilmgandhi 18:6a4db94011d3 292 #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 293 #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 294 #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */
sahilmgandhi 18:6a4db94011d3 295 #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
sahilmgandhi 18:6a4db94011d3 296 #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
sahilmgandhi 18:6a4db94011d3 297 #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 298 #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 299 #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */
sahilmgandhi 18:6a4db94011d3 300 #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
sahilmgandhi 18:6a4db94011d3 301 #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
sahilmgandhi 18:6a4db94011d3 302 #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 303 #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 304 #define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */
sahilmgandhi 18:6a4db94011d3 305 #define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
sahilmgandhi 18:6a4db94011d3 306 #define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
sahilmgandhi 18:6a4db94011d3 307 #define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 308 #define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 309 #define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */
sahilmgandhi 18:6a4db94011d3 310 #define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
sahilmgandhi 18:6a4db94011d3 311 #define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
sahilmgandhi 18:6a4db94011d3 312 #define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 313 #define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 314 #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */
sahilmgandhi 18:6a4db94011d3 315 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 316 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 317 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 318 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 319 #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */
sahilmgandhi 18:6a4db94011d3 320 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 321 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 322 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 323 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 324 #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */
sahilmgandhi 18:6a4db94011d3 325 #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
sahilmgandhi 18:6a4db94011d3 326 #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
sahilmgandhi 18:6a4db94011d3 327 #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 328 #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 329 #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */
sahilmgandhi 18:6a4db94011d3 330 #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
sahilmgandhi 18:6a4db94011d3 331 #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
sahilmgandhi 18:6a4db94011d3 332 #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 333 #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 334 #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */
sahilmgandhi 18:6a4db94011d3 335 #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
sahilmgandhi 18:6a4db94011d3 336 #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
sahilmgandhi 18:6a4db94011d3 337 #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 338 #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 339 #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */
sahilmgandhi 18:6a4db94011d3 340 #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
sahilmgandhi 18:6a4db94011d3 341 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
sahilmgandhi 18:6a4db94011d3 342 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 343 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 344 #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */
sahilmgandhi 18:6a4db94011d3 345 #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 346 #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 347 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 348 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 349 #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */
sahilmgandhi 18:6a4db94011d3 350 #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 351 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 352 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 353 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 354 #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */
sahilmgandhi 18:6a4db94011d3 355 #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 356 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 357 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 358 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 /* Bit fields for EMU IFS */
sahilmgandhi 18:6a4db94011d3 361 #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 362 #define _EMU_IFS_MASK 0xE11FC0FFUL /**< Mask for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 363 #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 364 #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
sahilmgandhi 18:6a4db94011d3 365 #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
sahilmgandhi 18:6a4db94011d3 366 #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 367 #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 368 #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 369 #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
sahilmgandhi 18:6a4db94011d3 370 #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
sahilmgandhi 18:6a4db94011d3 371 #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 372 #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 373 #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 374 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
sahilmgandhi 18:6a4db94011d3 375 #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
sahilmgandhi 18:6a4db94011d3 376 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 377 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 378 #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 379 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
sahilmgandhi 18:6a4db94011d3 380 #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
sahilmgandhi 18:6a4db94011d3 381 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 382 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 383 #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 384 #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
sahilmgandhi 18:6a4db94011d3 385 #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
sahilmgandhi 18:6a4db94011d3 386 #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 387 #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 388 #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 389 #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
sahilmgandhi 18:6a4db94011d3 390 #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
sahilmgandhi 18:6a4db94011d3 391 #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 392 #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 393 #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 394 #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
sahilmgandhi 18:6a4db94011d3 395 #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
sahilmgandhi 18:6a4db94011d3 396 #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 397 #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 398 #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 399 #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
sahilmgandhi 18:6a4db94011d3 400 #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
sahilmgandhi 18:6a4db94011d3 401 #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 402 #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 403 #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 404 #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
sahilmgandhi 18:6a4db94011d3 405 #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
sahilmgandhi 18:6a4db94011d3 406 #define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 407 #define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 408 #define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 409 #define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
sahilmgandhi 18:6a4db94011d3 410 #define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
sahilmgandhi 18:6a4db94011d3 411 #define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 412 #define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 413 #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 414 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 415 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 416 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 417 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 418 #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 419 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 420 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 421 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 422 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 423 #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 424 #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
sahilmgandhi 18:6a4db94011d3 425 #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
sahilmgandhi 18:6a4db94011d3 426 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 427 #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 428 #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 429 #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
sahilmgandhi 18:6a4db94011d3 430 #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
sahilmgandhi 18:6a4db94011d3 431 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 432 #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 433 #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 434 #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
sahilmgandhi 18:6a4db94011d3 435 #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
sahilmgandhi 18:6a4db94011d3 436 #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 437 #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 438 #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 439 #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
sahilmgandhi 18:6a4db94011d3 440 #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
sahilmgandhi 18:6a4db94011d3 441 #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 442 #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 443 #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 444 #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 445 #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 446 #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 447 #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 448 #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 449 #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 450 #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 451 #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 452 #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 453 #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 454 #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 455 #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 456 #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 457 #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 /* Bit fields for EMU IFC */
sahilmgandhi 18:6a4db94011d3 460 #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 461 #define _EMU_IFC_MASK 0xE11FC0FFUL /**< Mask for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 462 #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 463 #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
sahilmgandhi 18:6a4db94011d3 464 #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
sahilmgandhi 18:6a4db94011d3 465 #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 466 #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 467 #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 468 #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
sahilmgandhi 18:6a4db94011d3 469 #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
sahilmgandhi 18:6a4db94011d3 470 #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 471 #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 472 #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 473 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
sahilmgandhi 18:6a4db94011d3 474 #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
sahilmgandhi 18:6a4db94011d3 475 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 476 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 477 #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 478 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
sahilmgandhi 18:6a4db94011d3 479 #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
sahilmgandhi 18:6a4db94011d3 480 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 481 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 482 #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 483 #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
sahilmgandhi 18:6a4db94011d3 484 #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
sahilmgandhi 18:6a4db94011d3 485 #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 486 #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 487 #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 488 #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
sahilmgandhi 18:6a4db94011d3 489 #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
sahilmgandhi 18:6a4db94011d3 490 #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 491 #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 492 #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 493 #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
sahilmgandhi 18:6a4db94011d3 494 #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
sahilmgandhi 18:6a4db94011d3 495 #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 496 #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 497 #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 498 #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
sahilmgandhi 18:6a4db94011d3 499 #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
sahilmgandhi 18:6a4db94011d3 500 #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 501 #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 502 #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 503 #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
sahilmgandhi 18:6a4db94011d3 504 #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
sahilmgandhi 18:6a4db94011d3 505 #define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 506 #define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 507 #define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 508 #define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
sahilmgandhi 18:6a4db94011d3 509 #define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
sahilmgandhi 18:6a4db94011d3 510 #define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 511 #define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 512 #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 513 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 514 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 515 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 516 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 517 #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 518 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 519 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 520 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 521 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 522 #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 523 #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
sahilmgandhi 18:6a4db94011d3 524 #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
sahilmgandhi 18:6a4db94011d3 525 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 526 #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 527 #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 528 #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
sahilmgandhi 18:6a4db94011d3 529 #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
sahilmgandhi 18:6a4db94011d3 530 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 531 #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 532 #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 533 #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
sahilmgandhi 18:6a4db94011d3 534 #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
sahilmgandhi 18:6a4db94011d3 535 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 536 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 537 #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 538 #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
sahilmgandhi 18:6a4db94011d3 539 #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
sahilmgandhi 18:6a4db94011d3 540 #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 541 #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 542 #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 543 #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 544 #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 545 #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 546 #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 547 #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 548 #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 549 #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 550 #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 551 #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 552 #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 553 #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 554 #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 555 #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 556 #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 /* Bit fields for EMU IEN */
sahilmgandhi 18:6a4db94011d3 559 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 560 #define _EMU_IEN_MASK 0xE11FC0FFUL /**< Mask for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 561 #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 562 #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
sahilmgandhi 18:6a4db94011d3 563 #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
sahilmgandhi 18:6a4db94011d3 564 #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 565 #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 566 #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 567 #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
sahilmgandhi 18:6a4db94011d3 568 #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
sahilmgandhi 18:6a4db94011d3 569 #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 570 #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 571 #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 572 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
sahilmgandhi 18:6a4db94011d3 573 #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
sahilmgandhi 18:6a4db94011d3 574 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 575 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 576 #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 577 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
sahilmgandhi 18:6a4db94011d3 578 #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
sahilmgandhi 18:6a4db94011d3 579 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 580 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 581 #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 582 #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
sahilmgandhi 18:6a4db94011d3 583 #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
sahilmgandhi 18:6a4db94011d3 584 #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 585 #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 586 #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 587 #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
sahilmgandhi 18:6a4db94011d3 588 #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
sahilmgandhi 18:6a4db94011d3 589 #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 590 #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 591 #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 592 #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
sahilmgandhi 18:6a4db94011d3 593 #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
sahilmgandhi 18:6a4db94011d3 594 #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 595 #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 596 #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 597 #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
sahilmgandhi 18:6a4db94011d3 598 #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
sahilmgandhi 18:6a4db94011d3 599 #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 600 #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 601 #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 602 #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */
sahilmgandhi 18:6a4db94011d3 603 #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */
sahilmgandhi 18:6a4db94011d3 604 #define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 605 #define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 606 #define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 607 #define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */
sahilmgandhi 18:6a4db94011d3 608 #define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */
sahilmgandhi 18:6a4db94011d3 609 #define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 610 #define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 611 #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 612 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 613 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 614 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 615 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 616 #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 617 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 618 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
sahilmgandhi 18:6a4db94011d3 619 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 620 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 621 #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 622 #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
sahilmgandhi 18:6a4db94011d3 623 #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
sahilmgandhi 18:6a4db94011d3 624 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 625 #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 626 #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 627 #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
sahilmgandhi 18:6a4db94011d3 628 #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
sahilmgandhi 18:6a4db94011d3 629 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 630 #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 631 #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 632 #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
sahilmgandhi 18:6a4db94011d3 633 #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
sahilmgandhi 18:6a4db94011d3 634 #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 635 #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 636 #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 637 #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
sahilmgandhi 18:6a4db94011d3 638 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
sahilmgandhi 18:6a4db94011d3 639 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 640 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 641 #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 642 #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 643 #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
sahilmgandhi 18:6a4db94011d3 644 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 645 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 646 #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 647 #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 648 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
sahilmgandhi 18:6a4db94011d3 649 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 650 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 651 #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 652 #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 653 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
sahilmgandhi 18:6a4db94011d3 654 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 655 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 /* Bit fields for EMU PWRLOCK */
sahilmgandhi 18:6a4db94011d3 658 #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 659 #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 660 #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 661 #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 662 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 663 #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 664 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 665 #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 666 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 667 #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 668 #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 669 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 670 #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 671 #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /* Bit fields for EMU PWRCFG */
sahilmgandhi 18:6a4db94011d3 674 #define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 675 #define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 676 #define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 677 #define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 678 #define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 679 #define _EMU_PWRCFG_PWRCFG_STARTUP 0x00000000UL /**< Mode STARTUP for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 680 #define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 681 #define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 682 #define EMU_PWRCFG_PWRCFG_STARTUP (_EMU_PWRCFG_PWRCFG_STARTUP << 0) /**< Shifted mode STARTUP for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 683 #define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 /* Bit fields for EMU PWRCTRL */
sahilmgandhi 18:6a4db94011d3 686 #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */
sahilmgandhi 18:6a4db94011d3 687 #define _EMU_PWRCTRL_MASK 0x00000020UL /**< Mask for EMU_PWRCTRL */
sahilmgandhi 18:6a4db94011d3 688 #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */
sahilmgandhi 18:6a4db94011d3 689 #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */
sahilmgandhi 18:6a4db94011d3 690 #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */
sahilmgandhi 18:6a4db94011d3 691 #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
sahilmgandhi 18:6a4db94011d3 692 #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */
sahilmgandhi 18:6a4db94011d3 693 #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */
sahilmgandhi 18:6a4db94011d3 694 #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
sahilmgandhi 18:6a4db94011d3 695 #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */
sahilmgandhi 18:6a4db94011d3 696 #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698 /* Bit fields for EMU DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 699 #define _EMU_DCDCCTRL_RESETVALUE 0x00000030UL /**< Default value for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 700 #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 701 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */
sahilmgandhi 18:6a4db94011d3 702 #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */
sahilmgandhi 18:6a4db94011d3 703 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 704 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 705 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 706 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 707 #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 708 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 709 #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 710 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 711 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 712 #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 713 #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */
sahilmgandhi 18:6a4db94011d3 714 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */
sahilmgandhi 18:6a4db94011d3 715 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */
sahilmgandhi 18:6a4db94011d3 716 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 717 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 718 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 719 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 720 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 721 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 722 #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */
sahilmgandhi 18:6a4db94011d3 723 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */
sahilmgandhi 18:6a4db94011d3 724 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */
sahilmgandhi 18:6a4db94011d3 725 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 726 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 727 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 728 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 729 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 730 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 /* Bit fields for EMU DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 733 #define _EMU_DCDCMISCCTRL_RESETVALUE 0x33307700UL /**< Default value for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 734 #define _EMU_DCDCMISCCTRL_MASK 0x377FFF01UL /**< Mask for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 735 #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */
sahilmgandhi 18:6a4db94011d3 736 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */
sahilmgandhi 18:6a4db94011d3 737 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */
sahilmgandhi 18:6a4db94011d3 738 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 739 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 740 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */
sahilmgandhi 18:6a4db94011d3 741 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */
sahilmgandhi 18:6a4db94011d3 742 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 743 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 744 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */
sahilmgandhi 18:6a4db94011d3 745 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */
sahilmgandhi 18:6a4db94011d3 746 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 747 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 748 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */
sahilmgandhi 18:6a4db94011d3 749 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */
sahilmgandhi 18:6a4db94011d3 750 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 751 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 752 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */
sahilmgandhi 18:6a4db94011d3 753 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */
sahilmgandhi 18:6a4db94011d3 754 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 755 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 756 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */
sahilmgandhi 18:6a4db94011d3 757 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */
sahilmgandhi 18:6a4db94011d3 758 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 759 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 760 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT 28 /**< Shift value for EMU_LPCMPBIAS */
sahilmgandhi 18:6a4db94011d3 761 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIAS */
sahilmgandhi 18:6a4db94011d3 762 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 763 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 764 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 765 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 766 #define _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 767 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 768 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 769 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 770 #define EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIAS_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 771 #define EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773 /* Bit fields for EMU DCDCZDETCTRL */
sahilmgandhi 18:6a4db94011d3 774 #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000130UL /**< Default value for EMU_DCDCZDETCTRL */
sahilmgandhi 18:6a4db94011d3 775 #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */
sahilmgandhi 18:6a4db94011d3 776 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */
sahilmgandhi 18:6a4db94011d3 777 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */
sahilmgandhi 18:6a4db94011d3 778 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
sahilmgandhi 18:6a4db94011d3 779 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
sahilmgandhi 18:6a4db94011d3 780 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */
sahilmgandhi 18:6a4db94011d3 781 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */
sahilmgandhi 18:6a4db94011d3 782 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
sahilmgandhi 18:6a4db94011d3 783 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 /* Bit fields for EMU DCDCCLIMCTRL */
sahilmgandhi 18:6a4db94011d3 786 #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00002100UL /**< Default value for EMU_DCDCCLIMCTRL */
sahilmgandhi 18:6a4db94011d3 787 #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */
sahilmgandhi 18:6a4db94011d3 788 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */
sahilmgandhi 18:6a4db94011d3 789 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */
sahilmgandhi 18:6a4db94011d3 790 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
sahilmgandhi 18:6a4db94011d3 791 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
sahilmgandhi 18:6a4db94011d3 792 #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */
sahilmgandhi 18:6a4db94011d3 793 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */
sahilmgandhi 18:6a4db94011d3 794 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */
sahilmgandhi 18:6a4db94011d3 795 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
sahilmgandhi 18:6a4db94011d3 796 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
sahilmgandhi 18:6a4db94011d3 797
sahilmgandhi 18:6a4db94011d3 798 /* Bit fields for EMU DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 799 #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 800 #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 801 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */
sahilmgandhi 18:6a4db94011d3 802 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */
sahilmgandhi 18:6a4db94011d3 803 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 804 #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 805 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */
sahilmgandhi 18:6a4db94011d3 806 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */
sahilmgandhi 18:6a4db94011d3 807 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 808 #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 809 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */
sahilmgandhi 18:6a4db94011d3 810 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */
sahilmgandhi 18:6a4db94011d3 811 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 812 #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 813 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */
sahilmgandhi 18:6a4db94011d3 814 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */
sahilmgandhi 18:6a4db94011d3 815 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 816 #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 817 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */
sahilmgandhi 18:6a4db94011d3 818 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */
sahilmgandhi 18:6a4db94011d3 819 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 820 #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 821 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */
sahilmgandhi 18:6a4db94011d3 822 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */
sahilmgandhi 18:6a4db94011d3 823 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 824 #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
sahilmgandhi 18:6a4db94011d3 825
sahilmgandhi 18:6a4db94011d3 826 /* Bit fields for EMU DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 827 #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 828 #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 829 #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */
sahilmgandhi 18:6a4db94011d3 830 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */
sahilmgandhi 18:6a4db94011d3 831 #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */
sahilmgandhi 18:6a4db94011d3 832 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 833 #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 834 #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 835 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 836 #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 837 #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 838 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */
sahilmgandhi 18:6a4db94011d3 839 #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */
sahilmgandhi 18:6a4db94011d3 840 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 841 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
sahilmgandhi 18:6a4db94011d3 842
sahilmgandhi 18:6a4db94011d3 843 /* Bit fields for EMU DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 844 #define _EMU_DCDCTIMING_RESETVALUE 0x0FF1F8FFUL /**< Default value for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 845 #define _EMU_DCDCTIMING_MASK 0x6FF1F8FFUL /**< Mask for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 846 #define _EMU_DCDCTIMING_LPINITWAIT_SHIFT 0 /**< Shift value for EMU_LPINITWAIT */
sahilmgandhi 18:6a4db94011d3 847 #define _EMU_DCDCTIMING_LPINITWAIT_MASK 0xFFUL /**< Bit mask for EMU_LPINITWAIT */
sahilmgandhi 18:6a4db94011d3 848 #define _EMU_DCDCTIMING_LPINITWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 849 #define EMU_DCDCTIMING_LPINITWAIT_DEFAULT (_EMU_DCDCTIMING_LPINITWAIT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 850 #define EMU_DCDCTIMING_COMPENPRCHGEN (0x1UL << 11) /**< LN mode precharge enable */
sahilmgandhi 18:6a4db94011d3 851 #define _EMU_DCDCTIMING_COMPENPRCHGEN_SHIFT 11 /**< Shift value for EMU_COMPENPRCHGEN */
sahilmgandhi 18:6a4db94011d3 852 #define _EMU_DCDCTIMING_COMPENPRCHGEN_MASK 0x800UL /**< Bit mask for EMU_COMPENPRCHGEN */
sahilmgandhi 18:6a4db94011d3 853 #define _EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 854 #define EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT (_EMU_DCDCTIMING_COMPENPRCHGEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 855 #define _EMU_DCDCTIMING_LNWAIT_SHIFT 12 /**< Shift value for EMU_LNWAIT */
sahilmgandhi 18:6a4db94011d3 856 #define _EMU_DCDCTIMING_LNWAIT_MASK 0x1F000UL /**< Bit mask for EMU_LNWAIT */
sahilmgandhi 18:6a4db94011d3 857 #define _EMU_DCDCTIMING_LNWAIT_DEFAULT 0x0000001FUL /**< Mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 858 #define EMU_DCDCTIMING_LNWAIT_DEFAULT (_EMU_DCDCTIMING_LNWAIT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 859 #define _EMU_DCDCTIMING_BYPWAIT_SHIFT 20 /**< Shift value for EMU_BYPWAIT */
sahilmgandhi 18:6a4db94011d3 860 #define _EMU_DCDCTIMING_BYPWAIT_MASK 0xFF00000UL /**< Bit mask for EMU_BYPWAIT */
sahilmgandhi 18:6a4db94011d3 861 #define _EMU_DCDCTIMING_BYPWAIT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 862 #define EMU_DCDCTIMING_BYPWAIT_DEFAULT (_EMU_DCDCTIMING_BYPWAIT_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 863 #define _EMU_DCDCTIMING_DUTYSCALE_SHIFT 29 /**< Shift value for EMU_DUTYSCALE */
sahilmgandhi 18:6a4db94011d3 864 #define _EMU_DCDCTIMING_DUTYSCALE_MASK 0x60000000UL /**< Bit mask for EMU_DUTYSCALE */
sahilmgandhi 18:6a4db94011d3 865 #define _EMU_DCDCTIMING_DUTYSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 866 #define EMU_DCDCTIMING_DUTYSCALE_DEFAULT (_EMU_DCDCTIMING_DUTYSCALE_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DCDCTIMING */
sahilmgandhi 18:6a4db94011d3 867
sahilmgandhi 18:6a4db94011d3 868 /* Bit fields for EMU DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 869 #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 870 #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 871 #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */
sahilmgandhi 18:6a4db94011d3 872 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */
sahilmgandhi 18:6a4db94011d3 873 #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */
sahilmgandhi 18:6a4db94011d3 874 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 875 #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 876 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 877 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 878 #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 879 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 880 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */
sahilmgandhi 18:6a4db94011d3 881 #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */
sahilmgandhi 18:6a4db94011d3 882 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 883 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
sahilmgandhi 18:6a4db94011d3 884
sahilmgandhi 18:6a4db94011d3 885 /* Bit fields for EMU DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 886 #define _EMU_DCDCLPCTRL_RESETVALUE 0x00007000UL /**< Default value for EMU_DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 887 #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 888 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSEL */
sahilmgandhi 18:6a4db94011d3 889 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSEL */
sahilmgandhi 18:6a4db94011d3 890 #define _EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 891 #define EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 892 #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */
sahilmgandhi 18:6a4db94011d3 893 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */
sahilmgandhi 18:6a4db94011d3 894 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */
sahilmgandhi 18:6a4db94011d3 895 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 896 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 897 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */
sahilmgandhi 18:6a4db94011d3 898 #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */
sahilmgandhi 18:6a4db94011d3 899 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 900 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
sahilmgandhi 18:6a4db94011d3 901
sahilmgandhi 18:6a4db94011d3 902 /* Bit fields for EMU DCDCLNFREQCTRL */
sahilmgandhi 18:6a4db94011d3 903 #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */
sahilmgandhi 18:6a4db94011d3 904 #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */
sahilmgandhi 18:6a4db94011d3 905 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */
sahilmgandhi 18:6a4db94011d3 906 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */
sahilmgandhi 18:6a4db94011d3 907 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
sahilmgandhi 18:6a4db94011d3 908 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
sahilmgandhi 18:6a4db94011d3 909 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */
sahilmgandhi 18:6a4db94011d3 910 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */
sahilmgandhi 18:6a4db94011d3 911 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
sahilmgandhi 18:6a4db94011d3 912 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 /* Bit fields for EMU DCDCSYNC */
sahilmgandhi 18:6a4db94011d3 915 #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */
sahilmgandhi 18:6a4db94011d3 916 #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */
sahilmgandhi 18:6a4db94011d3 917 #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */
sahilmgandhi 18:6a4db94011d3 918 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */
sahilmgandhi 18:6a4db94011d3 919 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */
sahilmgandhi 18:6a4db94011d3 920 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */
sahilmgandhi 18:6a4db94011d3 921 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */
sahilmgandhi 18:6a4db94011d3 922
sahilmgandhi 18:6a4db94011d3 923 /* Bit fields for EMU VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 924 #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 925 #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 926 #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */
sahilmgandhi 18:6a4db94011d3 927 #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
sahilmgandhi 18:6a4db94011d3 928 #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
sahilmgandhi 18:6a4db94011d3 929 #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 930 #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 931 #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
sahilmgandhi 18:6a4db94011d3 932 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
sahilmgandhi 18:6a4db94011d3 933 #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
sahilmgandhi 18:6a4db94011d3 934 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 935 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 936 #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
sahilmgandhi 18:6a4db94011d3 937 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
sahilmgandhi 18:6a4db94011d3 938 #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
sahilmgandhi 18:6a4db94011d3 939 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 940 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 941 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */
sahilmgandhi 18:6a4db94011d3 942 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */
sahilmgandhi 18:6a4db94011d3 943 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 944 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 945 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */
sahilmgandhi 18:6a4db94011d3 946 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */
sahilmgandhi 18:6a4db94011d3 947 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 948 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 949 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */
sahilmgandhi 18:6a4db94011d3 950 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */
sahilmgandhi 18:6a4db94011d3 951 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 952 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 953 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */
sahilmgandhi 18:6a4db94011d3 954 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */
sahilmgandhi 18:6a4db94011d3 955 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 956 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 957
sahilmgandhi 18:6a4db94011d3 958 /* Bit fields for EMU VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 959 #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 960 #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 961 #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */
sahilmgandhi 18:6a4db94011d3 962 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
sahilmgandhi 18:6a4db94011d3 963 #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
sahilmgandhi 18:6a4db94011d3 964 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 965 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 966 #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
sahilmgandhi 18:6a4db94011d3 967 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
sahilmgandhi 18:6a4db94011d3 968 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
sahilmgandhi 18:6a4db94011d3 969 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 970 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 971 #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
sahilmgandhi 18:6a4db94011d3 972 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
sahilmgandhi 18:6a4db94011d3 973 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
sahilmgandhi 18:6a4db94011d3 974 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 975 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 976 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
sahilmgandhi 18:6a4db94011d3 977 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
sahilmgandhi 18:6a4db94011d3 978 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 979 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 980 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 981 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 982 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 983 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
sahilmgandhi 18:6a4db94011d3 984
sahilmgandhi 18:6a4db94011d3 985 /* Bit fields for EMU VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 986 #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 987 #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 988 #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */
sahilmgandhi 18:6a4db94011d3 989 #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
sahilmgandhi 18:6a4db94011d3 990 #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
sahilmgandhi 18:6a4db94011d3 991 #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 992 #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 993 #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
sahilmgandhi 18:6a4db94011d3 994 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
sahilmgandhi 18:6a4db94011d3 995 #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
sahilmgandhi 18:6a4db94011d3 996 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 997 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 998 #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
sahilmgandhi 18:6a4db94011d3 999 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
sahilmgandhi 18:6a4db94011d3 1000 #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
sahilmgandhi 18:6a4db94011d3 1001 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 1002 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 1003 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
sahilmgandhi 18:6a4db94011d3 1004 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
sahilmgandhi 18:6a4db94011d3 1005 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 1006 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 1007 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 1008 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 1009 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 1010 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 /* Bit fields for EMU VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1013 #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1014 #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1015 #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */
sahilmgandhi 18:6a4db94011d3 1016 #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
sahilmgandhi 18:6a4db94011d3 1017 #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
sahilmgandhi 18:6a4db94011d3 1018 #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1019 #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1020 #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
sahilmgandhi 18:6a4db94011d3 1021 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
sahilmgandhi 18:6a4db94011d3 1022 #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
sahilmgandhi 18:6a4db94011d3 1023 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1024 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1025 #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
sahilmgandhi 18:6a4db94011d3 1026 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
sahilmgandhi 18:6a4db94011d3 1027 #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
sahilmgandhi 18:6a4db94011d3 1028 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1029 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1030 #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */
sahilmgandhi 18:6a4db94011d3 1031 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
sahilmgandhi 18:6a4db94011d3 1032 #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
sahilmgandhi 18:6a4db94011d3 1033 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1034 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1035 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
sahilmgandhi 18:6a4db94011d3 1036 #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
sahilmgandhi 18:6a4db94011d3 1037 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1038 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1039 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 1040 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 1041 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1042 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
sahilmgandhi 18:6a4db94011d3 1043
sahilmgandhi 18:6a4db94011d3 1044 /* Bit fields for EMU BIASCONF */
sahilmgandhi 18:6a4db94011d3 1045 #define _EMU_BIASCONF_RESETVALUE 0x000000F8UL /**< Default value for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1046 #define _EMU_BIASCONF_MASK 0x000000FCUL /**< Mask for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1047 #define EMU_BIASCONF_NADUTYEM01 (0x1UL << 2) /**< NA DUTY in EM01 */
sahilmgandhi 18:6a4db94011d3 1048 #define _EMU_BIASCONF_NADUTYEM01_SHIFT 2 /**< Shift value for EMU_NADUTYEM01 */
sahilmgandhi 18:6a4db94011d3 1049 #define _EMU_BIASCONF_NADUTYEM01_MASK 0x4UL /**< Bit mask for EMU_NADUTYEM01 */
sahilmgandhi 18:6a4db94011d3 1050 #define _EMU_BIASCONF_NADUTYEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1051 #define EMU_BIASCONF_NADUTYEM01_DEFAULT (_EMU_BIASCONF_NADUTYEM01_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1052 #define EMU_BIASCONF_LPEM01 (0x1UL << 3) /**< LP in EM01 */
sahilmgandhi 18:6a4db94011d3 1053 #define _EMU_BIASCONF_LPEM01_SHIFT 3 /**< Shift value for EMU_LPEM01 */
sahilmgandhi 18:6a4db94011d3 1054 #define _EMU_BIASCONF_LPEM01_MASK 0x8UL /**< Bit mask for EMU_LPEM01 */
sahilmgandhi 18:6a4db94011d3 1055 #define _EMU_BIASCONF_LPEM01_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1056 #define EMU_BIASCONF_LPEM01_DEFAULT (_EMU_BIASCONF_LPEM01_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1057 #define EMU_BIASCONF_GMCEM23 (0x1UL << 4) /**< GMC in EM234 */
sahilmgandhi 18:6a4db94011d3 1058 #define _EMU_BIASCONF_GMCEM23_SHIFT 4 /**< Shift value for EMU_GMCEM23 */
sahilmgandhi 18:6a4db94011d3 1059 #define _EMU_BIASCONF_GMCEM23_MASK 0x10UL /**< Bit mask for EMU_GMCEM23 */
sahilmgandhi 18:6a4db94011d3 1060 #define _EMU_BIASCONF_GMCEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1061 #define EMU_BIASCONF_GMCEM23_DEFAULT (_EMU_BIASCONF_GMCEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1062 #define EMU_BIASCONF_UADUTYEM23 (0x1UL << 5) /**< UADUTY in EM234 */
sahilmgandhi 18:6a4db94011d3 1063 #define _EMU_BIASCONF_UADUTYEM23_SHIFT 5 /**< Shift value for EMU_UADUTYEM23 */
sahilmgandhi 18:6a4db94011d3 1064 #define _EMU_BIASCONF_UADUTYEM23_MASK 0x20UL /**< Bit mask for EMU_UADUTYEM23 */
sahilmgandhi 18:6a4db94011d3 1065 #define _EMU_BIASCONF_UADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1066 #define EMU_BIASCONF_UADUTYEM23_DEFAULT (_EMU_BIASCONF_UADUTYEM23_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1067 #define EMU_BIASCONF_NADUTYEM23 (0x1UL << 6) /**< NA DUTY in EM234 */
sahilmgandhi 18:6a4db94011d3 1068 #define _EMU_BIASCONF_NADUTYEM23_SHIFT 6 /**< Shift value for EMU_NADUTYEM23 */
sahilmgandhi 18:6a4db94011d3 1069 #define _EMU_BIASCONF_NADUTYEM23_MASK 0x40UL /**< Bit mask for EMU_NADUTYEM23 */
sahilmgandhi 18:6a4db94011d3 1070 #define _EMU_BIASCONF_NADUTYEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1071 #define EMU_BIASCONF_NADUTYEM23_DEFAULT (_EMU_BIASCONF_NADUTYEM23_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1072 #define EMU_BIASCONF_LPEM23 (0x1UL << 7) /**< LP in EM234 */
sahilmgandhi 18:6a4db94011d3 1073 #define _EMU_BIASCONF_LPEM23_SHIFT 7 /**< Shift value for EMU_LPEM23 */
sahilmgandhi 18:6a4db94011d3 1074 #define _EMU_BIASCONF_LPEM23_MASK 0x80UL /**< Bit mask for EMU_LPEM23 */
sahilmgandhi 18:6a4db94011d3 1075 #define _EMU_BIASCONF_LPEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1076 #define EMU_BIASCONF_LPEM23_DEFAULT (_EMU_BIASCONF_LPEM23_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_BIASCONF */
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 /* Bit fields for EMU TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1079 #define _EMU_TESTLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1080 #define _EMU_TESTLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1081 #define _EMU_TESTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 1082 #define _EMU_TESTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 1083 #define _EMU_TESTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1084 #define _EMU_TESTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1085 #define _EMU_TESTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1086 #define _EMU_TESTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1087 #define _EMU_TESTLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1088 #define EMU_TESTLOCK_LOCKKEY_DEFAULT (_EMU_TESTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1089 #define EMU_TESTLOCK_LOCKKEY_LOCK (_EMU_TESTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1090 #define EMU_TESTLOCK_LOCKKEY_UNLOCKED (_EMU_TESTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1091 #define EMU_TESTLOCK_LOCKKEY_LOCKED (_EMU_TESTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1092 #define EMU_TESTLOCK_LOCKKEY_UNLOCK (_EMU_TESTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_TESTLOCK */
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094 /* Bit fields for EMU BIASTESTCTRL */
sahilmgandhi 18:6a4db94011d3 1095 #define _EMU_BIASTESTCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BIASTESTCTRL */
sahilmgandhi 18:6a4db94011d3 1096 #define _EMU_BIASTESTCTRL_MASK 0x00000008UL /**< Mask for EMU_BIASTESTCTRL */
sahilmgandhi 18:6a4db94011d3 1097 #define EMU_BIASTESTCTRL_BIAS_RIP_RESET (0x1UL << 3) /**< Reset Bias Ripple Counter */
sahilmgandhi 18:6a4db94011d3 1098 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_SHIFT 3 /**< Shift value for EMU_BIAS_RIP_RESET */
sahilmgandhi 18:6a4db94011d3 1099 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_MASK 0x8UL /**< Bit mask for EMU_BIAS_RIP_RESET */
sahilmgandhi 18:6a4db94011d3 1100 #define _EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BIASTESTCTRL */
sahilmgandhi 18:6a4db94011d3 1101 #define EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT (_EMU_BIASTESTCTRL_BIAS_RIP_RESET_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BIASTESTCTRL */
sahilmgandhi 18:6a4db94011d3 1102
sahilmgandhi 18:6a4db94011d3 1103 /** @} End of group EFR32MG1P_EMU */
sahilmgandhi 18:6a4db94011d3 1104 /** @} End of group Parts */
sahilmgandhi 18:6a4db94011d3 1105