MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_devinfo.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file efr32mg1p_devinfo.h
sahilmgandhi 18:6a4db94011d3 3 * @brief EFR32MG1P_DEVINFO register and bit field definitions
sahilmgandhi 18:6a4db94011d3 4 * @version 5.1.2
sahilmgandhi 18:6a4db94011d3 5 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 6 * @section License
sahilmgandhi 18:6a4db94011d3 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 *
sahilmgandhi 18:6a4db94011d3 10 * Permission is granted to anyone to use this software for any purpose,
sahilmgandhi 18:6a4db94011d3 11 * including commercial applications, and to alter it and redistribute it
sahilmgandhi 18:6a4db94011d3 12 * freely, subject to the following restrictions:
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * 1. The origin of this software must not be misrepresented; you must not
sahilmgandhi 18:6a4db94011d3 15 * claim that you wrote the original software.@n
sahilmgandhi 18:6a4db94011d3 16 * 2. Altered source versions must be plainly marked as such, and must not be
sahilmgandhi 18:6a4db94011d3 17 * misrepresented as being the original software.@n
sahilmgandhi 18:6a4db94011d3 18 * 3. This notice may not be removed or altered from any source distribution.
sahilmgandhi 18:6a4db94011d3 19 *
sahilmgandhi 18:6a4db94011d3 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
sahilmgandhi 18:6a4db94011d3 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
sahilmgandhi 18:6a4db94011d3 22 * providing the Software "AS IS", with no express or implied warranties of any
sahilmgandhi 18:6a4db94011d3 23 * kind, including, but not limited to, any implied warranties of
sahilmgandhi 18:6a4db94011d3 24 * merchantability or fitness for any particular purpose or warranties against
sahilmgandhi 18:6a4db94011d3 25 * infringement of any proprietary rights of a third party.
sahilmgandhi 18:6a4db94011d3 26 *
sahilmgandhi 18:6a4db94011d3 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
sahilmgandhi 18:6a4db94011d3 28 * incidental, or special damages, or any other relief, or for any claim by
sahilmgandhi 18:6a4db94011d3 29 * any third party, arising from your use of this Software.
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 32 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 33 * @addtogroup Parts
sahilmgandhi 18:6a4db94011d3 34 * @{
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 36 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 37 * @defgroup EFR32MG1P_DEVINFO
sahilmgandhi 18:6a4db94011d3 38 * @{
sahilmgandhi 18:6a4db94011d3 39 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 typedef struct
sahilmgandhi 18:6a4db94011d3 42 {
sahilmgandhi 18:6a4db94011d3 43 __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */
sahilmgandhi 18:6a4db94011d3 44 uint32_t RESERVED0[7]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 45 __IM uint32_t EXTINFO; /**< External Component description */
sahilmgandhi 18:6a4db94011d3 46 uint32_t RESERVED1[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 47 __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */
sahilmgandhi 18:6a4db94011d3 48 __IM uint32_t EUI48H; /**< OUI */
sahilmgandhi 18:6a4db94011d3 49 __IM uint32_t CUSTOMINFO; /**< Custom information */
sahilmgandhi 18:6a4db94011d3 50 __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */
sahilmgandhi 18:6a4db94011d3 51 uint32_t RESERVED2[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 52 __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
sahilmgandhi 18:6a4db94011d3 53 __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */
sahilmgandhi 18:6a4db94011d3 54 __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */
sahilmgandhi 18:6a4db94011d3 55 __IM uint32_t PART; /**< Part description */
sahilmgandhi 18:6a4db94011d3 56 __IM uint32_t DEVINFOREV; /**< Device information page revision */
sahilmgandhi 18:6a4db94011d3 57 __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */
sahilmgandhi 18:6a4db94011d3 58 uint32_t RESERVED3[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 59 __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */
sahilmgandhi 18:6a4db94011d3 60 __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */
sahilmgandhi 18:6a4db94011d3 61 __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */
sahilmgandhi 18:6a4db94011d3 62 __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */
sahilmgandhi 18:6a4db94011d3 63 uint32_t RESERVED4[4]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 64 __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */
sahilmgandhi 18:6a4db94011d3 65 uint32_t RESERVED5[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 66 __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */
sahilmgandhi 18:6a4db94011d3 67 uint32_t RESERVED6[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 68 __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */
sahilmgandhi 18:6a4db94011d3 69 __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */
sahilmgandhi 18:6a4db94011d3 70 __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */
sahilmgandhi 18:6a4db94011d3 71 uint32_t RESERVED7[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 72 __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */
sahilmgandhi 18:6a4db94011d3 73 __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */
sahilmgandhi 18:6a4db94011d3 74 __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */
sahilmgandhi 18:6a4db94011d3 75 uint32_t RESERVED8[11]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 76 __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */
sahilmgandhi 18:6a4db94011d3 77 uint32_t RESERVED9[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 78 __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */
sahilmgandhi 18:6a4db94011d3 79 uint32_t RESERVED10[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 80 __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */
sahilmgandhi 18:6a4db94011d3 81 __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */
sahilmgandhi 18:6a4db94011d3 82 __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */
sahilmgandhi 18:6a4db94011d3 83 uint32_t RESERVED11[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 84 __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */
sahilmgandhi 18:6a4db94011d3 85 __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */
sahilmgandhi 18:6a4db94011d3 86 __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */
sahilmgandhi 18:6a4db94011d3 87 uint32_t RESERVED12[11]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 88 __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */
sahilmgandhi 18:6a4db94011d3 89 __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */
sahilmgandhi 18:6a4db94011d3 90 __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */
sahilmgandhi 18:6a4db94011d3 91 uint32_t RESERVED13[3]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 92 __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */
sahilmgandhi 18:6a4db94011d3 93 __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */
sahilmgandhi 18:6a4db94011d3 94 uint32_t RESERVED14[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 95 __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */
sahilmgandhi 18:6a4db94011d3 96 __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */
sahilmgandhi 18:6a4db94011d3 97 __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */
sahilmgandhi 18:6a4db94011d3 98 __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */
sahilmgandhi 18:6a4db94011d3 99 __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */
sahilmgandhi 18:6a4db94011d3 100 __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */
sahilmgandhi 18:6a4db94011d3 101 __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */
sahilmgandhi 18:6a4db94011d3 102 } DEVINFO_TypeDef; /** @} */
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 105 * @defgroup EFR32MG1P_DEVINFO_BitFields
sahilmgandhi 18:6a4db94011d3 106 * @{
sahilmgandhi 18:6a4db94011d3 107 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 /* Bit fields for DEVINFO CAL */
sahilmgandhi 18:6a4db94011d3 110 #define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */
sahilmgandhi 18:6a4db94011d3 111 #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */
sahilmgandhi 18:6a4db94011d3 112 #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */
sahilmgandhi 18:6a4db94011d3 113 #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */
sahilmgandhi 18:6a4db94011d3 114 #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 /* Bit fields for DEVINFO EXTINFO */
sahilmgandhi 18:6a4db94011d3 117 #define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 118 #define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */
sahilmgandhi 18:6a4db94011d3 119 #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */
sahilmgandhi 18:6a4db94011d3 120 #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 121 #define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 122 #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 123 #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 124 #define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 125 #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 126 #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */
sahilmgandhi 18:6a4db94011d3 127 #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */
sahilmgandhi 18:6a4db94011d3 128 #define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 129 #define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 130 #define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 131 #define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 132 #define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */
sahilmgandhi 18:6a4db94011d3 133 #define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */
sahilmgandhi 18:6a4db94011d3 134 #define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 135 #define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 136 #define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 137 #define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /* Bit fields for DEVINFO EUI48L */
sahilmgandhi 18:6a4db94011d3 140 #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */
sahilmgandhi 18:6a4db94011d3 141 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */
sahilmgandhi 18:6a4db94011d3 142 #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */
sahilmgandhi 18:6a4db94011d3 143 #define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */
sahilmgandhi 18:6a4db94011d3 144 #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /* Bit fields for DEVINFO EUI48H */
sahilmgandhi 18:6a4db94011d3 147 #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */
sahilmgandhi 18:6a4db94011d3 148 #define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */
sahilmgandhi 18:6a4db94011d3 149 #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /* Bit fields for DEVINFO CUSTOMINFO */
sahilmgandhi 18:6a4db94011d3 152 #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */
sahilmgandhi 18:6a4db94011d3 153 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */
sahilmgandhi 18:6a4db94011d3 154 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 /* Bit fields for DEVINFO MEMINFO */
sahilmgandhi 18:6a4db94011d3 157 #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 158 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */
sahilmgandhi 18:6a4db94011d3 159 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */
sahilmgandhi 18:6a4db94011d3 160 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 161 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 162 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 163 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 164 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 165 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 166 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 167 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 168 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */
sahilmgandhi 18:6a4db94011d3 169 #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */
sahilmgandhi 18:6a4db94011d3 170 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 171 #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 172 #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 173 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 174 #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 175 #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */
sahilmgandhi 18:6a4db94011d3 176 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */
sahilmgandhi 18:6a4db94011d3 177 #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */
sahilmgandhi 18:6a4db94011d3 178 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */
sahilmgandhi 18:6a4db94011d3 179 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 /* Bit fields for DEVINFO UNIQUEL */
sahilmgandhi 18:6a4db94011d3 182 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */
sahilmgandhi 18:6a4db94011d3 183 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */
sahilmgandhi 18:6a4db94011d3 184 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 /* Bit fields for DEVINFO UNIQUEH */
sahilmgandhi 18:6a4db94011d3 187 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */
sahilmgandhi 18:6a4db94011d3 188 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */
sahilmgandhi 18:6a4db94011d3 189 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 /* Bit fields for DEVINFO MSIZE */
sahilmgandhi 18:6a4db94011d3 192 #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */
sahilmgandhi 18:6a4db94011d3 193 #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */
sahilmgandhi 18:6a4db94011d3 194 #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */
sahilmgandhi 18:6a4db94011d3 195 #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */
sahilmgandhi 18:6a4db94011d3 196 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 /* Bit fields for DEVINFO PART */
sahilmgandhi 18:6a4db94011d3 199 #define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 200 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */
sahilmgandhi 18:6a4db94011d3 201 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */
sahilmgandhi 18:6a4db94011d3 202 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */
sahilmgandhi 18:6a4db94011d3 203 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */
sahilmgandhi 18:6a4db94011d3 204 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 205 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 206 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 207 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 208 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 209 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 210 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 211 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 212 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 213 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 214 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 215 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 216 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 217 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 218 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 219 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 220 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 221 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 222 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 223 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 224 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 225 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 226 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 227 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 228 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 229 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 230 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 231 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 232 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 233 #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 234 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 235 #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 236 #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 237 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 238 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 239 #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 240 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 241 #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 242 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 243 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 244 #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 245 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 246 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 247 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 248 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 249 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 250 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 251 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 252 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 253 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 254 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 255 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 256 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 257 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 258 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 259 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 260 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 261 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 262 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 263 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 264 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 265 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 266 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 267 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 268 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 269 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 270 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 271 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 272 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 273 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 274 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 275 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 276 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 277 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 278 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 279 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 280 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 281 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 282 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 283 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 284 #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 285 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 286 #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 287 #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 288 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 289 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 290 #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 291 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 292 #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 293 #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 294 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 295 #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 296 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 297 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 298 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 299 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 300 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 301 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 302 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 303 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 304 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 305 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */
sahilmgandhi 18:6a4db94011d3 306 #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */
sahilmgandhi 18:6a4db94011d3 307 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /* Bit fields for DEVINFO DEVINFOREV */
sahilmgandhi 18:6a4db94011d3 310 #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */
sahilmgandhi 18:6a4db94011d3 311 #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */
sahilmgandhi 18:6a4db94011d3 312 #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 /* Bit fields for DEVINFO EMUTEMP */
sahilmgandhi 18:6a4db94011d3 315 #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */
sahilmgandhi 18:6a4db94011d3 316 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */
sahilmgandhi 18:6a4db94011d3 317 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 /* Bit fields for DEVINFO ADC0CAL0 */
sahilmgandhi 18:6a4db94011d3 320 #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */
sahilmgandhi 18:6a4db94011d3 321 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */
sahilmgandhi 18:6a4db94011d3 322 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */
sahilmgandhi 18:6a4db94011d3 323 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */
sahilmgandhi 18:6a4db94011d3 324 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */
sahilmgandhi 18:6a4db94011d3 325 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */
sahilmgandhi 18:6a4db94011d3 326 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */
sahilmgandhi 18:6a4db94011d3 327 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */
sahilmgandhi 18:6a4db94011d3 328 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */
sahilmgandhi 18:6a4db94011d3 329 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */
sahilmgandhi 18:6a4db94011d3 330 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */
sahilmgandhi 18:6a4db94011d3 331 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */
sahilmgandhi 18:6a4db94011d3 332 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 /* Bit fields for DEVINFO ADC0CAL1 */
sahilmgandhi 18:6a4db94011d3 335 #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */
sahilmgandhi 18:6a4db94011d3 336 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */
sahilmgandhi 18:6a4db94011d3 337 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */
sahilmgandhi 18:6a4db94011d3 338 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */
sahilmgandhi 18:6a4db94011d3 339 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */
sahilmgandhi 18:6a4db94011d3 340 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */
sahilmgandhi 18:6a4db94011d3 341 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */
sahilmgandhi 18:6a4db94011d3 342 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */
sahilmgandhi 18:6a4db94011d3 343 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */
sahilmgandhi 18:6a4db94011d3 344 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */
sahilmgandhi 18:6a4db94011d3 345 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */
sahilmgandhi 18:6a4db94011d3 346 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */
sahilmgandhi 18:6a4db94011d3 347 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 /* Bit fields for DEVINFO ADC0CAL2 */
sahilmgandhi 18:6a4db94011d3 350 #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */
sahilmgandhi 18:6a4db94011d3 351 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */
sahilmgandhi 18:6a4db94011d3 352 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */
sahilmgandhi 18:6a4db94011d3 353 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */
sahilmgandhi 18:6a4db94011d3 354 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /* Bit fields for DEVINFO ADC0CAL3 */
sahilmgandhi 18:6a4db94011d3 357 #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */
sahilmgandhi 18:6a4db94011d3 358 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */
sahilmgandhi 18:6a4db94011d3 359 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 /* Bit fields for DEVINFO HFRCOCAL0 */
sahilmgandhi 18:6a4db94011d3 362 #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */
sahilmgandhi 18:6a4db94011d3 363 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 364 #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 365 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 366 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 367 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 368 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 369 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 370 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 371 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 372 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 373 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 374 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 375 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 376 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 377 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 378 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 /* Bit fields for DEVINFO HFRCOCAL3 */
sahilmgandhi 18:6a4db94011d3 381 #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */
sahilmgandhi 18:6a4db94011d3 382 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 383 #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 384 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 385 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 386 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 387 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 388 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 389 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 390 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 391 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 392 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 393 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 394 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 395 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 396 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 397 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 /* Bit fields for DEVINFO HFRCOCAL6 */
sahilmgandhi 18:6a4db94011d3 400 #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */
sahilmgandhi 18:6a4db94011d3 401 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 402 #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 403 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 404 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 405 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 406 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 407 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 408 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 409 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 410 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 411 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 412 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 413 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 414 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 415 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 416 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 /* Bit fields for DEVINFO HFRCOCAL7 */
sahilmgandhi 18:6a4db94011d3 419 #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */
sahilmgandhi 18:6a4db94011d3 420 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 421 #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 422 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 423 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 424 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 425 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 426 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 427 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 428 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 429 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 430 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 431 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 432 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 433 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 434 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 435 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /* Bit fields for DEVINFO HFRCOCAL8 */
sahilmgandhi 18:6a4db94011d3 438 #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */
sahilmgandhi 18:6a4db94011d3 439 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 440 #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 441 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 442 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 443 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 444 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 445 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 446 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 447 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 448 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 449 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 450 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 451 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 452 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 453 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 454 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 /* Bit fields for DEVINFO HFRCOCAL10 */
sahilmgandhi 18:6a4db94011d3 457 #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */
sahilmgandhi 18:6a4db94011d3 458 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 459 #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 460 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 461 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 462 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 463 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 464 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 465 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 466 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 467 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 468 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 469 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 470 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 471 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 472 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 473 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /* Bit fields for DEVINFO HFRCOCAL11 */
sahilmgandhi 18:6a4db94011d3 476 #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */
sahilmgandhi 18:6a4db94011d3 477 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 478 #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 479 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 480 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 481 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 482 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 483 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 484 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 485 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 486 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 487 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 488 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 489 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 490 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 491 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 492 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /* Bit fields for DEVINFO HFRCOCAL12 */
sahilmgandhi 18:6a4db94011d3 495 #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */
sahilmgandhi 18:6a4db94011d3 496 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 497 #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 498 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 499 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 500 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 501 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 502 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 503 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 504 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 505 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 506 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 507 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 508 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 509 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 510 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 511 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 /* Bit fields for DEVINFO AUXHFRCOCAL0 */
sahilmgandhi 18:6a4db94011d3 514 #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */
sahilmgandhi 18:6a4db94011d3 515 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 516 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 517 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 518 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 519 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 520 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 521 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 522 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 523 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 524 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 525 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 526 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 527 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 528 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 529 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 530 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 531
sahilmgandhi 18:6a4db94011d3 532 /* Bit fields for DEVINFO AUXHFRCOCAL3 */
sahilmgandhi 18:6a4db94011d3 533 #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */
sahilmgandhi 18:6a4db94011d3 534 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 535 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 536 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 537 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 538 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 539 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 540 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 541 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 542 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 543 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 544 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 545 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 546 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 547 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 548 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 549 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 /* Bit fields for DEVINFO AUXHFRCOCAL6 */
sahilmgandhi 18:6a4db94011d3 552 #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */
sahilmgandhi 18:6a4db94011d3 553 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 554 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 555 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 556 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 557 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 558 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 559 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 560 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 561 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 562 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 563 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 564 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 565 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 566 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 567 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 568 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /* Bit fields for DEVINFO AUXHFRCOCAL7 */
sahilmgandhi 18:6a4db94011d3 571 #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */
sahilmgandhi 18:6a4db94011d3 572 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 573 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 574 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 575 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 576 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 577 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 578 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 579 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 580 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 581 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 582 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 583 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 584 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 585 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 586 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 587 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 588
sahilmgandhi 18:6a4db94011d3 589 /* Bit fields for DEVINFO AUXHFRCOCAL8 */
sahilmgandhi 18:6a4db94011d3 590 #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */
sahilmgandhi 18:6a4db94011d3 591 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 592 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 593 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 594 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 595 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 596 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 597 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 598 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 599 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 600 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 601 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 602 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 603 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 604 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 605 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 606 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /* Bit fields for DEVINFO AUXHFRCOCAL10 */
sahilmgandhi 18:6a4db94011d3 609 #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */
sahilmgandhi 18:6a4db94011d3 610 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 611 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 612 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 613 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 614 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 615 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 616 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 617 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 618 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 619 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 620 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 621 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 622 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 623 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 624 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 625 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 /* Bit fields for DEVINFO AUXHFRCOCAL11 */
sahilmgandhi 18:6a4db94011d3 628 #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */
sahilmgandhi 18:6a4db94011d3 629 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 630 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 631 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 632 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 633 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 634 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 635 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 636 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 637 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 638 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 639 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 640 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 641 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 642 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 643 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 644 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 /* Bit fields for DEVINFO AUXHFRCOCAL12 */
sahilmgandhi 18:6a4db94011d3 647 #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */
sahilmgandhi 18:6a4db94011d3 648 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */
sahilmgandhi 18:6a4db94011d3 649 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */
sahilmgandhi 18:6a4db94011d3 650 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */
sahilmgandhi 18:6a4db94011d3 651 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */
sahilmgandhi 18:6a4db94011d3 652 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 653 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */
sahilmgandhi 18:6a4db94011d3 654 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 655 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */
sahilmgandhi 18:6a4db94011d3 656 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */
sahilmgandhi 18:6a4db94011d3 657 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */
sahilmgandhi 18:6a4db94011d3 658 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */
sahilmgandhi 18:6a4db94011d3 659 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */
sahilmgandhi 18:6a4db94011d3 660 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 661 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */
sahilmgandhi 18:6a4db94011d3 662 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */
sahilmgandhi 18:6a4db94011d3 663 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */
sahilmgandhi 18:6a4db94011d3 664
sahilmgandhi 18:6a4db94011d3 665 /* Bit fields for DEVINFO VMONCAL0 */
sahilmgandhi 18:6a4db94011d3 666 #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */
sahilmgandhi 18:6a4db94011d3 667 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 668 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 669 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 670 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 671 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 672 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 673 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 674 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 675 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 676 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 677 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 678 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 679 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 680 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 681 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 682 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 683
sahilmgandhi 18:6a4db94011d3 684 /* Bit fields for DEVINFO VMONCAL1 */
sahilmgandhi 18:6a4db94011d3 685 #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */
sahilmgandhi 18:6a4db94011d3 686 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 687 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 688 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 689 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 690 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 691 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 692 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 693 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 694 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 695 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 696 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 697 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 698 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 699 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 700 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 701 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 /* Bit fields for DEVINFO VMONCAL2 */
sahilmgandhi 18:6a4db94011d3 704 #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */
sahilmgandhi 18:6a4db94011d3 705 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 706 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 707 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 708 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 709 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 710 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 711 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 712 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 713 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 714 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */
sahilmgandhi 18:6a4db94011d3 715 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 716 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 717 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 718 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */
sahilmgandhi 18:6a4db94011d3 719 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 720 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */
sahilmgandhi 18:6a4db94011d3 721
sahilmgandhi 18:6a4db94011d3 722 /* Bit fields for DEVINFO IDAC0CAL0 */
sahilmgandhi 18:6a4db94011d3 723 #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */
sahilmgandhi 18:6a4db94011d3 724 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */
sahilmgandhi 18:6a4db94011d3 725 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */
sahilmgandhi 18:6a4db94011d3 726 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */
sahilmgandhi 18:6a4db94011d3 727 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */
sahilmgandhi 18:6a4db94011d3 728 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */
sahilmgandhi 18:6a4db94011d3 729 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */
sahilmgandhi 18:6a4db94011d3 730 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */
sahilmgandhi 18:6a4db94011d3 731 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */
sahilmgandhi 18:6a4db94011d3 732
sahilmgandhi 18:6a4db94011d3 733 /* Bit fields for DEVINFO IDAC0CAL1 */
sahilmgandhi 18:6a4db94011d3 734 #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */
sahilmgandhi 18:6a4db94011d3 735 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */
sahilmgandhi 18:6a4db94011d3 736 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */
sahilmgandhi 18:6a4db94011d3 737 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */
sahilmgandhi 18:6a4db94011d3 738 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */
sahilmgandhi 18:6a4db94011d3 739 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */
sahilmgandhi 18:6a4db94011d3 740 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */
sahilmgandhi 18:6a4db94011d3 741 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */
sahilmgandhi 18:6a4db94011d3 742 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */
sahilmgandhi 18:6a4db94011d3 743
sahilmgandhi 18:6a4db94011d3 744 /* Bit fields for DEVINFO DCDCLNVCTRL0 */
sahilmgandhi 18:6a4db94011d3 745 #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */
sahilmgandhi 18:6a4db94011d3 746 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */
sahilmgandhi 18:6a4db94011d3 747 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */
sahilmgandhi 18:6a4db94011d3 748 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */
sahilmgandhi 18:6a4db94011d3 749 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */
sahilmgandhi 18:6a4db94011d3 750 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */
sahilmgandhi 18:6a4db94011d3 751 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */
sahilmgandhi 18:6a4db94011d3 752 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */
sahilmgandhi 18:6a4db94011d3 753 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 /* Bit fields for DEVINFO DCDCLPVCTRL0 */
sahilmgandhi 18:6a4db94011d3 756 #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */
sahilmgandhi 18:6a4db94011d3 757 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 758 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 759 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 760 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 761 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 762 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 763 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 764 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 765
sahilmgandhi 18:6a4db94011d3 766 /* Bit fields for DEVINFO DCDCLPVCTRL1 */
sahilmgandhi 18:6a4db94011d3 767 #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */
sahilmgandhi 18:6a4db94011d3 768 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 769 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 770 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 771 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 772 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 773 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 774 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 775 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 776
sahilmgandhi 18:6a4db94011d3 777 /* Bit fields for DEVINFO DCDCLPVCTRL2 */
sahilmgandhi 18:6a4db94011d3 778 #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */
sahilmgandhi 18:6a4db94011d3 779 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 780 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 781 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 782 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 783 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 784 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 785 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 786 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 /* Bit fields for DEVINFO DCDCLPVCTRL3 */
sahilmgandhi 18:6a4db94011d3 789 #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */
sahilmgandhi 18:6a4db94011d3 790 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 791 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 792 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 793 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 794 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 795 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 796 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 797 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
sahilmgandhi 18:6a4db94011d3 800 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */
sahilmgandhi 18:6a4db94011d3 801 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */
sahilmgandhi 18:6a4db94011d3 802 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */
sahilmgandhi 18:6a4db94011d3 803 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */
sahilmgandhi 18:6a4db94011d3 804 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */
sahilmgandhi 18:6a4db94011d3 805
sahilmgandhi 18:6a4db94011d3 806 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
sahilmgandhi 18:6a4db94011d3 807 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */
sahilmgandhi 18:6a4db94011d3 808 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 809 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */
sahilmgandhi 18:6a4db94011d3 810 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 811 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */
sahilmgandhi 18:6a4db94011d3 812 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 813 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */
sahilmgandhi 18:6a4db94011d3 814 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 815 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */
sahilmgandhi 18:6a4db94011d3 816
sahilmgandhi 18:6a4db94011d3 817 /** @} End of group EFR32MG1P_DEVINFO */
sahilmgandhi 18:6a4db94011d3 818 /** @} End of group Parts */
sahilmgandhi 18:6a4db94011d3 819