MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/gpio_irq_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /* mbed Microcontroller Library
sahilmgandhi 18:6a4db94011d3 2 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * Copyright (c) 2014, STMicroelectronics
sahilmgandhi 18:6a4db94011d3 4 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 5 *
sahilmgandhi 18:6a4db94011d3 6 * Redistribution and use in source and binary forms, with or without
sahilmgandhi 18:6a4db94011d3 7 * modification, are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 10 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 12 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 13 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 15 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 16 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 28 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 29 */
sahilmgandhi 18:6a4db94011d3 30 #include <stddef.h>
sahilmgandhi 18:6a4db94011d3 31 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 32 #include "gpio_irq_api.h"
sahilmgandhi 18:6a4db94011d3 33 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 34 #include "mbed_error.h"
sahilmgandhi 18:6a4db94011d3 35 #include "gpio_irq_device.h"
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #define EDGE_NONE (0)
sahilmgandhi 18:6a4db94011d3 38 #define EDGE_RISE (1)
sahilmgandhi 18:6a4db94011d3 39 #define EDGE_FALL (2)
sahilmgandhi 18:6a4db94011d3 40 #define EDGE_BOTH (3)
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 typedef struct gpio_channel {
sahilmgandhi 18:6a4db94011d3 44 uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
sahilmgandhi 18:6a4db94011d3 45 uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
sahilmgandhi 18:6a4db94011d3 46 GPIO_TypeDef* channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
sahilmgandhi 18:6a4db94011d3 47 uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
sahilmgandhi 18:6a4db94011d3 48 } gpio_channel_t;
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 static gpio_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 static gpio_channel_t channels[CHANNEL_NUM] = {
sahilmgandhi 18:6a4db94011d3 53 #ifdef EXTI_IRQ0_NUM_LINES
sahilmgandhi 18:6a4db94011d3 54 {.pin_mask = 0},
sahilmgandhi 18:6a4db94011d3 55 #endif
sahilmgandhi 18:6a4db94011d3 56 #ifdef EXTI_IRQ1_NUM_LINES
sahilmgandhi 18:6a4db94011d3 57 {.pin_mask = 0},
sahilmgandhi 18:6a4db94011d3 58 #endif
sahilmgandhi 18:6a4db94011d3 59 #ifdef EXTI_IRQ2_NUM_LINES
sahilmgandhi 18:6a4db94011d3 60 {.pin_mask = 0},
sahilmgandhi 18:6a4db94011d3 61 #endif
sahilmgandhi 18:6a4db94011d3 62 #ifdef EXTI_IRQ3_NUM_LINES
sahilmgandhi 18:6a4db94011d3 63 {.pin_mask = 0},
sahilmgandhi 18:6a4db94011d3 64 #endif
sahilmgandhi 18:6a4db94011d3 65 #ifdef EXTI_IRQ4_NUM_LINES
sahilmgandhi 18:6a4db94011d3 66 {.pin_mask = 0},
sahilmgandhi 18:6a4db94011d3 67 #endif
sahilmgandhi 18:6a4db94011d3 68 #ifdef EXTI_IRQ5_NUM_LINES
sahilmgandhi 18:6a4db94011d3 69 {.pin_mask = 0},
sahilmgandhi 18:6a4db94011d3 70 #endif
sahilmgandhi 18:6a4db94011d3 71 #ifdef EXTI_IRQ6_NUM_LINES
sahilmgandhi 18:6a4db94011d3 72 {.pin_mask = 0}
sahilmgandhi 18:6a4db94011d3 73 #endif
sahilmgandhi 18:6a4db94011d3 74 };
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
sahilmgandhi 18:6a4db94011d3 77 {
sahilmgandhi 18:6a4db94011d3 78 gpio_channel_t *gpio_channel = &channels[irq_index];
sahilmgandhi 18:6a4db94011d3 79 uint32_t gpio_idx;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
sahilmgandhi 18:6a4db94011d3 82 uint32_t current_mask = (1 << gpio_idx);
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 if (gpio_channel->pin_mask & current_mask) {
sahilmgandhi 18:6a4db94011d3 85 // Retrieve the gpio and pin that generate the irq
sahilmgandhi 18:6a4db94011d3 86 GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
sahilmgandhi 18:6a4db94011d3 87 uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 // Clear interrupt flag
sahilmgandhi 18:6a4db94011d3 90 if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
sahilmgandhi 18:6a4db94011d3 91 __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 if (gpio_channel->channel_ids[gpio_idx] == 0)
sahilmgandhi 18:6a4db94011d3 94 continue;
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 // Check which edge has generated the irq
sahilmgandhi 18:6a4db94011d3 97 if ((gpio->IDR & pin) == 0) {
sahilmgandhi 18:6a4db94011d3 98 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
sahilmgandhi 18:6a4db94011d3 99 } else {
sahilmgandhi 18:6a4db94011d3 100 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
sahilmgandhi 18:6a4db94011d3 101 }
sahilmgandhi 18:6a4db94011d3 102 }
sahilmgandhi 18:6a4db94011d3 103 }
sahilmgandhi 18:6a4db94011d3 104 }
sahilmgandhi 18:6a4db94011d3 105 }
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 #ifdef EXTI_IRQ0_NUM_LINES
sahilmgandhi 18:6a4db94011d3 109 // EXTI line 0
sahilmgandhi 18:6a4db94011d3 110 static void gpio_irq0(void)
sahilmgandhi 18:6a4db94011d3 111 {
sahilmgandhi 18:6a4db94011d3 112 handle_interrupt_in(0, EXTI_IRQ0_NUM_LINES);
sahilmgandhi 18:6a4db94011d3 113 }
sahilmgandhi 18:6a4db94011d3 114 #endif
sahilmgandhi 18:6a4db94011d3 115 #ifdef EXTI_IRQ1_NUM_LINES
sahilmgandhi 18:6a4db94011d3 116 // EXTI line 1
sahilmgandhi 18:6a4db94011d3 117 static void gpio_irq1(void)
sahilmgandhi 18:6a4db94011d3 118 {
sahilmgandhi 18:6a4db94011d3 119 handle_interrupt_in(1, EXTI_IRQ1_NUM_LINES);
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121 #endif
sahilmgandhi 18:6a4db94011d3 122 #ifdef EXTI_IRQ2_NUM_LINES
sahilmgandhi 18:6a4db94011d3 123 // EXTI line 2
sahilmgandhi 18:6a4db94011d3 124 static void gpio_irq2(void)
sahilmgandhi 18:6a4db94011d3 125 {
sahilmgandhi 18:6a4db94011d3 126 handle_interrupt_in(2, EXTI_IRQ2_NUM_LINES);
sahilmgandhi 18:6a4db94011d3 127 }
sahilmgandhi 18:6a4db94011d3 128 #endif
sahilmgandhi 18:6a4db94011d3 129 #ifdef EXTI_IRQ3_NUM_LINES
sahilmgandhi 18:6a4db94011d3 130 // EXTI line 3
sahilmgandhi 18:6a4db94011d3 131 static void gpio_irq3(void)
sahilmgandhi 18:6a4db94011d3 132 {
sahilmgandhi 18:6a4db94011d3 133 handle_interrupt_in(3, EXTI_IRQ3_NUM_LINES);
sahilmgandhi 18:6a4db94011d3 134 }
sahilmgandhi 18:6a4db94011d3 135 #endif
sahilmgandhi 18:6a4db94011d3 136 #ifdef EXTI_IRQ4_NUM_LINES
sahilmgandhi 18:6a4db94011d3 137 // EXTI line 4
sahilmgandhi 18:6a4db94011d3 138 static void gpio_irq4(void)
sahilmgandhi 18:6a4db94011d3 139 {
sahilmgandhi 18:6a4db94011d3 140 handle_interrupt_in(4, EXTI_IRQ4_NUM_LINES);
sahilmgandhi 18:6a4db94011d3 141 }
sahilmgandhi 18:6a4db94011d3 142 #endif
sahilmgandhi 18:6a4db94011d3 143 #ifdef EXTI_IRQ5_NUM_LINES
sahilmgandhi 18:6a4db94011d3 144 // EXTI lines 5 to 9
sahilmgandhi 18:6a4db94011d3 145 static void gpio_irq5(void)
sahilmgandhi 18:6a4db94011d3 146 {
sahilmgandhi 18:6a4db94011d3 147 handle_interrupt_in(5, EXTI_IRQ5_NUM_LINES);
sahilmgandhi 18:6a4db94011d3 148 }
sahilmgandhi 18:6a4db94011d3 149 #endif
sahilmgandhi 18:6a4db94011d3 150 #ifdef EXTI_IRQ6_NUM_LINES
sahilmgandhi 18:6a4db94011d3 151 // EXTI lines 10 to 15
sahilmgandhi 18:6a4db94011d3 152 static void gpio_irq6(void)
sahilmgandhi 18:6a4db94011d3 153 {
sahilmgandhi 18:6a4db94011d3 154 handle_interrupt_in(6, EXTI_IRQ6_NUM_LINES);
sahilmgandhi 18:6a4db94011d3 155 }
sahilmgandhi 18:6a4db94011d3 156 #endif
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx);
sahilmgandhi 18:6a4db94011d3 159 extern void pin_function_gpiomode(PinName pin, uint32_t gpiomode);
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 162 {
sahilmgandhi 18:6a4db94011d3 163 uint32_t vector = 0;
sahilmgandhi 18:6a4db94011d3 164 uint32_t irq_index;
sahilmgandhi 18:6a4db94011d3 165 gpio_channel_t *gpio_channel;
sahilmgandhi 18:6a4db94011d3 166 uint32_t gpio_idx;
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 if (pin == NC) return -1;
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 /* Enable SYSCFG Clock */
sahilmgandhi 18:6a4db94011d3 171 __HAL_RCC_SYSCFG_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 uint32_t port_index = STM_PORT(pin);
sahilmgandhi 18:6a4db94011d3 174 uint32_t pin_index = STM_PIN(pin);
sahilmgandhi 18:6a4db94011d3 175 irq_index = pin_lines_desc[pin_index].irq_index;
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 switch (irq_index) {
sahilmgandhi 18:6a4db94011d3 178 #ifdef EXTI_IRQ0_NUM_LINES
sahilmgandhi 18:6a4db94011d3 179 case 0:
sahilmgandhi 18:6a4db94011d3 180 vector = (uint32_t)&gpio_irq0;
sahilmgandhi 18:6a4db94011d3 181 break;
sahilmgandhi 18:6a4db94011d3 182 #endif
sahilmgandhi 18:6a4db94011d3 183 #ifdef EXTI_IRQ1_NUM_LINES
sahilmgandhi 18:6a4db94011d3 184 case 1:
sahilmgandhi 18:6a4db94011d3 185 vector = (uint32_t)&gpio_irq1;
sahilmgandhi 18:6a4db94011d3 186 break;
sahilmgandhi 18:6a4db94011d3 187 #endif
sahilmgandhi 18:6a4db94011d3 188 #ifdef EXTI_IRQ2_NUM_LINES
sahilmgandhi 18:6a4db94011d3 189 case 2:
sahilmgandhi 18:6a4db94011d3 190 vector = (uint32_t)&gpio_irq2;
sahilmgandhi 18:6a4db94011d3 191 break;
sahilmgandhi 18:6a4db94011d3 192 #endif
sahilmgandhi 18:6a4db94011d3 193 #ifdef EXTI_IRQ3_NUM_LINES
sahilmgandhi 18:6a4db94011d3 194 case 3:
sahilmgandhi 18:6a4db94011d3 195 vector = (uint32_t)&gpio_irq3;
sahilmgandhi 18:6a4db94011d3 196 break;
sahilmgandhi 18:6a4db94011d3 197 #endif
sahilmgandhi 18:6a4db94011d3 198 #ifdef EXTI_IRQ4_NUM_LINES
sahilmgandhi 18:6a4db94011d3 199 case 4:
sahilmgandhi 18:6a4db94011d3 200 vector = (uint32_t)&gpio_irq4;
sahilmgandhi 18:6a4db94011d3 201 break;
sahilmgandhi 18:6a4db94011d3 202 #endif
sahilmgandhi 18:6a4db94011d3 203 #ifdef EXTI_IRQ5_NUM_LINES
sahilmgandhi 18:6a4db94011d3 204 case 5:
sahilmgandhi 18:6a4db94011d3 205 vector = (uint32_t)&gpio_irq5;
sahilmgandhi 18:6a4db94011d3 206 break;
sahilmgandhi 18:6a4db94011d3 207 #endif
sahilmgandhi 18:6a4db94011d3 208 #ifdef EXTI_IRQ6_NUM_LINES
sahilmgandhi 18:6a4db94011d3 209 case 6:
sahilmgandhi 18:6a4db94011d3 210 vector = (uint32_t)&gpio_irq6;
sahilmgandhi 18:6a4db94011d3 211 break;
sahilmgandhi 18:6a4db94011d3 212 #endif
sahilmgandhi 18:6a4db94011d3 213 default:
sahilmgandhi 18:6a4db94011d3 214 error("InterruptIn error: pin not supported.\n");
sahilmgandhi 18:6a4db94011d3 215 return -1;
sahilmgandhi 18:6a4db94011d3 216 }
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 // Enable GPIO clock
sahilmgandhi 18:6a4db94011d3 219 GPIO_TypeDef *gpio_add = Set_GPIO_Clock(port_index);
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 // Save informations for future use
sahilmgandhi 18:6a4db94011d3 222 obj->irq_n = pin_lines_desc[pin_index].irq_n;
sahilmgandhi 18:6a4db94011d3 223 obj->irq_index = pin_lines_desc[pin_index].irq_index;
sahilmgandhi 18:6a4db94011d3 224 obj->event = EDGE_NONE;
sahilmgandhi 18:6a4db94011d3 225 obj->pin = pin;
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 gpio_channel = &channels[irq_index];
sahilmgandhi 18:6a4db94011d3 228 gpio_idx = pin_lines_desc[pin_index].gpio_idx;
sahilmgandhi 18:6a4db94011d3 229 gpio_channel->pin_mask |= (1 << gpio_idx);
sahilmgandhi 18:6a4db94011d3 230 gpio_channel->channel_ids[gpio_idx] = id;
sahilmgandhi 18:6a4db94011d3 231 gpio_channel->channel_gpio[gpio_idx] = gpio_add;
sahilmgandhi 18:6a4db94011d3 232 gpio_channel->channel_pin[gpio_idx] = pin_index;
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 // Enable EXTI interrupt
sahilmgandhi 18:6a4db94011d3 237 NVIC_SetVector(obj->irq_n, vector);
sahilmgandhi 18:6a4db94011d3 238 gpio_irq_enable(obj);
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 return 0;
sahilmgandhi 18:6a4db94011d3 241 }
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 void gpio_irq_free(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 244 {
sahilmgandhi 18:6a4db94011d3 245 uint32_t gpio_idx = pin_lines_desc[STM_PIN(obj->pin)].gpio_idx;
sahilmgandhi 18:6a4db94011d3 246 gpio_channel_t *gpio_channel = &channels[obj->irq_index];
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 gpio_irq_disable(obj);
sahilmgandhi 18:6a4db94011d3 249 gpio_channel->pin_mask &= ~(1 << gpio_idx);
sahilmgandhi 18:6a4db94011d3 250 gpio_channel->channel_ids[gpio_idx] = 0;
sahilmgandhi 18:6a4db94011d3 251 gpio_channel->channel_gpio[gpio_idx] = 0;
sahilmgandhi 18:6a4db94011d3 252 gpio_channel->channel_pin[gpio_idx] = 0;
sahilmgandhi 18:6a4db94011d3 253 }
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 256 {
sahilmgandhi 18:6a4db94011d3 257 if (event == IRQ_RISE) {
sahilmgandhi 18:6a4db94011d3 258 if (enable) {
sahilmgandhi 18:6a4db94011d3 259 LL_EXTI_EnableRisingTrig_0_31(1 << STM_PIN(obj->pin));
sahilmgandhi 18:6a4db94011d3 260 } else {
sahilmgandhi 18:6a4db94011d3 261 LL_EXTI_DisableRisingTrig_0_31(1 << STM_PIN(obj->pin));
sahilmgandhi 18:6a4db94011d3 262 }
sahilmgandhi 18:6a4db94011d3 263 }
sahilmgandhi 18:6a4db94011d3 264 if (event == IRQ_FALL) {
sahilmgandhi 18:6a4db94011d3 265 if (enable) {
sahilmgandhi 18:6a4db94011d3 266 LL_EXTI_EnableFallingTrig_0_31(1 << STM_PIN(obj->pin));
sahilmgandhi 18:6a4db94011d3 267 } else {
sahilmgandhi 18:6a4db94011d3 268 LL_EXTI_DisableFallingTrig_0_31(1 << STM_PIN(obj->pin));
sahilmgandhi 18:6a4db94011d3 269 }
sahilmgandhi 18:6a4db94011d3 270 }
sahilmgandhi 18:6a4db94011d3 271 }
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 void gpio_irq_enable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 274 {
sahilmgandhi 18:6a4db94011d3 275 uint32_t temp = 0;
sahilmgandhi 18:6a4db94011d3 276 uint32_t port_index = STM_PORT(obj->pin);
sahilmgandhi 18:6a4db94011d3 277 uint32_t pin_index = STM_PIN(obj->pin);
sahilmgandhi 18:6a4db94011d3 278
sahilmgandhi 18:6a4db94011d3 279 /* Select Source */
sahilmgandhi 18:6a4db94011d3 280 temp = SYSCFG->EXTICR[pin_index >> 2];
sahilmgandhi 18:6a4db94011d3 281 CLEAR_BIT(temp, (0x0FU) << (4U * (pin_index & 0x03U)));
sahilmgandhi 18:6a4db94011d3 282 SET_BIT(temp, port_index << (4U * (pin_index & 0x03U)));
sahilmgandhi 18:6a4db94011d3 283 SYSCFG->EXTICR[pin_index >> 2] = temp;
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 LL_EXTI_EnableIT_0_31(1 << pin_index);
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 NVIC_EnableIRQ(obj->irq_n);
sahilmgandhi 18:6a4db94011d3 288 }
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 void gpio_irq_disable(gpio_irq_t *obj)
sahilmgandhi 18:6a4db94011d3 291 {
sahilmgandhi 18:6a4db94011d3 292 /* Clear EXTI line configuration */
sahilmgandhi 18:6a4db94011d3 293 LL_EXTI_DisableIT_0_31(1 << STM_PIN(obj->pin));
sahilmgandhi 18:6a4db94011d3 294 NVIC_DisableIRQ(obj->irq_n);
sahilmgandhi 18:6a4db94011d3 295 NVIC_ClearPendingIRQ(obj->irq_n);
sahilmgandhi 18:6a4db94011d3 296 obj->event = EDGE_NONE;
sahilmgandhi 18:6a4db94011d3 297 }