Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file system_stm32l0xx.c |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @author MCD Application Team |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V1.7.0 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 31-May-2016 |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. |
sahilmgandhi | 18:6a4db94011d3 | 8 | * |
sahilmgandhi | 18:6a4db94011d3 | 9 | * This file provides two functions and one global variable to be called from |
sahilmgandhi | 18:6a4db94011d3 | 10 | * user application: |
sahilmgandhi | 18:6a4db94011d3 | 11 | * - SystemInit(): This function is called at startup just after reset and |
sahilmgandhi | 18:6a4db94011d3 | 12 | * before branch to main program. This call is made inside |
sahilmgandhi | 18:6a4db94011d3 | 13 | * the "startup_stm32l0xx.s" file. |
sahilmgandhi | 18:6a4db94011d3 | 14 | * |
sahilmgandhi | 18:6a4db94011d3 | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
sahilmgandhi | 18:6a4db94011d3 | 16 | * by the user application to setup the SysTick |
sahilmgandhi | 18:6a4db94011d3 | 17 | * timer or configure other parameters. |
sahilmgandhi | 18:6a4db94011d3 | 18 | * |
sahilmgandhi | 18:6a4db94011d3 | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
sahilmgandhi | 18:6a4db94011d3 | 20 | * be called whenever the core clock is changed |
sahilmgandhi | 18:6a4db94011d3 | 21 | * during program execution. |
sahilmgandhi | 18:6a4db94011d3 | 22 | * |
sahilmgandhi | 18:6a4db94011d3 | 23 | * This file configures the system clock as follows: |
sahilmgandhi | 18:6a4db94011d3 | 24 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 25 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
sahilmgandhi | 18:6a4db94011d3 | 26 | * | (external 8 MHz clock) | (internal 16 MHz) |
sahilmgandhi | 18:6a4db94011d3 | 27 | * | 2- PLL_HSE_XTAL | |
sahilmgandhi | 18:6a4db94011d3 | 28 | * | (external 8 MHz xtal) | |
sahilmgandhi | 18:6a4db94011d3 | 29 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 30 | * SYSCLK(MHz) | 32 | 32 |
sahilmgandhi | 18:6a4db94011d3 | 31 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 32 | * AHBCLK (MHz) | 32 | 32 |
sahilmgandhi | 18:6a4db94011d3 | 33 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 34 | * APB1CLK (MHz) | 32 | 32 |
sahilmgandhi | 18:6a4db94011d3 | 35 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 36 | * APB2CLK (MHz) | 32 | 32 |
sahilmgandhi | 18:6a4db94011d3 | 37 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 38 | * USB capable (48 MHz precise clock) | YES | YES |
sahilmgandhi | 18:6a4db94011d3 | 39 | *----------------------------------------------------------------------------- |
sahilmgandhi | 18:6a4db94011d3 | 40 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 41 | * @attention |
sahilmgandhi | 18:6a4db94011d3 | 42 | * |
sahilmgandhi | 18:6a4db94011d3 | 43 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
sahilmgandhi | 18:6a4db94011d3 | 44 | * |
sahilmgandhi | 18:6a4db94011d3 | 45 | * Redistribution and use in source and binary forms, with or without modification, |
sahilmgandhi | 18:6a4db94011d3 | 46 | * are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 47 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 48 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 49 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 50 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 51 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 52 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 53 | * may be used to endorse or promote products derived from this software |
sahilmgandhi | 18:6a4db94011d3 | 54 | * without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 55 | * |
sahilmgandhi | 18:6a4db94011d3 | 56 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 57 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 58 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
sahilmgandhi | 18:6a4db94011d3 | 59 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
sahilmgandhi | 18:6a4db94011d3 | 60 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 61 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
sahilmgandhi | 18:6a4db94011d3 | 62 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
sahilmgandhi | 18:6a4db94011d3 | 63 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
sahilmgandhi | 18:6a4db94011d3 | 64 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
sahilmgandhi | 18:6a4db94011d3 | 65 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 66 | * |
sahilmgandhi | 18:6a4db94011d3 | 67 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 68 | */ |
sahilmgandhi | 18:6a4db94011d3 | 69 | |
sahilmgandhi | 18:6a4db94011d3 | 70 | /** @addtogroup CMSIS |
sahilmgandhi | 18:6a4db94011d3 | 71 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 72 | */ |
sahilmgandhi | 18:6a4db94011d3 | 73 | |
sahilmgandhi | 18:6a4db94011d3 | 74 | /** @addtogroup stm32l0xx_system |
sahilmgandhi | 18:6a4db94011d3 | 75 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 76 | */ |
sahilmgandhi | 18:6a4db94011d3 | 77 | |
sahilmgandhi | 18:6a4db94011d3 | 78 | /** @addtogroup STM32L0xx_System_Private_Includes |
sahilmgandhi | 18:6a4db94011d3 | 79 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 80 | */ |
sahilmgandhi | 18:6a4db94011d3 | 81 | |
sahilmgandhi | 18:6a4db94011d3 | 82 | #include "stm32l0xx.h" |
sahilmgandhi | 18:6a4db94011d3 | 83 | #include "hal_tick.h" |
sahilmgandhi | 18:6a4db94011d3 | 84 | |
sahilmgandhi | 18:6a4db94011d3 | 85 | #if !defined (HSE_VALUE) |
sahilmgandhi | 18:6a4db94011d3 | 86 | #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ |
sahilmgandhi | 18:6a4db94011d3 | 87 | #endif /* HSE_VALUE */ |
sahilmgandhi | 18:6a4db94011d3 | 88 | |
sahilmgandhi | 18:6a4db94011d3 | 89 | #if !defined (MSI_VALUE) |
sahilmgandhi | 18:6a4db94011d3 | 90 | #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ |
sahilmgandhi | 18:6a4db94011d3 | 91 | #endif /* MSI_VALUE */ |
sahilmgandhi | 18:6a4db94011d3 | 92 | |
sahilmgandhi | 18:6a4db94011d3 | 93 | #if !defined (HSI_VALUE) |
sahilmgandhi | 18:6a4db94011d3 | 94 | #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ |
sahilmgandhi | 18:6a4db94011d3 | 95 | #endif /* HSI_VALUE */ |
sahilmgandhi | 18:6a4db94011d3 | 96 | |
sahilmgandhi | 18:6a4db94011d3 | 97 | |
sahilmgandhi | 18:6a4db94011d3 | 98 | /** |
sahilmgandhi | 18:6a4db94011d3 | 99 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 100 | */ |
sahilmgandhi | 18:6a4db94011d3 | 101 | |
sahilmgandhi | 18:6a4db94011d3 | 102 | /** @addtogroup STM32L0xx_System_Private_TypesDefinitions |
sahilmgandhi | 18:6a4db94011d3 | 103 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 104 | */ |
sahilmgandhi | 18:6a4db94011d3 | 105 | |
sahilmgandhi | 18:6a4db94011d3 | 106 | /** |
sahilmgandhi | 18:6a4db94011d3 | 107 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 108 | */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | |
sahilmgandhi | 18:6a4db94011d3 | 110 | /** @addtogroup STM32L0xx_System_Private_Defines |
sahilmgandhi | 18:6a4db94011d3 | 111 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 112 | */ |
sahilmgandhi | 18:6a4db94011d3 | 113 | /************************* Miscellaneous Configuration ************************/ |
sahilmgandhi | 18:6a4db94011d3 | 114 | |
sahilmgandhi | 18:6a4db94011d3 | 115 | /*!< Uncomment the following line if you need to relocate your vector Table in |
sahilmgandhi | 18:6a4db94011d3 | 116 | Internal SRAM. */ |
sahilmgandhi | 18:6a4db94011d3 | 117 | /* #define VECT_TAB_SRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 118 | #define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. |
sahilmgandhi | 18:6a4db94011d3 | 119 | This value must be a multiple of 0x100. */ |
sahilmgandhi | 18:6a4db94011d3 | 120 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 121 | /** |
sahilmgandhi | 18:6a4db94011d3 | 122 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 123 | */ |
sahilmgandhi | 18:6a4db94011d3 | 124 | |
sahilmgandhi | 18:6a4db94011d3 | 125 | /** @addtogroup STM32L0xx_System_Private_Macros |
sahilmgandhi | 18:6a4db94011d3 | 126 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 127 | */ |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
sahilmgandhi | 18:6a4db94011d3 | 130 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
sahilmgandhi | 18:6a4db94011d3 | 131 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | /** |
sahilmgandhi | 18:6a4db94011d3 | 134 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 135 | */ |
sahilmgandhi | 18:6a4db94011d3 | 136 | |
sahilmgandhi | 18:6a4db94011d3 | 137 | /** @addtogroup STM32L0xx_System_Private_Variables |
sahilmgandhi | 18:6a4db94011d3 | 138 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 139 | */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | /* This variable is updated in three ways: |
sahilmgandhi | 18:6a4db94011d3 | 141 | 1) by calling CMSIS function SystemCoreClockUpdate() |
sahilmgandhi | 18:6a4db94011d3 | 142 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
sahilmgandhi | 18:6a4db94011d3 | 143 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
sahilmgandhi | 18:6a4db94011d3 | 144 | Note: If you use this function to configure the system clock; then there |
sahilmgandhi | 18:6a4db94011d3 | 145 | is no need to call the 2 first functions listed above, since SystemCoreClock |
sahilmgandhi | 18:6a4db94011d3 | 146 | variable is updated automatically. |
sahilmgandhi | 18:6a4db94011d3 | 147 | */ |
sahilmgandhi | 18:6a4db94011d3 | 148 | uint32_t SystemCoreClock = 32000000; |
sahilmgandhi | 18:6a4db94011d3 | 149 | const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; |
sahilmgandhi | 18:6a4db94011d3 | 150 | const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; |
sahilmgandhi | 18:6a4db94011d3 | 151 | const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; |
sahilmgandhi | 18:6a4db94011d3 | 152 | |
sahilmgandhi | 18:6a4db94011d3 | 153 | /** |
sahilmgandhi | 18:6a4db94011d3 | 154 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 155 | */ |
sahilmgandhi | 18:6a4db94011d3 | 156 | |
sahilmgandhi | 18:6a4db94011d3 | 157 | /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes |
sahilmgandhi | 18:6a4db94011d3 | 158 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 159 | */ |
sahilmgandhi | 18:6a4db94011d3 | 160 | |
sahilmgandhi | 18:6a4db94011d3 | 161 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
sahilmgandhi | 18:6a4db94011d3 | 162 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
sahilmgandhi | 18:6a4db94011d3 | 163 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 164 | |
sahilmgandhi | 18:6a4db94011d3 | 165 | uint8_t SetSysClock_PLL_HSI(void); |
sahilmgandhi | 18:6a4db94011d3 | 166 | |
sahilmgandhi | 18:6a4db94011d3 | 167 | /** |
sahilmgandhi | 18:6a4db94011d3 | 168 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 169 | */ |
sahilmgandhi | 18:6a4db94011d3 | 170 | |
sahilmgandhi | 18:6a4db94011d3 | 171 | /** @addtogroup STM32L0xx_System_Private_Functions |
sahilmgandhi | 18:6a4db94011d3 | 172 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 173 | */ |
sahilmgandhi | 18:6a4db94011d3 | 174 | |
sahilmgandhi | 18:6a4db94011d3 | 175 | /** |
sahilmgandhi | 18:6a4db94011d3 | 176 | * @brief Setup the microcontroller system. |
sahilmgandhi | 18:6a4db94011d3 | 177 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 178 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 179 | */ |
sahilmgandhi | 18:6a4db94011d3 | 180 | void SystemInit (void) |
sahilmgandhi | 18:6a4db94011d3 | 181 | { |
sahilmgandhi | 18:6a4db94011d3 | 182 | /*!< Set MSION bit */ |
sahilmgandhi | 18:6a4db94011d3 | 183 | RCC->CR |= (uint32_t)0x00000100U; |
sahilmgandhi | 18:6a4db94011d3 | 184 | |
sahilmgandhi | 18:6a4db94011d3 | 185 | /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ |
sahilmgandhi | 18:6a4db94011d3 | 186 | RCC->CFGR &= (uint32_t) 0x88FF400CU; |
sahilmgandhi | 18:6a4db94011d3 | 187 | |
sahilmgandhi | 18:6a4db94011d3 | 188 | /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ |
sahilmgandhi | 18:6a4db94011d3 | 189 | RCC->CR &= (uint32_t)0xFEF6FFF6U; |
sahilmgandhi | 18:6a4db94011d3 | 190 | |
sahilmgandhi | 18:6a4db94011d3 | 191 | /*!< Reset HSI48ON bit */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; |
sahilmgandhi | 18:6a4db94011d3 | 193 | |
sahilmgandhi | 18:6a4db94011d3 | 194 | /*!< Reset HSEBYP bit */ |
sahilmgandhi | 18:6a4db94011d3 | 195 | RCC->CR &= (uint32_t)0xFFFBFFFFU; |
sahilmgandhi | 18:6a4db94011d3 | 196 | |
sahilmgandhi | 18:6a4db94011d3 | 197 | /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ |
sahilmgandhi | 18:6a4db94011d3 | 198 | RCC->CFGR &= (uint32_t)0xFF02FFFFU; |
sahilmgandhi | 18:6a4db94011d3 | 199 | |
sahilmgandhi | 18:6a4db94011d3 | 200 | /*!< Disable all interrupts */ |
sahilmgandhi | 18:6a4db94011d3 | 201 | RCC->CIER = 0x00000000U; |
sahilmgandhi | 18:6a4db94011d3 | 202 | |
sahilmgandhi | 18:6a4db94011d3 | 203 | /* Configure the Vector Table location add offset address ------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 204 | #ifdef VECT_TAB_SRAM |
sahilmgandhi | 18:6a4db94011d3 | 205 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
sahilmgandhi | 18:6a4db94011d3 | 206 | #else |
sahilmgandhi | 18:6a4db94011d3 | 207 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
sahilmgandhi | 18:6a4db94011d3 | 208 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 209 | |
sahilmgandhi | 18:6a4db94011d3 | 210 | /* Configure the Cube driver */ |
sahilmgandhi | 18:6a4db94011d3 | 211 | SystemCoreClock = 8000000; // At this stage the HSI is used as system clock |
sahilmgandhi | 18:6a4db94011d3 | 212 | HAL_Init(); |
sahilmgandhi | 18:6a4db94011d3 | 213 | |
sahilmgandhi | 18:6a4db94011d3 | 214 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
sahilmgandhi | 18:6a4db94011d3 | 215 | AHB/APBx prescalers and Flash settings */ |
sahilmgandhi | 18:6a4db94011d3 | 216 | SetSysClock(); |
sahilmgandhi | 18:6a4db94011d3 | 217 | |
sahilmgandhi | 18:6a4db94011d3 | 218 | /* Reset the timer to avoid issues after the RAM initialization */ |
sahilmgandhi | 18:6a4db94011d3 | 219 | TIM_MST_RESET_ON; |
sahilmgandhi | 18:6a4db94011d3 | 220 | TIM_MST_RESET_OFF; |
sahilmgandhi | 18:6a4db94011d3 | 221 | } |
sahilmgandhi | 18:6a4db94011d3 | 222 | |
sahilmgandhi | 18:6a4db94011d3 | 223 | /** |
sahilmgandhi | 18:6a4db94011d3 | 224 | * @brief Update SystemCoreClock according to Clock Register Values |
sahilmgandhi | 18:6a4db94011d3 | 225 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
sahilmgandhi | 18:6a4db94011d3 | 226 | * be used by the user application to setup the SysTick timer or configure |
sahilmgandhi | 18:6a4db94011d3 | 227 | * other parameters. |
sahilmgandhi | 18:6a4db94011d3 | 228 | * |
sahilmgandhi | 18:6a4db94011d3 | 229 | * @note Each time the core clock (HCLK) changes, this function must be called |
sahilmgandhi | 18:6a4db94011d3 | 230 | * to update SystemCoreClock variable value. Otherwise, any configuration |
sahilmgandhi | 18:6a4db94011d3 | 231 | * based on this variable will be incorrect. |
sahilmgandhi | 18:6a4db94011d3 | 232 | * |
sahilmgandhi | 18:6a4db94011d3 | 233 | * @note - The system frequency computed by this function is not the real |
sahilmgandhi | 18:6a4db94011d3 | 234 | * frequency in the chip. It is calculated based on the predefined |
sahilmgandhi | 18:6a4db94011d3 | 235 | * constant and the selected clock source: |
sahilmgandhi | 18:6a4db94011d3 | 236 | * |
sahilmgandhi | 18:6a4db94011d3 | 237 | * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI |
sahilmgandhi | 18:6a4db94011d3 | 238 | * value as defined by the MSI range. |
sahilmgandhi | 18:6a4db94011d3 | 239 | * |
sahilmgandhi | 18:6a4db94011d3 | 240 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
sahilmgandhi | 18:6a4db94011d3 | 241 | * |
sahilmgandhi | 18:6a4db94011d3 | 242 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
sahilmgandhi | 18:6a4db94011d3 | 243 | * |
sahilmgandhi | 18:6a4db94011d3 | 244 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
sahilmgandhi | 18:6a4db94011d3 | 245 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
sahilmgandhi | 18:6a4db94011d3 | 246 | * |
sahilmgandhi | 18:6a4db94011d3 | 247 | * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value |
sahilmgandhi | 18:6a4db94011d3 | 248 | * 16 MHz) but the real value may vary depending on the variations |
sahilmgandhi | 18:6a4db94011d3 | 249 | * in voltage and temperature. |
sahilmgandhi | 18:6a4db94011d3 | 250 | * |
sahilmgandhi | 18:6a4db94011d3 | 251 | * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value |
sahilmgandhi | 18:6a4db94011d3 | 252 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
sahilmgandhi | 18:6a4db94011d3 | 253 | * frequency of the crystal used. Otherwise, this function may |
sahilmgandhi | 18:6a4db94011d3 | 254 | * have wrong result. |
sahilmgandhi | 18:6a4db94011d3 | 255 | * |
sahilmgandhi | 18:6a4db94011d3 | 256 | * - The result of this function could be not correct when using fractional |
sahilmgandhi | 18:6a4db94011d3 | 257 | * value for HSE crystal. |
sahilmgandhi | 18:6a4db94011d3 | 258 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 259 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 260 | */ |
sahilmgandhi | 18:6a4db94011d3 | 261 | void SystemCoreClockUpdate (void) |
sahilmgandhi | 18:6a4db94011d3 | 262 | { |
sahilmgandhi | 18:6a4db94011d3 | 263 | uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 264 | |
sahilmgandhi | 18:6a4db94011d3 | 265 | /* Get SYSCLK source -------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 266 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
sahilmgandhi | 18:6a4db94011d3 | 267 | |
sahilmgandhi | 18:6a4db94011d3 | 268 | switch (tmp) |
sahilmgandhi | 18:6a4db94011d3 | 269 | { |
sahilmgandhi | 18:6a4db94011d3 | 270 | case 0x00U: /* MSI used as system clock */ |
sahilmgandhi | 18:6a4db94011d3 | 271 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; |
sahilmgandhi | 18:6a4db94011d3 | 272 | SystemCoreClock = (32768U * (1U << (msirange + 1U))); |
sahilmgandhi | 18:6a4db94011d3 | 273 | break; |
sahilmgandhi | 18:6a4db94011d3 | 274 | case 0x04U: /* HSI used as system clock */ |
sahilmgandhi | 18:6a4db94011d3 | 275 | SystemCoreClock = HSI_VALUE; |
sahilmgandhi | 18:6a4db94011d3 | 276 | break; |
sahilmgandhi | 18:6a4db94011d3 | 277 | case 0x08U: /* HSE used as system clock */ |
sahilmgandhi | 18:6a4db94011d3 | 278 | SystemCoreClock = HSE_VALUE; |
sahilmgandhi | 18:6a4db94011d3 | 279 | break; |
sahilmgandhi | 18:6a4db94011d3 | 280 | case 0x0CU: /* PLL used as system clock */ |
sahilmgandhi | 18:6a4db94011d3 | 281 | /* Get PLL clock source and multiplication factor ----------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 282 | pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
sahilmgandhi | 18:6a4db94011d3 | 283 | plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
sahilmgandhi | 18:6a4db94011d3 | 284 | pllmul = PLLMulTable[(pllmul >> 18U)]; |
sahilmgandhi | 18:6a4db94011d3 | 285 | plldiv = (plldiv >> 22U) + 1U; |
sahilmgandhi | 18:6a4db94011d3 | 286 | |
sahilmgandhi | 18:6a4db94011d3 | 287 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
sahilmgandhi | 18:6a4db94011d3 | 288 | |
sahilmgandhi | 18:6a4db94011d3 | 289 | if (pllsource == 0x00U) |
sahilmgandhi | 18:6a4db94011d3 | 290 | { |
sahilmgandhi | 18:6a4db94011d3 | 291 | /* HSI oscillator clock selected as PLL clock entry */ |
sahilmgandhi | 18:6a4db94011d3 | 292 | SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); |
sahilmgandhi | 18:6a4db94011d3 | 293 | } |
sahilmgandhi | 18:6a4db94011d3 | 294 | else |
sahilmgandhi | 18:6a4db94011d3 | 295 | { |
sahilmgandhi | 18:6a4db94011d3 | 296 | /* HSE selected as PLL clock entry */ |
sahilmgandhi | 18:6a4db94011d3 | 297 | SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); |
sahilmgandhi | 18:6a4db94011d3 | 298 | } |
sahilmgandhi | 18:6a4db94011d3 | 299 | break; |
sahilmgandhi | 18:6a4db94011d3 | 300 | default: /* MSI used as system clock */ |
sahilmgandhi | 18:6a4db94011d3 | 301 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; |
sahilmgandhi | 18:6a4db94011d3 | 302 | SystemCoreClock = (32768U * (1U << (msirange + 1U))); |
sahilmgandhi | 18:6a4db94011d3 | 303 | break; |
sahilmgandhi | 18:6a4db94011d3 | 304 | } |
sahilmgandhi | 18:6a4db94011d3 | 305 | /* Compute HCLK clock frequency --------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 306 | /* Get HCLK prescaler */ |
sahilmgandhi | 18:6a4db94011d3 | 307 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; |
sahilmgandhi | 18:6a4db94011d3 | 308 | /* HCLK clock frequency */ |
sahilmgandhi | 18:6a4db94011d3 | 309 | SystemCoreClock >>= tmp; |
sahilmgandhi | 18:6a4db94011d3 | 310 | } |
sahilmgandhi | 18:6a4db94011d3 | 311 | |
sahilmgandhi | 18:6a4db94011d3 | 312 | /** |
sahilmgandhi | 18:6a4db94011d3 | 313 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
sahilmgandhi | 18:6a4db94011d3 | 314 | * AHB/APBx prescalers and Flash settings |
sahilmgandhi | 18:6a4db94011d3 | 315 | * @note This function should be called only once the RCC clock configuration |
sahilmgandhi | 18:6a4db94011d3 | 316 | * is reset to the default reset state (done in SystemInit() function). |
sahilmgandhi | 18:6a4db94011d3 | 317 | * @param None |
sahilmgandhi | 18:6a4db94011d3 | 318 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 319 | */ |
sahilmgandhi | 18:6a4db94011d3 | 320 | void SetSysClock(void) |
sahilmgandhi | 18:6a4db94011d3 | 321 | { |
sahilmgandhi | 18:6a4db94011d3 | 322 | /* 1- Try to start with HSE and external clock */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | #if USE_PLL_HSE_EXTC != 0 |
sahilmgandhi | 18:6a4db94011d3 | 324 | if (SetSysClock_PLL_HSE(1) == 0) |
sahilmgandhi | 18:6a4db94011d3 | 325 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 326 | { |
sahilmgandhi | 18:6a4db94011d3 | 327 | /* 2- If fail try to start with HSE and external xtal */ |
sahilmgandhi | 18:6a4db94011d3 | 328 | #if USE_PLL_HSE_XTAL != 0 |
sahilmgandhi | 18:6a4db94011d3 | 329 | if (SetSysClock_PLL_HSE(0) == 0) |
sahilmgandhi | 18:6a4db94011d3 | 330 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 331 | { |
sahilmgandhi | 18:6a4db94011d3 | 332 | /* 3- If fail start with HSI clock */ |
sahilmgandhi | 18:6a4db94011d3 | 333 | if (SetSysClock_PLL_HSI() == 0) |
sahilmgandhi | 18:6a4db94011d3 | 334 | { |
sahilmgandhi | 18:6a4db94011d3 | 335 | while(1) |
sahilmgandhi | 18:6a4db94011d3 | 336 | { |
sahilmgandhi | 18:6a4db94011d3 | 337 | // [TODO] Put something here to tell the user that a problem occured... |
sahilmgandhi | 18:6a4db94011d3 | 338 | } |
sahilmgandhi | 18:6a4db94011d3 | 339 | } |
sahilmgandhi | 18:6a4db94011d3 | 340 | } |
sahilmgandhi | 18:6a4db94011d3 | 341 | } |
sahilmgandhi | 18:6a4db94011d3 | 342 | |
sahilmgandhi | 18:6a4db94011d3 | 343 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
sahilmgandhi | 18:6a4db94011d3 | 344 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); |
sahilmgandhi | 18:6a4db94011d3 | 345 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); |
sahilmgandhi | 18:6a4db94011d3 | 346 | } |
sahilmgandhi | 18:6a4db94011d3 | 347 | |
sahilmgandhi | 18:6a4db94011d3 | 348 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
sahilmgandhi | 18:6a4db94011d3 | 349 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 350 | /* PLL (clocked by HSE) used as System clock source */ |
sahilmgandhi | 18:6a4db94011d3 | 351 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 352 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
sahilmgandhi | 18:6a4db94011d3 | 353 | { |
sahilmgandhi | 18:6a4db94011d3 | 354 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
sahilmgandhi | 18:6a4db94011d3 | 355 | RCC_OscInitTypeDef RCC_OscInitStruct; |
sahilmgandhi | 18:6a4db94011d3 | 356 | |
sahilmgandhi | 18:6a4db94011d3 | 357 | /* Used to gain time after DeepSleep in case HSI is used */ |
sahilmgandhi | 18:6a4db94011d3 | 358 | if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
sahilmgandhi | 18:6a4db94011d3 | 359 | { |
sahilmgandhi | 18:6a4db94011d3 | 360 | return 0; |
sahilmgandhi | 18:6a4db94011d3 | 361 | } |
sahilmgandhi | 18:6a4db94011d3 | 362 | |
sahilmgandhi | 18:6a4db94011d3 | 363 | /* The voltage scaling allows optimizing the power consumption when the device is |
sahilmgandhi | 18:6a4db94011d3 | 364 | clocked below the maximum system frequency, to update the voltage scaling value |
sahilmgandhi | 18:6a4db94011d3 | 365 | regarding system frequency refer to product datasheet. */ |
sahilmgandhi | 18:6a4db94011d3 | 366 | __PWR_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 367 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
sahilmgandhi | 18:6a4db94011d3 | 368 | |
sahilmgandhi | 18:6a4db94011d3 | 369 | /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ |
sahilmgandhi | 18:6a4db94011d3 | 370 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; |
sahilmgandhi | 18:6a4db94011d3 | 371 | if (bypass == 0) |
sahilmgandhi | 18:6a4db94011d3 | 372 | { |
sahilmgandhi | 18:6a4db94011d3 | 373 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
sahilmgandhi | 18:6a4db94011d3 | 374 | } |
sahilmgandhi | 18:6a4db94011d3 | 375 | else |
sahilmgandhi | 18:6a4db94011d3 | 376 | { |
sahilmgandhi | 18:6a4db94011d3 | 377 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
sahilmgandhi | 18:6a4db94011d3 | 378 | } |
sahilmgandhi | 18:6a4db94011d3 | 379 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
sahilmgandhi | 18:6a4db94011d3 | 380 | #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ |
sahilmgandhi | 18:6a4db94011d3 | 381 | !defined (STM32L011xx) && !defined (STM32L021xx) |
sahilmgandhi | 18:6a4db94011d3 | 382 | RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ |
sahilmgandhi | 18:6a4db94011d3 | 383 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 384 | // PLLCLK = (8 MHz * 8)/2 = 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 385 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
sahilmgandhi | 18:6a4db94011d3 | 386 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
sahilmgandhi | 18:6a4db94011d3 | 387 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8; |
sahilmgandhi | 18:6a4db94011d3 | 388 | RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; |
sahilmgandhi | 18:6a4db94011d3 | 389 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
sahilmgandhi | 18:6a4db94011d3 | 390 | { |
sahilmgandhi | 18:6a4db94011d3 | 391 | return 0; // FAIL |
sahilmgandhi | 18:6a4db94011d3 | 392 | } |
sahilmgandhi | 18:6a4db94011d3 | 393 | |
sahilmgandhi | 18:6a4db94011d3 | 394 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
sahilmgandhi | 18:6a4db94011d3 | 395 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
sahilmgandhi | 18:6a4db94011d3 | 396 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 397 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 398 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 399 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 400 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
sahilmgandhi | 18:6a4db94011d3 | 401 | { |
sahilmgandhi | 18:6a4db94011d3 | 402 | return 0; // FAIL |
sahilmgandhi | 18:6a4db94011d3 | 403 | } |
sahilmgandhi | 18:6a4db94011d3 | 404 | |
sahilmgandhi | 18:6a4db94011d3 | 405 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
sahilmgandhi | 18:6a4db94011d3 | 406 | //if (bypass == 0) |
sahilmgandhi | 18:6a4db94011d3 | 407 | // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz |
sahilmgandhi | 18:6a4db94011d3 | 408 | //else |
sahilmgandhi | 18:6a4db94011d3 | 409 | // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
sahilmgandhi | 18:6a4db94011d3 | 410 | |
sahilmgandhi | 18:6a4db94011d3 | 411 | return 1; // OK |
sahilmgandhi | 18:6a4db94011d3 | 412 | } |
sahilmgandhi | 18:6a4db94011d3 | 413 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 414 | |
sahilmgandhi | 18:6a4db94011d3 | 415 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 416 | /* PLL (clocked by HSI) used as System clock source */ |
sahilmgandhi | 18:6a4db94011d3 | 417 | /******************************************************************************/ |
sahilmgandhi | 18:6a4db94011d3 | 418 | uint8_t SetSysClock_PLL_HSI(void) |
sahilmgandhi | 18:6a4db94011d3 | 419 | { |
sahilmgandhi | 18:6a4db94011d3 | 420 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
sahilmgandhi | 18:6a4db94011d3 | 421 | RCC_OscInitTypeDef RCC_OscInitStruct; |
sahilmgandhi | 18:6a4db94011d3 | 422 | |
sahilmgandhi | 18:6a4db94011d3 | 423 | /* The voltage scaling allows optimizing the power consumption when the device is |
sahilmgandhi | 18:6a4db94011d3 | 424 | clocked below the maximum system frequency, to update the voltage scaling value |
sahilmgandhi | 18:6a4db94011d3 | 425 | regarding system frequency refer to product datasheet. */ |
sahilmgandhi | 18:6a4db94011d3 | 426 | __PWR_CLK_ENABLE(); |
sahilmgandhi | 18:6a4db94011d3 | 427 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
sahilmgandhi | 18:6a4db94011d3 | 428 | |
sahilmgandhi | 18:6a4db94011d3 | 429 | /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */ |
sahilmgandhi | 18:6a4db94011d3 | 430 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; |
sahilmgandhi | 18:6a4db94011d3 | 431 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
sahilmgandhi | 18:6a4db94011d3 | 432 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
sahilmgandhi | 18:6a4db94011d3 | 433 | #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ |
sahilmgandhi | 18:6a4db94011d3 | 434 | !defined (STM32L011xx) && !defined (STM32L021xx) |
sahilmgandhi | 18:6a4db94011d3 | 435 | RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ |
sahilmgandhi | 18:6a4db94011d3 | 436 | #endif |
sahilmgandhi | 18:6a4db94011d3 | 437 | // PLLCLK = (16 MHz * 4)/2 = 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 438 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
sahilmgandhi | 18:6a4db94011d3 | 439 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
sahilmgandhi | 18:6a4db94011d3 | 440 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4; |
sahilmgandhi | 18:6a4db94011d3 | 441 | RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; |
sahilmgandhi | 18:6a4db94011d3 | 442 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
sahilmgandhi | 18:6a4db94011d3 | 443 | { |
sahilmgandhi | 18:6a4db94011d3 | 444 | return 0; // FAIL |
sahilmgandhi | 18:6a4db94011d3 | 445 | } |
sahilmgandhi | 18:6a4db94011d3 | 446 | |
sahilmgandhi | 18:6a4db94011d3 | 447 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
sahilmgandhi | 18:6a4db94011d3 | 448 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
sahilmgandhi | 18:6a4db94011d3 | 449 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 450 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 451 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 452 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
sahilmgandhi | 18:6a4db94011d3 | 453 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
sahilmgandhi | 18:6a4db94011d3 | 454 | { |
sahilmgandhi | 18:6a4db94011d3 | 455 | return 0; // FAIL |
sahilmgandhi | 18:6a4db94011d3 | 456 | } |
sahilmgandhi | 18:6a4db94011d3 | 457 | |
sahilmgandhi | 18:6a4db94011d3 | 458 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
sahilmgandhi | 18:6a4db94011d3 | 459 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
sahilmgandhi | 18:6a4db94011d3 | 460 | |
sahilmgandhi | 18:6a4db94011d3 | 461 | return 1; // OK |
sahilmgandhi | 18:6a4db94011d3 | 462 | } |
sahilmgandhi | 18:6a4db94011d3 | 463 | |
sahilmgandhi | 18:6a4db94011d3 | 464 | /** |
sahilmgandhi | 18:6a4db94011d3 | 465 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 466 | */ |
sahilmgandhi | 18:6a4db94011d3 | 467 | |
sahilmgandhi | 18:6a4db94011d3 | 468 | /** |
sahilmgandhi | 18:6a4db94011d3 | 469 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 470 | */ |
sahilmgandhi | 18:6a4db94011d3 | 471 | |
sahilmgandhi | 18:6a4db94011d3 | 472 | /** |
sahilmgandhi | 18:6a4db94011d3 | 473 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 474 | */ |
sahilmgandhi | 18:6a4db94011d3 | 475 | |
sahilmgandhi | 18:6a4db94011d3 | 476 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |