MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_ll_usb.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief USB Low Layer HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 10 * functionalities of the USB Peripheral Controller:
sahilmgandhi 18:6a4db94011d3 11 * + Initialization/de-initialization functions
sahilmgandhi 18:6a4db94011d3 12 * + I/O operation functions
sahilmgandhi 18:6a4db94011d3 13 * + Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 14 * + Peripheral State functions
sahilmgandhi 18:6a4db94011d3 15 *
sahilmgandhi 18:6a4db94011d3 16 @verbatim
sahilmgandhi 18:6a4db94011d3 17 ==============================================================================
sahilmgandhi 18:6a4db94011d3 18 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 19 ==============================================================================
sahilmgandhi 18:6a4db94011d3 20 [..]
sahilmgandhi 18:6a4db94011d3 21 (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 @endverbatim
sahilmgandhi 18:6a4db94011d3 28 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 29 * @attention
sahilmgandhi 18:6a4db94011d3 30 *
sahilmgandhi 18:6a4db94011d3 31 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 32 *
sahilmgandhi 18:6a4db94011d3 33 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 34 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 35 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 36 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 37 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 38 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 39 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 40 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 41 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 42 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 43 *
sahilmgandhi 18:6a4db94011d3 44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 45 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 47 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 50 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 51 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 54 *
sahilmgandhi 18:6a4db94011d3 55 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 56 */
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 59 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 /** @addtogroup STM32F4xx_LL_USB_DRIVER
sahilmgandhi 18:6a4db94011d3 62 * @{
sahilmgandhi 18:6a4db94011d3 63 */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 #if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED)
sahilmgandhi 18:6a4db94011d3 66 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
sahilmgandhi 18:6a4db94011d3 67 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
sahilmgandhi 18:6a4db94011d3 68 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
sahilmgandhi 18:6a4db94011d3 69 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
sahilmgandhi 18:6a4db94011d3 70 defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 71 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 72 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 73 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 74 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 75 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 76 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 77 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
sahilmgandhi 18:6a4db94011d3 82 * @{
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /** @defgroup LL_USB_Group1 Initialization/de-initialization functions
sahilmgandhi 18:6a4db94011d3 86 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 87 *
sahilmgandhi 18:6a4db94011d3 88 @verbatim
sahilmgandhi 18:6a4db94011d3 89 ===============================================================================
sahilmgandhi 18:6a4db94011d3 90 ##### Initialization/de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 91 ===============================================================================
sahilmgandhi 18:6a4db94011d3 92 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 @endverbatim
sahilmgandhi 18:6a4db94011d3 95 * @{
sahilmgandhi 18:6a4db94011d3 96 */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /**
sahilmgandhi 18:6a4db94011d3 99 * @brief Initializes the USB Core
sahilmgandhi 18:6a4db94011d3 100 * @param USBx: USB Instance
sahilmgandhi 18:6a4db94011d3 101 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 102 * the configuration information for the specified USBx peripheral.
sahilmgandhi 18:6a4db94011d3 103 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 104 */
sahilmgandhi 18:6a4db94011d3 105 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
sahilmgandhi 18:6a4db94011d3 106 {
sahilmgandhi 18:6a4db94011d3 107 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
sahilmgandhi 18:6a4db94011d3 108 {
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 /* Init The ULPI Interface */
sahilmgandhi 18:6a4db94011d3 113 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /* Select vbus source */
sahilmgandhi 18:6a4db94011d3 116 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
sahilmgandhi 18:6a4db94011d3 117 if(cfg.use_external_vbus == 1U)
sahilmgandhi 18:6a4db94011d3 118 {
sahilmgandhi 18:6a4db94011d3 119 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
sahilmgandhi 18:6a4db94011d3 120 }
sahilmgandhi 18:6a4db94011d3 121 /* Reset after a PHY select */
sahilmgandhi 18:6a4db94011d3 122 USB_CoreReset(USBx);
sahilmgandhi 18:6a4db94011d3 123 }
sahilmgandhi 18:6a4db94011d3 124 else /* FS interface (embedded Phy) */
sahilmgandhi 18:6a4db94011d3 125 {
sahilmgandhi 18:6a4db94011d3 126 /* Select FS Embedded PHY */
sahilmgandhi 18:6a4db94011d3 127 USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 /* Reset after a PHY select and set Host mode */
sahilmgandhi 18:6a4db94011d3 130 USB_CoreReset(USBx);
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /* Deactivate the power down*/
sahilmgandhi 18:6a4db94011d3 133 USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
sahilmgandhi 18:6a4db94011d3 134 }
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 if(cfg.dma_enable == ENABLE)
sahilmgandhi 18:6a4db94011d3 137 {
sahilmgandhi 18:6a4db94011d3 138 USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
sahilmgandhi 18:6a4db94011d3 139 }
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 142 }
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /**
sahilmgandhi 18:6a4db94011d3 145 * @brief USB_EnableGlobalInt
sahilmgandhi 18:6a4db94011d3 146 * Enables the controller's Global Int in the AHB Config reg
sahilmgandhi 18:6a4db94011d3 147 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 148 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 151 {
sahilmgandhi 18:6a4db94011d3 152 USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
sahilmgandhi 18:6a4db94011d3 153 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 /**
sahilmgandhi 18:6a4db94011d3 158 * @brief USB_DisableGlobalInt
sahilmgandhi 18:6a4db94011d3 159 * Disable the controller's Global Int in the AHB Config reg
sahilmgandhi 18:6a4db94011d3 160 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 161 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 162 */
sahilmgandhi 18:6a4db94011d3 163 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 164 {
sahilmgandhi 18:6a4db94011d3 165 USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
sahilmgandhi 18:6a4db94011d3 166 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 167 }
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 /**
sahilmgandhi 18:6a4db94011d3 170 * @brief USB_SetCurrentMode : Set functional mode
sahilmgandhi 18:6a4db94011d3 171 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 172 * @param mode : current core mode
sahilmgandhi 18:6a4db94011d3 173 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 174 * @arg USB_OTG_DEVICE_MODE: Peripheral mode
sahilmgandhi 18:6a4db94011d3 175 * @arg USB_OTG_HOST_MODE: Host mode
sahilmgandhi 18:6a4db94011d3 176 * @arg USB_OTG_DRD_MODE: Dual Role Device mode
sahilmgandhi 18:6a4db94011d3 177 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 178 */
sahilmgandhi 18:6a4db94011d3 179 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
sahilmgandhi 18:6a4db94011d3 180 {
sahilmgandhi 18:6a4db94011d3 181 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 if ( mode == USB_OTG_HOST_MODE)
sahilmgandhi 18:6a4db94011d3 184 {
sahilmgandhi 18:6a4db94011d3 185 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
sahilmgandhi 18:6a4db94011d3 186 }
sahilmgandhi 18:6a4db94011d3 187 else if ( mode == USB_OTG_DEVICE_MODE)
sahilmgandhi 18:6a4db94011d3 188 {
sahilmgandhi 18:6a4db94011d3 189 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
sahilmgandhi 18:6a4db94011d3 190 }
sahilmgandhi 18:6a4db94011d3 191 HAL_Delay(50U);
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 194 }
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 /**
sahilmgandhi 18:6a4db94011d3 197 * @brief USB_DevInit : Initializes the USB_OTG controller registers
sahilmgandhi 18:6a4db94011d3 198 * for device mode
sahilmgandhi 18:6a4db94011d3 199 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 200 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 201 * the configuration information for the specified USBx peripheral.
sahilmgandhi 18:6a4db94011d3 202 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 203 */
sahilmgandhi 18:6a4db94011d3 204 HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
sahilmgandhi 18:6a4db94011d3 205 {
sahilmgandhi 18:6a4db94011d3 206 uint32_t i = 0U;
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 /*Activate VBUS Sensing B */
sahilmgandhi 18:6a4db94011d3 209 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
sahilmgandhi 18:6a4db94011d3 210 defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 211 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 if (cfg.vbus_sensing_enable == 0U)
sahilmgandhi 18:6a4db94011d3 214 {
sahilmgandhi 18:6a4db94011d3 215 /* Deactivate VBUS Sensing B */
sahilmgandhi 18:6a4db94011d3 216 USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /* B-peripheral session valid override enable*/
sahilmgandhi 18:6a4db94011d3 219 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
sahilmgandhi 18:6a4db94011d3 220 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
sahilmgandhi 18:6a4db94011d3 221 }
sahilmgandhi 18:6a4db94011d3 222 #else
sahilmgandhi 18:6a4db94011d3 223 USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 if (cfg.vbus_sensing_enable == 0U)
sahilmgandhi 18:6a4db94011d3 226 {
sahilmgandhi 18:6a4db94011d3 227 USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
sahilmgandhi 18:6a4db94011d3 228 }
sahilmgandhi 18:6a4db94011d3 229 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 /* Restart the Phy Clock */
sahilmgandhi 18:6a4db94011d3 232 USBx_PCGCCTL = 0U;
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 /* Device mode configuration */
sahilmgandhi 18:6a4db94011d3 235 USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 if(cfg.phy_itface == USB_OTG_ULPI_PHY)
sahilmgandhi 18:6a4db94011d3 238 {
sahilmgandhi 18:6a4db94011d3 239 if(cfg.speed == USB_OTG_SPEED_HIGH)
sahilmgandhi 18:6a4db94011d3 240 {
sahilmgandhi 18:6a4db94011d3 241 /* Set High speed phy */
sahilmgandhi 18:6a4db94011d3 242 USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
sahilmgandhi 18:6a4db94011d3 243 }
sahilmgandhi 18:6a4db94011d3 244 else
sahilmgandhi 18:6a4db94011d3 245 {
sahilmgandhi 18:6a4db94011d3 246 /* set High speed phy in Full speed mode */
sahilmgandhi 18:6a4db94011d3 247 USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
sahilmgandhi 18:6a4db94011d3 248 }
sahilmgandhi 18:6a4db94011d3 249 }
sahilmgandhi 18:6a4db94011d3 250 else
sahilmgandhi 18:6a4db94011d3 251 {
sahilmgandhi 18:6a4db94011d3 252 /* Set Full speed phy */
sahilmgandhi 18:6a4db94011d3 253 USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
sahilmgandhi 18:6a4db94011d3 254 }
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 /* Flush the FIFOs */
sahilmgandhi 18:6a4db94011d3 257 USB_FlushTxFifo(USBx , 0x10U); /* all Tx FIFOs */
sahilmgandhi 18:6a4db94011d3 258 USB_FlushRxFifo(USBx);
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 /* Clear all pending Device Interrupts */
sahilmgandhi 18:6a4db94011d3 261 USBx_DEVICE->DIEPMSK = 0U;
sahilmgandhi 18:6a4db94011d3 262 USBx_DEVICE->DOEPMSK = 0U;
sahilmgandhi 18:6a4db94011d3 263 USBx_DEVICE->DAINT = 0xFFFFFFFFU;
sahilmgandhi 18:6a4db94011d3 264 USBx_DEVICE->DAINTMSK = 0U;
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 for (i = 0U; i < cfg.dev_endpoints; i++)
sahilmgandhi 18:6a4db94011d3 267 {
sahilmgandhi 18:6a4db94011d3 268 if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
sahilmgandhi 18:6a4db94011d3 269 {
sahilmgandhi 18:6a4db94011d3 270 USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
sahilmgandhi 18:6a4db94011d3 271 }
sahilmgandhi 18:6a4db94011d3 272 else
sahilmgandhi 18:6a4db94011d3 273 {
sahilmgandhi 18:6a4db94011d3 274 USBx_INEP(i)->DIEPCTL = 0U;
sahilmgandhi 18:6a4db94011d3 275 }
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 USBx_INEP(i)->DIEPTSIZ = 0U;
sahilmgandhi 18:6a4db94011d3 278 USBx_INEP(i)->DIEPINT = 0xFFU;
sahilmgandhi 18:6a4db94011d3 279 }
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 for (i = 0U; i < cfg.dev_endpoints; i++)
sahilmgandhi 18:6a4db94011d3 282 {
sahilmgandhi 18:6a4db94011d3 283 if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
sahilmgandhi 18:6a4db94011d3 284 {
sahilmgandhi 18:6a4db94011d3 285 USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287 else
sahilmgandhi 18:6a4db94011d3 288 {
sahilmgandhi 18:6a4db94011d3 289 USBx_OUTEP(i)->DOEPCTL = 0U;
sahilmgandhi 18:6a4db94011d3 290 }
sahilmgandhi 18:6a4db94011d3 291
sahilmgandhi 18:6a4db94011d3 292 USBx_OUTEP(i)->DOEPTSIZ = 0U;
sahilmgandhi 18:6a4db94011d3 293 USBx_OUTEP(i)->DOEPINT = 0xFFU;
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 if (cfg.dma_enable == 1U)
sahilmgandhi 18:6a4db94011d3 299 {
sahilmgandhi 18:6a4db94011d3 300 /*Set threshold parameters */
sahilmgandhi 18:6a4db94011d3 301 USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
sahilmgandhi 18:6a4db94011d3 302 USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 i= USBx_DEVICE->DTHRCTL;
sahilmgandhi 18:6a4db94011d3 305 }
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Disable all interrupts. */
sahilmgandhi 18:6a4db94011d3 308 USBx->GINTMSK = 0U;
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /* Clear any pending interrupts */
sahilmgandhi 18:6a4db94011d3 311 USBx->GINTSTS = 0xBFFFFFFFU;
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 /* Enable the common interrupts */
sahilmgandhi 18:6a4db94011d3 314 if (cfg.dma_enable == DISABLE)
sahilmgandhi 18:6a4db94011d3 315 {
sahilmgandhi 18:6a4db94011d3 316 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
sahilmgandhi 18:6a4db94011d3 317 }
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 /* Enable interrupts matching to the Device mode ONLY */
sahilmgandhi 18:6a4db94011d3 320 USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
sahilmgandhi 18:6a4db94011d3 321 USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
sahilmgandhi 18:6a4db94011d3 322 USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
sahilmgandhi 18:6a4db94011d3 323 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 if(cfg.Sof_enable)
sahilmgandhi 18:6a4db94011d3 326 {
sahilmgandhi 18:6a4db94011d3 327 USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
sahilmgandhi 18:6a4db94011d3 328 }
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 if (cfg.vbus_sensing_enable == ENABLE)
sahilmgandhi 18:6a4db94011d3 331 {
sahilmgandhi 18:6a4db94011d3 332 USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 336 }
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /**
sahilmgandhi 18:6a4db94011d3 340 * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
sahilmgandhi 18:6a4db94011d3 341 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 342 * @param num : FIFO number
sahilmgandhi 18:6a4db94011d3 343 * This parameter can be a value from 1 to 15
sahilmgandhi 18:6a4db94011d3 344 15 means Flush all Tx FIFOs
sahilmgandhi 18:6a4db94011d3 345 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 346 */
sahilmgandhi 18:6a4db94011d3 347 HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
sahilmgandhi 18:6a4db94011d3 348 {
sahilmgandhi 18:6a4db94011d3 349 uint32_t count = 0U;
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 do
sahilmgandhi 18:6a4db94011d3 354 {
sahilmgandhi 18:6a4db94011d3 355 if (++count > 200000U)
sahilmgandhi 18:6a4db94011d3 356 {
sahilmgandhi 18:6a4db94011d3 357 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 358 }
sahilmgandhi 18:6a4db94011d3 359 }
sahilmgandhi 18:6a4db94011d3 360 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 363 }
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /**
sahilmgandhi 18:6a4db94011d3 367 * @brief USB_FlushRxFifo : Flush Rx FIFO
sahilmgandhi 18:6a4db94011d3 368 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 369 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 370 */
sahilmgandhi 18:6a4db94011d3 371 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 372 {
sahilmgandhi 18:6a4db94011d3 373 uint32_t count = 0U;
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 do
sahilmgandhi 18:6a4db94011d3 378 {
sahilmgandhi 18:6a4db94011d3 379 if (++count > 200000U)
sahilmgandhi 18:6a4db94011d3 380 {
sahilmgandhi 18:6a4db94011d3 381 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 382 }
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 387 }
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 /**
sahilmgandhi 18:6a4db94011d3 390 * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
sahilmgandhi 18:6a4db94011d3 391 * depending the PHY type and the enumeration speed of the device.
sahilmgandhi 18:6a4db94011d3 392 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 393 * @param speed : device speed
sahilmgandhi 18:6a4db94011d3 394 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 395 * @arg USB_OTG_SPEED_HIGH: High speed mode
sahilmgandhi 18:6a4db94011d3 396 * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
sahilmgandhi 18:6a4db94011d3 397 * @arg USB_OTG_SPEED_FULL: Full speed mode
sahilmgandhi 18:6a4db94011d3 398 * @arg USB_OTG_SPEED_LOW: Low speed mode
sahilmgandhi 18:6a4db94011d3 399 * @retval Hal status
sahilmgandhi 18:6a4db94011d3 400 */
sahilmgandhi 18:6a4db94011d3 401 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
sahilmgandhi 18:6a4db94011d3 402 {
sahilmgandhi 18:6a4db94011d3 403 USBx_DEVICE->DCFG |= speed;
sahilmgandhi 18:6a4db94011d3 404 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 405 }
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /**
sahilmgandhi 18:6a4db94011d3 408 * @brief USB_GetDevSpeed :Return the Dev Speed
sahilmgandhi 18:6a4db94011d3 409 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 410 * @retval speed : device speed
sahilmgandhi 18:6a4db94011d3 411 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 412 * @arg USB_OTG_SPEED_HIGH: High speed mode
sahilmgandhi 18:6a4db94011d3 413 * @arg USB_OTG_SPEED_FULL: Full speed mode
sahilmgandhi 18:6a4db94011d3 414 * @arg USB_OTG_SPEED_LOW: Low speed mode
sahilmgandhi 18:6a4db94011d3 415 */
sahilmgandhi 18:6a4db94011d3 416 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 417 {
sahilmgandhi 18:6a4db94011d3 418 uint8_t speed = 0U;
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
sahilmgandhi 18:6a4db94011d3 421 {
sahilmgandhi 18:6a4db94011d3 422 speed = USB_OTG_SPEED_HIGH;
sahilmgandhi 18:6a4db94011d3 423 }
sahilmgandhi 18:6a4db94011d3 424 else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
sahilmgandhi 18:6a4db94011d3 425 ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
sahilmgandhi 18:6a4db94011d3 426 {
sahilmgandhi 18:6a4db94011d3 427 speed = USB_OTG_SPEED_FULL;
sahilmgandhi 18:6a4db94011d3 428 }
sahilmgandhi 18:6a4db94011d3 429 else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
sahilmgandhi 18:6a4db94011d3 430 {
sahilmgandhi 18:6a4db94011d3 431 speed = USB_OTG_SPEED_LOW;
sahilmgandhi 18:6a4db94011d3 432 }
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 return speed;
sahilmgandhi 18:6a4db94011d3 435 }
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /**
sahilmgandhi 18:6a4db94011d3 438 * @brief Activate and configure an endpoint
sahilmgandhi 18:6a4db94011d3 439 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 440 * @param ep: pointer to endpoint structure
sahilmgandhi 18:6a4db94011d3 441 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 442 */
sahilmgandhi 18:6a4db94011d3 443 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
sahilmgandhi 18:6a4db94011d3 444 {
sahilmgandhi 18:6a4db94011d3 445 if (ep->is_in == 1U)
sahilmgandhi 18:6a4db94011d3 446 {
sahilmgandhi 18:6a4db94011d3 447 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)));
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
sahilmgandhi 18:6a4db94011d3 450 {
sahilmgandhi 18:6a4db94011d3 451 USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
sahilmgandhi 18:6a4db94011d3 452 ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
sahilmgandhi 18:6a4db94011d3 453 }
sahilmgandhi 18:6a4db94011d3 454 }
sahilmgandhi 18:6a4db94011d3 455 else
sahilmgandhi 18:6a4db94011d3 456 {
sahilmgandhi 18:6a4db94011d3 457 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U);
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
sahilmgandhi 18:6a4db94011d3 460 {
sahilmgandhi 18:6a4db94011d3 461 USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
sahilmgandhi 18:6a4db94011d3 462 (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464 }
sahilmgandhi 18:6a4db94011d3 465 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 466 }
sahilmgandhi 18:6a4db94011d3 467 /**
sahilmgandhi 18:6a4db94011d3 468 * @brief Activate and configure a dedicated endpoint
sahilmgandhi 18:6a4db94011d3 469 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 470 * @param ep: pointer to endpoint structure
sahilmgandhi 18:6a4db94011d3 471 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 472 */
sahilmgandhi 18:6a4db94011d3 473 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
sahilmgandhi 18:6a4db94011d3 474 {
sahilmgandhi 18:6a4db94011d3 475 static __IO uint32_t debug = 0U;
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /* Read DEPCTLn register */
sahilmgandhi 18:6a4db94011d3 478 if (ep->is_in == 1U)
sahilmgandhi 18:6a4db94011d3 479 {
sahilmgandhi 18:6a4db94011d3 480 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)
sahilmgandhi 18:6a4db94011d3 481 {
sahilmgandhi 18:6a4db94011d3 482 USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
sahilmgandhi 18:6a4db94011d3 483 ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
sahilmgandhi 18:6a4db94011d3 484 }
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18U) |\
sahilmgandhi 18:6a4db94011d3 488 ((ep->num) << 22U) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num)));
sahilmgandhi 18:6a4db94011d3 491 }
sahilmgandhi 18:6a4db94011d3 492 else
sahilmgandhi 18:6a4db94011d3 493 {
sahilmgandhi 18:6a4db94011d3 494 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)
sahilmgandhi 18:6a4db94011d3 495 {
sahilmgandhi 18:6a4db94011d3 496 USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
sahilmgandhi 18:6a4db94011d3 497 ((ep->num) << 22U) | (USB_OTG_DOEPCTL_USBAEP));
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0U)*USB_OTG_EP_REG_SIZE);
sahilmgandhi 18:6a4db94011d3 500 debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
sahilmgandhi 18:6a4db94011d3 501 debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18U) |\
sahilmgandhi 18:6a4db94011d3 502 ((ep->num) << 22U) | (USB_OTG_DOEPCTL_USBAEP));
sahilmgandhi 18:6a4db94011d3 503 }
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U);
sahilmgandhi 18:6a4db94011d3 506 }
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 509 }
sahilmgandhi 18:6a4db94011d3 510 /**
sahilmgandhi 18:6a4db94011d3 511 * @brief De-activate and de-initialize an endpoint
sahilmgandhi 18:6a4db94011d3 512 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 513 * @param ep: pointer to endpoint structure
sahilmgandhi 18:6a4db94011d3 514 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 515 */
sahilmgandhi 18:6a4db94011d3 516 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
sahilmgandhi 18:6a4db94011d3 517 {
sahilmgandhi 18:6a4db94011d3 518 /* Read DEPCTLn register */
sahilmgandhi 18:6a4db94011d3 519 if (ep->is_in == 1U)
sahilmgandhi 18:6a4db94011d3 520 {
sahilmgandhi 18:6a4db94011d3 521 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
sahilmgandhi 18:6a4db94011d3 522 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
sahilmgandhi 18:6a4db94011d3 523 USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
sahilmgandhi 18:6a4db94011d3 524 }
sahilmgandhi 18:6a4db94011d3 525 else
sahilmgandhi 18:6a4db94011d3 526 {
sahilmgandhi 18:6a4db94011d3 527 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
sahilmgandhi 18:6a4db94011d3 528 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
sahilmgandhi 18:6a4db94011d3 529 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
sahilmgandhi 18:6a4db94011d3 530 }
sahilmgandhi 18:6a4db94011d3 531 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 532 }
sahilmgandhi 18:6a4db94011d3 533
sahilmgandhi 18:6a4db94011d3 534 /**
sahilmgandhi 18:6a4db94011d3 535 * @brief De-activate and de-initialize a dedicated endpoint
sahilmgandhi 18:6a4db94011d3 536 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 537 * @param ep: pointer to endpoint structure
sahilmgandhi 18:6a4db94011d3 538 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 539 */
sahilmgandhi 18:6a4db94011d3 540 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
sahilmgandhi 18:6a4db94011d3 541 {
sahilmgandhi 18:6a4db94011d3 542 /* Read DEPCTLn register */
sahilmgandhi 18:6a4db94011d3 543 if (ep->is_in == 1U)
sahilmgandhi 18:6a4db94011d3 544 {
sahilmgandhi 18:6a4db94011d3 545 USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
sahilmgandhi 18:6a4db94011d3 546 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1U << (ep->num))));
sahilmgandhi 18:6a4db94011d3 547 }
sahilmgandhi 18:6a4db94011d3 548 else
sahilmgandhi 18:6a4db94011d3 549 {
sahilmgandhi 18:6a4db94011d3 550 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
sahilmgandhi 18:6a4db94011d3 551 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1U << (ep->num)) << 16U));
sahilmgandhi 18:6a4db94011d3 552 }
sahilmgandhi 18:6a4db94011d3 553 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 554 }
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /**
sahilmgandhi 18:6a4db94011d3 557 * @brief USB_EPStartXfer : setup and starts a transfer over an EP
sahilmgandhi 18:6a4db94011d3 558 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 559 * @param ep: pointer to endpoint structure
sahilmgandhi 18:6a4db94011d3 560 * @param dma: USB dma enabled or disabled
sahilmgandhi 18:6a4db94011d3 561 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 562 * 0 : DMA feature not used
sahilmgandhi 18:6a4db94011d3 563 * 1 : DMA feature used
sahilmgandhi 18:6a4db94011d3 564 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 565 */
sahilmgandhi 18:6a4db94011d3 566 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
sahilmgandhi 18:6a4db94011d3 567 {
sahilmgandhi 18:6a4db94011d3 568 uint16_t pktcnt = 0U;
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /* IN endpoint */
sahilmgandhi 18:6a4db94011d3 571 if (ep->is_in == 1U)
sahilmgandhi 18:6a4db94011d3 572 {
sahilmgandhi 18:6a4db94011d3 573 /* Zero Length Packet? */
sahilmgandhi 18:6a4db94011d3 574 if (ep->xfer_len == 0U)
sahilmgandhi 18:6a4db94011d3 575 {
sahilmgandhi 18:6a4db94011d3 576 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
sahilmgandhi 18:6a4db94011d3 577 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
sahilmgandhi 18:6a4db94011d3 578 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580 else
sahilmgandhi 18:6a4db94011d3 581 {
sahilmgandhi 18:6a4db94011d3 582 /* Program the transfer size and packet count
sahilmgandhi 18:6a4db94011d3 583 * as follows: xfersize = N * maxpacket +
sahilmgandhi 18:6a4db94011d3 584 * short_packet pktcnt = N + (short_packet
sahilmgandhi 18:6a4db94011d3 585 * exist ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 586 */
sahilmgandhi 18:6a4db94011d3 587 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
sahilmgandhi 18:6a4db94011d3 588 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
sahilmgandhi 18:6a4db94011d3 589 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket) << 19U)) ;
sahilmgandhi 18:6a4db94011d3 590 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592 if (ep->type == EP_TYPE_ISOC)
sahilmgandhi 18:6a4db94011d3 593 {
sahilmgandhi 18:6a4db94011d3 594 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
sahilmgandhi 18:6a4db94011d3 595 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29U));
sahilmgandhi 18:6a4db94011d3 596 }
sahilmgandhi 18:6a4db94011d3 597 }
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 if (dma == 1U)
sahilmgandhi 18:6a4db94011d3 600 {
sahilmgandhi 18:6a4db94011d3 601 USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
sahilmgandhi 18:6a4db94011d3 602 }
sahilmgandhi 18:6a4db94011d3 603 else
sahilmgandhi 18:6a4db94011d3 604 {
sahilmgandhi 18:6a4db94011d3 605 if (ep->type != EP_TYPE_ISOC)
sahilmgandhi 18:6a4db94011d3 606 {
sahilmgandhi 18:6a4db94011d3 607 /* Enable the Tx FIFO Empty Interrupt for this EP */
sahilmgandhi 18:6a4db94011d3 608 if (ep->xfer_len > 0U)
sahilmgandhi 18:6a4db94011d3 609 {
sahilmgandhi 18:6a4db94011d3 610 atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << ep->num);
sahilmgandhi 18:6a4db94011d3 611 }
sahilmgandhi 18:6a4db94011d3 612 }
sahilmgandhi 18:6a4db94011d3 613 }
sahilmgandhi 18:6a4db94011d3 614
sahilmgandhi 18:6a4db94011d3 615 if (ep->type == EP_TYPE_ISOC)
sahilmgandhi 18:6a4db94011d3 616 {
sahilmgandhi 18:6a4db94011d3 617 if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U)
sahilmgandhi 18:6a4db94011d3 618 {
sahilmgandhi 18:6a4db94011d3 619 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
sahilmgandhi 18:6a4db94011d3 620 }
sahilmgandhi 18:6a4db94011d3 621 else
sahilmgandhi 18:6a4db94011d3 622 {
sahilmgandhi 18:6a4db94011d3 623 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
sahilmgandhi 18:6a4db94011d3 624 }
sahilmgandhi 18:6a4db94011d3 625 }
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 /* EP enable, IN data in FIFO */
sahilmgandhi 18:6a4db94011d3 628 USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
sahilmgandhi 18:6a4db94011d3 629
sahilmgandhi 18:6a4db94011d3 630 if (ep->type == EP_TYPE_ISOC)
sahilmgandhi 18:6a4db94011d3 631 {
sahilmgandhi 18:6a4db94011d3 632 USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
sahilmgandhi 18:6a4db94011d3 633 }
sahilmgandhi 18:6a4db94011d3 634 }
sahilmgandhi 18:6a4db94011d3 635 else /* OUT endpoint */
sahilmgandhi 18:6a4db94011d3 636 {
sahilmgandhi 18:6a4db94011d3 637 /* Program the transfer size and packet count as follows:
sahilmgandhi 18:6a4db94011d3 638 * pktcnt = N
sahilmgandhi 18:6a4db94011d3 639 * xfersize = N * maxpacket
sahilmgandhi 18:6a4db94011d3 640 */
sahilmgandhi 18:6a4db94011d3 641 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
sahilmgandhi 18:6a4db94011d3 642 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
sahilmgandhi 18:6a4db94011d3 643
sahilmgandhi 18:6a4db94011d3 644 if (ep->xfer_len == 0U)
sahilmgandhi 18:6a4db94011d3 645 {
sahilmgandhi 18:6a4db94011d3 646 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
sahilmgandhi 18:6a4db94011d3 647 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
sahilmgandhi 18:6a4db94011d3 648 }
sahilmgandhi 18:6a4db94011d3 649 else
sahilmgandhi 18:6a4db94011d3 650 {
sahilmgandhi 18:6a4db94011d3 651 pktcnt = (ep->xfer_len + ep->maxpacket -1U)/ ep->maxpacket;
sahilmgandhi 18:6a4db94011d3 652 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19U));
sahilmgandhi 18:6a4db94011d3 653 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
sahilmgandhi 18:6a4db94011d3 654 }
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 if (dma == 1U)
sahilmgandhi 18:6a4db94011d3 657 {
sahilmgandhi 18:6a4db94011d3 658 USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
sahilmgandhi 18:6a4db94011d3 659 }
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 if (ep->type == EP_TYPE_ISOC)
sahilmgandhi 18:6a4db94011d3 662 {
sahilmgandhi 18:6a4db94011d3 663 if ((USBx_DEVICE->DSTS & ( 1U << 8U )) == 0U)
sahilmgandhi 18:6a4db94011d3 664 {
sahilmgandhi 18:6a4db94011d3 665 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
sahilmgandhi 18:6a4db94011d3 666 }
sahilmgandhi 18:6a4db94011d3 667 else
sahilmgandhi 18:6a4db94011d3 668 {
sahilmgandhi 18:6a4db94011d3 669 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
sahilmgandhi 18:6a4db94011d3 670 }
sahilmgandhi 18:6a4db94011d3 671 }
sahilmgandhi 18:6a4db94011d3 672 /* EP enable */
sahilmgandhi 18:6a4db94011d3 673 USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
sahilmgandhi 18:6a4db94011d3 674 }
sahilmgandhi 18:6a4db94011d3 675 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 676 }
sahilmgandhi 18:6a4db94011d3 677
sahilmgandhi 18:6a4db94011d3 678 /**
sahilmgandhi 18:6a4db94011d3 679 * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
sahilmgandhi 18:6a4db94011d3 680 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 681 * @param ep: pointer to endpoint structure
sahilmgandhi 18:6a4db94011d3 682 * @param dma: USB dma enabled or disabled
sahilmgandhi 18:6a4db94011d3 683 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 684 * 0 : DMA feature not used
sahilmgandhi 18:6a4db94011d3 685 * 1 : DMA feature used
sahilmgandhi 18:6a4db94011d3 686 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 687 */
sahilmgandhi 18:6a4db94011d3 688 HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
sahilmgandhi 18:6a4db94011d3 689 {
sahilmgandhi 18:6a4db94011d3 690 /* IN endpoint */
sahilmgandhi 18:6a4db94011d3 691 if (ep->is_in == 1U)
sahilmgandhi 18:6a4db94011d3 692 {
sahilmgandhi 18:6a4db94011d3 693 /* Zero Length Packet? */
sahilmgandhi 18:6a4db94011d3 694 if (ep->xfer_len == 0U)
sahilmgandhi 18:6a4db94011d3 695 {
sahilmgandhi 18:6a4db94011d3 696 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
sahilmgandhi 18:6a4db94011d3 697 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
sahilmgandhi 18:6a4db94011d3 698 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
sahilmgandhi 18:6a4db94011d3 699 }
sahilmgandhi 18:6a4db94011d3 700 else
sahilmgandhi 18:6a4db94011d3 701 {
sahilmgandhi 18:6a4db94011d3 702 /* Program the transfer size and packet count
sahilmgandhi 18:6a4db94011d3 703 * as follows: xfersize = N * maxpacket +
sahilmgandhi 18:6a4db94011d3 704 * short_packet pktcnt = N + (short_packet
sahilmgandhi 18:6a4db94011d3 705 * exist ? 1 : 0)
sahilmgandhi 18:6a4db94011d3 706 */
sahilmgandhi 18:6a4db94011d3 707 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
sahilmgandhi 18:6a4db94011d3 708 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 if(ep->xfer_len > ep->maxpacket)
sahilmgandhi 18:6a4db94011d3 711 {
sahilmgandhi 18:6a4db94011d3 712 ep->xfer_len = ep->maxpacket;
sahilmgandhi 18:6a4db94011d3 713 }
sahilmgandhi 18:6a4db94011d3 714 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19U)) ;
sahilmgandhi 18:6a4db94011d3 715 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 }
sahilmgandhi 18:6a4db94011d3 718
sahilmgandhi 18:6a4db94011d3 719 if (dma == 1)
sahilmgandhi 18:6a4db94011d3 720 {
sahilmgandhi 18:6a4db94011d3 721 USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
sahilmgandhi 18:6a4db94011d3 722 }
sahilmgandhi 18:6a4db94011d3 723 else
sahilmgandhi 18:6a4db94011d3 724 {
sahilmgandhi 18:6a4db94011d3 725 /* Enable the Tx FIFO Empty Interrupt for this EP */
sahilmgandhi 18:6a4db94011d3 726 if (ep->xfer_len > 0U)
sahilmgandhi 18:6a4db94011d3 727 {
sahilmgandhi 18:6a4db94011d3 728 atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << (ep->num));
sahilmgandhi 18:6a4db94011d3 729 }
sahilmgandhi 18:6a4db94011d3 730 }
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 /* EP enable, IN data in FIFO */
sahilmgandhi 18:6a4db94011d3 733 USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
sahilmgandhi 18:6a4db94011d3 734 }
sahilmgandhi 18:6a4db94011d3 735 else /* OUT endpoint */
sahilmgandhi 18:6a4db94011d3 736 {
sahilmgandhi 18:6a4db94011d3 737 /* Program the transfer size and packet count as follows:
sahilmgandhi 18:6a4db94011d3 738 * pktcnt = N
sahilmgandhi 18:6a4db94011d3 739 * xfersize = N * maxpacket
sahilmgandhi 18:6a4db94011d3 740 */
sahilmgandhi 18:6a4db94011d3 741 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
sahilmgandhi 18:6a4db94011d3 742 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
sahilmgandhi 18:6a4db94011d3 743
sahilmgandhi 18:6a4db94011d3 744 if (ep->xfer_len > 0U)
sahilmgandhi 18:6a4db94011d3 745 {
sahilmgandhi 18:6a4db94011d3 746 ep->xfer_len = ep->maxpacket;
sahilmgandhi 18:6a4db94011d3 747 }
sahilmgandhi 18:6a4db94011d3 748
sahilmgandhi 18:6a4db94011d3 749 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U));
sahilmgandhi 18:6a4db94011d3 750 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 if (dma == 1U)
sahilmgandhi 18:6a4db94011d3 754 {
sahilmgandhi 18:6a4db94011d3 755 USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
sahilmgandhi 18:6a4db94011d3 756 }
sahilmgandhi 18:6a4db94011d3 757
sahilmgandhi 18:6a4db94011d3 758 /* EP enable */
sahilmgandhi 18:6a4db94011d3 759 USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
sahilmgandhi 18:6a4db94011d3 760 }
sahilmgandhi 18:6a4db94011d3 761 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 762 }
sahilmgandhi 18:6a4db94011d3 763
sahilmgandhi 18:6a4db94011d3 764 /**
sahilmgandhi 18:6a4db94011d3 765 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
sahilmgandhi 18:6a4db94011d3 766 * with the EP/channel
sahilmgandhi 18:6a4db94011d3 767 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 768 * @param src : pointer to source buffer
sahilmgandhi 18:6a4db94011d3 769 * @param ch_ep_num : endpoint or host channel number
sahilmgandhi 18:6a4db94011d3 770 * @param len : Number of bytes to write
sahilmgandhi 18:6a4db94011d3 771 * @param dma: USB dma enabled or disabled
sahilmgandhi 18:6a4db94011d3 772 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 773 * 0 : DMA feature not used
sahilmgandhi 18:6a4db94011d3 774 * 1 : DMA feature used
sahilmgandhi 18:6a4db94011d3 775 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 776 */
sahilmgandhi 18:6a4db94011d3 777 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
sahilmgandhi 18:6a4db94011d3 778 {
sahilmgandhi 18:6a4db94011d3 779 uint32_t count32b = 0U , i = 0U;
sahilmgandhi 18:6a4db94011d3 780
sahilmgandhi 18:6a4db94011d3 781 if (dma == 0U)
sahilmgandhi 18:6a4db94011d3 782 {
sahilmgandhi 18:6a4db94011d3 783 count32b = (len + 3U) / 4U;
sahilmgandhi 18:6a4db94011d3 784 for (i = 0U; i < count32b; i++, src += 4U)
sahilmgandhi 18:6a4db94011d3 785 {
sahilmgandhi 18:6a4db94011d3 786 USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src);
sahilmgandhi 18:6a4db94011d3 787 }
sahilmgandhi 18:6a4db94011d3 788 }
sahilmgandhi 18:6a4db94011d3 789 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 790 }
sahilmgandhi 18:6a4db94011d3 791
sahilmgandhi 18:6a4db94011d3 792 /**
sahilmgandhi 18:6a4db94011d3 793 * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
sahilmgandhi 18:6a4db94011d3 794 * with the EP/channel
sahilmgandhi 18:6a4db94011d3 795 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 796 * @param src : source pointer
sahilmgandhi 18:6a4db94011d3 797 * @param ch_ep_num : endpoint or host channel number
sahilmgandhi 18:6a4db94011d3 798 * @param len : Number of bytes to read
sahilmgandhi 18:6a4db94011d3 799 * @param dma: USB dma enabled or disabled
sahilmgandhi 18:6a4db94011d3 800 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 801 * 0 : DMA feature not used
sahilmgandhi 18:6a4db94011d3 802 * 1 : DMA feature used
sahilmgandhi 18:6a4db94011d3 803 * @retval pointer to destination buffer
sahilmgandhi 18:6a4db94011d3 804 */
sahilmgandhi 18:6a4db94011d3 805 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
sahilmgandhi 18:6a4db94011d3 806 {
sahilmgandhi 18:6a4db94011d3 807 uint32_t i=0U;
sahilmgandhi 18:6a4db94011d3 808 uint32_t count32b = (len + 3U) / 4U;
sahilmgandhi 18:6a4db94011d3 809
sahilmgandhi 18:6a4db94011d3 810 for ( i = 0U; i < count32b; i++, dest += 4U )
sahilmgandhi 18:6a4db94011d3 811 {
sahilmgandhi 18:6a4db94011d3 812 *(__packed uint32_t *)dest = USBx_DFIFO(0U);
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814 }
sahilmgandhi 18:6a4db94011d3 815 return ((void *)dest);
sahilmgandhi 18:6a4db94011d3 816 }
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 /**
sahilmgandhi 18:6a4db94011d3 819 * @brief USB_EPSetStall : set a stall condition over an EP
sahilmgandhi 18:6a4db94011d3 820 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 821 * @param ep: pointer to endpoint structure
sahilmgandhi 18:6a4db94011d3 822 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 823 */
sahilmgandhi 18:6a4db94011d3 824 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
sahilmgandhi 18:6a4db94011d3 825 {
sahilmgandhi 18:6a4db94011d3 826 if (ep->is_in == 1U)
sahilmgandhi 18:6a4db94011d3 827 {
sahilmgandhi 18:6a4db94011d3 828 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0U)
sahilmgandhi 18:6a4db94011d3 829 {
sahilmgandhi 18:6a4db94011d3 830 USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
sahilmgandhi 18:6a4db94011d3 831 }
sahilmgandhi 18:6a4db94011d3 832 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
sahilmgandhi 18:6a4db94011d3 833 }
sahilmgandhi 18:6a4db94011d3 834 else
sahilmgandhi 18:6a4db94011d3 835 {
sahilmgandhi 18:6a4db94011d3 836 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0U)
sahilmgandhi 18:6a4db94011d3 837 {
sahilmgandhi 18:6a4db94011d3 838 USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
sahilmgandhi 18:6a4db94011d3 839 }
sahilmgandhi 18:6a4db94011d3 840 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
sahilmgandhi 18:6a4db94011d3 841 }
sahilmgandhi 18:6a4db94011d3 842 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 843 }
sahilmgandhi 18:6a4db94011d3 844
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 /**
sahilmgandhi 18:6a4db94011d3 847 * @brief USB_EPClearStall : Clear a stall condition over an EP
sahilmgandhi 18:6a4db94011d3 848 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 849 * @param ep: pointer to endpoint structure
sahilmgandhi 18:6a4db94011d3 850 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 851 */
sahilmgandhi 18:6a4db94011d3 852 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
sahilmgandhi 18:6a4db94011d3 853 {
sahilmgandhi 18:6a4db94011d3 854 if (ep->is_in == 1U)
sahilmgandhi 18:6a4db94011d3 855 {
sahilmgandhi 18:6a4db94011d3 856 USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
sahilmgandhi 18:6a4db94011d3 857 if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
sahilmgandhi 18:6a4db94011d3 858 {
sahilmgandhi 18:6a4db94011d3 859 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
sahilmgandhi 18:6a4db94011d3 860 }
sahilmgandhi 18:6a4db94011d3 861 }
sahilmgandhi 18:6a4db94011d3 862 else
sahilmgandhi 18:6a4db94011d3 863 {
sahilmgandhi 18:6a4db94011d3 864 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
sahilmgandhi 18:6a4db94011d3 865 if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
sahilmgandhi 18:6a4db94011d3 866 {
sahilmgandhi 18:6a4db94011d3 867 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
sahilmgandhi 18:6a4db94011d3 868 }
sahilmgandhi 18:6a4db94011d3 869 }
sahilmgandhi 18:6a4db94011d3 870 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 871 }
sahilmgandhi 18:6a4db94011d3 872
sahilmgandhi 18:6a4db94011d3 873 /**
sahilmgandhi 18:6a4db94011d3 874 * @brief USB_StopDevice : Stop the usb device mode
sahilmgandhi 18:6a4db94011d3 875 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 876 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 877 */
sahilmgandhi 18:6a4db94011d3 878 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 879 {
sahilmgandhi 18:6a4db94011d3 880 uint32_t i;
sahilmgandhi 18:6a4db94011d3 881
sahilmgandhi 18:6a4db94011d3 882 /* Clear Pending interrupt */
sahilmgandhi 18:6a4db94011d3 883 for (i = 0U; i < 15U ; i++)
sahilmgandhi 18:6a4db94011d3 884 {
sahilmgandhi 18:6a4db94011d3 885 USBx_INEP(i)->DIEPINT = 0xFFU;
sahilmgandhi 18:6a4db94011d3 886 USBx_OUTEP(i)->DOEPINT = 0xFFU;
sahilmgandhi 18:6a4db94011d3 887 }
sahilmgandhi 18:6a4db94011d3 888 USBx_DEVICE->DAINT = 0xFFFFFFFFU;
sahilmgandhi 18:6a4db94011d3 889
sahilmgandhi 18:6a4db94011d3 890 /* Clear interrupt masks */
sahilmgandhi 18:6a4db94011d3 891 USBx_DEVICE->DIEPMSK = 0U;
sahilmgandhi 18:6a4db94011d3 892 USBx_DEVICE->DOEPMSK = 0U;
sahilmgandhi 18:6a4db94011d3 893 USBx_DEVICE->DAINTMSK = 0U;
sahilmgandhi 18:6a4db94011d3 894
sahilmgandhi 18:6a4db94011d3 895 /* Flush the FIFO */
sahilmgandhi 18:6a4db94011d3 896 USB_FlushRxFifo(USBx);
sahilmgandhi 18:6a4db94011d3 897 USB_FlushTxFifo(USBx , 0x10U);
sahilmgandhi 18:6a4db94011d3 898
sahilmgandhi 18:6a4db94011d3 899 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 900 }
sahilmgandhi 18:6a4db94011d3 901
sahilmgandhi 18:6a4db94011d3 902 /**
sahilmgandhi 18:6a4db94011d3 903 * @brief USB_SetDevAddress : Stop the usb device mode
sahilmgandhi 18:6a4db94011d3 904 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 905 * @param address : new device address to be assigned
sahilmgandhi 18:6a4db94011d3 906 * This parameter can be a value from 0 to 255
sahilmgandhi 18:6a4db94011d3 907 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 908 */
sahilmgandhi 18:6a4db94011d3 909 HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
sahilmgandhi 18:6a4db94011d3 910 {
sahilmgandhi 18:6a4db94011d3 911 USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
sahilmgandhi 18:6a4db94011d3 912 USBx_DEVICE->DCFG |= (address << 4U) & USB_OTG_DCFG_DAD ;
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 /**
sahilmgandhi 18:6a4db94011d3 918 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
sahilmgandhi 18:6a4db94011d3 919 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 920 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 921 */
sahilmgandhi 18:6a4db94011d3 922 HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 923 {
sahilmgandhi 18:6a4db94011d3 924 USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
sahilmgandhi 18:6a4db94011d3 925 HAL_Delay(3U);
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 928 }
sahilmgandhi 18:6a4db94011d3 929
sahilmgandhi 18:6a4db94011d3 930 /**
sahilmgandhi 18:6a4db94011d3 931 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
sahilmgandhi 18:6a4db94011d3 932 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 933 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 934 */
sahilmgandhi 18:6a4db94011d3 935 HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 936 {
sahilmgandhi 18:6a4db94011d3 937 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
sahilmgandhi 18:6a4db94011d3 938 HAL_Delay(3U);
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 941 }
sahilmgandhi 18:6a4db94011d3 942
sahilmgandhi 18:6a4db94011d3 943 /**
sahilmgandhi 18:6a4db94011d3 944 * @brief USB_ReadInterrupts: return the global USB interrupt status
sahilmgandhi 18:6a4db94011d3 945 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 946 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 947 */
sahilmgandhi 18:6a4db94011d3 948 uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 949 {
sahilmgandhi 18:6a4db94011d3 950 uint32_t v = 0U;
sahilmgandhi 18:6a4db94011d3 951
sahilmgandhi 18:6a4db94011d3 952 v = USBx->GINTSTS;
sahilmgandhi 18:6a4db94011d3 953 v &= USBx->GINTMSK;
sahilmgandhi 18:6a4db94011d3 954 return v;
sahilmgandhi 18:6a4db94011d3 955 }
sahilmgandhi 18:6a4db94011d3 956
sahilmgandhi 18:6a4db94011d3 957 /**
sahilmgandhi 18:6a4db94011d3 958 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
sahilmgandhi 18:6a4db94011d3 959 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 960 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 961 */
sahilmgandhi 18:6a4db94011d3 962 uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 963 {
sahilmgandhi 18:6a4db94011d3 964 uint32_t v;
sahilmgandhi 18:6a4db94011d3 965 v = USBx_DEVICE->DAINT;
sahilmgandhi 18:6a4db94011d3 966 v &= USBx_DEVICE->DAINTMSK;
sahilmgandhi 18:6a4db94011d3 967 return ((v & 0xffff0000U) >> 16U);
sahilmgandhi 18:6a4db94011d3 968 }
sahilmgandhi 18:6a4db94011d3 969
sahilmgandhi 18:6a4db94011d3 970 /**
sahilmgandhi 18:6a4db94011d3 971 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
sahilmgandhi 18:6a4db94011d3 972 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 973 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 974 */
sahilmgandhi 18:6a4db94011d3 975 uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 976 {
sahilmgandhi 18:6a4db94011d3 977 uint32_t v;
sahilmgandhi 18:6a4db94011d3 978 v = USBx_DEVICE->DAINT;
sahilmgandhi 18:6a4db94011d3 979 v &= USBx_DEVICE->DAINTMSK;
sahilmgandhi 18:6a4db94011d3 980 return ((v & 0xFFFFU));
sahilmgandhi 18:6a4db94011d3 981 }
sahilmgandhi 18:6a4db94011d3 982
sahilmgandhi 18:6a4db94011d3 983 /**
sahilmgandhi 18:6a4db94011d3 984 * @brief Returns Device OUT EP Interrupt register
sahilmgandhi 18:6a4db94011d3 985 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 986 * @param epnum : endpoint number
sahilmgandhi 18:6a4db94011d3 987 * This parameter can be a value from 0 to 15
sahilmgandhi 18:6a4db94011d3 988 * @retval Device OUT EP Interrupt register
sahilmgandhi 18:6a4db94011d3 989 */
sahilmgandhi 18:6a4db94011d3 990 uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
sahilmgandhi 18:6a4db94011d3 991 {
sahilmgandhi 18:6a4db94011d3 992 uint32_t v;
sahilmgandhi 18:6a4db94011d3 993 v = USBx_OUTEP(epnum)->DOEPINT;
sahilmgandhi 18:6a4db94011d3 994 v &= USBx_DEVICE->DOEPMSK;
sahilmgandhi 18:6a4db94011d3 995 return v;
sahilmgandhi 18:6a4db94011d3 996 }
sahilmgandhi 18:6a4db94011d3 997
sahilmgandhi 18:6a4db94011d3 998 /**
sahilmgandhi 18:6a4db94011d3 999 * @brief Returns Device IN EP Interrupt register
sahilmgandhi 18:6a4db94011d3 1000 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1001 * @param epnum : endpoint number
sahilmgandhi 18:6a4db94011d3 1002 * This parameter can be a value from 0 to 15
sahilmgandhi 18:6a4db94011d3 1003 * @retval Device IN EP Interrupt register
sahilmgandhi 18:6a4db94011d3 1004 */
sahilmgandhi 18:6a4db94011d3 1005 uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
sahilmgandhi 18:6a4db94011d3 1006 {
sahilmgandhi 18:6a4db94011d3 1007 uint32_t v, msk, emp;
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009 msk = USBx_DEVICE->DIEPMSK;
sahilmgandhi 18:6a4db94011d3 1010 emp = USBx_DEVICE->DIEPEMPMSK;
sahilmgandhi 18:6a4db94011d3 1011 msk |= ((emp >> epnum) & 0x1U) << 7U;
sahilmgandhi 18:6a4db94011d3 1012 v = USBx_INEP(epnum)->DIEPINT & msk;
sahilmgandhi 18:6a4db94011d3 1013 return v;
sahilmgandhi 18:6a4db94011d3 1014 }
sahilmgandhi 18:6a4db94011d3 1015
sahilmgandhi 18:6a4db94011d3 1016 /**
sahilmgandhi 18:6a4db94011d3 1017 * @brief USB_ClearInterrupts: clear a USB interrupt
sahilmgandhi 18:6a4db94011d3 1018 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1019 * @param interrupt : interrupt flag
sahilmgandhi 18:6a4db94011d3 1020 * @retval None
sahilmgandhi 18:6a4db94011d3 1021 */
sahilmgandhi 18:6a4db94011d3 1022 void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
sahilmgandhi 18:6a4db94011d3 1023 {
sahilmgandhi 18:6a4db94011d3 1024 USBx->GINTSTS |= interrupt;
sahilmgandhi 18:6a4db94011d3 1025 }
sahilmgandhi 18:6a4db94011d3 1026
sahilmgandhi 18:6a4db94011d3 1027 /**
sahilmgandhi 18:6a4db94011d3 1028 * @brief Returns USB core mode
sahilmgandhi 18:6a4db94011d3 1029 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1030 * @retval return core mode : Host or Device
sahilmgandhi 18:6a4db94011d3 1031 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 1032 * 0 : Host
sahilmgandhi 18:6a4db94011d3 1033 * 1 : Device
sahilmgandhi 18:6a4db94011d3 1034 */
sahilmgandhi 18:6a4db94011d3 1035 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 1036 {
sahilmgandhi 18:6a4db94011d3 1037 return ((USBx->GINTSTS ) & 0x1U);
sahilmgandhi 18:6a4db94011d3 1038 }
sahilmgandhi 18:6a4db94011d3 1039
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041 /**
sahilmgandhi 18:6a4db94011d3 1042 * @brief Activate EP0 for Setup transactions
sahilmgandhi 18:6a4db94011d3 1043 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1044 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1045 */
sahilmgandhi 18:6a4db94011d3 1046 HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 1047 {
sahilmgandhi 18:6a4db94011d3 1048 /* Set the MPS of the IN EP based on the enumeration speed */
sahilmgandhi 18:6a4db94011d3 1049 USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
sahilmgandhi 18:6a4db94011d3 1050
sahilmgandhi 18:6a4db94011d3 1051 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
sahilmgandhi 18:6a4db94011d3 1052 {
sahilmgandhi 18:6a4db94011d3 1053 USBx_INEP(0U)->DIEPCTL |= 3U;
sahilmgandhi 18:6a4db94011d3 1054 }
sahilmgandhi 18:6a4db94011d3 1055 USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
sahilmgandhi 18:6a4db94011d3 1056
sahilmgandhi 18:6a4db94011d3 1057 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1058 }
sahilmgandhi 18:6a4db94011d3 1059
sahilmgandhi 18:6a4db94011d3 1060
sahilmgandhi 18:6a4db94011d3 1061 /**
sahilmgandhi 18:6a4db94011d3 1062 * @brief Prepare the EP0 to start the first control setup
sahilmgandhi 18:6a4db94011d3 1063 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1064 * @param dma: USB dma enabled or disabled
sahilmgandhi 18:6a4db94011d3 1065 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 1066 * 0 : DMA feature not used
sahilmgandhi 18:6a4db94011d3 1067 * 1 : DMA feature used
sahilmgandhi 18:6a4db94011d3 1068 * @param psetup : pointer to setup packet
sahilmgandhi 18:6a4db94011d3 1069 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1070 */
sahilmgandhi 18:6a4db94011d3 1071 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
sahilmgandhi 18:6a4db94011d3 1072 {
sahilmgandhi 18:6a4db94011d3 1073 USBx_OUTEP(0U)->DOEPTSIZ = 0U;
sahilmgandhi 18:6a4db94011d3 1074 USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19U)) ;
sahilmgandhi 18:6a4db94011d3 1075 USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
sahilmgandhi 18:6a4db94011d3 1076 USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 if (dma == 1U)
sahilmgandhi 18:6a4db94011d3 1079 {
sahilmgandhi 18:6a4db94011d3 1080 USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;
sahilmgandhi 18:6a4db94011d3 1081 /* EP enable */
sahilmgandhi 18:6a4db94011d3 1082 USBx_OUTEP(0U)->DOEPCTL = 0x80008000U;
sahilmgandhi 18:6a4db94011d3 1083 }
sahilmgandhi 18:6a4db94011d3 1084
sahilmgandhi 18:6a4db94011d3 1085 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1086 }
sahilmgandhi 18:6a4db94011d3 1087
sahilmgandhi 18:6a4db94011d3 1088
sahilmgandhi 18:6a4db94011d3 1089 /**
sahilmgandhi 18:6a4db94011d3 1090 * @brief Reset the USB Core (needed after USB clock settings change)
sahilmgandhi 18:6a4db94011d3 1091 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1092 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1093 */
sahilmgandhi 18:6a4db94011d3 1094 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 1095 {
sahilmgandhi 18:6a4db94011d3 1096 uint32_t count = 0U;
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 /* Wait for AHB master IDLE state. */
sahilmgandhi 18:6a4db94011d3 1099 do
sahilmgandhi 18:6a4db94011d3 1100 {
sahilmgandhi 18:6a4db94011d3 1101 if (++count > 200000U)
sahilmgandhi 18:6a4db94011d3 1102 {
sahilmgandhi 18:6a4db94011d3 1103 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1104 }
sahilmgandhi 18:6a4db94011d3 1105 }
sahilmgandhi 18:6a4db94011d3 1106 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
sahilmgandhi 18:6a4db94011d3 1107
sahilmgandhi 18:6a4db94011d3 1108 /* Core Soft Reset */
sahilmgandhi 18:6a4db94011d3 1109 count = 0U;
sahilmgandhi 18:6a4db94011d3 1110 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
sahilmgandhi 18:6a4db94011d3 1111
sahilmgandhi 18:6a4db94011d3 1112 do
sahilmgandhi 18:6a4db94011d3 1113 {
sahilmgandhi 18:6a4db94011d3 1114 if (++count > 200000U)
sahilmgandhi 18:6a4db94011d3 1115 {
sahilmgandhi 18:6a4db94011d3 1116 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1117 }
sahilmgandhi 18:6a4db94011d3 1118 }
sahilmgandhi 18:6a4db94011d3 1119 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
sahilmgandhi 18:6a4db94011d3 1120
sahilmgandhi 18:6a4db94011d3 1121 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1122 }
sahilmgandhi 18:6a4db94011d3 1123
sahilmgandhi 18:6a4db94011d3 1124
sahilmgandhi 18:6a4db94011d3 1125 /**
sahilmgandhi 18:6a4db94011d3 1126 * @brief USB_HostInit : Initializes the USB OTG controller registers
sahilmgandhi 18:6a4db94011d3 1127 * for Host mode
sahilmgandhi 18:6a4db94011d3 1128 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1129 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1130 * the configuration information for the specified USBx peripheral.
sahilmgandhi 18:6a4db94011d3 1131 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1132 */
sahilmgandhi 18:6a4db94011d3 1133 HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
sahilmgandhi 18:6a4db94011d3 1134 {
sahilmgandhi 18:6a4db94011d3 1135 uint32_t i;
sahilmgandhi 18:6a4db94011d3 1136
sahilmgandhi 18:6a4db94011d3 1137 /* Restart the Phy Clock */
sahilmgandhi 18:6a4db94011d3 1138 USBx_PCGCCTL = 0U;
sahilmgandhi 18:6a4db94011d3 1139
sahilmgandhi 18:6a4db94011d3 1140 /* Activate VBUS Sensing B */
sahilmgandhi 18:6a4db94011d3 1141 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
sahilmgandhi 18:6a4db94011d3 1142 defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 1143 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
sahilmgandhi 18:6a4db94011d3 1144 #else
sahilmgandhi 18:6a4db94011d3 1145 USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSASEN);
sahilmgandhi 18:6a4db94011d3 1146 USBx->GCCFG &=~ (USB_OTG_GCCFG_VBUSBSEN);
sahilmgandhi 18:6a4db94011d3 1147 USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
sahilmgandhi 18:6a4db94011d3 1148 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 1149
sahilmgandhi 18:6a4db94011d3 1150 /* Disable the FS/LS support mode only */
sahilmgandhi 18:6a4db94011d3 1151 if((cfg.speed == USB_OTG_SPEED_FULL)&&
sahilmgandhi 18:6a4db94011d3 1152 (USBx != USB_OTG_FS))
sahilmgandhi 18:6a4db94011d3 1153 {
sahilmgandhi 18:6a4db94011d3 1154 USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
sahilmgandhi 18:6a4db94011d3 1155 }
sahilmgandhi 18:6a4db94011d3 1156 else
sahilmgandhi 18:6a4db94011d3 1157 {
sahilmgandhi 18:6a4db94011d3 1158 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
sahilmgandhi 18:6a4db94011d3 1159 }
sahilmgandhi 18:6a4db94011d3 1160
sahilmgandhi 18:6a4db94011d3 1161 /* Make sure the FIFOs are flushed. */
sahilmgandhi 18:6a4db94011d3 1162 USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
sahilmgandhi 18:6a4db94011d3 1163 USB_FlushRxFifo(USBx);
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 /* Clear all pending HC Interrupts */
sahilmgandhi 18:6a4db94011d3 1166 for (i = 0U; i < cfg.Host_channels; i++)
sahilmgandhi 18:6a4db94011d3 1167 {
sahilmgandhi 18:6a4db94011d3 1168 USBx_HC(i)->HCINT = 0xFFFFFFFFU;
sahilmgandhi 18:6a4db94011d3 1169 USBx_HC(i)->HCINTMSK = 0U;
sahilmgandhi 18:6a4db94011d3 1170 }
sahilmgandhi 18:6a4db94011d3 1171
sahilmgandhi 18:6a4db94011d3 1172 /* Enable VBUS driving */
sahilmgandhi 18:6a4db94011d3 1173 USB_DriveVbus(USBx, 1U);
sahilmgandhi 18:6a4db94011d3 1174
sahilmgandhi 18:6a4db94011d3 1175 HAL_Delay(200U);
sahilmgandhi 18:6a4db94011d3 1176
sahilmgandhi 18:6a4db94011d3 1177 /* Disable all interrupts. */
sahilmgandhi 18:6a4db94011d3 1178 USBx->GINTMSK = 0U;
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 /* Clear any pending interrupts */
sahilmgandhi 18:6a4db94011d3 1181 USBx->GINTSTS = 0xFFFFFFFFU;
sahilmgandhi 18:6a4db94011d3 1182
sahilmgandhi 18:6a4db94011d3 1183 if(USBx == USB_OTG_FS)
sahilmgandhi 18:6a4db94011d3 1184 {
sahilmgandhi 18:6a4db94011d3 1185 /* set Rx FIFO size */
sahilmgandhi 18:6a4db94011d3 1186 USBx->GRXFSIZ = (uint32_t )0x80U;
sahilmgandhi 18:6a4db94011d3 1187 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60U << 16U)& USB_OTG_NPTXFD) | 0x80U);
sahilmgandhi 18:6a4db94011d3 1188 USBx->HPTXFSIZ = (uint32_t )(((0x40U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
sahilmgandhi 18:6a4db94011d3 1189 }
sahilmgandhi 18:6a4db94011d3 1190 else
sahilmgandhi 18:6a4db94011d3 1191 {
sahilmgandhi 18:6a4db94011d3 1192 /* set Rx FIFO size */
sahilmgandhi 18:6a4db94011d3 1193 USBx->GRXFSIZ = (uint32_t )0x200U;
sahilmgandhi 18:6a4db94011d3 1194 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100U << 16U)& USB_OTG_NPTXFD) | 0x200U);
sahilmgandhi 18:6a4db94011d3 1195 USBx->HPTXFSIZ = (uint32_t )(((0xE0U << 16U)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
sahilmgandhi 18:6a4db94011d3 1196 }
sahilmgandhi 18:6a4db94011d3 1197
sahilmgandhi 18:6a4db94011d3 1198 /* Enable the common interrupts */
sahilmgandhi 18:6a4db94011d3 1199 if (cfg.dma_enable == DISABLE)
sahilmgandhi 18:6a4db94011d3 1200 {
sahilmgandhi 18:6a4db94011d3 1201 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
sahilmgandhi 18:6a4db94011d3 1202 }
sahilmgandhi 18:6a4db94011d3 1203
sahilmgandhi 18:6a4db94011d3 1204 /* Enable interrupts matching to the Host mode ONLY */
sahilmgandhi 18:6a4db94011d3 1205 USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
sahilmgandhi 18:6a4db94011d3 1206 USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
sahilmgandhi 18:6a4db94011d3 1207 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
sahilmgandhi 18:6a4db94011d3 1208
sahilmgandhi 18:6a4db94011d3 1209 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1210 }
sahilmgandhi 18:6a4db94011d3 1211
sahilmgandhi 18:6a4db94011d3 1212 /**
sahilmgandhi 18:6a4db94011d3 1213 * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
sahilmgandhi 18:6a4db94011d3 1214 * HCFG register on the PHY type and set the right frame interval
sahilmgandhi 18:6a4db94011d3 1215 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1216 * @param freq : clock frequency
sahilmgandhi 18:6a4db94011d3 1217 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 1218 * HCFG_48_MHZ : Full Speed 48 MHz Clock
sahilmgandhi 18:6a4db94011d3 1219 * HCFG_6_MHZ : Low Speed 6 MHz Clock
sahilmgandhi 18:6a4db94011d3 1220 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1221 */
sahilmgandhi 18:6a4db94011d3 1222 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
sahilmgandhi 18:6a4db94011d3 1223 {
sahilmgandhi 18:6a4db94011d3 1224 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
sahilmgandhi 18:6a4db94011d3 1225 USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
sahilmgandhi 18:6a4db94011d3 1226
sahilmgandhi 18:6a4db94011d3 1227 if (freq == HCFG_48_MHZ)
sahilmgandhi 18:6a4db94011d3 1228 {
sahilmgandhi 18:6a4db94011d3 1229 USBx_HOST->HFIR = (uint32_t)48000U;
sahilmgandhi 18:6a4db94011d3 1230 }
sahilmgandhi 18:6a4db94011d3 1231 else if (freq == HCFG_6_MHZ)
sahilmgandhi 18:6a4db94011d3 1232 {
sahilmgandhi 18:6a4db94011d3 1233 USBx_HOST->HFIR = (uint32_t)6000U;
sahilmgandhi 18:6a4db94011d3 1234 }
sahilmgandhi 18:6a4db94011d3 1235 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1236 }
sahilmgandhi 18:6a4db94011d3 1237
sahilmgandhi 18:6a4db94011d3 1238 /**
sahilmgandhi 18:6a4db94011d3 1239 * @brief USB_OTG_ResetPort : Reset Host Port
sahilmgandhi 18:6a4db94011d3 1240 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1241 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1242 * @note (1)The application must wait at least 10 ms
sahilmgandhi 18:6a4db94011d3 1243 * before clearing the reset bit.
sahilmgandhi 18:6a4db94011d3 1244 */
sahilmgandhi 18:6a4db94011d3 1245 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 1246 {
sahilmgandhi 18:6a4db94011d3 1247 __IO uint32_t hprt0;
sahilmgandhi 18:6a4db94011d3 1248
sahilmgandhi 18:6a4db94011d3 1249 hprt0 = USBx_HPRT0;
sahilmgandhi 18:6a4db94011d3 1250
sahilmgandhi 18:6a4db94011d3 1251 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
sahilmgandhi 18:6a4db94011d3 1252 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
sahilmgandhi 18:6a4db94011d3 1253
sahilmgandhi 18:6a4db94011d3 1254 USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
sahilmgandhi 18:6a4db94011d3 1255 HAL_Delay (10U); /* See Note #1 */
sahilmgandhi 18:6a4db94011d3 1256 USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
sahilmgandhi 18:6a4db94011d3 1257 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1258 }
sahilmgandhi 18:6a4db94011d3 1259
sahilmgandhi 18:6a4db94011d3 1260 /**
sahilmgandhi 18:6a4db94011d3 1261 * @brief USB_DriveVbus : activate or de-activate vbus
sahilmgandhi 18:6a4db94011d3 1262 * @param state : VBUS state
sahilmgandhi 18:6a4db94011d3 1263 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 1264 * 0 : VBUS Active
sahilmgandhi 18:6a4db94011d3 1265 * 1 : VBUS Inactive
sahilmgandhi 18:6a4db94011d3 1266 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1267 */
sahilmgandhi 18:6a4db94011d3 1268 HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
sahilmgandhi 18:6a4db94011d3 1269 {
sahilmgandhi 18:6a4db94011d3 1270 __IO uint32_t hprt0;
sahilmgandhi 18:6a4db94011d3 1271
sahilmgandhi 18:6a4db94011d3 1272 hprt0 = USBx_HPRT0;
sahilmgandhi 18:6a4db94011d3 1273 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
sahilmgandhi 18:6a4db94011d3 1274 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
sahilmgandhi 18:6a4db94011d3 1275
sahilmgandhi 18:6a4db94011d3 1276 if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
sahilmgandhi 18:6a4db94011d3 1277 {
sahilmgandhi 18:6a4db94011d3 1278 USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
sahilmgandhi 18:6a4db94011d3 1279 }
sahilmgandhi 18:6a4db94011d3 1280 if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
sahilmgandhi 18:6a4db94011d3 1281 {
sahilmgandhi 18:6a4db94011d3 1282 USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
sahilmgandhi 18:6a4db94011d3 1283 }
sahilmgandhi 18:6a4db94011d3 1284 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1285 }
sahilmgandhi 18:6a4db94011d3 1286
sahilmgandhi 18:6a4db94011d3 1287 /**
sahilmgandhi 18:6a4db94011d3 1288 * @brief Return Host Core speed
sahilmgandhi 18:6a4db94011d3 1289 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1290 * @retval speed : Host speed
sahilmgandhi 18:6a4db94011d3 1291 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 1292 * @arg USB_OTG_SPEED_HIGH: High speed mode
sahilmgandhi 18:6a4db94011d3 1293 * @arg USB_OTG_SPEED_FULL: Full speed mode
sahilmgandhi 18:6a4db94011d3 1294 * @arg USB_OTG_SPEED_LOW: Low speed mode
sahilmgandhi 18:6a4db94011d3 1295 */
sahilmgandhi 18:6a4db94011d3 1296 uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 1297 {
sahilmgandhi 18:6a4db94011d3 1298 __IO uint32_t hprt0;
sahilmgandhi 18:6a4db94011d3 1299
sahilmgandhi 18:6a4db94011d3 1300 hprt0 = USBx_HPRT0;
sahilmgandhi 18:6a4db94011d3 1301 return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17U);
sahilmgandhi 18:6a4db94011d3 1302 }
sahilmgandhi 18:6a4db94011d3 1303
sahilmgandhi 18:6a4db94011d3 1304 /**
sahilmgandhi 18:6a4db94011d3 1305 * @brief Return Host Current Frame number
sahilmgandhi 18:6a4db94011d3 1306 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1307 * @retval current frame number
sahilmgandhi 18:6a4db94011d3 1308 */
sahilmgandhi 18:6a4db94011d3 1309 uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 1310 {
sahilmgandhi 18:6a4db94011d3 1311 return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
sahilmgandhi 18:6a4db94011d3 1312 }
sahilmgandhi 18:6a4db94011d3 1313
sahilmgandhi 18:6a4db94011d3 1314 /**
sahilmgandhi 18:6a4db94011d3 1315 * @brief Initialize a host channel
sahilmgandhi 18:6a4db94011d3 1316 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1317 * @param ch_num : Channel number
sahilmgandhi 18:6a4db94011d3 1318 * This parameter can be a value from 1 to 15
sahilmgandhi 18:6a4db94011d3 1319 * @param epnum : Endpoint number
sahilmgandhi 18:6a4db94011d3 1320 * This parameter can be a value from 1 to 15
sahilmgandhi 18:6a4db94011d3 1321 * @param dev_address : Current device address
sahilmgandhi 18:6a4db94011d3 1322 * This parameter can be a value from 0 to 255
sahilmgandhi 18:6a4db94011d3 1323 * @param speed : Current device speed
sahilmgandhi 18:6a4db94011d3 1324 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 1325 * @arg USB_OTG_SPEED_HIGH: High speed mode
sahilmgandhi 18:6a4db94011d3 1326 * @arg USB_OTG_SPEED_FULL: Full speed mode
sahilmgandhi 18:6a4db94011d3 1327 * @arg USB_OTG_SPEED_LOW: Low speed mode
sahilmgandhi 18:6a4db94011d3 1328 * @param ep_type : Endpoint Type
sahilmgandhi 18:6a4db94011d3 1329 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 1330 * @arg EP_TYPE_CTRL: Control type
sahilmgandhi 18:6a4db94011d3 1331 * @arg EP_TYPE_ISOC: Isochronous type
sahilmgandhi 18:6a4db94011d3 1332 * @arg EP_TYPE_BULK: Bulk type
sahilmgandhi 18:6a4db94011d3 1333 * @arg EP_TYPE_INTR: Interrupt type
sahilmgandhi 18:6a4db94011d3 1334 * @param mps : Max Packet Size
sahilmgandhi 18:6a4db94011d3 1335 * This parameter can be a value from 0 to32K
sahilmgandhi 18:6a4db94011d3 1336 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1337 */
sahilmgandhi 18:6a4db94011d3 1338 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
sahilmgandhi 18:6a4db94011d3 1339 uint8_t ch_num,
sahilmgandhi 18:6a4db94011d3 1340 uint8_t epnum,
sahilmgandhi 18:6a4db94011d3 1341 uint8_t dev_address,
sahilmgandhi 18:6a4db94011d3 1342 uint8_t speed,
sahilmgandhi 18:6a4db94011d3 1343 uint8_t ep_type,
sahilmgandhi 18:6a4db94011d3 1344 uint16_t mps)
sahilmgandhi 18:6a4db94011d3 1345 {
sahilmgandhi 18:6a4db94011d3 1346
sahilmgandhi 18:6a4db94011d3 1347 /* Clear old interrupt conditions for this host channel. */
sahilmgandhi 18:6a4db94011d3 1348 USBx_HC(ch_num)->HCINT = 0xFFFFFFFFU;
sahilmgandhi 18:6a4db94011d3 1349
sahilmgandhi 18:6a4db94011d3 1350 /* Enable channel interrupts required for this transfer. */
sahilmgandhi 18:6a4db94011d3 1351 switch (ep_type)
sahilmgandhi 18:6a4db94011d3 1352 {
sahilmgandhi 18:6a4db94011d3 1353 case EP_TYPE_CTRL:
sahilmgandhi 18:6a4db94011d3 1354 case EP_TYPE_BULK:
sahilmgandhi 18:6a4db94011d3 1355
sahilmgandhi 18:6a4db94011d3 1356 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
sahilmgandhi 18:6a4db94011d3 1357 USB_OTG_HCINTMSK_STALLM |\
sahilmgandhi 18:6a4db94011d3 1358 USB_OTG_HCINTMSK_TXERRM |\
sahilmgandhi 18:6a4db94011d3 1359 USB_OTG_HCINTMSK_DTERRM |\
sahilmgandhi 18:6a4db94011d3 1360 USB_OTG_HCINTMSK_AHBERR |\
sahilmgandhi 18:6a4db94011d3 1361 USB_OTG_HCINTMSK_NAKM ;
sahilmgandhi 18:6a4db94011d3 1362
sahilmgandhi 18:6a4db94011d3 1363 if (epnum & 0x80U)
sahilmgandhi 18:6a4db94011d3 1364 {
sahilmgandhi 18:6a4db94011d3 1365 USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
sahilmgandhi 18:6a4db94011d3 1366 }
sahilmgandhi 18:6a4db94011d3 1367 else
sahilmgandhi 18:6a4db94011d3 1368 {
sahilmgandhi 18:6a4db94011d3 1369 if(USBx != USB_OTG_FS)
sahilmgandhi 18:6a4db94011d3 1370 {
sahilmgandhi 18:6a4db94011d3 1371 USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
sahilmgandhi 18:6a4db94011d3 1372 }
sahilmgandhi 18:6a4db94011d3 1373 }
sahilmgandhi 18:6a4db94011d3 1374 break;
sahilmgandhi 18:6a4db94011d3 1375
sahilmgandhi 18:6a4db94011d3 1376 case EP_TYPE_INTR:
sahilmgandhi 18:6a4db94011d3 1377
sahilmgandhi 18:6a4db94011d3 1378 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
sahilmgandhi 18:6a4db94011d3 1379 USB_OTG_HCINTMSK_STALLM |\
sahilmgandhi 18:6a4db94011d3 1380 USB_OTG_HCINTMSK_TXERRM |\
sahilmgandhi 18:6a4db94011d3 1381 USB_OTG_HCINTMSK_DTERRM |\
sahilmgandhi 18:6a4db94011d3 1382 USB_OTG_HCINTMSK_NAKM |\
sahilmgandhi 18:6a4db94011d3 1383 USB_OTG_HCINTMSK_AHBERR |\
sahilmgandhi 18:6a4db94011d3 1384 USB_OTG_HCINTMSK_FRMORM ;
sahilmgandhi 18:6a4db94011d3 1385
sahilmgandhi 18:6a4db94011d3 1386 if (epnum & 0x80U)
sahilmgandhi 18:6a4db94011d3 1387 {
sahilmgandhi 18:6a4db94011d3 1388 USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
sahilmgandhi 18:6a4db94011d3 1389 }
sahilmgandhi 18:6a4db94011d3 1390
sahilmgandhi 18:6a4db94011d3 1391 break;
sahilmgandhi 18:6a4db94011d3 1392 case EP_TYPE_ISOC:
sahilmgandhi 18:6a4db94011d3 1393
sahilmgandhi 18:6a4db94011d3 1394 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
sahilmgandhi 18:6a4db94011d3 1395 USB_OTG_HCINTMSK_ACKM |\
sahilmgandhi 18:6a4db94011d3 1396 USB_OTG_HCINTMSK_AHBERR |\
sahilmgandhi 18:6a4db94011d3 1397 USB_OTG_HCINTMSK_FRMORM ;
sahilmgandhi 18:6a4db94011d3 1398
sahilmgandhi 18:6a4db94011d3 1399 if (epnum & 0x80U)
sahilmgandhi 18:6a4db94011d3 1400 {
sahilmgandhi 18:6a4db94011d3 1401 USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
sahilmgandhi 18:6a4db94011d3 1402 }
sahilmgandhi 18:6a4db94011d3 1403 break;
sahilmgandhi 18:6a4db94011d3 1404 }
sahilmgandhi 18:6a4db94011d3 1405
sahilmgandhi 18:6a4db94011d3 1406 /* Enable the top level host channel interrupt. */
sahilmgandhi 18:6a4db94011d3 1407 USBx_HOST->HAINTMSK |= (1 << ch_num);
sahilmgandhi 18:6a4db94011d3 1408
sahilmgandhi 18:6a4db94011d3 1409 /* Make sure host channel interrupts are enabled. */
sahilmgandhi 18:6a4db94011d3 1410 USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
sahilmgandhi 18:6a4db94011d3 1411
sahilmgandhi 18:6a4db94011d3 1412 /* Program the HCCHAR register */
sahilmgandhi 18:6a4db94011d3 1413 USBx_HC(ch_num)->HCCHAR = (((dev_address << 22U) & USB_OTG_HCCHAR_DAD) |\
sahilmgandhi 18:6a4db94011d3 1414 (((epnum & 0x7FU)<< 11U) & USB_OTG_HCCHAR_EPNUM)|\
sahilmgandhi 18:6a4db94011d3 1415 ((((epnum & 0x80U) == 0x80U)<< 15U) & USB_OTG_HCCHAR_EPDIR)|\
sahilmgandhi 18:6a4db94011d3 1416 (((speed == USB_OTG_SPEED_LOW)<< 17U) & USB_OTG_HCCHAR_LSDEV)|\
sahilmgandhi 18:6a4db94011d3 1417 ((ep_type << 18U) & USB_OTG_HCCHAR_EPTYP)|\
sahilmgandhi 18:6a4db94011d3 1418 (mps & USB_OTG_HCCHAR_MPSIZ));
sahilmgandhi 18:6a4db94011d3 1419
sahilmgandhi 18:6a4db94011d3 1420 if (ep_type == EP_TYPE_INTR)
sahilmgandhi 18:6a4db94011d3 1421 {
sahilmgandhi 18:6a4db94011d3 1422 USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
sahilmgandhi 18:6a4db94011d3 1423 }
sahilmgandhi 18:6a4db94011d3 1424
sahilmgandhi 18:6a4db94011d3 1425 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1426 }
sahilmgandhi 18:6a4db94011d3 1427
sahilmgandhi 18:6a4db94011d3 1428 /**
sahilmgandhi 18:6a4db94011d3 1429 * @brief Start a transfer over a host channel
sahilmgandhi 18:6a4db94011d3 1430 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1431 * @param hc : pointer to host channel structure
sahilmgandhi 18:6a4db94011d3 1432 * @param dma: USB dma enabled or disabled
sahilmgandhi 18:6a4db94011d3 1433 * This parameter can be one of these values:
sahilmgandhi 18:6a4db94011d3 1434 * 0 : DMA feature not used
sahilmgandhi 18:6a4db94011d3 1435 * 1 : DMA feature used
sahilmgandhi 18:6a4db94011d3 1436 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1437 */
sahilmgandhi 18:6a4db94011d3 1438 #if defined (__CC_ARM) /*!< ARM Compiler */
sahilmgandhi 18:6a4db94011d3 1439 #pragma O0
sahilmgandhi 18:6a4db94011d3 1440 #elif defined (__GNUC__) /*!< GNU Compiler */
sahilmgandhi 18:6a4db94011d3 1441 #pragma GCC optimize ("O0")
sahilmgandhi 18:6a4db94011d3 1442 #endif /* __CC_ARM */
sahilmgandhi 18:6a4db94011d3 1443 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
sahilmgandhi 18:6a4db94011d3 1444 {
sahilmgandhi 18:6a4db94011d3 1445 uint8_t is_oddframe = 0U;
sahilmgandhi 18:6a4db94011d3 1446 uint16_t len_words = 0U;
sahilmgandhi 18:6a4db94011d3 1447 uint16_t num_packets = 0U;
sahilmgandhi 18:6a4db94011d3 1448 uint16_t max_hc_pkt_count = 256U;
sahilmgandhi 18:6a4db94011d3 1449 uint32_t tmpreg = 0U;
sahilmgandhi 18:6a4db94011d3 1450
sahilmgandhi 18:6a4db94011d3 1451 if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
sahilmgandhi 18:6a4db94011d3 1452 {
sahilmgandhi 18:6a4db94011d3 1453 if((dma == 0U) && (hc->do_ping == 1U))
sahilmgandhi 18:6a4db94011d3 1454 {
sahilmgandhi 18:6a4db94011d3 1455 USB_DoPing(USBx, hc->ch_num);
sahilmgandhi 18:6a4db94011d3 1456 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1457 }
sahilmgandhi 18:6a4db94011d3 1458 else if(dma == 1U)
sahilmgandhi 18:6a4db94011d3 1459 {
sahilmgandhi 18:6a4db94011d3 1460 USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
sahilmgandhi 18:6a4db94011d3 1461 hc->do_ping = 0U;
sahilmgandhi 18:6a4db94011d3 1462 }
sahilmgandhi 18:6a4db94011d3 1463 }
sahilmgandhi 18:6a4db94011d3 1464
sahilmgandhi 18:6a4db94011d3 1465 /* Compute the expected number of packets associated to the transfer */
sahilmgandhi 18:6a4db94011d3 1466 if (hc->xfer_len > 0U)
sahilmgandhi 18:6a4db94011d3 1467 {
sahilmgandhi 18:6a4db94011d3 1468 num_packets = (hc->xfer_len + hc->max_packet - 1U) / hc->max_packet;
sahilmgandhi 18:6a4db94011d3 1469
sahilmgandhi 18:6a4db94011d3 1470 if (num_packets > max_hc_pkt_count)
sahilmgandhi 18:6a4db94011d3 1471 {
sahilmgandhi 18:6a4db94011d3 1472 num_packets = max_hc_pkt_count;
sahilmgandhi 18:6a4db94011d3 1473 hc->xfer_len = num_packets * hc->max_packet;
sahilmgandhi 18:6a4db94011d3 1474 }
sahilmgandhi 18:6a4db94011d3 1475 }
sahilmgandhi 18:6a4db94011d3 1476 else
sahilmgandhi 18:6a4db94011d3 1477 {
sahilmgandhi 18:6a4db94011d3 1478 num_packets = 1U;
sahilmgandhi 18:6a4db94011d3 1479 }
sahilmgandhi 18:6a4db94011d3 1480 if (hc->ep_is_in)
sahilmgandhi 18:6a4db94011d3 1481 {
sahilmgandhi 18:6a4db94011d3 1482 hc->xfer_len = num_packets * hc->max_packet;
sahilmgandhi 18:6a4db94011d3 1483 }
sahilmgandhi 18:6a4db94011d3 1484
sahilmgandhi 18:6a4db94011d3 1485 /* Initialize the HCTSIZn register */
sahilmgandhi 18:6a4db94011d3 1486 USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
sahilmgandhi 18:6a4db94011d3 1487 ((num_packets << 19U) & USB_OTG_HCTSIZ_PKTCNT) |\
sahilmgandhi 18:6a4db94011d3 1488 (((hc->data_pid) << 29U) & USB_OTG_HCTSIZ_DPID);
sahilmgandhi 18:6a4db94011d3 1489
sahilmgandhi 18:6a4db94011d3 1490 if (dma)
sahilmgandhi 18:6a4db94011d3 1491 {
sahilmgandhi 18:6a4db94011d3 1492 /* xfer_buff MUST be 32-bits aligned */
sahilmgandhi 18:6a4db94011d3 1493 USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
sahilmgandhi 18:6a4db94011d3 1494 }
sahilmgandhi 18:6a4db94011d3 1495
sahilmgandhi 18:6a4db94011d3 1496 is_oddframe = (USBx_HOST->HFNUM & 0x01U) ? 0U : 1U;
sahilmgandhi 18:6a4db94011d3 1497 USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
sahilmgandhi 18:6a4db94011d3 1498 USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29U);
sahilmgandhi 18:6a4db94011d3 1499
sahilmgandhi 18:6a4db94011d3 1500 /* Set host channel enable */
sahilmgandhi 18:6a4db94011d3 1501 tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
sahilmgandhi 18:6a4db94011d3 1502 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
sahilmgandhi 18:6a4db94011d3 1503 tmpreg |= USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1504 USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
sahilmgandhi 18:6a4db94011d3 1505
sahilmgandhi 18:6a4db94011d3 1506 if (dma == 0U) /* Slave mode */
sahilmgandhi 18:6a4db94011d3 1507 {
sahilmgandhi 18:6a4db94011d3 1508 if((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
sahilmgandhi 18:6a4db94011d3 1509 {
sahilmgandhi 18:6a4db94011d3 1510 switch(hc->ep_type)
sahilmgandhi 18:6a4db94011d3 1511 {
sahilmgandhi 18:6a4db94011d3 1512 /* Non periodic transfer */
sahilmgandhi 18:6a4db94011d3 1513 case EP_TYPE_CTRL:
sahilmgandhi 18:6a4db94011d3 1514 case EP_TYPE_BULK:
sahilmgandhi 18:6a4db94011d3 1515
sahilmgandhi 18:6a4db94011d3 1516 len_words = (hc->xfer_len + 3U) / 4U;
sahilmgandhi 18:6a4db94011d3 1517
sahilmgandhi 18:6a4db94011d3 1518 /* check if there is enough space in FIFO space */
sahilmgandhi 18:6a4db94011d3 1519 if(len_words > (USBx->HNPTXSTS & 0xFFFFU))
sahilmgandhi 18:6a4db94011d3 1520 {
sahilmgandhi 18:6a4db94011d3 1521 /* need to process data in nptxfempty interrupt */
sahilmgandhi 18:6a4db94011d3 1522 USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
sahilmgandhi 18:6a4db94011d3 1523 }
sahilmgandhi 18:6a4db94011d3 1524 break;
sahilmgandhi 18:6a4db94011d3 1525 /* Periodic transfer */
sahilmgandhi 18:6a4db94011d3 1526 case EP_TYPE_INTR:
sahilmgandhi 18:6a4db94011d3 1527 case EP_TYPE_ISOC:
sahilmgandhi 18:6a4db94011d3 1528 len_words = (hc->xfer_len + 3U) / 4U;
sahilmgandhi 18:6a4db94011d3 1529 /* check if there is enough space in FIFO space */
sahilmgandhi 18:6a4db94011d3 1530 if(len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
sahilmgandhi 18:6a4db94011d3 1531 {
sahilmgandhi 18:6a4db94011d3 1532 /* need to process data in ptxfempty interrupt */
sahilmgandhi 18:6a4db94011d3 1533 USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
sahilmgandhi 18:6a4db94011d3 1534 }
sahilmgandhi 18:6a4db94011d3 1535 break;
sahilmgandhi 18:6a4db94011d3 1536
sahilmgandhi 18:6a4db94011d3 1537 default:
sahilmgandhi 18:6a4db94011d3 1538 break;
sahilmgandhi 18:6a4db94011d3 1539 }
sahilmgandhi 18:6a4db94011d3 1540
sahilmgandhi 18:6a4db94011d3 1541 /* Write packet into the Tx FIFO. */
sahilmgandhi 18:6a4db94011d3 1542 USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
sahilmgandhi 18:6a4db94011d3 1543 hc->xfer_count = hc->xfer_len;
sahilmgandhi 18:6a4db94011d3 1544 }
sahilmgandhi 18:6a4db94011d3 1545 }
sahilmgandhi 18:6a4db94011d3 1546
sahilmgandhi 18:6a4db94011d3 1547 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1548 }
sahilmgandhi 18:6a4db94011d3 1549
sahilmgandhi 18:6a4db94011d3 1550 /**
sahilmgandhi 18:6a4db94011d3 1551 * @brief Read all host channel interrupts status
sahilmgandhi 18:6a4db94011d3 1552 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1553 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1554 */
sahilmgandhi 18:6a4db94011d3 1555 uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 1556 {
sahilmgandhi 18:6a4db94011d3 1557 return ((USBx_HOST->HAINT) & 0xFFFFU);
sahilmgandhi 18:6a4db94011d3 1558 }
sahilmgandhi 18:6a4db94011d3 1559
sahilmgandhi 18:6a4db94011d3 1560 /**
sahilmgandhi 18:6a4db94011d3 1561 * @brief Halt a host channel
sahilmgandhi 18:6a4db94011d3 1562 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1563 * @param hc_num : Host Channel number
sahilmgandhi 18:6a4db94011d3 1564 * This parameter can be a value from 1 to 15
sahilmgandhi 18:6a4db94011d3 1565 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1566 */
sahilmgandhi 18:6a4db94011d3 1567 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
sahilmgandhi 18:6a4db94011d3 1568 {
sahilmgandhi 18:6a4db94011d3 1569 uint32_t count = 0U;
sahilmgandhi 18:6a4db94011d3 1570
sahilmgandhi 18:6a4db94011d3 1571 /* Check for space in the request queue to issue the halt. */
sahilmgandhi 18:6a4db94011d3 1572 if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || (((((USBx_HC(hc_num)->HCCHAR) &
sahilmgandhi 18:6a4db94011d3 1573 USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
sahilmgandhi 18:6a4db94011d3 1574 {
sahilmgandhi 18:6a4db94011d3 1575 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
sahilmgandhi 18:6a4db94011d3 1576
sahilmgandhi 18:6a4db94011d3 1577 if ((USBx->HNPTXSTS & 0xFF0000U) == 0U)
sahilmgandhi 18:6a4db94011d3 1578 {
sahilmgandhi 18:6a4db94011d3 1579 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1580 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1581 do
sahilmgandhi 18:6a4db94011d3 1582 {
sahilmgandhi 18:6a4db94011d3 1583 if (++count > 1000U)
sahilmgandhi 18:6a4db94011d3 1584 {
sahilmgandhi 18:6a4db94011d3 1585 break;
sahilmgandhi 18:6a4db94011d3 1586 }
sahilmgandhi 18:6a4db94011d3 1587 }
sahilmgandhi 18:6a4db94011d3 1588 while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
sahilmgandhi 18:6a4db94011d3 1589 }
sahilmgandhi 18:6a4db94011d3 1590 else
sahilmgandhi 18:6a4db94011d3 1591 {
sahilmgandhi 18:6a4db94011d3 1592 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1593 }
sahilmgandhi 18:6a4db94011d3 1594 }
sahilmgandhi 18:6a4db94011d3 1595 else
sahilmgandhi 18:6a4db94011d3 1596 {
sahilmgandhi 18:6a4db94011d3 1597 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
sahilmgandhi 18:6a4db94011d3 1598
sahilmgandhi 18:6a4db94011d3 1599 if ((USBx_HOST->HPTXSTS & 0xFFFFU) == 0U)
sahilmgandhi 18:6a4db94011d3 1600 {
sahilmgandhi 18:6a4db94011d3 1601 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1602 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1603 do
sahilmgandhi 18:6a4db94011d3 1604 {
sahilmgandhi 18:6a4db94011d3 1605 if (++count > 1000U)
sahilmgandhi 18:6a4db94011d3 1606 {
sahilmgandhi 18:6a4db94011d3 1607 break;
sahilmgandhi 18:6a4db94011d3 1608 }
sahilmgandhi 18:6a4db94011d3 1609 }
sahilmgandhi 18:6a4db94011d3 1610 while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
sahilmgandhi 18:6a4db94011d3 1611 }
sahilmgandhi 18:6a4db94011d3 1612 else
sahilmgandhi 18:6a4db94011d3 1613 {
sahilmgandhi 18:6a4db94011d3 1614 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1615 }
sahilmgandhi 18:6a4db94011d3 1616 }
sahilmgandhi 18:6a4db94011d3 1617
sahilmgandhi 18:6a4db94011d3 1618 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1619 }
sahilmgandhi 18:6a4db94011d3 1620
sahilmgandhi 18:6a4db94011d3 1621 /**
sahilmgandhi 18:6a4db94011d3 1622 * @brief Initiate Do Ping protocol
sahilmgandhi 18:6a4db94011d3 1623 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1624 * @param hc_num : Host Channel number
sahilmgandhi 18:6a4db94011d3 1625 * This parameter can be a value from 1 to 15
sahilmgandhi 18:6a4db94011d3 1626 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1627 */
sahilmgandhi 18:6a4db94011d3 1628 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
sahilmgandhi 18:6a4db94011d3 1629 {
sahilmgandhi 18:6a4db94011d3 1630 uint8_t num_packets = 1U;
sahilmgandhi 18:6a4db94011d3 1631 uint32_t tmpreg = 0U;
sahilmgandhi 18:6a4db94011d3 1632
sahilmgandhi 18:6a4db94011d3 1633 USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19U) & USB_OTG_HCTSIZ_PKTCNT) |\
sahilmgandhi 18:6a4db94011d3 1634 USB_OTG_HCTSIZ_DOPING;
sahilmgandhi 18:6a4db94011d3 1635
sahilmgandhi 18:6a4db94011d3 1636 /* Set host channel enable */
sahilmgandhi 18:6a4db94011d3 1637 tmpreg = USBx_HC(ch_num)->HCCHAR;
sahilmgandhi 18:6a4db94011d3 1638 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
sahilmgandhi 18:6a4db94011d3 1639 tmpreg |= USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1640 USBx_HC(ch_num)->HCCHAR = tmpreg;
sahilmgandhi 18:6a4db94011d3 1641
sahilmgandhi 18:6a4db94011d3 1642 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1643 }
sahilmgandhi 18:6a4db94011d3 1644
sahilmgandhi 18:6a4db94011d3 1645 /**
sahilmgandhi 18:6a4db94011d3 1646 * @brief Stop Host Core
sahilmgandhi 18:6a4db94011d3 1647 * @param USBx : Selected device
sahilmgandhi 18:6a4db94011d3 1648 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1649 */
sahilmgandhi 18:6a4db94011d3 1650 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
sahilmgandhi 18:6a4db94011d3 1651 {
sahilmgandhi 18:6a4db94011d3 1652 uint8_t i;
sahilmgandhi 18:6a4db94011d3 1653 uint32_t count = 0U;
sahilmgandhi 18:6a4db94011d3 1654 uint32_t value;
sahilmgandhi 18:6a4db94011d3 1655
sahilmgandhi 18:6a4db94011d3 1656 USB_DisableGlobalInt(USBx);
sahilmgandhi 18:6a4db94011d3 1657
sahilmgandhi 18:6a4db94011d3 1658 /* Flush FIFO */
sahilmgandhi 18:6a4db94011d3 1659 USB_FlushTxFifo(USBx, 0x10U);
sahilmgandhi 18:6a4db94011d3 1660 USB_FlushRxFifo(USBx);
sahilmgandhi 18:6a4db94011d3 1661
sahilmgandhi 18:6a4db94011d3 1662 /* Flush out any leftover queued requests. */
sahilmgandhi 18:6a4db94011d3 1663 for (i = 0U; i <= 15U; i++)
sahilmgandhi 18:6a4db94011d3 1664 {
sahilmgandhi 18:6a4db94011d3 1665
sahilmgandhi 18:6a4db94011d3 1666 value = USBx_HC(i)->HCCHAR ;
sahilmgandhi 18:6a4db94011d3 1667 value |= USB_OTG_HCCHAR_CHDIS;
sahilmgandhi 18:6a4db94011d3 1668 value &= ~USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1669 value &= ~USB_OTG_HCCHAR_EPDIR;
sahilmgandhi 18:6a4db94011d3 1670 USBx_HC(i)->HCCHAR = value;
sahilmgandhi 18:6a4db94011d3 1671 }
sahilmgandhi 18:6a4db94011d3 1672
sahilmgandhi 18:6a4db94011d3 1673 /* Halt all channels to put them into a known state. */
sahilmgandhi 18:6a4db94011d3 1674 for (i = 0U; i <= 15U; i++)
sahilmgandhi 18:6a4db94011d3 1675 {
sahilmgandhi 18:6a4db94011d3 1676 value = USBx_HC(i)->HCCHAR ;
sahilmgandhi 18:6a4db94011d3 1677
sahilmgandhi 18:6a4db94011d3 1678 value |= USB_OTG_HCCHAR_CHDIS;
sahilmgandhi 18:6a4db94011d3 1679 value |= USB_OTG_HCCHAR_CHENA;
sahilmgandhi 18:6a4db94011d3 1680 value &= ~USB_OTG_HCCHAR_EPDIR;
sahilmgandhi 18:6a4db94011d3 1681
sahilmgandhi 18:6a4db94011d3 1682 USBx_HC(i)->HCCHAR = value;
sahilmgandhi 18:6a4db94011d3 1683 do
sahilmgandhi 18:6a4db94011d3 1684 {
sahilmgandhi 18:6a4db94011d3 1685 if (++count > 1000U)
sahilmgandhi 18:6a4db94011d3 1686 {
sahilmgandhi 18:6a4db94011d3 1687 break;
sahilmgandhi 18:6a4db94011d3 1688 }
sahilmgandhi 18:6a4db94011d3 1689 }
sahilmgandhi 18:6a4db94011d3 1690 while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
sahilmgandhi 18:6a4db94011d3 1691 }
sahilmgandhi 18:6a4db94011d3 1692
sahilmgandhi 18:6a4db94011d3 1693 /* Clear any pending Host interrupts */
sahilmgandhi 18:6a4db94011d3 1694 USBx_HOST->HAINT = 0xFFFFFFFFU;
sahilmgandhi 18:6a4db94011d3 1695 USBx->GINTSTS = 0xFFFFFFFFU;
sahilmgandhi 18:6a4db94011d3 1696 USB_EnableGlobalInt(USBx);
sahilmgandhi 18:6a4db94011d3 1697 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1698 }
sahilmgandhi 18:6a4db94011d3 1699 /**
sahilmgandhi 18:6a4db94011d3 1700 * @}
sahilmgandhi 18:6a4db94011d3 1701 */
sahilmgandhi 18:6a4db94011d3 1702 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
sahilmgandhi 18:6a4db94011d3 1703 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Rx ||
sahilmgandhi 18:6a4db94011d3 1704 STM32F412Vx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 1705 #endif /* defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) */
sahilmgandhi 18:6a4db94011d3 1706
sahilmgandhi 18:6a4db94011d3 1707 /**
sahilmgandhi 18:6a4db94011d3 1708 * @}
sahilmgandhi 18:6a4db94011d3 1709 */
sahilmgandhi 18:6a4db94011d3 1710
sahilmgandhi 18:6a4db94011d3 1711 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/