MacroRat
Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
| sahilmgandhi | 18:6a4db94011d3 | 3 | * @file stm32f4xx_ll_fsmc.h |
| sahilmgandhi | 18:6a4db94011d3 | 4 | * @author MCD Application Team |
| sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V1.5.0 |
| sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 06-May-2016 |
| sahilmgandhi | 18:6a4db94011d3 | 7 | * @brief Header file of FSMC HAL module. |
| sahilmgandhi | 18:6a4db94011d3 | 8 | ****************************************************************************** |
| sahilmgandhi | 18:6a4db94011d3 | 9 | * @attention |
| sahilmgandhi | 18:6a4db94011d3 | 10 | * |
| sahilmgandhi | 18:6a4db94011d3 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| sahilmgandhi | 18:6a4db94011d3 | 12 | * |
| sahilmgandhi | 18:6a4db94011d3 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| sahilmgandhi | 18:6a4db94011d3 | 14 | * are permitted provided that the following conditions are met: |
| sahilmgandhi | 18:6a4db94011d3 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| sahilmgandhi | 18:6a4db94011d3 | 16 | * this list of conditions and the following disclaimer. |
| sahilmgandhi | 18:6a4db94011d3 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| sahilmgandhi | 18:6a4db94011d3 | 18 | * this list of conditions and the following disclaimer in the documentation |
| sahilmgandhi | 18:6a4db94011d3 | 19 | * and/or other materials provided with the distribution. |
| sahilmgandhi | 18:6a4db94011d3 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| sahilmgandhi | 18:6a4db94011d3 | 21 | * may be used to endorse or promote products derived from this software |
| sahilmgandhi | 18:6a4db94011d3 | 22 | * without specific prior written permission. |
| sahilmgandhi | 18:6a4db94011d3 | 23 | * |
| sahilmgandhi | 18:6a4db94011d3 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| sahilmgandhi | 18:6a4db94011d3 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| sahilmgandhi | 18:6a4db94011d3 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| sahilmgandhi | 18:6a4db94011d3 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| sahilmgandhi | 18:6a4db94011d3 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| sahilmgandhi | 18:6a4db94011d3 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| sahilmgandhi | 18:6a4db94011d3 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| sahilmgandhi | 18:6a4db94011d3 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| sahilmgandhi | 18:6a4db94011d3 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| sahilmgandhi | 18:6a4db94011d3 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| sahilmgandhi | 18:6a4db94011d3 | 34 | * |
| sahilmgandhi | 18:6a4db94011d3 | 35 | ****************************************************************************** |
| sahilmgandhi | 18:6a4db94011d3 | 36 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 37 | |
| sahilmgandhi | 18:6a4db94011d3 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 39 | #ifndef __STM32F4xx_LL_FSMC_H |
| sahilmgandhi | 18:6a4db94011d3 | 40 | #define __STM32F4xx_LL_FSMC_H |
| sahilmgandhi | 18:6a4db94011d3 | 41 | |
| sahilmgandhi | 18:6a4db94011d3 | 42 | #ifdef __cplusplus |
| sahilmgandhi | 18:6a4db94011d3 | 43 | extern "C" { |
| sahilmgandhi | 18:6a4db94011d3 | 44 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 45 | |
| sahilmgandhi | 18:6a4db94011d3 | 46 | /* Includes ------------------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 47 | #include "stm32f4xx_hal_def.h" |
| sahilmgandhi | 18:6a4db94011d3 | 48 | |
| sahilmgandhi | 18:6a4db94011d3 | 49 | /** @addtogroup STM32F4xx_HAL_Driver |
| sahilmgandhi | 18:6a4db94011d3 | 50 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 51 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 52 | |
| sahilmgandhi | 18:6a4db94011d3 | 53 | /** @addtogroup FSMC_LL |
| sahilmgandhi | 18:6a4db94011d3 | 54 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 55 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 56 | |
| sahilmgandhi | 18:6a4db94011d3 | 57 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) |
| sahilmgandhi | 18:6a4db94011d3 | 58 | /* Private types -------------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 59 | /** @defgroup FSMC_LL_Private_Types FSMC Private Types |
| sahilmgandhi | 18:6a4db94011d3 | 60 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 61 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 62 | |
| sahilmgandhi | 18:6a4db94011d3 | 63 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 64 | * @brief FSMC NORSRAM Configuration Structure definition |
| sahilmgandhi | 18:6a4db94011d3 | 65 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 66 | typedef struct |
| sahilmgandhi | 18:6a4db94011d3 | 67 | { |
| sahilmgandhi | 18:6a4db94011d3 | 68 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| sahilmgandhi | 18:6a4db94011d3 | 69 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| sahilmgandhi | 18:6a4db94011d3 | 70 | |
| sahilmgandhi | 18:6a4db94011d3 | 71 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| sahilmgandhi | 18:6a4db94011d3 | 72 | multiplexed on the data bus or not. |
| sahilmgandhi | 18:6a4db94011d3 | 73 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| sahilmgandhi | 18:6a4db94011d3 | 74 | |
| sahilmgandhi | 18:6a4db94011d3 | 75 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| sahilmgandhi | 18:6a4db94011d3 | 76 | the corresponding memory device. |
| sahilmgandhi | 18:6a4db94011d3 | 77 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| sahilmgandhi | 18:6a4db94011d3 | 78 | |
| sahilmgandhi | 18:6a4db94011d3 | 79 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| sahilmgandhi | 18:6a4db94011d3 | 80 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| sahilmgandhi | 18:6a4db94011d3 | 81 | |
| sahilmgandhi | 18:6a4db94011d3 | 82 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| sahilmgandhi | 18:6a4db94011d3 | 83 | valid only with synchronous burst Flash memories. |
| sahilmgandhi | 18:6a4db94011d3 | 84 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 85 | |
| sahilmgandhi | 18:6a4db94011d3 | 86 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| sahilmgandhi | 18:6a4db94011d3 | 87 | the Flash memory in burst mode. |
| sahilmgandhi | 18:6a4db94011d3 | 88 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| sahilmgandhi | 18:6a4db94011d3 | 89 | |
| sahilmgandhi | 18:6a4db94011d3 | 90 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| sahilmgandhi | 18:6a4db94011d3 | 91 | memory, valid only when accessing Flash memories in burst mode. |
| sahilmgandhi | 18:6a4db94011d3 | 92 | This parameter can be a value of @ref FSMC_Wrap_Mode |
| sahilmgandhi | 18:6a4db94011d3 | 93 | This mode is available only for the STM32F405/407/4015/417xx devices */ |
| sahilmgandhi | 18:6a4db94011d3 | 94 | |
| sahilmgandhi | 18:6a4db94011d3 | 95 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| sahilmgandhi | 18:6a4db94011d3 | 96 | clock cycle before the wait state or during the wait state, |
| sahilmgandhi | 18:6a4db94011d3 | 97 | valid only when accessing memories in burst mode. |
| sahilmgandhi | 18:6a4db94011d3 | 98 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| sahilmgandhi | 18:6a4db94011d3 | 99 | |
| sahilmgandhi | 18:6a4db94011d3 | 100 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
| sahilmgandhi | 18:6a4db94011d3 | 101 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| sahilmgandhi | 18:6a4db94011d3 | 102 | |
| sahilmgandhi | 18:6a4db94011d3 | 103 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| sahilmgandhi | 18:6a4db94011d3 | 104 | signal, valid for Flash memory access in burst mode. |
| sahilmgandhi | 18:6a4db94011d3 | 105 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| sahilmgandhi | 18:6a4db94011d3 | 106 | |
| sahilmgandhi | 18:6a4db94011d3 | 107 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| sahilmgandhi | 18:6a4db94011d3 | 108 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 109 | |
| sahilmgandhi | 18:6a4db94011d3 | 110 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| sahilmgandhi | 18:6a4db94011d3 | 111 | valid only with asynchronous Flash memories. |
| sahilmgandhi | 18:6a4db94011d3 | 112 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| sahilmgandhi | 18:6a4db94011d3 | 113 | |
| sahilmgandhi | 18:6a4db94011d3 | 114 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| sahilmgandhi | 18:6a4db94011d3 | 115 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| sahilmgandhi | 18:6a4db94011d3 | 116 | |
| sahilmgandhi | 18:6a4db94011d3 | 117 | uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. |
| sahilmgandhi | 18:6a4db94011d3 | 118 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| sahilmgandhi | 18:6a4db94011d3 | 119 | through FMC_BCR2..4 registers. |
| sahilmgandhi | 18:6a4db94011d3 | 120 | This parameter can be a value of @ref FMC_Continous_Clock |
| sahilmgandhi | 18:6a4db94011d3 | 121 | This mode is available only for the STM32F412Vx/Zx/Rx devices */ |
| sahilmgandhi | 18:6a4db94011d3 | 122 | |
| sahilmgandhi | 18:6a4db94011d3 | 123 | uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. |
| sahilmgandhi | 18:6a4db94011d3 | 124 | This parameter is only enabled through the FMC_BCR1 register, and don't care |
| sahilmgandhi | 18:6a4db94011d3 | 125 | through FMC_BCR2..4 registers. |
| sahilmgandhi | 18:6a4db94011d3 | 126 | This parameter can be a value of @ref FMC_Write_FIFO |
| sahilmgandhi | 18:6a4db94011d3 | 127 | This mode is available only for the STM32F412Vx/Vx devices */ |
| sahilmgandhi | 18:6a4db94011d3 | 128 | |
| sahilmgandhi | 18:6a4db94011d3 | 129 | uint32_t PageSize; /*!< Specifies the memory page size. |
| sahilmgandhi | 18:6a4db94011d3 | 130 | This parameter can be a value of @ref FMC_Page_Size */ |
| sahilmgandhi | 18:6a4db94011d3 | 131 | }FSMC_NORSRAM_InitTypeDef; |
| sahilmgandhi | 18:6a4db94011d3 | 132 | |
| sahilmgandhi | 18:6a4db94011d3 | 133 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 134 | * @brief FSMC NORSRAM Timing parameters structure definition |
| sahilmgandhi | 18:6a4db94011d3 | 135 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 136 | typedef struct |
| sahilmgandhi | 18:6a4db94011d3 | 137 | { |
| sahilmgandhi | 18:6a4db94011d3 | 138 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| sahilmgandhi | 18:6a4db94011d3 | 139 | the duration of the address setup time. |
| sahilmgandhi | 18:6a4db94011d3 | 140 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| sahilmgandhi | 18:6a4db94011d3 | 141 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| sahilmgandhi | 18:6a4db94011d3 | 142 | |
| sahilmgandhi | 18:6a4db94011d3 | 143 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| sahilmgandhi | 18:6a4db94011d3 | 144 | the duration of the address hold time. |
| sahilmgandhi | 18:6a4db94011d3 | 145 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| sahilmgandhi | 18:6a4db94011d3 | 146 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| sahilmgandhi | 18:6a4db94011d3 | 147 | |
| sahilmgandhi | 18:6a4db94011d3 | 148 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| sahilmgandhi | 18:6a4db94011d3 | 149 | the duration of the data setup time. |
| sahilmgandhi | 18:6a4db94011d3 | 150 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| sahilmgandhi | 18:6a4db94011d3 | 151 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| sahilmgandhi | 18:6a4db94011d3 | 152 | NOR Flash memories. */ |
| sahilmgandhi | 18:6a4db94011d3 | 153 | |
| sahilmgandhi | 18:6a4db94011d3 | 154 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| sahilmgandhi | 18:6a4db94011d3 | 155 | the duration of the bus turnaround. |
| sahilmgandhi | 18:6a4db94011d3 | 156 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| sahilmgandhi | 18:6a4db94011d3 | 157 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| sahilmgandhi | 18:6a4db94011d3 | 158 | |
| sahilmgandhi | 18:6a4db94011d3 | 159 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| sahilmgandhi | 18:6a4db94011d3 | 160 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| sahilmgandhi | 18:6a4db94011d3 | 161 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| sahilmgandhi | 18:6a4db94011d3 | 162 | accesses. */ |
| sahilmgandhi | 18:6a4db94011d3 | 163 | |
| sahilmgandhi | 18:6a4db94011d3 | 164 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| sahilmgandhi | 18:6a4db94011d3 | 165 | to the memory before getting the first data. |
| sahilmgandhi | 18:6a4db94011d3 | 166 | The parameter value depends on the memory type as shown below: |
| sahilmgandhi | 18:6a4db94011d3 | 167 | - It must be set to 0 in case of a CRAM |
| sahilmgandhi | 18:6a4db94011d3 | 168 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| sahilmgandhi | 18:6a4db94011d3 | 169 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| sahilmgandhi | 18:6a4db94011d3 | 170 | with synchronous burst mode enable */ |
| sahilmgandhi | 18:6a4db94011d3 | 171 | |
| sahilmgandhi | 18:6a4db94011d3 | 172 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| sahilmgandhi | 18:6a4db94011d3 | 173 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| sahilmgandhi | 18:6a4db94011d3 | 174 | |
| sahilmgandhi | 18:6a4db94011d3 | 175 | }FSMC_NORSRAM_TimingTypeDef; |
| sahilmgandhi | 18:6a4db94011d3 | 176 | |
| sahilmgandhi | 18:6a4db94011d3 | 177 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 178 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 179 | * @brief FSMC NAND Configuration Structure definition |
| sahilmgandhi | 18:6a4db94011d3 | 180 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 181 | typedef struct |
| sahilmgandhi | 18:6a4db94011d3 | 182 | { |
| sahilmgandhi | 18:6a4db94011d3 | 183 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| sahilmgandhi | 18:6a4db94011d3 | 184 | This parameter can be a value of @ref FSMC_NAND_Bank */ |
| sahilmgandhi | 18:6a4db94011d3 | 185 | |
| sahilmgandhi | 18:6a4db94011d3 | 186 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
| sahilmgandhi | 18:6a4db94011d3 | 187 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| sahilmgandhi | 18:6a4db94011d3 | 188 | |
| sahilmgandhi | 18:6a4db94011d3 | 189 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| sahilmgandhi | 18:6a4db94011d3 | 190 | This parameter can be any value of @ref FSMC_NAND_Data_Width */ |
| sahilmgandhi | 18:6a4db94011d3 | 191 | |
| sahilmgandhi | 18:6a4db94011d3 | 192 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
| sahilmgandhi | 18:6a4db94011d3 | 193 | This parameter can be any value of @ref FSMC_ECC */ |
| sahilmgandhi | 18:6a4db94011d3 | 194 | |
| sahilmgandhi | 18:6a4db94011d3 | 195 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
| sahilmgandhi | 18:6a4db94011d3 | 196 | This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
| sahilmgandhi | 18:6a4db94011d3 | 197 | |
| sahilmgandhi | 18:6a4db94011d3 | 198 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| sahilmgandhi | 18:6a4db94011d3 | 199 | delay between CLE low and RE low. |
| sahilmgandhi | 18:6a4db94011d3 | 200 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| sahilmgandhi | 18:6a4db94011d3 | 201 | |
| sahilmgandhi | 18:6a4db94011d3 | 202 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| sahilmgandhi | 18:6a4db94011d3 | 203 | delay between ALE low and RE low. |
| sahilmgandhi | 18:6a4db94011d3 | 204 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| sahilmgandhi | 18:6a4db94011d3 | 205 | |
| sahilmgandhi | 18:6a4db94011d3 | 206 | }FSMC_NAND_InitTypeDef; |
| sahilmgandhi | 18:6a4db94011d3 | 207 | |
| sahilmgandhi | 18:6a4db94011d3 | 208 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 209 | * @brief FSMC NAND/PCCARD Timing parameters structure definition |
| sahilmgandhi | 18:6a4db94011d3 | 210 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 211 | typedef struct |
| sahilmgandhi | 18:6a4db94011d3 | 212 | { |
| sahilmgandhi | 18:6a4db94011d3 | 213 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| sahilmgandhi | 18:6a4db94011d3 | 214 | the command assertion for NAND-Flash read or write access |
| sahilmgandhi | 18:6a4db94011d3 | 215 | to common/Attribute or I/O memory space (depending on |
| sahilmgandhi | 18:6a4db94011d3 | 216 | the memory space timing to be configured). |
| sahilmgandhi | 18:6a4db94011d3 | 217 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| sahilmgandhi | 18:6a4db94011d3 | 218 | |
| sahilmgandhi | 18:6a4db94011d3 | 219 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
| sahilmgandhi | 18:6a4db94011d3 | 220 | command for NAND-Flash read or write access to |
| sahilmgandhi | 18:6a4db94011d3 | 221 | common/Attribute or I/O memory space (depending on the |
| sahilmgandhi | 18:6a4db94011d3 | 222 | memory space timing to be configured). |
| sahilmgandhi | 18:6a4db94011d3 | 223 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| sahilmgandhi | 18:6a4db94011d3 | 224 | |
| sahilmgandhi | 18:6a4db94011d3 | 225 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
| sahilmgandhi | 18:6a4db94011d3 | 226 | (and data for write access) after the command de-assertion |
| sahilmgandhi | 18:6a4db94011d3 | 227 | for NAND-Flash read or write access to common/Attribute |
| sahilmgandhi | 18:6a4db94011d3 | 228 | or I/O memory space (depending on the memory space timing |
| sahilmgandhi | 18:6a4db94011d3 | 229 | to be configured). |
| sahilmgandhi | 18:6a4db94011d3 | 230 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| sahilmgandhi | 18:6a4db94011d3 | 231 | |
| sahilmgandhi | 18:6a4db94011d3 | 232 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
| sahilmgandhi | 18:6a4db94011d3 | 233 | data bus is kept in HiZ after the start of a NAND-Flash |
| sahilmgandhi | 18:6a4db94011d3 | 234 | write access to common/Attribute or I/O memory space (depending |
| sahilmgandhi | 18:6a4db94011d3 | 235 | on the memory space timing to be configured). |
| sahilmgandhi | 18:6a4db94011d3 | 236 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| sahilmgandhi | 18:6a4db94011d3 | 237 | |
| sahilmgandhi | 18:6a4db94011d3 | 238 | }FSMC_NAND_PCC_TimingTypeDef; |
| sahilmgandhi | 18:6a4db94011d3 | 239 | |
| sahilmgandhi | 18:6a4db94011d3 | 240 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 241 | * @brief FSMC NAND Configuration Structure definition |
| sahilmgandhi | 18:6a4db94011d3 | 242 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 243 | typedef struct |
| sahilmgandhi | 18:6a4db94011d3 | 244 | { |
| sahilmgandhi | 18:6a4db94011d3 | 245 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
| sahilmgandhi | 18:6a4db94011d3 | 246 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| sahilmgandhi | 18:6a4db94011d3 | 247 | |
| sahilmgandhi | 18:6a4db94011d3 | 248 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| sahilmgandhi | 18:6a4db94011d3 | 249 | delay between CLE low and RE low. |
| sahilmgandhi | 18:6a4db94011d3 | 250 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| sahilmgandhi | 18:6a4db94011d3 | 251 | |
| sahilmgandhi | 18:6a4db94011d3 | 252 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
| sahilmgandhi | 18:6a4db94011d3 | 253 | delay between ALE low and RE low. |
| sahilmgandhi | 18:6a4db94011d3 | 254 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| sahilmgandhi | 18:6a4db94011d3 | 255 | |
| sahilmgandhi | 18:6a4db94011d3 | 256 | }FSMC_PCCARD_InitTypeDef; |
| sahilmgandhi | 18:6a4db94011d3 | 257 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 258 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 259 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 260 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 261 | |
| sahilmgandhi | 18:6a4db94011d3 | 262 | /* Private constants ---------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 263 | /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants |
| sahilmgandhi | 18:6a4db94011d3 | 264 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 265 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 266 | |
| sahilmgandhi | 18:6a4db94011d3 | 267 | /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller |
| sahilmgandhi | 18:6a4db94011d3 | 268 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 269 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 270 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
| sahilmgandhi | 18:6a4db94011d3 | 271 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 272 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 273 | #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 274 | #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) |
| sahilmgandhi | 18:6a4db94011d3 | 275 | #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) |
| sahilmgandhi | 18:6a4db94011d3 | 276 | #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) |
| sahilmgandhi | 18:6a4db94011d3 | 277 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 278 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 279 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 280 | |
| sahilmgandhi | 18:6a4db94011d3 | 281 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
| sahilmgandhi | 18:6a4db94011d3 | 282 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 283 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 284 | #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 285 | #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) |
| sahilmgandhi | 18:6a4db94011d3 | 286 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 287 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 288 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 289 | |
| sahilmgandhi | 18:6a4db94011d3 | 290 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
| sahilmgandhi | 18:6a4db94011d3 | 291 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 292 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 293 | #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 294 | #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) |
| sahilmgandhi | 18:6a4db94011d3 | 295 | #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) |
| sahilmgandhi | 18:6a4db94011d3 | 296 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 297 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 298 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 299 | |
| sahilmgandhi | 18:6a4db94011d3 | 300 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width |
| sahilmgandhi | 18:6a4db94011d3 | 301 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 302 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 303 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 304 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) |
| sahilmgandhi | 18:6a4db94011d3 | 305 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) |
| sahilmgandhi | 18:6a4db94011d3 | 306 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 307 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 308 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 309 | |
| sahilmgandhi | 18:6a4db94011d3 | 310 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
| sahilmgandhi | 18:6a4db94011d3 | 311 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 312 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 313 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) |
| sahilmgandhi | 18:6a4db94011d3 | 314 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 315 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 316 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 317 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 318 | |
| sahilmgandhi | 18:6a4db94011d3 | 319 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
| sahilmgandhi | 18:6a4db94011d3 | 320 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 321 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 322 | #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 323 | #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) |
| sahilmgandhi | 18:6a4db94011d3 | 324 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 325 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 326 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 327 | |
| sahilmgandhi | 18:6a4db94011d3 | 328 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
| sahilmgandhi | 18:6a4db94011d3 | 329 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 330 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 331 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 332 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) |
| sahilmgandhi | 18:6a4db94011d3 | 333 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 334 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 335 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 336 | |
| sahilmgandhi | 18:6a4db94011d3 | 337 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
| sahilmgandhi | 18:6a4db94011d3 | 338 | * @note These values are available only for the STM32F405/415/407/417xx devices. |
| sahilmgandhi | 18:6a4db94011d3 | 339 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 340 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 341 | #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 342 | #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U) |
| sahilmgandhi | 18:6a4db94011d3 | 343 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 344 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 345 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 346 | |
| sahilmgandhi | 18:6a4db94011d3 | 347 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
| sahilmgandhi | 18:6a4db94011d3 | 348 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 349 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 350 | #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 351 | #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) |
| sahilmgandhi | 18:6a4db94011d3 | 352 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 353 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 354 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 355 | |
| sahilmgandhi | 18:6a4db94011d3 | 356 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
| sahilmgandhi | 18:6a4db94011d3 | 357 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 358 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 359 | #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 360 | #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) |
| sahilmgandhi | 18:6a4db94011d3 | 361 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 362 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 363 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 364 | |
| sahilmgandhi | 18:6a4db94011d3 | 365 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
| sahilmgandhi | 18:6a4db94011d3 | 366 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 367 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 368 | #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 369 | #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) |
| sahilmgandhi | 18:6a4db94011d3 | 370 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 371 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 372 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 373 | |
| sahilmgandhi | 18:6a4db94011d3 | 374 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
| sahilmgandhi | 18:6a4db94011d3 | 375 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 376 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 377 | #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 378 | #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) |
| sahilmgandhi | 18:6a4db94011d3 | 379 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 380 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 381 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 382 | |
| sahilmgandhi | 18:6a4db94011d3 | 383 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
| sahilmgandhi | 18:6a4db94011d3 | 384 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 385 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 386 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 387 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) |
| sahilmgandhi | 18:6a4db94011d3 | 388 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 389 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 390 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 391 | |
| sahilmgandhi | 18:6a4db94011d3 | 392 | /** @defgroup FSMC_Page_Size FSMC Page Size |
| sahilmgandhi | 18:6a4db94011d3 | 393 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 394 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 395 | #define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 396 | #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0) |
| sahilmgandhi | 18:6a4db94011d3 | 397 | #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1) |
| sahilmgandhi | 18:6a4db94011d3 | 398 | #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1)) |
| sahilmgandhi | 18:6a4db94011d3 | 399 | #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2) |
| sahilmgandhi | 18:6a4db94011d3 | 400 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 401 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 402 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 403 | |
| sahilmgandhi | 18:6a4db94011d3 | 404 | /** @defgroup FSMC_Write_FIFO FSMC Write FIFO |
| sahilmgandhi | 18:6a4db94011d3 | 405 | * @note These values are available only for the STM32F412Vx/Zx/Rx devices. |
| sahilmgandhi | 18:6a4db94011d3 | 406 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 407 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 408 | #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS) |
| sahilmgandhi | 18:6a4db94011d3 | 409 | #define FSMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 410 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 411 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 412 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 413 | |
| sahilmgandhi | 18:6a4db94011d3 | 414 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
| sahilmgandhi | 18:6a4db94011d3 | 415 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 416 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 417 | #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 418 | #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) |
| sahilmgandhi | 18:6a4db94011d3 | 419 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 420 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 421 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 422 | |
| sahilmgandhi | 18:6a4db94011d3 | 423 | /** @defgroup FSMC_Continous_Clock FSMC Continous Clock |
| sahilmgandhi | 18:6a4db94011d3 | 424 | * @note These values are available only for the STM32F412Vx/Zx/Rx devices. |
| sahilmgandhi | 18:6a4db94011d3 | 425 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 426 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 427 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 428 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) |
| sahilmgandhi | 18:6a4db94011d3 | 429 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 430 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 431 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 432 | |
| sahilmgandhi | 18:6a4db94011d3 | 433 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
| sahilmgandhi | 18:6a4db94011d3 | 434 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 435 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 436 | #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 437 | #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 438 | #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 439 | #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 440 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 441 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 442 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 443 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 444 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 445 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 446 | |
| sahilmgandhi | 18:6a4db94011d3 | 447 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 448 | /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller |
| sahilmgandhi | 18:6a4db94011d3 | 449 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 450 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 451 | /** @defgroup FSMC_NAND_Bank FSMC NAND Bank |
| sahilmgandhi | 18:6a4db94011d3 | 452 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 453 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 454 | #define FSMC_NAND_BANK2 ((uint32_t)0x00000010U) |
| sahilmgandhi | 18:6a4db94011d3 | 455 | #define FSMC_NAND_BANK3 ((uint32_t)0x00000100U) |
| sahilmgandhi | 18:6a4db94011d3 | 456 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 457 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 458 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 459 | |
| sahilmgandhi | 18:6a4db94011d3 | 460 | /** @defgroup FSMC_Wait_feature FSMC Wait feature |
| sahilmgandhi | 18:6a4db94011d3 | 461 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 462 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 463 | #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 464 | #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) |
| sahilmgandhi | 18:6a4db94011d3 | 465 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 466 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 467 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 468 | |
| sahilmgandhi | 18:6a4db94011d3 | 469 | /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type |
| sahilmgandhi | 18:6a4db94011d3 | 470 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 471 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 472 | #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 473 | #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) |
| sahilmgandhi | 18:6a4db94011d3 | 474 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 475 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 476 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 477 | |
| sahilmgandhi | 18:6a4db94011d3 | 478 | /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width |
| sahilmgandhi | 18:6a4db94011d3 | 479 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 480 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 481 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 482 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) |
| sahilmgandhi | 18:6a4db94011d3 | 483 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 484 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 485 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 486 | |
| sahilmgandhi | 18:6a4db94011d3 | 487 | /** @defgroup FSMC_ECC FSMC ECC |
| sahilmgandhi | 18:6a4db94011d3 | 488 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 489 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 490 | #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 491 | #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) |
| sahilmgandhi | 18:6a4db94011d3 | 492 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 493 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 494 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 495 | |
| sahilmgandhi | 18:6a4db94011d3 | 496 | /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size |
| sahilmgandhi | 18:6a4db94011d3 | 497 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 498 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 499 | #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) |
| sahilmgandhi | 18:6a4db94011d3 | 500 | #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) |
| sahilmgandhi | 18:6a4db94011d3 | 501 | #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) |
| sahilmgandhi | 18:6a4db94011d3 | 502 | #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) |
| sahilmgandhi | 18:6a4db94011d3 | 503 | #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) |
| sahilmgandhi | 18:6a4db94011d3 | 504 | #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) |
| sahilmgandhi | 18:6a4db94011d3 | 505 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 506 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 507 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 508 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 509 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 510 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 511 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 512 | |
| sahilmgandhi | 18:6a4db94011d3 | 513 | /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition |
| sahilmgandhi | 18:6a4db94011d3 | 514 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 515 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 516 | #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U) |
| sahilmgandhi | 18:6a4db94011d3 | 517 | #define FSMC_IT_LEVEL ((uint32_t)0x00000010U) |
| sahilmgandhi | 18:6a4db94011d3 | 518 | #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) |
| sahilmgandhi | 18:6a4db94011d3 | 519 | #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U) |
| sahilmgandhi | 18:6a4db94011d3 | 520 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 521 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 522 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 523 | |
| sahilmgandhi | 18:6a4db94011d3 | 524 | /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition |
| sahilmgandhi | 18:6a4db94011d3 | 525 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 526 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 527 | #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) |
| sahilmgandhi | 18:6a4db94011d3 | 528 | #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U) |
| sahilmgandhi | 18:6a4db94011d3 | 529 | #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) |
| sahilmgandhi | 18:6a4db94011d3 | 530 | #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U) |
| sahilmgandhi | 18:6a4db94011d3 | 531 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 532 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 533 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 534 | |
| sahilmgandhi | 18:6a4db94011d3 | 535 | /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition |
| sahilmgandhi | 18:6a4db94011d3 | 536 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 537 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 538 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 539 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 540 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 541 | #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 542 | #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 543 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 544 | |
| sahilmgandhi | 18:6a4db94011d3 | 545 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| sahilmgandhi | 18:6a4db94011d3 | 546 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| sahilmgandhi | 18:6a4db94011d3 | 547 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 548 | #define FSMC_NAND_DEVICE FSMC_Bank2_3 |
| sahilmgandhi | 18:6a4db94011d3 | 549 | #define FSMC_PCCARD_DEVICE FSMC_Bank4 |
| sahilmgandhi | 18:6a4db94011d3 | 550 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 551 | |
| sahilmgandhi | 18:6a4db94011d3 | 552 | #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8 |
| sahilmgandhi | 18:6a4db94011d3 | 553 | #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16 |
| sahilmgandhi | 18:6a4db94011d3 | 554 | #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32 |
| sahilmgandhi | 18:6a4db94011d3 | 555 | |
| sahilmgandhi | 18:6a4db94011d3 | 556 | #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 557 | #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 558 | #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 559 | #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 560 | |
| sahilmgandhi | 18:6a4db94011d3 | 561 | #define FMC_NORSRAM_Init FSMC_NORSRAM_Init |
| sahilmgandhi | 18:6a4db94011d3 | 562 | #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init |
| sahilmgandhi | 18:6a4db94011d3 | 563 | #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init |
| sahilmgandhi | 18:6a4db94011d3 | 564 | #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit |
| sahilmgandhi | 18:6a4db94011d3 | 565 | #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable |
| sahilmgandhi | 18:6a4db94011d3 | 566 | #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable |
| sahilmgandhi | 18:6a4db94011d3 | 567 | |
| sahilmgandhi | 18:6a4db94011d3 | 568 | #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE |
| sahilmgandhi | 18:6a4db94011d3 | 569 | #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE |
| sahilmgandhi | 18:6a4db94011d3 | 570 | |
| sahilmgandhi | 18:6a4db94011d3 | 571 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 572 | #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 573 | #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 574 | #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 575 | |
| sahilmgandhi | 18:6a4db94011d3 | 576 | #define FMC_NAND_Init FSMC_NAND_Init |
| sahilmgandhi | 18:6a4db94011d3 | 577 | #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init |
| sahilmgandhi | 18:6a4db94011d3 | 578 | #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init |
| sahilmgandhi | 18:6a4db94011d3 | 579 | #define FMC_NAND_DeInit FSMC_NAND_DeInit |
| sahilmgandhi | 18:6a4db94011d3 | 580 | #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable |
| sahilmgandhi | 18:6a4db94011d3 | 581 | #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable |
| sahilmgandhi | 18:6a4db94011d3 | 582 | #define FMC_NAND_GetECC FSMC_NAND_GetECC |
| sahilmgandhi | 18:6a4db94011d3 | 583 | #define FMC_PCCARD_Init FSMC_PCCARD_Init |
| sahilmgandhi | 18:6a4db94011d3 | 584 | #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init |
| sahilmgandhi | 18:6a4db94011d3 | 585 | #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init |
| sahilmgandhi | 18:6a4db94011d3 | 586 | #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init |
| sahilmgandhi | 18:6a4db94011d3 | 587 | #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit |
| sahilmgandhi | 18:6a4db94011d3 | 588 | |
| sahilmgandhi | 18:6a4db94011d3 | 589 | #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE |
| sahilmgandhi | 18:6a4db94011d3 | 590 | #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE |
| sahilmgandhi | 18:6a4db94011d3 | 591 | #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE |
| sahilmgandhi | 18:6a4db94011d3 | 592 | #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE |
| sahilmgandhi | 18:6a4db94011d3 | 593 | #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT |
| sahilmgandhi | 18:6a4db94011d3 | 594 | #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT |
| sahilmgandhi | 18:6a4db94011d3 | 595 | #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG |
| sahilmgandhi | 18:6a4db94011d3 | 596 | #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG |
| sahilmgandhi | 18:6a4db94011d3 | 597 | #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT |
| sahilmgandhi | 18:6a4db94011d3 | 598 | #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT |
| sahilmgandhi | 18:6a4db94011d3 | 599 | #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG |
| sahilmgandhi | 18:6a4db94011d3 | 600 | #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG |
| sahilmgandhi | 18:6a4db94011d3 | 601 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 602 | |
| sahilmgandhi | 18:6a4db94011d3 | 603 | #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 604 | #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 605 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 606 | #define FMC_NAND_TypeDef FSMC_NAND_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 607 | #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef |
| sahilmgandhi | 18:6a4db94011d3 | 608 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 609 | |
| sahilmgandhi | 18:6a4db94011d3 | 610 | #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE |
| sahilmgandhi | 18:6a4db94011d3 | 611 | #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE |
| sahilmgandhi | 18:6a4db94011d3 | 612 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 613 | #define FMC_NAND_DEVICE FSMC_NAND_DEVICE |
| sahilmgandhi | 18:6a4db94011d3 | 614 | #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE |
| sahilmgandhi | 18:6a4db94011d3 | 615 | |
| sahilmgandhi | 18:6a4db94011d3 | 616 | #define FMC_NAND_BANK2 FSMC_NAND_BANK2 |
| sahilmgandhi | 18:6a4db94011d3 | 617 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 618 | |
| sahilmgandhi | 18:6a4db94011d3 | 619 | #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 |
| sahilmgandhi | 18:6a4db94011d3 | 620 | #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 |
| sahilmgandhi | 18:6a4db94011d3 | 621 | #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 |
| sahilmgandhi | 18:6a4db94011d3 | 622 | |
| sahilmgandhi | 18:6a4db94011d3 | 623 | #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE |
| sahilmgandhi | 18:6a4db94011d3 | 624 | #define FMC_IT_LEVEL FSMC_IT_LEVEL |
| sahilmgandhi | 18:6a4db94011d3 | 625 | #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE |
| sahilmgandhi | 18:6a4db94011d3 | 626 | #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR |
| sahilmgandhi | 18:6a4db94011d3 | 627 | |
| sahilmgandhi | 18:6a4db94011d3 | 628 | #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE |
| sahilmgandhi | 18:6a4db94011d3 | 629 | #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL |
| sahilmgandhi | 18:6a4db94011d3 | 630 | #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE |
| sahilmgandhi | 18:6a4db94011d3 | 631 | #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT |
| sahilmgandhi | 18:6a4db94011d3 | 632 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 633 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 634 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 635 | |
| sahilmgandhi | 18:6a4db94011d3 | 636 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 637 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 638 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 639 | |
| sahilmgandhi | 18:6a4db94011d3 | 640 | /* Private macro -------------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 641 | /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros |
| sahilmgandhi | 18:6a4db94011d3 | 642 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 643 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 644 | |
| sahilmgandhi | 18:6a4db94011d3 | 645 | /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros |
| sahilmgandhi | 18:6a4db94011d3 | 646 | * @brief macros to handle NOR device enable/disable and read/write operations |
| sahilmgandhi | 18:6a4db94011d3 | 647 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 648 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 649 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 650 | * @brief Enable the NORSRAM device access. |
| sahilmgandhi | 18:6a4db94011d3 | 651 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| sahilmgandhi | 18:6a4db94011d3 | 652 | * @param __BANK__: FSMC_NORSRAM Bank |
| sahilmgandhi | 18:6a4db94011d3 | 653 | * @retval none |
| sahilmgandhi | 18:6a4db94011d3 | 654 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 655 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) |
| sahilmgandhi | 18:6a4db94011d3 | 656 | |
| sahilmgandhi | 18:6a4db94011d3 | 657 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 658 | * @brief Disable the NORSRAM device access. |
| sahilmgandhi | 18:6a4db94011d3 | 659 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| sahilmgandhi | 18:6a4db94011d3 | 660 | * @param __BANK__: FSMC_NORSRAM Bank |
| sahilmgandhi | 18:6a4db94011d3 | 661 | * @retval none |
| sahilmgandhi | 18:6a4db94011d3 | 662 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 663 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) |
| sahilmgandhi | 18:6a4db94011d3 | 664 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 665 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 666 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 667 | |
| sahilmgandhi | 18:6a4db94011d3 | 668 | /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros |
| sahilmgandhi | 18:6a4db94011d3 | 669 | * @brief macros to handle NAND device enable/disable |
| sahilmgandhi | 18:6a4db94011d3 | 670 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 671 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 672 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 673 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 674 | * @brief Enable the NAND device access. |
| sahilmgandhi | 18:6a4db94011d3 | 675 | * @param __INSTANCE__: FSMC_NAND Instance |
| sahilmgandhi | 18:6a4db94011d3 | 676 | * @param __BANK__: FSMC_NAND Bank |
| sahilmgandhi | 18:6a4db94011d3 | 677 | * @retval none |
| sahilmgandhi | 18:6a4db94011d3 | 678 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 679 | #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ |
| sahilmgandhi | 18:6a4db94011d3 | 680 | ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) |
| sahilmgandhi | 18:6a4db94011d3 | 681 | |
| sahilmgandhi | 18:6a4db94011d3 | 682 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 683 | * @brief Disable the NAND device access. |
| sahilmgandhi | 18:6a4db94011d3 | 684 | * @param __INSTANCE__: FSMC_NAND Instance |
| sahilmgandhi | 18:6a4db94011d3 | 685 | * @param __BANK__: FSMC_NAND Bank |
| sahilmgandhi | 18:6a4db94011d3 | 686 | * @retval none |
| sahilmgandhi | 18:6a4db94011d3 | 687 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 688 | #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ |
| sahilmgandhi | 18:6a4db94011d3 | 689 | ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN)) |
| sahilmgandhi | 18:6a4db94011d3 | 690 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 691 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 692 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 693 | |
| sahilmgandhi | 18:6a4db94011d3 | 694 | /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros |
| sahilmgandhi | 18:6a4db94011d3 | 695 | * @brief macros to handle SRAM read/write operations |
| sahilmgandhi | 18:6a4db94011d3 | 696 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 697 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 698 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 699 | * @brief Enable the PCCARD device access. |
| sahilmgandhi | 18:6a4db94011d3 | 700 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| sahilmgandhi | 18:6a4db94011d3 | 701 | * @retval none |
| sahilmgandhi | 18:6a4db94011d3 | 702 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 703 | #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) |
| sahilmgandhi | 18:6a4db94011d3 | 704 | |
| sahilmgandhi | 18:6a4db94011d3 | 705 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 706 | * @brief Disable the PCCARD device access. |
| sahilmgandhi | 18:6a4db94011d3 | 707 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| sahilmgandhi | 18:6a4db94011d3 | 708 | * @retval none |
| sahilmgandhi | 18:6a4db94011d3 | 709 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 710 | #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) |
| sahilmgandhi | 18:6a4db94011d3 | 711 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 712 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 713 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 714 | |
| sahilmgandhi | 18:6a4db94011d3 | 715 | /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros |
| sahilmgandhi | 18:6a4db94011d3 | 716 | * @brief macros to handle FSMC flags and interrupts |
| sahilmgandhi | 18:6a4db94011d3 | 717 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 718 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 719 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 720 | * @brief Enable the NAND device interrupt. |
| sahilmgandhi | 18:6a4db94011d3 | 721 | * @param __INSTANCE__: FSMC_NAND Instance |
| sahilmgandhi | 18:6a4db94011d3 | 722 | * @param __BANK__: FSMC_NAND Bank |
| sahilmgandhi | 18:6a4db94011d3 | 723 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| sahilmgandhi | 18:6a4db94011d3 | 724 | * This parameter can be any combination of the following values: |
| sahilmgandhi | 18:6a4db94011d3 | 725 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| sahilmgandhi | 18:6a4db94011d3 | 726 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| sahilmgandhi | 18:6a4db94011d3 | 727 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| sahilmgandhi | 18:6a4db94011d3 | 728 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 729 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 730 | #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ |
| sahilmgandhi | 18:6a4db94011d3 | 731 | ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) |
| sahilmgandhi | 18:6a4db94011d3 | 732 | |
| sahilmgandhi | 18:6a4db94011d3 | 733 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 734 | * @brief Disable the NAND device interrupt. |
| sahilmgandhi | 18:6a4db94011d3 | 735 | * @param __INSTANCE__: FSMC_NAND Instance |
| sahilmgandhi | 18:6a4db94011d3 | 736 | * @param __BANK__: FSMC_NAND Bank |
| sahilmgandhi | 18:6a4db94011d3 | 737 | * @param __INTERRUPT__: FSMC_NAND interrupt |
| sahilmgandhi | 18:6a4db94011d3 | 738 | * This parameter can be any combination of the following values: |
| sahilmgandhi | 18:6a4db94011d3 | 739 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| sahilmgandhi | 18:6a4db94011d3 | 740 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| sahilmgandhi | 18:6a4db94011d3 | 741 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| sahilmgandhi | 18:6a4db94011d3 | 742 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 743 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 744 | #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ |
| sahilmgandhi | 18:6a4db94011d3 | 745 | ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) |
| sahilmgandhi | 18:6a4db94011d3 | 746 | |
| sahilmgandhi | 18:6a4db94011d3 | 747 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 748 | * @brief Get flag status of the NAND device. |
| sahilmgandhi | 18:6a4db94011d3 | 749 | * @param __INSTANCE__: FSMC_NAND Instance |
| sahilmgandhi | 18:6a4db94011d3 | 750 | * @param __BANK__ : FSMC_NAND Bank |
| sahilmgandhi | 18:6a4db94011d3 | 751 | * @param __FLAG__ : FSMC_NAND flag |
| sahilmgandhi | 18:6a4db94011d3 | 752 | * This parameter can be any combination of the following values: |
| sahilmgandhi | 18:6a4db94011d3 | 753 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 754 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 755 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 756 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| sahilmgandhi | 18:6a4db94011d3 | 757 | * @retval The state of FLAG (SET or RESET). |
| sahilmgandhi | 18:6a4db94011d3 | 758 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 759 | #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
| sahilmgandhi | 18:6a4db94011d3 | 760 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
| sahilmgandhi | 18:6a4db94011d3 | 761 | |
| sahilmgandhi | 18:6a4db94011d3 | 762 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 763 | * @brief Clear flag status of the NAND device. |
| sahilmgandhi | 18:6a4db94011d3 | 764 | * @param __INSTANCE__: FSMC_NAND Instance |
| sahilmgandhi | 18:6a4db94011d3 | 765 | * @param __BANK__: FSMC_NAND Bank |
| sahilmgandhi | 18:6a4db94011d3 | 766 | * @param __FLAG__: FSMC_NAND flag |
| sahilmgandhi | 18:6a4db94011d3 | 767 | * This parameter can be any combination of the following values: |
| sahilmgandhi | 18:6a4db94011d3 | 768 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 769 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 770 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 771 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| sahilmgandhi | 18:6a4db94011d3 | 772 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 773 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 774 | #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ |
| sahilmgandhi | 18:6a4db94011d3 | 775 | ((__INSTANCE__)->SR3 &= ~(__FLAG__))) |
| sahilmgandhi | 18:6a4db94011d3 | 776 | |
| sahilmgandhi | 18:6a4db94011d3 | 777 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 778 | * @brief Enable the PCCARD device interrupt. |
| sahilmgandhi | 18:6a4db94011d3 | 779 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| sahilmgandhi | 18:6a4db94011d3 | 780 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| sahilmgandhi | 18:6a4db94011d3 | 781 | * This parameter can be any combination of the following values: |
| sahilmgandhi | 18:6a4db94011d3 | 782 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| sahilmgandhi | 18:6a4db94011d3 | 783 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| sahilmgandhi | 18:6a4db94011d3 | 784 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| sahilmgandhi | 18:6a4db94011d3 | 785 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 786 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 787 | #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) |
| sahilmgandhi | 18:6a4db94011d3 | 788 | |
| sahilmgandhi | 18:6a4db94011d3 | 789 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 790 | * @brief Disable the PCCARD device interrupt. |
| sahilmgandhi | 18:6a4db94011d3 | 791 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| sahilmgandhi | 18:6a4db94011d3 | 792 | * @param __INTERRUPT__: FSMC_PCCARD interrupt |
| sahilmgandhi | 18:6a4db94011d3 | 793 | * This parameter can be any combination of the following values: |
| sahilmgandhi | 18:6a4db94011d3 | 794 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| sahilmgandhi | 18:6a4db94011d3 | 795 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| sahilmgandhi | 18:6a4db94011d3 | 796 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| sahilmgandhi | 18:6a4db94011d3 | 797 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 798 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 799 | #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) |
| sahilmgandhi | 18:6a4db94011d3 | 800 | |
| sahilmgandhi | 18:6a4db94011d3 | 801 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 802 | * @brief Get flag status of the PCCARD device. |
| sahilmgandhi | 18:6a4db94011d3 | 803 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| sahilmgandhi | 18:6a4db94011d3 | 804 | * @param __FLAG__: FSMC_PCCARD flag |
| sahilmgandhi | 18:6a4db94011d3 | 805 | * This parameter can be any combination of the following values: |
| sahilmgandhi | 18:6a4db94011d3 | 806 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 807 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 808 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 809 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| sahilmgandhi | 18:6a4db94011d3 | 810 | * @retval The state of FLAG (SET or RESET). |
| sahilmgandhi | 18:6a4db94011d3 | 811 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 812 | #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
| sahilmgandhi | 18:6a4db94011d3 | 813 | |
| sahilmgandhi | 18:6a4db94011d3 | 814 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 815 | * @brief Clear flag status of the PCCARD device. |
| sahilmgandhi | 18:6a4db94011d3 | 816 | * @param __INSTANCE__: FSMC_PCCARD Instance |
| sahilmgandhi | 18:6a4db94011d3 | 817 | * @param __FLAG__: FSMC_PCCARD flag |
| sahilmgandhi | 18:6a4db94011d3 | 818 | * This parameter can be any combination of the following values: |
| sahilmgandhi | 18:6a4db94011d3 | 819 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 820 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 821 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| sahilmgandhi | 18:6a4db94011d3 | 822 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| sahilmgandhi | 18:6a4db94011d3 | 823 | * @retval None |
| sahilmgandhi | 18:6a4db94011d3 | 824 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 825 | #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) |
| sahilmgandhi | 18:6a4db94011d3 | 826 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 827 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 828 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 829 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 830 | |
| sahilmgandhi | 18:6a4db94011d3 | 831 | /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros |
| sahilmgandhi | 18:6a4db94011d3 | 832 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 833 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 834 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 835 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 836 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 837 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
| sahilmgandhi | 18:6a4db94011d3 | 838 | |
| sahilmgandhi | 18:6a4db94011d3 | 839 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 840 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 841 | |
| sahilmgandhi | 18:6a4db94011d3 | 842 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 843 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| sahilmgandhi | 18:6a4db94011d3 | 844 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
| sahilmgandhi | 18:6a4db94011d3 | 845 | |
| sahilmgandhi | 18:6a4db94011d3 | 846 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 847 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 848 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| sahilmgandhi | 18:6a4db94011d3 | 849 | |
| sahilmgandhi | 18:6a4db94011d3 | 850 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 851 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 852 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 853 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
| sahilmgandhi | 18:6a4db94011d3 | 854 | |
| sahilmgandhi | 18:6a4db94011d3 | 855 | #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 856 | ((BANK) == FSMC_NAND_BANK3)) |
| sahilmgandhi | 18:6a4db94011d3 | 857 | |
| sahilmgandhi | 18:6a4db94011d3 | 858 | #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 859 | ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 860 | |
| sahilmgandhi | 18:6a4db94011d3 | 861 | #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 862 | ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
| sahilmgandhi | 18:6a4db94011d3 | 863 | |
| sahilmgandhi | 18:6a4db94011d3 | 864 | #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 865 | ((STATE) == FSMC_NAND_ECC_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 866 | |
| sahilmgandhi | 18:6a4db94011d3 | 867 | #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 868 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 869 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 870 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 871 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 872 | ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| sahilmgandhi | 18:6a4db94011d3 | 873 | |
| sahilmgandhi | 18:6a4db94011d3 | 874 | #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U) |
| sahilmgandhi | 18:6a4db94011d3 | 875 | |
| sahilmgandhi | 18:6a4db94011d3 | 876 | #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U) |
| sahilmgandhi | 18:6a4db94011d3 | 877 | |
| sahilmgandhi | 18:6a4db94011d3 | 878 | #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U) |
| sahilmgandhi | 18:6a4db94011d3 | 879 | |
| sahilmgandhi | 18:6a4db94011d3 | 880 | #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U) |
| sahilmgandhi | 18:6a4db94011d3 | 881 | |
| sahilmgandhi | 18:6a4db94011d3 | 882 | #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U) |
| sahilmgandhi | 18:6a4db94011d3 | 883 | |
| sahilmgandhi | 18:6a4db94011d3 | 884 | #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U) |
| sahilmgandhi | 18:6a4db94011d3 | 885 | |
| sahilmgandhi | 18:6a4db94011d3 | 886 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
| sahilmgandhi | 18:6a4db94011d3 | 887 | |
| sahilmgandhi | 18:6a4db94011d3 | 888 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| sahilmgandhi | 18:6a4db94011d3 | 889 | |
| sahilmgandhi | 18:6a4db94011d3 | 890 | #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) |
| sahilmgandhi | 18:6a4db94011d3 | 891 | |
| sahilmgandhi | 18:6a4db94011d3 | 892 | #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) |
| sahilmgandhi | 18:6a4db94011d3 | 893 | |
| sahilmgandhi | 18:6a4db94011d3 | 894 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 895 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 896 | |
| sahilmgandhi | 18:6a4db94011d3 | 897 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 898 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| sahilmgandhi | 18:6a4db94011d3 | 899 | |
| sahilmgandhi | 18:6a4db94011d3 | 900 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 901 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 902 | |
| sahilmgandhi | 18:6a4db94011d3 | 903 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 904 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
| sahilmgandhi | 18:6a4db94011d3 | 905 | |
| sahilmgandhi | 18:6a4db94011d3 | 906 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 907 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 908 | |
| sahilmgandhi | 18:6a4db94011d3 | 909 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 910 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 911 | |
| sahilmgandhi | 18:6a4db94011d3 | 912 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 913 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 914 | |
| sahilmgandhi | 18:6a4db94011d3 | 915 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 916 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 917 | |
| sahilmgandhi | 18:6a4db94011d3 | 918 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) |
| sahilmgandhi | 18:6a4db94011d3 | 919 | |
| sahilmgandhi | 18:6a4db94011d3 | 920 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 921 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 922 | |
| sahilmgandhi | 18:6a4db94011d3 | 923 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) |
| sahilmgandhi | 18:6a4db94011d3 | 924 | |
| sahilmgandhi | 18:6a4db94011d3 | 925 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) |
| sahilmgandhi | 18:6a4db94011d3 | 926 | |
| sahilmgandhi | 18:6a4db94011d3 | 927 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) |
| sahilmgandhi | 18:6a4db94011d3 | 928 | |
| sahilmgandhi | 18:6a4db94011d3 | 929 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) |
| sahilmgandhi | 18:6a4db94011d3 | 930 | |
| sahilmgandhi | 18:6a4db94011d3 | 931 | #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 932 | ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| sahilmgandhi | 18:6a4db94011d3 | 933 | |
| sahilmgandhi | 18:6a4db94011d3 | 934 | #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) |
| sahilmgandhi | 18:6a4db94011d3 | 935 | |
| sahilmgandhi | 18:6a4db94011d3 | 936 | #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 937 | ((SIZE) == FSMC_PAGE_SIZE_128) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 938 | ((SIZE) == FSMC_PAGE_SIZE_256) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 939 | ((SIZE) == FSMC_PAGE_SIZE_1024)) |
| sahilmgandhi | 18:6a4db94011d3 | 940 | |
| sahilmgandhi | 18:6a4db94011d3 | 941 | #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \ |
| sahilmgandhi | 18:6a4db94011d3 | 942 | ((FIFO) == FSMC_WRITE_FIFO_ENABLE)) |
| sahilmgandhi | 18:6a4db94011d3 | 943 | |
| sahilmgandhi | 18:6a4db94011d3 | 944 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 945 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 946 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 947 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 948 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 949 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 950 | |
| sahilmgandhi | 18:6a4db94011d3 | 951 | /* Private functions ---------------------------------------------------------*/ |
| sahilmgandhi | 18:6a4db94011d3 | 952 | /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions |
| sahilmgandhi | 18:6a4db94011d3 | 953 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 954 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 955 | |
| sahilmgandhi | 18:6a4db94011d3 | 956 | /** @defgroup FSMC_LL_NORSRAM NOR SRAM |
| sahilmgandhi | 18:6a4db94011d3 | 957 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 958 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 959 | |
| sahilmgandhi | 18:6a4db94011d3 | 960 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions |
| sahilmgandhi | 18:6a4db94011d3 | 961 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 962 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 963 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); |
| sahilmgandhi | 18:6a4db94011d3 | 964 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 965 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| sahilmgandhi | 18:6a4db94011d3 | 966 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 967 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 968 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 969 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 970 | |
| sahilmgandhi | 18:6a4db94011d3 | 971 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions |
| sahilmgandhi | 18:6a4db94011d3 | 972 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 973 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 974 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 975 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 976 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 977 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 978 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 979 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 980 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 981 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 982 | |
| sahilmgandhi | 18:6a4db94011d3 | 983 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
| sahilmgandhi | 18:6a4db94011d3 | 984 | /** @defgroup FSMC_LL_NAND NAND |
| sahilmgandhi | 18:6a4db94011d3 | 985 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 986 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 987 | /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions |
| sahilmgandhi | 18:6a4db94011d3 | 988 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 989 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 990 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); |
| sahilmgandhi | 18:6a4db94011d3 | 991 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 992 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 993 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 994 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 995 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 996 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 997 | |
| sahilmgandhi | 18:6a4db94011d3 | 998 | /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions |
| sahilmgandhi | 18:6a4db94011d3 | 999 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 1000 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1001 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 1002 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| sahilmgandhi | 18:6a4db94011d3 | 1003 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
| sahilmgandhi | 18:6a4db94011d3 | 1004 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 1005 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 1006 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1007 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 1008 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 1009 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1010 | |
| sahilmgandhi | 18:6a4db94011d3 | 1011 | /** @defgroup FSMC_LL_PCCARD PCCARD |
| sahilmgandhi | 18:6a4db94011d3 | 1012 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 1013 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1014 | /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions |
| sahilmgandhi | 18:6a4db94011d3 | 1015 | * @{ |
| sahilmgandhi | 18:6a4db94011d3 | 1016 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1017 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); |
| sahilmgandhi | 18:6a4db94011d3 | 1018 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| sahilmgandhi | 18:6a4db94011d3 | 1019 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| sahilmgandhi | 18:6a4db94011d3 | 1020 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
| sahilmgandhi | 18:6a4db94011d3 | 1021 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); |
| sahilmgandhi | 18:6a4db94011d3 | 1022 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 1023 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 1024 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1025 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 1026 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 1027 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1028 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| sahilmgandhi | 18:6a4db94011d3 | 1029 | |
| sahilmgandhi | 18:6a4db94011d3 | 1030 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 1031 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 1032 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1033 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ |
| sahilmgandhi | 18:6a4db94011d3 | 1034 | |
| sahilmgandhi | 18:6a4db94011d3 | 1035 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 1036 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 1037 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1038 | |
| sahilmgandhi | 18:6a4db94011d3 | 1039 | /** |
| sahilmgandhi | 18:6a4db94011d3 | 1040 | * @} |
| sahilmgandhi | 18:6a4db94011d3 | 1041 | */ |
| sahilmgandhi | 18:6a4db94011d3 | 1042 | |
| sahilmgandhi | 18:6a4db94011d3 | 1043 | #ifdef __cplusplus |
| sahilmgandhi | 18:6a4db94011d3 | 1044 | } |
| sahilmgandhi | 18:6a4db94011d3 | 1045 | #endif |
| sahilmgandhi | 18:6a4db94011d3 | 1046 | |
| sahilmgandhi | 18:6a4db94011d3 | 1047 | #endif /* __STM32F4xx_LL_FSMC_H */ |
| sahilmgandhi | 18:6a4db94011d3 | 1048 | |
| sahilmgandhi | 18:6a4db94011d3 | 1049 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |