MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_ll_fsmc.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief FSMC Low Layer HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
sahilmgandhi 18:6a4db94011d3 11 * + Initialization/de-initialization functions
sahilmgandhi 18:6a4db94011d3 12 * + Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 13 * + Peripheral State functions
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 @verbatim
sahilmgandhi 18:6a4db94011d3 16 ==============================================================================
sahilmgandhi 18:6a4db94011d3 17 ##### FSMC peripheral features #####
sahilmgandhi 18:6a4db94011d3 18 ==============================================================================
sahilmgandhi 18:6a4db94011d3 19 [..] The Flexible static memory controller (FSMC) includes two memory controllers:
sahilmgandhi 18:6a4db94011d3 20 (+) The NOR/PSRAM memory controller
sahilmgandhi 18:6a4db94011d3 21 (+) The NAND/PC Card memory controller
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
sahilmgandhi 18:6a4db94011d3 24 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
sahilmgandhi 18:6a4db94011d3 25 (+) to translate AHB transactions into the appropriate external device protocol.
sahilmgandhi 18:6a4db94011d3 26 (+) to meet the access time requirements of the external memory devices.
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 [..] All external memories share the addresses, data and control signals with the controller.
sahilmgandhi 18:6a4db94011d3 29 Each external device is accessed by means of a unique Chip Select. The FSMC performs
sahilmgandhi 18:6a4db94011d3 30 only one access at a time to an external device.
sahilmgandhi 18:6a4db94011d3 31 The main features of the FSMC controller are the following:
sahilmgandhi 18:6a4db94011d3 32 (+) Interface with static-memory mapped devices including:
sahilmgandhi 18:6a4db94011d3 33 (++) Static random access memory (SRAM).
sahilmgandhi 18:6a4db94011d3 34 (++) Read-only memory (ROM).
sahilmgandhi 18:6a4db94011d3 35 (++) NOR Flash memory/OneNAND Flash memory.
sahilmgandhi 18:6a4db94011d3 36 (++) PSRAM (4 memory banks).
sahilmgandhi 18:6a4db94011d3 37 (++) 16-bit PC Card compatible devices.
sahilmgandhi 18:6a4db94011d3 38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
sahilmgandhi 18:6a4db94011d3 39 data.
sahilmgandhi 18:6a4db94011d3 40 (+) Independent Chip Select control for each memory bank.
sahilmgandhi 18:6a4db94011d3 41 (+) Independent configuration for each memory bank.
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 @endverbatim
sahilmgandhi 18:6a4db94011d3 44 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 45 * @attention
sahilmgandhi 18:6a4db94011d3 46 *
sahilmgandhi 18:6a4db94011d3 47 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 48 *
sahilmgandhi 18:6a4db94011d3 49 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 50 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 51 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 52 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 54 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 55 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 57 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 58 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 59 *
sahilmgandhi 18:6a4db94011d3 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 70 *
sahilmgandhi 18:6a4db94011d3 71 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 72 */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 75 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 78 * @{
sahilmgandhi 18:6a4db94011d3 79 */
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 /** @defgroup FSMC_LL FSMC Low Layer
sahilmgandhi 18:6a4db94011d3 82 * @brief FSMC driver modules
sahilmgandhi 18:6a4db94011d3 83 * @{
sahilmgandhi 18:6a4db94011d3 84 */
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
sahilmgandhi 18:6a4db94011d3 87 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
sahilmgandhi 18:6a4db94011d3 88 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 89 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 90 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 91 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 92 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 93 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 94 /** @addtogroup FSMC_LL_Private_Functions
sahilmgandhi 18:6a4db94011d3 95 * @{
sahilmgandhi 18:6a4db94011d3 96 */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /** @addtogroup FSMC_LL_NORSRAM
sahilmgandhi 18:6a4db94011d3 99 * @brief NORSRAM Controller functions
sahilmgandhi 18:6a4db94011d3 100 *
sahilmgandhi 18:6a4db94011d3 101 @verbatim
sahilmgandhi 18:6a4db94011d3 102 ==============================================================================
sahilmgandhi 18:6a4db94011d3 103 ##### How to use NORSRAM device driver #####
sahilmgandhi 18:6a4db94011d3 104 ==============================================================================
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 [..]
sahilmgandhi 18:6a4db94011d3 107 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
sahilmgandhi 18:6a4db94011d3 108 to run the NORSRAM external devices.
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
sahilmgandhi 18:6a4db94011d3 111 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
sahilmgandhi 18:6a4db94011d3 112 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
sahilmgandhi 18:6a4db94011d3 113 (+) FSMC NORSRAM bank extended timing configuration using the function
sahilmgandhi 18:6a4db94011d3 114 FSMC_NORSRAM_Extended_Timing_Init()
sahilmgandhi 18:6a4db94011d3 115 (+) FSMC NORSRAM bank enable/disable write operation using the functions
sahilmgandhi 18:6a4db94011d3 116 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 @endverbatim
sahilmgandhi 18:6a4db94011d3 119 * @{
sahilmgandhi 18:6a4db94011d3 120 */
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
sahilmgandhi 18:6a4db94011d3 123 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 124 *
sahilmgandhi 18:6a4db94011d3 125 @verbatim
sahilmgandhi 18:6a4db94011d3 126 ==============================================================================
sahilmgandhi 18:6a4db94011d3 127 ##### Initialization and de_initialization functions #####
sahilmgandhi 18:6a4db94011d3 128 ==============================================================================
sahilmgandhi 18:6a4db94011d3 129 [..]
sahilmgandhi 18:6a4db94011d3 130 This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 131 (+) Initialize and configure the FSMC NORSRAM interface
sahilmgandhi 18:6a4db94011d3 132 (+) De-initialize the FSMC NORSRAM interface
sahilmgandhi 18:6a4db94011d3 133 (+) Configure the FSMC clock and associated GPIOs
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 @endverbatim
sahilmgandhi 18:6a4db94011d3 136 * @{
sahilmgandhi 18:6a4db94011d3 137 */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /**
sahilmgandhi 18:6a4db94011d3 140 * @brief Initialize the FSMC_NORSRAM device according to the specified
sahilmgandhi 18:6a4db94011d3 141 * control parameters in the FSMC_NORSRAM_InitTypeDef
sahilmgandhi 18:6a4db94011d3 142 * @param Device: Pointer to NORSRAM device instance
sahilmgandhi 18:6a4db94011d3 143 * @param Init: Pointer to NORSRAM Initialization structure
sahilmgandhi 18:6a4db94011d3 144 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 145 */
sahilmgandhi 18:6a4db94011d3 146 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
sahilmgandhi 18:6a4db94011d3 147 {
sahilmgandhi 18:6a4db94011d3 148 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 151 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
sahilmgandhi 18:6a4db94011d3 152 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
sahilmgandhi 18:6a4db94011d3 153 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
sahilmgandhi 18:6a4db94011d3 154 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
sahilmgandhi 18:6a4db94011d3 155 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
sahilmgandhi 18:6a4db94011d3 156 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
sahilmgandhi 18:6a4db94011d3 157 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
sahilmgandhi 18:6a4db94011d3 158 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
sahilmgandhi 18:6a4db94011d3 159 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
sahilmgandhi 18:6a4db94011d3 160 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
sahilmgandhi 18:6a4db94011d3 161 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
sahilmgandhi 18:6a4db94011d3 162 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
sahilmgandhi 18:6a4db94011d3 163 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
sahilmgandhi 18:6a4db94011d3 164 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
sahilmgandhi 18:6a4db94011d3 165 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
sahilmgandhi 18:6a4db94011d3 166 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
sahilmgandhi 18:6a4db94011d3 167 assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
sahilmgandhi 18:6a4db94011d3 168 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
sahilmgandhi 18:6a4db94011d3 169 assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
sahilmgandhi 18:6a4db94011d3 170 assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
sahilmgandhi 18:6a4db94011d3 171 #endif /* STM32F412Zx || TM32F412Vx */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /* Get the BTCR register value */
sahilmgandhi 18:6a4db94011d3 174 tmpr = Device->BTCR[Init->NSBank];
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
sahilmgandhi 18:6a4db94011d3 177 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
sahilmgandhi 18:6a4db94011d3 178 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */
sahilmgandhi 18:6a4db94011d3 179 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
sahilmgandhi 18:6a4db94011d3 180 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
sahilmgandhi 18:6a4db94011d3 181 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
sahilmgandhi 18:6a4db94011d3 182 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
sahilmgandhi 18:6a4db94011d3 183 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW));
sahilmgandhi 18:6a4db94011d3 184 /* Set NORSRAM device control parameters */
sahilmgandhi 18:6a4db94011d3 185 tmpr |= (uint32_t)(Init->DataAddressMux |\
sahilmgandhi 18:6a4db94011d3 186 Init->MemoryType |\
sahilmgandhi 18:6a4db94011d3 187 Init->MemoryDataWidth |\
sahilmgandhi 18:6a4db94011d3 188 Init->BurstAccessMode |\
sahilmgandhi 18:6a4db94011d3 189 Init->WaitSignalPolarity |\
sahilmgandhi 18:6a4db94011d3 190 Init->WrapMode |\
sahilmgandhi 18:6a4db94011d3 191 Init->WaitSignalActive |\
sahilmgandhi 18:6a4db94011d3 192 Init->WriteOperation |\
sahilmgandhi 18:6a4db94011d3 193 Init->WaitSignal |\
sahilmgandhi 18:6a4db94011d3 194 Init->ExtendedMode |\
sahilmgandhi 18:6a4db94011d3 195 Init->AsynchronousWait |\
sahilmgandhi 18:6a4db94011d3 196 Init->PageSize |\
sahilmgandhi 18:6a4db94011d3 197 Init->WriteBurst
sahilmgandhi 18:6a4db94011d3 198 );
sahilmgandhi 18:6a4db94011d3 199 #else /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
sahilmgandhi 18:6a4db94011d3 200 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
sahilmgandhi 18:6a4db94011d3 201 WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */
sahilmgandhi 18:6a4db94011d3 202 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
sahilmgandhi 18:6a4db94011d3 203 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
sahilmgandhi 18:6a4db94011d3 204 FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \
sahilmgandhi 18:6a4db94011d3 205 FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \
sahilmgandhi 18:6a4db94011d3 206 FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \
sahilmgandhi 18:6a4db94011d3 207 FSMC_BCR1_WFDIS));
sahilmgandhi 18:6a4db94011d3 208 /* Set NORSRAM device control parameters */
sahilmgandhi 18:6a4db94011d3 209 tmpr |= (uint32_t)(Init->DataAddressMux |\
sahilmgandhi 18:6a4db94011d3 210 Init->MemoryType |\
sahilmgandhi 18:6a4db94011d3 211 Init->MemoryDataWidth |\
sahilmgandhi 18:6a4db94011d3 212 Init->BurstAccessMode |\
sahilmgandhi 18:6a4db94011d3 213 Init->WaitSignalPolarity |\
sahilmgandhi 18:6a4db94011d3 214 Init->WaitSignalActive |\
sahilmgandhi 18:6a4db94011d3 215 Init->WriteOperation |\
sahilmgandhi 18:6a4db94011d3 216 Init->WaitSignal |\
sahilmgandhi 18:6a4db94011d3 217 Init->ExtendedMode |\
sahilmgandhi 18:6a4db94011d3 218 Init->AsynchronousWait |\
sahilmgandhi 18:6a4db94011d3 219 Init->WriteBurst |\
sahilmgandhi 18:6a4db94011d3 220 Init->ContinuousClock |\
sahilmgandhi 18:6a4db94011d3 221 Init->PageSize |\
sahilmgandhi 18:6a4db94011d3 222 Init->WriteFifo);
sahilmgandhi 18:6a4db94011d3 223 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
sahilmgandhi 18:6a4db94011d3 226 {
sahilmgandhi 18:6a4db94011d3 227 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
sahilmgandhi 18:6a4db94011d3 228 }
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 Device->BTCR[Init->NSBank] = tmpr;
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
sahilmgandhi 18:6a4db94011d3 233 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
sahilmgandhi 18:6a4db94011d3 234 if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
sahilmgandhi 18:6a4db94011d3 235 {
sahilmgandhi 18:6a4db94011d3 236 Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 if(Init->NSBank != FSMC_NORSRAM_BANK1)
sahilmgandhi 18:6a4db94011d3 240 {
sahilmgandhi 18:6a4db94011d3 241 Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
sahilmgandhi 18:6a4db94011d3 242 }
sahilmgandhi 18:6a4db94011d3 243 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 246 }
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /**
sahilmgandhi 18:6a4db94011d3 249 * @brief DeInitialize the FSMC_NORSRAM peripheral
sahilmgandhi 18:6a4db94011d3 250 * @param Device: Pointer to NORSRAM device instance
sahilmgandhi 18:6a4db94011d3 251 * @param ExDevice: Pointer to NORSRAM extended mode device instance
sahilmgandhi 18:6a4db94011d3 252 * @param Bank: NORSRAM bank number
sahilmgandhi 18:6a4db94011d3 253 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 254 */
sahilmgandhi 18:6a4db94011d3 255 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 256 {
sahilmgandhi 18:6a4db94011d3 257 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 258 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
sahilmgandhi 18:6a4db94011d3 259 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
sahilmgandhi 18:6a4db94011d3 260 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /* Disable the FSMC_NORSRAM device */
sahilmgandhi 18:6a4db94011d3 263 __FSMC_NORSRAM_DISABLE(Device, Bank);
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /* De-initialize the FSMC_NORSRAM device */
sahilmgandhi 18:6a4db94011d3 266 /* FSMC_NORSRAM_BANK1 */
sahilmgandhi 18:6a4db94011d3 267 if(Bank == FSMC_NORSRAM_BANK1)
sahilmgandhi 18:6a4db94011d3 268 {
sahilmgandhi 18:6a4db94011d3 269 Device->BTCR[Bank] = 0x000030DBU;
sahilmgandhi 18:6a4db94011d3 270 }
sahilmgandhi 18:6a4db94011d3 271 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
sahilmgandhi 18:6a4db94011d3 272 else
sahilmgandhi 18:6a4db94011d3 273 {
sahilmgandhi 18:6a4db94011d3 274 Device->BTCR[Bank] = 0x000030D2U;
sahilmgandhi 18:6a4db94011d3 275 }
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
sahilmgandhi 18:6a4db94011d3 278 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 281 }
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 /**
sahilmgandhi 18:6a4db94011d3 285 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
sahilmgandhi 18:6a4db94011d3 286 * parameters in the FSMC_NORSRAM_TimingTypeDef
sahilmgandhi 18:6a4db94011d3 287 * @param Device: Pointer to NORSRAM device instance
sahilmgandhi 18:6a4db94011d3 288 * @param Timing: Pointer to NORSRAM Timing structure
sahilmgandhi 18:6a4db94011d3 289 * @param Bank: NORSRAM bank number
sahilmgandhi 18:6a4db94011d3 290 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 291 */
sahilmgandhi 18:6a4db94011d3 292 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 293 {
sahilmgandhi 18:6a4db94011d3 294 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 297 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
sahilmgandhi 18:6a4db94011d3 298 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
sahilmgandhi 18:6a4db94011d3 299 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
sahilmgandhi 18:6a4db94011d3 300 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
sahilmgandhi 18:6a4db94011d3 301 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
sahilmgandhi 18:6a4db94011d3 302 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
sahilmgandhi 18:6a4db94011d3 303 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
sahilmgandhi 18:6a4db94011d3 304 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
sahilmgandhi 18:6a4db94011d3 305 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Get the BTCR register value */
sahilmgandhi 18:6a4db94011d3 308 tmpr = Device->BTCR[Bank + 1U];
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
sahilmgandhi 18:6a4db94011d3 311 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
sahilmgandhi 18:6a4db94011d3 312 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
sahilmgandhi 18:6a4db94011d3 313 FSMC_BTR1_ACCMOD));
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 /* Set FSMC_NORSRAM device timing parameters */
sahilmgandhi 18:6a4db94011d3 316 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
sahilmgandhi 18:6a4db94011d3 317 ((Timing->AddressHoldTime) << 4U) |\
sahilmgandhi 18:6a4db94011d3 318 ((Timing->DataSetupTime) << 8U) |\
sahilmgandhi 18:6a4db94011d3 319 ((Timing->BusTurnAroundDuration) << 16U) |\
sahilmgandhi 18:6a4db94011d3 320 (((Timing->CLKDivision)-1U) << 20U) |\
sahilmgandhi 18:6a4db94011d3 321 (((Timing->DataLatency)-2U) << 24U) |\
sahilmgandhi 18:6a4db94011d3 322 (Timing->AccessMode));
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 Device->BTCR[Bank + 1] = tmpr;
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
sahilmgandhi 18:6a4db94011d3 327 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
sahilmgandhi 18:6a4db94011d3 328 if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
sahilmgandhi 18:6a4db94011d3 329 {
sahilmgandhi 18:6a4db94011d3 330 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0FU) << 20U));
sahilmgandhi 18:6a4db94011d3 331 tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U);
sahilmgandhi 18:6a4db94011d3 332 Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr;
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx */
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 337 }
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /**
sahilmgandhi 18:6a4db94011d3 340 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
sahilmgandhi 18:6a4db94011d3 341 * parameters in the FSMC_NORSRAM_TimingTypeDef
sahilmgandhi 18:6a4db94011d3 342 * @param Device: Pointer to NORSRAM device instance
sahilmgandhi 18:6a4db94011d3 343 * @param Timing: Pointer to NORSRAM Timing structure
sahilmgandhi 18:6a4db94011d3 344 * @param Bank: NORSRAM bank number
sahilmgandhi 18:6a4db94011d3 345 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 346 */
sahilmgandhi 18:6a4db94011d3 347 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
sahilmgandhi 18:6a4db94011d3 348 {
sahilmgandhi 18:6a4db94011d3 349 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 352 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
sahilmgandhi 18:6a4db94011d3 355 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 356 {
sahilmgandhi 18:6a4db94011d3 357 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 358 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
sahilmgandhi 18:6a4db94011d3 359 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
sahilmgandhi 18:6a4db94011d3 360 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
sahilmgandhi 18:6a4db94011d3 361 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
sahilmgandhi 18:6a4db94011d3 362 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
sahilmgandhi 18:6a4db94011d3 363 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
sahilmgandhi 18:6a4db94011d3 364 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 /* Get the BWTR register value */
sahilmgandhi 18:6a4db94011d3 367 tmpr = Device->BWTR[Bank];
sahilmgandhi 18:6a4db94011d3 368
sahilmgandhi 18:6a4db94011d3 369 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
sahilmgandhi 18:6a4db94011d3 370 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
sahilmgandhi 18:6a4db94011d3 371 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
sahilmgandhi 18:6a4db94011d3 374 ((Timing->AddressHoldTime) << 4U) |\
sahilmgandhi 18:6a4db94011d3 375 ((Timing->DataSetupTime) << 8U) |\
sahilmgandhi 18:6a4db94011d3 376 ((Timing->BusTurnAroundDuration) << 16U) |\
sahilmgandhi 18:6a4db94011d3 377 (Timing->AccessMode));
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 Device->BWTR[Bank] = tmpr;
sahilmgandhi 18:6a4db94011d3 380 }
sahilmgandhi 18:6a4db94011d3 381 else
sahilmgandhi 18:6a4db94011d3 382 {
sahilmgandhi 18:6a4db94011d3 383 Device->BWTR[Bank] = 0x0FFFFFFFU;
sahilmgandhi 18:6a4db94011d3 384 }
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 387 }
sahilmgandhi 18:6a4db94011d3 388 /**
sahilmgandhi 18:6a4db94011d3 389 * @}
sahilmgandhi 18:6a4db94011d3 390 */
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
sahilmgandhi 18:6a4db94011d3 393 * @brief management functions
sahilmgandhi 18:6a4db94011d3 394 *
sahilmgandhi 18:6a4db94011d3 395 @verbatim
sahilmgandhi 18:6a4db94011d3 396 ==============================================================================
sahilmgandhi 18:6a4db94011d3 397 ##### FSMC_NORSRAM Control functions #####
sahilmgandhi 18:6a4db94011d3 398 ==============================================================================
sahilmgandhi 18:6a4db94011d3 399 [..]
sahilmgandhi 18:6a4db94011d3 400 This subsection provides a set of functions allowing to control dynamically
sahilmgandhi 18:6a4db94011d3 401 the FSMC NORSRAM interface.
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 @endverbatim
sahilmgandhi 18:6a4db94011d3 404 * @{
sahilmgandhi 18:6a4db94011d3 405 */
sahilmgandhi 18:6a4db94011d3 406
sahilmgandhi 18:6a4db94011d3 407 /**
sahilmgandhi 18:6a4db94011d3 408 * @brief Enables dynamically FSMC_NORSRAM write operation.
sahilmgandhi 18:6a4db94011d3 409 * @param Device: Pointer to NORSRAM device instance
sahilmgandhi 18:6a4db94011d3 410 * @param Bank: NORSRAM bank number
sahilmgandhi 18:6a4db94011d3 411 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 412 */
sahilmgandhi 18:6a4db94011d3 413 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 414 {
sahilmgandhi 18:6a4db94011d3 415 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 416 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
sahilmgandhi 18:6a4db94011d3 417 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 /* Enable write operation */
sahilmgandhi 18:6a4db94011d3 420 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 423 }
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 /**
sahilmgandhi 18:6a4db94011d3 426 * @brief Disables dynamically FSMC_NORSRAM write operation.
sahilmgandhi 18:6a4db94011d3 427 * @param Device: Pointer to NORSRAM device instance
sahilmgandhi 18:6a4db94011d3 428 * @param Bank: NORSRAM bank number
sahilmgandhi 18:6a4db94011d3 429 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 430 */
sahilmgandhi 18:6a4db94011d3 431 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 432 {
sahilmgandhi 18:6a4db94011d3 433 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 434 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
sahilmgandhi 18:6a4db94011d3 435 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 /* Disable write operation */
sahilmgandhi 18:6a4db94011d3 438 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 441 }
sahilmgandhi 18:6a4db94011d3 442 /**
sahilmgandhi 18:6a4db94011d3 443 * @}
sahilmgandhi 18:6a4db94011d3 444 */
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 /**
sahilmgandhi 18:6a4db94011d3 447 * @}
sahilmgandhi 18:6a4db94011d3 448 */
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
sahilmgandhi 18:6a4db94011d3 451 /** @addtogroup FSMC_LL_NAND
sahilmgandhi 18:6a4db94011d3 452 * @brief NAND Controller functions
sahilmgandhi 18:6a4db94011d3 453 *
sahilmgandhi 18:6a4db94011d3 454 @verbatim
sahilmgandhi 18:6a4db94011d3 455 ==============================================================================
sahilmgandhi 18:6a4db94011d3 456 ##### How to use NAND device driver #####
sahilmgandhi 18:6a4db94011d3 457 ==============================================================================
sahilmgandhi 18:6a4db94011d3 458 [..]
sahilmgandhi 18:6a4db94011d3 459 This driver contains a set of APIs to interface with the FSMC NAND banks in order
sahilmgandhi 18:6a4db94011d3 460 to run the NAND external devices.
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
sahilmgandhi 18:6a4db94011d3 463 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
sahilmgandhi 18:6a4db94011d3 464 (+) FSMC NAND bank common space timing configuration using the function
sahilmgandhi 18:6a4db94011d3 465 FSMC_NAND_CommonSpace_Timing_Init()
sahilmgandhi 18:6a4db94011d3 466 (+) FSMC NAND bank attribute space timing configuration using the function
sahilmgandhi 18:6a4db94011d3 467 FSMC_NAND_AttributeSpace_Timing_Init()
sahilmgandhi 18:6a4db94011d3 468 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
sahilmgandhi 18:6a4db94011d3 469 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
sahilmgandhi 18:6a4db94011d3 470 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 @endverbatim
sahilmgandhi 18:6a4db94011d3 473 * @{
sahilmgandhi 18:6a4db94011d3 474 */
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
sahilmgandhi 18:6a4db94011d3 477 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 478 *
sahilmgandhi 18:6a4db94011d3 479 @verbatim
sahilmgandhi 18:6a4db94011d3 480 ==============================================================================
sahilmgandhi 18:6a4db94011d3 481 ##### Initialization and de_initialization functions #####
sahilmgandhi 18:6a4db94011d3 482 ==============================================================================
sahilmgandhi 18:6a4db94011d3 483 [..]
sahilmgandhi 18:6a4db94011d3 484 This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 485 (+) Initialize and configure the FSMC NAND interface
sahilmgandhi 18:6a4db94011d3 486 (+) De-initialize the FSMC NAND interface
sahilmgandhi 18:6a4db94011d3 487 (+) Configure the FSMC clock and associated GPIOs
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 @endverbatim
sahilmgandhi 18:6a4db94011d3 490 * @{
sahilmgandhi 18:6a4db94011d3 491 */
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 /**
sahilmgandhi 18:6a4db94011d3 494 * @brief Initializes the FSMC_NAND device according to the specified
sahilmgandhi 18:6a4db94011d3 495 * control parameters in the FSMC_NAND_HandleTypeDef
sahilmgandhi 18:6a4db94011d3 496 * @param Device: Pointer to NAND device instance
sahilmgandhi 18:6a4db94011d3 497 * @param Init: Pointer to NAND Initialization structure
sahilmgandhi 18:6a4db94011d3 498 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 499 */
sahilmgandhi 18:6a4db94011d3 500 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
sahilmgandhi 18:6a4db94011d3 501 {
sahilmgandhi 18:6a4db94011d3 502 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 503
sahilmgandhi 18:6a4db94011d3 504 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 505 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
sahilmgandhi 18:6a4db94011d3 506 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
sahilmgandhi 18:6a4db94011d3 507 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
sahilmgandhi 18:6a4db94011d3 508 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
sahilmgandhi 18:6a4db94011d3 509 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
sahilmgandhi 18:6a4db94011d3 510 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
sahilmgandhi 18:6a4db94011d3 511 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 if(Init->NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 514 {
sahilmgandhi 18:6a4db94011d3 515 /* Get the NAND bank 2 register value */
sahilmgandhi 18:6a4db94011d3 516 tmpr = Device->PCR2;
sahilmgandhi 18:6a4db94011d3 517 }
sahilmgandhi 18:6a4db94011d3 518 else
sahilmgandhi 18:6a4db94011d3 519 {
sahilmgandhi 18:6a4db94011d3 520 /* Get the NAND bank 3 register value */
sahilmgandhi 18:6a4db94011d3 521 tmpr = Device->PCR3;
sahilmgandhi 18:6a4db94011d3 522 }
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
sahilmgandhi 18:6a4db94011d3 525 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
sahilmgandhi 18:6a4db94011d3 526 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
sahilmgandhi 18:6a4db94011d3 527 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 /* Set NAND device control parameters */
sahilmgandhi 18:6a4db94011d3 530 tmpr |= (uint32_t)(Init->Waitfeature |\
sahilmgandhi 18:6a4db94011d3 531 FSMC_PCR_MEMORY_TYPE_NAND |\
sahilmgandhi 18:6a4db94011d3 532 Init->MemoryDataWidth |\
sahilmgandhi 18:6a4db94011d3 533 Init->EccComputation |\
sahilmgandhi 18:6a4db94011d3 534 Init->ECCPageSize |\
sahilmgandhi 18:6a4db94011d3 535 ((Init->TCLRSetupTime) << 9U) |\
sahilmgandhi 18:6a4db94011d3 536 ((Init->TARSetupTime) << 13U));
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 if(Init->NandBank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 /* NAND bank 2 registers configuration */
sahilmgandhi 18:6a4db94011d3 541 Device->PCR2 = tmpr;
sahilmgandhi 18:6a4db94011d3 542 }
sahilmgandhi 18:6a4db94011d3 543 else
sahilmgandhi 18:6a4db94011d3 544 {
sahilmgandhi 18:6a4db94011d3 545 /* NAND bank 3 registers configuration */
sahilmgandhi 18:6a4db94011d3 546 Device->PCR3 = tmpr;
sahilmgandhi 18:6a4db94011d3 547 }
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 550 }
sahilmgandhi 18:6a4db94011d3 551
sahilmgandhi 18:6a4db94011d3 552 /**
sahilmgandhi 18:6a4db94011d3 553 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
sahilmgandhi 18:6a4db94011d3 554 * parameters in the FSMC_NAND_PCC_TimingTypeDef
sahilmgandhi 18:6a4db94011d3 555 * @param Device: Pointer to NAND device instance
sahilmgandhi 18:6a4db94011d3 556 * @param Timing: Pointer to NAND timing structure
sahilmgandhi 18:6a4db94011d3 557 * @param Bank: NAND bank number
sahilmgandhi 18:6a4db94011d3 558 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 559 */
sahilmgandhi 18:6a4db94011d3 560 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 561 {
sahilmgandhi 18:6a4db94011d3 562 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 565 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
sahilmgandhi 18:6a4db94011d3 566 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
sahilmgandhi 18:6a4db94011d3 567 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
sahilmgandhi 18:6a4db94011d3 568 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 if(Bank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 571 {
sahilmgandhi 18:6a4db94011d3 572 /* Get the NAND bank 2 register value */
sahilmgandhi 18:6a4db94011d3 573 tmpr = Device->PMEM2;
sahilmgandhi 18:6a4db94011d3 574 }
sahilmgandhi 18:6a4db94011d3 575 else
sahilmgandhi 18:6a4db94011d3 576 {
sahilmgandhi 18:6a4db94011d3 577 /* Get the NAND bank 3 register value */
sahilmgandhi 18:6a4db94011d3 578 tmpr = Device->PMEM3;
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
sahilmgandhi 18:6a4db94011d3 582 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
sahilmgandhi 18:6a4db94011d3 583 FSMC_PMEM2_MEMHIZ2));
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 /* Set FSMC_NAND device timing parameters */
sahilmgandhi 18:6a4db94011d3 586 tmpr |= (uint32_t)(Timing->SetupTime |\
sahilmgandhi 18:6a4db94011d3 587 ((Timing->WaitSetupTime) << 8U) |\
sahilmgandhi 18:6a4db94011d3 588 ((Timing->HoldSetupTime) << 16U) |\
sahilmgandhi 18:6a4db94011d3 589 ((Timing->HiZSetupTime) << 24U)
sahilmgandhi 18:6a4db94011d3 590 );
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592 if(Bank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 593 {
sahilmgandhi 18:6a4db94011d3 594 /* NAND bank 2 registers configuration */
sahilmgandhi 18:6a4db94011d3 595 Device->PMEM2 = tmpr;
sahilmgandhi 18:6a4db94011d3 596 }
sahilmgandhi 18:6a4db94011d3 597 else
sahilmgandhi 18:6a4db94011d3 598 {
sahilmgandhi 18:6a4db94011d3 599 /* NAND bank 3 registers configuration */
sahilmgandhi 18:6a4db94011d3 600 Device->PMEM3 = tmpr;
sahilmgandhi 18:6a4db94011d3 601 }
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 604 }
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 /**
sahilmgandhi 18:6a4db94011d3 607 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
sahilmgandhi 18:6a4db94011d3 608 * parameters in the FSMC_NAND_PCC_TimingTypeDef
sahilmgandhi 18:6a4db94011d3 609 * @param Device: Pointer to NAND device instance
sahilmgandhi 18:6a4db94011d3 610 * @param Timing: Pointer to NAND timing structure
sahilmgandhi 18:6a4db94011d3 611 * @param Bank: NAND bank number
sahilmgandhi 18:6a4db94011d3 612 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 613 */
sahilmgandhi 18:6a4db94011d3 614 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 615 {
sahilmgandhi 18:6a4db94011d3 616 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 619 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
sahilmgandhi 18:6a4db94011d3 620 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
sahilmgandhi 18:6a4db94011d3 621 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
sahilmgandhi 18:6a4db94011d3 622 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 if(Bank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 625 {
sahilmgandhi 18:6a4db94011d3 626 /* Get the NAND bank 2 register value */
sahilmgandhi 18:6a4db94011d3 627 tmpr = Device->PATT2;
sahilmgandhi 18:6a4db94011d3 628 }
sahilmgandhi 18:6a4db94011d3 629 else
sahilmgandhi 18:6a4db94011d3 630 {
sahilmgandhi 18:6a4db94011d3 631 /* Get the NAND bank 3 register value */
sahilmgandhi 18:6a4db94011d3 632 tmpr = Device->PATT3;
sahilmgandhi 18:6a4db94011d3 633 }
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
sahilmgandhi 18:6a4db94011d3 636 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
sahilmgandhi 18:6a4db94011d3 637 FSMC_PATT2_ATTHIZ2));
sahilmgandhi 18:6a4db94011d3 638
sahilmgandhi 18:6a4db94011d3 639 /* Set FSMC_NAND device timing parameters */
sahilmgandhi 18:6a4db94011d3 640 tmpr |= (uint32_t)(Timing->SetupTime |\
sahilmgandhi 18:6a4db94011d3 641 ((Timing->WaitSetupTime) << 8U) |\
sahilmgandhi 18:6a4db94011d3 642 ((Timing->HoldSetupTime) << 16U) |\
sahilmgandhi 18:6a4db94011d3 643 ((Timing->HiZSetupTime) << 24U)
sahilmgandhi 18:6a4db94011d3 644 );
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 if(Bank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 647 {
sahilmgandhi 18:6a4db94011d3 648 /* NAND bank 2 registers configuration */
sahilmgandhi 18:6a4db94011d3 649 Device->PATT2 = tmpr;
sahilmgandhi 18:6a4db94011d3 650 }
sahilmgandhi 18:6a4db94011d3 651 else
sahilmgandhi 18:6a4db94011d3 652 {
sahilmgandhi 18:6a4db94011d3 653 /* NAND bank 3 registers configuration */
sahilmgandhi 18:6a4db94011d3 654 Device->PATT3 = tmpr;
sahilmgandhi 18:6a4db94011d3 655 }
sahilmgandhi 18:6a4db94011d3 656
sahilmgandhi 18:6a4db94011d3 657 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 658 }
sahilmgandhi 18:6a4db94011d3 659
sahilmgandhi 18:6a4db94011d3 660 /**
sahilmgandhi 18:6a4db94011d3 661 * @brief DeInitializes the FSMC_NAND device
sahilmgandhi 18:6a4db94011d3 662 * @param Device: Pointer to NAND device instance
sahilmgandhi 18:6a4db94011d3 663 * @param Bank: NAND bank number
sahilmgandhi 18:6a4db94011d3 664 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 665 */
sahilmgandhi 18:6a4db94011d3 666 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 667 {
sahilmgandhi 18:6a4db94011d3 668 /* Disable the NAND Bank */
sahilmgandhi 18:6a4db94011d3 669 __FSMC_NAND_DISABLE(Device, Bank);
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671 /* De-initialize the NAND Bank */
sahilmgandhi 18:6a4db94011d3 672 if(Bank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 673 {
sahilmgandhi 18:6a4db94011d3 674 /* Set the FSMC_NAND_BANK2 registers to their reset values */
sahilmgandhi 18:6a4db94011d3 675 Device->PCR2 = 0x00000018U;
sahilmgandhi 18:6a4db94011d3 676 Device->SR2 = 0x00000040U;
sahilmgandhi 18:6a4db94011d3 677 Device->PMEM2 = 0xFCFCFCFCU;
sahilmgandhi 18:6a4db94011d3 678 Device->PATT2 = 0xFCFCFCFCU;
sahilmgandhi 18:6a4db94011d3 679 }
sahilmgandhi 18:6a4db94011d3 680 /* FSMC_Bank3_NAND */
sahilmgandhi 18:6a4db94011d3 681 else
sahilmgandhi 18:6a4db94011d3 682 {
sahilmgandhi 18:6a4db94011d3 683 /* Set the FSMC_NAND_BANK3 registers to their reset values */
sahilmgandhi 18:6a4db94011d3 684 Device->PCR3 = 0x00000018U;
sahilmgandhi 18:6a4db94011d3 685 Device->SR3 = 0x00000040U;
sahilmgandhi 18:6a4db94011d3 686 Device->PMEM3 = 0xFCFCFCFCU;
sahilmgandhi 18:6a4db94011d3 687 Device->PATT3 = 0xFCFCFCFCU;
sahilmgandhi 18:6a4db94011d3 688 }
sahilmgandhi 18:6a4db94011d3 689
sahilmgandhi 18:6a4db94011d3 690 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 691 }
sahilmgandhi 18:6a4db94011d3 692 /**
sahilmgandhi 18:6a4db94011d3 693 * @}
sahilmgandhi 18:6a4db94011d3 694 */
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
sahilmgandhi 18:6a4db94011d3 697 * @brief management functions
sahilmgandhi 18:6a4db94011d3 698 *
sahilmgandhi 18:6a4db94011d3 699 @verbatim
sahilmgandhi 18:6a4db94011d3 700 ==============================================================================
sahilmgandhi 18:6a4db94011d3 701 ##### FSMC_NAND Control functions #####
sahilmgandhi 18:6a4db94011d3 702 ==============================================================================
sahilmgandhi 18:6a4db94011d3 703 [..]
sahilmgandhi 18:6a4db94011d3 704 This subsection provides a set of functions allowing to control dynamically
sahilmgandhi 18:6a4db94011d3 705 the FSMC NAND interface.
sahilmgandhi 18:6a4db94011d3 706
sahilmgandhi 18:6a4db94011d3 707 @endverbatim
sahilmgandhi 18:6a4db94011d3 708 * @{
sahilmgandhi 18:6a4db94011d3 709 */
sahilmgandhi 18:6a4db94011d3 710
sahilmgandhi 18:6a4db94011d3 711 /**
sahilmgandhi 18:6a4db94011d3 712 * @brief Enables dynamically FSMC_NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 713 * @param Device: Pointer to NAND device instance
sahilmgandhi 18:6a4db94011d3 714 * @param Bank: NAND bank number
sahilmgandhi 18:6a4db94011d3 715 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 716 */
sahilmgandhi 18:6a4db94011d3 717 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 718 {
sahilmgandhi 18:6a4db94011d3 719 /* Enable ECC feature */
sahilmgandhi 18:6a4db94011d3 720 if(Bank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 721 {
sahilmgandhi 18:6a4db94011d3 722 Device->PCR2 |= FSMC_PCR2_ECCEN;
sahilmgandhi 18:6a4db94011d3 723 }
sahilmgandhi 18:6a4db94011d3 724 else
sahilmgandhi 18:6a4db94011d3 725 {
sahilmgandhi 18:6a4db94011d3 726 Device->PCR3 |= FSMC_PCR3_ECCEN;
sahilmgandhi 18:6a4db94011d3 727 }
sahilmgandhi 18:6a4db94011d3 728
sahilmgandhi 18:6a4db94011d3 729 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 730 }
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 /**
sahilmgandhi 18:6a4db94011d3 733 * @brief Disables dynamically FSMC_NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 734 * @param Device: Pointer to NAND device instance
sahilmgandhi 18:6a4db94011d3 735 * @param Bank: NAND bank number
sahilmgandhi 18:6a4db94011d3 736 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 737 */
sahilmgandhi 18:6a4db94011d3 738 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
sahilmgandhi 18:6a4db94011d3 739 {
sahilmgandhi 18:6a4db94011d3 740 /* Disable ECC feature */
sahilmgandhi 18:6a4db94011d3 741 if(Bank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 742 {
sahilmgandhi 18:6a4db94011d3 743 Device->PCR2 &= ~FSMC_PCR2_ECCEN;
sahilmgandhi 18:6a4db94011d3 744 }
sahilmgandhi 18:6a4db94011d3 745 else
sahilmgandhi 18:6a4db94011d3 746 {
sahilmgandhi 18:6a4db94011d3 747 Device->PCR3 &= ~FSMC_PCR3_ECCEN;
sahilmgandhi 18:6a4db94011d3 748 }
sahilmgandhi 18:6a4db94011d3 749
sahilmgandhi 18:6a4db94011d3 750 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 751 }
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 /**
sahilmgandhi 18:6a4db94011d3 754 * @brief Disables dynamically FSMC_NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 755 * @param Device: Pointer to NAND device instance
sahilmgandhi 18:6a4db94011d3 756 * @param ECCval: Pointer to ECC value
sahilmgandhi 18:6a4db94011d3 757 * @param Bank: NAND bank number
sahilmgandhi 18:6a4db94011d3 758 * @param Timeout: Timeout wait value
sahilmgandhi 18:6a4db94011d3 759 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 760 */
sahilmgandhi 18:6a4db94011d3 761 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 762 {
sahilmgandhi 18:6a4db94011d3 763 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 766 assert_param(IS_FSMC_NAND_DEVICE(Device));
sahilmgandhi 18:6a4db94011d3 767 assert_param(IS_FSMC_NAND_BANK(Bank));
sahilmgandhi 18:6a4db94011d3 768
sahilmgandhi 18:6a4db94011d3 769 /* Get tick */
sahilmgandhi 18:6a4db94011d3 770 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 771
sahilmgandhi 18:6a4db94011d3 772 /* Wait until FIFO is empty */
sahilmgandhi 18:6a4db94011d3 773 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
sahilmgandhi 18:6a4db94011d3 774 {
sahilmgandhi 18:6a4db94011d3 775 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 776 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 777 {
sahilmgandhi 18:6a4db94011d3 778 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 779 {
sahilmgandhi 18:6a4db94011d3 780 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 781 }
sahilmgandhi 18:6a4db94011d3 782 }
sahilmgandhi 18:6a4db94011d3 783 }
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 if(Bank == FSMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 786 {
sahilmgandhi 18:6a4db94011d3 787 /* Get the ECCR2 register value */
sahilmgandhi 18:6a4db94011d3 788 *ECCval = (uint32_t)Device->ECCR2;
sahilmgandhi 18:6a4db94011d3 789 }
sahilmgandhi 18:6a4db94011d3 790 else
sahilmgandhi 18:6a4db94011d3 791 {
sahilmgandhi 18:6a4db94011d3 792 /* Get the ECCR3 register value */
sahilmgandhi 18:6a4db94011d3 793 *ECCval = (uint32_t)Device->ECCR3;
sahilmgandhi 18:6a4db94011d3 794 }
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 797 }
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 /**
sahilmgandhi 18:6a4db94011d3 800 * @}
sahilmgandhi 18:6a4db94011d3 801 */
sahilmgandhi 18:6a4db94011d3 802
sahilmgandhi 18:6a4db94011d3 803 /**
sahilmgandhi 18:6a4db94011d3 804 * @}
sahilmgandhi 18:6a4db94011d3 805 */
sahilmgandhi 18:6a4db94011d3 806
sahilmgandhi 18:6a4db94011d3 807 /** @addtogroup FSMC_LL_PCCARD
sahilmgandhi 18:6a4db94011d3 808 * @brief PCCARD Controller functions
sahilmgandhi 18:6a4db94011d3 809 *
sahilmgandhi 18:6a4db94011d3 810 @verbatim
sahilmgandhi 18:6a4db94011d3 811 ==============================================================================
sahilmgandhi 18:6a4db94011d3 812 ##### How to use PCCARD device driver #####
sahilmgandhi 18:6a4db94011d3 813 ==============================================================================
sahilmgandhi 18:6a4db94011d3 814 [..]
sahilmgandhi 18:6a4db94011d3 815 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
sahilmgandhi 18:6a4db94011d3 816 to run the PCCARD/compact flash external devices.
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
sahilmgandhi 18:6a4db94011d3 819 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
sahilmgandhi 18:6a4db94011d3 820 (+) FSMC PCCARD bank common space timing configuration using the function
sahilmgandhi 18:6a4db94011d3 821 FSMC_PCCARD_CommonSpace_Timing_Init()
sahilmgandhi 18:6a4db94011d3 822 (+) FSMC PCCARD bank attribute space timing configuration using the function
sahilmgandhi 18:6a4db94011d3 823 FSMC_PCCARD_AttributeSpace_Timing_Init()
sahilmgandhi 18:6a4db94011d3 824 (+) FSMC PCCARD bank IO space timing configuration using the function
sahilmgandhi 18:6a4db94011d3 825 FSMC_PCCARD_IOSpace_Timing_Init()
sahilmgandhi 18:6a4db94011d3 826
sahilmgandhi 18:6a4db94011d3 827 @endverbatim
sahilmgandhi 18:6a4db94011d3 828 * @{
sahilmgandhi 18:6a4db94011d3 829 */
sahilmgandhi 18:6a4db94011d3 830
sahilmgandhi 18:6a4db94011d3 831 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
sahilmgandhi 18:6a4db94011d3 832 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 833 *
sahilmgandhi 18:6a4db94011d3 834 @verbatim
sahilmgandhi 18:6a4db94011d3 835 ==============================================================================
sahilmgandhi 18:6a4db94011d3 836 ##### Initialization and de_initialization functions #####
sahilmgandhi 18:6a4db94011d3 837 ==============================================================================
sahilmgandhi 18:6a4db94011d3 838 [..]
sahilmgandhi 18:6a4db94011d3 839 This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 840 (+) Initialize and configure the FSMC PCCARD interface
sahilmgandhi 18:6a4db94011d3 841 (+) De-initialize the FSMC PCCARD interface
sahilmgandhi 18:6a4db94011d3 842 (+) Configure the FSMC clock and associated GPIOs
sahilmgandhi 18:6a4db94011d3 843
sahilmgandhi 18:6a4db94011d3 844 @endverbatim
sahilmgandhi 18:6a4db94011d3 845 * @{
sahilmgandhi 18:6a4db94011d3 846 */
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 /**
sahilmgandhi 18:6a4db94011d3 849 * @brief Initializes the FSMC_PCCARD device according to the specified
sahilmgandhi 18:6a4db94011d3 850 * control parameters in the FSMC_PCCARD_HandleTypeDef
sahilmgandhi 18:6a4db94011d3 851 * @param Device: Pointer to PCCARD device instance
sahilmgandhi 18:6a4db94011d3 852 * @param Init: Pointer to PCCARD Initialization structure
sahilmgandhi 18:6a4db94011d3 853 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 854 */
sahilmgandhi 18:6a4db94011d3 855 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
sahilmgandhi 18:6a4db94011d3 856 {
sahilmgandhi 18:6a4db94011d3 857 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 858
sahilmgandhi 18:6a4db94011d3 859 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 860 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
sahilmgandhi 18:6a4db94011d3 861 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
sahilmgandhi 18:6a4db94011d3 862 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 /* Get PCCARD control register value */
sahilmgandhi 18:6a4db94011d3 865 tmpr = Device->PCR4;
sahilmgandhi 18:6a4db94011d3 866
sahilmgandhi 18:6a4db94011d3 867 /* Clear TAR, TCLR, PWAITEN and PWID bits */
sahilmgandhi 18:6a4db94011d3 868 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
sahilmgandhi 18:6a4db94011d3 869 FSMC_PCR4_PWID));
sahilmgandhi 18:6a4db94011d3 870
sahilmgandhi 18:6a4db94011d3 871 /* Set FSMC_PCCARD device control parameters */
sahilmgandhi 18:6a4db94011d3 872 tmpr |= (uint32_t)(Init->Waitfeature |\
sahilmgandhi 18:6a4db94011d3 873 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
sahilmgandhi 18:6a4db94011d3 874 (Init->TCLRSetupTime << 9U) |\
sahilmgandhi 18:6a4db94011d3 875 (Init->TARSetupTime << 13U));
sahilmgandhi 18:6a4db94011d3 876
sahilmgandhi 18:6a4db94011d3 877 Device->PCR4 = tmpr;
sahilmgandhi 18:6a4db94011d3 878
sahilmgandhi 18:6a4db94011d3 879 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 880 }
sahilmgandhi 18:6a4db94011d3 881
sahilmgandhi 18:6a4db94011d3 882 /**
sahilmgandhi 18:6a4db94011d3 883 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
sahilmgandhi 18:6a4db94011d3 884 * parameters in the FSMC_NAND_PCC_TimingTypeDef
sahilmgandhi 18:6a4db94011d3 885 * @param Device: Pointer to PCCARD device instance
sahilmgandhi 18:6a4db94011d3 886 * @param Timing: Pointer to PCCARD timing structure
sahilmgandhi 18:6a4db94011d3 887 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 888 */
sahilmgandhi 18:6a4db94011d3 889 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
sahilmgandhi 18:6a4db94011d3 890 {
sahilmgandhi 18:6a4db94011d3 891 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 892
sahilmgandhi 18:6a4db94011d3 893 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 894 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
sahilmgandhi 18:6a4db94011d3 895 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
sahilmgandhi 18:6a4db94011d3 896 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
sahilmgandhi 18:6a4db94011d3 897 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
sahilmgandhi 18:6a4db94011d3 898
sahilmgandhi 18:6a4db94011d3 899 /* Get PCCARD common space timing register value */
sahilmgandhi 18:6a4db94011d3 900 tmpr = Device->PMEM4;
sahilmgandhi 18:6a4db94011d3 901
sahilmgandhi 18:6a4db94011d3 902 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
sahilmgandhi 18:6a4db94011d3 903 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
sahilmgandhi 18:6a4db94011d3 904 FSMC_PMEM4_MEMHIZ4));
sahilmgandhi 18:6a4db94011d3 905 /* Set PCCARD timing parameters */
sahilmgandhi 18:6a4db94011d3 906 tmpr |= (uint32_t)((Timing->SetupTime |\
sahilmgandhi 18:6a4db94011d3 907 ((Timing->WaitSetupTime) << 8U) |\
sahilmgandhi 18:6a4db94011d3 908 (Timing->HoldSetupTime) << 16U) |\
sahilmgandhi 18:6a4db94011d3 909 ((Timing->HiZSetupTime) << 24U));
sahilmgandhi 18:6a4db94011d3 910
sahilmgandhi 18:6a4db94011d3 911 Device->PMEM4 = tmpr;
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 914 }
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 /**
sahilmgandhi 18:6a4db94011d3 917 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
sahilmgandhi 18:6a4db94011d3 918 * parameters in the FSMC_NAND_PCC_TimingTypeDef
sahilmgandhi 18:6a4db94011d3 919 * @param Device: Pointer to PCCARD device instance
sahilmgandhi 18:6a4db94011d3 920 * @param Timing: Pointer to PCCARD timing structure
sahilmgandhi 18:6a4db94011d3 921 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 922 */
sahilmgandhi 18:6a4db94011d3 923 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
sahilmgandhi 18:6a4db94011d3 924 {
sahilmgandhi 18:6a4db94011d3 925 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 928 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
sahilmgandhi 18:6a4db94011d3 929 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
sahilmgandhi 18:6a4db94011d3 930 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
sahilmgandhi 18:6a4db94011d3 931 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
sahilmgandhi 18:6a4db94011d3 932
sahilmgandhi 18:6a4db94011d3 933 /* Get PCCARD timing parameters */
sahilmgandhi 18:6a4db94011d3 934 tmpr = Device->PATT4;
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
sahilmgandhi 18:6a4db94011d3 937 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
sahilmgandhi 18:6a4db94011d3 938 FSMC_PATT4_ATTHIZ4));
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 /* Set PCCARD timing parameters */
sahilmgandhi 18:6a4db94011d3 941 tmpr |= (uint32_t)(Timing->SetupTime |\
sahilmgandhi 18:6a4db94011d3 942 ((Timing->WaitSetupTime) << 8U) |\
sahilmgandhi 18:6a4db94011d3 943 ((Timing->HoldSetupTime) << 16U) |\
sahilmgandhi 18:6a4db94011d3 944 ((Timing->HiZSetupTime) << 24U));
sahilmgandhi 18:6a4db94011d3 945 Device->PATT4 = tmpr;
sahilmgandhi 18:6a4db94011d3 946
sahilmgandhi 18:6a4db94011d3 947 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 948 }
sahilmgandhi 18:6a4db94011d3 949
sahilmgandhi 18:6a4db94011d3 950 /**
sahilmgandhi 18:6a4db94011d3 951 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
sahilmgandhi 18:6a4db94011d3 952 * parameters in the FSMC_NAND_PCC_TimingTypeDef
sahilmgandhi 18:6a4db94011d3 953 * @param Device: Pointer to PCCARD device instance
sahilmgandhi 18:6a4db94011d3 954 * @param Timing: Pointer to PCCARD timing structure
sahilmgandhi 18:6a4db94011d3 955 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 956 */
sahilmgandhi 18:6a4db94011d3 957 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 uint32_t tmpr = 0U;
sahilmgandhi 18:6a4db94011d3 960
sahilmgandhi 18:6a4db94011d3 961 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 962 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
sahilmgandhi 18:6a4db94011d3 963 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
sahilmgandhi 18:6a4db94011d3 964 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
sahilmgandhi 18:6a4db94011d3 965 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967 /* Get FSMC_PCCARD device timing parameters */
sahilmgandhi 18:6a4db94011d3 968 tmpr = Device->PIO4;
sahilmgandhi 18:6a4db94011d3 969
sahilmgandhi 18:6a4db94011d3 970 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
sahilmgandhi 18:6a4db94011d3 971 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
sahilmgandhi 18:6a4db94011d3 972 FSMC_PIO4_IOHIZ4));
sahilmgandhi 18:6a4db94011d3 973
sahilmgandhi 18:6a4db94011d3 974 /* Set FSMC_PCCARD device timing parameters */
sahilmgandhi 18:6a4db94011d3 975 tmpr |= (uint32_t)(Timing->SetupTime |\
sahilmgandhi 18:6a4db94011d3 976 ((Timing->WaitSetupTime) << 8U) |\
sahilmgandhi 18:6a4db94011d3 977 ((Timing->HoldSetupTime) << 16U) |\
sahilmgandhi 18:6a4db94011d3 978 ((Timing->HiZSetupTime) << 24U));
sahilmgandhi 18:6a4db94011d3 979
sahilmgandhi 18:6a4db94011d3 980 Device->PIO4 = tmpr;
sahilmgandhi 18:6a4db94011d3 981
sahilmgandhi 18:6a4db94011d3 982 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 983 }
sahilmgandhi 18:6a4db94011d3 984
sahilmgandhi 18:6a4db94011d3 985 /**
sahilmgandhi 18:6a4db94011d3 986 * @brief DeInitializes the FSMC_PCCARD device
sahilmgandhi 18:6a4db94011d3 987 * @param Device: Pointer to PCCARD device instance
sahilmgandhi 18:6a4db94011d3 988 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 989 */
sahilmgandhi 18:6a4db94011d3 990 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
sahilmgandhi 18:6a4db94011d3 991 {
sahilmgandhi 18:6a4db94011d3 992 /* Disable the FSMC_PCCARD device */
sahilmgandhi 18:6a4db94011d3 993 __FSMC_PCCARD_DISABLE(Device);
sahilmgandhi 18:6a4db94011d3 994
sahilmgandhi 18:6a4db94011d3 995 /* De-initialize the FSMC_PCCARD device */
sahilmgandhi 18:6a4db94011d3 996 Device->PCR4 = 0x00000018U;
sahilmgandhi 18:6a4db94011d3 997 Device->SR4 = 0x00000000U;
sahilmgandhi 18:6a4db94011d3 998 Device->PMEM4 = 0xFCFCFCFCU;
sahilmgandhi 18:6a4db94011d3 999 Device->PATT4 = 0xFCFCFCFCU;
sahilmgandhi 18:6a4db94011d3 1000 Device->PIO4 = 0xFCFCFCFCU;
sahilmgandhi 18:6a4db94011d3 1001
sahilmgandhi 18:6a4db94011d3 1002 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1003 }
sahilmgandhi 18:6a4db94011d3 1004 /**
sahilmgandhi 18:6a4db94011d3 1005 * @}
sahilmgandhi 18:6a4db94011d3 1006 */
sahilmgandhi 18:6a4db94011d3 1007
sahilmgandhi 18:6a4db94011d3 1008 /**
sahilmgandhi 18:6a4db94011d3 1009 * @}
sahilmgandhi 18:6a4db94011d3 1010 */
sahilmgandhi 18:6a4db94011d3 1011 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 /**
sahilmgandhi 18:6a4db94011d3 1014 * @}
sahilmgandhi 18:6a4db94011d3 1015 */
sahilmgandhi 18:6a4db94011d3 1016 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
sahilmgandhi 18:6a4db94011d3 1017 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1018
sahilmgandhi 18:6a4db94011d3 1019 /**
sahilmgandhi 18:6a4db94011d3 1020 * @}
sahilmgandhi 18:6a4db94011d3 1021 */
sahilmgandhi 18:6a4db94011d3 1022
sahilmgandhi 18:6a4db94011d3 1023 /**
sahilmgandhi 18:6a4db94011d3 1024 * @}
sahilmgandhi 18:6a4db94011d3 1025 */
sahilmgandhi 18:6a4db94011d3 1026 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/