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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f4xx_hal_tim.h
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.5.0
sahilmgandhi	18:6a4db94011d3	6	* @date 06-May-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief Header file of TIM HAL module.
sahilmgandhi	18:6a4db94011d3	8	******************************************************************************
sahilmgandhi	18:6a4db94011d3	9	* @attention
sahilmgandhi	18:6a4db94011d3	10	*
sahilmgandhi	18:6a4db94011d3	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	12	*
sahilmgandhi	18:6a4db94011d3	13	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	14	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	15	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	16	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	18	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	19	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	21	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	22	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	23	*
sahilmgandhi	18:6a4db94011d3	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	34	*
sahilmgandhi	18:6a4db94011d3	35	******************************************************************************
sahilmgandhi	18:6a4db94011d3	36	*/
sahilmgandhi	18:6a4db94011d3	37
sahilmgandhi	18:6a4db94011d3	38	/* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	39	#ifndef __STM32F4xx_HAL_TIM_H
sahilmgandhi	18:6a4db94011d3	40	#define __STM32F4xx_HAL_TIM_H
sahilmgandhi	18:6a4db94011d3	41
sahilmgandhi	18:6a4db94011d3	42	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	43	extern "C" {
sahilmgandhi	18:6a4db94011d3	44	#endif
sahilmgandhi	18:6a4db94011d3	45
sahilmgandhi	18:6a4db94011d3	46	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	47	#include "stm32f4xx_hal_def.h"
sahilmgandhi	18:6a4db94011d3	48
sahilmgandhi	18:6a4db94011d3	49	/** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	50	* @{
sahilmgandhi	18:6a4db94011d3	51	*/
sahilmgandhi	18:6a4db94011d3	52
sahilmgandhi	18:6a4db94011d3	53	/** @addtogroup TIM
sahilmgandhi	18:6a4db94011d3	54	* @{
sahilmgandhi	18:6a4db94011d3	55	*/
sahilmgandhi	18:6a4db94011d3	56
sahilmgandhi	18:6a4db94011d3	57	/* Exported types ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	58	/** @defgroup TIM_Exported_Types TIM Exported Types
sahilmgandhi	18:6a4db94011d3	59	* @{
sahilmgandhi	18:6a4db94011d3	60	*/
sahilmgandhi	18:6a4db94011d3	61
sahilmgandhi	18:6a4db94011d3	62	/**
sahilmgandhi	18:6a4db94011d3	63	* @brief TIM Time base Configuration Structure definition
sahilmgandhi	18:6a4db94011d3	64	*/
sahilmgandhi	18:6a4db94011d3	65	typedef struct
sahilmgandhi	18:6a4db94011d3	66	{
sahilmgandhi	18:6a4db94011d3	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
sahilmgandhi	18:6a4db94011d3	68	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
sahilmgandhi	18:6a4db94011d3	69
sahilmgandhi	18:6a4db94011d3	70	uint32_t CounterMode; /*!< Specifies the counter mode.
sahilmgandhi	18:6a4db94011d3	71	This parameter can be a value of @ref TIM_Counter_Mode */
sahilmgandhi	18:6a4db94011d3	72
sahilmgandhi	18:6a4db94011d3	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
sahilmgandhi	18:6a4db94011d3	74	Auto-Reload Register at the next update event.
sahilmgandhi	18:6a4db94011d3	75	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */
sahilmgandhi	18:6a4db94011d3	76
sahilmgandhi	18:6a4db94011d3	77	uint32_t ClockDivision; /*!< Specifies the clock division.
sahilmgandhi	18:6a4db94011d3	78	This parameter can be a value of @ref TIM_ClockDivision */
sahilmgandhi	18:6a4db94011d3	79
sahilmgandhi	18:6a4db94011d3	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
sahilmgandhi	18:6a4db94011d3	81	reaches zero, an update event is generated and counting restarts
sahilmgandhi	18:6a4db94011d3	82	from the RCR value (N).
sahilmgandhi	18:6a4db94011d3	83	This means in PWM mode that (N+1) corresponds to:
sahilmgandhi	18:6a4db94011d3	84	- the number of PWM periods in edge-aligned mode
sahilmgandhi	18:6a4db94011d3	85	- the number of half PWM period in center-aligned mode
sahilmgandhi	18:6a4db94011d3	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
sahilmgandhi	18:6a4db94011d3	87	@note This parameter is valid only for TIM1 and TIM8. */
sahilmgandhi	18:6a4db94011d3	88	} TIM_Base_InitTypeDef;
sahilmgandhi	18:6a4db94011d3	89
sahilmgandhi	18:6a4db94011d3	90	/**
sahilmgandhi	18:6a4db94011d3	91	* @brief TIM Output Compare Configuration Structure definition
sahilmgandhi	18:6a4db94011d3	92	*/
sahilmgandhi	18:6a4db94011d3	93
sahilmgandhi	18:6a4db94011d3	94	typedef struct
sahilmgandhi	18:6a4db94011d3	95	{
sahilmgandhi	18:6a4db94011d3	96	uint32_t OCMode; /*!< Specifies the TIM mode.
sahilmgandhi	18:6a4db94011d3	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
sahilmgandhi	18:6a4db94011d3	98
sahilmgandhi	18:6a4db94011d3	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
sahilmgandhi	18:6a4db94011d3	100	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
sahilmgandhi	18:6a4db94011d3	101
sahilmgandhi	18:6a4db94011d3	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
sahilmgandhi	18:6a4db94011d3	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
sahilmgandhi	18:6a4db94011d3	104
sahilmgandhi	18:6a4db94011d3	105	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
sahilmgandhi	18:6a4db94011d3	106	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
sahilmgandhi	18:6a4db94011d3	107	@note This parameter is valid only for TIM1 and TIM8. */
sahilmgandhi	18:6a4db94011d3	108
sahilmgandhi	18:6a4db94011d3	109	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
sahilmgandhi	18:6a4db94011d3	110	This parameter can be a value of @ref TIM_Output_Fast_State
sahilmgandhi	18:6a4db94011d3	111	@note This parameter is valid only in PWM1 and PWM2 mode. */
sahilmgandhi	18:6a4db94011d3	112
sahilmgandhi	18:6a4db94011d3	113
sahilmgandhi	18:6a4db94011d3	114	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
sahilmgandhi	18:6a4db94011d3	115	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
sahilmgandhi	18:6a4db94011d3	116	@note This parameter is valid only for TIM1 and TIM8. */
sahilmgandhi	18:6a4db94011d3	117
sahilmgandhi	18:6a4db94011d3	118	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
sahilmgandhi	18:6a4db94011d3	119	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
sahilmgandhi	18:6a4db94011d3	120	@note This parameter is valid only for TIM1 and TIM8. */
sahilmgandhi	18:6a4db94011d3	121	} TIM_OC_InitTypeDef;
sahilmgandhi	18:6a4db94011d3	122
sahilmgandhi	18:6a4db94011d3	123	/**
sahilmgandhi	18:6a4db94011d3	124	* @brief TIM One Pulse Mode Configuration Structure definition
sahilmgandhi	18:6a4db94011d3	125	*/
sahilmgandhi	18:6a4db94011d3	126	typedef struct
sahilmgandhi	18:6a4db94011d3	127	{
sahilmgandhi	18:6a4db94011d3	128	uint32_t OCMode; /*!< Specifies the TIM mode.
sahilmgandhi	18:6a4db94011d3	129	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
sahilmgandhi	18:6a4db94011d3	130
sahilmgandhi	18:6a4db94011d3	131	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
sahilmgandhi	18:6a4db94011d3	132	This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */
sahilmgandhi	18:6a4db94011d3	133
sahilmgandhi	18:6a4db94011d3	134	uint32_t OCPolarity; /*!< Specifies the output polarity.
sahilmgandhi	18:6a4db94011d3	135	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
sahilmgandhi	18:6a4db94011d3	136
sahilmgandhi	18:6a4db94011d3	137	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
sahilmgandhi	18:6a4db94011d3	138	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
sahilmgandhi	18:6a4db94011d3	139	@note This parameter is valid only for TIM1 and TIM8. */
sahilmgandhi	18:6a4db94011d3	140
sahilmgandhi	18:6a4db94011d3	141	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
sahilmgandhi	18:6a4db94011d3	142	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
sahilmgandhi	18:6a4db94011d3	143	@note This parameter is valid only for TIM1 and TIM8. */
sahilmgandhi	18:6a4db94011d3	144
sahilmgandhi	18:6a4db94011d3	145	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
sahilmgandhi	18:6a4db94011d3	146	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
sahilmgandhi	18:6a4db94011d3	147	@note This parameter is valid only for TIM1 and TIM8. */
sahilmgandhi	18:6a4db94011d3	148
sahilmgandhi	18:6a4db94011d3	149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
sahilmgandhi	18:6a4db94011d3	150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
sahilmgandhi	18:6a4db94011d3	151
sahilmgandhi	18:6a4db94011d3	152	uint32_t ICSelection; /*!< Specifies the input.
sahilmgandhi	18:6a4db94011d3	153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
sahilmgandhi	18:6a4db94011d3	154
sahilmgandhi	18:6a4db94011d3	155	uint32_t ICFilter; /*!< Specifies the input capture filter.
sahilmgandhi	18:6a4db94011d3	156	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
sahilmgandhi	18:6a4db94011d3	157	} TIM_OnePulse_InitTypeDef;
sahilmgandhi	18:6a4db94011d3	158
sahilmgandhi	18:6a4db94011d3	159
sahilmgandhi	18:6a4db94011d3	160	/**
sahilmgandhi	18:6a4db94011d3	161	* @brief TIM Input Capture Configuration Structure definition
sahilmgandhi	18:6a4db94011d3	162	*/
sahilmgandhi	18:6a4db94011d3	163
sahilmgandhi	18:6a4db94011d3	164	typedef struct
sahilmgandhi	18:6a4db94011d3	165	{
sahilmgandhi	18:6a4db94011d3	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
sahilmgandhi	18:6a4db94011d3	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
sahilmgandhi	18:6a4db94011d3	168
sahilmgandhi	18:6a4db94011d3	169	uint32_t ICSelection; /*!< Specifies the input.
sahilmgandhi	18:6a4db94011d3	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
sahilmgandhi	18:6a4db94011d3	171
sahilmgandhi	18:6a4db94011d3	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
sahilmgandhi	18:6a4db94011d3	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
sahilmgandhi	18:6a4db94011d3	174
sahilmgandhi	18:6a4db94011d3	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
sahilmgandhi	18:6a4db94011d3	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
sahilmgandhi	18:6a4db94011d3	177	} TIM_IC_InitTypeDef;
sahilmgandhi	18:6a4db94011d3	178
sahilmgandhi	18:6a4db94011d3	179	/**
sahilmgandhi	18:6a4db94011d3	180	* @brief TIM Encoder Configuration Structure definition
sahilmgandhi	18:6a4db94011d3	181	*/
sahilmgandhi	18:6a4db94011d3	182
sahilmgandhi	18:6a4db94011d3	183	typedef struct
sahilmgandhi	18:6a4db94011d3	184	{
sahilmgandhi	18:6a4db94011d3	185	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
sahilmgandhi	18:6a4db94011d3	186	This parameter can be a value of @ref TIM_Encoder_Mode */
sahilmgandhi	18:6a4db94011d3	187
sahilmgandhi	18:6a4db94011d3	188	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
sahilmgandhi	18:6a4db94011d3	189	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
sahilmgandhi	18:6a4db94011d3	190
sahilmgandhi	18:6a4db94011d3	191	uint32_t IC1Selection; /*!< Specifies the input.
sahilmgandhi	18:6a4db94011d3	192	This parameter can be a value of @ref TIM_Input_Capture_Selection */
sahilmgandhi	18:6a4db94011d3	193
sahilmgandhi	18:6a4db94011d3	194	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
sahilmgandhi	18:6a4db94011d3	195	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
sahilmgandhi	18:6a4db94011d3	196
sahilmgandhi	18:6a4db94011d3	197	uint32_t IC1Filter; /*!< Specifies the input capture filter.
sahilmgandhi	18:6a4db94011d3	198	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
sahilmgandhi	18:6a4db94011d3	199
sahilmgandhi	18:6a4db94011d3	200	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
sahilmgandhi	18:6a4db94011d3	201	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
sahilmgandhi	18:6a4db94011d3	202
sahilmgandhi	18:6a4db94011d3	203	uint32_t IC2Selection; /*!< Specifies the input.
sahilmgandhi	18:6a4db94011d3	204	This parameter can be a value of @ref TIM_Input_Capture_Selection */
sahilmgandhi	18:6a4db94011d3	205
sahilmgandhi	18:6a4db94011d3	206	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
sahilmgandhi	18:6a4db94011d3	207	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
sahilmgandhi	18:6a4db94011d3	208
sahilmgandhi	18:6a4db94011d3	209	uint32_t IC2Filter; /*!< Specifies the input capture filter.
sahilmgandhi	18:6a4db94011d3	210	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
sahilmgandhi	18:6a4db94011d3	211	} TIM_Encoder_InitTypeDef;
sahilmgandhi	18:6a4db94011d3	212
sahilmgandhi	18:6a4db94011d3	213	/**
sahilmgandhi	18:6a4db94011d3	214	* @brief Clock Configuration Handle Structure definition
sahilmgandhi	18:6a4db94011d3	215	*/
sahilmgandhi	18:6a4db94011d3	216	typedef struct
sahilmgandhi	18:6a4db94011d3	217	{
sahilmgandhi	18:6a4db94011d3	218	uint32_t ClockSource; /*!< TIM clock sources.
sahilmgandhi	18:6a4db94011d3	219	This parameter can be a value of @ref TIM_Clock_Source */
sahilmgandhi	18:6a4db94011d3	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
sahilmgandhi	18:6a4db94011d3	221	This parameter can be a value of @ref TIM_Clock_Polarity */
sahilmgandhi	18:6a4db94011d3	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
sahilmgandhi	18:6a4db94011d3	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
sahilmgandhi	18:6a4db94011d3	224	uint32_t ClockFilter; /*!< TIM clock filter.
sahilmgandhi	18:6a4db94011d3	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
sahilmgandhi	18:6a4db94011d3	226	}TIM_ClockConfigTypeDef;
sahilmgandhi	18:6a4db94011d3	227
sahilmgandhi	18:6a4db94011d3	228	/**
sahilmgandhi	18:6a4db94011d3	229	* @brief Clear Input Configuration Handle Structure definition
sahilmgandhi	18:6a4db94011d3	230	*/
sahilmgandhi	18:6a4db94011d3	231	typedef struct
sahilmgandhi	18:6a4db94011d3	232	{
sahilmgandhi	18:6a4db94011d3	233	uint32_t ClearInputState; /*!< TIM clear Input state.
sahilmgandhi	18:6a4db94011d3	234	This parameter can be ENABLE or DISABLE */
sahilmgandhi	18:6a4db94011d3	235	uint32_t ClearInputSource; /*!< TIM clear Input sources.
sahilmgandhi	18:6a4db94011d3	236	This parameter can be a value of @ref TIM_ClearInput_Source */
sahilmgandhi	18:6a4db94011d3	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
sahilmgandhi	18:6a4db94011d3	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
sahilmgandhi	18:6a4db94011d3	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
sahilmgandhi	18:6a4db94011d3	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
sahilmgandhi	18:6a4db94011d3	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
sahilmgandhi	18:6a4db94011d3	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
sahilmgandhi	18:6a4db94011d3	243	}TIM_ClearInputConfigTypeDef;
sahilmgandhi	18:6a4db94011d3	244
sahilmgandhi	18:6a4db94011d3	245	/**
sahilmgandhi	18:6a4db94011d3	246	* @brief TIM Slave configuration Structure definition
sahilmgandhi	18:6a4db94011d3	247	*/
sahilmgandhi	18:6a4db94011d3	248	typedef struct {
sahilmgandhi	18:6a4db94011d3	249	uint32_t SlaveMode; /*!< Slave mode selection
sahilmgandhi	18:6a4db94011d3	250	This parameter can be a value of @ref TIM_Slave_Mode */
sahilmgandhi	18:6a4db94011d3	251	uint32_t InputTrigger; /*!< Input Trigger source
sahilmgandhi	18:6a4db94011d3	252	This parameter can be a value of @ref TIM_Trigger_Selection */
sahilmgandhi	18:6a4db94011d3	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
sahilmgandhi	18:6a4db94011d3	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
sahilmgandhi	18:6a4db94011d3	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
sahilmgandhi	18:6a4db94011d3	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
sahilmgandhi	18:6a4db94011d3	257	uint32_t TriggerFilter; /*!< Input trigger filter
sahilmgandhi	18:6a4db94011d3	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
sahilmgandhi	18:6a4db94011d3	259
sahilmgandhi	18:6a4db94011d3	260	}TIM_SlaveConfigTypeDef;
sahilmgandhi	18:6a4db94011d3	261
sahilmgandhi	18:6a4db94011d3	262	/**
sahilmgandhi	18:6a4db94011d3	263	* @brief HAL State structures definition
sahilmgandhi	18:6a4db94011d3	264	*/
sahilmgandhi	18:6a4db94011d3	265	typedef enum
sahilmgandhi	18:6a4db94011d3	266	{
sahilmgandhi	18:6a4db94011d3	267	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
sahilmgandhi	18:6a4db94011d3	268	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
sahilmgandhi	18:6a4db94011d3	269	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
sahilmgandhi	18:6a4db94011d3	270	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
sahilmgandhi	18:6a4db94011d3	271	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
sahilmgandhi	18:6a4db94011d3	272	}HAL_TIM_StateTypeDef;
sahilmgandhi	18:6a4db94011d3	273
sahilmgandhi	18:6a4db94011d3	274	/**
sahilmgandhi	18:6a4db94011d3	275	* @brief HAL Active channel structures definition
sahilmgandhi	18:6a4db94011d3	276	*/
sahilmgandhi	18:6a4db94011d3	277	typedef enum
sahilmgandhi	18:6a4db94011d3	278	{
sahilmgandhi	18:6a4db94011d3	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
sahilmgandhi	18:6a4db94011d3	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
sahilmgandhi	18:6a4db94011d3	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
sahilmgandhi	18:6a4db94011d3	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
sahilmgandhi	18:6a4db94011d3	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
sahilmgandhi	18:6a4db94011d3	284	}HAL_TIM_ActiveChannel;
sahilmgandhi	18:6a4db94011d3	285
sahilmgandhi	18:6a4db94011d3	286	/**
sahilmgandhi	18:6a4db94011d3	287	* @brief TIM Time Base Handle Structure definition
sahilmgandhi	18:6a4db94011d3	288	*/
sahilmgandhi	18:6a4db94011d3	289	typedef struct
sahilmgandhi	18:6a4db94011d3	290	{
sahilmgandhi	18:6a4db94011d3	291	TIM_TypeDef Instance; /!< Register base address */
sahilmgandhi	18:6a4db94011d3	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
sahilmgandhi	18:6a4db94011d3	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
sahilmgandhi	18:6a4db94011d3	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
sahilmgandhi	18:6a4db94011d3	295	This array is accessed by a @ref DMA_Handle_index */
sahilmgandhi	18:6a4db94011d3	296	HAL_LockTypeDef Lock; /!< Locking object /
sahilmgandhi	18:6a4db94011d3	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
sahilmgandhi	18:6a4db94011d3	298	}TIM_HandleTypeDef;
sahilmgandhi	18:6a4db94011d3	299	/**
sahilmgandhi	18:6a4db94011d3	300	* @}
sahilmgandhi	18:6a4db94011d3	301	*/
sahilmgandhi	18:6a4db94011d3	302
sahilmgandhi	18:6a4db94011d3	303	/* Exported constants --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	304	/** @defgroup TIM_Exported_Constants TIM Exported Constants
sahilmgandhi	18:6a4db94011d3	305	* @{
sahilmgandhi	18:6a4db94011d3	306	*/
sahilmgandhi	18:6a4db94011d3	307
sahilmgandhi	18:6a4db94011d3	308	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
sahilmgandhi	18:6a4db94011d3	309	* @{
sahilmgandhi	18:6a4db94011d3	310	*/
sahilmgandhi	18:6a4db94011d3	311	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /!< Polarity for TIx source /
sahilmgandhi	18:6a4db94011d3	312	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
sahilmgandhi	18:6a4db94011d3	313	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
sahilmgandhi	18:6a4db94011d3	314	/**
sahilmgandhi	18:6a4db94011d3	315	* @}
sahilmgandhi	18:6a4db94011d3	316	*/
sahilmgandhi	18:6a4db94011d3	317
sahilmgandhi	18:6a4db94011d3	318	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
sahilmgandhi	18:6a4db94011d3	319	* @{
sahilmgandhi	18:6a4db94011d3	320	*/
sahilmgandhi	18:6a4db94011d3	321	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
sahilmgandhi	18:6a4db94011d3	322	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x00000000U) /!< Polarity for ETR source /
sahilmgandhi	18:6a4db94011d3	323	/**
sahilmgandhi	18:6a4db94011d3	324	* @}
sahilmgandhi	18:6a4db94011d3	325	*/
sahilmgandhi	18:6a4db94011d3	326
sahilmgandhi	18:6a4db94011d3	327	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
sahilmgandhi	18:6a4db94011d3	328	* @{
sahilmgandhi	18:6a4db94011d3	329	*/
sahilmgandhi	18:6a4db94011d3	330	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x00000000U) /!< No prescaler is used /
sahilmgandhi	18:6a4db94011d3	331	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
sahilmgandhi	18:6a4db94011d3	332	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
sahilmgandhi	18:6a4db94011d3	333	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
sahilmgandhi	18:6a4db94011d3	334	/**
sahilmgandhi	18:6a4db94011d3	335	* @}
sahilmgandhi	18:6a4db94011d3	336	*/
sahilmgandhi	18:6a4db94011d3	337
sahilmgandhi	18:6a4db94011d3	338	/** @defgroup TIM_Counter_Mode TIM Counter Mode
sahilmgandhi	18:6a4db94011d3	339	* @{
sahilmgandhi	18:6a4db94011d3	340	*/
sahilmgandhi	18:6a4db94011d3	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
sahilmgandhi	18:6a4db94011d3	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
sahilmgandhi	18:6a4db94011d3	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
sahilmgandhi	18:6a4db94011d3	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
sahilmgandhi	18:6a4db94011d3	346	/**
sahilmgandhi	18:6a4db94011d3	347	* @}
sahilmgandhi	18:6a4db94011d3	348	*/
sahilmgandhi	18:6a4db94011d3	349
sahilmgandhi	18:6a4db94011d3	350	/** @defgroup TIM_ClockDivision TIM Clock Division
sahilmgandhi	18:6a4db94011d3	351	* @{
sahilmgandhi	18:6a4db94011d3	352	*/
sahilmgandhi	18:6a4db94011d3	353	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
sahilmgandhi	18:6a4db94011d3	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
sahilmgandhi	18:6a4db94011d3	356	/**
sahilmgandhi	18:6a4db94011d3	357	* @}
sahilmgandhi	18:6a4db94011d3	358	*/
sahilmgandhi	18:6a4db94011d3	359
sahilmgandhi	18:6a4db94011d3	360	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
sahilmgandhi	18:6a4db94011d3	361	* @{
sahilmgandhi	18:6a4db94011d3	362	*/
sahilmgandhi	18:6a4db94011d3	363	#define TIM_OCMODE_TIMING ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	364	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
sahilmgandhi	18:6a4db94011d3	365	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
sahilmgandhi	18:6a4db94011d3	366	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
sahilmgandhi	18:6a4db94011d3	367	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
sahilmgandhi	18:6a4db94011d3	368	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
sahilmgandhi	18:6a4db94011d3	369	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
sahilmgandhi	18:6a4db94011d3	370	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
sahilmgandhi	18:6a4db94011d3	371
sahilmgandhi	18:6a4db94011d3	372	/**
sahilmgandhi	18:6a4db94011d3	373	* @}
sahilmgandhi	18:6a4db94011d3	374	*/
sahilmgandhi	18:6a4db94011d3	375
sahilmgandhi	18:6a4db94011d3	376	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
sahilmgandhi	18:6a4db94011d3	377	* @{
sahilmgandhi	18:6a4db94011d3	378	*/
sahilmgandhi	18:6a4db94011d3	379	#define TIM_OCFAST_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	380	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
sahilmgandhi	18:6a4db94011d3	381	/**
sahilmgandhi	18:6a4db94011d3	382	* @}
sahilmgandhi	18:6a4db94011d3	383	*/
sahilmgandhi	18:6a4db94011d3	384
sahilmgandhi	18:6a4db94011d3	385	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
sahilmgandhi	18:6a4db94011d3	386	* @{
sahilmgandhi	18:6a4db94011d3	387	*/
sahilmgandhi	18:6a4db94011d3	388	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	389	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
sahilmgandhi	18:6a4db94011d3	390	/**
sahilmgandhi	18:6a4db94011d3	391	* @}
sahilmgandhi	18:6a4db94011d3	392	*/
sahilmgandhi	18:6a4db94011d3	393
sahilmgandhi	18:6a4db94011d3	394	/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
sahilmgandhi	18:6a4db94011d3	395	* @{
sahilmgandhi	18:6a4db94011d3	396	*/
sahilmgandhi	18:6a4db94011d3	397	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	398	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
sahilmgandhi	18:6a4db94011d3	399	/**
sahilmgandhi	18:6a4db94011d3	400	* @}
sahilmgandhi	18:6a4db94011d3	401	*/
sahilmgandhi	18:6a4db94011d3	402
sahilmgandhi	18:6a4db94011d3	403	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
sahilmgandhi	18:6a4db94011d3	404	* @{
sahilmgandhi	18:6a4db94011d3	405	*/
sahilmgandhi	18:6a4db94011d3	406	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
sahilmgandhi	18:6a4db94011d3	407	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	408	/**
sahilmgandhi	18:6a4db94011d3	409	* @}
sahilmgandhi	18:6a4db94011d3	410	*/
sahilmgandhi	18:6a4db94011d3	411
sahilmgandhi	18:6a4db94011d3	412	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
sahilmgandhi	18:6a4db94011d3	413	* @{
sahilmgandhi	18:6a4db94011d3	414	*/
sahilmgandhi	18:6a4db94011d3	415	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
sahilmgandhi	18:6a4db94011d3	416	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	417	/**
sahilmgandhi	18:6a4db94011d3	418	* @}
sahilmgandhi	18:6a4db94011d3	419	*/
sahilmgandhi	18:6a4db94011d3	420
sahilmgandhi	18:6a4db94011d3	421	/** @defgroup TIM_Channel TIM Channel
sahilmgandhi	18:6a4db94011d3	422	* @{
sahilmgandhi	18:6a4db94011d3	423	*/
sahilmgandhi	18:6a4db94011d3	424	#define TIM_CHANNEL_1 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	425	#define TIM_CHANNEL_2 ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	426	#define TIM_CHANNEL_3 ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	427	#define TIM_CHANNEL_4 ((uint32_t)0x0000000CU)
sahilmgandhi	18:6a4db94011d3	428	#define TIM_CHANNEL_ALL ((uint32_t)0x00000018U)
sahilmgandhi	18:6a4db94011d3	429
sahilmgandhi	18:6a4db94011d3	430	/**
sahilmgandhi	18:6a4db94011d3	431	* @}
sahilmgandhi	18:6a4db94011d3	432	*/
sahilmgandhi	18:6a4db94011d3	433
sahilmgandhi	18:6a4db94011d3	434	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
sahilmgandhi	18:6a4db94011d3	435	* @{
sahilmgandhi	18:6a4db94011d3	436	*/
sahilmgandhi	18:6a4db94011d3	437	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
sahilmgandhi	18:6a4db94011d3	438	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
sahilmgandhi	18:6a4db94011d3	439	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
sahilmgandhi	18:6a4db94011d3	440	/**
sahilmgandhi	18:6a4db94011d3	441	* @}
sahilmgandhi	18:6a4db94011d3	442	*/
sahilmgandhi	18:6a4db94011d3	443
sahilmgandhi	18:6a4db94011d3	444	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
sahilmgandhi	18:6a4db94011d3	445	* @{
sahilmgandhi	18:6a4db94011d3	446	*/
sahilmgandhi	18:6a4db94011d3	447	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
sahilmgandhi	18:6a4db94011d3	448	connected to IC1, IC2, IC3 or IC4, respectively */
sahilmgandhi	18:6a4db94011d3	449	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
sahilmgandhi	18:6a4db94011d3	450	connected to IC2, IC1, IC4 or IC3, respectively */
sahilmgandhi	18:6a4db94011d3	451	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
sahilmgandhi	18:6a4db94011d3	452
sahilmgandhi	18:6a4db94011d3	453	/**
sahilmgandhi	18:6a4db94011d3	454	* @}
sahilmgandhi	18:6a4db94011d3	455	*/
sahilmgandhi	18:6a4db94011d3	456
sahilmgandhi	18:6a4db94011d3	457	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
sahilmgandhi	18:6a4db94011d3	458	* @{
sahilmgandhi	18:6a4db94011d3	459	*/
sahilmgandhi	18:6a4db94011d3	460	#define TIM_ICPSC_DIV1 ((uint32_t)0x00000000U) /!< Capture performed each time an edge is detected on the capture input /
sahilmgandhi	18:6a4db94011d3	461	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
sahilmgandhi	18:6a4db94011d3	462	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
sahilmgandhi	18:6a4db94011d3	463	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
sahilmgandhi	18:6a4db94011d3	464	/**
sahilmgandhi	18:6a4db94011d3	465	* @}
sahilmgandhi	18:6a4db94011d3	466	*/
sahilmgandhi	18:6a4db94011d3	467
sahilmgandhi	18:6a4db94011d3	468	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
sahilmgandhi	18:6a4db94011d3	469	* @{
sahilmgandhi	18:6a4db94011d3	470	*/
sahilmgandhi	18:6a4db94011d3	471	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
sahilmgandhi	18:6a4db94011d3	472	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	473	/**
sahilmgandhi	18:6a4db94011d3	474	* @}
sahilmgandhi	18:6a4db94011d3	475	*/
sahilmgandhi	18:6a4db94011d3	476
sahilmgandhi	18:6a4db94011d3	477	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
sahilmgandhi	18:6a4db94011d3	478	* @{
sahilmgandhi	18:6a4db94011d3	479	*/
sahilmgandhi	18:6a4db94011d3	480	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
sahilmgandhi	18:6a4db94011d3	481	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
sahilmgandhi	18:6a4db94011d3	482	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
sahilmgandhi	18:6a4db94011d3	483
sahilmgandhi	18:6a4db94011d3	484	/**
sahilmgandhi	18:6a4db94011d3	485	* @}
sahilmgandhi	18:6a4db94011d3	486	*/
sahilmgandhi	18:6a4db94011d3	487
sahilmgandhi	18:6a4db94011d3	488	/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
sahilmgandhi	18:6a4db94011d3	489	* @{
sahilmgandhi	18:6a4db94011d3	490	*/
sahilmgandhi	18:6a4db94011d3	491	#define TIM_IT_UPDATE (TIM_DIER_UIE)
sahilmgandhi	18:6a4db94011d3	492	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
sahilmgandhi	18:6a4db94011d3	493	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
sahilmgandhi	18:6a4db94011d3	494	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
sahilmgandhi	18:6a4db94011d3	495	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
sahilmgandhi	18:6a4db94011d3	496	#define TIM_IT_COM (TIM_DIER_COMIE)
sahilmgandhi	18:6a4db94011d3	497	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
sahilmgandhi	18:6a4db94011d3	498	#define TIM_IT_BREAK (TIM_DIER_BIE)
sahilmgandhi	18:6a4db94011d3	499	/**
sahilmgandhi	18:6a4db94011d3	500	* @}
sahilmgandhi	18:6a4db94011d3	501	*/
sahilmgandhi	18:6a4db94011d3	502
sahilmgandhi	18:6a4db94011d3	503	/** @defgroup TIM_Commutation_Source TIM Commutation Source
sahilmgandhi	18:6a4db94011d3	504	* @{
sahilmgandhi	18:6a4db94011d3	505	*/
sahilmgandhi	18:6a4db94011d3	506	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
sahilmgandhi	18:6a4db94011d3	507	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	508	/**
sahilmgandhi	18:6a4db94011d3	509	* @}
sahilmgandhi	18:6a4db94011d3	510	*/
sahilmgandhi	18:6a4db94011d3	511
sahilmgandhi	18:6a4db94011d3	512	/** @defgroup TIM_DMA_sources TIM DMA sources
sahilmgandhi	18:6a4db94011d3	513	* @{
sahilmgandhi	18:6a4db94011d3	514	*/
sahilmgandhi	18:6a4db94011d3	515	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
sahilmgandhi	18:6a4db94011d3	516	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
sahilmgandhi	18:6a4db94011d3	517	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
sahilmgandhi	18:6a4db94011d3	518	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
sahilmgandhi	18:6a4db94011d3	519	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
sahilmgandhi	18:6a4db94011d3	520	#define TIM_DMA_COM (TIM_DIER_COMDE)
sahilmgandhi	18:6a4db94011d3	521	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
sahilmgandhi	18:6a4db94011d3	522	/**
sahilmgandhi	18:6a4db94011d3	523	* @}
sahilmgandhi	18:6a4db94011d3	524	*/
sahilmgandhi	18:6a4db94011d3	525
sahilmgandhi	18:6a4db94011d3	526	/** @defgroup TIM_Event_Source TIM Event Source
sahilmgandhi	18:6a4db94011d3	527	* @{
sahilmgandhi	18:6a4db94011d3	528	*/
sahilmgandhi	18:6a4db94011d3	529	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
sahilmgandhi	18:6a4db94011d3	530	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
sahilmgandhi	18:6a4db94011d3	531	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
sahilmgandhi	18:6a4db94011d3	532	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
sahilmgandhi	18:6a4db94011d3	533	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
sahilmgandhi	18:6a4db94011d3	534	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
sahilmgandhi	18:6a4db94011d3	535	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
sahilmgandhi	18:6a4db94011d3	536	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
sahilmgandhi	18:6a4db94011d3	537
sahilmgandhi	18:6a4db94011d3	538	/**
sahilmgandhi	18:6a4db94011d3	539	* @}
sahilmgandhi	18:6a4db94011d3	540	*/
sahilmgandhi	18:6a4db94011d3	541
sahilmgandhi	18:6a4db94011d3	542	/** @defgroup TIM_Flag_definition TIM Flag definition
sahilmgandhi	18:6a4db94011d3	543	* @{
sahilmgandhi	18:6a4db94011d3	544	*/
sahilmgandhi	18:6a4db94011d3	545	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
sahilmgandhi	18:6a4db94011d3	546	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
sahilmgandhi	18:6a4db94011d3	547	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
sahilmgandhi	18:6a4db94011d3	548	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
sahilmgandhi	18:6a4db94011d3	549	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
sahilmgandhi	18:6a4db94011d3	550	#define TIM_FLAG_COM (TIM_SR_COMIF)
sahilmgandhi	18:6a4db94011d3	551	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
sahilmgandhi	18:6a4db94011d3	552	#define TIM_FLAG_BREAK (TIM_SR_BIF)
sahilmgandhi	18:6a4db94011d3	553	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
sahilmgandhi	18:6a4db94011d3	554	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
sahilmgandhi	18:6a4db94011d3	555	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
sahilmgandhi	18:6a4db94011d3	556	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
sahilmgandhi	18:6a4db94011d3	557	/**
sahilmgandhi	18:6a4db94011d3	558	* @}
sahilmgandhi	18:6a4db94011d3	559	*/
sahilmgandhi	18:6a4db94011d3	560
sahilmgandhi	18:6a4db94011d3	561	/** @defgroup TIM_Clock_Source TIM Clock Source
sahilmgandhi	18:6a4db94011d3	562	* @{
sahilmgandhi	18:6a4db94011d3	563	*/
sahilmgandhi	18:6a4db94011d3	564	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
sahilmgandhi	18:6a4db94011d3	565	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
sahilmgandhi	18:6a4db94011d3	566	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	567	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
sahilmgandhi	18:6a4db94011d3	568	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
sahilmgandhi	18:6a4db94011d3	569	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
sahilmgandhi	18:6a4db94011d3	570	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
sahilmgandhi	18:6a4db94011d3	571	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
sahilmgandhi	18:6a4db94011d3	572	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
sahilmgandhi	18:6a4db94011d3	573	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
sahilmgandhi	18:6a4db94011d3	574	/**
sahilmgandhi	18:6a4db94011d3	575	* @}
sahilmgandhi	18:6a4db94011d3	576	*/
sahilmgandhi	18:6a4db94011d3	577
sahilmgandhi	18:6a4db94011d3	578	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
sahilmgandhi	18:6a4db94011d3	579	* @{
sahilmgandhi	18:6a4db94011d3	580	*/
sahilmgandhi	18:6a4db94011d3	581	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
sahilmgandhi	18:6a4db94011d3	582	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
sahilmgandhi	18:6a4db94011d3	583	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
sahilmgandhi	18:6a4db94011d3	584	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
sahilmgandhi	18:6a4db94011d3	585	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
sahilmgandhi	18:6a4db94011d3	586	/**
sahilmgandhi	18:6a4db94011d3	587	* @}
sahilmgandhi	18:6a4db94011d3	588	*/
sahilmgandhi	18:6a4db94011d3	589
sahilmgandhi	18:6a4db94011d3	590	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
sahilmgandhi	18:6a4db94011d3	591	* @{
sahilmgandhi	18:6a4db94011d3	592	*/
sahilmgandhi	18:6a4db94011d3	593	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
sahilmgandhi	18:6a4db94011d3	594	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
sahilmgandhi	18:6a4db94011d3	595	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
sahilmgandhi	18:6a4db94011d3	596	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
sahilmgandhi	18:6a4db94011d3	597	/**
sahilmgandhi	18:6a4db94011d3	598	* @}
sahilmgandhi	18:6a4db94011d3	599	*/
sahilmgandhi	18:6a4db94011d3	600
sahilmgandhi	18:6a4db94011d3	601	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
sahilmgandhi	18:6a4db94011d3	602	* @{
sahilmgandhi	18:6a4db94011d3	603	*/
sahilmgandhi	18:6a4db94011d3	604	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	605	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	606	/**
sahilmgandhi	18:6a4db94011d3	607	* @}
sahilmgandhi	18:6a4db94011d3	608	*/
sahilmgandhi	18:6a4db94011d3	609
sahilmgandhi	18:6a4db94011d3	610	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
sahilmgandhi	18:6a4db94011d3	611	* @{
sahilmgandhi	18:6a4db94011d3	612	*/
sahilmgandhi	18:6a4db94011d3	613	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
sahilmgandhi	18:6a4db94011d3	614	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
sahilmgandhi	18:6a4db94011d3	615	/**
sahilmgandhi	18:6a4db94011d3	616	* @}
sahilmgandhi	18:6a4db94011d3	617	*/
sahilmgandhi	18:6a4db94011d3	618
sahilmgandhi	18:6a4db94011d3	619	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
sahilmgandhi	18:6a4db94011d3	620	* @{
sahilmgandhi	18:6a4db94011d3	621	*/
sahilmgandhi	18:6a4db94011d3	622	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
sahilmgandhi	18:6a4db94011d3	623	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
sahilmgandhi	18:6a4db94011d3	624	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
sahilmgandhi	18:6a4db94011d3	625	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
sahilmgandhi	18:6a4db94011d3	626	/**
sahilmgandhi	18:6a4db94011d3	627	* @}
sahilmgandhi	18:6a4db94011d3	628	*/
sahilmgandhi	18:6a4db94011d3	629
sahilmgandhi	18:6a4db94011d3	630	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
sahilmgandhi	18:6a4db94011d3	631	* @{
sahilmgandhi	18:6a4db94011d3	632	*/
sahilmgandhi	18:6a4db94011d3	633	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
sahilmgandhi	18:6a4db94011d3	634	#define TIM_OSSR_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	635	/**
sahilmgandhi	18:6a4db94011d3	636	* @}
sahilmgandhi	18:6a4db94011d3	637	*/
sahilmgandhi	18:6a4db94011d3	638
sahilmgandhi	18:6a4db94011d3	639	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
sahilmgandhi	18:6a4db94011d3	640	* @{
sahilmgandhi	18:6a4db94011d3	641	*/
sahilmgandhi	18:6a4db94011d3	642	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
sahilmgandhi	18:6a4db94011d3	643	#define TIM_OSSI_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	644	/**
sahilmgandhi	18:6a4db94011d3	645	* @}
sahilmgandhi	18:6a4db94011d3	646	*/
sahilmgandhi	18:6a4db94011d3	647
sahilmgandhi	18:6a4db94011d3	648	/** @defgroup TIM_Lock_level TIM Lock level
sahilmgandhi	18:6a4db94011d3	649	* @{
sahilmgandhi	18:6a4db94011d3	650	*/
sahilmgandhi	18:6a4db94011d3	651	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	652	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
sahilmgandhi	18:6a4db94011d3	653	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
sahilmgandhi	18:6a4db94011d3	654	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
sahilmgandhi	18:6a4db94011d3	655	/**
sahilmgandhi	18:6a4db94011d3	656	* @}
sahilmgandhi	18:6a4db94011d3	657	*/
sahilmgandhi	18:6a4db94011d3	658	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
sahilmgandhi	18:6a4db94011d3	659	* @{
sahilmgandhi	18:6a4db94011d3	660	*/
sahilmgandhi	18:6a4db94011d3	661	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
sahilmgandhi	18:6a4db94011d3	662	#define TIM_BREAK_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	663	/**
sahilmgandhi	18:6a4db94011d3	664	* @}
sahilmgandhi	18:6a4db94011d3	665	*/
sahilmgandhi	18:6a4db94011d3	666
sahilmgandhi	18:6a4db94011d3	667	/** @defgroup TIM_Break_Polarity TIM Break Polarity
sahilmgandhi	18:6a4db94011d3	668	* @{
sahilmgandhi	18:6a4db94011d3	669	*/
sahilmgandhi	18:6a4db94011d3	670	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	671	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
sahilmgandhi	18:6a4db94011d3	672	/**
sahilmgandhi	18:6a4db94011d3	673	* @}
sahilmgandhi	18:6a4db94011d3	674	*/
sahilmgandhi	18:6a4db94011d3	675
sahilmgandhi	18:6a4db94011d3	676	/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
sahilmgandhi	18:6a4db94011d3	677	* @{
sahilmgandhi	18:6a4db94011d3	678	*/
sahilmgandhi	18:6a4db94011d3	679	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
sahilmgandhi	18:6a4db94011d3	680	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	681	/**
sahilmgandhi	18:6a4db94011d3	682	* @}
sahilmgandhi	18:6a4db94011d3	683	*/
sahilmgandhi	18:6a4db94011d3	684
sahilmgandhi	18:6a4db94011d3	685	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
sahilmgandhi	18:6a4db94011d3	686	* @{
sahilmgandhi	18:6a4db94011d3	687	*/
sahilmgandhi	18:6a4db94011d3	688	#define TIM_TRGO_RESET ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	689	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
sahilmgandhi	18:6a4db94011d3	690	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
sahilmgandhi	18:6a4db94011d3	691	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
sahilmgandhi	18:6a4db94011d3	692	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
sahilmgandhi	18:6a4db94011d3	693	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
sahilmgandhi	18:6a4db94011d3	694	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
sahilmgandhi	18:6a4db94011d3	695	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
sahilmgandhi	18:6a4db94011d3	696	/**
sahilmgandhi	18:6a4db94011d3	697	* @}
sahilmgandhi	18:6a4db94011d3	698	*/
sahilmgandhi	18:6a4db94011d3	699
sahilmgandhi	18:6a4db94011d3	700	/** @defgroup TIM_Slave_Mode TIM Slave Mode
sahilmgandhi	18:6a4db94011d3	701	* @{
sahilmgandhi	18:6a4db94011d3	702	*/
sahilmgandhi	18:6a4db94011d3	703	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	704	#define TIM_SLAVEMODE_RESET ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	705	#define TIM_SLAVEMODE_GATED ((uint32_t)0x00000005U)
sahilmgandhi	18:6a4db94011d3	706	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x00000006U)
sahilmgandhi	18:6a4db94011d3	707	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x00000007U)
sahilmgandhi	18:6a4db94011d3	708	/**
sahilmgandhi	18:6a4db94011d3	709	* @}
sahilmgandhi	18:6a4db94011d3	710	*/
sahilmgandhi	18:6a4db94011d3	711
sahilmgandhi	18:6a4db94011d3	712	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
sahilmgandhi	18:6a4db94011d3	713	* @{
sahilmgandhi	18:6a4db94011d3	714	*/
sahilmgandhi	18:6a4db94011d3	715	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x00000080U)
sahilmgandhi	18:6a4db94011d3	716	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	717	/**
sahilmgandhi	18:6a4db94011d3	718	* @}
sahilmgandhi	18:6a4db94011d3	719	*/
sahilmgandhi	18:6a4db94011d3	720
sahilmgandhi	18:6a4db94011d3	721	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
sahilmgandhi	18:6a4db94011d3	722	* @{
sahilmgandhi	18:6a4db94011d3	723	*/
sahilmgandhi	18:6a4db94011d3	724	#define TIM_TS_ITR0 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	725	#define TIM_TS_ITR1 ((uint32_t)0x00000010U)
sahilmgandhi	18:6a4db94011d3	726	#define TIM_TS_ITR2 ((uint32_t)0x00000020U)
sahilmgandhi	18:6a4db94011d3	727	#define TIM_TS_ITR3 ((uint32_t)0x00000030U)
sahilmgandhi	18:6a4db94011d3	728	#define TIM_TS_TI1F_ED ((uint32_t)0x00000040U)
sahilmgandhi	18:6a4db94011d3	729	#define TIM_TS_TI1FP1 ((uint32_t)0x00000050U)
sahilmgandhi	18:6a4db94011d3	730	#define TIM_TS_TI2FP2 ((uint32_t)0x00000060U)
sahilmgandhi	18:6a4db94011d3	731	#define TIM_TS_ETRF ((uint32_t)0x00000070U)
sahilmgandhi	18:6a4db94011d3	732	#define TIM_TS_NONE ((uint32_t)0x0000FFFFU)
sahilmgandhi	18:6a4db94011d3	733	/**
sahilmgandhi	18:6a4db94011d3	734	* @}
sahilmgandhi	18:6a4db94011d3	735	*/
sahilmgandhi	18:6a4db94011d3	736
sahilmgandhi	18:6a4db94011d3	737	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
sahilmgandhi	18:6a4db94011d3	738	* @{
sahilmgandhi	18:6a4db94011d3	739	*/
sahilmgandhi	18:6a4db94011d3	740	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
sahilmgandhi	18:6a4db94011d3	741	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
sahilmgandhi	18:6a4db94011d3	742	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
sahilmgandhi	18:6a4db94011d3	743	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
sahilmgandhi	18:6a4db94011d3	744	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
sahilmgandhi	18:6a4db94011d3	745	/**
sahilmgandhi	18:6a4db94011d3	746	* @}
sahilmgandhi	18:6a4db94011d3	747	*/
sahilmgandhi	18:6a4db94011d3	748
sahilmgandhi	18:6a4db94011d3	749	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
sahilmgandhi	18:6a4db94011d3	750	* @{
sahilmgandhi	18:6a4db94011d3	751	*/
sahilmgandhi	18:6a4db94011d3	752	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
sahilmgandhi	18:6a4db94011d3	753	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
sahilmgandhi	18:6a4db94011d3	754	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
sahilmgandhi	18:6a4db94011d3	755	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
sahilmgandhi	18:6a4db94011d3	756	/**
sahilmgandhi	18:6a4db94011d3	757	* @}
sahilmgandhi	18:6a4db94011d3	758	*/
sahilmgandhi	18:6a4db94011d3	759
sahilmgandhi	18:6a4db94011d3	760
sahilmgandhi	18:6a4db94011d3	761	/** @defgroup TIM_TI1_Selection TIM TI1 Selection
sahilmgandhi	18:6a4db94011d3	762	* @{
sahilmgandhi	18:6a4db94011d3	763	*/
sahilmgandhi	18:6a4db94011d3	764	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	765	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
sahilmgandhi	18:6a4db94011d3	766	/**
sahilmgandhi	18:6a4db94011d3	767	* @}
sahilmgandhi	18:6a4db94011d3	768	*/
sahilmgandhi	18:6a4db94011d3	769
sahilmgandhi	18:6a4db94011d3	770	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
sahilmgandhi	18:6a4db94011d3	771	* @{
sahilmgandhi	18:6a4db94011d3	772	*/
sahilmgandhi	18:6a4db94011d3	773	#define TIM_DMABASE_CR1 (0x00000000U)
sahilmgandhi	18:6a4db94011d3	774	#define TIM_DMABASE_CR2 (0x00000001U)
sahilmgandhi	18:6a4db94011d3	775	#define TIM_DMABASE_SMCR (0x00000002U)
sahilmgandhi	18:6a4db94011d3	776	#define TIM_DMABASE_DIER (0x00000003U)
sahilmgandhi	18:6a4db94011d3	777	#define TIM_DMABASE_SR (0x00000004U)
sahilmgandhi	18:6a4db94011d3	778	#define TIM_DMABASE_EGR (0x00000005U)
sahilmgandhi	18:6a4db94011d3	779	#define TIM_DMABASE_CCMR1 (0x00000006U)
sahilmgandhi	18:6a4db94011d3	780	#define TIM_DMABASE_CCMR2 (0x00000007U)
sahilmgandhi	18:6a4db94011d3	781	#define TIM_DMABASE_CCER (0x00000008U)
sahilmgandhi	18:6a4db94011d3	782	#define TIM_DMABASE_CNT (0x00000009U)
sahilmgandhi	18:6a4db94011d3	783	#define TIM_DMABASE_PSC (0x0000000AU)
sahilmgandhi	18:6a4db94011d3	784	#define TIM_DMABASE_ARR (0x0000000BU)
sahilmgandhi	18:6a4db94011d3	785	#define TIM_DMABASE_RCR (0x0000000CU)
sahilmgandhi	18:6a4db94011d3	786	#define TIM_DMABASE_CCR1 (0x0000000DU)
sahilmgandhi	18:6a4db94011d3	787	#define TIM_DMABASE_CCR2 (0x0000000EU)
sahilmgandhi	18:6a4db94011d3	788	#define TIM_DMABASE_CCR3 (0x0000000FU)
sahilmgandhi	18:6a4db94011d3	789	#define TIM_DMABASE_CCR4 (0x00000010U)
sahilmgandhi	18:6a4db94011d3	790	#define TIM_DMABASE_BDTR (0x00000011U)
sahilmgandhi	18:6a4db94011d3	791	#define TIM_DMABASE_DCR (0x00000012U)
sahilmgandhi	18:6a4db94011d3	792	#define TIM_DMABASE_OR (0x00000013U)
sahilmgandhi	18:6a4db94011d3	793	/**
sahilmgandhi	18:6a4db94011d3	794	* @}
sahilmgandhi	18:6a4db94011d3	795	*/
sahilmgandhi	18:6a4db94011d3	796
sahilmgandhi	18:6a4db94011d3	797	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
sahilmgandhi	18:6a4db94011d3	798	* @{
sahilmgandhi	18:6a4db94011d3	799	*/
sahilmgandhi	18:6a4db94011d3	800	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
sahilmgandhi	18:6a4db94011d3	801	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
sahilmgandhi	18:6a4db94011d3	802	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
sahilmgandhi	18:6a4db94011d3	803	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
sahilmgandhi	18:6a4db94011d3	804	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
sahilmgandhi	18:6a4db94011d3	805	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
sahilmgandhi	18:6a4db94011d3	806	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
sahilmgandhi	18:6a4db94011d3	807	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
sahilmgandhi	18:6a4db94011d3	808	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
sahilmgandhi	18:6a4db94011d3	809	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
sahilmgandhi	18:6a4db94011d3	810	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
sahilmgandhi	18:6a4db94011d3	811	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
sahilmgandhi	18:6a4db94011d3	812	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
sahilmgandhi	18:6a4db94011d3	813	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
sahilmgandhi	18:6a4db94011d3	814	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
sahilmgandhi	18:6a4db94011d3	815	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
sahilmgandhi	18:6a4db94011d3	816	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
sahilmgandhi	18:6a4db94011d3	817	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
sahilmgandhi	18:6a4db94011d3	818	/**
sahilmgandhi	18:6a4db94011d3	819	* @}
sahilmgandhi	18:6a4db94011d3	820	*/
sahilmgandhi	18:6a4db94011d3	821
sahilmgandhi	18:6a4db94011d3	822	/** @defgroup DMA_Handle_index DMA Handle index
sahilmgandhi	18:6a4db94011d3	823	* @{
sahilmgandhi	18:6a4db94011d3	824	*/
sahilmgandhi	18:6a4db94011d3	825	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000U) /!< Index of the DMA handle used for Update DMA requests /
sahilmgandhi	18:6a4db94011d3	826	#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001U) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
sahilmgandhi	18:6a4db94011d3	827	#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002U) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
sahilmgandhi	18:6a4db94011d3	828	#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003U) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
sahilmgandhi	18:6a4db94011d3	829	#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004U) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
sahilmgandhi	18:6a4db94011d3	830	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005U) /!< Index of the DMA handle used for Commutation DMA requests /
sahilmgandhi	18:6a4db94011d3	831	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006U) /!< Index of the DMA handle used for Trigger DMA requests /
sahilmgandhi	18:6a4db94011d3	832	/**
sahilmgandhi	18:6a4db94011d3	833	* @}
sahilmgandhi	18:6a4db94011d3	834	*/
sahilmgandhi	18:6a4db94011d3	835
sahilmgandhi	18:6a4db94011d3	836	/** @defgroup Channel_CC_State Channel CC State
sahilmgandhi	18:6a4db94011d3	837	* @{
sahilmgandhi	18:6a4db94011d3	838	*/
sahilmgandhi	18:6a4db94011d3	839	#define TIM_CCx_ENABLE ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	840	#define TIM_CCx_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	841	#define TIM_CCxN_ENABLE ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	842	#define TIM_CCxN_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	843	/**
sahilmgandhi	18:6a4db94011d3	844	* @}
sahilmgandhi	18:6a4db94011d3	845	*/
sahilmgandhi	18:6a4db94011d3	846
sahilmgandhi	18:6a4db94011d3	847	/**
sahilmgandhi	18:6a4db94011d3	848	* @}
sahilmgandhi	18:6a4db94011d3	849	*/
sahilmgandhi	18:6a4db94011d3	850
sahilmgandhi	18:6a4db94011d3	851	/* Exported macro ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	852	/** @defgroup TIM_Exported_Macros TIM Exported Macros
sahilmgandhi	18:6a4db94011d3	853	* @{
sahilmgandhi	18:6a4db94011d3	854	*/
sahilmgandhi	18:6a4db94011d3	855	/** @brief Reset TIM handle state
sahilmgandhi	18:6a4db94011d3	856	* @param __HANDLE__: TIM handle
sahilmgandhi	18:6a4db94011d3	857	* @retval None
sahilmgandhi	18:6a4db94011d3	858	*/
sahilmgandhi	18:6a4db94011d3	859	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	860
sahilmgandhi	18:6a4db94011d3	861	/**
sahilmgandhi	18:6a4db94011d3	862	* @brief Enable the TIM peripheral.
sahilmgandhi	18:6a4db94011d3	863	* @param __HANDLE__: TIM handle
sahilmgandhi	18:6a4db94011d3	864	* @retval None
sahilmgandhi	18:6a4db94011d3	865	*/
sahilmgandhi	18:6a4db94011d3	866	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
sahilmgandhi	18:6a4db94011d3	867
sahilmgandhi	18:6a4db94011d3	868	/**
sahilmgandhi	18:6a4db94011d3	869	* @brief Enable the TIM main Output.
sahilmgandhi	18:6a4db94011d3	870	* @param __HANDLE__: TIM handle
sahilmgandhi	18:6a4db94011d3	871	* @retval None
sahilmgandhi	18:6a4db94011d3	872	*/
sahilmgandhi	18:6a4db94011d3	873	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
sahilmgandhi	18:6a4db94011d3	874
sahilmgandhi	18:6a4db94011d3	875
sahilmgandhi	18:6a4db94011d3	876	/**
sahilmgandhi	18:6a4db94011d3	877	* @brief Disable the TIM peripheral.
sahilmgandhi	18:6a4db94011d3	878	* @param __HANDLE__: TIM handle
sahilmgandhi	18:6a4db94011d3	879	* @retval None
sahilmgandhi	18:6a4db94011d3	880	*/
sahilmgandhi	18:6a4db94011d3	881	#define __HAL_TIM_DISABLE(__HANDLE__) \
sahilmgandhi	18:6a4db94011d3	882	do { \
sahilmgandhi	18:6a4db94011d3	883	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
sahilmgandhi	18:6a4db94011d3	884	{ \
sahilmgandhi	18:6a4db94011d3	885	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
sahilmgandhi	18:6a4db94011d3	886	{ \
sahilmgandhi	18:6a4db94011d3	887	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
sahilmgandhi	18:6a4db94011d3	888	} \
sahilmgandhi	18:6a4db94011d3	889	} \
sahilmgandhi	18:6a4db94011d3	890	} while(0)
sahilmgandhi	18:6a4db94011d3	891
sahilmgandhi	18:6a4db94011d3	892	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
sahilmgandhi	18:6a4db94011d3	893	channels have been disabled */
sahilmgandhi	18:6a4db94011d3	894	/**
sahilmgandhi	18:6a4db94011d3	895	* @brief Disable the TIM main Output.
sahilmgandhi	18:6a4db94011d3	896	* @param __HANDLE__: TIM handle
sahilmgandhi	18:6a4db94011d3	897	* @retval None
sahilmgandhi	18:6a4db94011d3	898	*/
sahilmgandhi	18:6a4db94011d3	899	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
sahilmgandhi	18:6a4db94011d3	900	do { \
sahilmgandhi	18:6a4db94011d3	901	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
sahilmgandhi	18:6a4db94011d3	902	{ \
sahilmgandhi	18:6a4db94011d3	903	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
sahilmgandhi	18:6a4db94011d3	904	{ \
sahilmgandhi	18:6a4db94011d3	905	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
sahilmgandhi	18:6a4db94011d3	906	} \
sahilmgandhi	18:6a4db94011d3	907	} \
sahilmgandhi	18:6a4db94011d3	908	} while(0)
sahilmgandhi	18:6a4db94011d3	909
sahilmgandhi	18:6a4db94011d3	910	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
sahilmgandhi	18:6a4db94011d3	911	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
sahilmgandhi	18:6a4db94011d3	912	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
sahilmgandhi	18:6a4db94011d3	913	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
sahilmgandhi	18:6a4db94011d3	914	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
sahilmgandhi	18:6a4db94011d3	915	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
sahilmgandhi	18:6a4db94011d3	916
sahilmgandhi	18:6a4db94011d3	917	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
sahilmgandhi	18:6a4db94011d3	918	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
sahilmgandhi	18:6a4db94011d3	919
sahilmgandhi	18:6a4db94011d3	920	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
sahilmgandhi	18:6a4db94011d3	921	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
sahilmgandhi	18:6a4db94011d3	922
sahilmgandhi	18:6a4db94011d3	923	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
sahilmgandhi	18:6a4db94011d3	924	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
sahilmgandhi	18:6a4db94011d3	925	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
sahilmgandhi	18:6a4db94011d3	926	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
sahilmgandhi	18:6a4db94011d3	927	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
sahilmgandhi	18:6a4db94011d3	928
sahilmgandhi	18:6a4db94011d3	929	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
sahilmgandhi	18:6a4db94011d3	930	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
sahilmgandhi	18:6a4db94011d3	931	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
sahilmgandhi	18:6a4db94011d3	932	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
sahilmgandhi	18:6a4db94011d3	933	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
sahilmgandhi	18:6a4db94011d3	934
sahilmgandhi	18:6a4db94011d3	935	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
sahilmgandhi	18:6a4db94011d3	936	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
sahilmgandhi	18:6a4db94011d3	937	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
sahilmgandhi	18:6a4db94011d3	938	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
sahilmgandhi	18:6a4db94011d3	939	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
sahilmgandhi	18:6a4db94011d3	940
sahilmgandhi	18:6a4db94011d3	941	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
sahilmgandhi	18:6a4db94011d3	942	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
sahilmgandhi	18:6a4db94011d3	943	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
sahilmgandhi	18:6a4db94011d3	944	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
sahilmgandhi	18:6a4db94011d3	945	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
sahilmgandhi	18:6a4db94011d3	946
sahilmgandhi	18:6a4db94011d3	947	/**
sahilmgandhi	18:6a4db94011d3	948	* @brief Sets the TIM Capture Compare Register value on runtime without
sahilmgandhi	18:6a4db94011d3	949	* calling another time ConfigChannel function.
sahilmgandhi	18:6a4db94011d3	950	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	951	* @param __CHANNEL__ : TIM Channels to be configured.
sahilmgandhi	18:6a4db94011d3	952	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	953	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	954	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	955	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	956	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	957	* @param __COMPARE__: specifies the Capture Compare register new value.
sahilmgandhi	18:6a4db94011d3	958	* @retval None
sahilmgandhi	18:6a4db94011d3	959	*/
sahilmgandhi	18:6a4db94011d3	960	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
sahilmgandhi	18:6a4db94011d3	961	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
sahilmgandhi	18:6a4db94011d3	962
sahilmgandhi	18:6a4db94011d3	963	/**
sahilmgandhi	18:6a4db94011d3	964	* @brief Gets the TIM Capture Compare Register value on runtime
sahilmgandhi	18:6a4db94011d3	965	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	966	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
sahilmgandhi	18:6a4db94011d3	967	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	968	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
sahilmgandhi	18:6a4db94011d3	969	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
sahilmgandhi	18:6a4db94011d3	970	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
sahilmgandhi	18:6a4db94011d3	971	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
sahilmgandhi	18:6a4db94011d3	972	* @retval None
sahilmgandhi	18:6a4db94011d3	973	*/
sahilmgandhi	18:6a4db94011d3	974	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
sahilmgandhi	18:6a4db94011d3	975	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
sahilmgandhi	18:6a4db94011d3	976
sahilmgandhi	18:6a4db94011d3	977	/**
sahilmgandhi	18:6a4db94011d3	978	* @brief Sets the TIM Counter Register value on runtime.
sahilmgandhi	18:6a4db94011d3	979	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	980	* @param __COUNTER__: specifies the Counter register new value.
sahilmgandhi	18:6a4db94011d3	981	* @retval None
sahilmgandhi	18:6a4db94011d3	982	*/
sahilmgandhi	18:6a4db94011d3	983	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
sahilmgandhi	18:6a4db94011d3	984
sahilmgandhi	18:6a4db94011d3	985	/**
sahilmgandhi	18:6a4db94011d3	986	* @brief Gets the TIM Counter Register value on runtime.
sahilmgandhi	18:6a4db94011d3	987	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	988	* @retval None
sahilmgandhi	18:6a4db94011d3	989	*/
sahilmgandhi	18:6a4db94011d3	990	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
sahilmgandhi	18:6a4db94011d3	991
sahilmgandhi	18:6a4db94011d3	992	/**
sahilmgandhi	18:6a4db94011d3	993	* @brief Sets the TIM Autoreload Register value on runtime without calling
sahilmgandhi	18:6a4db94011d3	994	* another time any Init function.
sahilmgandhi	18:6a4db94011d3	995	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	996	* @param __AUTORELOAD__: specifies the Counter register new value.
sahilmgandhi	18:6a4db94011d3	997	* @retval None
sahilmgandhi	18:6a4db94011d3	998	*/
sahilmgandhi	18:6a4db94011d3	999	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
sahilmgandhi	18:6a4db94011d3	1000	do{ \
sahilmgandhi	18:6a4db94011d3	1001	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
sahilmgandhi	18:6a4db94011d3	1002	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
sahilmgandhi	18:6a4db94011d3	1003	} while(0)
sahilmgandhi	18:6a4db94011d3	1004	/**
sahilmgandhi	18:6a4db94011d3	1005	* @brief Gets the TIM Autoreload Register value on runtime
sahilmgandhi	18:6a4db94011d3	1006	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	1007	* @retval None
sahilmgandhi	18:6a4db94011d3	1008	*/
sahilmgandhi	18:6a4db94011d3	1009	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
sahilmgandhi	18:6a4db94011d3	1010
sahilmgandhi	18:6a4db94011d3	1011	/**
sahilmgandhi	18:6a4db94011d3	1012	* @brief Sets the TIM Clock Division value on runtime without calling
sahilmgandhi	18:6a4db94011d3	1013	* another time any Init function.
sahilmgandhi	18:6a4db94011d3	1014	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	1015	* @param __CKD__: specifies the clock division value.
sahilmgandhi	18:6a4db94011d3	1016	* This parameter can be one of the following value:
sahilmgandhi	18:6a4db94011d3	1017	* @arg TIM_CLOCKDIVISION_DIV1
sahilmgandhi	18:6a4db94011d3	1018	* @arg TIM_CLOCKDIVISION_DIV2
sahilmgandhi	18:6a4db94011d3	1019	* @arg TIM_CLOCKDIVISION_DIV4
sahilmgandhi	18:6a4db94011d3	1020	* @retval None
sahilmgandhi	18:6a4db94011d3	1021	*/
sahilmgandhi	18:6a4db94011d3	1022	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
sahilmgandhi	18:6a4db94011d3	1023	do{ \
sahilmgandhi	18:6a4db94011d3	1024	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
sahilmgandhi	18:6a4db94011d3	1025	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
sahilmgandhi	18:6a4db94011d3	1026	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
sahilmgandhi	18:6a4db94011d3	1027	} while(0)
sahilmgandhi	18:6a4db94011d3	1028	/**
sahilmgandhi	18:6a4db94011d3	1029	* @brief Gets the TIM Clock Division value on runtime
sahilmgandhi	18:6a4db94011d3	1030	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	1031	* @retval None
sahilmgandhi	18:6a4db94011d3	1032	*/
sahilmgandhi	18:6a4db94011d3	1033	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
sahilmgandhi	18:6a4db94011d3	1034
sahilmgandhi	18:6a4db94011d3	1035	/**
sahilmgandhi	18:6a4db94011d3	1036	* @brief Sets the TIM Input Capture prescaler on runtime without calling
sahilmgandhi	18:6a4db94011d3	1037	* another time HAL_TIM_IC_ConfigChannel() function.
sahilmgandhi	18:6a4db94011d3	1038	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	1039	* @param __CHANNEL__ : TIM Channels to be configured.
sahilmgandhi	18:6a4db94011d3	1040	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1041	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1042	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1043	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1044	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1045	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
sahilmgandhi	18:6a4db94011d3	1046	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1047	* @arg TIM_ICPSC_DIV1: no prescaler
sahilmgandhi	18:6a4db94011d3	1048	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
sahilmgandhi	18:6a4db94011d3	1049	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
sahilmgandhi	18:6a4db94011d3	1050	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
sahilmgandhi	18:6a4db94011d3	1051	* @retval None
sahilmgandhi	18:6a4db94011d3	1052	*/
sahilmgandhi	18:6a4db94011d3	1053	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
sahilmgandhi	18:6a4db94011d3	1054	do{ \
sahilmgandhi	18:6a4db94011d3	1055	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
sahilmgandhi	18:6a4db94011d3	1056	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
sahilmgandhi	18:6a4db94011d3	1057	} while(0)
sahilmgandhi	18:6a4db94011d3	1058
sahilmgandhi	18:6a4db94011d3	1059	/**
sahilmgandhi	18:6a4db94011d3	1060	* @brief Gets the TIM Input Capture prescaler on runtime
sahilmgandhi	18:6a4db94011d3	1061	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	1062	* @param __CHANNEL__ : TIM Channels to be configured.
sahilmgandhi	18:6a4db94011d3	1063	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1064	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
sahilmgandhi	18:6a4db94011d3	1065	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
sahilmgandhi	18:6a4db94011d3	1066	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
sahilmgandhi	18:6a4db94011d3	1067	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
sahilmgandhi	18:6a4db94011d3	1068	* @retval None
sahilmgandhi	18:6a4db94011d3	1069	*/
sahilmgandhi	18:6a4db94011d3	1070	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
sahilmgandhi	18:6a4db94011d3	1071	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
sahilmgandhi	18:6a4db94011d3	1072	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
sahilmgandhi	18:6a4db94011d3	1073	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
sahilmgandhi	18:6a4db94011d3	1074	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
sahilmgandhi	18:6a4db94011d3	1075
sahilmgandhi	18:6a4db94011d3	1076	/**
sahilmgandhi	18:6a4db94011d3	1077	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
sahilmgandhi	18:6a4db94011d3	1078	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	1079	* @note When the USR bit of the TIMx_CR1 register is set, only counter
sahilmgandhi	18:6a4db94011d3	1080	* overflow/underflow generates an update interrupt or DMA request (if
sahilmgandhi	18:6a4db94011d3	1081	* enabled)
sahilmgandhi	18:6a4db94011d3	1082	* @retval None
sahilmgandhi	18:6a4db94011d3	1083	*/
sahilmgandhi	18:6a4db94011d3	1084	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
sahilmgandhi	18:6a4db94011d3	1085	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
sahilmgandhi	18:6a4db94011d3	1086
sahilmgandhi	18:6a4db94011d3	1087	/**
sahilmgandhi	18:6a4db94011d3	1088	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
sahilmgandhi	18:6a4db94011d3	1089	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	1090	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
sahilmgandhi	18:6a4db94011d3	1091	* following events generate an update interrupt or DMA request (if
sahilmgandhi	18:6a4db94011d3	1092	* enabled):
sahilmgandhi	18:6a4db94011d3	1093	* _ Counter overflow/underflow
sahilmgandhi	18:6a4db94011d3	1094	* _ Setting the UG bit
sahilmgandhi	18:6a4db94011d3	1095	* _ Update generation through the slave mode controller
sahilmgandhi	18:6a4db94011d3	1096	* @retval None
sahilmgandhi	18:6a4db94011d3	1097	*/
sahilmgandhi	18:6a4db94011d3	1098	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
sahilmgandhi	18:6a4db94011d3	1099	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
sahilmgandhi	18:6a4db94011d3	1100
sahilmgandhi	18:6a4db94011d3	1101	/**
sahilmgandhi	18:6a4db94011d3	1102	* @brief Sets the TIM Capture x input polarity on runtime.
sahilmgandhi	18:6a4db94011d3	1103	* @param __HANDLE__: TIM handle.
sahilmgandhi	18:6a4db94011d3	1104	* @param __CHANNEL__: TIM Channels to be configured.
sahilmgandhi	18:6a4db94011d3	1105	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1106	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
sahilmgandhi	18:6a4db94011d3	1107	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
sahilmgandhi	18:6a4db94011d3	1108	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
sahilmgandhi	18:6a4db94011d3	1109	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
sahilmgandhi	18:6a4db94011d3	1110	* @param __POLARITY__: Polarity for TIx source
sahilmgandhi	18:6a4db94011d3	1111	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
sahilmgandhi	18:6a4db94011d3	1112	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
sahilmgandhi	18:6a4db94011d3	1113	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
sahilmgandhi	18:6a4db94011d3	1114	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
sahilmgandhi	18:6a4db94011d3	1115	* @retval None
sahilmgandhi	18:6a4db94011d3	1116	*/
sahilmgandhi	18:6a4db94011d3	1117	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
sahilmgandhi	18:6a4db94011d3	1118	do{ \
sahilmgandhi	18:6a4db94011d3	1119	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
sahilmgandhi	18:6a4db94011d3	1120	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
sahilmgandhi	18:6a4db94011d3	1121	}while(0)
sahilmgandhi	18:6a4db94011d3	1122	/**
sahilmgandhi	18:6a4db94011d3	1123	* @}
sahilmgandhi	18:6a4db94011d3	1124	*/
sahilmgandhi	18:6a4db94011d3	1125
sahilmgandhi	18:6a4db94011d3	1126	/* Include TIM HAL Extension module */
sahilmgandhi	18:6a4db94011d3	1127	#include "stm32f4xx_hal_tim_ex.h"
sahilmgandhi	18:6a4db94011d3	1128
sahilmgandhi	18:6a4db94011d3	1129	/* Exported functions --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1130	/** @addtogroup TIM_Exported_Functions
sahilmgandhi	18:6a4db94011d3	1131	* @{
sahilmgandhi	18:6a4db94011d3	1132	*/
sahilmgandhi	18:6a4db94011d3	1133
sahilmgandhi	18:6a4db94011d3	1134	/** @addtogroup TIM_Exported_Functions_Group1
sahilmgandhi	18:6a4db94011d3	1135	* @{
sahilmgandhi	18:6a4db94011d3	1136	*/
sahilmgandhi	18:6a4db94011d3	1137
sahilmgandhi	18:6a4db94011d3	1138	/* Time Base functions ********************************************************/
sahilmgandhi	18:6a4db94011d3	1139	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1140	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1141	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1142	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1143	/* Blocking mode: Polling */
sahilmgandhi	18:6a4db94011d3	1144	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1145	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1146	/* Non-Blocking mode: Interrupt */
sahilmgandhi	18:6a4db94011d3	1147	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1148	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1149	/* Non-Blocking mode: DMA */
sahilmgandhi	18:6a4db94011d3	1150	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
sahilmgandhi	18:6a4db94011d3	1151	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1152	/**
sahilmgandhi	18:6a4db94011d3	1153	* @}
sahilmgandhi	18:6a4db94011d3	1154	*/
sahilmgandhi	18:6a4db94011d3	1155
sahilmgandhi	18:6a4db94011d3	1156	/** @addtogroup TIM_Exported_Functions_Group2
sahilmgandhi	18:6a4db94011d3	1157	* @{
sahilmgandhi	18:6a4db94011d3	1158	*/
sahilmgandhi	18:6a4db94011d3	1159	/* Timer Output Compare functions **********************************************/
sahilmgandhi	18:6a4db94011d3	1160	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1161	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1162	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1163	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1164	/* Blocking mode: Polling */
sahilmgandhi	18:6a4db94011d3	1165	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1166	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1167	/* Non-Blocking mode: Interrupt */
sahilmgandhi	18:6a4db94011d3	1168	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1169	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1170	/* Non-Blocking mode: DMA */
sahilmgandhi	18:6a4db94011d3	1171	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
sahilmgandhi	18:6a4db94011d3	1172	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1173
sahilmgandhi	18:6a4db94011d3	1174	/**
sahilmgandhi	18:6a4db94011d3	1175	* @}
sahilmgandhi	18:6a4db94011d3	1176	*/
sahilmgandhi	18:6a4db94011d3	1177
sahilmgandhi	18:6a4db94011d3	1178	/** @addtogroup TIM_Exported_Functions_Group3
sahilmgandhi	18:6a4db94011d3	1179	* @{
sahilmgandhi	18:6a4db94011d3	1180	*/
sahilmgandhi	18:6a4db94011d3	1181	/* Timer PWM functions *********************************************************/
sahilmgandhi	18:6a4db94011d3	1182	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1183	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1184	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1185	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1186	/* Blocking mode: Polling */
sahilmgandhi	18:6a4db94011d3	1187	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1188	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1189	/* Non-Blocking mode: Interrupt */
sahilmgandhi	18:6a4db94011d3	1190	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1191	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1192	/* Non-Blocking mode: DMA */
sahilmgandhi	18:6a4db94011d3	1193	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
sahilmgandhi	18:6a4db94011d3	1194	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1195
sahilmgandhi	18:6a4db94011d3	1196	/**
sahilmgandhi	18:6a4db94011d3	1197	* @}
sahilmgandhi	18:6a4db94011d3	1198	*/
sahilmgandhi	18:6a4db94011d3	1199
sahilmgandhi	18:6a4db94011d3	1200	/** @addtogroup TIM_Exported_Functions_Group4
sahilmgandhi	18:6a4db94011d3	1201	* @{
sahilmgandhi	18:6a4db94011d3	1202	*/
sahilmgandhi	18:6a4db94011d3	1203	/* Timer Input Capture functions ***********************************************/
sahilmgandhi	18:6a4db94011d3	1204	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1205	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1206	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1207	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1208	/* Blocking mode: Polling */
sahilmgandhi	18:6a4db94011d3	1209	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1210	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1211	/* Non-Blocking mode: Interrupt */
sahilmgandhi	18:6a4db94011d3	1212	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1213	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1214	/* Non-Blocking mode: DMA */
sahilmgandhi	18:6a4db94011d3	1215	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
sahilmgandhi	18:6a4db94011d3	1216	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1217
sahilmgandhi	18:6a4db94011d3	1218	/**
sahilmgandhi	18:6a4db94011d3	1219	* @}
sahilmgandhi	18:6a4db94011d3	1220	*/
sahilmgandhi	18:6a4db94011d3	1221
sahilmgandhi	18:6a4db94011d3	1222	/** @addtogroup TIM_Exported_Functions_Group5
sahilmgandhi	18:6a4db94011d3	1223	* @{
sahilmgandhi	18:6a4db94011d3	1224	*/
sahilmgandhi	18:6a4db94011d3	1225	/* Timer One Pulse functions ***************************************************/
sahilmgandhi	18:6a4db94011d3	1226	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
sahilmgandhi	18:6a4db94011d3	1227	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1228	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1229	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1230	/* Blocking mode: Polling */
sahilmgandhi	18:6a4db94011d3	1231	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
sahilmgandhi	18:6a4db94011d3	1232	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
sahilmgandhi	18:6a4db94011d3	1233
sahilmgandhi	18:6a4db94011d3	1234	/* Non-Blocking mode: Interrupt */
sahilmgandhi	18:6a4db94011d3	1235	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
sahilmgandhi	18:6a4db94011d3	1236	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
sahilmgandhi	18:6a4db94011d3	1237
sahilmgandhi	18:6a4db94011d3	1238	/**
sahilmgandhi	18:6a4db94011d3	1239	* @}
sahilmgandhi	18:6a4db94011d3	1240	*/
sahilmgandhi	18:6a4db94011d3	1241
sahilmgandhi	18:6a4db94011d3	1242	/** @addtogroup TIM_Exported_Functions_Group6
sahilmgandhi	18:6a4db94011d3	1243	* @{
sahilmgandhi	18:6a4db94011d3	1244	*/
sahilmgandhi	18:6a4db94011d3	1245	/* Timer Encoder functions *****************************************************/
sahilmgandhi	18:6a4db94011d3	1246	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
sahilmgandhi	18:6a4db94011d3	1247	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1248	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1249	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1250	/* Blocking mode: Polling */
sahilmgandhi	18:6a4db94011d3	1251	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1252	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1253	/* Non-Blocking mode: Interrupt */
sahilmgandhi	18:6a4db94011d3	1254	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1255	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1256	/* Non-Blocking mode: DMA */
sahilmgandhi	18:6a4db94011d3	1257	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
sahilmgandhi	18:6a4db94011d3	1258	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1259
sahilmgandhi	18:6a4db94011d3	1260	/**
sahilmgandhi	18:6a4db94011d3	1261	* @}
sahilmgandhi	18:6a4db94011d3	1262	*/
sahilmgandhi	18:6a4db94011d3	1263
sahilmgandhi	18:6a4db94011d3	1264	/** @addtogroup TIM_Exported_Functions_Group7
sahilmgandhi	18:6a4db94011d3	1265	* @{
sahilmgandhi	18:6a4db94011d3	1266	*/
sahilmgandhi	18:6a4db94011d3	1267	/* Interrupt Handler functions **********************************************/
sahilmgandhi	18:6a4db94011d3	1268	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1269
sahilmgandhi	18:6a4db94011d3	1270	/**
sahilmgandhi	18:6a4db94011d3	1271	* @}
sahilmgandhi	18:6a4db94011d3	1272	*/
sahilmgandhi	18:6a4db94011d3	1273
sahilmgandhi	18:6a4db94011d3	1274	/** @addtogroup TIM_Exported_Functions_Group8
sahilmgandhi	18:6a4db94011d3	1275	* @{
sahilmgandhi	18:6a4db94011d3	1276	*/
sahilmgandhi	18:6a4db94011d3	1277	/* Control functions *********************************************************/
sahilmgandhi	18:6a4db94011d3	1278	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1279	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1280	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1281	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
sahilmgandhi	18:6a4db94011d3	1282	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1283	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
sahilmgandhi	18:6a4db94011d3	1284	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
sahilmgandhi	18:6a4db94011d3	1285	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
sahilmgandhi	18:6a4db94011d3	1286	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
sahilmgandhi	18:6a4db94011d3	1287	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
sahilmgandhi	18:6a4db94011d3	1288	uint32_t *BurstBuffer, uint32_t BurstLength);
sahilmgandhi	18:6a4db94011d3	1289	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
sahilmgandhi	18:6a4db94011d3	1290	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
sahilmgandhi	18:6a4db94011d3	1291	uint32_t *BurstBuffer, uint32_t BurstLength);
sahilmgandhi	18:6a4db94011d3	1292	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
sahilmgandhi	18:6a4db94011d3	1293	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
sahilmgandhi	18:6a4db94011d3	1294	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
sahilmgandhi	18:6a4db94011d3	1295
sahilmgandhi	18:6a4db94011d3	1296	/**
sahilmgandhi	18:6a4db94011d3	1297	* @}
sahilmgandhi	18:6a4db94011d3	1298	*/
sahilmgandhi	18:6a4db94011d3	1299
sahilmgandhi	18:6a4db94011d3	1300	/** @addtogroup TIM_Exported_Functions_Group9
sahilmgandhi	18:6a4db94011d3	1301	* @{
sahilmgandhi	18:6a4db94011d3	1302	*/
sahilmgandhi	18:6a4db94011d3	1303	/* Callback in non blocking modes (Interrupt and DMA) *************************/
sahilmgandhi	18:6a4db94011d3	1304	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1305	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1306	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1307	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1308	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1309	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1310
sahilmgandhi	18:6a4db94011d3	1311	/**
sahilmgandhi	18:6a4db94011d3	1312	* @}
sahilmgandhi	18:6a4db94011d3	1313	*/
sahilmgandhi	18:6a4db94011d3	1314
sahilmgandhi	18:6a4db94011d3	1315	/** @addtogroup TIM_Exported_Functions_Group10
sahilmgandhi	18:6a4db94011d3	1316	* @{
sahilmgandhi	18:6a4db94011d3	1317	*/
sahilmgandhi	18:6a4db94011d3	1318	/* Peripheral State functions **************************************************/
sahilmgandhi	18:6a4db94011d3	1319	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1320	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1321	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1322	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1323	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1324	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
sahilmgandhi	18:6a4db94011d3	1325
sahilmgandhi	18:6a4db94011d3	1326	/**
sahilmgandhi	18:6a4db94011d3	1327	* @}
sahilmgandhi	18:6a4db94011d3	1328	*/
sahilmgandhi	18:6a4db94011d3	1329
sahilmgandhi	18:6a4db94011d3	1330	/**
sahilmgandhi	18:6a4db94011d3	1331	* @}
sahilmgandhi	18:6a4db94011d3	1332	*/
sahilmgandhi	18:6a4db94011d3	1333
sahilmgandhi	18:6a4db94011d3	1334	/* Private macros ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1335	/** @defgroup TIM_Private_Macros TIM Private Macros
sahilmgandhi	18:6a4db94011d3	1336	* @{
sahilmgandhi	18:6a4db94011d3	1337	*/
sahilmgandhi	18:6a4db94011d3	1338
sahilmgandhi	18:6a4db94011d3	1339	/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
sahilmgandhi	18:6a4db94011d3	1340	* @{
sahilmgandhi	18:6a4db94011d3	1341	*/
sahilmgandhi	18:6a4db94011d3	1342	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
sahilmgandhi	18:6a4db94011d3	1343	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
sahilmgandhi	18:6a4db94011d3	1344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
sahilmgandhi	18:6a4db94011d3	1345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
sahilmgandhi	18:6a4db94011d3	1346	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
sahilmgandhi	18:6a4db94011d3	1347
sahilmgandhi	18:6a4db94011d3	1348	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
sahilmgandhi	18:6a4db94011d3	1349	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
sahilmgandhi	18:6a4db94011d3	1350	((DIV) == TIM_CLOCKDIVISION_DIV4))
sahilmgandhi	18:6a4db94011d3	1351
sahilmgandhi	18:6a4db94011d3	1352	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
sahilmgandhi	18:6a4db94011d3	1353	((MODE) == TIM_OCMODE_PWM2))
sahilmgandhi	18:6a4db94011d3	1354
sahilmgandhi	18:6a4db94011d3	1355	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
sahilmgandhi	18:6a4db94011d3	1356	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
sahilmgandhi	18:6a4db94011d3	1357	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
sahilmgandhi	18:6a4db94011d3	1358	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1359	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
sahilmgandhi	18:6a4db94011d3	1360	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
sahilmgandhi	18:6a4db94011d3	1361
sahilmgandhi	18:6a4db94011d3	1362	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1363	((STATE) == TIM_OCFAST_ENABLE))
sahilmgandhi	18:6a4db94011d3	1364
sahilmgandhi	18:6a4db94011d3	1365	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
sahilmgandhi	18:6a4db94011d3	1366	((POLARITY) == TIM_OCPOLARITY_LOW))
sahilmgandhi	18:6a4db94011d3	1367
sahilmgandhi	18:6a4db94011d3	1368	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
sahilmgandhi	18:6a4db94011d3	1369	((POLARITY) == TIM_OCNPOLARITY_LOW))
sahilmgandhi	18:6a4db94011d3	1370
sahilmgandhi	18:6a4db94011d3	1371	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
sahilmgandhi	18:6a4db94011d3	1372	((STATE) == TIM_OCIDLESTATE_RESET))
sahilmgandhi	18:6a4db94011d3	1373
sahilmgandhi	18:6a4db94011d3	1374	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
sahilmgandhi	18:6a4db94011d3	1375	((STATE) == TIM_OCNIDLESTATE_RESET))
sahilmgandhi	18:6a4db94011d3	1376
sahilmgandhi	18:6a4db94011d3	1377	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
sahilmgandhi	18:6a4db94011d3	1378	((CHANNEL) == TIM_CHANNEL_2) \|\| \
sahilmgandhi	18:6a4db94011d3	1379	((CHANNEL) == TIM_CHANNEL_3) \|\| \
sahilmgandhi	18:6a4db94011d3	1380	((CHANNEL) == TIM_CHANNEL_4) \|\| \
sahilmgandhi	18:6a4db94011d3	1381	((CHANNEL) == TIM_CHANNEL_ALL))
sahilmgandhi	18:6a4db94011d3	1382
sahilmgandhi	18:6a4db94011d3	1383	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
sahilmgandhi	18:6a4db94011d3	1384	((CHANNEL) == TIM_CHANNEL_2))
sahilmgandhi	18:6a4db94011d3	1385
sahilmgandhi	18:6a4db94011d3	1386	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
sahilmgandhi	18:6a4db94011d3	1387	((CHANNEL) == TIM_CHANNEL_2) \|\| \
sahilmgandhi	18:6a4db94011d3	1388	((CHANNEL) == TIM_CHANNEL_3))
sahilmgandhi	18:6a4db94011d3	1389
sahilmgandhi	18:6a4db94011d3	1390	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
sahilmgandhi	18:6a4db94011d3	1391	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
sahilmgandhi	18:6a4db94011d3	1392	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
sahilmgandhi	18:6a4db94011d3	1393
sahilmgandhi	18:6a4db94011d3	1394	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
sahilmgandhi	18:6a4db94011d3	1395	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
sahilmgandhi	18:6a4db94011d3	1396	((SELECTION) == TIM_ICSELECTION_TRC))
sahilmgandhi	18:6a4db94011d3	1397
sahilmgandhi	18:6a4db94011d3	1398	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
sahilmgandhi	18:6a4db94011d3	1399	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
sahilmgandhi	18:6a4db94011d3	1400	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
sahilmgandhi	18:6a4db94011d3	1401	((PRESCALER) == TIM_ICPSC_DIV8))
sahilmgandhi	18:6a4db94011d3	1402
sahilmgandhi	18:6a4db94011d3	1403	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1404	((MODE) == TIM_OPMODE_REPETITIVE))
sahilmgandhi	18:6a4db94011d3	1405
sahilmgandhi	18:6a4db94011d3	1406	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
sahilmgandhi	18:6a4db94011d3	1407
sahilmgandhi	18:6a4db94011d3	1408	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
sahilmgandhi	18:6a4db94011d3	1409	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
sahilmgandhi	18:6a4db94011d3	1410	((MODE) == TIM_ENCODERMODE_TI12))
sahilmgandhi	18:6a4db94011d3	1411
sahilmgandhi	18:6a4db94011d3	1412	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
sahilmgandhi	18:6a4db94011d3	1413
sahilmgandhi	18:6a4db94011d3	1414	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
sahilmgandhi	18:6a4db94011d3	1415	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
sahilmgandhi	18:6a4db94011d3	1416	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
sahilmgandhi	18:6a4db94011d3	1417	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
sahilmgandhi	18:6a4db94011d3	1418	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
sahilmgandhi	18:6a4db94011d3	1419	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
sahilmgandhi	18:6a4db94011d3	1420	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
sahilmgandhi	18:6a4db94011d3	1421	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
sahilmgandhi	18:6a4db94011d3	1422	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
sahilmgandhi	18:6a4db94011d3	1423	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
sahilmgandhi	18:6a4db94011d3	1424
sahilmgandhi	18:6a4db94011d3	1425	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
sahilmgandhi	18:6a4db94011d3	1426	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
sahilmgandhi	18:6a4db94011d3	1427	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
sahilmgandhi	18:6a4db94011d3	1428	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
sahilmgandhi	18:6a4db94011d3	1429	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
sahilmgandhi	18:6a4db94011d3	1430
sahilmgandhi	18:6a4db94011d3	1431	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
sahilmgandhi	18:6a4db94011d3	1432	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
sahilmgandhi	18:6a4db94011d3	1433	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
sahilmgandhi	18:6a4db94011d3	1434	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
sahilmgandhi	18:6a4db94011d3	1435
sahilmgandhi	18:6a4db94011d3	1436	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
sahilmgandhi	18:6a4db94011d3	1437
sahilmgandhi	18:6a4db94011d3	1438	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
sahilmgandhi	18:6a4db94011d3	1439	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
sahilmgandhi	18:6a4db94011d3	1440
sahilmgandhi	18:6a4db94011d3	1441	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
sahilmgandhi	18:6a4db94011d3	1442	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
sahilmgandhi	18:6a4db94011d3	1443
sahilmgandhi	18:6a4db94011d3	1444	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
sahilmgandhi	18:6a4db94011d3	1445	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
sahilmgandhi	18:6a4db94011d3	1446	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
sahilmgandhi	18:6a4db94011d3	1447	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
sahilmgandhi	18:6a4db94011d3	1448
sahilmgandhi	18:6a4db94011d3	1449	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
sahilmgandhi	18:6a4db94011d3	1450
sahilmgandhi	18:6a4db94011d3	1451	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1452	((STATE) == TIM_OSSR_DISABLE))
sahilmgandhi	18:6a4db94011d3	1453
sahilmgandhi	18:6a4db94011d3	1454	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1455	((STATE) == TIM_OSSI_DISABLE))
sahilmgandhi	18:6a4db94011d3	1456
sahilmgandhi	18:6a4db94011d3	1457	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
sahilmgandhi	18:6a4db94011d3	1458	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
sahilmgandhi	18:6a4db94011d3	1459	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
sahilmgandhi	18:6a4db94011d3	1460	((LEVEL) == TIM_LOCKLEVEL_3))
sahilmgandhi	18:6a4db94011d3	1461
sahilmgandhi	18:6a4db94011d3	1462	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1463	((STATE) == TIM_BREAK_DISABLE))
sahilmgandhi	18:6a4db94011d3	1464
sahilmgandhi	18:6a4db94011d3	1465	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
sahilmgandhi	18:6a4db94011d3	1466	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
sahilmgandhi	18:6a4db94011d3	1467
sahilmgandhi	18:6a4db94011d3	1468	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1469	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
sahilmgandhi	18:6a4db94011d3	1470
sahilmgandhi	18:6a4db94011d3	1471	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
sahilmgandhi	18:6a4db94011d3	1472	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1473	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
sahilmgandhi	18:6a4db94011d3	1474	((SOURCE) == TIM_TRGO_OC1) \|\| \
sahilmgandhi	18:6a4db94011d3	1475	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
sahilmgandhi	18:6a4db94011d3	1476	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
sahilmgandhi	18:6a4db94011d3	1477	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
sahilmgandhi	18:6a4db94011d3	1478	((SOURCE) == TIM_TRGO_OC4REF))
sahilmgandhi	18:6a4db94011d3	1479
sahilmgandhi	18:6a4db94011d3	1480	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1481	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
sahilmgandhi	18:6a4db94011d3	1482	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
sahilmgandhi	18:6a4db94011d3	1483	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
sahilmgandhi	18:6a4db94011d3	1484	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
sahilmgandhi	18:6a4db94011d3	1485
sahilmgandhi	18:6a4db94011d3	1486	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
sahilmgandhi	18:6a4db94011d3	1487	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
sahilmgandhi	18:6a4db94011d3	1488
sahilmgandhi	18:6a4db94011d3	1489	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
sahilmgandhi	18:6a4db94011d3	1490	((SELECTION) == TIM_TS_ITR1) \|\| \
sahilmgandhi	18:6a4db94011d3	1491	((SELECTION) == TIM_TS_ITR2) \|\| \
sahilmgandhi	18:6a4db94011d3	1492	((SELECTION) == TIM_TS_ITR3) \|\| \
sahilmgandhi	18:6a4db94011d3	1493	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
sahilmgandhi	18:6a4db94011d3	1494	((SELECTION) == TIM_TS_TI1FP1) \|\| \
sahilmgandhi	18:6a4db94011d3	1495	((SELECTION) == TIM_TS_TI2FP2) \|\| \
sahilmgandhi	18:6a4db94011d3	1496	((SELECTION) == TIM_TS_ETRF))
sahilmgandhi	18:6a4db94011d3	1497
sahilmgandhi	18:6a4db94011d3	1498	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
sahilmgandhi	18:6a4db94011d3	1499	((SELECTION) == TIM_TS_ITR1) \|\| \
sahilmgandhi	18:6a4db94011d3	1500	((SELECTION) == TIM_TS_ITR2) \|\| \
sahilmgandhi	18:6a4db94011d3	1501	((SELECTION) == TIM_TS_ITR3) \|\| \
sahilmgandhi	18:6a4db94011d3	1502	((SELECTION) == TIM_TS_NONE))
sahilmgandhi	18:6a4db94011d3	1503
sahilmgandhi	18:6a4db94011d3	1504	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
sahilmgandhi	18:6a4db94011d3	1505	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
sahilmgandhi	18:6a4db94011d3	1506	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
sahilmgandhi	18:6a4db94011d3	1507	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
sahilmgandhi	18:6a4db94011d3	1508	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
sahilmgandhi	18:6a4db94011d3	1509
sahilmgandhi	18:6a4db94011d3	1510	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
sahilmgandhi	18:6a4db94011d3	1511	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
sahilmgandhi	18:6a4db94011d3	1512	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
sahilmgandhi	18:6a4db94011d3	1513	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
sahilmgandhi	18:6a4db94011d3	1514
sahilmgandhi	18:6a4db94011d3	1515	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
sahilmgandhi	18:6a4db94011d3	1516
sahilmgandhi	18:6a4db94011d3	1517	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
sahilmgandhi	18:6a4db94011d3	1518	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
sahilmgandhi	18:6a4db94011d3	1519
sahilmgandhi	18:6a4db94011d3	1520	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
sahilmgandhi	18:6a4db94011d3	1521	((BASE) == TIM_DMABASE_CR2) \|\| \
sahilmgandhi	18:6a4db94011d3	1522	((BASE) == TIM_DMABASE_SMCR) \|\| \
sahilmgandhi	18:6a4db94011d3	1523	((BASE) == TIM_DMABASE_DIER) \|\| \
sahilmgandhi	18:6a4db94011d3	1524	((BASE) == TIM_DMABASE_SR) \|\| \
sahilmgandhi	18:6a4db94011d3	1525	((BASE) == TIM_DMABASE_EGR) \|\| \
sahilmgandhi	18:6a4db94011d3	1526	((BASE) == TIM_DMABASE_CCMR1) \|\| \
sahilmgandhi	18:6a4db94011d3	1527	((BASE) == TIM_DMABASE_CCMR2) \|\| \
sahilmgandhi	18:6a4db94011d3	1528	((BASE) == TIM_DMABASE_CCER) \|\| \
sahilmgandhi	18:6a4db94011d3	1529	((BASE) == TIM_DMABASE_CNT) \|\| \
sahilmgandhi	18:6a4db94011d3	1530	((BASE) == TIM_DMABASE_PSC) \|\| \
sahilmgandhi	18:6a4db94011d3	1531	((BASE) == TIM_DMABASE_ARR) \|\| \
sahilmgandhi	18:6a4db94011d3	1532	((BASE) == TIM_DMABASE_RCR) \|\| \
sahilmgandhi	18:6a4db94011d3	1533	((BASE) == TIM_DMABASE_CCR1) \|\| \
sahilmgandhi	18:6a4db94011d3	1534	((BASE) == TIM_DMABASE_CCR2) \|\| \
sahilmgandhi	18:6a4db94011d3	1535	((BASE) == TIM_DMABASE_CCR3) \|\| \
sahilmgandhi	18:6a4db94011d3	1536	((BASE) == TIM_DMABASE_CCR4) \|\| \
sahilmgandhi	18:6a4db94011d3	1537	((BASE) == TIM_DMABASE_BDTR) \|\| \
sahilmgandhi	18:6a4db94011d3	1538	((BASE) == TIM_DMABASE_DCR) \|\| \
sahilmgandhi	18:6a4db94011d3	1539	((BASE) == TIM_DMABASE_OR))
sahilmgandhi	18:6a4db94011d3	1540
sahilmgandhi	18:6a4db94011d3	1541	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
sahilmgandhi	18:6a4db94011d3	1542	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1543	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1544	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1545	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1546	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1547	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1548	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1549	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1550	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1551	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1552	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1553	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1554	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1555	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1556	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1557	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
sahilmgandhi	18:6a4db94011d3	1558	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
sahilmgandhi	18:6a4db94011d3	1559
sahilmgandhi	18:6a4db94011d3	1560	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
sahilmgandhi	18:6a4db94011d3	1561	/**
sahilmgandhi	18:6a4db94011d3	1562	* @}
sahilmgandhi	18:6a4db94011d3	1563	*/
sahilmgandhi	18:6a4db94011d3	1564
sahilmgandhi	18:6a4db94011d3	1565	/** @defgroup TIM_Mask_Definitions TIM Mask Definition
sahilmgandhi	18:6a4db94011d3	1566	* @{
sahilmgandhi	18:6a4db94011d3	1567	*/
sahilmgandhi	18:6a4db94011d3	1568	/* The counter of a timer instance is disabled only if all the CCx and CCxN
sahilmgandhi	18:6a4db94011d3	1569	channels have been disabled */
sahilmgandhi	18:6a4db94011d3	1570	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
sahilmgandhi	18:6a4db94011d3	1571	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
sahilmgandhi	18:6a4db94011d3	1572	/**
sahilmgandhi	18:6a4db94011d3	1573	* @}
sahilmgandhi	18:6a4db94011d3	1574	*/
sahilmgandhi	18:6a4db94011d3	1575
sahilmgandhi	18:6a4db94011d3	1576	/**
sahilmgandhi	18:6a4db94011d3	1577	* @}
sahilmgandhi	18:6a4db94011d3	1578	*/
sahilmgandhi	18:6a4db94011d3	1579
sahilmgandhi	18:6a4db94011d3	1580	/* Private functions ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1581	/** @defgroup TIM_Private_Functions TIM Private Functions
sahilmgandhi	18:6a4db94011d3	1582	* @{
sahilmgandhi	18:6a4db94011d3	1583	*/
sahilmgandhi	18:6a4db94011d3	1584	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
sahilmgandhi	18:6a4db94011d3	1585	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
sahilmgandhi	18:6a4db94011d3	1586	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
sahilmgandhi	18:6a4db94011d3	1587	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	1588	void TIM_DMAError(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	1589	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi	18:6a4db94011d3	1590	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
sahilmgandhi	18:6a4db94011d3	1591	/**
sahilmgandhi	18:6a4db94011d3	1592	* @}
sahilmgandhi	18:6a4db94011d3	1593	*/
sahilmgandhi	18:6a4db94011d3	1594
sahilmgandhi	18:6a4db94011d3	1595	/**
sahilmgandhi	18:6a4db94011d3	1596	* @}
sahilmgandhi	18:6a4db94011d3	1597	*/
sahilmgandhi	18:6a4db94011d3	1598
sahilmgandhi	18:6a4db94011d3	1599	/**
sahilmgandhi	18:6a4db94011d3	1600	* @}
sahilmgandhi	18:6a4db94011d3	1601	*/
sahilmgandhi	18:6a4db94011d3	1602
sahilmgandhi	18:6a4db94011d3	1603	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	1604	}
sahilmgandhi	18:6a4db94011d3	1605	#endif
sahilmgandhi	18:6a4db94011d3	1606
sahilmgandhi	18:6a4db94011d3	1607	#endif /* __STM32F4xx_HAL_TIM_H */
sahilmgandhi	18:6a4db94011d3	1608
sahilmgandhi	18:6a4db94011d3	1609	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h@46:b156ef445742, 2017-06-03 (annotated)

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