MouseCode - Mouse code for the MacroRat

MacroRat » Code » MouseCode

Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f4xx_hal_rcc_ex.h
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.5.0
sahilmgandhi	18:6a4db94011d3	6	* @date 06-May-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief Header file of RCC HAL Extension module.
sahilmgandhi	18:6a4db94011d3	8	******************************************************************************
sahilmgandhi	18:6a4db94011d3	9	* @attention
sahilmgandhi	18:6a4db94011d3	10	*
sahilmgandhi	18:6a4db94011d3	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	12	*
sahilmgandhi	18:6a4db94011d3	13	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	14	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	15	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	16	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	18	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	19	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	21	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	22	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	23	*
sahilmgandhi	18:6a4db94011d3	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	34	*
sahilmgandhi	18:6a4db94011d3	35	******************************************************************************
sahilmgandhi	18:6a4db94011d3	36	*/
sahilmgandhi	18:6a4db94011d3	37
sahilmgandhi	18:6a4db94011d3	38	/* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
sahilmgandhi	18:6a4db94011d3	40	#define __STM32F4xx_HAL_RCC_EX_H
sahilmgandhi	18:6a4db94011d3	41
sahilmgandhi	18:6a4db94011d3	42	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	43	extern "C" {
sahilmgandhi	18:6a4db94011d3	44	#endif
sahilmgandhi	18:6a4db94011d3	45
sahilmgandhi	18:6a4db94011d3	46	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	47	#include "stm32f4xx_hal_def.h"
sahilmgandhi	18:6a4db94011d3	48
sahilmgandhi	18:6a4db94011d3	49	/** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	50	* @{
sahilmgandhi	18:6a4db94011d3	51	*/
sahilmgandhi	18:6a4db94011d3	52
sahilmgandhi	18:6a4db94011d3	53	/** @addtogroup RCCEx
sahilmgandhi	18:6a4db94011d3	54	* @{
sahilmgandhi	18:6a4db94011d3	55	*/
sahilmgandhi	18:6a4db94011d3	56
sahilmgandhi	18:6a4db94011d3	57	/* Exported types ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
sahilmgandhi	18:6a4db94011d3	59	* @{
sahilmgandhi	18:6a4db94011d3	60	*/
sahilmgandhi	18:6a4db94011d3	61
sahilmgandhi	18:6a4db94011d3	62	/**
sahilmgandhi	18:6a4db94011d3	63	* @brief RCC PLL configuration structure definition
sahilmgandhi	18:6a4db94011d3	64	*/
sahilmgandhi	18:6a4db94011d3	65	typedef struct
sahilmgandhi	18:6a4db94011d3	66	{
sahilmgandhi	18:6a4db94011d3	67	uint32_t PLLState; /*!< The new state of the PLL.
sahilmgandhi	18:6a4db94011d3	68	This parameter can be a value of @ref RCC_PLL_Config */
sahilmgandhi	18:6a4db94011d3	69
sahilmgandhi	18:6a4db94011d3	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
sahilmgandhi	18:6a4db94011d3	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
sahilmgandhi	18:6a4db94011d3	72
sahilmgandhi	18:6a4db94011d3	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
sahilmgandhi	18:6a4db94011d3	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
sahilmgandhi	18:6a4db94011d3	75
sahilmgandhi	18:6a4db94011d3	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
sahilmgandhi	18:6a4db94011d3	77	This parameter must be a number between Min_Data = 50 and Max_Data = 432
sahilmgandhi	18:6a4db94011d3	78	except for STM32F411xE devices where the Min_Data = 192 */
sahilmgandhi	18:6a4db94011d3	79
sahilmgandhi	18:6a4db94011d3	80	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
sahilmgandhi	18:6a4db94011d3	81	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
sahilmgandhi	18:6a4db94011d3	82
sahilmgandhi	18:6a4db94011d3	83	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
sahilmgandhi	18:6a4db94011d3	84	This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
sahilmgandhi	18:6a4db94011d3	85	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
sahilmgandhi	18:6a4db94011d3	86	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	87	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
sahilmgandhi	18:6a4db94011d3	88	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
sahilmgandhi	18:6a4db94011d3	89	and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
sahilmgandhi	18:6a4db94011d3	90	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
sahilmgandhi	18:6a4db94011d3	91	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	92	}RCC_PLLInitTypeDef;
sahilmgandhi	18:6a4db94011d3	93
sahilmgandhi	18:6a4db94011d3	94	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	95	/**
sahilmgandhi	18:6a4db94011d3	96	* @brief PLLI2S Clock structure definition
sahilmgandhi	18:6a4db94011d3	97	*/
sahilmgandhi	18:6a4db94011d3	98	typedef struct
sahilmgandhi	18:6a4db94011d3	99	{
sahilmgandhi	18:6a4db94011d3	100	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
sahilmgandhi	18:6a4db94011d3	101	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
sahilmgandhi	18:6a4db94011d3	102
sahilmgandhi	18:6a4db94011d3	103	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
sahilmgandhi	18:6a4db94011d3	104	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
sahilmgandhi	18:6a4db94011d3	105
sahilmgandhi	18:6a4db94011d3	106	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
sahilmgandhi	18:6a4db94011d3	107	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
sahilmgandhi	18:6a4db94011d3	108
sahilmgandhi	18:6a4db94011d3	109	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
sahilmgandhi	18:6a4db94011d3	110	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	111	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
sahilmgandhi	18:6a4db94011d3	112
sahilmgandhi	18:6a4db94011d3	113	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
sahilmgandhi	18:6a4db94011d3	114	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	115	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
sahilmgandhi	18:6a4db94011d3	116	}RCC_PLLI2SInitTypeDef;
sahilmgandhi	18:6a4db94011d3	117
sahilmgandhi	18:6a4db94011d3	118	/**
sahilmgandhi	18:6a4db94011d3	119	* @brief PLLSAI Clock structure definition
sahilmgandhi	18:6a4db94011d3	120	*/
sahilmgandhi	18:6a4db94011d3	121	typedef struct
sahilmgandhi	18:6a4db94011d3	122	{
sahilmgandhi	18:6a4db94011d3	123	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
sahilmgandhi	18:6a4db94011d3	124	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
sahilmgandhi	18:6a4db94011d3	125
sahilmgandhi	18:6a4db94011d3	126	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
sahilmgandhi	18:6a4db94011d3	127	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
sahilmgandhi	18:6a4db94011d3	128
sahilmgandhi	18:6a4db94011d3	129	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
sahilmgandhi	18:6a4db94011d3	130	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
sahilmgandhi	18:6a4db94011d3	131
sahilmgandhi	18:6a4db94011d3	132	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
sahilmgandhi	18:6a4db94011d3	133	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	134	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
sahilmgandhi	18:6a4db94011d3	135	}RCC_PLLSAIInitTypeDef;
sahilmgandhi	18:6a4db94011d3	136
sahilmgandhi	18:6a4db94011d3	137	/**
sahilmgandhi	18:6a4db94011d3	138	* @brief RCC extended clocks structure definition
sahilmgandhi	18:6a4db94011d3	139	*/
sahilmgandhi	18:6a4db94011d3	140	typedef struct
sahilmgandhi	18:6a4db94011d3	141	{
sahilmgandhi	18:6a4db94011d3	142	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
sahilmgandhi	18:6a4db94011d3	143	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
sahilmgandhi	18:6a4db94011d3	144
sahilmgandhi	18:6a4db94011d3	145	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
sahilmgandhi	18:6a4db94011d3	146	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
sahilmgandhi	18:6a4db94011d3	147
sahilmgandhi	18:6a4db94011d3	148	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
sahilmgandhi	18:6a4db94011d3	149	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
sahilmgandhi	18:6a4db94011d3	150
sahilmgandhi	18:6a4db94011d3	151	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
sahilmgandhi	18:6a4db94011d3	152	This parameter must be a number between Min_Data = 1 and Max_Data = 32
sahilmgandhi	18:6a4db94011d3	153	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
sahilmgandhi	18:6a4db94011d3	154
sahilmgandhi	18:6a4db94011d3	155	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
sahilmgandhi	18:6a4db94011d3	156	This parameter must be a number between Min_Data = 1 and Max_Data = 32
sahilmgandhi	18:6a4db94011d3	157	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
sahilmgandhi	18:6a4db94011d3	158
sahilmgandhi	18:6a4db94011d3	159	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	160	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
sahilmgandhi	18:6a4db94011d3	161
sahilmgandhi	18:6a4db94011d3	162	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	163	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
sahilmgandhi	18:6a4db94011d3	164
sahilmgandhi	18:6a4db94011d3	165	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	166	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
sahilmgandhi	18:6a4db94011d3	167
sahilmgandhi	18:6a4db94011d3	168	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	169	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
sahilmgandhi	18:6a4db94011d3	170
sahilmgandhi	18:6a4db94011d3	171	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	172	This parameter can be a value of @ref RCC_RTC_Clock_Source */
sahilmgandhi	18:6a4db94011d3	173
sahilmgandhi	18:6a4db94011d3	174	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	175	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
sahilmgandhi	18:6a4db94011d3	176
sahilmgandhi	18:6a4db94011d3	177	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	178	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
sahilmgandhi	18:6a4db94011d3	179
sahilmgandhi	18:6a4db94011d3	180	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	181	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
sahilmgandhi	18:6a4db94011d3	182
sahilmgandhi	18:6a4db94011d3	183	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	184	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
sahilmgandhi	18:6a4db94011d3	185
sahilmgandhi	18:6a4db94011d3	186	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
sahilmgandhi	18:6a4db94011d3	187	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
sahilmgandhi	18:6a4db94011d3	188
sahilmgandhi	18:6a4db94011d3	189	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	190	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
sahilmgandhi	18:6a4db94011d3	191	}RCC_PeriphCLKInitTypeDef;
sahilmgandhi	18:6a4db94011d3	192	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	193
sahilmgandhi	18:6a4db94011d3	194	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	195	/**
sahilmgandhi	18:6a4db94011d3	196	* @brief RCC extended clocks structure definition
sahilmgandhi	18:6a4db94011d3	197	*/
sahilmgandhi	18:6a4db94011d3	198	typedef struct
sahilmgandhi	18:6a4db94011d3	199	{
sahilmgandhi	18:6a4db94011d3	200	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
sahilmgandhi	18:6a4db94011d3	201	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
sahilmgandhi	18:6a4db94011d3	202
sahilmgandhi	18:6a4db94011d3	203	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	204	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
sahilmgandhi	18:6a4db94011d3	205
sahilmgandhi	18:6a4db94011d3	206	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	207	This parameter can be a value of @ref RCC_RTC_Clock_Source */
sahilmgandhi	18:6a4db94011d3	208
sahilmgandhi	18:6a4db94011d3	209	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	210	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
sahilmgandhi	18:6a4db94011d3	211
sahilmgandhi	18:6a4db94011d3	212	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	213	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
sahilmgandhi	18:6a4db94011d3	214
sahilmgandhi	18:6a4db94011d3	215	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	216	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
sahilmgandhi	18:6a4db94011d3	217	}RCC_PeriphCLKInitTypeDef;
sahilmgandhi	18:6a4db94011d3	218	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	219
sahilmgandhi	18:6a4db94011d3	220	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	221	/**
sahilmgandhi	18:6a4db94011d3	222	* @brief PLLI2S Clock structure definition
sahilmgandhi	18:6a4db94011d3	223	*/
sahilmgandhi	18:6a4db94011d3	224	typedef struct
sahilmgandhi	18:6a4db94011d3	225	{
sahilmgandhi	18:6a4db94011d3	226	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
sahilmgandhi	18:6a4db94011d3	227	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
sahilmgandhi	18:6a4db94011d3	228
sahilmgandhi	18:6a4db94011d3	229	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
sahilmgandhi	18:6a4db94011d3	230	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
sahilmgandhi	18:6a4db94011d3	231
sahilmgandhi	18:6a4db94011d3	232	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
sahilmgandhi	18:6a4db94011d3	233	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	234	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
sahilmgandhi	18:6a4db94011d3	235
sahilmgandhi	18:6a4db94011d3	236	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
sahilmgandhi	18:6a4db94011d3	237	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	238	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
sahilmgandhi	18:6a4db94011d3	239	}RCC_PLLI2SInitTypeDef;
sahilmgandhi	18:6a4db94011d3	240
sahilmgandhi	18:6a4db94011d3	241	/**
sahilmgandhi	18:6a4db94011d3	242	* @brief RCC extended clocks structure definition
sahilmgandhi	18:6a4db94011d3	243	*/
sahilmgandhi	18:6a4db94011d3	244	typedef struct
sahilmgandhi	18:6a4db94011d3	245	{
sahilmgandhi	18:6a4db94011d3	246	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
sahilmgandhi	18:6a4db94011d3	247	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
sahilmgandhi	18:6a4db94011d3	248
sahilmgandhi	18:6a4db94011d3	249	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
sahilmgandhi	18:6a4db94011d3	250	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
sahilmgandhi	18:6a4db94011d3	251
sahilmgandhi	18:6a4db94011d3	252	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	253	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
sahilmgandhi	18:6a4db94011d3	254
sahilmgandhi	18:6a4db94011d3	255	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	256	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
sahilmgandhi	18:6a4db94011d3	257
sahilmgandhi	18:6a4db94011d3	258	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	259	This parameter can be a value of @ref RCC_RTC_Clock_Source */
sahilmgandhi	18:6a4db94011d3	260
sahilmgandhi	18:6a4db94011d3	261	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	262	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
sahilmgandhi	18:6a4db94011d3	263
sahilmgandhi	18:6a4db94011d3	264	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	265	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
sahilmgandhi	18:6a4db94011d3	266
sahilmgandhi	18:6a4db94011d3	267	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
sahilmgandhi	18:6a4db94011d3	268	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
sahilmgandhi	18:6a4db94011d3	269
sahilmgandhi	18:6a4db94011d3	270	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection.
sahilmgandhi	18:6a4db94011d3	271	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
sahilmgandhi	18:6a4db94011d3	272
sahilmgandhi	18:6a4db94011d3	273	uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
sahilmgandhi	18:6a4db94011d3	274	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
sahilmgandhi	18:6a4db94011d3	275
sahilmgandhi	18:6a4db94011d3	276	uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	277	This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
sahilmgandhi	18:6a4db94011d3	278
sahilmgandhi	18:6a4db94011d3	279	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	280	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
sahilmgandhi	18:6a4db94011d3	281	}RCC_PeriphCLKInitTypeDef;
sahilmgandhi	18:6a4db94011d3	282	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	283
sahilmgandhi	18:6a4db94011d3	284	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	285	/**
sahilmgandhi	18:6a4db94011d3	286	* @brief PLLI2S Clock structure definition
sahilmgandhi	18:6a4db94011d3	287	*/
sahilmgandhi	18:6a4db94011d3	288	typedef struct
sahilmgandhi	18:6a4db94011d3	289	{
sahilmgandhi	18:6a4db94011d3	290	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
sahilmgandhi	18:6a4db94011d3	291	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	292	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
sahilmgandhi	18:6a4db94011d3	293
sahilmgandhi	18:6a4db94011d3	294	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
sahilmgandhi	18:6a4db94011d3	295	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	296	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
sahilmgandhi	18:6a4db94011d3	297
sahilmgandhi	18:6a4db94011d3	298	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
sahilmgandhi	18:6a4db94011d3	299	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	300	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
sahilmgandhi	18:6a4db94011d3	301	}RCC_PLLI2SInitTypeDef;
sahilmgandhi	18:6a4db94011d3	302
sahilmgandhi	18:6a4db94011d3	303	/**
sahilmgandhi	18:6a4db94011d3	304	* @brief PLLSAI Clock structure definition
sahilmgandhi	18:6a4db94011d3	305	*/
sahilmgandhi	18:6a4db94011d3	306	typedef struct
sahilmgandhi	18:6a4db94011d3	307	{
sahilmgandhi	18:6a4db94011d3	308	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
sahilmgandhi	18:6a4db94011d3	309	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	310	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
sahilmgandhi	18:6a4db94011d3	311	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	312	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
sahilmgandhi	18:6a4db94011d3	313	This parameter is only available in STM32F469xx/STM32F479xx devices.
sahilmgandhi	18:6a4db94011d3	314	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
sahilmgandhi	18:6a4db94011d3	315	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	316
sahilmgandhi	18:6a4db94011d3	317	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
sahilmgandhi	18:6a4db94011d3	318	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	319	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
sahilmgandhi	18:6a4db94011d3	320
sahilmgandhi	18:6a4db94011d3	321	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
sahilmgandhi	18:6a4db94011d3	322	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	323	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
sahilmgandhi	18:6a4db94011d3	324
sahilmgandhi	18:6a4db94011d3	325	}RCC_PLLSAIInitTypeDef;
sahilmgandhi	18:6a4db94011d3	326
sahilmgandhi	18:6a4db94011d3	327	/**
sahilmgandhi	18:6a4db94011d3	328	* @brief RCC extended clocks structure definition
sahilmgandhi	18:6a4db94011d3	329	*/
sahilmgandhi	18:6a4db94011d3	330	typedef struct
sahilmgandhi	18:6a4db94011d3	331	{
sahilmgandhi	18:6a4db94011d3	332	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
sahilmgandhi	18:6a4db94011d3	333	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
sahilmgandhi	18:6a4db94011d3	334
sahilmgandhi	18:6a4db94011d3	335	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
sahilmgandhi	18:6a4db94011d3	336	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
sahilmgandhi	18:6a4db94011d3	337
sahilmgandhi	18:6a4db94011d3	338	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
sahilmgandhi	18:6a4db94011d3	339	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
sahilmgandhi	18:6a4db94011d3	340
sahilmgandhi	18:6a4db94011d3	341	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
sahilmgandhi	18:6a4db94011d3	342	This parameter must be a number between Min_Data = 1 and Max_Data = 32
sahilmgandhi	18:6a4db94011d3	343	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
sahilmgandhi	18:6a4db94011d3	344
sahilmgandhi	18:6a4db94011d3	345	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
sahilmgandhi	18:6a4db94011d3	346	This parameter must be a number between Min_Data = 1 and Max_Data = 32
sahilmgandhi	18:6a4db94011d3	347	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
sahilmgandhi	18:6a4db94011d3	348
sahilmgandhi	18:6a4db94011d3	349	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
sahilmgandhi	18:6a4db94011d3	350	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
sahilmgandhi	18:6a4db94011d3	351
sahilmgandhi	18:6a4db94011d3	352	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
sahilmgandhi	18:6a4db94011d3	353	This parameter can be a value of @ref RCC_RTC_Clock_Source */
sahilmgandhi	18:6a4db94011d3	354
sahilmgandhi	18:6a4db94011d3	355	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
sahilmgandhi	18:6a4db94011d3	356	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
sahilmgandhi	18:6a4db94011d3	357	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	358	uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
sahilmgandhi	18:6a4db94011d3	359	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
sahilmgandhi	18:6a4db94011d3	360
sahilmgandhi	18:6a4db94011d3	361	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	362	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
sahilmgandhi	18:6a4db94011d3	363	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	364	}RCC_PeriphCLKInitTypeDef;
sahilmgandhi	18:6a4db94011d3	365
sahilmgandhi	18:6a4db94011d3	366	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	367
sahilmgandhi	18:6a4db94011d3	368	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
sahilmgandhi	18:6a4db94011d3	369	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	370	/**
sahilmgandhi	18:6a4db94011d3	371	* @brief PLLI2S Clock structure definition
sahilmgandhi	18:6a4db94011d3	372	*/
sahilmgandhi	18:6a4db94011d3	373	typedef struct
sahilmgandhi	18:6a4db94011d3	374	{
sahilmgandhi	18:6a4db94011d3	375	#if defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	376	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
sahilmgandhi	18:6a4db94011d3	377	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
sahilmgandhi	18:6a4db94011d3	378	#endif /* STM32F411xE */
sahilmgandhi	18:6a4db94011d3	379
sahilmgandhi	18:6a4db94011d3	380	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
sahilmgandhi	18:6a4db94011d3	381	This parameter must be a number between Min_Data = 50 and Max_Data = 432
sahilmgandhi	18:6a4db94011d3	382	Except for STM32F411xE devices where the Min_Data = 192.
sahilmgandhi	18:6a4db94011d3	383	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
sahilmgandhi	18:6a4db94011d3	384
sahilmgandhi	18:6a4db94011d3	385	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
sahilmgandhi	18:6a4db94011d3	386	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	387	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
sahilmgandhi	18:6a4db94011d3	388
sahilmgandhi	18:6a4db94011d3	389	}RCC_PLLI2SInitTypeDef;
sahilmgandhi	18:6a4db94011d3	390
sahilmgandhi	18:6a4db94011d3	391	/**
sahilmgandhi	18:6a4db94011d3	392	* @brief RCC extended clocks structure definition
sahilmgandhi	18:6a4db94011d3	393	*/
sahilmgandhi	18:6a4db94011d3	394	typedef struct
sahilmgandhi	18:6a4db94011d3	395	{
sahilmgandhi	18:6a4db94011d3	396	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
sahilmgandhi	18:6a4db94011d3	397	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
sahilmgandhi	18:6a4db94011d3	398
sahilmgandhi	18:6a4db94011d3	399	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
sahilmgandhi	18:6a4db94011d3	400	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
sahilmgandhi	18:6a4db94011d3	401
sahilmgandhi	18:6a4db94011d3	402	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
sahilmgandhi	18:6a4db94011d3	403	This parameter can be a value of @ref RCC_RTC_Clock_Source */
sahilmgandhi	18:6a4db94011d3	404	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	405	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
sahilmgandhi	18:6a4db94011d3	406	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
sahilmgandhi	18:6a4db94011d3	407	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
sahilmgandhi	18:6a4db94011d3	408	}RCC_PeriphCLKInitTypeDef;
sahilmgandhi	18:6a4db94011d3	409	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
sahilmgandhi	18:6a4db94011d3	410	/**
sahilmgandhi	18:6a4db94011d3	411	* @}
sahilmgandhi	18:6a4db94011d3	412	*/
sahilmgandhi	18:6a4db94011d3	413
sahilmgandhi	18:6a4db94011d3	414	/* Exported constants --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	415	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
sahilmgandhi	18:6a4db94011d3	416	* @{
sahilmgandhi	18:6a4db94011d3	417	*/
sahilmgandhi	18:6a4db94011d3	418
sahilmgandhi	18:6a4db94011d3	419	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
sahilmgandhi	18:6a4db94011d3	420	* @{
sahilmgandhi	18:6a4db94011d3	421	*/
sahilmgandhi	18:6a4db94011d3	422	/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	423	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	424	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	425	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	426	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	427	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	428	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000010U)
sahilmgandhi	18:6a4db94011d3	429	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000020U)
sahilmgandhi	18:6a4db94011d3	430	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000040U)
sahilmgandhi	18:6a4db94011d3	431	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000080U)
sahilmgandhi	18:6a4db94011d3	432	#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00000100U)
sahilmgandhi	18:6a4db94011d3	433	#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x00000200U)
sahilmgandhi	18:6a4db94011d3	434	#endif /* STM32F412Zx \|\| STM32F412Vx) \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	435	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	436
sahilmgandhi	18:6a4db94011d3	437	/------------------- Peripheral Clock source for STM32F410xx ----------------/
sahilmgandhi	18:6a4db94011d3	438	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	439	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	440	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	441	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	442	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	443	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010U)
sahilmgandhi	18:6a4db94011d3	444	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	445	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	446
sahilmgandhi	18:6a4db94011d3	447	/------------------- Peripheral Clock source for STM32F446xx ----------------/
sahilmgandhi	18:6a4db94011d3	448	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	449	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	450	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	451	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	452	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	453	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
sahilmgandhi	18:6a4db94011d3	454	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
sahilmgandhi	18:6a4db94011d3	455	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040U)
sahilmgandhi	18:6a4db94011d3	456	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080U)
sahilmgandhi	18:6a4db94011d3	457	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000100U)
sahilmgandhi	18:6a4db94011d3	458	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200U)
sahilmgandhi	18:6a4db94011d3	459	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400U)
sahilmgandhi	18:6a4db94011d3	460	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800U)
sahilmgandhi	18:6a4db94011d3	461	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	462	/-----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	463
sahilmgandhi	18:6a4db94011d3	464	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
sahilmgandhi	18:6a4db94011d3	465	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	466	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	467	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	468	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	469	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	470	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
sahilmgandhi	18:6a4db94011d3	471	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
sahilmgandhi	18:6a4db94011d3	472	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040U)
sahilmgandhi	18:6a4db94011d3	473	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00000080U)
sahilmgandhi	18:6a4db94011d3	474	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000100U)
sahilmgandhi	18:6a4db94011d3	475	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	476	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	477
sahilmgandhi	18:6a4db94011d3	478	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
sahilmgandhi	18:6a4db94011d3	479	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
sahilmgandhi	18:6a4db94011d3	480	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	481	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	482	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	483	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	484	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
sahilmgandhi	18:6a4db94011d3	485	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
sahilmgandhi	18:6a4db94011d3	486	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040U)
sahilmgandhi	18:6a4db94011d3	487	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
sahilmgandhi	18:6a4db94011d3	488	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	489
sahilmgandhi	18:6a4db94011d3	490	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
sahilmgandhi	18:6a4db94011d3	491	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
sahilmgandhi	18:6a4db94011d3	492	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	493	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	494	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	495	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	496	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
sahilmgandhi	18:6a4db94011d3	497	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	498	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	499	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
sahilmgandhi	18:6a4db94011d3	500	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	501	/**
sahilmgandhi	18:6a4db94011d3	502	* @}
sahilmgandhi	18:6a4db94011d3	503	*/
sahilmgandhi	18:6a4db94011d3	504	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
sahilmgandhi	18:6a4db94011d3	505	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
sahilmgandhi	18:6a4db94011d3	506	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
sahilmgandhi	18:6a4db94011d3	507	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	508	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	509	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
sahilmgandhi	18:6a4db94011d3	510	* @{
sahilmgandhi	18:6a4db94011d3	511	*/
sahilmgandhi	18:6a4db94011d3	512	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	513	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	514	/**
sahilmgandhi	18:6a4db94011d3	515	* @}
sahilmgandhi	18:6a4db94011d3	516	*/
sahilmgandhi	18:6a4db94011d3	517	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
sahilmgandhi	18:6a4db94011d3	518	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
sahilmgandhi	18:6a4db94011d3	519	STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	520
sahilmgandhi	18:6a4db94011d3	521	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
sahilmgandhi	18:6a4db94011d3	522	* @{
sahilmgandhi	18:6a4db94011d3	523	*/
sahilmgandhi	18:6a4db94011d3	524	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
sahilmgandhi	18:6a4db94011d3	525	defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	526	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	527	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000U)
sahilmgandhi	18:6a4db94011d3	528	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000U)
sahilmgandhi	18:6a4db94011d3	529	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000U)
sahilmgandhi	18:6a4db94011d3	530	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	531	/**
sahilmgandhi	18:6a4db94011d3	532	* @}
sahilmgandhi	18:6a4db94011d3	533	*/
sahilmgandhi	18:6a4db94011d3	534
sahilmgandhi	18:6a4db94011d3	535	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
sahilmgandhi	18:6a4db94011d3	536	* @{
sahilmgandhi	18:6a4db94011d3	537	*/
sahilmgandhi	18:6a4db94011d3	538	#if defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	539	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	540	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	541	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	542	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006U)
sahilmgandhi	18:6a4db94011d3	543	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	544	#endif /* STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	545	/**
sahilmgandhi	18:6a4db94011d3	546	* @}
sahilmgandhi	18:6a4db94011d3	547	*/
sahilmgandhi	18:6a4db94011d3	548
sahilmgandhi	18:6a4db94011d3	549	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
sahilmgandhi	18:6a4db94011d3	550	* @{
sahilmgandhi	18:6a4db94011d3	551	*/
sahilmgandhi	18:6a4db94011d3	552	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	553	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	554	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	555	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006U)
sahilmgandhi	18:6a4db94011d3	556	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	557	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	558	/**
sahilmgandhi	18:6a4db94011d3	559	* @}
sahilmgandhi	18:6a4db94011d3	560	*/
sahilmgandhi	18:6a4db94011d3	561
sahilmgandhi	18:6a4db94011d3	562	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	563	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
sahilmgandhi	18:6a4db94011d3	564	* @{
sahilmgandhi	18:6a4db94011d3	565	*/
sahilmgandhi	18:6a4db94011d3	566	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	567	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000U)
sahilmgandhi	18:6a4db94011d3	568	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000U)
sahilmgandhi	18:6a4db94011d3	569	/**
sahilmgandhi	18:6a4db94011d3	570	* @}
sahilmgandhi	18:6a4db94011d3	571	*/
sahilmgandhi	18:6a4db94011d3	572
sahilmgandhi	18:6a4db94011d3	573	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
sahilmgandhi	18:6a4db94011d3	574	* @{
sahilmgandhi	18:6a4db94011d3	575	*/
sahilmgandhi	18:6a4db94011d3	576	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	577	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000U)
sahilmgandhi	18:6a4db94011d3	578	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000U)
sahilmgandhi	18:6a4db94011d3	579	/**
sahilmgandhi	18:6a4db94011d3	580	* @}
sahilmgandhi	18:6a4db94011d3	581	*/
sahilmgandhi	18:6a4db94011d3	582	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	583
sahilmgandhi	18:6a4db94011d3	584	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	585	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
sahilmgandhi	18:6a4db94011d3	586	* @{
sahilmgandhi	18:6a4db94011d3	587	*/
sahilmgandhi	18:6a4db94011d3	588	#define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	589	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
sahilmgandhi	18:6a4db94011d3	590	/**
sahilmgandhi	18:6a4db94011d3	591	* @}
sahilmgandhi	18:6a4db94011d3	592	*/
sahilmgandhi	18:6a4db94011d3	593
sahilmgandhi	18:6a4db94011d3	594	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
sahilmgandhi	18:6a4db94011d3	595	* @{
sahilmgandhi	18:6a4db94011d3	596	*/
sahilmgandhi	18:6a4db94011d3	597	#define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	598	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
sahilmgandhi	18:6a4db94011d3	599	/**
sahilmgandhi	18:6a4db94011d3	600	* @}
sahilmgandhi	18:6a4db94011d3	601	*/
sahilmgandhi	18:6a4db94011d3	602
sahilmgandhi	18:6a4db94011d3	603	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
sahilmgandhi	18:6a4db94011d3	604	* @{
sahilmgandhi	18:6a4db94011d3	605	*/
sahilmgandhi	18:6a4db94011d3	606	#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	607	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
sahilmgandhi	18:6a4db94011d3	608	/**
sahilmgandhi	18:6a4db94011d3	609	* @}
sahilmgandhi	18:6a4db94011d3	610	*/
sahilmgandhi	18:6a4db94011d3	611	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	612
sahilmgandhi	18:6a4db94011d3	613	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	614	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
sahilmgandhi	18:6a4db94011d3	615	* @{
sahilmgandhi	18:6a4db94011d3	616	*/
sahilmgandhi	18:6a4db94011d3	617	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	618	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
sahilmgandhi	18:6a4db94011d3	619	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
sahilmgandhi	18:6a4db94011d3	620	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
sahilmgandhi	18:6a4db94011d3	621	/**
sahilmgandhi	18:6a4db94011d3	622	* @}
sahilmgandhi	18:6a4db94011d3	623	*/
sahilmgandhi	18:6a4db94011d3	624
sahilmgandhi	18:6a4db94011d3	625	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
sahilmgandhi	18:6a4db94011d3	626	* @{
sahilmgandhi	18:6a4db94011d3	627	*/
sahilmgandhi	18:6a4db94011d3	628	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	629	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
sahilmgandhi	18:6a4db94011d3	630	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
sahilmgandhi	18:6a4db94011d3	631	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
sahilmgandhi	18:6a4db94011d3	632	/**
sahilmgandhi	18:6a4db94011d3	633	* @}
sahilmgandhi	18:6a4db94011d3	634	*/
sahilmgandhi	18:6a4db94011d3	635
sahilmgandhi	18:6a4db94011d3	636	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
sahilmgandhi	18:6a4db94011d3	637	* @{
sahilmgandhi	18:6a4db94011d3	638	*/
sahilmgandhi	18:6a4db94011d3	639	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	640	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
sahilmgandhi	18:6a4db94011d3	641	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
sahilmgandhi	18:6a4db94011d3	642	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
sahilmgandhi	18:6a4db94011d3	643	/**
sahilmgandhi	18:6a4db94011d3	644	* @}
sahilmgandhi	18:6a4db94011d3	645	*/
sahilmgandhi	18:6a4db94011d3	646
sahilmgandhi	18:6a4db94011d3	647	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
sahilmgandhi	18:6a4db94011d3	648	* @{
sahilmgandhi	18:6a4db94011d3	649	*/
sahilmgandhi	18:6a4db94011d3	650	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	651	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
sahilmgandhi	18:6a4db94011d3	652	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
sahilmgandhi	18:6a4db94011d3	653	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
sahilmgandhi	18:6a4db94011d3	654	/**
sahilmgandhi	18:6a4db94011d3	655	* @}
sahilmgandhi	18:6a4db94011d3	656	*/
sahilmgandhi	18:6a4db94011d3	657
sahilmgandhi	18:6a4db94011d3	658	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
sahilmgandhi	18:6a4db94011d3	659	* @{
sahilmgandhi	18:6a4db94011d3	660	*/
sahilmgandhi	18:6a4db94011d3	661	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	662	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
sahilmgandhi	18:6a4db94011d3	663	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
sahilmgandhi	18:6a4db94011d3	664	/**
sahilmgandhi	18:6a4db94011d3	665	* @}
sahilmgandhi	18:6a4db94011d3	666	*/
sahilmgandhi	18:6a4db94011d3	667
sahilmgandhi	18:6a4db94011d3	668	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
sahilmgandhi	18:6a4db94011d3	669	* @{
sahilmgandhi	18:6a4db94011d3	670	*/
sahilmgandhi	18:6a4db94011d3	671	#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	672	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
sahilmgandhi	18:6a4db94011d3	673	/**
sahilmgandhi	18:6a4db94011d3	674	* @}
sahilmgandhi	18:6a4db94011d3	675	*/
sahilmgandhi	18:6a4db94011d3	676
sahilmgandhi	18:6a4db94011d3	677	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
sahilmgandhi	18:6a4db94011d3	678	* @{
sahilmgandhi	18:6a4db94011d3	679	*/
sahilmgandhi	18:6a4db94011d3	680	#define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	681	#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
sahilmgandhi	18:6a4db94011d3	682	/**
sahilmgandhi	18:6a4db94011d3	683	* @}
sahilmgandhi	18:6a4db94011d3	684	*/
sahilmgandhi	18:6a4db94011d3	685
sahilmgandhi	18:6a4db94011d3	686	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
sahilmgandhi	18:6a4db94011d3	687	* @{
sahilmgandhi	18:6a4db94011d3	688	*/
sahilmgandhi	18:6a4db94011d3	689	#define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	690	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
sahilmgandhi	18:6a4db94011d3	691	/**
sahilmgandhi	18:6a4db94011d3	692	* @}
sahilmgandhi	18:6a4db94011d3	693	*/
sahilmgandhi	18:6a4db94011d3	694
sahilmgandhi	18:6a4db94011d3	695	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
sahilmgandhi	18:6a4db94011d3	696	* @{
sahilmgandhi	18:6a4db94011d3	697	*/
sahilmgandhi	18:6a4db94011d3	698	#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	699	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
sahilmgandhi	18:6a4db94011d3	700	/**
sahilmgandhi	18:6a4db94011d3	701	* @}
sahilmgandhi	18:6a4db94011d3	702	*/
sahilmgandhi	18:6a4db94011d3	703	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	704
sahilmgandhi	18:6a4db94011d3	705	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	706	/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
sahilmgandhi	18:6a4db94011d3	707	* @{
sahilmgandhi	18:6a4db94011d3	708	*/
sahilmgandhi	18:6a4db94011d3	709	#define RCC_PLLI2SCLKSOURCE_PLLSRC ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	710	#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
sahilmgandhi	18:6a4db94011d3	711	/**
sahilmgandhi	18:6a4db94011d3	712	* @}
sahilmgandhi	18:6a4db94011d3	713	*/
sahilmgandhi	18:6a4db94011d3	714
sahilmgandhi	18:6a4db94011d3	715	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source
sahilmgandhi	18:6a4db94011d3	716	* @{
sahilmgandhi	18:6a4db94011d3	717	*/
sahilmgandhi	18:6a4db94011d3	718	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	719	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
sahilmgandhi	18:6a4db94011d3	720	/**
sahilmgandhi	18:6a4db94011d3	721	* @}
sahilmgandhi	18:6a4db94011d3	722	*/
sahilmgandhi	18:6a4db94011d3	723
sahilmgandhi	18:6a4db94011d3	724	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source
sahilmgandhi	18:6a4db94011d3	725	* @{
sahilmgandhi	18:6a4db94011d3	726	*/
sahilmgandhi	18:6a4db94011d3	727	#define RCC_DFSDM1CLKSOURCE_APB2 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	728	#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
sahilmgandhi	18:6a4db94011d3	729	/**
sahilmgandhi	18:6a4db94011d3	730	* @}
sahilmgandhi	18:6a4db94011d3	731	*/
sahilmgandhi	18:6a4db94011d3	732
sahilmgandhi	18:6a4db94011d3	733	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
sahilmgandhi	18:6a4db94011d3	734	* @{
sahilmgandhi	18:6a4db94011d3	735	*/
sahilmgandhi	18:6a4db94011d3	736	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	737	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
sahilmgandhi	18:6a4db94011d3	738	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
sahilmgandhi	18:6a4db94011d3	739	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
sahilmgandhi	18:6a4db94011d3	740	/**
sahilmgandhi	18:6a4db94011d3	741	* @}
sahilmgandhi	18:6a4db94011d3	742	*/
sahilmgandhi	18:6a4db94011d3	743
sahilmgandhi	18:6a4db94011d3	744	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
sahilmgandhi	18:6a4db94011d3	745	* @{
sahilmgandhi	18:6a4db94011d3	746	*/
sahilmgandhi	18:6a4db94011d3	747	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	748	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
sahilmgandhi	18:6a4db94011d3	749	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
sahilmgandhi	18:6a4db94011d3	750	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
sahilmgandhi	18:6a4db94011d3	751	/**
sahilmgandhi	18:6a4db94011d3	752	* @}
sahilmgandhi	18:6a4db94011d3	753	*/
sahilmgandhi	18:6a4db94011d3	754
sahilmgandhi	18:6a4db94011d3	755	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
sahilmgandhi	18:6a4db94011d3	756	* @{
sahilmgandhi	18:6a4db94011d3	757	*/
sahilmgandhi	18:6a4db94011d3	758	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	759	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
sahilmgandhi	18:6a4db94011d3	760	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
sahilmgandhi	18:6a4db94011d3	761	/**
sahilmgandhi	18:6a4db94011d3	762	* @}
sahilmgandhi	18:6a4db94011d3	763	*/
sahilmgandhi	18:6a4db94011d3	764
sahilmgandhi	18:6a4db94011d3	765	/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source
sahilmgandhi	18:6a4db94011d3	766	* @{
sahilmgandhi	18:6a4db94011d3	767	*/
sahilmgandhi	18:6a4db94011d3	768	#define RCC_CLK48CLKSOURCE_PLLQ ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	769	#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
sahilmgandhi	18:6a4db94011d3	770	/**
sahilmgandhi	18:6a4db94011d3	771	* @}
sahilmgandhi	18:6a4db94011d3	772	*/
sahilmgandhi	18:6a4db94011d3	773
sahilmgandhi	18:6a4db94011d3	774	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
sahilmgandhi	18:6a4db94011d3	775	* @{
sahilmgandhi	18:6a4db94011d3	776	*/
sahilmgandhi	18:6a4db94011d3	777	#define RCC_SDIOCLKSOURCE_CLK48 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	778	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
sahilmgandhi	18:6a4db94011d3	779	/**
sahilmgandhi	18:6a4db94011d3	780	* @}
sahilmgandhi	18:6a4db94011d3	781	*/
sahilmgandhi	18:6a4db94011d3	782	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	783
sahilmgandhi	18:6a4db94011d3	784	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	785	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
sahilmgandhi	18:6a4db94011d3	786	* @{
sahilmgandhi	18:6a4db94011d3	787	*/
sahilmgandhi	18:6a4db94011d3	788	#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	789	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
sahilmgandhi	18:6a4db94011d3	790	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
sahilmgandhi	18:6a4db94011d3	791	/**
sahilmgandhi	18:6a4db94011d3	792	* @}
sahilmgandhi	18:6a4db94011d3	793	*/
sahilmgandhi	18:6a4db94011d3	794
sahilmgandhi	18:6a4db94011d3	795	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
sahilmgandhi	18:6a4db94011d3	796	* @{
sahilmgandhi	18:6a4db94011d3	797	*/
sahilmgandhi	18:6a4db94011d3	798	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	799	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
sahilmgandhi	18:6a4db94011d3	800	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
sahilmgandhi	18:6a4db94011d3	801	/**
sahilmgandhi	18:6a4db94011d3	802	* @}
sahilmgandhi	18:6a4db94011d3	803	*/
sahilmgandhi	18:6a4db94011d3	804
sahilmgandhi	18:6a4db94011d3	805	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
sahilmgandhi	18:6a4db94011d3	806	* @{
sahilmgandhi	18:6a4db94011d3	807	*/
sahilmgandhi	18:6a4db94011d3	808	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	809	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
sahilmgandhi	18:6a4db94011d3	810	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
sahilmgandhi	18:6a4db94011d3	811	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
sahilmgandhi	18:6a4db94011d3	812	/**
sahilmgandhi	18:6a4db94011d3	813	* @}
sahilmgandhi	18:6a4db94011d3	814	*/
sahilmgandhi	18:6a4db94011d3	815	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	816
sahilmgandhi	18:6a4db94011d3	817	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
sahilmgandhi	18:6a4db94011d3	818	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
sahilmgandhi	18:6a4db94011d3	819	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
sahilmgandhi	18:6a4db94011d3	820	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
sahilmgandhi	18:6a4db94011d3	821	defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	822	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
sahilmgandhi	18:6a4db94011d3	823	* @{
sahilmgandhi	18:6a4db94011d3	824	*/
sahilmgandhi	18:6a4db94011d3	825	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00U)
sahilmgandhi	18:6a4db94011d3	826	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01U)
sahilmgandhi	18:6a4db94011d3	827	/**
sahilmgandhi	18:6a4db94011d3	828	* @}
sahilmgandhi	18:6a4db94011d3	829	*/
sahilmgandhi	18:6a4db94011d3	830	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
sahilmgandhi	18:6a4db94011d3	831	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
sahilmgandhi	18:6a4db94011d3	832	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	833
sahilmgandhi	18:6a4db94011d3	834	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
sahilmgandhi	18:6a4db94011d3	835	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
sahilmgandhi	18:6a4db94011d3	836	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	837	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
sahilmgandhi	18:6a4db94011d3	838	* @{
sahilmgandhi	18:6a4db94011d3	839	*/
sahilmgandhi	18:6a4db94011d3	840	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00U)
sahilmgandhi	18:6a4db94011d3	841	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01U)
sahilmgandhi	18:6a4db94011d3	842	/**
sahilmgandhi	18:6a4db94011d3	843	* @}
sahilmgandhi	18:6a4db94011d3	844	*/
sahilmgandhi	18:6a4db94011d3	845	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|\
sahilmgandhi	18:6a4db94011d3	846	STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	847
sahilmgandhi	18:6a4db94011d3	848	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
sahilmgandhi	18:6a4db94011d3	849	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
sahilmgandhi	18:6a4db94011d3	850	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
sahilmgandhi	18:6a4db94011d3	851	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	852	defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	853	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
sahilmgandhi	18:6a4db94011d3	854	* @{
sahilmgandhi	18:6a4db94011d3	855	*/
sahilmgandhi	18:6a4db94011d3	856	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	857	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
sahilmgandhi	18:6a4db94011d3	858	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
sahilmgandhi	18:6a4db94011d3	859	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
sahilmgandhi	18:6a4db94011d3	860	/**
sahilmgandhi	18:6a4db94011d3	861	* @}
sahilmgandhi	18:6a4db94011d3	862	*/
sahilmgandhi	18:6a4db94011d3	863	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
sahilmgandhi	18:6a4db94011d3	864	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
sahilmgandhi	18:6a4db94011d3	865	STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	866
sahilmgandhi	18:6a4db94011d3	867	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	868	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
sahilmgandhi	18:6a4db94011d3	869	* @{
sahilmgandhi	18:6a4db94011d3	870	*/
sahilmgandhi	18:6a4db94011d3	871	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	872	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
sahilmgandhi	18:6a4db94011d3	873	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
sahilmgandhi	18:6a4db94011d3	874	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
sahilmgandhi	18:6a4db94011d3	875	/**
sahilmgandhi	18:6a4db94011d3	876	* @}
sahilmgandhi	18:6a4db94011d3	877	*/
sahilmgandhi	18:6a4db94011d3	878	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	879
sahilmgandhi	18:6a4db94011d3	880	/**
sahilmgandhi	18:6a4db94011d3	881	* @}
sahilmgandhi	18:6a4db94011d3	882	*/
sahilmgandhi	18:6a4db94011d3	883
sahilmgandhi	18:6a4db94011d3	884	/* Exported macro ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	885	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
sahilmgandhi	18:6a4db94011d3	886	* @{
sahilmgandhi	18:6a4db94011d3	887	*/
sahilmgandhi	18:6a4db94011d3	888	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
sahilmgandhi	18:6a4db94011d3	889	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	890	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	891	* @brief Enables or disables the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	892	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	893	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	894	* using it.
sahilmgandhi	18:6a4db94011d3	895	* @{
sahilmgandhi	18:6a4db94011d3	896	*/
sahilmgandhi	18:6a4db94011d3	897	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	898	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	899	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	900	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	901	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	902	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	903	} while(0)
sahilmgandhi	18:6a4db94011d3	904	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	905	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	906	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	907	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	908	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	909	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	910	} while(0)
sahilmgandhi	18:6a4db94011d3	911	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	912	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	913	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	914	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	915	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	916	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	917	} while(0)
sahilmgandhi	18:6a4db94011d3	918	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	919	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	920	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	921	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	922	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	923	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	924	} while(0)
sahilmgandhi	18:6a4db94011d3	925	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	926	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	927	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	928	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	929	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	930	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	931	} while(0)
sahilmgandhi	18:6a4db94011d3	932	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	933	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	934	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
sahilmgandhi	18:6a4db94011d3	935	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	936	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
sahilmgandhi	18:6a4db94011d3	937	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	938	} while(0)
sahilmgandhi	18:6a4db94011d3	939	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	940	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	941	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
sahilmgandhi	18:6a4db94011d3	942	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	943	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
sahilmgandhi	18:6a4db94011d3	944	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	945	} while(0)
sahilmgandhi	18:6a4db94011d3	946	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	947	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	948	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
sahilmgandhi	18:6a4db94011d3	949	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	950	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
sahilmgandhi	18:6a4db94011d3	951	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	952	} while(0)
sahilmgandhi	18:6a4db94011d3	953	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	954	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	955	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
sahilmgandhi	18:6a4db94011d3	956	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	957	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
sahilmgandhi	18:6a4db94011d3	958	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	959	} while(0)
sahilmgandhi	18:6a4db94011d3	960	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	961	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	962	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
sahilmgandhi	18:6a4db94011d3	963	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	964	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
sahilmgandhi	18:6a4db94011d3	965	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	966	} while(0)
sahilmgandhi	18:6a4db94011d3	967	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	968	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	969	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
sahilmgandhi	18:6a4db94011d3	970	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	971	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
sahilmgandhi	18:6a4db94011d3	972	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	973	} while(0)
sahilmgandhi	18:6a4db94011d3	974	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	975	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	976	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
sahilmgandhi	18:6a4db94011d3	977	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	978	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
sahilmgandhi	18:6a4db94011d3	979	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	980	} while(0)
sahilmgandhi	18:6a4db94011d3	981	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	982	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	983	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
sahilmgandhi	18:6a4db94011d3	984	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	985	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
sahilmgandhi	18:6a4db94011d3	986	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	987	} while(0)
sahilmgandhi	18:6a4db94011d3	988	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	989	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	990	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
sahilmgandhi	18:6a4db94011d3	991	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	992	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
sahilmgandhi	18:6a4db94011d3	993	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	994	} while(0)
sahilmgandhi	18:6a4db94011d3	995	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	996	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	997	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
sahilmgandhi	18:6a4db94011d3	998	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	999	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
sahilmgandhi	18:6a4db94011d3	1000	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1001	} while(0)
sahilmgandhi	18:6a4db94011d3	1002	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1003	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1004	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
sahilmgandhi	18:6a4db94011d3	1005	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1006	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
sahilmgandhi	18:6a4db94011d3	1007	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1008	} while(0)
sahilmgandhi	18:6a4db94011d3	1009	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1010	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1011	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
sahilmgandhi	18:6a4db94011d3	1012	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1013	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
sahilmgandhi	18:6a4db94011d3	1014	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1015	} while(0)
sahilmgandhi	18:6a4db94011d3	1016	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
sahilmgandhi	18:6a4db94011d3	1017	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
sahilmgandhi	18:6a4db94011d3	1018	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
sahilmgandhi	18:6a4db94011d3	1019	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
sahilmgandhi	18:6a4db94011d3	1020	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
sahilmgandhi	18:6a4db94011d3	1021	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
sahilmgandhi	18:6a4db94011d3	1022	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
sahilmgandhi	18:6a4db94011d3	1023	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
sahilmgandhi	18:6a4db94011d3	1024	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
sahilmgandhi	18:6a4db94011d3	1025	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
sahilmgandhi	18:6a4db94011d3	1026	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
sahilmgandhi	18:6a4db94011d3	1027	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
sahilmgandhi	18:6a4db94011d3	1028	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
sahilmgandhi	18:6a4db94011d3	1029	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
sahilmgandhi	18:6a4db94011d3	1030	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
sahilmgandhi	18:6a4db94011d3	1031	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
sahilmgandhi	18:6a4db94011d3	1032	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
sahilmgandhi	18:6a4db94011d3	1033
sahilmgandhi	18:6a4db94011d3	1034	/**
sahilmgandhi	18:6a4db94011d3	1035	* @brief Enable ETHERNET clock.
sahilmgandhi	18:6a4db94011d3	1036	*/
sahilmgandhi	18:6a4db94011d3	1037	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1038	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
sahilmgandhi	18:6a4db94011d3	1039	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
sahilmgandhi	18:6a4db94011d3	1040	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
sahilmgandhi	18:6a4db94011d3	1041	} while(0)
sahilmgandhi	18:6a4db94011d3	1042	/**
sahilmgandhi	18:6a4db94011d3	1043	* @brief Disable ETHERNET clock.
sahilmgandhi	18:6a4db94011d3	1044	*/
sahilmgandhi	18:6a4db94011d3	1045	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
sahilmgandhi	18:6a4db94011d3	1046	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
sahilmgandhi	18:6a4db94011d3	1047	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
sahilmgandhi	18:6a4db94011d3	1048	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
sahilmgandhi	18:6a4db94011d3	1049	} while(0)
sahilmgandhi	18:6a4db94011d3	1050	/**
sahilmgandhi	18:6a4db94011d3	1051	* @}
sahilmgandhi	18:6a4db94011d3	1052	*/
sahilmgandhi	18:6a4db94011d3	1053
sahilmgandhi	18:6a4db94011d3	1054	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	1055	* @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	1056	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1057	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1058	* using it.
sahilmgandhi	18:6a4db94011d3	1059	* @{
sahilmgandhi	18:6a4db94011d3	1060	*/
sahilmgandhi	18:6a4db94011d3	1061	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1062	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1063	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1064	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1065	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1066	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1067	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1068	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1069	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1070	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1071	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1072	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1073	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1074	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1075	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1076	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1077	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1078	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
sahilmgandhi	18:6a4db94011d3	1079	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
sahilmgandhi	18:6a4db94011d3	1080	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
sahilmgandhi	18:6a4db94011d3	1081
sahilmgandhi	18:6a4db94011d3	1082	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1083	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1084	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1085	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1086	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1087	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1088	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1089	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1090	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1091	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1092	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1093	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1094	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1095	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1096	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1097	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1098	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1099	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
sahilmgandhi	18:6a4db94011d3	1100	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
sahilmgandhi	18:6a4db94011d3	1101	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
sahilmgandhi	18:6a4db94011d3	1102	/**
sahilmgandhi	18:6a4db94011d3	1103	* @}
sahilmgandhi	18:6a4db94011d3	1104	*/
sahilmgandhi	18:6a4db94011d3	1105
sahilmgandhi	18:6a4db94011d3	1106	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	1107	* @brief Enable or disable the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	1108	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1109	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1110	* using it.
sahilmgandhi	18:6a4db94011d3	1111	* @{
sahilmgandhi	18:6a4db94011d3	1112	*/
sahilmgandhi	18:6a4db94011d3	1113	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1114	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1115	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
sahilmgandhi	18:6a4db94011d3	1116	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1117	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
sahilmgandhi	18:6a4db94011d3	1118	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1119	} while(0)
sahilmgandhi	18:6a4db94011d3	1120	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
sahilmgandhi	18:6a4db94011d3	1121
sahilmgandhi	18:6a4db94011d3	1122	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1123	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1124	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1125	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
sahilmgandhi	18:6a4db94011d3	1126	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1127	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
sahilmgandhi	18:6a4db94011d3	1128	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1129	} while(0)
sahilmgandhi	18:6a4db94011d3	1130	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1131	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1132	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
sahilmgandhi	18:6a4db94011d3	1133	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1134	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
sahilmgandhi	18:6a4db94011d3	1135	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1136	} while(0)
sahilmgandhi	18:6a4db94011d3	1137
sahilmgandhi	18:6a4db94011d3	1138	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
sahilmgandhi	18:6a4db94011d3	1139	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
sahilmgandhi	18:6a4db94011d3	1140	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1141
sahilmgandhi	18:6a4db94011d3	1142	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
sahilmgandhi	18:6a4db94011d3	1143	__HAL_RCC_SYSCFG_CLK_ENABLE();\
sahilmgandhi	18:6a4db94011d3	1144	}while(0)
sahilmgandhi	18:6a4db94011d3	1145
sahilmgandhi	18:6a4db94011d3	1146	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
sahilmgandhi	18:6a4db94011d3	1147
sahilmgandhi	18:6a4db94011d3	1148	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1149	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1150	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	1151	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1152	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	1153	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1154	} while(0)
sahilmgandhi	18:6a4db94011d3	1155	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
sahilmgandhi	18:6a4db94011d3	1156	/**
sahilmgandhi	18:6a4db94011d3	1157	* @}
sahilmgandhi	18:6a4db94011d3	1158	*/
sahilmgandhi	18:6a4db94011d3	1159
sahilmgandhi	18:6a4db94011d3	1160	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	1161	* @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	1162	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1163	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1164	* using it.
sahilmgandhi	18:6a4db94011d3	1165	* @{
sahilmgandhi	18:6a4db94011d3	1166	*/
sahilmgandhi	18:6a4db94011d3	1167	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1168	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1169
sahilmgandhi	18:6a4db94011d3	1170	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1171	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1172	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1173
sahilmgandhi	18:6a4db94011d3	1174	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1175	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1176	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1177
sahilmgandhi	18:6a4db94011d3	1178	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1179	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1180
sahilmgandhi	18:6a4db94011d3	1181	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1182	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1183	/**
sahilmgandhi	18:6a4db94011d3	1184	* @}
sahilmgandhi	18:6a4db94011d3	1185	*/
sahilmgandhi	18:6a4db94011d3	1186
sahilmgandhi	18:6a4db94011d3	1187	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	1188	* @brief Enables or disables the AHB3 peripheral clock.
sahilmgandhi	18:6a4db94011d3	1189	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1190	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1191	* using it.
sahilmgandhi	18:6a4db94011d3	1192	* @{
sahilmgandhi	18:6a4db94011d3	1193	*/
sahilmgandhi	18:6a4db94011d3	1194	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1195	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1196	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
sahilmgandhi	18:6a4db94011d3	1197	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1198	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
sahilmgandhi	18:6a4db94011d3	1199	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1200	} while(0)
sahilmgandhi	18:6a4db94011d3	1201	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
sahilmgandhi	18:6a4db94011d3	1202	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1203	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1204	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1205	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
sahilmgandhi	18:6a4db94011d3	1206	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1207	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
sahilmgandhi	18:6a4db94011d3	1208	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1209	} while(0)
sahilmgandhi	18:6a4db94011d3	1210	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
sahilmgandhi	18:6a4db94011d3	1211	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1212	/**
sahilmgandhi	18:6a4db94011d3	1213	* @}
sahilmgandhi	18:6a4db94011d3	1214	*/
sahilmgandhi	18:6a4db94011d3	1215
sahilmgandhi	18:6a4db94011d3	1216
sahilmgandhi	18:6a4db94011d3	1217	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	1218	* @brief Get the enable or disable status of the AHB3 peripheral clock.
sahilmgandhi	18:6a4db94011d3	1219	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1220	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1221	* using it.
sahilmgandhi	18:6a4db94011d3	1222	* @{
sahilmgandhi	18:6a4db94011d3	1223	*/
sahilmgandhi	18:6a4db94011d3	1224	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1225	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1226	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1227	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1228	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1229	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1230	/**
sahilmgandhi	18:6a4db94011d3	1231	* @}
sahilmgandhi	18:6a4db94011d3	1232	*/
sahilmgandhi	18:6a4db94011d3	1233
sahilmgandhi	18:6a4db94011d3	1234	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	1235	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
sahilmgandhi	18:6a4db94011d3	1236	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1237	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1238	* using it.
sahilmgandhi	18:6a4db94011d3	1239	* @{
sahilmgandhi	18:6a4db94011d3	1240	*/
sahilmgandhi	18:6a4db94011d3	1241	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1242	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1243	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	1244	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1245	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	1246	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1247	} while(0)
sahilmgandhi	18:6a4db94011d3	1248	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1249	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1250	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
sahilmgandhi	18:6a4db94011d3	1251	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1252	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
sahilmgandhi	18:6a4db94011d3	1253	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1254	} while(0)
sahilmgandhi	18:6a4db94011d3	1255	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1256	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1257	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
sahilmgandhi	18:6a4db94011d3	1258	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1259	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
sahilmgandhi	18:6a4db94011d3	1260	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1261	} while(0)
sahilmgandhi	18:6a4db94011d3	1262	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1263	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1264	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
sahilmgandhi	18:6a4db94011d3	1265	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1266	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
sahilmgandhi	18:6a4db94011d3	1267	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1268	} while(0)
sahilmgandhi	18:6a4db94011d3	1269	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1270	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1271	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	1272	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1273	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	1274	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1275	} while(0)
sahilmgandhi	18:6a4db94011d3	1276	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1277	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1278	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	1279	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1280	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	1281	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1282	} while(0)
sahilmgandhi	18:6a4db94011d3	1283	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1284	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1285	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
sahilmgandhi	18:6a4db94011d3	1286	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1287	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
sahilmgandhi	18:6a4db94011d3	1288	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1289	} while(0)
sahilmgandhi	18:6a4db94011d3	1290	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1291	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1292	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
sahilmgandhi	18:6a4db94011d3	1293	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1294	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
sahilmgandhi	18:6a4db94011d3	1295	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1296	} while(0)
sahilmgandhi	18:6a4db94011d3	1297	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1298	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1299	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
sahilmgandhi	18:6a4db94011d3	1300	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1301	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
sahilmgandhi	18:6a4db94011d3	1302	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1303	} while(0)
sahilmgandhi	18:6a4db94011d3	1304	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1305	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1306	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
sahilmgandhi	18:6a4db94011d3	1307	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1308	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
sahilmgandhi	18:6a4db94011d3	1309	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1310	} while(0)
sahilmgandhi	18:6a4db94011d3	1311	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1312	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1313	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
sahilmgandhi	18:6a4db94011d3	1314	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1315	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
sahilmgandhi	18:6a4db94011d3	1316	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1317	} while(0)
sahilmgandhi	18:6a4db94011d3	1318	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1319	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1320	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
sahilmgandhi	18:6a4db94011d3	1321	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1322	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
sahilmgandhi	18:6a4db94011d3	1323	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1324	} while(0)
sahilmgandhi	18:6a4db94011d3	1325	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1326	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1327	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
sahilmgandhi	18:6a4db94011d3	1328	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1329	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
sahilmgandhi	18:6a4db94011d3	1330	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1331	} while(0)
sahilmgandhi	18:6a4db94011d3	1332	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1333	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1334	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
sahilmgandhi	18:6a4db94011d3	1335	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1336	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
sahilmgandhi	18:6a4db94011d3	1337	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1338	} while(0)
sahilmgandhi	18:6a4db94011d3	1339	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1340	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1341	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	1342	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1343	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	1344	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1345	} while(0)
sahilmgandhi	18:6a4db94011d3	1346	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1347	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	1349	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	1351	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1352	} while(0)
sahilmgandhi	18:6a4db94011d3	1353	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1354	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	1356	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	1358	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1359	} while(0)
sahilmgandhi	18:6a4db94011d3	1360	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1361	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	1363	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	1365	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1366	} while(0)
sahilmgandhi	18:6a4db94011d3	1367	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1368	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	1370	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	1372	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1373	} while(0)
sahilmgandhi	18:6a4db94011d3	1374	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
sahilmgandhi	18:6a4db94011d3	1375	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
sahilmgandhi	18:6a4db94011d3	1376	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
sahilmgandhi	18:6a4db94011d3	1377	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
sahilmgandhi	18:6a4db94011d3	1378	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
sahilmgandhi	18:6a4db94011d3	1379	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
sahilmgandhi	18:6a4db94011d3	1380	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
sahilmgandhi	18:6a4db94011d3	1381	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
sahilmgandhi	18:6a4db94011d3	1382	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
sahilmgandhi	18:6a4db94011d3	1383	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
sahilmgandhi	18:6a4db94011d3	1384	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
sahilmgandhi	18:6a4db94011d3	1385	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
sahilmgandhi	18:6a4db94011d3	1386	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
sahilmgandhi	18:6a4db94011d3	1387	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
sahilmgandhi	18:6a4db94011d3	1388	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
sahilmgandhi	18:6a4db94011d3	1389	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
sahilmgandhi	18:6a4db94011d3	1390	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
sahilmgandhi	18:6a4db94011d3	1391	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
sahilmgandhi	18:6a4db94011d3	1392	/**
sahilmgandhi	18:6a4db94011d3	1393	* @}
sahilmgandhi	18:6a4db94011d3	1394	*/
sahilmgandhi	18:6a4db94011d3	1395
sahilmgandhi	18:6a4db94011d3	1396	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	1397	* @brief Get the enable or disable status of the APB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	1398	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1399	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1400	* using it.
sahilmgandhi	18:6a4db94011d3	1401	* @{
sahilmgandhi	18:6a4db94011d3	1402	*/
sahilmgandhi	18:6a4db94011d3	1403	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1404	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1405	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1406	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1407	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1408	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1409	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1410	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1411	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1412	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1413	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1414	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1415	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1416	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1417	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1418	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1419	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1420	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1421
sahilmgandhi	18:6a4db94011d3	1422	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1423	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1424	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1425	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1426	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1427	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1428	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1429	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1430	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1431	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1432	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1433	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1434	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1435	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1436	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1437	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1438	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1439	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1440	/**
sahilmgandhi	18:6a4db94011d3	1441	* @}
sahilmgandhi	18:6a4db94011d3	1442	*/
sahilmgandhi	18:6a4db94011d3	1443
sahilmgandhi	18:6a4db94011d3	1444	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	1445	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
sahilmgandhi	18:6a4db94011d3	1446	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1447	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1448	* using it.
sahilmgandhi	18:6a4db94011d3	1449	* @{
sahilmgandhi	18:6a4db94011d3	1450	*/
sahilmgandhi	18:6a4db94011d3	1451	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1452	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1453	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
sahilmgandhi	18:6a4db94011d3	1454	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1455	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
sahilmgandhi	18:6a4db94011d3	1456	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1457	} while(0)
sahilmgandhi	18:6a4db94011d3	1458	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1459	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1460	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
sahilmgandhi	18:6a4db94011d3	1461	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1462	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
sahilmgandhi	18:6a4db94011d3	1463	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1464	} while(0)
sahilmgandhi	18:6a4db94011d3	1465	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1466	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1467	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
sahilmgandhi	18:6a4db94011d3	1468	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1469	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
sahilmgandhi	18:6a4db94011d3	1470	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1471	} while(0)
sahilmgandhi	18:6a4db94011d3	1472	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1473	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1474	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
sahilmgandhi	18:6a4db94011d3	1475	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1476	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
sahilmgandhi	18:6a4db94011d3	1477	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1478	} while(0)
sahilmgandhi	18:6a4db94011d3	1479	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1480	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1481	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
sahilmgandhi	18:6a4db94011d3	1482	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1483	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
sahilmgandhi	18:6a4db94011d3	1484	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1485	} while(0)
sahilmgandhi	18:6a4db94011d3	1486	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1487	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1488	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
sahilmgandhi	18:6a4db94011d3	1489	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1490	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
sahilmgandhi	18:6a4db94011d3	1491	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1492	} while(0)
sahilmgandhi	18:6a4db94011d3	1493	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1494	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1495	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	1496	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1497	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	1498	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1499	} while(0)
sahilmgandhi	18:6a4db94011d3	1500	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1501	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1502	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	1503	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1504	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	1505	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1506	} while(0)
sahilmgandhi	18:6a4db94011d3	1507	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1508	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1509	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	1510	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1511	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	1512	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1513	} while(0)
sahilmgandhi	18:6a4db94011d3	1514	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
sahilmgandhi	18:6a4db94011d3	1515	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
sahilmgandhi	18:6a4db94011d3	1516	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
sahilmgandhi	18:6a4db94011d3	1517	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
sahilmgandhi	18:6a4db94011d3	1518	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
sahilmgandhi	18:6a4db94011d3	1519	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
sahilmgandhi	18:6a4db94011d3	1520	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
sahilmgandhi	18:6a4db94011d3	1521	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
sahilmgandhi	18:6a4db94011d3	1522	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
sahilmgandhi	18:6a4db94011d3	1523
sahilmgandhi	18:6a4db94011d3	1524	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1525	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1526	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1527	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
sahilmgandhi	18:6a4db94011d3	1528	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1529	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
sahilmgandhi	18:6a4db94011d3	1530	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1531	} while(0)
sahilmgandhi	18:6a4db94011d3	1532
sahilmgandhi	18:6a4db94011d3	1533	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
sahilmgandhi	18:6a4db94011d3	1534	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1535
sahilmgandhi	18:6a4db94011d3	1536	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1537	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1538	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1539	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
sahilmgandhi	18:6a4db94011d3	1540	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1541	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
sahilmgandhi	18:6a4db94011d3	1542	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1543	} while(0)
sahilmgandhi	18:6a4db94011d3	1544
sahilmgandhi	18:6a4db94011d3	1545	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
sahilmgandhi	18:6a4db94011d3	1546	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1547	/**
sahilmgandhi	18:6a4db94011d3	1548	* @}
sahilmgandhi	18:6a4db94011d3	1549	*/
sahilmgandhi	18:6a4db94011d3	1550
sahilmgandhi	18:6a4db94011d3	1551	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	1552	* @brief Get the enable or disable status of the APB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	1553	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1554	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1555	* using it.
sahilmgandhi	18:6a4db94011d3	1556	* @{
sahilmgandhi	18:6a4db94011d3	1557	*/
sahilmgandhi	18:6a4db94011d3	1558	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1559	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1560	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1561	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1562	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1563	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1564	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1565	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1566	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)
sahilmgandhi	18:6a4db94011d3	1567
sahilmgandhi	18:6a4db94011d3	1568	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1569	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1570	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
sahilmgandhi	18:6a4db94011d3	1571	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1572	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1573	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1574	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1575	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1576	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1577
sahilmgandhi	18:6a4db94011d3	1578	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1579	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1580	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1581	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1582
sahilmgandhi	18:6a4db94011d3	1583	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1584	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	1585	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	1586	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1587	/**
sahilmgandhi	18:6a4db94011d3	1588	* @}
sahilmgandhi	18:6a4db94011d3	1589	*/
sahilmgandhi	18:6a4db94011d3	1590
sahilmgandhi	18:6a4db94011d3	1591	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	1592	* @brief Force or release AHB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	1593	* @{
sahilmgandhi	18:6a4db94011d3	1594	*/
sahilmgandhi	18:6a4db94011d3	1595	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	1596	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	1597	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
sahilmgandhi	18:6a4db94011d3	1598	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
sahilmgandhi	18:6a4db94011d3	1599	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
sahilmgandhi	18:6a4db94011d3	1600	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
sahilmgandhi	18:6a4db94011d3	1601	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
sahilmgandhi	18:6a4db94011d3	1602	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
sahilmgandhi	18:6a4db94011d3	1603	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
sahilmgandhi	18:6a4db94011d3	1604	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
sahilmgandhi	18:6a4db94011d3	1605	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	1606
sahilmgandhi	18:6a4db94011d3	1607	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	1608	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	1609	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
sahilmgandhi	18:6a4db94011d3	1610	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
sahilmgandhi	18:6a4db94011d3	1611	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
sahilmgandhi	18:6a4db94011d3	1612	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
sahilmgandhi	18:6a4db94011d3	1613	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
sahilmgandhi	18:6a4db94011d3	1614	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
sahilmgandhi	18:6a4db94011d3	1615	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
sahilmgandhi	18:6a4db94011d3	1616	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
sahilmgandhi	18:6a4db94011d3	1617	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	1618	/**
sahilmgandhi	18:6a4db94011d3	1619	* @}
sahilmgandhi	18:6a4db94011d3	1620	*/
sahilmgandhi	18:6a4db94011d3	1621
sahilmgandhi	18:6a4db94011d3	1622	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	1623	* @brief Force or release AHB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	1624	* @{
sahilmgandhi	18:6a4db94011d3	1625	*/
sahilmgandhi	18:6a4db94011d3	1626	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	1627	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	1628	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	1629	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
sahilmgandhi	18:6a4db94011d3	1630
sahilmgandhi	18:6a4db94011d3	1631	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	1632	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	1633	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	1634	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
sahilmgandhi	18:6a4db94011d3	1635
sahilmgandhi	18:6a4db94011d3	1636	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1637	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
sahilmgandhi	18:6a4db94011d3	1638	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
sahilmgandhi	18:6a4db94011d3	1639
sahilmgandhi	18:6a4db94011d3	1640	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
sahilmgandhi	18:6a4db94011d3	1641	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
sahilmgandhi	18:6a4db94011d3	1642	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1643	/**
sahilmgandhi	18:6a4db94011d3	1644	* @}
sahilmgandhi	18:6a4db94011d3	1645	*/
sahilmgandhi	18:6a4db94011d3	1646
sahilmgandhi	18:6a4db94011d3	1647	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
sahilmgandhi	18:6a4db94011d3	1648	* @brief Force or release AHB3 peripheral reset.
sahilmgandhi	18:6a4db94011d3	1649	* @{
sahilmgandhi	18:6a4db94011d3	1650	*/
sahilmgandhi	18:6a4db94011d3	1651	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	1652	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	1653	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
sahilmgandhi	18:6a4db94011d3	1654	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
sahilmgandhi	18:6a4db94011d3	1655
sahilmgandhi	18:6a4db94011d3	1656	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1657	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
sahilmgandhi	18:6a4db94011d3	1658	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
sahilmgandhi	18:6a4db94011d3	1659	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1660	/**
sahilmgandhi	18:6a4db94011d3	1661	* @}
sahilmgandhi	18:6a4db94011d3	1662	*/
sahilmgandhi	18:6a4db94011d3	1663
sahilmgandhi	18:6a4db94011d3	1664	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	1665	* @brief Force or release APB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	1666	* @{
sahilmgandhi	18:6a4db94011d3	1667	*/
sahilmgandhi	18:6a4db94011d3	1668	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	1669	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
sahilmgandhi	18:6a4db94011d3	1670	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
sahilmgandhi	18:6a4db94011d3	1671	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
sahilmgandhi	18:6a4db94011d3	1672	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
sahilmgandhi	18:6a4db94011d3	1673	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
sahilmgandhi	18:6a4db94011d3	1674	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
sahilmgandhi	18:6a4db94011d3	1675	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
sahilmgandhi	18:6a4db94011d3	1676	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
sahilmgandhi	18:6a4db94011d3	1677	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
sahilmgandhi	18:6a4db94011d3	1678	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
sahilmgandhi	18:6a4db94011d3	1679	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
sahilmgandhi	18:6a4db94011d3	1680	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
sahilmgandhi	18:6a4db94011d3	1681	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	1682	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	1683	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	1684	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	1685	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	1686
sahilmgandhi	18:6a4db94011d3	1687	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	1688	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	1689	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	1690	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	1691	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	1692	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	1693	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
sahilmgandhi	18:6a4db94011d3	1694	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
sahilmgandhi	18:6a4db94011d3	1695	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
sahilmgandhi	18:6a4db94011d3	1696	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
sahilmgandhi	18:6a4db94011d3	1697	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
sahilmgandhi	18:6a4db94011d3	1698	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
sahilmgandhi	18:6a4db94011d3	1699	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
sahilmgandhi	18:6a4db94011d3	1700	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
sahilmgandhi	18:6a4db94011d3	1701	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
sahilmgandhi	18:6a4db94011d3	1702	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
sahilmgandhi	18:6a4db94011d3	1703	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
sahilmgandhi	18:6a4db94011d3	1704	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
sahilmgandhi	18:6a4db94011d3	1705	/**
sahilmgandhi	18:6a4db94011d3	1706	* @}
sahilmgandhi	18:6a4db94011d3	1707	*/
sahilmgandhi	18:6a4db94011d3	1708
sahilmgandhi	18:6a4db94011d3	1709	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	1710	* @brief Force or release APB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	1711	* @{
sahilmgandhi	18:6a4db94011d3	1712	*/
sahilmgandhi	18:6a4db94011d3	1713	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
sahilmgandhi	18:6a4db94011d3	1714	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
sahilmgandhi	18:6a4db94011d3	1715	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
sahilmgandhi	18:6a4db94011d3	1716	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
sahilmgandhi	18:6a4db94011d3	1717	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	1718	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	1719	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	1720
sahilmgandhi	18:6a4db94011d3	1721	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	1722	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	1723	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	1724	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
sahilmgandhi	18:6a4db94011d3	1725	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
sahilmgandhi	18:6a4db94011d3	1726	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
sahilmgandhi	18:6a4db94011d3	1727	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
sahilmgandhi	18:6a4db94011d3	1728
sahilmgandhi	18:6a4db94011d3	1729	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1730	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
sahilmgandhi	18:6a4db94011d3	1731	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
sahilmgandhi	18:6a4db94011d3	1732	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1733
sahilmgandhi	18:6a4db94011d3	1734	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1735	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
sahilmgandhi	18:6a4db94011d3	1736	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
sahilmgandhi	18:6a4db94011d3	1737	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1738	/**
sahilmgandhi	18:6a4db94011d3	1739	* @}
sahilmgandhi	18:6a4db94011d3	1740	*/
sahilmgandhi	18:6a4db94011d3	1741
sahilmgandhi	18:6a4db94011d3	1742	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	1743	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	1744	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	1745	* power consumption.
sahilmgandhi	18:6a4db94011d3	1746	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	1747	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	1748	* @{
sahilmgandhi	18:6a4db94011d3	1749	*/
sahilmgandhi	18:6a4db94011d3	1750	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	1751	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	1752	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
sahilmgandhi	18:6a4db94011d3	1753	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
sahilmgandhi	18:6a4db94011d3	1754	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
sahilmgandhi	18:6a4db94011d3	1755	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
sahilmgandhi	18:6a4db94011d3	1756	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
sahilmgandhi	18:6a4db94011d3	1757	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
sahilmgandhi	18:6a4db94011d3	1758	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
sahilmgandhi	18:6a4db94011d3	1759	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
sahilmgandhi	18:6a4db94011d3	1760	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
sahilmgandhi	18:6a4db94011d3	1761	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
sahilmgandhi	18:6a4db94011d3	1762	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
sahilmgandhi	18:6a4db94011d3	1763	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
sahilmgandhi	18:6a4db94011d3	1764	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
sahilmgandhi	18:6a4db94011d3	1765	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
sahilmgandhi	18:6a4db94011d3	1766	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	1767	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	1768	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	1769	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
sahilmgandhi	18:6a4db94011d3	1770
sahilmgandhi	18:6a4db94011d3	1771	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	1772	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	1773	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
sahilmgandhi	18:6a4db94011d3	1774	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
sahilmgandhi	18:6a4db94011d3	1775	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
sahilmgandhi	18:6a4db94011d3	1776	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
sahilmgandhi	18:6a4db94011d3	1777	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
sahilmgandhi	18:6a4db94011d3	1778	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
sahilmgandhi	18:6a4db94011d3	1779	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
sahilmgandhi	18:6a4db94011d3	1780	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
sahilmgandhi	18:6a4db94011d3	1781	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
sahilmgandhi	18:6a4db94011d3	1782	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
sahilmgandhi	18:6a4db94011d3	1783	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
sahilmgandhi	18:6a4db94011d3	1784	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
sahilmgandhi	18:6a4db94011d3	1785	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
sahilmgandhi	18:6a4db94011d3	1786	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	1787	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	1788	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	1789	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
sahilmgandhi	18:6a4db94011d3	1790	/**
sahilmgandhi	18:6a4db94011d3	1791	* @}
sahilmgandhi	18:6a4db94011d3	1792	*/
sahilmgandhi	18:6a4db94011d3	1793
sahilmgandhi	18:6a4db94011d3	1794	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	1795	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	1796	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	1797	* power consumption.
sahilmgandhi	18:6a4db94011d3	1798	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	1799	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	1800	* @{
sahilmgandhi	18:6a4db94011d3	1801	*/
sahilmgandhi	18:6a4db94011d3	1802	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	1803	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	1804
sahilmgandhi	18:6a4db94011d3	1805	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	1806	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	1807
sahilmgandhi	18:6a4db94011d3	1808	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
sahilmgandhi	18:6a4db94011d3	1809	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
sahilmgandhi	18:6a4db94011d3	1810
sahilmgandhi	18:6a4db94011d3	1811	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1812	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
sahilmgandhi	18:6a4db94011d3	1813	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
sahilmgandhi	18:6a4db94011d3	1814
sahilmgandhi	18:6a4db94011d3	1815	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
sahilmgandhi	18:6a4db94011d3	1816	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
sahilmgandhi	18:6a4db94011d3	1817	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1818	/**
sahilmgandhi	18:6a4db94011d3	1819	* @}
sahilmgandhi	18:6a4db94011d3	1820	*/
sahilmgandhi	18:6a4db94011d3	1821
sahilmgandhi	18:6a4db94011d3	1822	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	1823	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	1824	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	1825	* power consumption.
sahilmgandhi	18:6a4db94011d3	1826	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	1827	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	1828	* @{
sahilmgandhi	18:6a4db94011d3	1829	*/
sahilmgandhi	18:6a4db94011d3	1830	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
sahilmgandhi	18:6a4db94011d3	1831	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
sahilmgandhi	18:6a4db94011d3	1832
sahilmgandhi	18:6a4db94011d3	1833	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1834	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
sahilmgandhi	18:6a4db94011d3	1835	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
sahilmgandhi	18:6a4db94011d3	1836	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1837	/**
sahilmgandhi	18:6a4db94011d3	1838	* @}
sahilmgandhi	18:6a4db94011d3	1839	*/
sahilmgandhi	18:6a4db94011d3	1840
sahilmgandhi	18:6a4db94011d3	1841	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	1842	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	1843	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	1844	* power consumption.
sahilmgandhi	18:6a4db94011d3	1845	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	1846	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	1847	* @{
sahilmgandhi	18:6a4db94011d3	1848	*/
sahilmgandhi	18:6a4db94011d3	1849	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	1850	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
sahilmgandhi	18:6a4db94011d3	1851	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
sahilmgandhi	18:6a4db94011d3	1852	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
sahilmgandhi	18:6a4db94011d3	1853	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
sahilmgandhi	18:6a4db94011d3	1854	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
sahilmgandhi	18:6a4db94011d3	1855	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
sahilmgandhi	18:6a4db94011d3	1856	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
sahilmgandhi	18:6a4db94011d3	1857	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
sahilmgandhi	18:6a4db94011d3	1858	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
sahilmgandhi	18:6a4db94011d3	1859	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
sahilmgandhi	18:6a4db94011d3	1860	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
sahilmgandhi	18:6a4db94011d3	1861	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
sahilmgandhi	18:6a4db94011d3	1862	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	1863	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	1864	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	1865	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	1866	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	1867
sahilmgandhi	18:6a4db94011d3	1868	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	1869	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	1870	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	1871	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	1872	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	1873	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	1874	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
sahilmgandhi	18:6a4db94011d3	1875	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
sahilmgandhi	18:6a4db94011d3	1876	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
sahilmgandhi	18:6a4db94011d3	1877	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
sahilmgandhi	18:6a4db94011d3	1878	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
sahilmgandhi	18:6a4db94011d3	1879	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
sahilmgandhi	18:6a4db94011d3	1880	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
sahilmgandhi	18:6a4db94011d3	1881	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
sahilmgandhi	18:6a4db94011d3	1882	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
sahilmgandhi	18:6a4db94011d3	1883	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
sahilmgandhi	18:6a4db94011d3	1884	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
sahilmgandhi	18:6a4db94011d3	1885	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
sahilmgandhi	18:6a4db94011d3	1886	/**
sahilmgandhi	18:6a4db94011d3	1887	* @}
sahilmgandhi	18:6a4db94011d3	1888	*/
sahilmgandhi	18:6a4db94011d3	1889
sahilmgandhi	18:6a4db94011d3	1890	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	1891	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	1892	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	1893	* power consumption.
sahilmgandhi	18:6a4db94011d3	1894	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	1895	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	1896	* @{
sahilmgandhi	18:6a4db94011d3	1897	*/
sahilmgandhi	18:6a4db94011d3	1898	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
sahilmgandhi	18:6a4db94011d3	1899	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
sahilmgandhi	18:6a4db94011d3	1900	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
sahilmgandhi	18:6a4db94011d3	1901	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
sahilmgandhi	18:6a4db94011d3	1902	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
sahilmgandhi	18:6a4db94011d3	1903	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
sahilmgandhi	18:6a4db94011d3	1904	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	1905	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	1906	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	1907
sahilmgandhi	18:6a4db94011d3	1908	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	1909	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	1910	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	1911	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
sahilmgandhi	18:6a4db94011d3	1912	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
sahilmgandhi	18:6a4db94011d3	1913	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
sahilmgandhi	18:6a4db94011d3	1914	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
sahilmgandhi	18:6a4db94011d3	1915	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
sahilmgandhi	18:6a4db94011d3	1916	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
sahilmgandhi	18:6a4db94011d3	1917
sahilmgandhi	18:6a4db94011d3	1918	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1919	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
sahilmgandhi	18:6a4db94011d3	1920
sahilmgandhi	18:6a4db94011d3	1921	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
sahilmgandhi	18:6a4db94011d3	1922	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1923
sahilmgandhi	18:6a4db94011d3	1924	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	1925	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
sahilmgandhi	18:6a4db94011d3	1926	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
sahilmgandhi	18:6a4db94011d3	1927	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1928	/**
sahilmgandhi	18:6a4db94011d3	1929	* @}
sahilmgandhi	18:6a4db94011d3	1930	*/
sahilmgandhi	18:6a4db94011d3	1931	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1932	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1933
sahilmgandhi	18:6a4db94011d3	1934	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
sahilmgandhi	18:6a4db94011d3	1935	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	1936	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	1937	* @brief Enables or disables the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	1938	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	1939	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	1940	* using it.
sahilmgandhi	18:6a4db94011d3	1941	* @{
sahilmgandhi	18:6a4db94011d3	1942	*/
sahilmgandhi	18:6a4db94011d3	1943	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1944	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1945	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	1946	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1947	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	1948	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1949	} while(0)
sahilmgandhi	18:6a4db94011d3	1950	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1951	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1952	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	1953	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1954	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	1955	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1956	} while(0)
sahilmgandhi	18:6a4db94011d3	1957	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1958	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1959	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	1960	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1961	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	1962	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1963	} while(0)
sahilmgandhi	18:6a4db94011d3	1964	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1965	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1966	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	1967	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1968	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	1969	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1970	} while(0)
sahilmgandhi	18:6a4db94011d3	1971	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1972	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1973	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	1974	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1975	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	1976	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1977	} while(0)
sahilmgandhi	18:6a4db94011d3	1978	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1979	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1980	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
sahilmgandhi	18:6a4db94011d3	1981	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1982	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
sahilmgandhi	18:6a4db94011d3	1983	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1984	} while(0)
sahilmgandhi	18:6a4db94011d3	1985	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1986	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1987	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
sahilmgandhi	18:6a4db94011d3	1988	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1989	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
sahilmgandhi	18:6a4db94011d3	1990	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1991	} while(0)
sahilmgandhi	18:6a4db94011d3	1992	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	1993	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	1994	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
sahilmgandhi	18:6a4db94011d3	1995	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	1996	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
sahilmgandhi	18:6a4db94011d3	1997	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	1998	} while(0)
sahilmgandhi	18:6a4db94011d3	1999	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2000	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2001	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
sahilmgandhi	18:6a4db94011d3	2002	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2003	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
sahilmgandhi	18:6a4db94011d3	2004	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2005	} while(0)
sahilmgandhi	18:6a4db94011d3	2006	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2007	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2008	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
sahilmgandhi	18:6a4db94011d3	2009	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2010	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
sahilmgandhi	18:6a4db94011d3	2011	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2012	} while(0)
sahilmgandhi	18:6a4db94011d3	2013	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
sahilmgandhi	18:6a4db94011d3	2014	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
sahilmgandhi	18:6a4db94011d3	2015	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
sahilmgandhi	18:6a4db94011d3	2016	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
sahilmgandhi	18:6a4db94011d3	2017	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
sahilmgandhi	18:6a4db94011d3	2018	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
sahilmgandhi	18:6a4db94011d3	2019	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
sahilmgandhi	18:6a4db94011d3	2020	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
sahilmgandhi	18:6a4db94011d3	2021	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
sahilmgandhi	18:6a4db94011d3	2022	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
sahilmgandhi	18:6a4db94011d3	2023	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2024	/**
sahilmgandhi	18:6a4db94011d3	2025	* @brief Enable ETHERNET clock.
sahilmgandhi	18:6a4db94011d3	2026	*/
sahilmgandhi	18:6a4db94011d3	2027	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2028	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2029	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
sahilmgandhi	18:6a4db94011d3	2030	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2031	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
sahilmgandhi	18:6a4db94011d3	2032	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2033	} while(0)
sahilmgandhi	18:6a4db94011d3	2034	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2035	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2036	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
sahilmgandhi	18:6a4db94011d3	2037	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2038	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
sahilmgandhi	18:6a4db94011d3	2039	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2040	} while(0)
sahilmgandhi	18:6a4db94011d3	2041	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2042	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2043	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
sahilmgandhi	18:6a4db94011d3	2044	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2045	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
sahilmgandhi	18:6a4db94011d3	2046	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2047	} while(0)
sahilmgandhi	18:6a4db94011d3	2048	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2049	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2050	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
sahilmgandhi	18:6a4db94011d3	2051	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2052	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
sahilmgandhi	18:6a4db94011d3	2053	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2054	} while(0)
sahilmgandhi	18:6a4db94011d3	2055	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2056	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
sahilmgandhi	18:6a4db94011d3	2057	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
sahilmgandhi	18:6a4db94011d3	2058	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
sahilmgandhi	18:6a4db94011d3	2059	} while(0)
sahilmgandhi	18:6a4db94011d3	2060
sahilmgandhi	18:6a4db94011d3	2061	/**
sahilmgandhi	18:6a4db94011d3	2062	* @brief Disable ETHERNET clock.
sahilmgandhi	18:6a4db94011d3	2063	*/
sahilmgandhi	18:6a4db94011d3	2064	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
sahilmgandhi	18:6a4db94011d3	2065	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
sahilmgandhi	18:6a4db94011d3	2066	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
sahilmgandhi	18:6a4db94011d3	2067	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
sahilmgandhi	18:6a4db94011d3	2068	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
sahilmgandhi	18:6a4db94011d3	2069	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
sahilmgandhi	18:6a4db94011d3	2070	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
sahilmgandhi	18:6a4db94011d3	2071	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
sahilmgandhi	18:6a4db94011d3	2072	} while(0)
sahilmgandhi	18:6a4db94011d3	2073	#endif /* STM32F407xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2074	/**
sahilmgandhi	18:6a4db94011d3	2075	* @}
sahilmgandhi	18:6a4db94011d3	2076	*/
sahilmgandhi	18:6a4db94011d3	2077
sahilmgandhi	18:6a4db94011d3	2078	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	2079	* @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2080	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2081	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2082	* using it.
sahilmgandhi	18:6a4db94011d3	2083	* @{
sahilmgandhi	18:6a4db94011d3	2084	*/
sahilmgandhi	18:6a4db94011d3	2085	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2086	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2087	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2088	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2089	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2090	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2091	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2092	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2093	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2094	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2095
sahilmgandhi	18:6a4db94011d3	2096	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2097	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2098	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2099	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2100	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2101	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2102	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
sahilmgandhi	18:6a4db94011d3	2103	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2104	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2105	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2106	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2107	/**
sahilmgandhi	18:6a4db94011d3	2108	* @brief Enable ETHERNET clock.
sahilmgandhi	18:6a4db94011d3	2109	*/
sahilmgandhi	18:6a4db94011d3	2110	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2111	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2112	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2113	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2114	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
sahilmgandhi	18:6a4db94011d3	2115	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
sahilmgandhi	18:6a4db94011d3	2116	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
sahilmgandhi	18:6a4db94011d3	2117	/**
sahilmgandhi	18:6a4db94011d3	2118	* @brief Disable ETHERNET clock.
sahilmgandhi	18:6a4db94011d3	2119	*/
sahilmgandhi	18:6a4db94011d3	2120	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2121	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2122	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2123	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2124	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
sahilmgandhi	18:6a4db94011d3	2125	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
sahilmgandhi	18:6a4db94011d3	2126	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
sahilmgandhi	18:6a4db94011d3	2127	#endif /* STM32F407xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2128	/**
sahilmgandhi	18:6a4db94011d3	2129	* @}
sahilmgandhi	18:6a4db94011d3	2130	*/
sahilmgandhi	18:6a4db94011d3	2131
sahilmgandhi	18:6a4db94011d3	2132	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	2133	* @brief Enable or disable the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2134	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2135	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2136	* using it.
sahilmgandhi	18:6a4db94011d3	2137	* @{
sahilmgandhi	18:6a4db94011d3	2138	*/
sahilmgandhi	18:6a4db94011d3	2139	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
sahilmgandhi	18:6a4db94011d3	2140	__HAL_RCC_SYSCFG_CLK_ENABLE();\
sahilmgandhi	18:6a4db94011d3	2141	}while(0)
sahilmgandhi	18:6a4db94011d3	2142
sahilmgandhi	18:6a4db94011d3	2143	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
sahilmgandhi	18:6a4db94011d3	2144
sahilmgandhi	18:6a4db94011d3	2145	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2146	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2147	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	2148	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2149	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	2150	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2151	} while(0)
sahilmgandhi	18:6a4db94011d3	2152	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
sahilmgandhi	18:6a4db94011d3	2153
sahilmgandhi	18:6a4db94011d3	2154	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2155	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2156	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2157	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
sahilmgandhi	18:6a4db94011d3	2158	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2159	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
sahilmgandhi	18:6a4db94011d3	2160	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2161	} while(0)
sahilmgandhi	18:6a4db94011d3	2162	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
sahilmgandhi	18:6a4db94011d3	2163	#endif /* STM32F407xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2164
sahilmgandhi	18:6a4db94011d3	2165	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2166	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2167	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2168	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
sahilmgandhi	18:6a4db94011d3	2169	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2170	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
sahilmgandhi	18:6a4db94011d3	2171	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2172	} while(0)
sahilmgandhi	18:6a4db94011d3	2173	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2174	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2175	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
sahilmgandhi	18:6a4db94011d3	2176	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2177	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
sahilmgandhi	18:6a4db94011d3	2178	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2179	} while(0)
sahilmgandhi	18:6a4db94011d3	2180	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
sahilmgandhi	18:6a4db94011d3	2181	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
sahilmgandhi	18:6a4db94011d3	2182	#endif /* STM32F415xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2183	/**
sahilmgandhi	18:6a4db94011d3	2184	* @}
sahilmgandhi	18:6a4db94011d3	2185	*/
sahilmgandhi	18:6a4db94011d3	2186
sahilmgandhi	18:6a4db94011d3	2187
sahilmgandhi	18:6a4db94011d3	2188	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	2189	* @brief Get the enable or disable status of the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2190	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2191	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2192	* using it.
sahilmgandhi	18:6a4db94011d3	2193	* @{
sahilmgandhi	18:6a4db94011d3	2194	*/
sahilmgandhi	18:6a4db94011d3	2195	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2196	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2197
sahilmgandhi	18:6a4db94011d3	2198	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2199	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2200
sahilmgandhi	18:6a4db94011d3	2201	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2202	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2203	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2204	#endif /* STM32F407xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2205
sahilmgandhi	18:6a4db94011d3	2206	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2207	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2208	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2209
sahilmgandhi	18:6a4db94011d3	2210	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2211	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2212	#endif /* STM32F415xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2213	/**
sahilmgandhi	18:6a4db94011d3	2214	* @}
sahilmgandhi	18:6a4db94011d3	2215	*/
sahilmgandhi	18:6a4db94011d3	2216
sahilmgandhi	18:6a4db94011d3	2217	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	2218	* @brief Enables or disables the AHB3 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2219	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2220	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2221	* using it.
sahilmgandhi	18:6a4db94011d3	2222	* @{
sahilmgandhi	18:6a4db94011d3	2223	*/
sahilmgandhi	18:6a4db94011d3	2224	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2225	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2226	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
sahilmgandhi	18:6a4db94011d3	2227	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2228	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
sahilmgandhi	18:6a4db94011d3	2229	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2230	} while(0)
sahilmgandhi	18:6a4db94011d3	2231	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
sahilmgandhi	18:6a4db94011d3	2232	/**
sahilmgandhi	18:6a4db94011d3	2233	* @}
sahilmgandhi	18:6a4db94011d3	2234	*/
sahilmgandhi	18:6a4db94011d3	2235
sahilmgandhi	18:6a4db94011d3	2236	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	2237	* @brief Get the enable or disable status of the AHB3 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2238	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2239	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2240	* using it.
sahilmgandhi	18:6a4db94011d3	2241	* @{
sahilmgandhi	18:6a4db94011d3	2242	*/
sahilmgandhi	18:6a4db94011d3	2243	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2244	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2245	/**
sahilmgandhi	18:6a4db94011d3	2246	* @}
sahilmgandhi	18:6a4db94011d3	2247	*/
sahilmgandhi	18:6a4db94011d3	2248
sahilmgandhi	18:6a4db94011d3	2249	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	2250	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
sahilmgandhi	18:6a4db94011d3	2251	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2252	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2253	* using it.
sahilmgandhi	18:6a4db94011d3	2254	* @{
sahilmgandhi	18:6a4db94011d3	2255	*/
sahilmgandhi	18:6a4db94011d3	2256	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2257	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2258	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	2259	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2260	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	2261	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2262	} while(0)
sahilmgandhi	18:6a4db94011d3	2263	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2264	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
sahilmgandhi	18:6a4db94011d3	2266	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
sahilmgandhi	18:6a4db94011d3	2268	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2269	} while(0)
sahilmgandhi	18:6a4db94011d3	2270	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2271	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2272	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
sahilmgandhi	18:6a4db94011d3	2273	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2274	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
sahilmgandhi	18:6a4db94011d3	2275	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2276	} while(0)
sahilmgandhi	18:6a4db94011d3	2277	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2278	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2279	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
sahilmgandhi	18:6a4db94011d3	2280	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2281	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
sahilmgandhi	18:6a4db94011d3	2282	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2283	} while(0)
sahilmgandhi	18:6a4db94011d3	2284	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2285	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2286	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	2287	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2288	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	2289	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2290	} while(0)
sahilmgandhi	18:6a4db94011d3	2291	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2292	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2293	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
sahilmgandhi	18:6a4db94011d3	2294	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2295	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
sahilmgandhi	18:6a4db94011d3	2296	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2297	} while(0)
sahilmgandhi	18:6a4db94011d3	2298	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2299	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2300	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
sahilmgandhi	18:6a4db94011d3	2301	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2302	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
sahilmgandhi	18:6a4db94011d3	2303	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2304	} while(0)
sahilmgandhi	18:6a4db94011d3	2305	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2306	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2307	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
sahilmgandhi	18:6a4db94011d3	2308	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2309	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
sahilmgandhi	18:6a4db94011d3	2310	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2311	} while(0)
sahilmgandhi	18:6a4db94011d3	2312	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2313	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2314	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
sahilmgandhi	18:6a4db94011d3	2315	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2316	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
sahilmgandhi	18:6a4db94011d3	2317	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2318	} while(0)
sahilmgandhi	18:6a4db94011d3	2319	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2320	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2321	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
sahilmgandhi	18:6a4db94011d3	2322	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2323	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
sahilmgandhi	18:6a4db94011d3	2324	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2325	} while(0)
sahilmgandhi	18:6a4db94011d3	2326	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2327	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2328	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
sahilmgandhi	18:6a4db94011d3	2329	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2330	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
sahilmgandhi	18:6a4db94011d3	2331	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2332	} while(0)
sahilmgandhi	18:6a4db94011d3	2333	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2334	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2335	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	2336	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2337	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	2338	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2339	} while(0)
sahilmgandhi	18:6a4db94011d3	2340	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2341	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2342	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	2343	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2344	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	2345	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2346	} while(0)
sahilmgandhi	18:6a4db94011d3	2347	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2348	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2349	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	2350	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2351	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	2352	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2353	} while(0)
sahilmgandhi	18:6a4db94011d3	2354	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2355	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2356	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	2357	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2358	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	2359	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2360	} while(0)
sahilmgandhi	18:6a4db94011d3	2361	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2362	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2363	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	2364	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2365	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	2366	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2367	} while(0)
sahilmgandhi	18:6a4db94011d3	2368	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
sahilmgandhi	18:6a4db94011d3	2369	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
sahilmgandhi	18:6a4db94011d3	2370	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
sahilmgandhi	18:6a4db94011d3	2371	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
sahilmgandhi	18:6a4db94011d3	2372	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
sahilmgandhi	18:6a4db94011d3	2373	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
sahilmgandhi	18:6a4db94011d3	2374	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
sahilmgandhi	18:6a4db94011d3	2375	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
sahilmgandhi	18:6a4db94011d3	2376	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
sahilmgandhi	18:6a4db94011d3	2377	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
sahilmgandhi	18:6a4db94011d3	2378	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
sahilmgandhi	18:6a4db94011d3	2379	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
sahilmgandhi	18:6a4db94011d3	2380	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
sahilmgandhi	18:6a4db94011d3	2381	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
sahilmgandhi	18:6a4db94011d3	2382	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
sahilmgandhi	18:6a4db94011d3	2383	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
sahilmgandhi	18:6a4db94011d3	2384	/**
sahilmgandhi	18:6a4db94011d3	2385	* @}
sahilmgandhi	18:6a4db94011d3	2386	*/
sahilmgandhi	18:6a4db94011d3	2387
sahilmgandhi	18:6a4db94011d3	2388	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	2389	* @brief Get the enable or disable status of the APB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2390	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2391	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2392	* using it.
sahilmgandhi	18:6a4db94011d3	2393	* @{
sahilmgandhi	18:6a4db94011d3	2394	*/
sahilmgandhi	18:6a4db94011d3	2395	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2396	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2397	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2398	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2399	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2400	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2401	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2402	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2403	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2404	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2405	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2406	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2407	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2408	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2409	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2410	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2411
sahilmgandhi	18:6a4db94011d3	2412	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2413	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2414	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2415	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2416	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2417	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2418	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2419	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2420	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2421	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2422	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2423	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2424	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2425	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2426	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2427	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2428	/**
sahilmgandhi	18:6a4db94011d3	2429	* @}
sahilmgandhi	18:6a4db94011d3	2430	*/
sahilmgandhi	18:6a4db94011d3	2431
sahilmgandhi	18:6a4db94011d3	2432	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	2433	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
sahilmgandhi	18:6a4db94011d3	2434	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2435	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2436	* using it.
sahilmgandhi	18:6a4db94011d3	2437	* @{
sahilmgandhi	18:6a4db94011d3	2438	*/
sahilmgandhi	18:6a4db94011d3	2439	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2440	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2441	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
sahilmgandhi	18:6a4db94011d3	2442	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2443	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
sahilmgandhi	18:6a4db94011d3	2444	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2445	} while(0)
sahilmgandhi	18:6a4db94011d3	2446	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2447	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2448	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
sahilmgandhi	18:6a4db94011d3	2449	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2450	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
sahilmgandhi	18:6a4db94011d3	2451	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2452	} while(0)
sahilmgandhi	18:6a4db94011d3	2453	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2454	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2455	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
sahilmgandhi	18:6a4db94011d3	2456	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2457	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
sahilmgandhi	18:6a4db94011d3	2458	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2459	} while(0)
sahilmgandhi	18:6a4db94011d3	2460	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2461	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2462	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	2463	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2464	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	2465	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2466	} while(0)
sahilmgandhi	18:6a4db94011d3	2467	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2468	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2469	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	2470	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2471	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	2472	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2473	} while(0)
sahilmgandhi	18:6a4db94011d3	2474	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2475	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2476	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	2477	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2478	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	2479	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2480	} while(0)
sahilmgandhi	18:6a4db94011d3	2481
sahilmgandhi	18:6a4db94011d3	2482	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
sahilmgandhi	18:6a4db94011d3	2483	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
sahilmgandhi	18:6a4db94011d3	2484	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
sahilmgandhi	18:6a4db94011d3	2485	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
sahilmgandhi	18:6a4db94011d3	2486	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
sahilmgandhi	18:6a4db94011d3	2487	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
sahilmgandhi	18:6a4db94011d3	2488	/**
sahilmgandhi	18:6a4db94011d3	2489	* @}
sahilmgandhi	18:6a4db94011d3	2490	*/
sahilmgandhi	18:6a4db94011d3	2491
sahilmgandhi	18:6a4db94011d3	2492	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	2493	* @brief Get the enable or disable status of the APB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2494	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2495	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2496	* using it.
sahilmgandhi	18:6a4db94011d3	2497	* @{
sahilmgandhi	18:6a4db94011d3	2498	*/
sahilmgandhi	18:6a4db94011d3	2499	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2500	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2501	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2502	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2503	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2504	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2505
sahilmgandhi	18:6a4db94011d3	2506	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2507	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2508	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2509	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2510	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2511	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2512	/**
sahilmgandhi	18:6a4db94011d3	2513	* @}
sahilmgandhi	18:6a4db94011d3	2514	*/
sahilmgandhi	18:6a4db94011d3	2515
sahilmgandhi	18:6a4db94011d3	2516	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	2517	* @brief Force or release AHB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	2518	* @{
sahilmgandhi	18:6a4db94011d3	2519	*/
sahilmgandhi	18:6a4db94011d3	2520	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	2521	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	2522	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
sahilmgandhi	18:6a4db94011d3	2523	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
sahilmgandhi	18:6a4db94011d3	2524	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
sahilmgandhi	18:6a4db94011d3	2525	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
sahilmgandhi	18:6a4db94011d3	2526	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
sahilmgandhi	18:6a4db94011d3	2527	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	2528
sahilmgandhi	18:6a4db94011d3	2529	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	2530	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	2531	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
sahilmgandhi	18:6a4db94011d3	2532	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
sahilmgandhi	18:6a4db94011d3	2533	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
sahilmgandhi	18:6a4db94011d3	2534	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
sahilmgandhi	18:6a4db94011d3	2535	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
sahilmgandhi	18:6a4db94011d3	2536	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	2537	/**
sahilmgandhi	18:6a4db94011d3	2538	* @}
sahilmgandhi	18:6a4db94011d3	2539	*/
sahilmgandhi	18:6a4db94011d3	2540
sahilmgandhi	18:6a4db94011d3	2541	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	2542	* @brief Force or release AHB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	2543	* @{
sahilmgandhi	18:6a4db94011d3	2544	*/
sahilmgandhi	18:6a4db94011d3	2545	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	2546	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	2547
sahilmgandhi	18:6a4db94011d3	2548	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2549	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
sahilmgandhi	18:6a4db94011d3	2550	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
sahilmgandhi	18:6a4db94011d3	2551	#endif /* STM32F407xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2552
sahilmgandhi	18:6a4db94011d3	2553	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2554	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
sahilmgandhi	18:6a4db94011d3	2555	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
sahilmgandhi	18:6a4db94011d3	2556
sahilmgandhi	18:6a4db94011d3	2557	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
sahilmgandhi	18:6a4db94011d3	2558	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
sahilmgandhi	18:6a4db94011d3	2559	#endif /* STM32F415xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2560
sahilmgandhi	18:6a4db94011d3	2561	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	2562	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	2563
sahilmgandhi	18:6a4db94011d3	2564	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	2565	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	2566	/**
sahilmgandhi	18:6a4db94011d3	2567	* @}
sahilmgandhi	18:6a4db94011d3	2568	*/
sahilmgandhi	18:6a4db94011d3	2569
sahilmgandhi	18:6a4db94011d3	2570	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
sahilmgandhi	18:6a4db94011d3	2571	* @brief Force or release AHB3 peripheral reset.
sahilmgandhi	18:6a4db94011d3	2572	* @{
sahilmgandhi	18:6a4db94011d3	2573	*/
sahilmgandhi	18:6a4db94011d3	2574	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	2575	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	2576
sahilmgandhi	18:6a4db94011d3	2577	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
sahilmgandhi	18:6a4db94011d3	2578	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
sahilmgandhi	18:6a4db94011d3	2579	/**
sahilmgandhi	18:6a4db94011d3	2580	* @}
sahilmgandhi	18:6a4db94011d3	2581	*/
sahilmgandhi	18:6a4db94011d3	2582
sahilmgandhi	18:6a4db94011d3	2583	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	2584	* @brief Force or release APB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	2585	* @{
sahilmgandhi	18:6a4db94011d3	2586	*/
sahilmgandhi	18:6a4db94011d3	2587	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	2588	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
sahilmgandhi	18:6a4db94011d3	2589	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
sahilmgandhi	18:6a4db94011d3	2590	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
sahilmgandhi	18:6a4db94011d3	2591	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
sahilmgandhi	18:6a4db94011d3	2592	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
sahilmgandhi	18:6a4db94011d3	2593	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
sahilmgandhi	18:6a4db94011d3	2594	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
sahilmgandhi	18:6a4db94011d3	2595	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
sahilmgandhi	18:6a4db94011d3	2596	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
sahilmgandhi	18:6a4db94011d3	2597	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
sahilmgandhi	18:6a4db94011d3	2598	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	2599	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	2600	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	2601	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	2602	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	2603
sahilmgandhi	18:6a4db94011d3	2604	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	2605	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	2606	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	2607	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	2608	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	2609	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	2610	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
sahilmgandhi	18:6a4db94011d3	2611	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
sahilmgandhi	18:6a4db94011d3	2612	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
sahilmgandhi	18:6a4db94011d3	2613	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
sahilmgandhi	18:6a4db94011d3	2614	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
sahilmgandhi	18:6a4db94011d3	2615	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
sahilmgandhi	18:6a4db94011d3	2616	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
sahilmgandhi	18:6a4db94011d3	2617	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
sahilmgandhi	18:6a4db94011d3	2618	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
sahilmgandhi	18:6a4db94011d3	2619	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
sahilmgandhi	18:6a4db94011d3	2620	/**
sahilmgandhi	18:6a4db94011d3	2621	* @}
sahilmgandhi	18:6a4db94011d3	2622	*/
sahilmgandhi	18:6a4db94011d3	2623
sahilmgandhi	18:6a4db94011d3	2624	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	2625	* @brief Force or release APB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	2626	* @{
sahilmgandhi	18:6a4db94011d3	2627	*/
sahilmgandhi	18:6a4db94011d3	2628	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
sahilmgandhi	18:6a4db94011d3	2629	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	2630	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	2631	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	2632
sahilmgandhi	18:6a4db94011d3	2633	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	2634	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	2635	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	2636	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
sahilmgandhi	18:6a4db94011d3	2637	/**
sahilmgandhi	18:6a4db94011d3	2638	* @}
sahilmgandhi	18:6a4db94011d3	2639	*/
sahilmgandhi	18:6a4db94011d3	2640
sahilmgandhi	18:6a4db94011d3	2641	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	2642	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	2643	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	2644	* power consumption.
sahilmgandhi	18:6a4db94011d3	2645	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	2646	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	2647	* @{
sahilmgandhi	18:6a4db94011d3	2648	*/
sahilmgandhi	18:6a4db94011d3	2649	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	2650	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	2651	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
sahilmgandhi	18:6a4db94011d3	2652	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
sahilmgandhi	18:6a4db94011d3	2653	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
sahilmgandhi	18:6a4db94011d3	2654	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
sahilmgandhi	18:6a4db94011d3	2655	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
sahilmgandhi	18:6a4db94011d3	2656	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
sahilmgandhi	18:6a4db94011d3	2657	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
sahilmgandhi	18:6a4db94011d3	2658	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
sahilmgandhi	18:6a4db94011d3	2659	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
sahilmgandhi	18:6a4db94011d3	2660	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
sahilmgandhi	18:6a4db94011d3	2661	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	2662	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	2663	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	2664	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
sahilmgandhi	18:6a4db94011d3	2665
sahilmgandhi	18:6a4db94011d3	2666	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	2667	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	2668	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
sahilmgandhi	18:6a4db94011d3	2669	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
sahilmgandhi	18:6a4db94011d3	2670	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
sahilmgandhi	18:6a4db94011d3	2671	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
sahilmgandhi	18:6a4db94011d3	2672	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
sahilmgandhi	18:6a4db94011d3	2673	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
sahilmgandhi	18:6a4db94011d3	2674	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
sahilmgandhi	18:6a4db94011d3	2675	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
sahilmgandhi	18:6a4db94011d3	2676	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
sahilmgandhi	18:6a4db94011d3	2677	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
sahilmgandhi	18:6a4db94011d3	2678	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	2679	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	2680	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	2681	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
sahilmgandhi	18:6a4db94011d3	2682	/**
sahilmgandhi	18:6a4db94011d3	2683	* @}
sahilmgandhi	18:6a4db94011d3	2684	*/
sahilmgandhi	18:6a4db94011d3	2685
sahilmgandhi	18:6a4db94011d3	2686	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	2687	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	2688	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	2689	* power consumption.
sahilmgandhi	18:6a4db94011d3	2690	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	2691	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	2692	* @{
sahilmgandhi	18:6a4db94011d3	2693	*/
sahilmgandhi	18:6a4db94011d3	2694	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	2695	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	2696
sahilmgandhi	18:6a4db94011d3	2697	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	2698	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	2699
sahilmgandhi	18:6a4db94011d3	2700	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2701	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
sahilmgandhi	18:6a4db94011d3	2702	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
sahilmgandhi	18:6a4db94011d3	2703	#endif /* STM32F407xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2704
sahilmgandhi	18:6a4db94011d3	2705	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	2706	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
sahilmgandhi	18:6a4db94011d3	2707	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
sahilmgandhi	18:6a4db94011d3	2708
sahilmgandhi	18:6a4db94011d3	2709	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
sahilmgandhi	18:6a4db94011d3	2710	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
sahilmgandhi	18:6a4db94011d3	2711	#endif /* STM32F415xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2712	/**
sahilmgandhi	18:6a4db94011d3	2713	* @}
sahilmgandhi	18:6a4db94011d3	2714	*/
sahilmgandhi	18:6a4db94011d3	2715
sahilmgandhi	18:6a4db94011d3	2716	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	2717	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	2718	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	2719	* power consumption.
sahilmgandhi	18:6a4db94011d3	2720	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	2721	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	2722	* @{
sahilmgandhi	18:6a4db94011d3	2723	*/
sahilmgandhi	18:6a4db94011d3	2724	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
sahilmgandhi	18:6a4db94011d3	2725	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
sahilmgandhi	18:6a4db94011d3	2726	/**
sahilmgandhi	18:6a4db94011d3	2727	* @}
sahilmgandhi	18:6a4db94011d3	2728	*/
sahilmgandhi	18:6a4db94011d3	2729
sahilmgandhi	18:6a4db94011d3	2730	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	2731	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	2732	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	2733	* power consumption.
sahilmgandhi	18:6a4db94011d3	2734	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	2735	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	2736	* @{
sahilmgandhi	18:6a4db94011d3	2737	*/
sahilmgandhi	18:6a4db94011d3	2738	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	2739	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
sahilmgandhi	18:6a4db94011d3	2740	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
sahilmgandhi	18:6a4db94011d3	2741	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
sahilmgandhi	18:6a4db94011d3	2742	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
sahilmgandhi	18:6a4db94011d3	2743	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
sahilmgandhi	18:6a4db94011d3	2744	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
sahilmgandhi	18:6a4db94011d3	2745	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
sahilmgandhi	18:6a4db94011d3	2746	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
sahilmgandhi	18:6a4db94011d3	2747	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
sahilmgandhi	18:6a4db94011d3	2748	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
sahilmgandhi	18:6a4db94011d3	2749	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	2750	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	2751	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	2752	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	2753	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	2754
sahilmgandhi	18:6a4db94011d3	2755	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	2756	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	2757	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	2758	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	2759	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	2760	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	2761	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
sahilmgandhi	18:6a4db94011d3	2762	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
sahilmgandhi	18:6a4db94011d3	2763	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
sahilmgandhi	18:6a4db94011d3	2764	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
sahilmgandhi	18:6a4db94011d3	2765	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
sahilmgandhi	18:6a4db94011d3	2766	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
sahilmgandhi	18:6a4db94011d3	2767	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
sahilmgandhi	18:6a4db94011d3	2768	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
sahilmgandhi	18:6a4db94011d3	2769	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
sahilmgandhi	18:6a4db94011d3	2770	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
sahilmgandhi	18:6a4db94011d3	2771	/**
sahilmgandhi	18:6a4db94011d3	2772	* @}
sahilmgandhi	18:6a4db94011d3	2773	*/
sahilmgandhi	18:6a4db94011d3	2774
sahilmgandhi	18:6a4db94011d3	2775	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	2776	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	2777	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	2778	* power consumption.
sahilmgandhi	18:6a4db94011d3	2779	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	2780	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	2781	* @{
sahilmgandhi	18:6a4db94011d3	2782	*/
sahilmgandhi	18:6a4db94011d3	2783	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
sahilmgandhi	18:6a4db94011d3	2784	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
sahilmgandhi	18:6a4db94011d3	2785	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
sahilmgandhi	18:6a4db94011d3	2786	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	2787	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	2788	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	2789
sahilmgandhi	18:6a4db94011d3	2790	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	2791	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	2792	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	2793	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
sahilmgandhi	18:6a4db94011d3	2794	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
sahilmgandhi	18:6a4db94011d3	2795	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
sahilmgandhi	18:6a4db94011d3	2796	/**
sahilmgandhi	18:6a4db94011d3	2797	* @}
sahilmgandhi	18:6a4db94011d3	2798	*/
sahilmgandhi	18:6a4db94011d3	2799	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	2800	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	2801
sahilmgandhi	18:6a4db94011d3	2802	/------------------------- STM32F401xE/STM32F401xC --------------------------/
sahilmgandhi	18:6a4db94011d3	2803	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
sahilmgandhi	18:6a4db94011d3	2804	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	2805	* @brief Enable or disable the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2806	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2807	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2808	* using it.
sahilmgandhi	18:6a4db94011d3	2809	* @{
sahilmgandhi	18:6a4db94011d3	2810	*/
sahilmgandhi	18:6a4db94011d3	2811	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2812	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2813	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	2814	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2815	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	2816	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2817	} while(0)
sahilmgandhi	18:6a4db94011d3	2818	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2819	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2820	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	2821	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2822	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	2823	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2824	} while(0)
sahilmgandhi	18:6a4db94011d3	2825	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2826	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2827	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	2828	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2829	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	2830	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2831	} while(0)
sahilmgandhi	18:6a4db94011d3	2832	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2833	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2834	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	2835	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2836	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	2837	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2838	} while(0)
sahilmgandhi	18:6a4db94011d3	2839	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2840	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2841	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	2842	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2843	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	2844	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2845	} while(0)
sahilmgandhi	18:6a4db94011d3	2846
sahilmgandhi	18:6a4db94011d3	2847	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
sahilmgandhi	18:6a4db94011d3	2848	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
sahilmgandhi	18:6a4db94011d3	2849	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
sahilmgandhi	18:6a4db94011d3	2850	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
sahilmgandhi	18:6a4db94011d3	2851	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
sahilmgandhi	18:6a4db94011d3	2852	/**
sahilmgandhi	18:6a4db94011d3	2853	* @}
sahilmgandhi	18:6a4db94011d3	2854	*/
sahilmgandhi	18:6a4db94011d3	2855
sahilmgandhi	18:6a4db94011d3	2856	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	2857	* @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2858	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2859	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2860	* using it.
sahilmgandhi	18:6a4db94011d3	2861	* @{
sahilmgandhi	18:6a4db94011d3	2862	*/
sahilmgandhi	18:6a4db94011d3	2863	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2864	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2865	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2866	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2867	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2868
sahilmgandhi	18:6a4db94011d3	2869	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2870	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2871	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2872	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2873	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2874	/**
sahilmgandhi	18:6a4db94011d3	2875	* @}
sahilmgandhi	18:6a4db94011d3	2876	*/
sahilmgandhi	18:6a4db94011d3	2877
sahilmgandhi	18:6a4db94011d3	2878	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	2879	* @brief Enable or disable the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2880	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2881	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2882	* using it.
sahilmgandhi	18:6a4db94011d3	2883	* @{
sahilmgandhi	18:6a4db94011d3	2884	*/
sahilmgandhi	18:6a4db94011d3	2885	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
sahilmgandhi	18:6a4db94011d3	2886	__HAL_RCC_SYSCFG_CLK_ENABLE();\
sahilmgandhi	18:6a4db94011d3	2887	}while(0)
sahilmgandhi	18:6a4db94011d3	2888
sahilmgandhi	18:6a4db94011d3	2889	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
sahilmgandhi	18:6a4db94011d3	2890	/**
sahilmgandhi	18:6a4db94011d3	2891	* @}
sahilmgandhi	18:6a4db94011d3	2892	*/
sahilmgandhi	18:6a4db94011d3	2893
sahilmgandhi	18:6a4db94011d3	2894	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	2895	* @brief Get the enable or disable status of the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2896	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2897	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2898	* using it.
sahilmgandhi	18:6a4db94011d3	2899	* @{
sahilmgandhi	18:6a4db94011d3	2900	*/
sahilmgandhi	18:6a4db94011d3	2901	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2902	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2903	/**
sahilmgandhi	18:6a4db94011d3	2904	* @}
sahilmgandhi	18:6a4db94011d3	2905	*/
sahilmgandhi	18:6a4db94011d3	2906
sahilmgandhi	18:6a4db94011d3	2907	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	2908	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
sahilmgandhi	18:6a4db94011d3	2909	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2910	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2911	* using it.
sahilmgandhi	18:6a4db94011d3	2912	* @{
sahilmgandhi	18:6a4db94011d3	2913	*/
sahilmgandhi	18:6a4db94011d3	2914	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2915	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2916	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	2917	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2918	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	2919	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2920	} while(0)
sahilmgandhi	18:6a4db94011d3	2921	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2922	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2923	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	2924	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2925	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	2926	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2927	} while(0)
sahilmgandhi	18:6a4db94011d3	2928	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2929	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2930	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	2931	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2932	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	2933	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2934	} while(0)
sahilmgandhi	18:6a4db94011d3	2935	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2936	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2937	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	2938	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2939	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	2940	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2941	} while(0)
sahilmgandhi	18:6a4db94011d3	2942	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2943	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	2945	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	2947	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2948	} while(0)
sahilmgandhi	18:6a4db94011d3	2949	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
sahilmgandhi	18:6a4db94011d3	2950	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
sahilmgandhi	18:6a4db94011d3	2951	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
sahilmgandhi	18:6a4db94011d3	2952	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
sahilmgandhi	18:6a4db94011d3	2953	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
sahilmgandhi	18:6a4db94011d3	2954	/**
sahilmgandhi	18:6a4db94011d3	2955	* @}
sahilmgandhi	18:6a4db94011d3	2956	*/
sahilmgandhi	18:6a4db94011d3	2957
sahilmgandhi	18:6a4db94011d3	2958	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	2959	* @brief Get the enable or disable status of the APB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	2960	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2961	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2962	* using it.
sahilmgandhi	18:6a4db94011d3	2963	* @{
sahilmgandhi	18:6a4db94011d3	2964	*/
sahilmgandhi	18:6a4db94011d3	2965	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2966	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2967	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2968	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2969	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	2970
sahilmgandhi	18:6a4db94011d3	2971	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2972	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2973	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2974	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2975	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	2976	/**
sahilmgandhi	18:6a4db94011d3	2977	* @}
sahilmgandhi	18:6a4db94011d3	2978	*/
sahilmgandhi	18:6a4db94011d3	2979
sahilmgandhi	18:6a4db94011d3	2980	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	2981	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
sahilmgandhi	18:6a4db94011d3	2982	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	2983	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	2984	* using it.
sahilmgandhi	18:6a4db94011d3	2985	* @{
sahilmgandhi	18:6a4db94011d3	2986	*/
sahilmgandhi	18:6a4db94011d3	2987	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2988	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2989	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	2990	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2991	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	2992	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	2993	} while(0)
sahilmgandhi	18:6a4db94011d3	2994	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	2995	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	2996	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	2997	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	2998	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	2999	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3000	} while(0)
sahilmgandhi	18:6a4db94011d3	3001	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3002	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3003	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	3004	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3005	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	3006	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3007	} while(0)
sahilmgandhi	18:6a4db94011d3	3008
sahilmgandhi	18:6a4db94011d3	3009	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
sahilmgandhi	18:6a4db94011d3	3010	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
sahilmgandhi	18:6a4db94011d3	3011	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
sahilmgandhi	18:6a4db94011d3	3012	/**
sahilmgandhi	18:6a4db94011d3	3013	* @}
sahilmgandhi	18:6a4db94011d3	3014	*/
sahilmgandhi	18:6a4db94011d3	3015
sahilmgandhi	18:6a4db94011d3	3016	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3017	* @brief Get the enable or disable status of the APB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3018	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3019	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3020	* using it.
sahilmgandhi	18:6a4db94011d3	3021	* @{
sahilmgandhi	18:6a4db94011d3	3022	*/
sahilmgandhi	18:6a4db94011d3	3023	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3024	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3025	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3026	/**
sahilmgandhi	18:6a4db94011d3	3027	* @}
sahilmgandhi	18:6a4db94011d3	3028	*/
sahilmgandhi	18:6a4db94011d3	3029	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3030	* @brief Force or release AHB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3031	* @{
sahilmgandhi	18:6a4db94011d3	3032	*/
sahilmgandhi	18:6a4db94011d3	3033	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	3034	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	3035	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	3036	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	3037
sahilmgandhi	18:6a4db94011d3	3038	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	3039	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	3040	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	3041	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	3042	/**
sahilmgandhi	18:6a4db94011d3	3043	* @}
sahilmgandhi	18:6a4db94011d3	3044	*/
sahilmgandhi	18:6a4db94011d3	3045
sahilmgandhi	18:6a4db94011d3	3046	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3047	* @brief Force or release AHB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3048	* @{
sahilmgandhi	18:6a4db94011d3	3049	*/
sahilmgandhi	18:6a4db94011d3	3050	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	3051	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	3052
sahilmgandhi	18:6a4db94011d3	3053	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	3054	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	3055	/**
sahilmgandhi	18:6a4db94011d3	3056	* @}
sahilmgandhi	18:6a4db94011d3	3057	*/
sahilmgandhi	18:6a4db94011d3	3058
sahilmgandhi	18:6a4db94011d3	3059	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3060	* @brief Force or release APB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3061	* @{
sahilmgandhi	18:6a4db94011d3	3062	*/
sahilmgandhi	18:6a4db94011d3	3063	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	3064	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	3065	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	3066	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	3067	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	3068	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	3069
sahilmgandhi	18:6a4db94011d3	3070	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	3071	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	3072	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	3073	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	3074	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	3075	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	3076	/**
sahilmgandhi	18:6a4db94011d3	3077	* @}
sahilmgandhi	18:6a4db94011d3	3078	*/
sahilmgandhi	18:6a4db94011d3	3079
sahilmgandhi	18:6a4db94011d3	3080	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3081	* @brief Force or release APB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3082	* @{
sahilmgandhi	18:6a4db94011d3	3083	*/
sahilmgandhi	18:6a4db94011d3	3084	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	3085	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	3086	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	3087	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	3088
sahilmgandhi	18:6a4db94011d3	3089	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	3090	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	3091	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	3092	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	3093	/**
sahilmgandhi	18:6a4db94011d3	3094	* @}
sahilmgandhi	18:6a4db94011d3	3095	*/
sahilmgandhi	18:6a4db94011d3	3096
sahilmgandhi	18:6a4db94011d3	3097	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3098	* @brief Force or release AHB3 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3099	* @{
sahilmgandhi	18:6a4db94011d3	3100	*/
sahilmgandhi	18:6a4db94011d3	3101	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	3102	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	3103	/**
sahilmgandhi	18:6a4db94011d3	3104	* @}
sahilmgandhi	18:6a4db94011d3	3105	*/
sahilmgandhi	18:6a4db94011d3	3106
sahilmgandhi	18:6a4db94011d3	3107	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3108	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3109	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	3110	* power consumption.
sahilmgandhi	18:6a4db94011d3	3111	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	3112	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	3113	* @{
sahilmgandhi	18:6a4db94011d3	3114	*/
sahilmgandhi	18:6a4db94011d3	3115	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	3116	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	3117	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	3118	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	3119	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	3120	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
sahilmgandhi	18:6a4db94011d3	3121
sahilmgandhi	18:6a4db94011d3	3122	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	3123	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	3124	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	3125	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	3126	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	3127	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
sahilmgandhi	18:6a4db94011d3	3128	/**
sahilmgandhi	18:6a4db94011d3	3129	* @}
sahilmgandhi	18:6a4db94011d3	3130	*/
sahilmgandhi	18:6a4db94011d3	3131
sahilmgandhi	18:6a4db94011d3	3132	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3133	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3134	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	3135	* power consumption.
sahilmgandhi	18:6a4db94011d3	3136	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	3137	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	3138	* @{
sahilmgandhi	18:6a4db94011d3	3139	*/
sahilmgandhi	18:6a4db94011d3	3140	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	3141
sahilmgandhi	18:6a4db94011d3	3142	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	3143	/**
sahilmgandhi	18:6a4db94011d3	3144	* @}
sahilmgandhi	18:6a4db94011d3	3145	*/
sahilmgandhi	18:6a4db94011d3	3146
sahilmgandhi	18:6a4db94011d3	3147	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3148	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3149	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	3150	* power consumption.
sahilmgandhi	18:6a4db94011d3	3151	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	3152	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	3153	* @{
sahilmgandhi	18:6a4db94011d3	3154	*/
sahilmgandhi	18:6a4db94011d3	3155	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	3156	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	3157	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	3158	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	3159	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	3160
sahilmgandhi	18:6a4db94011d3	3161	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	3162	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	3163	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	3164	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	3165	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	3166	/**
sahilmgandhi	18:6a4db94011d3	3167	* @}
sahilmgandhi	18:6a4db94011d3	3168	*/
sahilmgandhi	18:6a4db94011d3	3169
sahilmgandhi	18:6a4db94011d3	3170	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3171	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3172	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	3173	* power consumption.
sahilmgandhi	18:6a4db94011d3	3174	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	3175	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	3176	* @{
sahilmgandhi	18:6a4db94011d3	3177	*/
sahilmgandhi	18:6a4db94011d3	3178	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	3179	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	3180	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	3181
sahilmgandhi	18:6a4db94011d3	3182	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	3183	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	3184	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	3185	/**
sahilmgandhi	18:6a4db94011d3	3186	* @}
sahilmgandhi	18:6a4db94011d3	3187	*/
sahilmgandhi	18:6a4db94011d3	3188	#endif /* STM32F401xC \|\| STM32F401xE*/
sahilmgandhi	18:6a4db94011d3	3189	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	3190
sahilmgandhi	18:6a4db94011d3	3191	/-------------------------------- STM32F410xx -------------------------------/
sahilmgandhi	18:6a4db94011d3	3192	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	3193	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3194	* @brief Enables or disables the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3195	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3196	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3197	* using it.
sahilmgandhi	18:6a4db94011d3	3198	* @{
sahilmgandhi	18:6a4db94011d3	3199	*/
sahilmgandhi	18:6a4db94011d3	3200	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3201	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3202	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	3203	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3204	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	3205	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3206	} while(0)
sahilmgandhi	18:6a4db94011d3	3207	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3208	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3209	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	3210	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3211	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	3212	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3213	} while(0)
sahilmgandhi	18:6a4db94011d3	3214	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
sahilmgandhi	18:6a4db94011d3	3215	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
sahilmgandhi	18:6a4db94011d3	3216	/**
sahilmgandhi	18:6a4db94011d3	3217	* @}
sahilmgandhi	18:6a4db94011d3	3218	*/
sahilmgandhi	18:6a4db94011d3	3219
sahilmgandhi	18:6a4db94011d3	3220	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3221	* @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3222	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3223	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3224	* using it.
sahilmgandhi	18:6a4db94011d3	3225	* @{
sahilmgandhi	18:6a4db94011d3	3226	*/
sahilmgandhi	18:6a4db94011d3	3227	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3228	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3229	/**
sahilmgandhi	18:6a4db94011d3	3230	* @}
sahilmgandhi	18:6a4db94011d3	3231	*/
sahilmgandhi	18:6a4db94011d3	3232
sahilmgandhi	18:6a4db94011d3	3233	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3234	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
sahilmgandhi	18:6a4db94011d3	3235	* @{
sahilmgandhi	18:6a4db94011d3	3236	*/
sahilmgandhi	18:6a4db94011d3	3237	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3238	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3239	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	3240	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3241	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	3242	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3243	} while(0)
sahilmgandhi	18:6a4db94011d3	3244	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3245	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3246	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
sahilmgandhi	18:6a4db94011d3	3247	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3248	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
sahilmgandhi	18:6a4db94011d3	3249	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3250	} while(0)
sahilmgandhi	18:6a4db94011d3	3251	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3252	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3253	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
sahilmgandhi	18:6a4db94011d3	3254	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3255	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
sahilmgandhi	18:6a4db94011d3	3256	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3257	} while(0)
sahilmgandhi	18:6a4db94011d3	3258	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3259	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3260	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
sahilmgandhi	18:6a4db94011d3	3261	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3262	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
sahilmgandhi	18:6a4db94011d3	3263	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3264	} while(0)
sahilmgandhi	18:6a4db94011d3	3265	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3266	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3267	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
sahilmgandhi	18:6a4db94011d3	3268	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3269	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
sahilmgandhi	18:6a4db94011d3	3270	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3271	} while(0)
sahilmgandhi	18:6a4db94011d3	3272
sahilmgandhi	18:6a4db94011d3	3273	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
sahilmgandhi	18:6a4db94011d3	3274	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
sahilmgandhi	18:6a4db94011d3	3275	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
sahilmgandhi	18:6a4db94011d3	3276	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
sahilmgandhi	18:6a4db94011d3	3277	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
sahilmgandhi	18:6a4db94011d3	3278	/**
sahilmgandhi	18:6a4db94011d3	3279	* @}
sahilmgandhi	18:6a4db94011d3	3280	*/
sahilmgandhi	18:6a4db94011d3	3281
sahilmgandhi	18:6a4db94011d3	3282	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3283	* @brief Get the enable or disable status of the APB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3284	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3285	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3286	* using it.
sahilmgandhi	18:6a4db94011d3	3287	* @{
sahilmgandhi	18:6a4db94011d3	3288	*/
sahilmgandhi	18:6a4db94011d3	3289	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3290	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3291	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3292	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3293	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3294
sahilmgandhi	18:6a4db94011d3	3295	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3296	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3297	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3298	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3299	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3300	/**
sahilmgandhi	18:6a4db94011d3	3301	* @}
sahilmgandhi	18:6a4db94011d3	3302	*/
sahilmgandhi	18:6a4db94011d3	3303
sahilmgandhi	18:6a4db94011d3	3304	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3305	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
sahilmgandhi	18:6a4db94011d3	3306	* @{
sahilmgandhi	18:6a4db94011d3	3307	*/
sahilmgandhi	18:6a4db94011d3	3308	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3309	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3310	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
sahilmgandhi	18:6a4db94011d3	3311	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3312	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
sahilmgandhi	18:6a4db94011d3	3313	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3314	} while(0)
sahilmgandhi	18:6a4db94011d3	3315	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3316	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3317	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
sahilmgandhi	18:6a4db94011d3	3318	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3319	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
sahilmgandhi	18:6a4db94011d3	3320	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3321	} while(0)
sahilmgandhi	18:6a4db94011d3	3322	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
sahilmgandhi	18:6a4db94011d3	3323	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
sahilmgandhi	18:6a4db94011d3	3324	/**
sahilmgandhi	18:6a4db94011d3	3325	* @}
sahilmgandhi	18:6a4db94011d3	3326	*/
sahilmgandhi	18:6a4db94011d3	3327
sahilmgandhi	18:6a4db94011d3	3328	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3329	* @brief Get the enable or disable status of the APB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3330	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3331	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3332	* using it.
sahilmgandhi	18:6a4db94011d3	3333	* @{
sahilmgandhi	18:6a4db94011d3	3334	*/
sahilmgandhi	18:6a4db94011d3	3335	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3336	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3337
sahilmgandhi	18:6a4db94011d3	3338	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3339	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3340	/**
sahilmgandhi	18:6a4db94011d3	3341	* @}
sahilmgandhi	18:6a4db94011d3	3342	*/
sahilmgandhi	18:6a4db94011d3	3343
sahilmgandhi	18:6a4db94011d3	3344	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3345	* @brief Force or release AHB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3346	* @{
sahilmgandhi	18:6a4db94011d3	3347	*/
sahilmgandhi	18:6a4db94011d3	3348	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	3349	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	3350	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	3351	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	3352	/**
sahilmgandhi	18:6a4db94011d3	3353	* @}
sahilmgandhi	18:6a4db94011d3	3354	*/
sahilmgandhi	18:6a4db94011d3	3355
sahilmgandhi	18:6a4db94011d3	3356	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3357	* @brief Force or release AHB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3358	* @{
sahilmgandhi	18:6a4db94011d3	3359	*/
sahilmgandhi	18:6a4db94011d3	3360	#define __HAL_RCC_AHB2_FORCE_RESET()
sahilmgandhi	18:6a4db94011d3	3361	#define __HAL_RCC_AHB2_RELEASE_RESET()
sahilmgandhi	18:6a4db94011d3	3362	/**
sahilmgandhi	18:6a4db94011d3	3363	* @}
sahilmgandhi	18:6a4db94011d3	3364	*/
sahilmgandhi	18:6a4db94011d3	3365
sahilmgandhi	18:6a4db94011d3	3366	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3367	* @brief Force or release AHB3 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3368	* @{
sahilmgandhi	18:6a4db94011d3	3369	*/
sahilmgandhi	18:6a4db94011d3	3370	#define __HAL_RCC_AHB3_FORCE_RESET()
sahilmgandhi	18:6a4db94011d3	3371	#define __HAL_RCC_AHB3_RELEASE_RESET()
sahilmgandhi	18:6a4db94011d3	3372	/**
sahilmgandhi	18:6a4db94011d3	3373	* @}
sahilmgandhi	18:6a4db94011d3	3374	*/
sahilmgandhi	18:6a4db94011d3	3375
sahilmgandhi	18:6a4db94011d3	3376	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3377	* @brief Force or release APB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3378	* @{
sahilmgandhi	18:6a4db94011d3	3379	*/
sahilmgandhi	18:6a4db94011d3	3380	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	3381	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
sahilmgandhi	18:6a4db94011d3	3382	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
sahilmgandhi	18:6a4db94011d3	3383	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
sahilmgandhi	18:6a4db94011d3	3384
sahilmgandhi	18:6a4db94011d3	3385	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	3386	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
sahilmgandhi	18:6a4db94011d3	3387	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
sahilmgandhi	18:6a4db94011d3	3388	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
sahilmgandhi	18:6a4db94011d3	3389	/**
sahilmgandhi	18:6a4db94011d3	3390	* @}
sahilmgandhi	18:6a4db94011d3	3391	*/
sahilmgandhi	18:6a4db94011d3	3392
sahilmgandhi	18:6a4db94011d3	3393	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3394	* @brief Force or release APB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3395	* @{
sahilmgandhi	18:6a4db94011d3	3396	*/
sahilmgandhi	18:6a4db94011d3	3397	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
sahilmgandhi	18:6a4db94011d3	3398	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
sahilmgandhi	18:6a4db94011d3	3399	/**
sahilmgandhi	18:6a4db94011d3	3400	* @}
sahilmgandhi	18:6a4db94011d3	3401	*/
sahilmgandhi	18:6a4db94011d3	3402
sahilmgandhi	18:6a4db94011d3	3403	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3404	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3405	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	3406	* power consumption.
sahilmgandhi	18:6a4db94011d3	3407	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	3408	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	3409	* @{
sahilmgandhi	18:6a4db94011d3	3410	*/
sahilmgandhi	18:6a4db94011d3	3411	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	3412	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	3413	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	3414	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	3415
sahilmgandhi	18:6a4db94011d3	3416	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	3417	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	3418	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	3419	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	3420	/**
sahilmgandhi	18:6a4db94011d3	3421	* @}
sahilmgandhi	18:6a4db94011d3	3422	*/
sahilmgandhi	18:6a4db94011d3	3423
sahilmgandhi	18:6a4db94011d3	3424	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3425	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3426	* @{
sahilmgandhi	18:6a4db94011d3	3427	*/
sahilmgandhi	18:6a4db94011d3	3428	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	3429	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
sahilmgandhi	18:6a4db94011d3	3430	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
sahilmgandhi	18:6a4db94011d3	3431	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
sahilmgandhi	18:6a4db94011d3	3432	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
sahilmgandhi	18:6a4db94011d3	3433
sahilmgandhi	18:6a4db94011d3	3434	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	3435	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
sahilmgandhi	18:6a4db94011d3	3436	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
sahilmgandhi	18:6a4db94011d3	3437	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
sahilmgandhi	18:6a4db94011d3	3438	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
sahilmgandhi	18:6a4db94011d3	3439	/**
sahilmgandhi	18:6a4db94011d3	3440	* @}
sahilmgandhi	18:6a4db94011d3	3441	*/
sahilmgandhi	18:6a4db94011d3	3442
sahilmgandhi	18:6a4db94011d3	3443	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3444	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3445	* @{
sahilmgandhi	18:6a4db94011d3	3446	*/
sahilmgandhi	18:6a4db94011d3	3447	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
sahilmgandhi	18:6a4db94011d3	3448	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
sahilmgandhi	18:6a4db94011d3	3449	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
sahilmgandhi	18:6a4db94011d3	3450	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
sahilmgandhi	18:6a4db94011d3	3451	/**
sahilmgandhi	18:6a4db94011d3	3452	* @}
sahilmgandhi	18:6a4db94011d3	3453	*/
sahilmgandhi	18:6a4db94011d3	3454
sahilmgandhi	18:6a4db94011d3	3455	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	3456	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	3457
sahilmgandhi	18:6a4db94011d3	3458	/-------------------------------- STM32F411xx -------------------------------/
sahilmgandhi	18:6a4db94011d3	3459	#if defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	3460	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3461	* @brief Enables or disables the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3462	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3463	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3464	* using it.
sahilmgandhi	18:6a4db94011d3	3465	* @{
sahilmgandhi	18:6a4db94011d3	3466	*/
sahilmgandhi	18:6a4db94011d3	3467	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3468	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3469	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	3470	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3471	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	3472	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3473	} while(0)
sahilmgandhi	18:6a4db94011d3	3474	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3475	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3476	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	3477	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3478	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	3479	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3480	} while(0)
sahilmgandhi	18:6a4db94011d3	3481	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3482	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3483	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	3484	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3485	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	3486	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3487	} while(0)
sahilmgandhi	18:6a4db94011d3	3488	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3489	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3490	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	3491	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3492	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	3493	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3494	} while(0)
sahilmgandhi	18:6a4db94011d3	3495	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3496	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3497	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	3498	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3499	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	3500	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3501	} while(0)
sahilmgandhi	18:6a4db94011d3	3502	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
sahilmgandhi	18:6a4db94011d3	3503	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
sahilmgandhi	18:6a4db94011d3	3504	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
sahilmgandhi	18:6a4db94011d3	3505	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
sahilmgandhi	18:6a4db94011d3	3506	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
sahilmgandhi	18:6a4db94011d3	3507	/**
sahilmgandhi	18:6a4db94011d3	3508	* @}
sahilmgandhi	18:6a4db94011d3	3509	*/
sahilmgandhi	18:6a4db94011d3	3510
sahilmgandhi	18:6a4db94011d3	3511	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3512	* @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3513	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3514	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3515	* using it.
sahilmgandhi	18:6a4db94011d3	3516	* @{
sahilmgandhi	18:6a4db94011d3	3517	*/
sahilmgandhi	18:6a4db94011d3	3518	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3519	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3520	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3521	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3522	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3523
sahilmgandhi	18:6a4db94011d3	3524	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3525	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3526	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3527	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3528	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3529	/**
sahilmgandhi	18:6a4db94011d3	3530	* @}
sahilmgandhi	18:6a4db94011d3	3531	*/
sahilmgandhi	18:6a4db94011d3	3532
sahilmgandhi	18:6a4db94011d3	3533	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3534	* @brief Enable or disable the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3535	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3536	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3537	* using it.
sahilmgandhi	18:6a4db94011d3	3538	* @{
sahilmgandhi	18:6a4db94011d3	3539	*/
sahilmgandhi	18:6a4db94011d3	3540	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
sahilmgandhi	18:6a4db94011d3	3541	__HAL_RCC_SYSCFG_CLK_ENABLE();\
sahilmgandhi	18:6a4db94011d3	3542	}while(0)
sahilmgandhi	18:6a4db94011d3	3543
sahilmgandhi	18:6a4db94011d3	3544	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
sahilmgandhi	18:6a4db94011d3	3545	/**
sahilmgandhi	18:6a4db94011d3	3546	* @}
sahilmgandhi	18:6a4db94011d3	3547	*/
sahilmgandhi	18:6a4db94011d3	3548
sahilmgandhi	18:6a4db94011d3	3549	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3550	* @brief Get the enable or disable status of the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3551	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3552	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3553	* using it.
sahilmgandhi	18:6a4db94011d3	3554	* @{
sahilmgandhi	18:6a4db94011d3	3555	*/
sahilmgandhi	18:6a4db94011d3	3556	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3557	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3558	/**
sahilmgandhi	18:6a4db94011d3	3559	* @}
sahilmgandhi	18:6a4db94011d3	3560	*/
sahilmgandhi	18:6a4db94011d3	3561
sahilmgandhi	18:6a4db94011d3	3562	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3563	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
sahilmgandhi	18:6a4db94011d3	3564	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3565	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3566	* using it.
sahilmgandhi	18:6a4db94011d3	3567	* @{
sahilmgandhi	18:6a4db94011d3	3568	*/
sahilmgandhi	18:6a4db94011d3	3569	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3570	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3571	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	3572	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3573	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	3574	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3575	} while(0)
sahilmgandhi	18:6a4db94011d3	3576	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3577	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3578	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	3579	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3580	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	3581	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3582	} while(0)
sahilmgandhi	18:6a4db94011d3	3583	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3584	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3585	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	3586	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3587	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	3588	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3589	} while(0)
sahilmgandhi	18:6a4db94011d3	3590	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3591	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3592	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	3593	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3594	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	3595	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3596	} while(0)
sahilmgandhi	18:6a4db94011d3	3597	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3598	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3599	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	3600	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3601	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	3602	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3603	} while(0)
sahilmgandhi	18:6a4db94011d3	3604	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
sahilmgandhi	18:6a4db94011d3	3605	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
sahilmgandhi	18:6a4db94011d3	3606	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
sahilmgandhi	18:6a4db94011d3	3607	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
sahilmgandhi	18:6a4db94011d3	3608	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
sahilmgandhi	18:6a4db94011d3	3609	/**
sahilmgandhi	18:6a4db94011d3	3610	* @}
sahilmgandhi	18:6a4db94011d3	3611	*/
sahilmgandhi	18:6a4db94011d3	3612
sahilmgandhi	18:6a4db94011d3	3613	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3614	* @brief Get the enable or disable status of the APB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3615	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3616	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3617	* using it.
sahilmgandhi	18:6a4db94011d3	3618	* @{
sahilmgandhi	18:6a4db94011d3	3619	*/
sahilmgandhi	18:6a4db94011d3	3620	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3621	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3622	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3623	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3624	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3625
sahilmgandhi	18:6a4db94011d3	3626	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3627	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3628	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3629	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3630	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3631	/**
sahilmgandhi	18:6a4db94011d3	3632	* @}
sahilmgandhi	18:6a4db94011d3	3633	*/
sahilmgandhi	18:6a4db94011d3	3634
sahilmgandhi	18:6a4db94011d3	3635	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3636	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
sahilmgandhi	18:6a4db94011d3	3637	* @{
sahilmgandhi	18:6a4db94011d3	3638	*/
sahilmgandhi	18:6a4db94011d3	3639	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3640	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3641	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
sahilmgandhi	18:6a4db94011d3	3642	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3643	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
sahilmgandhi	18:6a4db94011d3	3644	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3645	} while(0)
sahilmgandhi	18:6a4db94011d3	3646	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3647	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3648	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	3649	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3650	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	3651	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3652	} while(0)
sahilmgandhi	18:6a4db94011d3	3653	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3654	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3655	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	3656	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3657	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	3658	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3659	} while(0)
sahilmgandhi	18:6a4db94011d3	3660	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3661	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3662	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	3663	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3664	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	3665	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3666	} while(0)
sahilmgandhi	18:6a4db94011d3	3667	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
sahilmgandhi	18:6a4db94011d3	3668	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
sahilmgandhi	18:6a4db94011d3	3669	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
sahilmgandhi	18:6a4db94011d3	3670	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
sahilmgandhi	18:6a4db94011d3	3671	/**
sahilmgandhi	18:6a4db94011d3	3672	* @}
sahilmgandhi	18:6a4db94011d3	3673	*/
sahilmgandhi	18:6a4db94011d3	3674
sahilmgandhi	18:6a4db94011d3	3675	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3676	* @brief Get the enable or disable status of the APB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3677	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3678	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3679	* using it.
sahilmgandhi	18:6a4db94011d3	3680	* @{
sahilmgandhi	18:6a4db94011d3	3681	*/
sahilmgandhi	18:6a4db94011d3	3682	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3683	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3684	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3685	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3686
sahilmgandhi	18:6a4db94011d3	3687	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3688	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3689	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3690	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3691	/**
sahilmgandhi	18:6a4db94011d3	3692	* @}
sahilmgandhi	18:6a4db94011d3	3693	*/
sahilmgandhi	18:6a4db94011d3	3694
sahilmgandhi	18:6a4db94011d3	3695	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3696	* @brief Force or release AHB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3697	* @{
sahilmgandhi	18:6a4db94011d3	3698	*/
sahilmgandhi	18:6a4db94011d3	3699	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	3700	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	3701	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	3702
sahilmgandhi	18:6a4db94011d3	3703	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	3704	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	3705	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	3706	/**
sahilmgandhi	18:6a4db94011d3	3707	* @}
sahilmgandhi	18:6a4db94011d3	3708	*/
sahilmgandhi	18:6a4db94011d3	3709
sahilmgandhi	18:6a4db94011d3	3710	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3711	* @brief Force or release AHB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3712	* @{
sahilmgandhi	18:6a4db94011d3	3713	*/
sahilmgandhi	18:6a4db94011d3	3714	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	3715	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	3716
sahilmgandhi	18:6a4db94011d3	3717	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	3718	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	3719	/**
sahilmgandhi	18:6a4db94011d3	3720	* @}
sahilmgandhi	18:6a4db94011d3	3721	*/
sahilmgandhi	18:6a4db94011d3	3722
sahilmgandhi	18:6a4db94011d3	3723	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3724	* @brief Force or release AHB3 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3725	* @{
sahilmgandhi	18:6a4db94011d3	3726	*/
sahilmgandhi	18:6a4db94011d3	3727	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	3728	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	3729	/**
sahilmgandhi	18:6a4db94011d3	3730	* @}
sahilmgandhi	18:6a4db94011d3	3731	*/
sahilmgandhi	18:6a4db94011d3	3732
sahilmgandhi	18:6a4db94011d3	3733	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3734	* @brief Force or release APB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3735	* @{
sahilmgandhi	18:6a4db94011d3	3736	*/
sahilmgandhi	18:6a4db94011d3	3737	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	3738	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	3739	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	3740	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	3741	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	3742
sahilmgandhi	18:6a4db94011d3	3743	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	3744	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	3745	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	3746	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	3747	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	3748	/**
sahilmgandhi	18:6a4db94011d3	3749	* @}
sahilmgandhi	18:6a4db94011d3	3750	*/
sahilmgandhi	18:6a4db94011d3	3751
sahilmgandhi	18:6a4db94011d3	3752	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	3753	* @brief Force or release APB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	3754	* @{
sahilmgandhi	18:6a4db94011d3	3755	*/
sahilmgandhi	18:6a4db94011d3	3756	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
sahilmgandhi	18:6a4db94011d3	3757	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	3758	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	3759	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	3760
sahilmgandhi	18:6a4db94011d3	3761	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	3762	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	3763	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	3764	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
sahilmgandhi	18:6a4db94011d3	3765	/**
sahilmgandhi	18:6a4db94011d3	3766	* @}
sahilmgandhi	18:6a4db94011d3	3767	*/
sahilmgandhi	18:6a4db94011d3	3768
sahilmgandhi	18:6a4db94011d3	3769	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3770	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3771	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	3772	* power consumption.
sahilmgandhi	18:6a4db94011d3	3773	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	3774	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	3775	* @{
sahilmgandhi	18:6a4db94011d3	3776	*/
sahilmgandhi	18:6a4db94011d3	3777	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	3778	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	3779	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	3780	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	3781	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	3782
sahilmgandhi	18:6a4db94011d3	3783	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	3784	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	3785	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	3786	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	3787	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	3788	/**
sahilmgandhi	18:6a4db94011d3	3789	* @}
sahilmgandhi	18:6a4db94011d3	3790	*/
sahilmgandhi	18:6a4db94011d3	3791
sahilmgandhi	18:6a4db94011d3	3792	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3793	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3794	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	3795	* power consumption.
sahilmgandhi	18:6a4db94011d3	3796	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	3797	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	3798	* @{
sahilmgandhi	18:6a4db94011d3	3799	*/
sahilmgandhi	18:6a4db94011d3	3800	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	3801	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	3802	/**
sahilmgandhi	18:6a4db94011d3	3803	* @}
sahilmgandhi	18:6a4db94011d3	3804	*/
sahilmgandhi	18:6a4db94011d3	3805
sahilmgandhi	18:6a4db94011d3	3806	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3807	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3808	* @{
sahilmgandhi	18:6a4db94011d3	3809	*/
sahilmgandhi	18:6a4db94011d3	3810	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	3811	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	3812	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	3813	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	3814	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	3815
sahilmgandhi	18:6a4db94011d3	3816	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	3817	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	3818	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	3819	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	3820	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	3821	/**
sahilmgandhi	18:6a4db94011d3	3822	* @}
sahilmgandhi	18:6a4db94011d3	3823	*/
sahilmgandhi	18:6a4db94011d3	3824
sahilmgandhi	18:6a4db94011d3	3825	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	3826	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	3827	* @{
sahilmgandhi	18:6a4db94011d3	3828	*/
sahilmgandhi	18:6a4db94011d3	3829	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
sahilmgandhi	18:6a4db94011d3	3830	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	3831	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	3832	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	3833
sahilmgandhi	18:6a4db94011d3	3834	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	3835	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	3836	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	3837	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
sahilmgandhi	18:6a4db94011d3	3838	/**
sahilmgandhi	18:6a4db94011d3	3839	* @}
sahilmgandhi	18:6a4db94011d3	3840	*/
sahilmgandhi	18:6a4db94011d3	3841	#endif /* STM32F411xE */
sahilmgandhi	18:6a4db94011d3	3842	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	3843
sahilmgandhi	18:6a4db94011d3	3844	/---------------------------------- STM32F446xx -----------------------------/
sahilmgandhi	18:6a4db94011d3	3845	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	3846	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3847	* @brief Enables or disables the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3848	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3849	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3850	* using it.
sahilmgandhi	18:6a4db94011d3	3851	* @{
sahilmgandhi	18:6a4db94011d3	3852	*/
sahilmgandhi	18:6a4db94011d3	3853	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3854	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3855	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	3856	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3857	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
sahilmgandhi	18:6a4db94011d3	3858	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3859	} while(0)
sahilmgandhi	18:6a4db94011d3	3860	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3861	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3862	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	3863	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3864	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
sahilmgandhi	18:6a4db94011d3	3865	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3866	} while(0)
sahilmgandhi	18:6a4db94011d3	3867	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3868	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3869	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	3870	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3871	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	3872	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3873	} while(0)
sahilmgandhi	18:6a4db94011d3	3874	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3875	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3876	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	3877	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3878	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	3879	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3880	} while(0)
sahilmgandhi	18:6a4db94011d3	3881	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3882	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3883	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	3884	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3885	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	3886	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3887	} while(0)
sahilmgandhi	18:6a4db94011d3	3888	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3889	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3890	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
sahilmgandhi	18:6a4db94011d3	3891	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3892	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
sahilmgandhi	18:6a4db94011d3	3893	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3894	} while(0)
sahilmgandhi	18:6a4db94011d3	3895	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3896	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3897	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
sahilmgandhi	18:6a4db94011d3	3898	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3899	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
sahilmgandhi	18:6a4db94011d3	3900	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3901	} while(0)
sahilmgandhi	18:6a4db94011d3	3902	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3903	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3904	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
sahilmgandhi	18:6a4db94011d3	3905	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3906	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
sahilmgandhi	18:6a4db94011d3	3907	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3908	} while(0)
sahilmgandhi	18:6a4db94011d3	3909	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3910	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3911	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
sahilmgandhi	18:6a4db94011d3	3912	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3913	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
sahilmgandhi	18:6a4db94011d3	3914	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3915	} while(0)
sahilmgandhi	18:6a4db94011d3	3916	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
sahilmgandhi	18:6a4db94011d3	3917	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
sahilmgandhi	18:6a4db94011d3	3918	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
sahilmgandhi	18:6a4db94011d3	3919	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
sahilmgandhi	18:6a4db94011d3	3920	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
sahilmgandhi	18:6a4db94011d3	3921	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
sahilmgandhi	18:6a4db94011d3	3922	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
sahilmgandhi	18:6a4db94011d3	3923	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
sahilmgandhi	18:6a4db94011d3	3924	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
sahilmgandhi	18:6a4db94011d3	3925	/**
sahilmgandhi	18:6a4db94011d3	3926	* @}
sahilmgandhi	18:6a4db94011d3	3927	*/
sahilmgandhi	18:6a4db94011d3	3928
sahilmgandhi	18:6a4db94011d3	3929	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3930	* @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3931	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3932	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3933	* using it.
sahilmgandhi	18:6a4db94011d3	3934	* @{
sahilmgandhi	18:6a4db94011d3	3935	*/
sahilmgandhi	18:6a4db94011d3	3936	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3937	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3938	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3939	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3940	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3941	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3942	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3943	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)
sahilmgandhi	18:6a4db94011d3	3944	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	3945
sahilmgandhi	18:6a4db94011d3	3946	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3947	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3948	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3949	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3950	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3951	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3952	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3953	#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3954	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	3955	/**
sahilmgandhi	18:6a4db94011d3	3956	* @}
sahilmgandhi	18:6a4db94011d3	3957	*/
sahilmgandhi	18:6a4db94011d3	3958
sahilmgandhi	18:6a4db94011d3	3959	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	3960	* @brief Enable or disable the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3961	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3962	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3963	* using it.
sahilmgandhi	18:6a4db94011d3	3964	* @{
sahilmgandhi	18:6a4db94011d3	3965	*/
sahilmgandhi	18:6a4db94011d3	3966	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3967	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3968	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
sahilmgandhi	18:6a4db94011d3	3969	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3970	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
sahilmgandhi	18:6a4db94011d3	3971	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3972	} while(0)
sahilmgandhi	18:6a4db94011d3	3973	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
sahilmgandhi	18:6a4db94011d3	3974	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
sahilmgandhi	18:6a4db94011d3	3975	__HAL_RCC_SYSCFG_CLK_ENABLE();\
sahilmgandhi	18:6a4db94011d3	3976	}while(0)
sahilmgandhi	18:6a4db94011d3	3977
sahilmgandhi	18:6a4db94011d3	3978	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
sahilmgandhi	18:6a4db94011d3	3979
sahilmgandhi	18:6a4db94011d3	3980	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	3981	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	3982	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	3983	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	3984	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	3985	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	3986	} while(0)
sahilmgandhi	18:6a4db94011d3	3987	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
sahilmgandhi	18:6a4db94011d3	3988	/**
sahilmgandhi	18:6a4db94011d3	3989	* @}
sahilmgandhi	18:6a4db94011d3	3990	*/
sahilmgandhi	18:6a4db94011d3	3991
sahilmgandhi	18:6a4db94011d3	3992	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	3993	* @brief Get the enable or disable status of the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	3994	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	3995	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	3996	* using it.
sahilmgandhi	18:6a4db94011d3	3997	* @{
sahilmgandhi	18:6a4db94011d3	3998	*/
sahilmgandhi	18:6a4db94011d3	3999	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4000	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4001
sahilmgandhi	18:6a4db94011d3	4002	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4003	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4004
sahilmgandhi	18:6a4db94011d3	4005	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4006	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4007	/**
sahilmgandhi	18:6a4db94011d3	4008	* @}
sahilmgandhi	18:6a4db94011d3	4009	*/
sahilmgandhi	18:6a4db94011d3	4010
sahilmgandhi	18:6a4db94011d3	4011	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	4012	* @brief Enables or disables the AHB3 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4013	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4014	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4015	* using it.
sahilmgandhi	18:6a4db94011d3	4016	* @{
sahilmgandhi	18:6a4db94011d3	4017	*/
sahilmgandhi	18:6a4db94011d3	4018	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4019	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4020	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
sahilmgandhi	18:6a4db94011d3	4021	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4022	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
sahilmgandhi	18:6a4db94011d3	4023	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4024	} while(0)
sahilmgandhi	18:6a4db94011d3	4025	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4026	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4027	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
sahilmgandhi	18:6a4db94011d3	4028	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4029	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
sahilmgandhi	18:6a4db94011d3	4030	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4031	} while(0)
sahilmgandhi	18:6a4db94011d3	4032
sahilmgandhi	18:6a4db94011d3	4033	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
sahilmgandhi	18:6a4db94011d3	4034	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
sahilmgandhi	18:6a4db94011d3	4035	/**
sahilmgandhi	18:6a4db94011d3	4036	* @}
sahilmgandhi	18:6a4db94011d3	4037	*/
sahilmgandhi	18:6a4db94011d3	4038
sahilmgandhi	18:6a4db94011d3	4039	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	4040	* @brief Get the enable or disable status of the AHB3 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4041	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4042	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4043	* using it.
sahilmgandhi	18:6a4db94011d3	4044	* @{
sahilmgandhi	18:6a4db94011d3	4045	*/
sahilmgandhi	18:6a4db94011d3	4046	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4047	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4048
sahilmgandhi	18:6a4db94011d3	4049	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4050	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4051	/**
sahilmgandhi	18:6a4db94011d3	4052	* @}
sahilmgandhi	18:6a4db94011d3	4053	*/
sahilmgandhi	18:6a4db94011d3	4054
sahilmgandhi	18:6a4db94011d3	4055	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	4056	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
sahilmgandhi	18:6a4db94011d3	4057	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4058	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4059	* using it.
sahilmgandhi	18:6a4db94011d3	4060	* @{
sahilmgandhi	18:6a4db94011d3	4061	*/
sahilmgandhi	18:6a4db94011d3	4062	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4063	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4064	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	4065	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4066	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	4067	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4068	} while(0)
sahilmgandhi	18:6a4db94011d3	4069	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4070	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4071	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
sahilmgandhi	18:6a4db94011d3	4072	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4073	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
sahilmgandhi	18:6a4db94011d3	4074	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4075	} while(0)
sahilmgandhi	18:6a4db94011d3	4076	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4077	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4078	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
sahilmgandhi	18:6a4db94011d3	4079	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4080	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
sahilmgandhi	18:6a4db94011d3	4081	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4082	} while(0)
sahilmgandhi	18:6a4db94011d3	4083	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4084	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4085	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
sahilmgandhi	18:6a4db94011d3	4086	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4087	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
sahilmgandhi	18:6a4db94011d3	4088	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4089	} while(0)
sahilmgandhi	18:6a4db94011d3	4090	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4091	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4092	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	4093	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4094	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	4095	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4096	} while(0)
sahilmgandhi	18:6a4db94011d3	4097	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4098	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4099	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
sahilmgandhi	18:6a4db94011d3	4100	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4101	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
sahilmgandhi	18:6a4db94011d3	4102	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4103	} while(0)
sahilmgandhi	18:6a4db94011d3	4104	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4105	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4106	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
sahilmgandhi	18:6a4db94011d3	4107	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4108	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
sahilmgandhi	18:6a4db94011d3	4109	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4110	} while(0)
sahilmgandhi	18:6a4db94011d3	4111	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4112	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4113	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
sahilmgandhi	18:6a4db94011d3	4114	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4115	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
sahilmgandhi	18:6a4db94011d3	4116	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4117	} while(0)
sahilmgandhi	18:6a4db94011d3	4118	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4119	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4120	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
sahilmgandhi	18:6a4db94011d3	4121	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4122	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
sahilmgandhi	18:6a4db94011d3	4123	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4124	} while(0)
sahilmgandhi	18:6a4db94011d3	4125	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4126	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4127	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
sahilmgandhi	18:6a4db94011d3	4128	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4129	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
sahilmgandhi	18:6a4db94011d3	4130	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4131	} while(0)
sahilmgandhi	18:6a4db94011d3	4132	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4133	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4134	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
sahilmgandhi	18:6a4db94011d3	4135	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4136	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
sahilmgandhi	18:6a4db94011d3	4137	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4138	} while(0)
sahilmgandhi	18:6a4db94011d3	4139	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4140	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4141	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
sahilmgandhi	18:6a4db94011d3	4142	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4143	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
sahilmgandhi	18:6a4db94011d3	4144	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4145	} while(0)
sahilmgandhi	18:6a4db94011d3	4146	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4147	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4148	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
sahilmgandhi	18:6a4db94011d3	4149	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4150	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
sahilmgandhi	18:6a4db94011d3	4151	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4152	} while(0)
sahilmgandhi	18:6a4db94011d3	4153	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4154	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4155	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
sahilmgandhi	18:6a4db94011d3	4156	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4157	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
sahilmgandhi	18:6a4db94011d3	4158	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4159	} while(0)
sahilmgandhi	18:6a4db94011d3	4160	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4161	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4162	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	4163	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4164	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	4165	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4166	} while(0)
sahilmgandhi	18:6a4db94011d3	4167	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4168	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4169	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	4170	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4171	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	4172	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4173	} while(0)
sahilmgandhi	18:6a4db94011d3	4174	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4175	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4176	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	4177	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4178	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	4179	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4180	} while(0)
sahilmgandhi	18:6a4db94011d3	4181	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4182	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4183	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	4184	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4185	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	4186	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4187	} while(0)
sahilmgandhi	18:6a4db94011d3	4188	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4189	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4190	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	4191	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4192	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	4193	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4194	} while(0)
sahilmgandhi	18:6a4db94011d3	4195	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
sahilmgandhi	18:6a4db94011d3	4196	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
sahilmgandhi	18:6a4db94011d3	4197	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
sahilmgandhi	18:6a4db94011d3	4198	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
sahilmgandhi	18:6a4db94011d3	4199	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
sahilmgandhi	18:6a4db94011d3	4200	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
sahilmgandhi	18:6a4db94011d3	4201	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
sahilmgandhi	18:6a4db94011d3	4202	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
sahilmgandhi	18:6a4db94011d3	4203	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
sahilmgandhi	18:6a4db94011d3	4204	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
sahilmgandhi	18:6a4db94011d3	4205	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
sahilmgandhi	18:6a4db94011d3	4206	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
sahilmgandhi	18:6a4db94011d3	4207	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
sahilmgandhi	18:6a4db94011d3	4208	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
sahilmgandhi	18:6a4db94011d3	4209	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
sahilmgandhi	18:6a4db94011d3	4210	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
sahilmgandhi	18:6a4db94011d3	4211	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
sahilmgandhi	18:6a4db94011d3	4212	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
sahilmgandhi	18:6a4db94011d3	4213	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
sahilmgandhi	18:6a4db94011d3	4214	/**
sahilmgandhi	18:6a4db94011d3	4215	* @}
sahilmgandhi	18:6a4db94011d3	4216	*/
sahilmgandhi	18:6a4db94011d3	4217
sahilmgandhi	18:6a4db94011d3	4218	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	4219	* @brief Get the enable or disable status of the APB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4220	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4221	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4222	* using it.
sahilmgandhi	18:6a4db94011d3	4223	* @{
sahilmgandhi	18:6a4db94011d3	4224	*/
sahilmgandhi	18:6a4db94011d3	4225	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4226	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4227	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4228	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4229	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4230	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4231	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4232	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4233	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4234	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4235	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4236	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4237	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4238	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4239	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4240	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4241	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4242	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4243	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4244
sahilmgandhi	18:6a4db94011d3	4245	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4246	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4247	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4248	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4249	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4250	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4251	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4252	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4253	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4254	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4255	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4256	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4257	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4258	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4259	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4260	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4261	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4262	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4263	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4264	/**
sahilmgandhi	18:6a4db94011d3	4265	* @}
sahilmgandhi	18:6a4db94011d3	4266	*/
sahilmgandhi	18:6a4db94011d3	4267
sahilmgandhi	18:6a4db94011d3	4268	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	4269	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
sahilmgandhi	18:6a4db94011d3	4270	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4271	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4272	* using it.
sahilmgandhi	18:6a4db94011d3	4273	* @{
sahilmgandhi	18:6a4db94011d3	4274	*/
sahilmgandhi	18:6a4db94011d3	4275	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4276	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4277	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
sahilmgandhi	18:6a4db94011d3	4278	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4279	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
sahilmgandhi	18:6a4db94011d3	4280	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4281	} while(0)
sahilmgandhi	18:6a4db94011d3	4282	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4283	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4284	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
sahilmgandhi	18:6a4db94011d3	4285	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4286	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
sahilmgandhi	18:6a4db94011d3	4287	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4288	} while(0)
sahilmgandhi	18:6a4db94011d3	4289	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4290	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4291	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
sahilmgandhi	18:6a4db94011d3	4292	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4293	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
sahilmgandhi	18:6a4db94011d3	4294	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4295	} while(0)
sahilmgandhi	18:6a4db94011d3	4296	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4297	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4298	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
sahilmgandhi	18:6a4db94011d3	4299	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4300	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
sahilmgandhi	18:6a4db94011d3	4301	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4302	} while(0)
sahilmgandhi	18:6a4db94011d3	4303	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4304	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4305	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
sahilmgandhi	18:6a4db94011d3	4306	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4307	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
sahilmgandhi	18:6a4db94011d3	4308	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4309	} while(0)
sahilmgandhi	18:6a4db94011d3	4310	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4311	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4312	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	4313	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4314	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	4315	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4316	} while(0)
sahilmgandhi	18:6a4db94011d3	4317	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4318	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4319	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	4320	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4321	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	4322	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4323	} while(0)
sahilmgandhi	18:6a4db94011d3	4324	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4325	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4326	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	4327	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4328	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	4329	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4330	} while(0)
sahilmgandhi	18:6a4db94011d3	4331	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
sahilmgandhi	18:6a4db94011d3	4332	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
sahilmgandhi	18:6a4db94011d3	4333	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
sahilmgandhi	18:6a4db94011d3	4334	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
sahilmgandhi	18:6a4db94011d3	4335	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
sahilmgandhi	18:6a4db94011d3	4336	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
sahilmgandhi	18:6a4db94011d3	4337	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
sahilmgandhi	18:6a4db94011d3	4338	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
sahilmgandhi	18:6a4db94011d3	4339	/**
sahilmgandhi	18:6a4db94011d3	4340	* @}
sahilmgandhi	18:6a4db94011d3	4341	*/
sahilmgandhi	18:6a4db94011d3	4342
sahilmgandhi	18:6a4db94011d3	4343	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	4344	* @brief Get the enable or disable status of the APB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4345	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4346	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4347	* using it.
sahilmgandhi	18:6a4db94011d3	4348	* @{
sahilmgandhi	18:6a4db94011d3	4349	*/
sahilmgandhi	18:6a4db94011d3	4350	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4351	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4352	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4353	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4354	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4355	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4356	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4357	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4358
sahilmgandhi	18:6a4db94011d3	4359	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4360	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4361	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4362	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4363	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4364	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4365	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4366	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4367	/**
sahilmgandhi	18:6a4db94011d3	4368	* @}
sahilmgandhi	18:6a4db94011d3	4369	*/
sahilmgandhi	18:6a4db94011d3	4370
sahilmgandhi	18:6a4db94011d3	4371	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	4372	* @brief Force or release AHB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	4373	* @{
sahilmgandhi	18:6a4db94011d3	4374	*/
sahilmgandhi	18:6a4db94011d3	4375	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	4376	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	4377	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
sahilmgandhi	18:6a4db94011d3	4378	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
sahilmgandhi	18:6a4db94011d3	4379	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
sahilmgandhi	18:6a4db94011d3	4380	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	4381
sahilmgandhi	18:6a4db94011d3	4382	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	4383	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	4384	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
sahilmgandhi	18:6a4db94011d3	4385	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
sahilmgandhi	18:6a4db94011d3	4386	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
sahilmgandhi	18:6a4db94011d3	4387	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	4388	/**
sahilmgandhi	18:6a4db94011d3	4389	* @}
sahilmgandhi	18:6a4db94011d3	4390	*/
sahilmgandhi	18:6a4db94011d3	4391
sahilmgandhi	18:6a4db94011d3	4392	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	4393	* @brief Force or release AHB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	4394	* @{
sahilmgandhi	18:6a4db94011d3	4395	*/
sahilmgandhi	18:6a4db94011d3	4396	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	4397	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	4398	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	4399	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
sahilmgandhi	18:6a4db94011d3	4400
sahilmgandhi	18:6a4db94011d3	4401	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	4402	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	4403	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	4404	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
sahilmgandhi	18:6a4db94011d3	4405	/**
sahilmgandhi	18:6a4db94011d3	4406	* @}
sahilmgandhi	18:6a4db94011d3	4407	*/
sahilmgandhi	18:6a4db94011d3	4408
sahilmgandhi	18:6a4db94011d3	4409	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
sahilmgandhi	18:6a4db94011d3	4410	* @brief Force or release AHB3 peripheral reset.
sahilmgandhi	18:6a4db94011d3	4411	* @{
sahilmgandhi	18:6a4db94011d3	4412	*/
sahilmgandhi	18:6a4db94011d3	4413	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	4414	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	4415
sahilmgandhi	18:6a4db94011d3	4416	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
sahilmgandhi	18:6a4db94011d3	4417	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
sahilmgandhi	18:6a4db94011d3	4418
sahilmgandhi	18:6a4db94011d3	4419	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
sahilmgandhi	18:6a4db94011d3	4420	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
sahilmgandhi	18:6a4db94011d3	4421	/**
sahilmgandhi	18:6a4db94011d3	4422	* @}
sahilmgandhi	18:6a4db94011d3	4423	*/
sahilmgandhi	18:6a4db94011d3	4424
sahilmgandhi	18:6a4db94011d3	4425	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	4426	* @brief Force or release APB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	4427	* @{
sahilmgandhi	18:6a4db94011d3	4428	*/
sahilmgandhi	18:6a4db94011d3	4429	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	4430	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
sahilmgandhi	18:6a4db94011d3	4431	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
sahilmgandhi	18:6a4db94011d3	4432	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
sahilmgandhi	18:6a4db94011d3	4433	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
sahilmgandhi	18:6a4db94011d3	4434	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
sahilmgandhi	18:6a4db94011d3	4435	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
sahilmgandhi	18:6a4db94011d3	4436	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
sahilmgandhi	18:6a4db94011d3	4437	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
sahilmgandhi	18:6a4db94011d3	4438	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
sahilmgandhi	18:6a4db94011d3	4439	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
sahilmgandhi	18:6a4db94011d3	4440	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
sahilmgandhi	18:6a4db94011d3	4441	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
sahilmgandhi	18:6a4db94011d3	4442	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
sahilmgandhi	18:6a4db94011d3	4443	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	4444	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	4445	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	4446	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	4447	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	4448
sahilmgandhi	18:6a4db94011d3	4449	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	4450	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	4451	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	4452	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	4453	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	4454	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	4455	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
sahilmgandhi	18:6a4db94011d3	4456	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
sahilmgandhi	18:6a4db94011d3	4457	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
sahilmgandhi	18:6a4db94011d3	4458	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
sahilmgandhi	18:6a4db94011d3	4459	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
sahilmgandhi	18:6a4db94011d3	4460	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
sahilmgandhi	18:6a4db94011d3	4461	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
sahilmgandhi	18:6a4db94011d3	4462	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
sahilmgandhi	18:6a4db94011d3	4463	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
sahilmgandhi	18:6a4db94011d3	4464	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
sahilmgandhi	18:6a4db94011d3	4465	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
sahilmgandhi	18:6a4db94011d3	4466	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
sahilmgandhi	18:6a4db94011d3	4467	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
sahilmgandhi	18:6a4db94011d3	4468	/**
sahilmgandhi	18:6a4db94011d3	4469	* @}
sahilmgandhi	18:6a4db94011d3	4470	*/
sahilmgandhi	18:6a4db94011d3	4471
sahilmgandhi	18:6a4db94011d3	4472	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	4473	* @brief Force or release APB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	4474	* @{
sahilmgandhi	18:6a4db94011d3	4475	*/
sahilmgandhi	18:6a4db94011d3	4476	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
sahilmgandhi	18:6a4db94011d3	4477	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
sahilmgandhi	18:6a4db94011d3	4478	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
sahilmgandhi	18:6a4db94011d3	4479	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	4480	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	4481	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	4482
sahilmgandhi	18:6a4db94011d3	4483	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	4484	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	4485	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	4486	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
sahilmgandhi	18:6a4db94011d3	4487	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
sahilmgandhi	18:6a4db94011d3	4488	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
sahilmgandhi	18:6a4db94011d3	4489	/**
sahilmgandhi	18:6a4db94011d3	4490	* @}
sahilmgandhi	18:6a4db94011d3	4491	*/
sahilmgandhi	18:6a4db94011d3	4492
sahilmgandhi	18:6a4db94011d3	4493	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	4494	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	4495	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	4496	* power consumption.
sahilmgandhi	18:6a4db94011d3	4497	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	4498	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	4499	* @{
sahilmgandhi	18:6a4db94011d3	4500	*/
sahilmgandhi	18:6a4db94011d3	4501	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	4502	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	4503	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
sahilmgandhi	18:6a4db94011d3	4504	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
sahilmgandhi	18:6a4db94011d3	4505	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
sahilmgandhi	18:6a4db94011d3	4506	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
sahilmgandhi	18:6a4db94011d3	4507	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
sahilmgandhi	18:6a4db94011d3	4508	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	4509	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	4510	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	4511	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
sahilmgandhi	18:6a4db94011d3	4512
sahilmgandhi	18:6a4db94011d3	4513	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	4514	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	4515	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
sahilmgandhi	18:6a4db94011d3	4516	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
sahilmgandhi	18:6a4db94011d3	4517	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
sahilmgandhi	18:6a4db94011d3	4518	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
sahilmgandhi	18:6a4db94011d3	4519	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
sahilmgandhi	18:6a4db94011d3	4520	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	4521	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	4522	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	4523	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
sahilmgandhi	18:6a4db94011d3	4524	/**
sahilmgandhi	18:6a4db94011d3	4525	* @}
sahilmgandhi	18:6a4db94011d3	4526	*/
sahilmgandhi	18:6a4db94011d3	4527
sahilmgandhi	18:6a4db94011d3	4528	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	4529	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	4530	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	4531	* power consumption.
sahilmgandhi	18:6a4db94011d3	4532	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	4533	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	4534	* @{
sahilmgandhi	18:6a4db94011d3	4535	*/
sahilmgandhi	18:6a4db94011d3	4536	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	4537	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	4538
sahilmgandhi	18:6a4db94011d3	4539	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	4540	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	4541
sahilmgandhi	18:6a4db94011d3	4542	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
sahilmgandhi	18:6a4db94011d3	4543	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
sahilmgandhi	18:6a4db94011d3	4544	/**
sahilmgandhi	18:6a4db94011d3	4545	* @}
sahilmgandhi	18:6a4db94011d3	4546	*/
sahilmgandhi	18:6a4db94011d3	4547
sahilmgandhi	18:6a4db94011d3	4548	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	4549	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	4550	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	4551	* power consumption.
sahilmgandhi	18:6a4db94011d3	4552	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	4553	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	4554	* @{
sahilmgandhi	18:6a4db94011d3	4555	*/
sahilmgandhi	18:6a4db94011d3	4556	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
sahilmgandhi	18:6a4db94011d3	4557	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
sahilmgandhi	18:6a4db94011d3	4558
sahilmgandhi	18:6a4db94011d3	4559	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
sahilmgandhi	18:6a4db94011d3	4560	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
sahilmgandhi	18:6a4db94011d3	4561	/**
sahilmgandhi	18:6a4db94011d3	4562	* @}
sahilmgandhi	18:6a4db94011d3	4563	*/
sahilmgandhi	18:6a4db94011d3	4564
sahilmgandhi	18:6a4db94011d3	4565	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	4566	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	4567	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	4568	* power consumption.
sahilmgandhi	18:6a4db94011d3	4569	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	4570	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	4571	* @{
sahilmgandhi	18:6a4db94011d3	4572	*/
sahilmgandhi	18:6a4db94011d3	4573	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	4574	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
sahilmgandhi	18:6a4db94011d3	4575	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
sahilmgandhi	18:6a4db94011d3	4576	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
sahilmgandhi	18:6a4db94011d3	4577	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
sahilmgandhi	18:6a4db94011d3	4578	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
sahilmgandhi	18:6a4db94011d3	4579	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
sahilmgandhi	18:6a4db94011d3	4580	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
sahilmgandhi	18:6a4db94011d3	4581	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
sahilmgandhi	18:6a4db94011d3	4582	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
sahilmgandhi	18:6a4db94011d3	4583	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
sahilmgandhi	18:6a4db94011d3	4584	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
sahilmgandhi	18:6a4db94011d3	4585	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
sahilmgandhi	18:6a4db94011d3	4586	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
sahilmgandhi	18:6a4db94011d3	4587	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	4588	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	4589	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	4590	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	4591	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	4592
sahilmgandhi	18:6a4db94011d3	4593	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	4594	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	4595	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	4596	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	4597	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	4598	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	4599	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
sahilmgandhi	18:6a4db94011d3	4600	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
sahilmgandhi	18:6a4db94011d3	4601	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
sahilmgandhi	18:6a4db94011d3	4602	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
sahilmgandhi	18:6a4db94011d3	4603	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
sahilmgandhi	18:6a4db94011d3	4604	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
sahilmgandhi	18:6a4db94011d3	4605	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
sahilmgandhi	18:6a4db94011d3	4606	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
sahilmgandhi	18:6a4db94011d3	4607	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
sahilmgandhi	18:6a4db94011d3	4608	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
sahilmgandhi	18:6a4db94011d3	4609	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
sahilmgandhi	18:6a4db94011d3	4610	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
sahilmgandhi	18:6a4db94011d3	4611	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
sahilmgandhi	18:6a4db94011d3	4612	/**
sahilmgandhi	18:6a4db94011d3	4613	* @}
sahilmgandhi	18:6a4db94011d3	4614	*/
sahilmgandhi	18:6a4db94011d3	4615
sahilmgandhi	18:6a4db94011d3	4616	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	4617	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	4618	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	4619	* power consumption.
sahilmgandhi	18:6a4db94011d3	4620	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	4621	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	4622	* @{
sahilmgandhi	18:6a4db94011d3	4623	*/
sahilmgandhi	18:6a4db94011d3	4624	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
sahilmgandhi	18:6a4db94011d3	4625	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
sahilmgandhi	18:6a4db94011d3	4626	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
sahilmgandhi	18:6a4db94011d3	4627	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
sahilmgandhi	18:6a4db94011d3	4628	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
sahilmgandhi	18:6a4db94011d3	4629	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	4630	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	4631	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	4632
sahilmgandhi	18:6a4db94011d3	4633	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	4634	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	4635	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	4636	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
sahilmgandhi	18:6a4db94011d3	4637	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
sahilmgandhi	18:6a4db94011d3	4638	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
sahilmgandhi	18:6a4db94011d3	4639	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
sahilmgandhi	18:6a4db94011d3	4640	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
sahilmgandhi	18:6a4db94011d3	4641	/**
sahilmgandhi	18:6a4db94011d3	4642	* @}
sahilmgandhi	18:6a4db94011d3	4643	*/
sahilmgandhi	18:6a4db94011d3	4644
sahilmgandhi	18:6a4db94011d3	4645	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	4646	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	4647
sahilmgandhi	18:6a4db94011d3	4648	/----------STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx----------/
sahilmgandhi	18:6a4db94011d3	4649	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	4650	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	4651	* @brief Enables or disables the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4652	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4653	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4654	* using it.
sahilmgandhi	18:6a4db94011d3	4655	* @{
sahilmgandhi	18:6a4db94011d3	4656	*/
sahilmgandhi	18:6a4db94011d3	4657	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4658	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4659	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	4660	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4661	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	4662	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4663	} while(0)
sahilmgandhi	18:6a4db94011d3	4664	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4665	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4666	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	4667	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4668	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
sahilmgandhi	18:6a4db94011d3	4669	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4670	} while(0)
sahilmgandhi	18:6a4db94011d3	4671	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4672	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4673	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	4674	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4675	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
sahilmgandhi	18:6a4db94011d3	4676	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4677	} while(0)
sahilmgandhi	18:6a4db94011d3	4678	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4679	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4680	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
sahilmgandhi	18:6a4db94011d3	4681	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4682	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
sahilmgandhi	18:6a4db94011d3	4683	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4684	} while(0)
sahilmgandhi	18:6a4db94011d3	4685	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4686	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4687	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
sahilmgandhi	18:6a4db94011d3	4688	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4689	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
sahilmgandhi	18:6a4db94011d3	4690	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4691	} while(0)
sahilmgandhi	18:6a4db94011d3	4692	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4693	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4694	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	4695	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4696	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
sahilmgandhi	18:6a4db94011d3	4697	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4698	} while(0)
sahilmgandhi	18:6a4db94011d3	4699
sahilmgandhi	18:6a4db94011d3	4700	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
sahilmgandhi	18:6a4db94011d3	4701	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
sahilmgandhi	18:6a4db94011d3	4702	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
sahilmgandhi	18:6a4db94011d3	4703	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
sahilmgandhi	18:6a4db94011d3	4704	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
sahilmgandhi	18:6a4db94011d3	4705	/**
sahilmgandhi	18:6a4db94011d3	4706	* @}
sahilmgandhi	18:6a4db94011d3	4707	*/
sahilmgandhi	18:6a4db94011d3	4708
sahilmgandhi	18:6a4db94011d3	4709	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	4710	* @brief Get the enable or disable status of the AHB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4711	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4712	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4713	* using it.
sahilmgandhi	18:6a4db94011d3	4714	* @{
sahilmgandhi	18:6a4db94011d3	4715	*/
sahilmgandhi	18:6a4db94011d3	4716	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4717	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4718	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4719	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4720	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4721
sahilmgandhi	18:6a4db94011d3	4722	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4723	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4724	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4725	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4726	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4727	/**
sahilmgandhi	18:6a4db94011d3	4728	* @}
sahilmgandhi	18:6a4db94011d3	4729	*/
sahilmgandhi	18:6a4db94011d3	4730
sahilmgandhi	18:6a4db94011d3	4731	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	4732	* @brief Enable or disable the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4733	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4734	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4735	* using it.
sahilmgandhi	18:6a4db94011d3	4736	* @{
sahilmgandhi	18:6a4db94011d3	4737	*/
sahilmgandhi	18:6a4db94011d3	4738	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
sahilmgandhi	18:6a4db94011d3	4739	__HAL_RCC_SYSCFG_CLK_ENABLE();\
sahilmgandhi	18:6a4db94011d3	4740	}while(0)
sahilmgandhi	18:6a4db94011d3	4741
sahilmgandhi	18:6a4db94011d3	4742	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
sahilmgandhi	18:6a4db94011d3	4743
sahilmgandhi	18:6a4db94011d3	4744	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4745	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4746	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	4747	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4748	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
sahilmgandhi	18:6a4db94011d3	4749	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4750	} while(0)
sahilmgandhi	18:6a4db94011d3	4751	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
sahilmgandhi	18:6a4db94011d3	4752	/**
sahilmgandhi	18:6a4db94011d3	4753	* @}
sahilmgandhi	18:6a4db94011d3	4754	*/
sahilmgandhi	18:6a4db94011d3	4755
sahilmgandhi	18:6a4db94011d3	4756	/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	4757	* @brief Get the enable or disable status of the AHB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4758	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4759	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4760	* using it.
sahilmgandhi	18:6a4db94011d3	4761	* @{
sahilmgandhi	18:6a4db94011d3	4762	*/
sahilmgandhi	18:6a4db94011d3	4763	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4764	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4765
sahilmgandhi	18:6a4db94011d3	4766	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4767	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4768	/**
sahilmgandhi	18:6a4db94011d3	4769	* @}
sahilmgandhi	18:6a4db94011d3	4770	*/
sahilmgandhi	18:6a4db94011d3	4771
sahilmgandhi	18:6a4db94011d3	4772	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	4773	* @brief Enables or disables the AHB3 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4774	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4775	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4776	* using it.
sahilmgandhi	18:6a4db94011d3	4777	* @{
sahilmgandhi	18:6a4db94011d3	4778	*/
sahilmgandhi	18:6a4db94011d3	4779	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx)
sahilmgandhi	18:6a4db94011d3	4780	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4781	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4782	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
sahilmgandhi	18:6a4db94011d3	4783	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4784	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
sahilmgandhi	18:6a4db94011d3	4785	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4786	} while(0)
sahilmgandhi	18:6a4db94011d3	4787	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4788	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4789	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
sahilmgandhi	18:6a4db94011d3	4790	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4791	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
sahilmgandhi	18:6a4db94011d3	4792	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4793	} while(0)
sahilmgandhi	18:6a4db94011d3	4794
sahilmgandhi	18:6a4db94011d3	4795	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
sahilmgandhi	18:6a4db94011d3	4796	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
sahilmgandhi	18:6a4db94011d3	4797	#endif /* STM32F412Zx \|\| STM32F412Vx */
sahilmgandhi	18:6a4db94011d3	4798	#if defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	4799	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4800	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4801	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
sahilmgandhi	18:6a4db94011d3	4802	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4803	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
sahilmgandhi	18:6a4db94011d3	4804	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4805	} while(0)
sahilmgandhi	18:6a4db94011d3	4806
sahilmgandhi	18:6a4db94011d3	4807	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
sahilmgandhi	18:6a4db94011d3	4808	#endif /* STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	4809	/**
sahilmgandhi	18:6a4db94011d3	4810	* @}
sahilmgandhi	18:6a4db94011d3	4811	*/
sahilmgandhi	18:6a4db94011d3	4812
sahilmgandhi	18:6a4db94011d3	4813	/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	4814	* @brief Get the enable or disable status of the AHB3 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4815	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4816	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4817	* using it.
sahilmgandhi	18:6a4db94011d3	4818	* @{
sahilmgandhi	18:6a4db94011d3	4819	*/
sahilmgandhi	18:6a4db94011d3	4820	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx)
sahilmgandhi	18:6a4db94011d3	4821	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4822	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4823
sahilmgandhi	18:6a4db94011d3	4824	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4825	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4826	#endif /* STM32F412Zx \|\| STM32F412Vx */
sahilmgandhi	18:6a4db94011d3	4827	#if defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	4828	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4829	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4830	#endif /* STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	4831	/**
sahilmgandhi	18:6a4db94011d3	4832	* @}
sahilmgandhi	18:6a4db94011d3	4833	*/
sahilmgandhi	18:6a4db94011d3	4834
sahilmgandhi	18:6a4db94011d3	4835	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	4836	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
sahilmgandhi	18:6a4db94011d3	4837	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4838	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4839	* using it.
sahilmgandhi	18:6a4db94011d3	4840	* @{
sahilmgandhi	18:6a4db94011d3	4841	*/
sahilmgandhi	18:6a4db94011d3	4842	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4843	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4844	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	4845	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4846	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
sahilmgandhi	18:6a4db94011d3	4847	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4848	} while(0)
sahilmgandhi	18:6a4db94011d3	4849	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4850	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4851	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
sahilmgandhi	18:6a4db94011d3	4852	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4853	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
sahilmgandhi	18:6a4db94011d3	4854	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4855	} while(0)
sahilmgandhi	18:6a4db94011d3	4856	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4857	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4858	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
sahilmgandhi	18:6a4db94011d3	4859	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4860	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
sahilmgandhi	18:6a4db94011d3	4861	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4862	} while(0)
sahilmgandhi	18:6a4db94011d3	4863	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4864	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4865	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
sahilmgandhi	18:6a4db94011d3	4866	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4867	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
sahilmgandhi	18:6a4db94011d3	4868	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4869	} while(0)
sahilmgandhi	18:6a4db94011d3	4870	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4871	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4872	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	4873	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4874	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
sahilmgandhi	18:6a4db94011d3	4875	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4876	} while(0)
sahilmgandhi	18:6a4db94011d3	4877	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4878	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4879	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
sahilmgandhi	18:6a4db94011d3	4880	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4881	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
sahilmgandhi	18:6a4db94011d3	4882	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4883	} while(0)
sahilmgandhi	18:6a4db94011d3	4884	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	4885	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4886	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4887	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
sahilmgandhi	18:6a4db94011d3	4888	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4889	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
sahilmgandhi	18:6a4db94011d3	4890	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4891	} while(0)
sahilmgandhi	18:6a4db94011d3	4892	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	4893	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4894	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4895	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
sahilmgandhi	18:6a4db94011d3	4896	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4897	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
sahilmgandhi	18:6a4db94011d3	4898	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4899	} while(0)
sahilmgandhi	18:6a4db94011d3	4900	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4901	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4902	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
sahilmgandhi	18:6a4db94011d3	4903	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4904	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
sahilmgandhi	18:6a4db94011d3	4905	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4906	} while(0)
sahilmgandhi	18:6a4db94011d3	4907	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4908	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4909	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
sahilmgandhi	18:6a4db94011d3	4910	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4911	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
sahilmgandhi	18:6a4db94011d3	4912	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4913	} while(0)
sahilmgandhi	18:6a4db94011d3	4914	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4915	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4916	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	4917	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4918	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
sahilmgandhi	18:6a4db94011d3	4919	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4920	} while(0)
sahilmgandhi	18:6a4db94011d3	4921	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4922	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4923	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	4924	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4925	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
sahilmgandhi	18:6a4db94011d3	4926	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4927	} while(0)
sahilmgandhi	18:6a4db94011d3	4928	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4929	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4930	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	4931	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4932	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
sahilmgandhi	18:6a4db94011d3	4933	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4934	} while(0)
sahilmgandhi	18:6a4db94011d3	4935	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4936	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4937	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	4938	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4939	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
sahilmgandhi	18:6a4db94011d3	4940	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4941	} while(0)
sahilmgandhi	18:6a4db94011d3	4942	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	4943	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	4944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	4945	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	4946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
sahilmgandhi	18:6a4db94011d3	4947	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	4948	} while(0)
sahilmgandhi	18:6a4db94011d3	4949	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
sahilmgandhi	18:6a4db94011d3	4950	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
sahilmgandhi	18:6a4db94011d3	4951	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
sahilmgandhi	18:6a4db94011d3	4952	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
sahilmgandhi	18:6a4db94011d3	4953	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
sahilmgandhi	18:6a4db94011d3	4954	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
sahilmgandhi	18:6a4db94011d3	4955	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
sahilmgandhi	18:6a4db94011d3	4956	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
sahilmgandhi	18:6a4db94011d3	4957	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
sahilmgandhi	18:6a4db94011d3	4958	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
sahilmgandhi	18:6a4db94011d3	4959	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
sahilmgandhi	18:6a4db94011d3	4960	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	4961	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
sahilmgandhi	18:6a4db94011d3	4962	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	4963	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
sahilmgandhi	18:6a4db94011d3	4964	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
sahilmgandhi	18:6a4db94011d3	4965	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
sahilmgandhi	18:6a4db94011d3	4966	/**
sahilmgandhi	18:6a4db94011d3	4967	* @}
sahilmgandhi	18:6a4db94011d3	4968	*/
sahilmgandhi	18:6a4db94011d3	4969
sahilmgandhi	18:6a4db94011d3	4970	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	4971	* @brief Get the enable or disable status of the APB1 peripheral clock.
sahilmgandhi	18:6a4db94011d3	4972	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	4973	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	4974	* using it.
sahilmgandhi	18:6a4db94011d3	4975	* @{
sahilmgandhi	18:6a4db94011d3	4976	*/
sahilmgandhi	18:6a4db94011d3	4977	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4978	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4979	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4980	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4981	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4982	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4983	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4984	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4985	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4986	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4987	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4988	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	4989	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4990	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	4991	#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4992	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
sahilmgandhi	18:6a4db94011d3	4993	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	4994
sahilmgandhi	18:6a4db94011d3	4995	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4996	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4997	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4998	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	4999	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5000	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5001	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5002	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5003	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5004	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5005	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5006	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	5007	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5008	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	5009	#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5010	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5011	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5012	/**
sahilmgandhi	18:6a4db94011d3	5013	* @}
sahilmgandhi	18:6a4db94011d3	5014	*/
sahilmgandhi	18:6a4db94011d3	5015	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
sahilmgandhi	18:6a4db94011d3	5016	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
sahilmgandhi	18:6a4db94011d3	5017	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	5018	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	5019	* using it.
sahilmgandhi	18:6a4db94011d3	5020	* @{
sahilmgandhi	18:6a4db94011d3	5021	*/
sahilmgandhi	18:6a4db94011d3	5022	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	5023	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	5024	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
sahilmgandhi	18:6a4db94011d3	5025	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	5026	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
sahilmgandhi	18:6a4db94011d3	5027	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	5028	} while(0)
sahilmgandhi	18:6a4db94011d3	5029	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	5030	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	5031	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
sahilmgandhi	18:6a4db94011d3	5032	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	5033	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
sahilmgandhi	18:6a4db94011d3	5034	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	5035	} while(0)
sahilmgandhi	18:6a4db94011d3	5036	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	5037	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	5038	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
sahilmgandhi	18:6a4db94011d3	5039	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	5040	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
sahilmgandhi	18:6a4db94011d3	5041	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	5042	} while(0)
sahilmgandhi	18:6a4db94011d3	5043	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	5044	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	5045	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
sahilmgandhi	18:6a4db94011d3	5046	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	5047	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
sahilmgandhi	18:6a4db94011d3	5048	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	5049	} while(0)
sahilmgandhi	18:6a4db94011d3	5050	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	5051	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	5052	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	5053	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	5054	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
sahilmgandhi	18:6a4db94011d3	5055	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	5056	} while(0)
sahilmgandhi	18:6a4db94011d3	5057	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	5058	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	5059	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	5060	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	5061	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
sahilmgandhi	18:6a4db94011d3	5062	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	5063	} while(0)
sahilmgandhi	18:6a4db94011d3	5064	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
sahilmgandhi	18:6a4db94011d3	5065	__IO uint32_t tmpreg = 0x00U; \
sahilmgandhi	18:6a4db94011d3	5066	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	5067	/* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi	18:6a4db94011d3	5068	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
sahilmgandhi	18:6a4db94011d3	5069	UNUSED(tmpreg); \
sahilmgandhi	18:6a4db94011d3	5070	} while(0)
sahilmgandhi	18:6a4db94011d3	5071	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
sahilmgandhi	18:6a4db94011d3	5072	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
sahilmgandhi	18:6a4db94011d3	5073	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
sahilmgandhi	18:6a4db94011d3	5074	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
sahilmgandhi	18:6a4db94011d3	5075	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
sahilmgandhi	18:6a4db94011d3	5076	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
sahilmgandhi	18:6a4db94011d3	5077	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
sahilmgandhi	18:6a4db94011d3	5078	/**
sahilmgandhi	18:6a4db94011d3	5079	* @}
sahilmgandhi	18:6a4db94011d3	5080	*/
sahilmgandhi	18:6a4db94011d3	5081
sahilmgandhi	18:6a4db94011d3	5082	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
sahilmgandhi	18:6a4db94011d3	5083	* @brief Get the enable or disable status of the APB2 peripheral clock.
sahilmgandhi	18:6a4db94011d3	5084	* @note After reset, the peripheral clock (used for registers read/write access)
sahilmgandhi	18:6a4db94011d3	5085	* is disabled and the application software has to enable this clock before
sahilmgandhi	18:6a4db94011d3	5086	* using it.
sahilmgandhi	18:6a4db94011d3	5087	* @{
sahilmgandhi	18:6a4db94011d3	5088	*/
sahilmgandhi	18:6a4db94011d3	5089	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	5090	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	5091	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	5092	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	5093	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	5094	#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
sahilmgandhi	18:6a4db94011d3	5095	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
sahilmgandhi	18:6a4db94011d3	5096
sahilmgandhi	18:6a4db94011d3	5097	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5098	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5099	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5100	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5101	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5102	#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5103	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
sahilmgandhi	18:6a4db94011d3	5104	/**
sahilmgandhi	18:6a4db94011d3	5105	* @}
sahilmgandhi	18:6a4db94011d3	5106	*/
sahilmgandhi	18:6a4db94011d3	5107
sahilmgandhi	18:6a4db94011d3	5108	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	5109	* @brief Force or release AHB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	5110	* @{
sahilmgandhi	18:6a4db94011d3	5111	*/
sahilmgandhi	18:6a4db94011d3	5112	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	5113	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	5114	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
sahilmgandhi	18:6a4db94011d3	5115	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
sahilmgandhi	18:6a4db94011d3	5116	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	5117
sahilmgandhi	18:6a4db94011d3	5118	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
sahilmgandhi	18:6a4db94011d3	5119	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
sahilmgandhi	18:6a4db94011d3	5120	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
sahilmgandhi	18:6a4db94011d3	5121	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
sahilmgandhi	18:6a4db94011d3	5122	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
sahilmgandhi	18:6a4db94011d3	5123	/**
sahilmgandhi	18:6a4db94011d3	5124	* @}
sahilmgandhi	18:6a4db94011d3	5125	*/
sahilmgandhi	18:6a4db94011d3	5126
sahilmgandhi	18:6a4db94011d3	5127	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	5128	* @brief Force or release AHB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	5129	* @{
sahilmgandhi	18:6a4db94011d3	5130	*/
sahilmgandhi	18:6a4db94011d3	5131	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	5132	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	5133
sahilmgandhi	18:6a4db94011d3	5134	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	5135	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
sahilmgandhi	18:6a4db94011d3	5136
sahilmgandhi	18:6a4db94011d3	5137	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	5138	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
sahilmgandhi	18:6a4db94011d3	5139	/**
sahilmgandhi	18:6a4db94011d3	5140	* @}
sahilmgandhi	18:6a4db94011d3	5141	*/
sahilmgandhi	18:6a4db94011d3	5142
sahilmgandhi	18:6a4db94011d3	5143	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
sahilmgandhi	18:6a4db94011d3	5144	* @brief Force or release AHB3 peripheral reset.
sahilmgandhi	18:6a4db94011d3	5145	* @{
sahilmgandhi	18:6a4db94011d3	5146	*/
sahilmgandhi	18:6a4db94011d3	5147	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx)
sahilmgandhi	18:6a4db94011d3	5148	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	5149	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	5150
sahilmgandhi	18:6a4db94011d3	5151	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
sahilmgandhi	18:6a4db94011d3	5152	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
sahilmgandhi	18:6a4db94011d3	5153
sahilmgandhi	18:6a4db94011d3	5154	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
sahilmgandhi	18:6a4db94011d3	5155	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
sahilmgandhi	18:6a4db94011d3	5156	#endif /* STM32F412Zx \|\| STM32F412Vx */
sahilmgandhi	18:6a4db94011d3	5157	#if defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	5158	#define __HAL_RCC_AHB3_FORCE_RESET()
sahilmgandhi	18:6a4db94011d3	5159	#define __HAL_RCC_AHB3_RELEASE_RESET()
sahilmgandhi	18:6a4db94011d3	5160
sahilmgandhi	18:6a4db94011d3	5161	#define __HAL_RCC_FSMC_FORCE_RESET()
sahilmgandhi	18:6a4db94011d3	5162	#define __HAL_RCC_QSPI_FORCE_RESET()
sahilmgandhi	18:6a4db94011d3	5163
sahilmgandhi	18:6a4db94011d3	5164	#define __HAL_RCC_FSMC_RELEASE_RESET()
sahilmgandhi	18:6a4db94011d3	5165	#define __HAL_RCC_QSPI_RELEASE_RESET()
sahilmgandhi	18:6a4db94011d3	5166	#endif /* STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	5167	#if defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	5168	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
sahilmgandhi	18:6a4db94011d3	5169	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
sahilmgandhi	18:6a4db94011d3	5170
sahilmgandhi	18:6a4db94011d3	5171	#define __HAL_RCC_FSMC_FORCE_RESET()
sahilmgandhi	18:6a4db94011d3	5172	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
sahilmgandhi	18:6a4db94011d3	5173
sahilmgandhi	18:6a4db94011d3	5174	#define __HAL_RCC_FSMC_RELEASE_RESET()
sahilmgandhi	18:6a4db94011d3	5175	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
sahilmgandhi	18:6a4db94011d3	5176	#endif /* STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	5177	/**
sahilmgandhi	18:6a4db94011d3	5178	* @}
sahilmgandhi	18:6a4db94011d3	5179	*/
sahilmgandhi	18:6a4db94011d3	5180
sahilmgandhi	18:6a4db94011d3	5181	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
sahilmgandhi	18:6a4db94011d3	5182	* @brief Force or release APB1 peripheral reset.
sahilmgandhi	18:6a4db94011d3	5183	* @{
sahilmgandhi	18:6a4db94011d3	5184	*/
sahilmgandhi	18:6a4db94011d3	5185	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	5186	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
sahilmgandhi	18:6a4db94011d3	5187	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
sahilmgandhi	18:6a4db94011d3	5188	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
sahilmgandhi	18:6a4db94011d3	5189	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
sahilmgandhi	18:6a4db94011d3	5190	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	5191	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
sahilmgandhi	18:6a4db94011d3	5192	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	5193	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
sahilmgandhi	18:6a4db94011d3	5194	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
sahilmgandhi	18:6a4db94011d3	5195	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
sahilmgandhi	18:6a4db94011d3	5196	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	5197	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	5198	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	5199	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	5200	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	5201
sahilmgandhi	18:6a4db94011d3	5202	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
sahilmgandhi	18:6a4db94011d3	5203	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
sahilmgandhi	18:6a4db94011d3	5204	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
sahilmgandhi	18:6a4db94011d3	5205	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
sahilmgandhi	18:6a4db94011d3	5206	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
sahilmgandhi	18:6a4db94011d3	5207	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
sahilmgandhi	18:6a4db94011d3	5208	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
sahilmgandhi	18:6a4db94011d3	5209	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
sahilmgandhi	18:6a4db94011d3	5210	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
sahilmgandhi	18:6a4db94011d3	5211	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
sahilmgandhi	18:6a4db94011d3	5212	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	5213	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
sahilmgandhi	18:6a4db94011d3	5214	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	5215	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
sahilmgandhi	18:6a4db94011d3	5216	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
sahilmgandhi	18:6a4db94011d3	5217	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
sahilmgandhi	18:6a4db94011d3	5218	/**
sahilmgandhi	18:6a4db94011d3	5219	* @}
sahilmgandhi	18:6a4db94011d3	5220	*/
sahilmgandhi	18:6a4db94011d3	5221
sahilmgandhi	18:6a4db94011d3	5222	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
sahilmgandhi	18:6a4db94011d3	5223	* @brief Force or release APB2 peripheral reset.
sahilmgandhi	18:6a4db94011d3	5224	* @{
sahilmgandhi	18:6a4db94011d3	5225	*/
sahilmgandhi	18:6a4db94011d3	5226	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
sahilmgandhi	18:6a4db94011d3	5227	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
sahilmgandhi	18:6a4db94011d3	5228	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
sahilmgandhi	18:6a4db94011d3	5229	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	5230	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	5231	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	5232
sahilmgandhi	18:6a4db94011d3	5233	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
sahilmgandhi	18:6a4db94011d3	5234	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
sahilmgandhi	18:6a4db94011d3	5235	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
sahilmgandhi	18:6a4db94011d3	5236	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
sahilmgandhi	18:6a4db94011d3	5237	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
sahilmgandhi	18:6a4db94011d3	5238	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
sahilmgandhi	18:6a4db94011d3	5239	/**
sahilmgandhi	18:6a4db94011d3	5240	* @}
sahilmgandhi	18:6a4db94011d3	5241	*/
sahilmgandhi	18:6a4db94011d3	5242
sahilmgandhi	18:6a4db94011d3	5243	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	5244	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	5245	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	5246	* power consumption.
sahilmgandhi	18:6a4db94011d3	5247	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	5248	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	5249	* @{
sahilmgandhi	18:6a4db94011d3	5250	*/
sahilmgandhi	18:6a4db94011d3	5251	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	5252	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	5253	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
sahilmgandhi	18:6a4db94011d3	5254	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
sahilmgandhi	18:6a4db94011d3	5255	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	5256	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	5257	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	5258
sahilmgandhi	18:6a4db94011d3	5259	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
sahilmgandhi	18:6a4db94011d3	5260	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
sahilmgandhi	18:6a4db94011d3	5261	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
sahilmgandhi	18:6a4db94011d3	5262	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
sahilmgandhi	18:6a4db94011d3	5263	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
sahilmgandhi	18:6a4db94011d3	5264	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
sahilmgandhi	18:6a4db94011d3	5265	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
sahilmgandhi	18:6a4db94011d3	5266	/**
sahilmgandhi	18:6a4db94011d3	5267	* @}
sahilmgandhi	18:6a4db94011d3	5268	*/
sahilmgandhi	18:6a4db94011d3	5269
sahilmgandhi	18:6a4db94011d3	5270	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	5271	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	5272	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	5273	* power consumption.
sahilmgandhi	18:6a4db94011d3	5274	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	5275	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	5276	* @{
sahilmgandhi	18:6a4db94011d3	5277	*/
sahilmgandhi	18:6a4db94011d3	5278	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	5279
sahilmgandhi	18:6a4db94011d3	5280	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
sahilmgandhi	18:6a4db94011d3	5281
sahilmgandhi	18:6a4db94011d3	5282	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	5283	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
sahilmgandhi	18:6a4db94011d3	5284	/**
sahilmgandhi	18:6a4db94011d3	5285	* @}
sahilmgandhi	18:6a4db94011d3	5286	*/
sahilmgandhi	18:6a4db94011d3	5287
sahilmgandhi	18:6a4db94011d3	5288	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	5289	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	5290	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	5291	* power consumption.
sahilmgandhi	18:6a4db94011d3	5292	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	5293	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	5294	* @{
sahilmgandhi	18:6a4db94011d3	5295	*/
sahilmgandhi	18:6a4db94011d3	5296	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx)
sahilmgandhi	18:6a4db94011d3	5297	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
sahilmgandhi	18:6a4db94011d3	5298	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
sahilmgandhi	18:6a4db94011d3	5299
sahilmgandhi	18:6a4db94011d3	5300	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
sahilmgandhi	18:6a4db94011d3	5301	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
sahilmgandhi	18:6a4db94011d3	5302	#endif /* STM32F412Zx \|\| STM32F412Vx */
sahilmgandhi	18:6a4db94011d3	5303
sahilmgandhi	18:6a4db94011d3	5304	#if defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	5305	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
sahilmgandhi	18:6a4db94011d3	5306	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
sahilmgandhi	18:6a4db94011d3	5307	#endif /* STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	5308	/**
sahilmgandhi	18:6a4db94011d3	5309	* @}
sahilmgandhi	18:6a4db94011d3	5310	*/
sahilmgandhi	18:6a4db94011d3	5311
sahilmgandhi	18:6a4db94011d3	5312	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	5313	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	5314	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	5315	* power consumption.
sahilmgandhi	18:6a4db94011d3	5316	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	5317	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	5318	* @{
sahilmgandhi	18:6a4db94011d3	5319	*/
sahilmgandhi	18:6a4db94011d3	5320	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	5321	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
sahilmgandhi	18:6a4db94011d3	5322	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
sahilmgandhi	18:6a4db94011d3	5323	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
sahilmgandhi	18:6a4db94011d3	5324	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
sahilmgandhi	18:6a4db94011d3	5325	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
sahilmgandhi	18:6a4db94011d3	5326	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	5327	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
sahilmgandhi	18:6a4db94011d3	5328	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	5329	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
sahilmgandhi	18:6a4db94011d3	5330	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
sahilmgandhi	18:6a4db94011d3	5331	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
sahilmgandhi	18:6a4db94011d3	5332	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	5333	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	5334	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	5335	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	5336	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	5337
sahilmgandhi	18:6a4db94011d3	5338	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
sahilmgandhi	18:6a4db94011d3	5339	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
sahilmgandhi	18:6a4db94011d3	5340	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
sahilmgandhi	18:6a4db94011d3	5341	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
sahilmgandhi	18:6a4db94011d3	5342	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
sahilmgandhi	18:6a4db94011d3	5343	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
sahilmgandhi	18:6a4db94011d3	5344	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
sahilmgandhi	18:6a4db94011d3	5345	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
sahilmgandhi	18:6a4db94011d3	5346	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
sahilmgandhi	18:6a4db94011d3	5347	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
sahilmgandhi	18:6a4db94011d3	5348	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
sahilmgandhi	18:6a4db94011d3	5349	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	5350	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
sahilmgandhi	18:6a4db94011d3	5351	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	5352	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
sahilmgandhi	18:6a4db94011d3	5353	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
sahilmgandhi	18:6a4db94011d3	5354	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
sahilmgandhi	18:6a4db94011d3	5355	/**
sahilmgandhi	18:6a4db94011d3	5356	* @}
sahilmgandhi	18:6a4db94011d3	5357	*/
sahilmgandhi	18:6a4db94011d3	5358
sahilmgandhi	18:6a4db94011d3	5359	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
sahilmgandhi	18:6a4db94011d3	5360	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
sahilmgandhi	18:6a4db94011d3	5361	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
sahilmgandhi	18:6a4db94011d3	5362	* power consumption.
sahilmgandhi	18:6a4db94011d3	5363	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
sahilmgandhi	18:6a4db94011d3	5364	* @note By default, all peripheral clocks are enabled during SLEEP mode.
sahilmgandhi	18:6a4db94011d3	5365	* @{
sahilmgandhi	18:6a4db94011d3	5366	*/
sahilmgandhi	18:6a4db94011d3	5367	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
sahilmgandhi	18:6a4db94011d3	5368	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
sahilmgandhi	18:6a4db94011d3	5369	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
sahilmgandhi	18:6a4db94011d3	5370	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
sahilmgandhi	18:6a4db94011d3	5371	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	5372	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	5373	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	5374
sahilmgandhi	18:6a4db94011d3	5375	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
sahilmgandhi	18:6a4db94011d3	5376	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
sahilmgandhi	18:6a4db94011d3	5377	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
sahilmgandhi	18:6a4db94011d3	5378	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
sahilmgandhi	18:6a4db94011d3	5379	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
sahilmgandhi	18:6a4db94011d3	5380	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
sahilmgandhi	18:6a4db94011d3	5381	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
sahilmgandhi	18:6a4db94011d3	5382	/**
sahilmgandhi	18:6a4db94011d3	5383	* @}
sahilmgandhi	18:6a4db94011d3	5384	*/
sahilmgandhi	18:6a4db94011d3	5385	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	5386	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	5387
sahilmgandhi	18:6a4db94011d3	5388	/------------------------------- PLL Configuration --------------------------/
sahilmgandhi	18:6a4db94011d3	5389	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
sahilmgandhi	18:6a4db94011d3	5390	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	5391	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	5392	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
sahilmgandhi	18:6a4db94011d3	5393	* @note This function must be used only when the main PLL is disabled.
sahilmgandhi	18:6a4db94011d3	5394	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
sahilmgandhi	18:6a4db94011d3	5395	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5396	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
sahilmgandhi	18:6a4db94011d3	5397	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
sahilmgandhi	18:6a4db94011d3	5398	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
sahilmgandhi	18:6a4db94011d3	5399	* @param __PLLM__: specifies the division factor for PLL VCO input clock
sahilmgandhi	18:6a4db94011d3	5400	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
sahilmgandhi	18:6a4db94011d3	5401	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
sahilmgandhi	18:6a4db94011d3	5402	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
sahilmgandhi	18:6a4db94011d3	5403	* of 2 MHz to limit PLL jitter.
sahilmgandhi	18:6a4db94011d3	5404	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
sahilmgandhi	18:6a4db94011d3	5405	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5406	* @note You have to set the PLLN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5407	* output frequency is between 100 and 432 MHz.
sahilmgandhi	18:6a4db94011d3	5408	*
sahilmgandhi	18:6a4db94011d3	5409	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
sahilmgandhi	18:6a4db94011d3	5410	* This parameter must be a number in the range {2, 4, 6, or 8}.
sahilmgandhi	18:6a4db94011d3	5411	*
sahilmgandhi	18:6a4db94011d3	5412	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
sahilmgandhi	18:6a4db94011d3	5413	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	5414	* @note If the USB OTG FS is used in your application, you have to set the
sahilmgandhi	18:6a4db94011d3	5415	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
sahilmgandhi	18:6a4db94011d3	5416	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
sahilmgandhi	18:6a4db94011d3	5417	* correctly.
sahilmgandhi	18:6a4db94011d3	5418	*
sahilmgandhi	18:6a4db94011d3	5419	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
sahilmgandhi	18:6a4db94011d3	5420	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5421	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
sahilmgandhi	18:6a4db94011d3	5422	STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
sahilmgandhi	18:6a4db94011d3	5423	*
sahilmgandhi	18:6a4db94011d3	5424	*/
sahilmgandhi	18:6a4db94011d3	5425	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
sahilmgandhi	18:6a4db94011d3	5426	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
sahilmgandhi	18:6a4db94011d3	5427	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
sahilmgandhi	18:6a4db94011d3	5428	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
sahilmgandhi	18:6a4db94011d3	5429	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
sahilmgandhi	18:6a4db94011d3	5430	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
sahilmgandhi	18:6a4db94011d3	5431	#else
sahilmgandhi	18:6a4db94011d3	5432	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
sahilmgandhi	18:6a4db94011d3	5433	* @note This function must be used only when the main PLL is disabled.
sahilmgandhi	18:6a4db94011d3	5434	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
sahilmgandhi	18:6a4db94011d3	5435	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5436	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
sahilmgandhi	18:6a4db94011d3	5437	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
sahilmgandhi	18:6a4db94011d3	5438	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
sahilmgandhi	18:6a4db94011d3	5439	* @param __PLLM__: specifies the division factor for PLL VCO input clock
sahilmgandhi	18:6a4db94011d3	5440	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
sahilmgandhi	18:6a4db94011d3	5441	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
sahilmgandhi	18:6a4db94011d3	5442	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
sahilmgandhi	18:6a4db94011d3	5443	* of 2 MHz to limit PLL jitter.
sahilmgandhi	18:6a4db94011d3	5444	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
sahilmgandhi	18:6a4db94011d3	5445	* This parameter must be a number between Min_Data = 50 and Max_Data = 432
sahilmgandhi	18:6a4db94011d3	5446	* Except for STM32F411xE devices where Min_Data = 192.
sahilmgandhi	18:6a4db94011d3	5447	* @note You have to set the PLLN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5448	* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
sahilmgandhi	18:6a4db94011d3	5449	* where frequency is between 192 and 432 MHz.
sahilmgandhi	18:6a4db94011d3	5450	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
sahilmgandhi	18:6a4db94011d3	5451	* This parameter must be a number in the range {2, 4, 6, or 8}.
sahilmgandhi	18:6a4db94011d3	5452	*
sahilmgandhi	18:6a4db94011d3	5453	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
sahilmgandhi	18:6a4db94011d3	5454	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	5455	* @note If the USB OTG FS is used in your application, you have to set the
sahilmgandhi	18:6a4db94011d3	5456	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
sahilmgandhi	18:6a4db94011d3	5457	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
sahilmgandhi	18:6a4db94011d3	5458	* correctly.
sahilmgandhi	18:6a4db94011d3	5459	*
sahilmgandhi	18:6a4db94011d3	5460	*/
sahilmgandhi	18:6a4db94011d3	5461	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
sahilmgandhi	18:6a4db94011d3	5462	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
sahilmgandhi	18:6a4db94011d3	5463	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
sahilmgandhi	18:6a4db94011d3	5464	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
sahilmgandhi	18:6a4db94011d3	5465	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
sahilmgandhi	18:6a4db94011d3	5466	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	5467	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	5468
sahilmgandhi	18:6a4db94011d3	5469	/----------------------------PLLI2S Configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	5470	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
sahilmgandhi	18:6a4db94011d3	5471	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
sahilmgandhi	18:6a4db94011d3	5472	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
sahilmgandhi	18:6a4db94011d3	5473	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	5474	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	5475
sahilmgandhi	18:6a4db94011d3	5476	/** @brief Macros to enable or disable the PLLI2S.
sahilmgandhi	18:6a4db94011d3	5477	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
sahilmgandhi	18:6a4db94011d3	5478	*/
sahilmgandhi	18:6a4db94011d3	5479	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
sahilmgandhi	18:6a4db94011d3	5480	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
sahilmgandhi	18:6a4db94011d3	5481
sahilmgandhi	18:6a4db94011d3	5482	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
sahilmgandhi	18:6a4db94011d3	5483	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
sahilmgandhi	18:6a4db94011d3	5484	STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	5485	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	5486	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
sahilmgandhi	18:6a4db94011d3	5487	* @note This macro must be used only when the PLLI2S is disabled.
sahilmgandhi	18:6a4db94011d3	5488	* @note PLLI2S clock source is common with the main PLL (configured in
sahilmgandhi	18:6a4db94011d3	5489	* HAL_RCC_ClockConfig() API).
sahilmgandhi	18:6a4db94011d3	5490	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
sahilmgandhi	18:6a4db94011d3	5491	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
sahilmgandhi	18:6a4db94011d3	5492	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
sahilmgandhi	18:6a4db94011d3	5493	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
sahilmgandhi	18:6a4db94011d3	5494	* of 1 MHz to limit PLLI2S jitter.
sahilmgandhi	18:6a4db94011d3	5495	*
sahilmgandhi	18:6a4db94011d3	5496	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
sahilmgandhi	18:6a4db94011d3	5497	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5498	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5499	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
sahilmgandhi	18:6a4db94011d3	5500	*
sahilmgandhi	18:6a4db94011d3	5501	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
sahilmgandhi	18:6a4db94011d3	5502	* This parameter must be a number in the range {2, 4, 6, or 8}.
sahilmgandhi	18:6a4db94011d3	5503	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
sahilmgandhi	18:6a4db94011d3	5504	*
sahilmgandhi	18:6a4db94011d3	5505	* @param __PLLI2SR__: specifies the division factor for I2S clock
sahilmgandhi	18:6a4db94011d3	5506	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5507	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
sahilmgandhi	18:6a4db94011d3	5508	* on the I2S clock frequency.
sahilmgandhi	18:6a4db94011d3	5509	*
sahilmgandhi	18:6a4db94011d3	5510	* @param __PLLI2SQ__: specifies the division factor for SAI clock
sahilmgandhi	18:6a4db94011d3	5511	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	5512	*/
sahilmgandhi	18:6a4db94011d3	5513	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
sahilmgandhi	18:6a4db94011d3	5514	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
sahilmgandhi	18:6a4db94011d3	5515	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
sahilmgandhi	18:6a4db94011d3	5516	((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
sahilmgandhi	18:6a4db94011d3	5517	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
sahilmgandhi	18:6a4db94011d3	5518	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
sahilmgandhi	18:6a4db94011d3	5519	#elif defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	5520	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
sahilmgandhi	18:6a4db94011d3	5521	* @note This macro must be used only when the PLLI2S is disabled.
sahilmgandhi	18:6a4db94011d3	5522	* @note PLLI2S clock source is common with the main PLL (configured in
sahilmgandhi	18:6a4db94011d3	5523	* HAL_RCC_ClockConfig() API).
sahilmgandhi	18:6a4db94011d3	5524	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
sahilmgandhi	18:6a4db94011d3	5525	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
sahilmgandhi	18:6a4db94011d3	5526	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
sahilmgandhi	18:6a4db94011d3	5527	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
sahilmgandhi	18:6a4db94011d3	5528	* of 1 MHz to limit PLLI2S jitter.
sahilmgandhi	18:6a4db94011d3	5529	*
sahilmgandhi	18:6a4db94011d3	5530	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
sahilmgandhi	18:6a4db94011d3	5531	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5532	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5533	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
sahilmgandhi	18:6a4db94011d3	5534	*
sahilmgandhi	18:6a4db94011d3	5535	* @param __PLLI2SR__: specifies the division factor for I2S clock
sahilmgandhi	18:6a4db94011d3	5536	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5537	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
sahilmgandhi	18:6a4db94011d3	5538	* on the I2S clock frequency.
sahilmgandhi	18:6a4db94011d3	5539	*
sahilmgandhi	18:6a4db94011d3	5540	* @param __PLLI2SQ__: specifies the division factor for SAI clock
sahilmgandhi	18:6a4db94011d3	5541	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	5542	*/
sahilmgandhi	18:6a4db94011d3	5543	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
sahilmgandhi	18:6a4db94011d3	5544	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
sahilmgandhi	18:6a4db94011d3	5545	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
sahilmgandhi	18:6a4db94011d3	5546	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
sahilmgandhi	18:6a4db94011d3	5547	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
sahilmgandhi	18:6a4db94011d3	5548	#else
sahilmgandhi	18:6a4db94011d3	5549	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
sahilmgandhi	18:6a4db94011d3	5550	* @note This macro must be used only when the PLLI2S is disabled.
sahilmgandhi	18:6a4db94011d3	5551	* @note PLLI2S clock source is common with the main PLL (configured in
sahilmgandhi	18:6a4db94011d3	5552	* HAL_RCC_ClockConfig() API).
sahilmgandhi	18:6a4db94011d3	5553	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
sahilmgandhi	18:6a4db94011d3	5554	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5555	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5556	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
sahilmgandhi	18:6a4db94011d3	5557	*
sahilmgandhi	18:6a4db94011d3	5558	* @param __PLLI2SR__: specifies the division factor for I2S clock
sahilmgandhi	18:6a4db94011d3	5559	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5560	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
sahilmgandhi	18:6a4db94011d3	5561	* on the I2S clock frequency.
sahilmgandhi	18:6a4db94011d3	5562	*
sahilmgandhi	18:6a4db94011d3	5563	*/
sahilmgandhi	18:6a4db94011d3	5564	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
sahilmgandhi	18:6a4db94011d3	5565	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
sahilmgandhi	18:6a4db94011d3	5566	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
sahilmgandhi	18:6a4db94011d3	5567	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	5568
sahilmgandhi	18:6a4db94011d3	5569	#if defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	5570	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
sahilmgandhi	18:6a4db94011d3	5571	* @note This macro must be used only when the PLLI2S is disabled.
sahilmgandhi	18:6a4db94011d3	5572	* @note This macro must be used only when the PLLI2S is disabled.
sahilmgandhi	18:6a4db94011d3	5573	* @note PLLI2S clock source is common with the main PLL (configured in
sahilmgandhi	18:6a4db94011d3	5574	* HAL_RCC_ClockConfig() API).
sahilmgandhi	18:6a4db94011d3	5575	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
sahilmgandhi	18:6a4db94011d3	5576	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
sahilmgandhi	18:6a4db94011d3	5577	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
sahilmgandhi	18:6a4db94011d3	5578	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
sahilmgandhi	18:6a4db94011d3	5579	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
sahilmgandhi	18:6a4db94011d3	5580	* of 2 MHz to limit PLLI2S jitter.
sahilmgandhi	18:6a4db94011d3	5581	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
sahilmgandhi	18:6a4db94011d3	5582	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5583	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5584	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
sahilmgandhi	18:6a4db94011d3	5585	* @param __PLLI2SR__: specifies the division factor for I2S clock
sahilmgandhi	18:6a4db94011d3	5586	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5587	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
sahilmgandhi	18:6a4db94011d3	5588	* on the I2S clock frequency.
sahilmgandhi	18:6a4db94011d3	5589	*/
sahilmgandhi	18:6a4db94011d3	5590	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
sahilmgandhi	18:6a4db94011d3	5591	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
sahilmgandhi	18:6a4db94011d3	5592	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
sahilmgandhi	18:6a4db94011d3	5593	#endif /* STM32F411xE */
sahilmgandhi	18:6a4db94011d3	5594
sahilmgandhi	18:6a4db94011d3	5595	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	5596	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
sahilmgandhi	18:6a4db94011d3	5597	* @note This macro must be used only when the PLLI2S is disabled.
sahilmgandhi	18:6a4db94011d3	5598	* @note PLLI2S clock source is common with the main PLL (configured in
sahilmgandhi	18:6a4db94011d3	5599	* HAL_RCC_ClockConfig() API)
sahilmgandhi	18:6a4db94011d3	5600	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
sahilmgandhi	18:6a4db94011d3	5601	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5602	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5603	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
sahilmgandhi	18:6a4db94011d3	5604	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5605	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	5606	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
sahilmgandhi	18:6a4db94011d3	5607	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
sahilmgandhi	18:6a4db94011d3	5608	* @param __PLLI2SR__: specifies the division factor for I2S clock
sahilmgandhi	18:6a4db94011d3	5609	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5610	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
sahilmgandhi	18:6a4db94011d3	5611	* on the I2S clock frequency.
sahilmgandhi	18:6a4db94011d3	5612	*/
sahilmgandhi	18:6a4db94011d3	5613	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \|\
sahilmgandhi	18:6a4db94011d3	5614	((__PLLI2SQ__) << 24) \|\
sahilmgandhi	18:6a4db94011d3	5615	((__PLLI2SR__) << 28))
sahilmgandhi	18:6a4db94011d3	5616	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	5617	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	5618
sahilmgandhi	18:6a4db94011d3	5619	/------------------------------ PLLSAI Configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	5620	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	5621	/** @brief Macros to Enable or Disable the PLLISAI.
sahilmgandhi	18:6a4db94011d3	5622	* @note The PLLSAI is only available with STM32F429x/439x Devices.
sahilmgandhi	18:6a4db94011d3	5623	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
sahilmgandhi	18:6a4db94011d3	5624	*/
sahilmgandhi	18:6a4db94011d3	5625	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
sahilmgandhi	18:6a4db94011d3	5626	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
sahilmgandhi	18:6a4db94011d3	5627
sahilmgandhi	18:6a4db94011d3	5628	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	5629	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
sahilmgandhi	18:6a4db94011d3	5630	*
sahilmgandhi	18:6a4db94011d3	5631	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
sahilmgandhi	18:6a4db94011d3	5632	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
sahilmgandhi	18:6a4db94011d3	5633	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
sahilmgandhi	18:6a4db94011d3	5634	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
sahilmgandhi	18:6a4db94011d3	5635	* of 1 MHz to limit PLLI2S jitter.
sahilmgandhi	18:6a4db94011d3	5636	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
sahilmgandhi	18:6a4db94011d3	5637	*
sahilmgandhi	18:6a4db94011d3	5638	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
sahilmgandhi	18:6a4db94011d3	5639	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5640	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5641	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
sahilmgandhi	18:6a4db94011d3	5642	*
sahilmgandhi	18:6a4db94011d3	5643	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
sahilmgandhi	18:6a4db94011d3	5644	* This parameter must be a number in the range {2, 4, 6, or 8}.
sahilmgandhi	18:6a4db94011d3	5645	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
sahilmgandhi	18:6a4db94011d3	5646	*
sahilmgandhi	18:6a4db94011d3	5647	* @param __PLLSAIQ__: specifies the division factor for SAI clock
sahilmgandhi	18:6a4db94011d3	5648	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	5649	*
sahilmgandhi	18:6a4db94011d3	5650	* @param __PLLSAIR__: specifies the division factor for LTDC clock
sahilmgandhi	18:6a4db94011d3	5651	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5652	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
sahilmgandhi	18:6a4db94011d3	5653	*/
sahilmgandhi	18:6a4db94011d3	5654	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
sahilmgandhi	18:6a4db94011d3	5655	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
sahilmgandhi	18:6a4db94011d3	5656	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
sahilmgandhi	18:6a4db94011d3	5657	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
sahilmgandhi	18:6a4db94011d3	5658	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
sahilmgandhi	18:6a4db94011d3	5659	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	5660
sahilmgandhi	18:6a4db94011d3	5661	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	5662	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
sahilmgandhi	18:6a4db94011d3	5663	*
sahilmgandhi	18:6a4db94011d3	5664	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
sahilmgandhi	18:6a4db94011d3	5665	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5666	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5667	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
sahilmgandhi	18:6a4db94011d3	5668	*
sahilmgandhi	18:6a4db94011d3	5669	* @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
sahilmgandhi	18:6a4db94011d3	5670	* This parameter must be a number in the range {2, 4, 6, or 8}.
sahilmgandhi	18:6a4db94011d3	5671	*
sahilmgandhi	18:6a4db94011d3	5672	* @param __PLLSAIQ__: specifies the division factor for SAI clock
sahilmgandhi	18:6a4db94011d3	5673	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	5674	*
sahilmgandhi	18:6a4db94011d3	5675	* @param __PLLSAIR__: specifies the division factor for LTDC clock
sahilmgandhi	18:6a4db94011d3	5676	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5677	*/
sahilmgandhi	18:6a4db94011d3	5678	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
sahilmgandhi	18:6a4db94011d3	5679	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
sahilmgandhi	18:6a4db94011d3	5680	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
sahilmgandhi	18:6a4db94011d3	5681	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
sahilmgandhi	18:6a4db94011d3	5682	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
sahilmgandhi	18:6a4db94011d3	5683	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	5684
sahilmgandhi	18:6a4db94011d3	5685	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
sahilmgandhi	18:6a4db94011d3	5686	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
sahilmgandhi	18:6a4db94011d3	5687	*
sahilmgandhi	18:6a4db94011d3	5688	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
sahilmgandhi	18:6a4db94011d3	5689	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
sahilmgandhi	18:6a4db94011d3	5690	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
sahilmgandhi	18:6a4db94011d3	5691	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
sahilmgandhi	18:6a4db94011d3	5692	*
sahilmgandhi	18:6a4db94011d3	5693	* @param __PLLSAIQ__: specifies the division factor for SAI clock
sahilmgandhi	18:6a4db94011d3	5694	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
sahilmgandhi	18:6a4db94011d3	5695	*
sahilmgandhi	18:6a4db94011d3	5696	* @param __PLLSAIR__: specifies the division factor for LTDC clock
sahilmgandhi	18:6a4db94011d3	5697	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
sahilmgandhi	18:6a4db94011d3	5698	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
sahilmgandhi	18:6a4db94011d3	5699	*/
sahilmgandhi	18:6a4db94011d3	5700	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
sahilmgandhi	18:6a4db94011d3	5701	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
sahilmgandhi	18:6a4db94011d3	5702	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
sahilmgandhi	18:6a4db94011d3	5703	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
sahilmgandhi	18:6a4db94011d3	5704	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
sahilmgandhi	18:6a4db94011d3	5705
sahilmgandhi	18:6a4db94011d3	5706	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	5707	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	5708
sahilmgandhi	18:6a4db94011d3	5709	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
sahilmgandhi	18:6a4db94011d3	5710	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
sahilmgandhi	18:6a4db94011d3	5711	defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	5712	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
sahilmgandhi	18:6a4db94011d3	5713	* @note This function must be called before enabling the PLLI2S.
sahilmgandhi	18:6a4db94011d3	5714	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5715	* This parameter must be a number between 1 and 32.
sahilmgandhi	18:6a4db94011d3	5716	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
sahilmgandhi	18:6a4db94011d3	5717	*/
sahilmgandhi	18:6a4db94011d3	5718	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
sahilmgandhi	18:6a4db94011d3	5719
sahilmgandhi	18:6a4db94011d3	5720	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
sahilmgandhi	18:6a4db94011d3	5721	* @note This function must be called before enabling the PLLSAI.
sahilmgandhi	18:6a4db94011d3	5722	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
sahilmgandhi	18:6a4db94011d3	5723	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
sahilmgandhi	18:6a4db94011d3	5724	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
sahilmgandhi	18:6a4db94011d3	5725	*/
sahilmgandhi	18:6a4db94011d3	5726	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
sahilmgandhi	18:6a4db94011d3	5727	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	5728
sahilmgandhi	18:6a4db94011d3	5729	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	5730	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
sahilmgandhi	18:6a4db94011d3	5731	*
sahilmgandhi	18:6a4db94011d3	5732	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
sahilmgandhi	18:6a4db94011d3	5733	* @note This function must be called before enabling the PLLSAI.
sahilmgandhi	18:6a4db94011d3	5734	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
sahilmgandhi	18:6a4db94011d3	5735	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
sahilmgandhi	18:6a4db94011d3	5736	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
sahilmgandhi	18:6a4db94011d3	5737	*/
sahilmgandhi	18:6a4db94011d3	5738	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
sahilmgandhi	18:6a4db94011d3	5739	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	5740	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	5741
sahilmgandhi	18:6a4db94011d3	5742	/------------------------- Peripheral Clock selection -----------------------/
sahilmgandhi	18:6a4db94011d3	5743	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
sahilmgandhi	18:6a4db94011d3	5744	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
sahilmgandhi	18:6a4db94011d3	5745	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
sahilmgandhi	18:6a4db94011d3	5746	defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	5747	/** @brief Macro to configure the I2S clock source (I2SCLK).
sahilmgandhi	18:6a4db94011d3	5748	* @note This function must be called before enabling the I2S APB clock.
sahilmgandhi	18:6a4db94011d3	5749	* @param __SOURCE__: specifies the I2S clock source.
sahilmgandhi	18:6a4db94011d3	5750	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5751	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
sahilmgandhi	18:6a4db94011d3	5752	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
sahilmgandhi	18:6a4db94011d3	5753	* used as I2S clock source.
sahilmgandhi	18:6a4db94011d3	5754	*/
sahilmgandhi	18:6a4db94011d3	5755	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
sahilmgandhi	18:6a4db94011d3	5756	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	5757
sahilmgandhi	18:6a4db94011d3	5758	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	5759
sahilmgandhi	18:6a4db94011d3	5760	/** @brief Macro to configure SAI1BlockA clock source selection.
sahilmgandhi	18:6a4db94011d3	5761	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
sahilmgandhi	18:6a4db94011d3	5762	* @note This function must be called before enabling PLLSAI, PLLI2S and
sahilmgandhi	18:6a4db94011d3	5763	* the SAI clock.
sahilmgandhi	18:6a4db94011d3	5764	* @param __SOURCE__: specifies the SAI Block A clock source.
sahilmgandhi	18:6a4db94011d3	5765	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5766	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
sahilmgandhi	18:6a4db94011d3	5767	* as SAI1 Block A clock.
sahilmgandhi	18:6a4db94011d3	5768	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
sahilmgandhi	18:6a4db94011d3	5769	* as SAI1 Block A clock.
sahilmgandhi	18:6a4db94011d3	5770	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
sahilmgandhi	18:6a4db94011d3	5771	* used as SAI1 Block A clock.
sahilmgandhi	18:6a4db94011d3	5772	*/
sahilmgandhi	18:6a4db94011d3	5773	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5774
sahilmgandhi	18:6a4db94011d3	5775	/** @brief Macro to configure SAI1BlockB clock source selection.
sahilmgandhi	18:6a4db94011d3	5776	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
sahilmgandhi	18:6a4db94011d3	5777	* @note This function must be called before enabling PLLSAI, PLLI2S and
sahilmgandhi	18:6a4db94011d3	5778	* the SAI clock.
sahilmgandhi	18:6a4db94011d3	5779	* @param __SOURCE__: specifies the SAI Block B clock source.
sahilmgandhi	18:6a4db94011d3	5780	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5781	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
sahilmgandhi	18:6a4db94011d3	5782	* as SAI1 Block B clock.
sahilmgandhi	18:6a4db94011d3	5783	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
sahilmgandhi	18:6a4db94011d3	5784	* as SAI1 Block B clock.
sahilmgandhi	18:6a4db94011d3	5785	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
sahilmgandhi	18:6a4db94011d3	5786	* used as SAI1 Block B clock.
sahilmgandhi	18:6a4db94011d3	5787	*/
sahilmgandhi	18:6a4db94011d3	5788	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5789	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	5790
sahilmgandhi	18:6a4db94011d3	5791	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	5792	/** @brief Macro to configure SAI1 clock source selection.
sahilmgandhi	18:6a4db94011d3	5793	* @note This configuration is only available with STM32F446xx Devices.
sahilmgandhi	18:6a4db94011d3	5794	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
sahilmgandhi	18:6a4db94011d3	5795	* the SAI clock.
sahilmgandhi	18:6a4db94011d3	5796	* @param __SOURCE__: specifies the SAI1 clock source.
sahilmgandhi	18:6a4db94011d3	5797	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5798	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5799	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5800	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5801	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5802	*/
sahilmgandhi	18:6a4db94011d3	5803	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5804
sahilmgandhi	18:6a4db94011d3	5805	/** @brief Macro to Get SAI1 clock source selection.
sahilmgandhi	18:6a4db94011d3	5806	* @note This configuration is only available with STM32F446xx Devices.
sahilmgandhi	18:6a4db94011d3	5807	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5808	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5809	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5810	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5811	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5812	*/
sahilmgandhi	18:6a4db94011d3	5813	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
sahilmgandhi	18:6a4db94011d3	5814
sahilmgandhi	18:6a4db94011d3	5815	/** @brief Macro to configure SAI2 clock source selection.
sahilmgandhi	18:6a4db94011d3	5816	* @note This configuration is only available with STM32F446xx Devices.
sahilmgandhi	18:6a4db94011d3	5817	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
sahilmgandhi	18:6a4db94011d3	5818	* the SAI clock.
sahilmgandhi	18:6a4db94011d3	5819	* @param __SOURCE__: specifies the SAI2 clock source.
sahilmgandhi	18:6a4db94011d3	5820	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5821	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
sahilmgandhi	18:6a4db94011d3	5822	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
sahilmgandhi	18:6a4db94011d3	5823	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
sahilmgandhi	18:6a4db94011d3	5824	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
sahilmgandhi	18:6a4db94011d3	5825	*/
sahilmgandhi	18:6a4db94011d3	5826	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5827
sahilmgandhi	18:6a4db94011d3	5828	/** @brief Macro to Get SAI2 clock source selection.
sahilmgandhi	18:6a4db94011d3	5829	* @note This configuration is only available with STM32F446xx Devices.
sahilmgandhi	18:6a4db94011d3	5830	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5831	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
sahilmgandhi	18:6a4db94011d3	5832	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
sahilmgandhi	18:6a4db94011d3	5833	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
sahilmgandhi	18:6a4db94011d3	5834	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
sahilmgandhi	18:6a4db94011d3	5835	*/
sahilmgandhi	18:6a4db94011d3	5836	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
sahilmgandhi	18:6a4db94011d3	5837
sahilmgandhi	18:6a4db94011d3	5838	/** @brief Macro to configure I2S APB1 clock source selection.
sahilmgandhi	18:6a4db94011d3	5839	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
sahilmgandhi	18:6a4db94011d3	5840	* @param __SOURCE__: specifies the I2S APB1 clock source.
sahilmgandhi	18:6a4db94011d3	5841	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5842	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
sahilmgandhi	18:6a4db94011d3	5843	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5844	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5845	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	5846	*/
sahilmgandhi	18:6a4db94011d3	5847	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5848
sahilmgandhi	18:6a4db94011d3	5849	/** @brief Macro to Get I2S APB1 clock source selection.
sahilmgandhi	18:6a4db94011d3	5850	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5851	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
sahilmgandhi	18:6a4db94011d3	5852	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5853	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5854	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	5855	*/
sahilmgandhi	18:6a4db94011d3	5856	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
sahilmgandhi	18:6a4db94011d3	5857
sahilmgandhi	18:6a4db94011d3	5858	/** @brief Macro to configure I2S APB2 clock source selection.
sahilmgandhi	18:6a4db94011d3	5859	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
sahilmgandhi	18:6a4db94011d3	5860	* @param __SOURCE__: specifies the SAI Block A clock source.
sahilmgandhi	18:6a4db94011d3	5861	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5862	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
sahilmgandhi	18:6a4db94011d3	5863	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5864	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5865	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	5866	*/
sahilmgandhi	18:6a4db94011d3	5867	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5868
sahilmgandhi	18:6a4db94011d3	5869	/** @brief Macro to Get I2S APB2 clock source selection.
sahilmgandhi	18:6a4db94011d3	5870	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5871	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
sahilmgandhi	18:6a4db94011d3	5872	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5873	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
sahilmgandhi	18:6a4db94011d3	5874	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	5875	*/
sahilmgandhi	18:6a4db94011d3	5876	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
sahilmgandhi	18:6a4db94011d3	5877
sahilmgandhi	18:6a4db94011d3	5878	/** @brief Macro to configure the CEC clock.
sahilmgandhi	18:6a4db94011d3	5879	* @param __SOURCE__: specifies the CEC clock source.
sahilmgandhi	18:6a4db94011d3	5880	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5881	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
sahilmgandhi	18:6a4db94011d3	5882	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
sahilmgandhi	18:6a4db94011d3	5883	*/
sahilmgandhi	18:6a4db94011d3	5884	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5885
sahilmgandhi	18:6a4db94011d3	5886	/** @brief Macro to Get the CEC clock.
sahilmgandhi	18:6a4db94011d3	5887	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5888	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
sahilmgandhi	18:6a4db94011d3	5889	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
sahilmgandhi	18:6a4db94011d3	5890	*/
sahilmgandhi	18:6a4db94011d3	5891	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
sahilmgandhi	18:6a4db94011d3	5892
sahilmgandhi	18:6a4db94011d3	5893	/** @brief Macro to configure the FMPI2C1 clock.
sahilmgandhi	18:6a4db94011d3	5894	* @param __SOURCE__: specifies the FMPI2C1 clock source.
sahilmgandhi	18:6a4db94011d3	5895	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5896	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	5897	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	5898	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	5899	*/
sahilmgandhi	18:6a4db94011d3	5900	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5901
sahilmgandhi	18:6a4db94011d3	5902	/** @brief Macro to Get the FMPI2C1 clock.
sahilmgandhi	18:6a4db94011d3	5903	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5904	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	5905	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	5906	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	5907	*/
sahilmgandhi	18:6a4db94011d3	5908	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
sahilmgandhi	18:6a4db94011d3	5909
sahilmgandhi	18:6a4db94011d3	5910	/** @brief Macro to configure the CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5911	* @param __SOURCE__: specifies the CLK48 clock source.
sahilmgandhi	18:6a4db94011d3	5912	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5913	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5914	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5915	*/
sahilmgandhi	18:6a4db94011d3	5916	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5917
sahilmgandhi	18:6a4db94011d3	5918	/** @brief Macro to Get the CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5919	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5920	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5921	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5922	*/
sahilmgandhi	18:6a4db94011d3	5923	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
sahilmgandhi	18:6a4db94011d3	5924
sahilmgandhi	18:6a4db94011d3	5925	/** @brief Macro to configure the SDIO clock.
sahilmgandhi	18:6a4db94011d3	5926	* @param __SOURCE__: specifies the SDIO clock source.
sahilmgandhi	18:6a4db94011d3	5927	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5928	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	5929	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	5930	*/
sahilmgandhi	18:6a4db94011d3	5931	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5932
sahilmgandhi	18:6a4db94011d3	5933	/** @brief Macro to Get the SDIO clock.
sahilmgandhi	18:6a4db94011d3	5934	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5935	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	5936	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	5937	*/
sahilmgandhi	18:6a4db94011d3	5938	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
sahilmgandhi	18:6a4db94011d3	5939
sahilmgandhi	18:6a4db94011d3	5940	/** @brief Macro to configure the SPDIFRX clock.
sahilmgandhi	18:6a4db94011d3	5941	* @param __SOURCE__: specifies the SPDIFRX clock source.
sahilmgandhi	18:6a4db94011d3	5942	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5943	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
sahilmgandhi	18:6a4db94011d3	5944	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
sahilmgandhi	18:6a4db94011d3	5945	*/
sahilmgandhi	18:6a4db94011d3	5946	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5947
sahilmgandhi	18:6a4db94011d3	5948	/** @brief Macro to Get the SPDIFRX clock.
sahilmgandhi	18:6a4db94011d3	5949	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5950	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
sahilmgandhi	18:6a4db94011d3	5951	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
sahilmgandhi	18:6a4db94011d3	5952	*/
sahilmgandhi	18:6a4db94011d3	5953	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
sahilmgandhi	18:6a4db94011d3	5954	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	5955
sahilmgandhi	18:6a4db94011d3	5956	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	5957
sahilmgandhi	18:6a4db94011d3	5958	/** @brief Macro to configure the CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5959	* @param __SOURCE__: specifies the CLK48 clock source.
sahilmgandhi	18:6a4db94011d3	5960	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5961	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5962	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5963	*/
sahilmgandhi	18:6a4db94011d3	5964	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5965
sahilmgandhi	18:6a4db94011d3	5966	/** @brief Macro to Get the CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5967	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5968	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5969	* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	5970	*/
sahilmgandhi	18:6a4db94011d3	5971	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
sahilmgandhi	18:6a4db94011d3	5972
sahilmgandhi	18:6a4db94011d3	5973	/** @brief Macro to configure the SDIO clock.
sahilmgandhi	18:6a4db94011d3	5974	* @param __SOURCE__: specifies the SDIO clock source.
sahilmgandhi	18:6a4db94011d3	5975	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5976	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	5977	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	5978	*/
sahilmgandhi	18:6a4db94011d3	5979	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5980
sahilmgandhi	18:6a4db94011d3	5981	/** @brief Macro to Get the SDIO clock.
sahilmgandhi	18:6a4db94011d3	5982	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5983	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	5984	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	5985	*/
sahilmgandhi	18:6a4db94011d3	5986	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
sahilmgandhi	18:6a4db94011d3	5987
sahilmgandhi	18:6a4db94011d3	5988	/** @brief Macro to configure the DSI clock.
sahilmgandhi	18:6a4db94011d3	5989	* @param __SOURCE__: specifies the DSI clock source.
sahilmgandhi	18:6a4db94011d3	5990	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5991	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
sahilmgandhi	18:6a4db94011d3	5992	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
sahilmgandhi	18:6a4db94011d3	5993	*/
sahilmgandhi	18:6a4db94011d3	5994	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	5995
sahilmgandhi	18:6a4db94011d3	5996	/** @brief Macro to Get the DSI clock.
sahilmgandhi	18:6a4db94011d3	5997	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	5998	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
sahilmgandhi	18:6a4db94011d3	5999	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
sahilmgandhi	18:6a4db94011d3	6000	*/
sahilmgandhi	18:6a4db94011d3	6001	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
sahilmgandhi	18:6a4db94011d3	6002
sahilmgandhi	18:6a4db94011d3	6003	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	6004
sahilmgandhi	18:6a4db94011d3	6005	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6006	/** @brief Macro to configure the DFSDM1 clock.
sahilmgandhi	18:6a4db94011d3	6007	* @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
sahilmgandhi	18:6a4db94011d3	6008	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6009	* @arg RCC_DFSDM1CLKSOURCE_APB2: APB2 clock used as kernel clock.
sahilmgandhi	18:6a4db94011d3	6010	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
sahilmgandhi	18:6a4db94011d3	6011	* @retval None
sahilmgandhi	18:6a4db94011d3	6012	*/
sahilmgandhi	18:6a4db94011d3	6013	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
sahilmgandhi	18:6a4db94011d3	6014
sahilmgandhi	18:6a4db94011d3	6015	/** @brief Macro to get the DFSDM1 clock source.
sahilmgandhi	18:6a4db94011d3	6016	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6017	* @arg RCC_DFSDM1CLKSOURCE_APB2: APB2 clock used as kernel clock.
sahilmgandhi	18:6a4db94011d3	6018	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
sahilmgandhi	18:6a4db94011d3	6019	*/
sahilmgandhi	18:6a4db94011d3	6020	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
sahilmgandhi	18:6a4db94011d3	6021
sahilmgandhi	18:6a4db94011d3	6022	/** @brief Macro to configure DFSDM1 Audio clock source selection.
sahilmgandhi	18:6a4db94011d3	6023	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx Devices.
sahilmgandhi	18:6a4db94011d3	6024	* @param __SOURCE__: specifies the DFSDM1 Audio clock source.
sahilmgandhi	18:6a4db94011d3	6025	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6026	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: CK_I2S_APB1 selected as audio clock
sahilmgandhi	18:6a4db94011d3	6027	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: CK_I2S_APB2 selected as audio clock
sahilmgandhi	18:6a4db94011d3	6028	*/
sahilmgandhi	18:6a4db94011d3	6029	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6030
sahilmgandhi	18:6a4db94011d3	6031	/** @brief Macro to Get DFSDM1 Audio clock source selection.
sahilmgandhi	18:6a4db94011d3	6032	* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx Devices.
sahilmgandhi	18:6a4db94011d3	6033	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6034	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: CK_I2S_APB1 selected as audio clock
sahilmgandhi	18:6a4db94011d3	6035	* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: CK_I2S_APB2 selected as audio clock
sahilmgandhi	18:6a4db94011d3	6036	*/
sahilmgandhi	18:6a4db94011d3	6037	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
sahilmgandhi	18:6a4db94011d3	6038
sahilmgandhi	18:6a4db94011d3	6039	/** @brief Macro to configure I2S APB1 clock source selection.
sahilmgandhi	18:6a4db94011d3	6040	* @param __SOURCE__: specifies the I2S APB1 clock source.
sahilmgandhi	18:6a4db94011d3	6041	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6042	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
sahilmgandhi	18:6a4db94011d3	6043	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
sahilmgandhi	18:6a4db94011d3	6044	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
sahilmgandhi	18:6a4db94011d3	6045	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	6046	*/
sahilmgandhi	18:6a4db94011d3	6047	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6048
sahilmgandhi	18:6a4db94011d3	6049	/** @brief Macro to Get I2S APB1 clock source selection.
sahilmgandhi	18:6a4db94011d3	6050	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6051	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
sahilmgandhi	18:6a4db94011d3	6052	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
sahilmgandhi	18:6a4db94011d3	6053	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
sahilmgandhi	18:6a4db94011d3	6054	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	6055	*/
sahilmgandhi	18:6a4db94011d3	6056	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
sahilmgandhi	18:6a4db94011d3	6057
sahilmgandhi	18:6a4db94011d3	6058	/** @brief Macro to configure I2S APB2 clock source selection.
sahilmgandhi	18:6a4db94011d3	6059	* @param __SOURCE__: specifies the I2S APB2 clock source.
sahilmgandhi	18:6a4db94011d3	6060	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6061	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
sahilmgandhi	18:6a4db94011d3	6062	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
sahilmgandhi	18:6a4db94011d3	6063	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
sahilmgandhi	18:6a4db94011d3	6064	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	6065	*/
sahilmgandhi	18:6a4db94011d3	6066	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6067
sahilmgandhi	18:6a4db94011d3	6068	/** @brief Macro to Get I2S APB2 clock source selection.
sahilmgandhi	18:6a4db94011d3	6069	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6070	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
sahilmgandhi	18:6a4db94011d3	6071	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
sahilmgandhi	18:6a4db94011d3	6072	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
sahilmgandhi	18:6a4db94011d3	6073	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	6074	*/
sahilmgandhi	18:6a4db94011d3	6075	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
sahilmgandhi	18:6a4db94011d3	6076
sahilmgandhi	18:6a4db94011d3	6077	/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
sahilmgandhi	18:6a4db94011d3	6078	* @note This macro must be called before enabling the I2S APB clock.
sahilmgandhi	18:6a4db94011d3	6079	* @param __SOURCE__: specifies the I2S clock source.
sahilmgandhi	18:6a4db94011d3	6080	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6081	* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
sahilmgandhi	18:6a4db94011d3	6082	* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
sahilmgandhi	18:6a4db94011d3	6083	* used as I2S clock source.
sahilmgandhi	18:6a4db94011d3	6084	*/
sahilmgandhi	18:6a4db94011d3	6085	#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
sahilmgandhi	18:6a4db94011d3	6086
sahilmgandhi	18:6a4db94011d3	6087	/** @brief Macro to configure the FMPI2C1 clock.
sahilmgandhi	18:6a4db94011d3	6088	* @param __SOURCE__: specifies the FMPI2C1 clock source.
sahilmgandhi	18:6a4db94011d3	6089	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6090	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6091	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6092	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6093	*/
sahilmgandhi	18:6a4db94011d3	6094	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6095
sahilmgandhi	18:6a4db94011d3	6096	/** @brief Macro to Get the FMPI2C1 clock.
sahilmgandhi	18:6a4db94011d3	6097	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6098	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6099	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6100	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6101	*/
sahilmgandhi	18:6a4db94011d3	6102	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
sahilmgandhi	18:6a4db94011d3	6103
sahilmgandhi	18:6a4db94011d3	6104	/** @brief Macro to configure the CLK48 clock.
sahilmgandhi	18:6a4db94011d3	6105	* @param __SOURCE__: specifies the CLK48 clock source.
sahilmgandhi	18:6a4db94011d3	6106	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6107	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	6108	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	6109	*/
sahilmgandhi	18:6a4db94011d3	6110	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6111
sahilmgandhi	18:6a4db94011d3	6112	/** @brief Macro to Get the CLK48 clock.
sahilmgandhi	18:6a4db94011d3	6113	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6114	* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
sahilmgandhi	18:6a4db94011d3	6115	* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
sahilmgandhi	18:6a4db94011d3	6116	*/
sahilmgandhi	18:6a4db94011d3	6117	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
sahilmgandhi	18:6a4db94011d3	6118
sahilmgandhi	18:6a4db94011d3	6119	/** @brief Macro to configure the SDIO clock.
sahilmgandhi	18:6a4db94011d3	6120	* @param __SOURCE__: specifies the SDIO clock source.
sahilmgandhi	18:6a4db94011d3	6121	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6122	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	6123	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	6124	*/
sahilmgandhi	18:6a4db94011d3	6125	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6126
sahilmgandhi	18:6a4db94011d3	6127	/** @brief Macro to Get the SDIO clock.
sahilmgandhi	18:6a4db94011d3	6128	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6129	* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	6130	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
sahilmgandhi	18:6a4db94011d3	6131	*/
sahilmgandhi	18:6a4db94011d3	6132	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
sahilmgandhi	18:6a4db94011d3	6133
sahilmgandhi	18:6a4db94011d3	6134	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6135
sahilmgandhi	18:6a4db94011d3	6136	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	6137	/** @brief Macro to configure I2S clock source selection.
sahilmgandhi	18:6a4db94011d3	6138	* @param __SOURCE__: specifies the I2S clock source.
sahilmgandhi	18:6a4db94011d3	6139	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6140	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
sahilmgandhi	18:6a4db94011d3	6141	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
sahilmgandhi	18:6a4db94011d3	6142	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
sahilmgandhi	18:6a4db94011d3	6143	*/
sahilmgandhi	18:6a4db94011d3	6144	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6145
sahilmgandhi	18:6a4db94011d3	6146	/** @brief Macro to Get I2S clock source selection.
sahilmgandhi	18:6a4db94011d3	6147	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6148	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
sahilmgandhi	18:6a4db94011d3	6149	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
sahilmgandhi	18:6a4db94011d3	6150	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
sahilmgandhi	18:6a4db94011d3	6151	*/
sahilmgandhi	18:6a4db94011d3	6152	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
sahilmgandhi	18:6a4db94011d3	6153
sahilmgandhi	18:6a4db94011d3	6154	/** @brief Macro to configure the FMPI2C1 clock.
sahilmgandhi	18:6a4db94011d3	6155	* @param __SOURCE__: specifies the FMPI2C1 clock source.
sahilmgandhi	18:6a4db94011d3	6156	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6157	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6158	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6159	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6160	*/
sahilmgandhi	18:6a4db94011d3	6161	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6162
sahilmgandhi	18:6a4db94011d3	6163	/** @brief Macro to Get the FMPI2C1 clock.
sahilmgandhi	18:6a4db94011d3	6164	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6165	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6166	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6167	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
sahilmgandhi	18:6a4db94011d3	6168	*/
sahilmgandhi	18:6a4db94011d3	6169	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
sahilmgandhi	18:6a4db94011d3	6170
sahilmgandhi	18:6a4db94011d3	6171	/** @brief Macro to configure the LPTIM1 clock.
sahilmgandhi	18:6a4db94011d3	6172	* @param __SOURCE__: specifies the LPTIM1 clock source.
sahilmgandhi	18:6a4db94011d3	6173	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6174	* @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
sahilmgandhi	18:6a4db94011d3	6175	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
sahilmgandhi	18:6a4db94011d3	6176	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
sahilmgandhi	18:6a4db94011d3	6177	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
sahilmgandhi	18:6a4db94011d3	6178	*/
sahilmgandhi	18:6a4db94011d3	6179	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
sahilmgandhi	18:6a4db94011d3	6180
sahilmgandhi	18:6a4db94011d3	6181	/** @brief Macro to Get the LPTIM1 clock.
sahilmgandhi	18:6a4db94011d3	6182	* @retval The clock source can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6183	* @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
sahilmgandhi	18:6a4db94011d3	6184	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
sahilmgandhi	18:6a4db94011d3	6185	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
sahilmgandhi	18:6a4db94011d3	6186	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
sahilmgandhi	18:6a4db94011d3	6187	*/
sahilmgandhi	18:6a4db94011d3	6188	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
sahilmgandhi	18:6a4db94011d3	6189	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	6190
sahilmgandhi	18:6a4db94011d3	6191	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
sahilmgandhi	18:6a4db94011d3	6192	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
sahilmgandhi	18:6a4db94011d3	6193	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
sahilmgandhi	18:6a4db94011d3	6194	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
sahilmgandhi	18:6a4db94011d3	6195	defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6196	/** @brief Macro to configure the Timers clocks prescalers
sahilmgandhi	18:6a4db94011d3	6197	* @note This feature is only available with STM32F429x/439x Devices.
sahilmgandhi	18:6a4db94011d3	6198	* @param __PRESC__ : specifies the Timers clocks prescalers selection
sahilmgandhi	18:6a4db94011d3	6199	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	6200	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
sahilmgandhi	18:6a4db94011d3	6201	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
sahilmgandhi	18:6a4db94011d3	6202	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
sahilmgandhi	18:6a4db94011d3	6203	* division by 4 or more.
sahilmgandhi	18:6a4db94011d3	6204	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
sahilmgandhi	18:6a4db94011d3	6205	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
sahilmgandhi	18:6a4db94011d3	6206	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
sahilmgandhi	18:6a4db94011d3	6207	* to division by 8 or more.
sahilmgandhi	18:6a4db94011d3	6208	*/
sahilmgandhi	18:6a4db94011d3	6209	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
sahilmgandhi	18:6a4db94011d3	6210
sahilmgandhi	18:6a4db94011d3	6211	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
sahilmgandhi	18:6a4db94011d3	6212	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6213
sahilmgandhi	18:6a4db94011d3	6214	/----------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	6215
sahilmgandhi	18:6a4db94011d3	6216	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	6217	/** @brief Enable PLLSAI_RDY interrupt.
sahilmgandhi	18:6a4db94011d3	6218	*/
sahilmgandhi	18:6a4db94011d3	6219	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
sahilmgandhi	18:6a4db94011d3	6220
sahilmgandhi	18:6a4db94011d3	6221	/** @brief Disable PLLSAI_RDY interrupt.
sahilmgandhi	18:6a4db94011d3	6222	*/
sahilmgandhi	18:6a4db94011d3	6223	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
sahilmgandhi	18:6a4db94011d3	6224
sahilmgandhi	18:6a4db94011d3	6225	/** @brief Clear the PLLSAI RDY interrupt pending bits.
sahilmgandhi	18:6a4db94011d3	6226	*/
sahilmgandhi	18:6a4db94011d3	6227	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
sahilmgandhi	18:6a4db94011d3	6228
sahilmgandhi	18:6a4db94011d3	6229	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
sahilmgandhi	18:6a4db94011d3	6230	* @retval The new state (TRUE or FALSE).
sahilmgandhi	18:6a4db94011d3	6231	*/
sahilmgandhi	18:6a4db94011d3	6232	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
sahilmgandhi	18:6a4db94011d3	6233
sahilmgandhi	18:6a4db94011d3	6234	/** @brief Check PLLSAI RDY flag is set or not.
sahilmgandhi	18:6a4db94011d3	6235	* @retval The new state (TRUE or FALSE).
sahilmgandhi	18:6a4db94011d3	6236	*/
sahilmgandhi	18:6a4db94011d3	6237	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
sahilmgandhi	18:6a4db94011d3	6238
sahilmgandhi	18:6a4db94011d3	6239	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	6240
sahilmgandhi	18:6a4db94011d3	6241	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	6242	/** @brief Macros to enable or disable the RCC MCO1 feature.
sahilmgandhi	18:6a4db94011d3	6243	*/
sahilmgandhi	18:6a4db94011d3	6244	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
sahilmgandhi	18:6a4db94011d3	6245	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
sahilmgandhi	18:6a4db94011d3	6246
sahilmgandhi	18:6a4db94011d3	6247	/** @brief Macros to enable or disable the RCC MCO2 feature.
sahilmgandhi	18:6a4db94011d3	6248	*/
sahilmgandhi	18:6a4db94011d3	6249	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
sahilmgandhi	18:6a4db94011d3	6250	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
sahilmgandhi	18:6a4db94011d3	6251
sahilmgandhi	18:6a4db94011d3	6252	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	6253
sahilmgandhi	18:6a4db94011d3	6254	/**
sahilmgandhi	18:6a4db94011d3	6255	* @}
sahilmgandhi	18:6a4db94011d3	6256	*/
sahilmgandhi	18:6a4db94011d3	6257
sahilmgandhi	18:6a4db94011d3	6258	/* Exported functions --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	6259	/** @addtogroup RCCEx_Exported_Functions
sahilmgandhi	18:6a4db94011d3	6260	* @{
sahilmgandhi	18:6a4db94011d3	6261	*/
sahilmgandhi	18:6a4db94011d3	6262
sahilmgandhi	18:6a4db94011d3	6263	/** @addtogroup RCCEx_Exported_Functions_Group1
sahilmgandhi	18:6a4db94011d3	6264	* @{
sahilmgandhi	18:6a4db94011d3	6265	*/
sahilmgandhi	18:6a4db94011d3	6266	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
sahilmgandhi	18:6a4db94011d3	6267	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
sahilmgandhi	18:6a4db94011d3	6268
sahilmgandhi	18:6a4db94011d3	6269	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	6270	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
sahilmgandhi	18:6a4db94011d3	6271	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	6272
sahilmgandhi	18:6a4db94011d3	6273	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
sahilmgandhi	18:6a4db94011d3	6274	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
sahilmgandhi	18:6a4db94011d3	6275	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6276	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
sahilmgandhi	18:6a4db94011d3	6277	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6278	/**
sahilmgandhi	18:6a4db94011d3	6279	* @}
sahilmgandhi	18:6a4db94011d3	6280	*/
sahilmgandhi	18:6a4db94011d3	6281
sahilmgandhi	18:6a4db94011d3	6282	/**
sahilmgandhi	18:6a4db94011d3	6283	* @}
sahilmgandhi	18:6a4db94011d3	6284	*/
sahilmgandhi	18:6a4db94011d3	6285	/* Private types -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	6286	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	6287	/* Private constants ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	6288	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
sahilmgandhi	18:6a4db94011d3	6289	* @{
sahilmgandhi	18:6a4db94011d3	6290	*/
sahilmgandhi	18:6a4db94011d3	6291
sahilmgandhi	18:6a4db94011d3	6292	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
sahilmgandhi	18:6a4db94011d3	6293	* @brief RCC registers bit address in the alias region
sahilmgandhi	18:6a4db94011d3	6294	* @{
sahilmgandhi	18:6a4db94011d3	6295	*/
sahilmgandhi	18:6a4db94011d3	6296	/* --- CR Register ---*/
sahilmgandhi	18:6a4db94011d3	6297	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
sahilmgandhi	18:6a4db94011d3	6298	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	6299	/* Alias word address of PLLSAION bit */
sahilmgandhi	18:6a4db94011d3	6300	#define RCC_PLLSAION_BIT_NUMBER 0x1C
sahilmgandhi	18:6a4db94011d3	6301	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
sahilmgandhi	18:6a4db94011d3	6302
sahilmgandhi	18:6a4db94011d3	6303	#define PLLSAI_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
sahilmgandhi	18:6a4db94011d3	6304	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	6305
sahilmgandhi	18:6a4db94011d3	6306	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6307	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6308	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6309	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	6310	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6311	/* Alias word address of PLLI2SON bit */
sahilmgandhi	18:6a4db94011d3	6312	#define RCC_PLLI2SON_BIT_NUMBER 0x1A
sahilmgandhi	18:6a4db94011d3	6313	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
sahilmgandhi	18:6a4db94011d3	6314	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
sahilmgandhi	18:6a4db94011d3	6315	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
sahilmgandhi	18:6a4db94011d3	6316	STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6317
sahilmgandhi	18:6a4db94011d3	6318	/* --- DCKCFGR Register ---*/
sahilmgandhi	18:6a4db94011d3	6319	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
sahilmgandhi	18:6a4db94011d3	6320	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F401xC) \|\|\
sahilmgandhi	18:6a4db94011d3	6321	defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
sahilmgandhi	18:6a4db94011d3	6322	defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\|\
sahilmgandhi	18:6a4db94011d3	6323	defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6324	/* Alias word address of TIMPRE bit */
sahilmgandhi	18:6a4db94011d3	6325	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
sahilmgandhi	18:6a4db94011d3	6326	#define RCC_TIMPRE_BIT_NUMBER 0x18
sahilmgandhi	18:6a4db94011d3	6327	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
sahilmgandhi	18:6a4db94011d3	6328	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F401xC \|\|\
sahilmgandhi	18:6a4db94011d3	6329	STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\|\
sahilmgandhi	18:6a4db94011d3	6330	STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6331
sahilmgandhi	18:6a4db94011d3	6332	/* --- CFGR Register ---*/
sahilmgandhi	18:6a4db94011d3	6333	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
sahilmgandhi	18:6a4db94011d3	6334	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6335	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6336	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6337	defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	6338	/* Alias word address of I2SSRC bit */
sahilmgandhi	18:6a4db94011d3	6339	#define RCC_I2SSRC_BIT_NUMBER 0x17
sahilmgandhi	18:6a4db94011d3	6340	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
sahilmgandhi	18:6a4db94011d3	6341
sahilmgandhi	18:6a4db94011d3	6342	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
sahilmgandhi	18:6a4db94011d3	6343	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
sahilmgandhi	18:6a4db94011d3	6344	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	6345
sahilmgandhi	18:6a4db94011d3	6346	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6347	/* --- PLLI2SCFGR Register ---*/
sahilmgandhi	18:6a4db94011d3	6348	#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U)
sahilmgandhi	18:6a4db94011d3	6349	/* Alias word address of PLLI2SSRC bit */
sahilmgandhi	18:6a4db94011d3	6350	#define RCC_PLLI2SSRC_BIT_NUMBER 0x16
sahilmgandhi	18:6a4db94011d3	6351	#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32) + (RCC_PLLI2SSRC_BIT_NUMBER * 4))
sahilmgandhi	18:6a4db94011d3	6352
sahilmgandhi	18:6a4db94011d3	6353	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)2) /* Timeout value fixed to 2 ms */
sahilmgandhi	18:6a4db94011d3	6354	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6355
sahilmgandhi	18:6a4db94011d3	6356	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	6357	/* Alias word address of MCO1EN bit */
sahilmgandhi	18:6a4db94011d3	6358	#define RCC_MCO1EN_BIT_NUMBER 0x8
sahilmgandhi	18:6a4db94011d3	6359	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
sahilmgandhi	18:6a4db94011d3	6360
sahilmgandhi	18:6a4db94011d3	6361	/* Alias word address of MCO2EN bit */
sahilmgandhi	18:6a4db94011d3	6362	#define RCC_MCO2EN_BIT_NUMBER 0x9
sahilmgandhi	18:6a4db94011d3	6363	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
sahilmgandhi	18:6a4db94011d3	6364	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	6365
sahilmgandhi	18:6a4db94011d3	6366	#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
sahilmgandhi	18:6a4db94011d3	6367	/**
sahilmgandhi	18:6a4db94011d3	6368	* @}
sahilmgandhi	18:6a4db94011d3	6369	*/
sahilmgandhi	18:6a4db94011d3	6370
sahilmgandhi	18:6a4db94011d3	6371	/**
sahilmgandhi	18:6a4db94011d3	6372	* @}
sahilmgandhi	18:6a4db94011d3	6373	*/
sahilmgandhi	18:6a4db94011d3	6374
sahilmgandhi	18:6a4db94011d3	6375	/* Private macros ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	6376	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
sahilmgandhi	18:6a4db94011d3	6377	* @{
sahilmgandhi	18:6a4db94011d3	6378	*/
sahilmgandhi	18:6a4db94011d3	6379	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
sahilmgandhi	18:6a4db94011d3	6380	* @{
sahilmgandhi	18:6a4db94011d3	6381	*/
sahilmgandhi	18:6a4db94011d3	6382	#if defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	6383	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
sahilmgandhi	18:6a4db94011d3	6384	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
sahilmgandhi	18:6a4db94011d3	6385	#else /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\|
sahilmgandhi	18:6a4db94011d3	6386	STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410Tx \|\| STM32F410Cx \|\|
sahilmgandhi	18:6a4db94011d3	6387	STM32F410Rx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Cx \|\| STM32F412Rx \|\|
sahilmgandhi	18:6a4db94011d3	6388	STM32F412Vx \|\| STM32F412Zx */
sahilmgandhi	18:6a4db94011d3	6389	#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
sahilmgandhi	18:6a4db94011d3	6390	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
sahilmgandhi	18:6a4db94011d3	6391	#endif /* STM32F411xE */
sahilmgandhi	18:6a4db94011d3	6392
sahilmgandhi	18:6a4db94011d3	6393	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
sahilmgandhi	18:6a4db94011d3	6394	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
sahilmgandhi	18:6a4db94011d3	6395	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
sahilmgandhi	18:6a4db94011d3	6396
sahilmgandhi	18:6a4db94011d3	6397	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
sahilmgandhi	18:6a4db94011d3	6398	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
sahilmgandhi	18:6a4db94011d3	6399	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
sahilmgandhi	18:6a4db94011d3	6400
sahilmgandhi	18:6a4db94011d3	6401	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	6402	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
sahilmgandhi	18:6a4db94011d3	6403	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
sahilmgandhi	18:6a4db94011d3	6404
sahilmgandhi	18:6a4db94011d3	6405	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	6406	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
sahilmgandhi	18:6a4db94011d3	6407	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	6408
sahilmgandhi	18:6a4db94011d3	6409	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	6410	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
sahilmgandhi	18:6a4db94011d3	6411	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	6412
sahilmgandhi	18:6a4db94011d3	6413	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	6414	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
sahilmgandhi	18:6a4db94011d3	6415	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	6416
sahilmgandhi	18:6a4db94011d3	6417	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6418	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
sahilmgandhi	18:6a4db94011d3	6419	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6420
sahilmgandhi	18:6a4db94011d3	6421	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
sahilmgandhi	18:6a4db94011d3	6422
sahilmgandhi	18:6a4db94011d3	6423	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
sahilmgandhi	18:6a4db94011d3	6424	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	6425	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
sahilmgandhi	18:6a4db94011d3	6426
sahilmgandhi	18:6a4db94011d3	6427	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
sahilmgandhi	18:6a4db94011d3	6428
sahilmgandhi	18:6a4db94011d3	6429	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
sahilmgandhi	18:6a4db94011d3	6430
sahilmgandhi	18:6a4db94011d3	6431	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
sahilmgandhi	18:6a4db94011d3	6432
sahilmgandhi	18:6a4db94011d3	6433	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
sahilmgandhi	18:6a4db94011d3	6434
sahilmgandhi	18:6a4db94011d3	6435	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
sahilmgandhi	18:6a4db94011d3	6436
sahilmgandhi	18:6a4db94011d3	6437	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
sahilmgandhi	18:6a4db94011d3	6438	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
sahilmgandhi	18:6a4db94011d3	6439	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
sahilmgandhi	18:6a4db94011d3	6440	((VALUE) == RCC_PLLSAIDIVR_16))
sahilmgandhi	18:6a4db94011d3	6441	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	6442
sahilmgandhi	18:6a4db94011d3	6443	#if defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	6444	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6445	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63U)
sahilmgandhi	18:6a4db94011d3	6446
sahilmgandhi	18:6a4db94011d3	6447	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
sahilmgandhi	18:6a4db94011d3	6448	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
sahilmgandhi	18:6a4db94011d3	6449	#endif /* STM32F411xE \|\| STM32F446xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6450
sahilmgandhi	18:6a4db94011d3	6451	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	6452	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
sahilmgandhi	18:6a4db94011d3	6453
sahilmgandhi	18:6a4db94011d3	6454	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
sahilmgandhi	18:6a4db94011d3	6455	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
sahilmgandhi	18:6a4db94011d3	6456
sahilmgandhi	18:6a4db94011d3	6457	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
sahilmgandhi	18:6a4db94011d3	6458	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
sahilmgandhi	18:6a4db94011d3	6459	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
sahilmgandhi	18:6a4db94011d3	6460
sahilmgandhi	18:6a4db94011d3	6461	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) \|\|\
sahilmgandhi	18:6a4db94011d3	6462	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
sahilmgandhi	18:6a4db94011d3	6463	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
sahilmgandhi	18:6a4db94011d3	6464	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
sahilmgandhi	18:6a4db94011d3	6465
sahilmgandhi	18:6a4db94011d3	6466	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6467	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
sahilmgandhi	18:6a4db94011d3	6468	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
sahilmgandhi	18:6a4db94011d3	6469	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	6470
sahilmgandhi	18:6a4db94011d3	6471	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	6472	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
sahilmgandhi	18:6a4db94011d3	6473
sahilmgandhi	18:6a4db94011d3	6474	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
sahilmgandhi	18:6a4db94011d3	6475	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
sahilmgandhi	18:6a4db94011d3	6476	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
sahilmgandhi	18:6a4db94011d3	6477	((VALUE) == RCC_PLLI2SP_DIV8))
sahilmgandhi	18:6a4db94011d3	6478
sahilmgandhi	18:6a4db94011d3	6479	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U)
sahilmgandhi	18:6a4db94011d3	6480
sahilmgandhi	18:6a4db94011d3	6481	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
sahilmgandhi	18:6a4db94011d3	6482	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
sahilmgandhi	18:6a4db94011d3	6483	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
sahilmgandhi	18:6a4db94011d3	6484	((VALUE) == RCC_PLLSAIP_DIV8))
sahilmgandhi	18:6a4db94011d3	6485
sahilmgandhi	18:6a4db94011d3	6486	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
sahilmgandhi	18:6a4db94011d3	6487	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
sahilmgandhi	18:6a4db94011d3	6488	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6489	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
sahilmgandhi	18:6a4db94011d3	6490
sahilmgandhi	18:6a4db94011d3	6491	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
sahilmgandhi	18:6a4db94011d3	6492	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
sahilmgandhi	18:6a4db94011d3	6493	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6494	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
sahilmgandhi	18:6a4db94011d3	6495
sahilmgandhi	18:6a4db94011d3	6496	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
sahilmgandhi	18:6a4db94011d3	6497	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
sahilmgandhi	18:6a4db94011d3	6498	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6499	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
sahilmgandhi	18:6a4db94011d3	6500
sahilmgandhi	18:6a4db94011d3	6501	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
sahilmgandhi	18:6a4db94011d3	6502	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
sahilmgandhi	18:6a4db94011d3	6503	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6504	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
sahilmgandhi	18:6a4db94011d3	6505
sahilmgandhi	18:6a4db94011d3	6506	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
sahilmgandhi	18:6a4db94011d3	6507	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
sahilmgandhi	18:6a4db94011d3	6508	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
sahilmgandhi	18:6a4db94011d3	6509
sahilmgandhi	18:6a4db94011d3	6510	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
sahilmgandhi	18:6a4db94011d3	6511	((SOURCE) == RCC_CECCLKSOURCE_LSE))
sahilmgandhi	18:6a4db94011d3	6512
sahilmgandhi	18:6a4db94011d3	6513	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
sahilmgandhi	18:6a4db94011d3	6514	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
sahilmgandhi	18:6a4db94011d3	6515
sahilmgandhi	18:6a4db94011d3	6516	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
sahilmgandhi	18:6a4db94011d3	6517	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
sahilmgandhi	18:6a4db94011d3	6518
sahilmgandhi	18:6a4db94011d3	6519	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6520	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
sahilmgandhi	18:6a4db94011d3	6521	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	6522
sahilmgandhi	18:6a4db94011d3	6523	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	6524	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
sahilmgandhi	18:6a4db94011d3	6525
sahilmgandhi	18:6a4db94011d3	6526	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
sahilmgandhi	18:6a4db94011d3	6527	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
sahilmgandhi	18:6a4db94011d3	6528	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
sahilmgandhi	18:6a4db94011d3	6529	((VALUE) == RCC_PLLSAIP_DIV8))
sahilmgandhi	18:6a4db94011d3	6530
sahilmgandhi	18:6a4db94011d3	6531	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
sahilmgandhi	18:6a4db94011d3	6532	((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
sahilmgandhi	18:6a4db94011d3	6533
sahilmgandhi	18:6a4db94011d3	6534	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
sahilmgandhi	18:6a4db94011d3	6535	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
sahilmgandhi	18:6a4db94011d3	6536
sahilmgandhi	18:6a4db94011d3	6537	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6538	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
sahilmgandhi	18:6a4db94011d3	6539
sahilmgandhi	18:6a4db94011d3	6540	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
sahilmgandhi	18:6a4db94011d3	6541	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
sahilmgandhi	18:6a4db94011d3	6542	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	6543
sahilmgandhi	18:6a4db94011d3	6544	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	6545	#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
sahilmgandhi	18:6a4db94011d3	6546
sahilmgandhi	18:6a4db94011d3	6547	#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) \|\| \
sahilmgandhi	18:6a4db94011d3	6548	((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
sahilmgandhi	18:6a4db94011d3	6549
sahilmgandhi	18:6a4db94011d3	6550	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
sahilmgandhi	18:6a4db94011d3	6551	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
sahilmgandhi	18:6a4db94011d3	6552	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6553	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
sahilmgandhi	18:6a4db94011d3	6554
sahilmgandhi	18:6a4db94011d3	6555	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
sahilmgandhi	18:6a4db94011d3	6556	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
sahilmgandhi	18:6a4db94011d3	6557	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
sahilmgandhi	18:6a4db94011d3	6558	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
sahilmgandhi	18:6a4db94011d3	6559
sahilmgandhi	18:6a4db94011d3	6560	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
sahilmgandhi	18:6a4db94011d3	6561	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
sahilmgandhi	18:6a4db94011d3	6562	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
sahilmgandhi	18:6a4db94011d3	6563
sahilmgandhi	18:6a4db94011d3	6564	#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) \|\|\
sahilmgandhi	18:6a4db94011d3	6565	((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
sahilmgandhi	18:6a4db94011d3	6566
sahilmgandhi	18:6a4db94011d3	6567	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) \|\|\
sahilmgandhi	18:6a4db94011d3	6568	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
sahilmgandhi	18:6a4db94011d3	6569
sahilmgandhi	18:6a4db94011d3	6570	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_APB2) \|\| \
sahilmgandhi	18:6a4db94011d3	6571	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
sahilmgandhi	18:6a4db94011d3	6572
sahilmgandhi	18:6a4db94011d3	6573	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) \|\| \
sahilmgandhi	18:6a4db94011d3	6574	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
sahilmgandhi	18:6a4db94011d3	6575
sahilmgandhi	18:6a4db94011d3	6576	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	6577
sahilmgandhi	18:6a4db94011d3	6578	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6579	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6580	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
sahilmgandhi	18:6a4db94011d3	6581	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	6582	defined(STM32F412Rx)
sahilmgandhi	18:6a4db94011d3	6583
sahilmgandhi	18:6a4db94011d3	6584	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
sahilmgandhi	18:6a4db94011d3	6585	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
sahilmgandhi	18:6a4db94011d3	6586
sahilmgandhi	18:6a4db94011d3	6587	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
sahilmgandhi	18:6a4db94011d3	6588	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| \
sahilmgandhi	18:6a4db94011d3	6589	STM32F412Rx */
sahilmgandhi	18:6a4db94011d3	6590
sahilmgandhi	18:6a4db94011d3	6591	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	6592	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
sahilmgandhi	18:6a4db94011d3	6593	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
sahilmgandhi	18:6a4db94011d3	6594	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	6595	/**
sahilmgandhi	18:6a4db94011d3	6596	* @}
sahilmgandhi	18:6a4db94011d3	6597	*/
sahilmgandhi	18:6a4db94011d3	6598
sahilmgandhi	18:6a4db94011d3	6599	/**
sahilmgandhi	18:6a4db94011d3	6600	* @}
sahilmgandhi	18:6a4db94011d3	6601	*/
sahilmgandhi	18:6a4db94011d3	6602
sahilmgandhi	18:6a4db94011d3	6603	/**
sahilmgandhi	18:6a4db94011d3	6604	* @}
sahilmgandhi	18:6a4db94011d3	6605	*/
sahilmgandhi	18:6a4db94011d3	6606
sahilmgandhi	18:6a4db94011d3	6607	/**
sahilmgandhi	18:6a4db94011d3	6608	* @}
sahilmgandhi	18:6a4db94011d3	6609	*/
sahilmgandhi	18:6a4db94011d3	6610	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	6611	}
sahilmgandhi	18:6a4db94011d3	6612	#endif
sahilmgandhi	18:6a4db94011d3	6613
sahilmgandhi	18:6a4db94011d3	6614	#endif /* __STM32F4xx_HAL_RCC_EX_H */
sahilmgandhi	18:6a4db94011d3	6615
sahilmgandhi	18:6a4db94011d3	6616	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Build repository

Repository details

Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h@46:b156ef445742, 2017-06-03 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning