MouseCode - Mouse code for the MacroRat

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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f4xx_hal_rcc_ex.c
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.5.0
sahilmgandhi	18:6a4db94011d3	6	* @date 06-May-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief Extension RCC HAL module driver.
sahilmgandhi	18:6a4db94011d3	8	* This file provides firmware functions to manage the following
sahilmgandhi	18:6a4db94011d3	9	* functionalities RCC extension peripheral:
sahilmgandhi	18:6a4db94011d3	10	* + Extended Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	11	*
sahilmgandhi	18:6a4db94011d3	12	******************************************************************************
sahilmgandhi	18:6a4db94011d3	13	* @attention
sahilmgandhi	18:6a4db94011d3	14	*
sahilmgandhi	18:6a4db94011d3	15	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	16	*
sahilmgandhi	18:6a4db94011d3	17	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	18	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	19	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	20	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	21	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	22	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	23	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	24	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	25	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	26	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	27	*
sahilmgandhi	18:6a4db94011d3	28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	31	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	32	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	34	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	35	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	36	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	37	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	38	*
sahilmgandhi	18:6a4db94011d3	39	******************************************************************************
sahilmgandhi	18:6a4db94011d3	40	*/
sahilmgandhi	18:6a4db94011d3	41
sahilmgandhi	18:6a4db94011d3	42	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	43	#include "stm32f4xx_hal.h"
sahilmgandhi	18:6a4db94011d3	44
sahilmgandhi	18:6a4db94011d3	45	/** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	46	* @{
sahilmgandhi	18:6a4db94011d3	47	*/
sahilmgandhi	18:6a4db94011d3	48
sahilmgandhi	18:6a4db94011d3	49	/** @defgroup RCCEx RCCEx
sahilmgandhi	18:6a4db94011d3	50	* @brief RCCEx HAL module driver
sahilmgandhi	18:6a4db94011d3	51	* @{
sahilmgandhi	18:6a4db94011d3	52	*/
sahilmgandhi	18:6a4db94011d3	53
sahilmgandhi	18:6a4db94011d3	54	#ifdef HAL_RCC_MODULE_ENABLED
sahilmgandhi	18:6a4db94011d3	55
sahilmgandhi	18:6a4db94011d3	56	/* Private typedef -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	57	/* Private define ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	58	/** @addtogroup RCCEx_Private_Constants
sahilmgandhi	18:6a4db94011d3	59	* @{
sahilmgandhi	18:6a4db94011d3	60	*/
sahilmgandhi	18:6a4db94011d3	61	/**
sahilmgandhi	18:6a4db94011d3	62	* @}
sahilmgandhi	18:6a4db94011d3	63	*/
sahilmgandhi	18:6a4db94011d3	64	/* Private macro -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	65	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	66	/* Private function prototypes -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	67	/* Private functions ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	68	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
sahilmgandhi	18:6a4db94011d3	69	* @{
sahilmgandhi	18:6a4db94011d3	70	*/
sahilmgandhi	18:6a4db94011d3	71
sahilmgandhi	18:6a4db94011d3	72	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	73	* @brief Extended Peripheral Control functions
sahilmgandhi	18:6a4db94011d3	74	*
sahilmgandhi	18:6a4db94011d3	75	@verbatim
sahilmgandhi	18:6a4db94011d3	76	===============================================================================
sahilmgandhi	18:6a4db94011d3	77	##### Extended Peripheral Control functions #####
sahilmgandhi	18:6a4db94011d3	78	===============================================================================
sahilmgandhi	18:6a4db94011d3	79	[..]
sahilmgandhi	18:6a4db94011d3	80	This subsection provides a set of functions allowing to control the RCC Clocks
sahilmgandhi	18:6a4db94011d3	81	frequencies.
sahilmgandhi	18:6a4db94011d3	82	[..]
sahilmgandhi	18:6a4db94011d3	83	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
sahilmgandhi	18:6a4db94011d3	84	select the RTC clock source; in this case the Backup domain will be reset in
sahilmgandhi	18:6a4db94011d3	85	order to modify the RTC Clock source, as consequence RTC registers (including
sahilmgandhi	18:6a4db94011d3	86	the backup registers) and RCC_BDCR register are set to their reset values.
sahilmgandhi	18:6a4db94011d3	87
sahilmgandhi	18:6a4db94011d3	88	@endverbatim
sahilmgandhi	18:6a4db94011d3	89	* @{
sahilmgandhi	18:6a4db94011d3	90	*/
sahilmgandhi	18:6a4db94011d3	91	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
sahilmgandhi	18:6a4db94011d3	92	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
sahilmgandhi	18:6a4db94011d3	93	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
sahilmgandhi	18:6a4db94011d3	94	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
sahilmgandhi	18:6a4db94011d3	95	defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	96	/**
sahilmgandhi	18:6a4db94011d3	97	* @brief Resets the RCC clock configuration to the default reset state.
sahilmgandhi	18:6a4db94011d3	98	* @note The default reset state of the clock configuration is given below:
sahilmgandhi	18:6a4db94011d3	99	* - HSI ON and used as system clock source
sahilmgandhi	18:6a4db94011d3	100	* - HSE, PLL and PLLI2S OFF
sahilmgandhi	18:6a4db94011d3	101	* - AHB, APB1 and APB2 prescaler set to 1.
sahilmgandhi	18:6a4db94011d3	102	* - CSS, MCO1 and MCO2 OFF
sahilmgandhi	18:6a4db94011d3	103	* - All interrupts disabled
sahilmgandhi	18:6a4db94011d3	104	* @note This function doesn't modify the configuration of the
sahilmgandhi	18:6a4db94011d3	105	* - Peripheral clocks
sahilmgandhi	18:6a4db94011d3	106	* - LSI, LSE and RTC clocks
sahilmgandhi	18:6a4db94011d3	107	* @retval None
sahilmgandhi	18:6a4db94011d3	108	*/
sahilmgandhi	18:6a4db94011d3	109	void HAL_RCC_DeInit(void)
sahilmgandhi	18:6a4db94011d3	110	{
sahilmgandhi	18:6a4db94011d3	111	/* Set HSION bit */
sahilmgandhi	18:6a4db94011d3	112	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
sahilmgandhi	18:6a4db94011d3	113
sahilmgandhi	18:6a4db94011d3	114	/* Reset CFGR register */
sahilmgandhi	18:6a4db94011d3	115	CLEAR_REG(RCC->CFGR);
sahilmgandhi	18:6a4db94011d3	116
sahilmgandhi	18:6a4db94011d3	117	/* Reset HSEON, CSSON, PLLON, PLLI2S */
sahilmgandhi	18:6a4db94011d3	118	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON \| RCC_CR_PLLON\| RCC_CR_PLLI2SON);
sahilmgandhi	18:6a4db94011d3	119
sahilmgandhi	18:6a4db94011d3	120	/* Reset PLLCFGR register */
sahilmgandhi	18:6a4db94011d3	121	CLEAR_REG(RCC->PLLCFGR);
sahilmgandhi	18:6a4db94011d3	122	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2);
sahilmgandhi	18:6a4db94011d3	123
sahilmgandhi	18:6a4db94011d3	124	/* Reset PLLI2SCFGR register */
sahilmgandhi	18:6a4db94011d3	125	CLEAR_REG(RCC->PLLI2SCFGR);
sahilmgandhi	18:6a4db94011d3	126	SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 \| RCC_PLLI2SCFGR_PLLI2SN_7 \| RCC_PLLI2SCFGR_PLLI2SR_1);
sahilmgandhi	18:6a4db94011d3	127
sahilmgandhi	18:6a4db94011d3	128	/* Reset HSEBYP bit */
sahilmgandhi	18:6a4db94011d3	129	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
sahilmgandhi	18:6a4db94011d3	130
sahilmgandhi	18:6a4db94011d3	131	/* Disable all interrupts */
sahilmgandhi	18:6a4db94011d3	132	CLEAR_REG(RCC->CIR);
sahilmgandhi	18:6a4db94011d3	133
sahilmgandhi	18:6a4db94011d3	134	/* Update the SystemCoreClock global variable */
sahilmgandhi	18:6a4db94011d3	135	SystemCoreClock = HSI_VALUE;
sahilmgandhi	18:6a4db94011d3	136	}
sahilmgandhi	18:6a4db94011d3	137	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
sahilmgandhi	18:6a4db94011d3	138	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
sahilmgandhi	18:6a4db94011d3	139	STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	140
sahilmgandhi	18:6a4db94011d3	141	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	142	/**
sahilmgandhi	18:6a4db94011d3	143	* @brief Resets the RCC clock configuration to the default reset state.
sahilmgandhi	18:6a4db94011d3	144	* @note The default reset state of the clock configuration is given below:
sahilmgandhi	18:6a4db94011d3	145	* - HSI ON and used as system clock source
sahilmgandhi	18:6a4db94011d3	146	* - HSE and PLL OFF
sahilmgandhi	18:6a4db94011d3	147	* - AHB, APB1 and APB2 prescaler set to 1.
sahilmgandhi	18:6a4db94011d3	148	* - CSS, MCO1 and MCO2 OFF
sahilmgandhi	18:6a4db94011d3	149	* - All interrupts disabled
sahilmgandhi	18:6a4db94011d3	150	* @note This function doesn't modify the configuration of the
sahilmgandhi	18:6a4db94011d3	151	* - Peripheral clocks
sahilmgandhi	18:6a4db94011d3	152	* - LSI, LSE and RTC clocks
sahilmgandhi	18:6a4db94011d3	153	* @retval None
sahilmgandhi	18:6a4db94011d3	154	*/
sahilmgandhi	18:6a4db94011d3	155	void HAL_RCC_DeInit(void)
sahilmgandhi	18:6a4db94011d3	156	{
sahilmgandhi	18:6a4db94011d3	157	/* Set HSION bit */
sahilmgandhi	18:6a4db94011d3	158	SET_BIT(RCC->CR, RCC_CR_HSION \| RCC_CR_HSITRIM_4);
sahilmgandhi	18:6a4db94011d3	159
sahilmgandhi	18:6a4db94011d3	160	/* Reset CFGR register */
sahilmgandhi	18:6a4db94011d3	161	CLEAR_REG(RCC->CFGR);
sahilmgandhi	18:6a4db94011d3	162
sahilmgandhi	18:6a4db94011d3	163	/* Reset HSEON, CSSON, PLLON */
sahilmgandhi	18:6a4db94011d3	164	CLEAR_BIT(RCC->CR, RCC_CR_HSEON \| RCC_CR_CSSON \| RCC_CR_PLLON);
sahilmgandhi	18:6a4db94011d3	165
sahilmgandhi	18:6a4db94011d3	166	/* Reset PLLCFGR register */
sahilmgandhi	18:6a4db94011d3	167	CLEAR_REG(RCC->PLLCFGR);
sahilmgandhi	18:6a4db94011d3	168	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_1 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLN_6 \| RCC_PLLCFGR_PLLN_7 \| RCC_PLLCFGR_PLLQ_2);
sahilmgandhi	18:6a4db94011d3	169
sahilmgandhi	18:6a4db94011d3	170	/* Reset HSEBYP bit */
sahilmgandhi	18:6a4db94011d3	171	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
sahilmgandhi	18:6a4db94011d3	172
sahilmgandhi	18:6a4db94011d3	173	/* Disable all interrupts */
sahilmgandhi	18:6a4db94011d3	174	CLEAR_REG(RCC->CIR);
sahilmgandhi	18:6a4db94011d3	175
sahilmgandhi	18:6a4db94011d3	176	/* Update the SystemCoreClock global variable */
sahilmgandhi	18:6a4db94011d3	177	SystemCoreClock = HSI_VALUE;
sahilmgandhi	18:6a4db94011d3	178	}
sahilmgandhi	18:6a4db94011d3	179	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	180
sahilmgandhi	18:6a4db94011d3	181	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	182	/**
sahilmgandhi	18:6a4db94011d3	183	* @brief Initializes the RCC extended peripherals clocks according to the specified
sahilmgandhi	18:6a4db94011d3	184	* parameters in the RCC_PeriphCLKInitTypeDef.
sahilmgandhi	18:6a4db94011d3	185	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	186	* contains the configuration information for the Extended Peripherals
sahilmgandhi	18:6a4db94011d3	187	* clocks(I2S, SAI, LTDC RTC and TIM).
sahilmgandhi	18:6a4db94011d3	188	*
sahilmgandhi	18:6a4db94011d3	189	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
sahilmgandhi	18:6a4db94011d3	190	* the RTC clock source; in this case the Backup domain will be reset in
sahilmgandhi	18:6a4db94011d3	191	* order to modify the RTC Clock source, as consequence RTC registers (including
sahilmgandhi	18:6a4db94011d3	192	* the backup registers) and RCC_BDCR register are set to their reset values.
sahilmgandhi	18:6a4db94011d3	193	*
sahilmgandhi	18:6a4db94011d3	194	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	195	*/
sahilmgandhi	18:6a4db94011d3	196	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	197	{
sahilmgandhi	18:6a4db94011d3	198	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	199	uint32_t tmpreg1 = 0U;
sahilmgandhi	18:6a4db94011d3	200	uint32_t plli2sp = 0U;
sahilmgandhi	18:6a4db94011d3	201	uint32_t plli2sq = 0U;
sahilmgandhi	18:6a4db94011d3	202	uint32_t plli2sr = 0U;
sahilmgandhi	18:6a4db94011d3	203	uint32_t pllsaip = 0U;
sahilmgandhi	18:6a4db94011d3	204	uint32_t pllsaiq = 0U;
sahilmgandhi	18:6a4db94011d3	205	uint32_t plli2sused = 0U;
sahilmgandhi	18:6a4db94011d3	206	uint32_t pllsaiused = 0U;
sahilmgandhi	18:6a4db94011d3	207
sahilmgandhi	18:6a4db94011d3	208	/* Check the peripheral clock selection parameters */
sahilmgandhi	18:6a4db94011d3	209	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
sahilmgandhi	18:6a4db94011d3	210
sahilmgandhi	18:6a4db94011d3	211	/------------------------ I2S APB1 configuration --------------------------/
sahilmgandhi	18:6a4db94011d3	212	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
sahilmgandhi	18:6a4db94011d3	213	{
sahilmgandhi	18:6a4db94011d3	214	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	215	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
sahilmgandhi	18:6a4db94011d3	216
sahilmgandhi	18:6a4db94011d3	217	/* Configure I2S Clock source */
sahilmgandhi	18:6a4db94011d3	218	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
sahilmgandhi	18:6a4db94011d3	219	/* Enable the PLLI2S when it's used as clock source for I2S */
sahilmgandhi	18:6a4db94011d3	220	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
sahilmgandhi	18:6a4db94011d3	221	{
sahilmgandhi	18:6a4db94011d3	222	plli2sused = 1U;
sahilmgandhi	18:6a4db94011d3	223	}
sahilmgandhi	18:6a4db94011d3	224	}
sahilmgandhi	18:6a4db94011d3	225	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	226
sahilmgandhi	18:6a4db94011d3	227	/---------------------------- I2S APB2 configuration ----------------------/
sahilmgandhi	18:6a4db94011d3	228	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
sahilmgandhi	18:6a4db94011d3	229	{
sahilmgandhi	18:6a4db94011d3	230	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	231	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
sahilmgandhi	18:6a4db94011d3	232
sahilmgandhi	18:6a4db94011d3	233	/* Configure I2S Clock source */
sahilmgandhi	18:6a4db94011d3	234	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
sahilmgandhi	18:6a4db94011d3	235	/* Enable the PLLI2S when it's used as clock source for I2S */
sahilmgandhi	18:6a4db94011d3	236	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
sahilmgandhi	18:6a4db94011d3	237	{
sahilmgandhi	18:6a4db94011d3	238	plli2sused = 1U;
sahilmgandhi	18:6a4db94011d3	239	}
sahilmgandhi	18:6a4db94011d3	240	}
sahilmgandhi	18:6a4db94011d3	241	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	242
sahilmgandhi	18:6a4db94011d3	243	/--------------------------- SAI1 configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	244	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
sahilmgandhi	18:6a4db94011d3	245	{
sahilmgandhi	18:6a4db94011d3	246	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	247	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
sahilmgandhi	18:6a4db94011d3	248
sahilmgandhi	18:6a4db94011d3	249	/* Configure SAI1 Clock source */
sahilmgandhi	18:6a4db94011d3	250	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
sahilmgandhi	18:6a4db94011d3	251	/* Enable the PLLI2S when it's used as clock source for SAI */
sahilmgandhi	18:6a4db94011d3	252	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
sahilmgandhi	18:6a4db94011d3	253	{
sahilmgandhi	18:6a4db94011d3	254	plli2sused = 1U;
sahilmgandhi	18:6a4db94011d3	255	}
sahilmgandhi	18:6a4db94011d3	256	/* Enable the PLLSAI when it's used as clock source for SAI */
sahilmgandhi	18:6a4db94011d3	257	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
sahilmgandhi	18:6a4db94011d3	258	{
sahilmgandhi	18:6a4db94011d3	259	pllsaiused = 1U;
sahilmgandhi	18:6a4db94011d3	260	}
sahilmgandhi	18:6a4db94011d3	261	}
sahilmgandhi	18:6a4db94011d3	262	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	263
sahilmgandhi	18:6a4db94011d3	264	/-------------------------- SAI2 configuration ----------------------------/
sahilmgandhi	18:6a4db94011d3	265	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
sahilmgandhi	18:6a4db94011d3	266	{
sahilmgandhi	18:6a4db94011d3	267	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	268	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
sahilmgandhi	18:6a4db94011d3	269
sahilmgandhi	18:6a4db94011d3	270	/* Configure SAI2 Clock source */
sahilmgandhi	18:6a4db94011d3	271	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
sahilmgandhi	18:6a4db94011d3	272
sahilmgandhi	18:6a4db94011d3	273	/* Enable the PLLI2S when it's used as clock source for SAI */
sahilmgandhi	18:6a4db94011d3	274	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
sahilmgandhi	18:6a4db94011d3	275	{
sahilmgandhi	18:6a4db94011d3	276	plli2sused = 1U;
sahilmgandhi	18:6a4db94011d3	277	}
sahilmgandhi	18:6a4db94011d3	278	/* Enable the PLLSAI when it's used as clock source for SAI */
sahilmgandhi	18:6a4db94011d3	279	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
sahilmgandhi	18:6a4db94011d3	280	{
sahilmgandhi	18:6a4db94011d3	281	pllsaiused = 1U;
sahilmgandhi	18:6a4db94011d3	282	}
sahilmgandhi	18:6a4db94011d3	283	}
sahilmgandhi	18:6a4db94011d3	284	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	285
sahilmgandhi	18:6a4db94011d3	286	/----------------------------- RTC configuration --------------------------/
sahilmgandhi	18:6a4db94011d3	287	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
sahilmgandhi	18:6a4db94011d3	288	{
sahilmgandhi	18:6a4db94011d3	289	/* Check for RTC Parameters used to output RTCCLK */
sahilmgandhi	18:6a4db94011d3	290	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
sahilmgandhi	18:6a4db94011d3	291
sahilmgandhi	18:6a4db94011d3	292	/* Enable Power Clock*/
sahilmgandhi	18:6a4db94011d3	293	__HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	294
sahilmgandhi	18:6a4db94011d3	295	/* Enable write access to Backup domain */
sahilmgandhi	18:6a4db94011d3	296	PWR->CR \|= PWR_CR_DBP;
sahilmgandhi	18:6a4db94011d3	297
sahilmgandhi	18:6a4db94011d3	298	/* Get tick */
sahilmgandhi	18:6a4db94011d3	299	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	300
sahilmgandhi	18:6a4db94011d3	301	while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi	18:6a4db94011d3	302	{
sahilmgandhi	18:6a4db94011d3	303	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	304	{
sahilmgandhi	18:6a4db94011d3	305	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	306	}
sahilmgandhi	18:6a4db94011d3	307	}
sahilmgandhi	18:6a4db94011d3	308	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
sahilmgandhi	18:6a4db94011d3	309	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
sahilmgandhi	18:6a4db94011d3	310	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
sahilmgandhi	18:6a4db94011d3	311	{
sahilmgandhi	18:6a4db94011d3	312	/* Store the content of BDCR register before the reset of Backup Domain */
sahilmgandhi	18:6a4db94011d3	313	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	314	/* RTC Clock selection can be changed only if the Backup Domain is reset */
sahilmgandhi	18:6a4db94011d3	315	__HAL_RCC_BACKUPRESET_FORCE();
sahilmgandhi	18:6a4db94011d3	316	__HAL_RCC_BACKUPRESET_RELEASE();
sahilmgandhi	18:6a4db94011d3	317	/* Restore the Content of BDCR register */
sahilmgandhi	18:6a4db94011d3	318	RCC->BDCR = tmpreg1;
sahilmgandhi	18:6a4db94011d3	319
sahilmgandhi	18:6a4db94011d3	320	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
sahilmgandhi	18:6a4db94011d3	321	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
sahilmgandhi	18:6a4db94011d3	322	{
sahilmgandhi	18:6a4db94011d3	323	/* Get tick */
sahilmgandhi	18:6a4db94011d3	324	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	325
sahilmgandhi	18:6a4db94011d3	326	/* Wait till LSE is ready */
sahilmgandhi	18:6a4db94011d3	327	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi	18:6a4db94011d3	328	{
sahilmgandhi	18:6a4db94011d3	329	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	330	{
sahilmgandhi	18:6a4db94011d3	331	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	332	}
sahilmgandhi	18:6a4db94011d3	333	}
sahilmgandhi	18:6a4db94011d3	334	}
sahilmgandhi	18:6a4db94011d3	335	}
sahilmgandhi	18:6a4db94011d3	336	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
sahilmgandhi	18:6a4db94011d3	337	}
sahilmgandhi	18:6a4db94011d3	338	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	339
sahilmgandhi	18:6a4db94011d3	340	/---------------------------- TIM configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	341	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
sahilmgandhi	18:6a4db94011d3	342	{
sahilmgandhi	18:6a4db94011d3	343	/* Configure Timer Prescaler */
sahilmgandhi	18:6a4db94011d3	344	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
sahilmgandhi	18:6a4db94011d3	345	}
sahilmgandhi	18:6a4db94011d3	346	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	347
sahilmgandhi	18:6a4db94011d3	348	/---------------------------- FMPI2C1 Configuration -----------------------/
sahilmgandhi	18:6a4db94011d3	349	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
sahilmgandhi	18:6a4db94011d3	350	{
sahilmgandhi	18:6a4db94011d3	351	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	352	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
sahilmgandhi	18:6a4db94011d3	353
sahilmgandhi	18:6a4db94011d3	354	/* Configure the FMPI2C1 clock source */
sahilmgandhi	18:6a4db94011d3	355	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
sahilmgandhi	18:6a4db94011d3	356	}
sahilmgandhi	18:6a4db94011d3	357	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	358
sahilmgandhi	18:6a4db94011d3	359	/------------------------------ CEC Configuration -------------------------/
sahilmgandhi	18:6a4db94011d3	360	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
sahilmgandhi	18:6a4db94011d3	361	{
sahilmgandhi	18:6a4db94011d3	362	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	363	assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
sahilmgandhi	18:6a4db94011d3	364
sahilmgandhi	18:6a4db94011d3	365	/* Configure the CEC clock source */
sahilmgandhi	18:6a4db94011d3	366	__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
sahilmgandhi	18:6a4db94011d3	367	}
sahilmgandhi	18:6a4db94011d3	368	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	369
sahilmgandhi	18:6a4db94011d3	370	/----------------------------- CLK48 Configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	371	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
sahilmgandhi	18:6a4db94011d3	372	{
sahilmgandhi	18:6a4db94011d3	373	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	374	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
sahilmgandhi	18:6a4db94011d3	375
sahilmgandhi	18:6a4db94011d3	376	/* Configure the CLK48 clock source */
sahilmgandhi	18:6a4db94011d3	377	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
sahilmgandhi	18:6a4db94011d3	378
sahilmgandhi	18:6a4db94011d3	379	/* Enable the PLLSAI when it's used as clock source for CLK48 */
sahilmgandhi	18:6a4db94011d3	380	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
sahilmgandhi	18:6a4db94011d3	381	{
sahilmgandhi	18:6a4db94011d3	382	pllsaiused = 1U;
sahilmgandhi	18:6a4db94011d3	383	}
sahilmgandhi	18:6a4db94011d3	384	}
sahilmgandhi	18:6a4db94011d3	385	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	386
sahilmgandhi	18:6a4db94011d3	387	/----------------------------- SDIO Configuration -------------------------/
sahilmgandhi	18:6a4db94011d3	388	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
sahilmgandhi	18:6a4db94011d3	389	{
sahilmgandhi	18:6a4db94011d3	390	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	391	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
sahilmgandhi	18:6a4db94011d3	392
sahilmgandhi	18:6a4db94011d3	393	/* Configure the SDIO clock source */
sahilmgandhi	18:6a4db94011d3	394	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
sahilmgandhi	18:6a4db94011d3	395	}
sahilmgandhi	18:6a4db94011d3	396	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	397
sahilmgandhi	18:6a4db94011d3	398	/------------------------------ SPDIFRX Configuration ---------------------/
sahilmgandhi	18:6a4db94011d3	399	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
sahilmgandhi	18:6a4db94011d3	400	{
sahilmgandhi	18:6a4db94011d3	401	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	402	assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
sahilmgandhi	18:6a4db94011d3	403
sahilmgandhi	18:6a4db94011d3	404	/* Configure the SPDIFRX clock source */
sahilmgandhi	18:6a4db94011d3	405	__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
sahilmgandhi	18:6a4db94011d3	406	/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
sahilmgandhi	18:6a4db94011d3	407	if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
sahilmgandhi	18:6a4db94011d3	408	{
sahilmgandhi	18:6a4db94011d3	409	plli2sused = 1U;
sahilmgandhi	18:6a4db94011d3	410	}
sahilmgandhi	18:6a4db94011d3	411	}
sahilmgandhi	18:6a4db94011d3	412	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	413
sahilmgandhi	18:6a4db94011d3	414	/---------------------------- PLLI2S Configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	415	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
sahilmgandhi	18:6a4db94011d3	416	I2S on APB2 or SPDIFRX */
sahilmgandhi	18:6a4db94011d3	417	if((plli2sused == 1U) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
sahilmgandhi	18:6a4db94011d3	418	{
sahilmgandhi	18:6a4db94011d3	419	/* Disable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	420	__HAL_RCC_PLLI2S_DISABLE();
sahilmgandhi	18:6a4db94011d3	421	/* Get tick */
sahilmgandhi	18:6a4db94011d3	422	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	423	/* Wait till PLLI2S is disabled */
sahilmgandhi	18:6a4db94011d3	424	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	425	{
sahilmgandhi	18:6a4db94011d3	426	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	427	{
sahilmgandhi	18:6a4db94011d3	428	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	429	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	430	}
sahilmgandhi	18:6a4db94011d3	431	}
sahilmgandhi	18:6a4db94011d3	432
sahilmgandhi	18:6a4db94011d3	433	/* check for common PLLI2S Parameters */
sahilmgandhi	18:6a4db94011d3	434	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
sahilmgandhi	18:6a4db94011d3	435	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
sahilmgandhi	18:6a4db94011d3	436
sahilmgandhi	18:6a4db94011d3	437	/------ In Case of PLLI2S is selected as source clock for I2S -----------/
sahilmgandhi	18:6a4db94011d3	438	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
sahilmgandhi	18:6a4db94011d3	439	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
sahilmgandhi	18:6a4db94011d3	440	{
sahilmgandhi	18:6a4db94011d3	441	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	442	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
sahilmgandhi	18:6a4db94011d3	443
sahilmgandhi	18:6a4db94011d3	444	/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
sahilmgandhi	18:6a4db94011d3	445	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
sahilmgandhi	18:6a4db94011d3	446	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	447	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	448	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
sahilmgandhi	18:6a4db94011d3	449	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
sahilmgandhi	18:6a4db94011d3	450	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	451	}
sahilmgandhi	18:6a4db94011d3	452
sahilmgandhi	18:6a4db94011d3	453	/------- In Case of PLLI2S is selected as source clock for SAI ----------/
sahilmgandhi	18:6a4db94011d3	454	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
sahilmgandhi	18:6a4db94011d3	455	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
sahilmgandhi	18:6a4db94011d3	456	{
sahilmgandhi	18:6a4db94011d3	457	/* Check for PLLI2S Parameters */
sahilmgandhi	18:6a4db94011d3	458	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	459	/* Check for PLLI2S/DIVQ parameters */
sahilmgandhi	18:6a4db94011d3	460	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
sahilmgandhi	18:6a4db94011d3	461
sahilmgandhi	18:6a4db94011d3	462	/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	463	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
sahilmgandhi	18:6a4db94011d3	464	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	465	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	466	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
sahilmgandhi	18:6a4db94011d3	467	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
sahilmgandhi	18:6a4db94011d3	468	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
sahilmgandhi	18:6a4db94011d3	469	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
sahilmgandhi	18:6a4db94011d3	470
sahilmgandhi	18:6a4db94011d3	471	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
sahilmgandhi	18:6a4db94011d3	472	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
sahilmgandhi	18:6a4db94011d3	473	}
sahilmgandhi	18:6a4db94011d3	474
sahilmgandhi	18:6a4db94011d3	475	/------ In Case of PLLI2S is selected as source clock for SPDIFRX -------/
sahilmgandhi	18:6a4db94011d3	476	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
sahilmgandhi	18:6a4db94011d3	477	{
sahilmgandhi	18:6a4db94011d3	478	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	479	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
sahilmgandhi	18:6a4db94011d3	480	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	481	plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
sahilmgandhi	18:6a4db94011d3	482	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	483	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	484	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
sahilmgandhi	18:6a4db94011d3	485	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
sahilmgandhi	18:6a4db94011d3	486	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
sahilmgandhi	18:6a4db94011d3	487	}
sahilmgandhi	18:6a4db94011d3	488
sahilmgandhi	18:6a4db94011d3	489	/----------------- In Case of PLLI2S is just selected -----------------/
sahilmgandhi	18:6a4db94011d3	490	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
sahilmgandhi	18:6a4db94011d3	491	{
sahilmgandhi	18:6a4db94011d3	492	/* Check for Parameters */
sahilmgandhi	18:6a4db94011d3	493	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
sahilmgandhi	18:6a4db94011d3	494	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
sahilmgandhi	18:6a4db94011d3	495	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	496
sahilmgandhi	18:6a4db94011d3	497	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	498	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
sahilmgandhi	18:6a4db94011d3	499	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	500	}
sahilmgandhi	18:6a4db94011d3	501
sahilmgandhi	18:6a4db94011d3	502	/* Enable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	503	__HAL_RCC_PLLI2S_ENABLE();
sahilmgandhi	18:6a4db94011d3	504	/* Get tick */
sahilmgandhi	18:6a4db94011d3	505	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	506	/* Wait till PLLI2S is ready */
sahilmgandhi	18:6a4db94011d3	507	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
sahilmgandhi	18:6a4db94011d3	508	{
sahilmgandhi	18:6a4db94011d3	509	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	510	{
sahilmgandhi	18:6a4db94011d3	511	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	512	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	513	}
sahilmgandhi	18:6a4db94011d3	514	}
sahilmgandhi	18:6a4db94011d3	515	}
sahilmgandhi	18:6a4db94011d3	516	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	517
sahilmgandhi	18:6a4db94011d3	518	/----------------------------- PLLSAI Configuration -----------------------/
sahilmgandhi	18:6a4db94011d3	519	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
sahilmgandhi	18:6a4db94011d3	520	if(pllsaiused == 1U)
sahilmgandhi	18:6a4db94011d3	521	{
sahilmgandhi	18:6a4db94011d3	522	/* Disable PLLSAI Clock */
sahilmgandhi	18:6a4db94011d3	523	__HAL_RCC_PLLSAI_DISABLE();
sahilmgandhi	18:6a4db94011d3	524	/* Get tick */
sahilmgandhi	18:6a4db94011d3	525	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	526	/* Wait till PLLSAI is disabled */
sahilmgandhi	18:6a4db94011d3	527	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
sahilmgandhi	18:6a4db94011d3	528	{
sahilmgandhi	18:6a4db94011d3	529	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	530	{
sahilmgandhi	18:6a4db94011d3	531	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	532	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	533	}
sahilmgandhi	18:6a4db94011d3	534	}
sahilmgandhi	18:6a4db94011d3	535
sahilmgandhi	18:6a4db94011d3	536	/* Check the PLLSAI division factors */
sahilmgandhi	18:6a4db94011d3	537	assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
sahilmgandhi	18:6a4db94011d3	538	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
sahilmgandhi	18:6a4db94011d3	539
sahilmgandhi	18:6a4db94011d3	540	/------ In Case of PLLSAI is selected as source clock for SAI -----------/
sahilmgandhi	18:6a4db94011d3	541	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|
sahilmgandhi	18:6a4db94011d3	542	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
sahilmgandhi	18:6a4db94011d3	543	{
sahilmgandhi	18:6a4db94011d3	544	/* check for PLLSAIQ Parameter */
sahilmgandhi	18:6a4db94011d3	545	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	546	/* check for PLLSAI/DIVQ Parameter */
sahilmgandhi	18:6a4db94011d3	547	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
sahilmgandhi	18:6a4db94011d3	548
sahilmgandhi	18:6a4db94011d3	549	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	550	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
sahilmgandhi	18:6a4db94011d3	551	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	552	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
sahilmgandhi	18:6a4db94011d3	553	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
sahilmgandhi	18:6a4db94011d3	554	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
sahilmgandhi	18:6a4db94011d3	555
sahilmgandhi	18:6a4db94011d3	556	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
sahilmgandhi	18:6a4db94011d3	557	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
sahilmgandhi	18:6a4db94011d3	558	}
sahilmgandhi	18:6a4db94011d3	559
sahilmgandhi	18:6a4db94011d3	560	/------ In Case of PLLSAI is selected as source clock for CLK48 ---------/
sahilmgandhi	18:6a4db94011d3	561	/* In Case of PLLI2S is selected as source clock for CLK48 */
sahilmgandhi	18:6a4db94011d3	562	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
sahilmgandhi	18:6a4db94011d3	563	{
sahilmgandhi	18:6a4db94011d3	564	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	565	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
sahilmgandhi	18:6a4db94011d3	566	/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	567	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	568	/* Configure the PLLSAI division factors */
sahilmgandhi	18:6a4db94011d3	569	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
sahilmgandhi	18:6a4db94011d3	570	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
sahilmgandhi	18:6a4db94011d3	571	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
sahilmgandhi	18:6a4db94011d3	572	}
sahilmgandhi	18:6a4db94011d3	573
sahilmgandhi	18:6a4db94011d3	574	/* Enable PLLSAI Clock */
sahilmgandhi	18:6a4db94011d3	575	__HAL_RCC_PLLSAI_ENABLE();
sahilmgandhi	18:6a4db94011d3	576	/* Get tick */
sahilmgandhi	18:6a4db94011d3	577	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	578	/* Wait till PLLSAI is ready */
sahilmgandhi	18:6a4db94011d3	579	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
sahilmgandhi	18:6a4db94011d3	580	{
sahilmgandhi	18:6a4db94011d3	581	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	582	{
sahilmgandhi	18:6a4db94011d3	583	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	584	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	585	}
sahilmgandhi	18:6a4db94011d3	586	}
sahilmgandhi	18:6a4db94011d3	587	}
sahilmgandhi	18:6a4db94011d3	588	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	589	}
sahilmgandhi	18:6a4db94011d3	590
sahilmgandhi	18:6a4db94011d3	591	/**
sahilmgandhi	18:6a4db94011d3	592	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
sahilmgandhi	18:6a4db94011d3	593	* RCC configuration registers.
sahilmgandhi	18:6a4db94011d3	594	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	595	* will be configured.
sahilmgandhi	18:6a4db94011d3	596	* @retval None
sahilmgandhi	18:6a4db94011d3	597	*/
sahilmgandhi	18:6a4db94011d3	598	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	599	{
sahilmgandhi	18:6a4db94011d3	600	uint32_t tempreg;
sahilmgandhi	18:6a4db94011d3	601
sahilmgandhi	18:6a4db94011d3	602	/* Set all possible values for the extended clock type parameter------------*/
sahilmgandhi	18:6a4db94011d3	603	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
sahilmgandhi	18:6a4db94011d3	604	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
sahilmgandhi	18:6a4db94011d3	605	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
sahilmgandhi	18:6a4db94011d3	606	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_FMPI2C1 \|\
sahilmgandhi	18:6a4db94011d3	607	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDIO \|\
sahilmgandhi	18:6a4db94011d3	608	RCC_PERIPHCLK_SPDIFRX;
sahilmgandhi	18:6a4db94011d3	609
sahilmgandhi	18:6a4db94011d3	610	/* Get the PLLI2S Clock configuration --------------------------------------*/
sahilmgandhi	18:6a4db94011d3	611	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
sahilmgandhi	18:6a4db94011d3	612	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
sahilmgandhi	18:6a4db94011d3	613	PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
sahilmgandhi	18:6a4db94011d3	614	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	615	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	616	/* Get the PLLSAI Clock configuration --------------------------------------*/
sahilmgandhi	18:6a4db94011d3	617	PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
sahilmgandhi	18:6a4db94011d3	618	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
sahilmgandhi	18:6a4db94011d3	619	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
sahilmgandhi	18:6a4db94011d3	620	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	621	/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
sahilmgandhi	18:6a4db94011d3	622	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
sahilmgandhi	18:6a4db94011d3	623	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
sahilmgandhi	18:6a4db94011d3	624
sahilmgandhi	18:6a4db94011d3	625	/* Get the SAI1 clock configuration ----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	626	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
sahilmgandhi	18:6a4db94011d3	627
sahilmgandhi	18:6a4db94011d3	628	/* Get the SAI2 clock configuration ----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	629	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
sahilmgandhi	18:6a4db94011d3	630
sahilmgandhi	18:6a4db94011d3	631	/* Get the I2S APB1 clock configuration ------------------------------------*/
sahilmgandhi	18:6a4db94011d3	632	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
sahilmgandhi	18:6a4db94011d3	633
sahilmgandhi	18:6a4db94011d3	634	/* Get the I2S APB2 clock configuration ------------------------------------*/
sahilmgandhi	18:6a4db94011d3	635	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
sahilmgandhi	18:6a4db94011d3	636
sahilmgandhi	18:6a4db94011d3	637	/* Get the RTC Clock configuration -----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	638	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
sahilmgandhi	18:6a4db94011d3	639	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	640
sahilmgandhi	18:6a4db94011d3	641	/* Get the CEC clock configuration -----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	642	PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
sahilmgandhi	18:6a4db94011d3	643
sahilmgandhi	18:6a4db94011d3	644	/* Get the FMPI2C1 clock configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	645	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
sahilmgandhi	18:6a4db94011d3	646
sahilmgandhi	18:6a4db94011d3	647	/* Get the CLK48 clock configuration ----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	648	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
sahilmgandhi	18:6a4db94011d3	649
sahilmgandhi	18:6a4db94011d3	650	/* Get the SDIO clock configuration ----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	651	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
sahilmgandhi	18:6a4db94011d3	652
sahilmgandhi	18:6a4db94011d3	653	/* Get the SPDIFRX clock configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	654	PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
sahilmgandhi	18:6a4db94011d3	655
sahilmgandhi	18:6a4db94011d3	656	/* Get the TIM Prescaler configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	657	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
sahilmgandhi	18:6a4db94011d3	658	{
sahilmgandhi	18:6a4db94011d3	659	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
sahilmgandhi	18:6a4db94011d3	660	}
sahilmgandhi	18:6a4db94011d3	661	else
sahilmgandhi	18:6a4db94011d3	662	{
sahilmgandhi	18:6a4db94011d3	663	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
sahilmgandhi	18:6a4db94011d3	664	}
sahilmgandhi	18:6a4db94011d3	665	}
sahilmgandhi	18:6a4db94011d3	666
sahilmgandhi	18:6a4db94011d3	667	/**
sahilmgandhi	18:6a4db94011d3	668	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
sahilmgandhi	18:6a4db94011d3	669	* @note Return 0 if peripheral clock identifier not managed by this API
sahilmgandhi	18:6a4db94011d3	670	* @param PeriphClk: Peripheral clock identifier
sahilmgandhi	18:6a4db94011d3	671	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	672	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
sahilmgandhi	18:6a4db94011d3	673	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
sahilmgandhi	18:6a4db94011d3	674	* @retval Frequency in KHz
sahilmgandhi	18:6a4db94011d3	675	*/
sahilmgandhi	18:6a4db94011d3	676	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
sahilmgandhi	18:6a4db94011d3	677	{
sahilmgandhi	18:6a4db94011d3	678	uint32_t tmpreg1 = 0U;
sahilmgandhi	18:6a4db94011d3	679	/* This variable used to store the SAI clock frequency (value in Hz) */
sahilmgandhi	18:6a4db94011d3	680	uint32_t frequency = 0U;
sahilmgandhi	18:6a4db94011d3	681	/* This variable used to store the VCO Input (value in Hz) */
sahilmgandhi	18:6a4db94011d3	682	uint32_t vcoinput = 0U;
sahilmgandhi	18:6a4db94011d3	683	/* This variable used to store the SAI clock source */
sahilmgandhi	18:6a4db94011d3	684	uint32_t saiclocksource = 0U;
sahilmgandhi	18:6a4db94011d3	685	if ((PeriphClk == RCC_PERIPHCLK_SAI1) \|\| (PeriphClk == RCC_PERIPHCLK_SAI2))
sahilmgandhi	18:6a4db94011d3	686	{
sahilmgandhi	18:6a4db94011d3	687	saiclocksource = RCC->DCKCFGR;
sahilmgandhi	18:6a4db94011d3	688	saiclocksource &= (RCC_DCKCFGR_SAI1SRC \| RCC_DCKCFGR_SAI2SRC);
sahilmgandhi	18:6a4db94011d3	689	switch (saiclocksource)
sahilmgandhi	18:6a4db94011d3	690	{
sahilmgandhi	18:6a4db94011d3	691	case 0U: /* PLLSAI is the clock source for SAI*/
sahilmgandhi	18:6a4db94011d3	692	{
sahilmgandhi	18:6a4db94011d3	693	/* Configure the PLLSAI division factor */
sahilmgandhi	18:6a4db94011d3	694	/* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
sahilmgandhi	18:6a4db94011d3	695	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
sahilmgandhi	18:6a4db94011d3	696	{
sahilmgandhi	18:6a4db94011d3	697	/* In Case the PLL Source is HSI (Internal Clock) */
sahilmgandhi	18:6a4db94011d3	698	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
sahilmgandhi	18:6a4db94011d3	699	}
sahilmgandhi	18:6a4db94011d3	700	else
sahilmgandhi	18:6a4db94011d3	701	{
sahilmgandhi	18:6a4db94011d3	702	/* In Case the PLL Source is HSE (External Clock) */
sahilmgandhi	18:6a4db94011d3	703	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
sahilmgandhi	18:6a4db94011d3	704	}
sahilmgandhi	18:6a4db94011d3	705	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
sahilmgandhi	18:6a4db94011d3	706	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
sahilmgandhi	18:6a4db94011d3	707	tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
sahilmgandhi	18:6a4db94011d3	708	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
sahilmgandhi	18:6a4db94011d3	709
sahilmgandhi	18:6a4db94011d3	710	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
sahilmgandhi	18:6a4db94011d3	711	tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
sahilmgandhi	18:6a4db94011d3	712	frequency = frequency/(tmpreg1);
sahilmgandhi	18:6a4db94011d3	713	break;
sahilmgandhi	18:6a4db94011d3	714	}
sahilmgandhi	18:6a4db94011d3	715	case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
sahilmgandhi	18:6a4db94011d3	716	case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
sahilmgandhi	18:6a4db94011d3	717	{
sahilmgandhi	18:6a4db94011d3	718	/* Configure the PLLI2S division factor */
sahilmgandhi	18:6a4db94011d3	719	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
sahilmgandhi	18:6a4db94011d3	720	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
sahilmgandhi	18:6a4db94011d3	721	{
sahilmgandhi	18:6a4db94011d3	722	/* In Case the PLL Source is HSI (Internal Clock) */
sahilmgandhi	18:6a4db94011d3	723	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
sahilmgandhi	18:6a4db94011d3	724	}
sahilmgandhi	18:6a4db94011d3	725	else
sahilmgandhi	18:6a4db94011d3	726	{
sahilmgandhi	18:6a4db94011d3	727	/* In Case the PLL Source is HSE (External Clock) */
sahilmgandhi	18:6a4db94011d3	728	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
sahilmgandhi	18:6a4db94011d3	729	}
sahilmgandhi	18:6a4db94011d3	730
sahilmgandhi	18:6a4db94011d3	731	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
sahilmgandhi	18:6a4db94011d3	732	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
sahilmgandhi	18:6a4db94011d3	733	tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
sahilmgandhi	18:6a4db94011d3	734	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
sahilmgandhi	18:6a4db94011d3	735
sahilmgandhi	18:6a4db94011d3	736	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
sahilmgandhi	18:6a4db94011d3	737	tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
sahilmgandhi	18:6a4db94011d3	738	frequency = frequency/(tmpreg1);
sahilmgandhi	18:6a4db94011d3	739	break;
sahilmgandhi	18:6a4db94011d3	740	}
sahilmgandhi	18:6a4db94011d3	741	case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
sahilmgandhi	18:6a4db94011d3	742	case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
sahilmgandhi	18:6a4db94011d3	743	{
sahilmgandhi	18:6a4db94011d3	744	/* Configure the PLLI2S division factor */
sahilmgandhi	18:6a4db94011d3	745	/* PLL_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	746	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
sahilmgandhi	18:6a4db94011d3	747	{
sahilmgandhi	18:6a4db94011d3	748	/* In Case the PLL Source is HSI (Internal Clock) */
sahilmgandhi	18:6a4db94011d3	749	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
sahilmgandhi	18:6a4db94011d3	750	}
sahilmgandhi	18:6a4db94011d3	751	else
sahilmgandhi	18:6a4db94011d3	752	{
sahilmgandhi	18:6a4db94011d3	753	/* In Case the PLL Source is HSE (External Clock) */
sahilmgandhi	18:6a4db94011d3	754	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
sahilmgandhi	18:6a4db94011d3	755	}
sahilmgandhi	18:6a4db94011d3	756
sahilmgandhi	18:6a4db94011d3	757	/* PLL_VCO Output = PLL_VCO Input * PLLN */
sahilmgandhi	18:6a4db94011d3	758	/* SAI_CLK_x = PLL_VCO Output/PLLR */
sahilmgandhi	18:6a4db94011d3	759	tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
sahilmgandhi	18:6a4db94011d3	760	frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
sahilmgandhi	18:6a4db94011d3	761	break;
sahilmgandhi	18:6a4db94011d3	762	}
sahilmgandhi	18:6a4db94011d3	763	case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
sahilmgandhi	18:6a4db94011d3	764	{
sahilmgandhi	18:6a4db94011d3	765	frequency = EXTERNAL_CLOCK_VALUE;
sahilmgandhi	18:6a4db94011d3	766	break;
sahilmgandhi	18:6a4db94011d3	767	}
sahilmgandhi	18:6a4db94011d3	768	case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
sahilmgandhi	18:6a4db94011d3	769	{
sahilmgandhi	18:6a4db94011d3	770	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
sahilmgandhi	18:6a4db94011d3	771	{
sahilmgandhi	18:6a4db94011d3	772	/* In Case the PLL Source is HSI (Internal Clock) */
sahilmgandhi	18:6a4db94011d3	773	frequency = (uint32_t)(HSI_VALUE);
sahilmgandhi	18:6a4db94011d3	774	}
sahilmgandhi	18:6a4db94011d3	775	else
sahilmgandhi	18:6a4db94011d3	776	{
sahilmgandhi	18:6a4db94011d3	777	/* In Case the PLL Source is HSE (External Clock) */
sahilmgandhi	18:6a4db94011d3	778	frequency = (uint32_t)(HSE_VALUE);
sahilmgandhi	18:6a4db94011d3	779	}
sahilmgandhi	18:6a4db94011d3	780	break;
sahilmgandhi	18:6a4db94011d3	781	}
sahilmgandhi	18:6a4db94011d3	782	default :
sahilmgandhi	18:6a4db94011d3	783	{
sahilmgandhi	18:6a4db94011d3	784	break;
sahilmgandhi	18:6a4db94011d3	785	}
sahilmgandhi	18:6a4db94011d3	786	}
sahilmgandhi	18:6a4db94011d3	787	}
sahilmgandhi	18:6a4db94011d3	788	return frequency;
sahilmgandhi	18:6a4db94011d3	789	}
sahilmgandhi	18:6a4db94011d3	790
sahilmgandhi	18:6a4db94011d3	791	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	792
sahilmgandhi	18:6a4db94011d3	793	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	794	/**
sahilmgandhi	18:6a4db94011d3	795	* @brief Initializes the RCC extended peripherals clocks according to the specified
sahilmgandhi	18:6a4db94011d3	796	* parameters in the RCC_PeriphCLKInitTypeDef.
sahilmgandhi	18:6a4db94011d3	797	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	798	* contains the configuration information for the Extended Peripherals
sahilmgandhi	18:6a4db94011d3	799	* clocks(I2S, SAI, LTDC, RTC and TIM).
sahilmgandhi	18:6a4db94011d3	800	*
sahilmgandhi	18:6a4db94011d3	801	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
sahilmgandhi	18:6a4db94011d3	802	* the RTC clock source; in this case the Backup domain will be reset in
sahilmgandhi	18:6a4db94011d3	803	* order to modify the RTC Clock source, as consequence RTC registers (including
sahilmgandhi	18:6a4db94011d3	804	* the backup registers) and RCC_BDCR register are set to their reset values.
sahilmgandhi	18:6a4db94011d3	805	*
sahilmgandhi	18:6a4db94011d3	806	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	807	*/
sahilmgandhi	18:6a4db94011d3	808	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	809	{
sahilmgandhi	18:6a4db94011d3	810	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	811	uint32_t tmpreg1 = 0U;
sahilmgandhi	18:6a4db94011d3	812	uint32_t pllsaip = 0U;
sahilmgandhi	18:6a4db94011d3	813	uint32_t pllsaiq = 0U;
sahilmgandhi	18:6a4db94011d3	814	uint32_t pllsair = 0U;
sahilmgandhi	18:6a4db94011d3	815
sahilmgandhi	18:6a4db94011d3	816	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	817	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
sahilmgandhi	18:6a4db94011d3	818
sahilmgandhi	18:6a4db94011d3	819	/--------------------------- CLK48 Configuration --------------------------/
sahilmgandhi	18:6a4db94011d3	820	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
sahilmgandhi	18:6a4db94011d3	821	{
sahilmgandhi	18:6a4db94011d3	822	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	823	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
sahilmgandhi	18:6a4db94011d3	824
sahilmgandhi	18:6a4db94011d3	825	/* Configure the CLK48 clock source */
sahilmgandhi	18:6a4db94011d3	826	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
sahilmgandhi	18:6a4db94011d3	827	}
sahilmgandhi	18:6a4db94011d3	828	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	829
sahilmgandhi	18:6a4db94011d3	830	/------------------------------ SDIO Configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	831	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
sahilmgandhi	18:6a4db94011d3	832	{
sahilmgandhi	18:6a4db94011d3	833	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	834	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
sahilmgandhi	18:6a4db94011d3	835
sahilmgandhi	18:6a4db94011d3	836	/* Configure the SDIO clock source */
sahilmgandhi	18:6a4db94011d3	837	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
sahilmgandhi	18:6a4db94011d3	838	}
sahilmgandhi	18:6a4db94011d3	839	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	840
sahilmgandhi	18:6a4db94011d3	841	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------/
sahilmgandhi	18:6a4db94011d3	842	/------------------- Common configuration SAI/I2S -------------------------/
sahilmgandhi	18:6a4db94011d3	843	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
sahilmgandhi	18:6a4db94011d3	844	factor is common parameters for both peripherals */
sahilmgandhi	18:6a4db94011d3	845	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
sahilmgandhi	18:6a4db94011d3	846	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) \|\|
sahilmgandhi	18:6a4db94011d3	847	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
sahilmgandhi	18:6a4db94011d3	848	{
sahilmgandhi	18:6a4db94011d3	849	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	850	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
sahilmgandhi	18:6a4db94011d3	851
sahilmgandhi	18:6a4db94011d3	852	/* Disable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	853	__HAL_RCC_PLLI2S_DISABLE();
sahilmgandhi	18:6a4db94011d3	854	/* Get tick */
sahilmgandhi	18:6a4db94011d3	855	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	856	/* Wait till PLLI2S is disabled */
sahilmgandhi	18:6a4db94011d3	857	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	858	{
sahilmgandhi	18:6a4db94011d3	859	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	860	{
sahilmgandhi	18:6a4db94011d3	861	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	862	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	863	}
sahilmgandhi	18:6a4db94011d3	864	}
sahilmgandhi	18:6a4db94011d3	865
sahilmgandhi	18:6a4db94011d3	866	/---------------------- I2S configuration -------------------------------/
sahilmgandhi	18:6a4db94011d3	867	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
sahilmgandhi	18:6a4db94011d3	868	only for I2S configuration */
sahilmgandhi	18:6a4db94011d3	869	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
sahilmgandhi	18:6a4db94011d3	870	{
sahilmgandhi	18:6a4db94011d3	871	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	872	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
sahilmgandhi	18:6a4db94011d3	873	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	874	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
sahilmgandhi	18:6a4db94011d3	875	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
sahilmgandhi	18:6a4db94011d3	876	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	877	}
sahilmgandhi	18:6a4db94011d3	878
sahilmgandhi	18:6a4db94011d3	879	/---------------------------- SAI configuration -------------------------/
sahilmgandhi	18:6a4db94011d3	880	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
sahilmgandhi	18:6a4db94011d3	881	be added only for SAI configuration */
sahilmgandhi	18:6a4db94011d3	882	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
sahilmgandhi	18:6a4db94011d3	883	{
sahilmgandhi	18:6a4db94011d3	884	/* Check the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	885	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	886	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
sahilmgandhi	18:6a4db94011d3	887
sahilmgandhi	18:6a4db94011d3	888	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	889	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	890	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	891	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	892	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
sahilmgandhi	18:6a4db94011d3	893	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
sahilmgandhi	18:6a4db94011d3	894	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
sahilmgandhi	18:6a4db94011d3	895	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
sahilmgandhi	18:6a4db94011d3	896	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
sahilmgandhi	18:6a4db94011d3	897	}
sahilmgandhi	18:6a4db94011d3	898
sahilmgandhi	18:6a4db94011d3	899	/----------------- In Case of PLLI2S is just selected -----------------/
sahilmgandhi	18:6a4db94011d3	900	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
sahilmgandhi	18:6a4db94011d3	901	{
sahilmgandhi	18:6a4db94011d3	902	/* Check for Parameters */
sahilmgandhi	18:6a4db94011d3	903	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	904	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
sahilmgandhi	18:6a4db94011d3	905
sahilmgandhi	18:6a4db94011d3	906	/* Configure the PLLI2S multiplication and division factors */
sahilmgandhi	18:6a4db94011d3	907	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	908	}
sahilmgandhi	18:6a4db94011d3	909
sahilmgandhi	18:6a4db94011d3	910	/* Enable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	911	__HAL_RCC_PLLI2S_ENABLE();
sahilmgandhi	18:6a4db94011d3	912	/* Get tick */
sahilmgandhi	18:6a4db94011d3	913	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	914	/* Wait till PLLI2S is ready */
sahilmgandhi	18:6a4db94011d3	915	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
sahilmgandhi	18:6a4db94011d3	916	{
sahilmgandhi	18:6a4db94011d3	917	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	918	{
sahilmgandhi	18:6a4db94011d3	919	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	920	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	921	}
sahilmgandhi	18:6a4db94011d3	922	}
sahilmgandhi	18:6a4db94011d3	923	}
sahilmgandhi	18:6a4db94011d3	924	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	925
sahilmgandhi	18:6a4db94011d3	926	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
sahilmgandhi	18:6a4db94011d3	927	/----------------------- Common configuration SAI/LTDC --------------------/
sahilmgandhi	18:6a4db94011d3	928	/* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
sahilmgandhi	18:6a4db94011d3	929	factor is common parameters for these peripherals */
sahilmgandhi	18:6a4db94011d3	930	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
sahilmgandhi	18:6a4db94011d3	931	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\|
sahilmgandhi	18:6a4db94011d3	932	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) &&
sahilmgandhi	18:6a4db94011d3	933	(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
sahilmgandhi	18:6a4db94011d3	934	{
sahilmgandhi	18:6a4db94011d3	935	/* Check the PLLSAI division factors */
sahilmgandhi	18:6a4db94011d3	936	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
sahilmgandhi	18:6a4db94011d3	937
sahilmgandhi	18:6a4db94011d3	938	/* Disable PLLSAI Clock */
sahilmgandhi	18:6a4db94011d3	939	__HAL_RCC_PLLSAI_DISABLE();
sahilmgandhi	18:6a4db94011d3	940	/* Get tick */
sahilmgandhi	18:6a4db94011d3	941	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	942	/* Wait till PLLSAI is disabled */
sahilmgandhi	18:6a4db94011d3	943	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
sahilmgandhi	18:6a4db94011d3	944	{
sahilmgandhi	18:6a4db94011d3	945	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	946	{
sahilmgandhi	18:6a4db94011d3	947	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	948	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	949	}
sahilmgandhi	18:6a4db94011d3	950	}
sahilmgandhi	18:6a4db94011d3	951
sahilmgandhi	18:6a4db94011d3	952	/---------------------------- SAI configuration -------------------------/
sahilmgandhi	18:6a4db94011d3	953	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
sahilmgandhi	18:6a4db94011d3	954	be added only for SAI configuration */
sahilmgandhi	18:6a4db94011d3	955	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
sahilmgandhi	18:6a4db94011d3	956	{
sahilmgandhi	18:6a4db94011d3	957	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	958	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
sahilmgandhi	18:6a4db94011d3	959
sahilmgandhi	18:6a4db94011d3	960	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	961	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
sahilmgandhi	18:6a4db94011d3	962	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	963	pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
sahilmgandhi	18:6a4db94011d3	964	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	965	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
sahilmgandhi	18:6a4db94011d3	966	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
sahilmgandhi	18:6a4db94011d3	967	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
sahilmgandhi	18:6a4db94011d3	968	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
sahilmgandhi	18:6a4db94011d3	969	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
sahilmgandhi	18:6a4db94011d3	970	}
sahilmgandhi	18:6a4db94011d3	971
sahilmgandhi	18:6a4db94011d3	972	/---------------------------- LTDC configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	973	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
sahilmgandhi	18:6a4db94011d3	974	{
sahilmgandhi	18:6a4db94011d3	975	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
sahilmgandhi	18:6a4db94011d3	976	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
sahilmgandhi	18:6a4db94011d3	977
sahilmgandhi	18:6a4db94011d3	978	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	979	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
sahilmgandhi	18:6a4db94011d3	980	/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	981	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	982	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	983	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
sahilmgandhi	18:6a4db94011d3	984	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
sahilmgandhi	18:6a4db94011d3	985	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
sahilmgandhi	18:6a4db94011d3	986	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
sahilmgandhi	18:6a4db94011d3	987	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
sahilmgandhi	18:6a4db94011d3	988	}
sahilmgandhi	18:6a4db94011d3	989
sahilmgandhi	18:6a4db94011d3	990	/---------------------------- CLK48 configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	991	/* Configure the PLLSAI when it is used as clock source for CLK48 */
sahilmgandhi	18:6a4db94011d3	992	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
sahilmgandhi	18:6a4db94011d3	993	(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
sahilmgandhi	18:6a4db94011d3	994	{
sahilmgandhi	18:6a4db94011d3	995	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
sahilmgandhi	18:6a4db94011d3	996
sahilmgandhi	18:6a4db94011d3	997	/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	998	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	999	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	1000	pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
sahilmgandhi	18:6a4db94011d3	1001	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	1002	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
sahilmgandhi	18:6a4db94011d3	1003	/* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
sahilmgandhi	18:6a4db94011d3	1004	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
sahilmgandhi	18:6a4db94011d3	1005	}
sahilmgandhi	18:6a4db94011d3	1006
sahilmgandhi	18:6a4db94011d3	1007	/* Enable PLLSAI Clock */
sahilmgandhi	18:6a4db94011d3	1008	__HAL_RCC_PLLSAI_ENABLE();
sahilmgandhi	18:6a4db94011d3	1009	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1010	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1011	/* Wait till PLLSAI is ready */
sahilmgandhi	18:6a4db94011d3	1012	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
sahilmgandhi	18:6a4db94011d3	1013	{
sahilmgandhi	18:6a4db94011d3	1014	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1015	{
sahilmgandhi	18:6a4db94011d3	1016	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1017	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1018	}
sahilmgandhi	18:6a4db94011d3	1019	}
sahilmgandhi	18:6a4db94011d3	1020	}
sahilmgandhi	18:6a4db94011d3	1021
sahilmgandhi	18:6a4db94011d3	1022	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1023
sahilmgandhi	18:6a4db94011d3	1024	/---------------------------- RTC configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1025	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
sahilmgandhi	18:6a4db94011d3	1026	{
sahilmgandhi	18:6a4db94011d3	1027	/* Check for RTC Parameters used to output RTCCLK */
sahilmgandhi	18:6a4db94011d3	1028	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
sahilmgandhi	18:6a4db94011d3	1029
sahilmgandhi	18:6a4db94011d3	1030	/* Enable Power Clock*/
sahilmgandhi	18:6a4db94011d3	1031	__HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	1032
sahilmgandhi	18:6a4db94011d3	1033	/* Enable write access to Backup domain */
sahilmgandhi	18:6a4db94011d3	1034	PWR->CR \|= PWR_CR_DBP;
sahilmgandhi	18:6a4db94011d3	1035
sahilmgandhi	18:6a4db94011d3	1036	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1037	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1038
sahilmgandhi	18:6a4db94011d3	1039	while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi	18:6a4db94011d3	1040	{
sahilmgandhi	18:6a4db94011d3	1041	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1042	{
sahilmgandhi	18:6a4db94011d3	1043	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1044	}
sahilmgandhi	18:6a4db94011d3	1045	}
sahilmgandhi	18:6a4db94011d3	1046	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
sahilmgandhi	18:6a4db94011d3	1047	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
sahilmgandhi	18:6a4db94011d3	1048	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
sahilmgandhi	18:6a4db94011d3	1049	{
sahilmgandhi	18:6a4db94011d3	1050	/* Store the content of BDCR register before the reset of Backup Domain */
sahilmgandhi	18:6a4db94011d3	1051	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1052	/* RTC Clock selection can be changed only if the Backup Domain is reset */
sahilmgandhi	18:6a4db94011d3	1053	__HAL_RCC_BACKUPRESET_FORCE();
sahilmgandhi	18:6a4db94011d3	1054	__HAL_RCC_BACKUPRESET_RELEASE();
sahilmgandhi	18:6a4db94011d3	1055	/* Restore the Content of BDCR register */
sahilmgandhi	18:6a4db94011d3	1056	RCC->BDCR = tmpreg1;
sahilmgandhi	18:6a4db94011d3	1057
sahilmgandhi	18:6a4db94011d3	1058	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
sahilmgandhi	18:6a4db94011d3	1059	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
sahilmgandhi	18:6a4db94011d3	1060	{
sahilmgandhi	18:6a4db94011d3	1061	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1062	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1063
sahilmgandhi	18:6a4db94011d3	1064	/* Wait till LSE is ready */
sahilmgandhi	18:6a4db94011d3	1065	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi	18:6a4db94011d3	1066	{
sahilmgandhi	18:6a4db94011d3	1067	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1068	{
sahilmgandhi	18:6a4db94011d3	1069	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1070	}
sahilmgandhi	18:6a4db94011d3	1071	}
sahilmgandhi	18:6a4db94011d3	1072	}
sahilmgandhi	18:6a4db94011d3	1073	}
sahilmgandhi	18:6a4db94011d3	1074	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
sahilmgandhi	18:6a4db94011d3	1075	}
sahilmgandhi	18:6a4db94011d3	1076	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1077
sahilmgandhi	18:6a4db94011d3	1078	/---------------------------- TIM configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1079	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
sahilmgandhi	18:6a4db94011d3	1080	{
sahilmgandhi	18:6a4db94011d3	1081	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
sahilmgandhi	18:6a4db94011d3	1082	}
sahilmgandhi	18:6a4db94011d3	1083	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1084	}
sahilmgandhi	18:6a4db94011d3	1085
sahilmgandhi	18:6a4db94011d3	1086	/**
sahilmgandhi	18:6a4db94011d3	1087	* @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
sahilmgandhi	18:6a4db94011d3	1088	* RCC configuration registers.
sahilmgandhi	18:6a4db94011d3	1089	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	1090	* will be configured.
sahilmgandhi	18:6a4db94011d3	1091	* @retval None
sahilmgandhi	18:6a4db94011d3	1092	*/
sahilmgandhi	18:6a4db94011d3	1093	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	1094	{
sahilmgandhi	18:6a4db94011d3	1095	uint32_t tempreg;
sahilmgandhi	18:6a4db94011d3	1096
sahilmgandhi	18:6a4db94011d3	1097	/* Set all possible values for the extended clock type parameter------------*/
sahilmgandhi	18:6a4db94011d3	1098	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \|\
sahilmgandhi	18:6a4db94011d3	1099	RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \|\
sahilmgandhi	18:6a4db94011d3	1100	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
sahilmgandhi	18:6a4db94011d3	1101	RCC_PERIPHCLK_CLK48 \| RCC_PERIPHCLK_SDIO;
sahilmgandhi	18:6a4db94011d3	1102
sahilmgandhi	18:6a4db94011d3	1103	/* Get the PLLI2S Clock configuration --------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1104	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
sahilmgandhi	18:6a4db94011d3	1105	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	1106	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	1107	/* Get the PLLSAI Clock configuration --------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1108	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
sahilmgandhi	18:6a4db94011d3	1109	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
sahilmgandhi	18:6a4db94011d3	1110	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	1111	/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
sahilmgandhi	18:6a4db94011d3	1112	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
sahilmgandhi	18:6a4db94011d3	1113	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
sahilmgandhi	18:6a4db94011d3	1114	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
sahilmgandhi	18:6a4db94011d3	1115	/* Get the RTC Clock configuration -----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1116	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
sahilmgandhi	18:6a4db94011d3	1117	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1118
sahilmgandhi	18:6a4db94011d3	1119	/* Get the CLK48 clock configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1120	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
sahilmgandhi	18:6a4db94011d3	1121
sahilmgandhi	18:6a4db94011d3	1122	/* Get the SDIO clock configuration ----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1123	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
sahilmgandhi	18:6a4db94011d3	1124
sahilmgandhi	18:6a4db94011d3	1125	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
sahilmgandhi	18:6a4db94011d3	1126	{
sahilmgandhi	18:6a4db94011d3	1127	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
sahilmgandhi	18:6a4db94011d3	1128	}
sahilmgandhi	18:6a4db94011d3	1129	else
sahilmgandhi	18:6a4db94011d3	1130	{
sahilmgandhi	18:6a4db94011d3	1131	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
sahilmgandhi	18:6a4db94011d3	1132	}
sahilmgandhi	18:6a4db94011d3	1133	}
sahilmgandhi	18:6a4db94011d3	1134	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1135
sahilmgandhi	18:6a4db94011d3	1136	#if defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	1137	/**
sahilmgandhi	18:6a4db94011d3	1138	* @brief Initializes the RCC extended peripherals clocks according to the specified
sahilmgandhi	18:6a4db94011d3	1139	* parameters in the RCC_PeriphCLKInitTypeDef.
sahilmgandhi	18:6a4db94011d3	1140	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	1141	* contains the configuration information for the Extended Peripherals
sahilmgandhi	18:6a4db94011d3	1142	* clocks(I2S, LTDC RTC and TIM).
sahilmgandhi	18:6a4db94011d3	1143	*
sahilmgandhi	18:6a4db94011d3	1144	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
sahilmgandhi	18:6a4db94011d3	1145	* the RTC clock source; in this case the Backup domain will be reset in
sahilmgandhi	18:6a4db94011d3	1146	* order to modify the RTC Clock source, as consequence RTC registers (including
sahilmgandhi	18:6a4db94011d3	1147	* the backup registers) and RCC_BDCR register are set to their reset values.
sahilmgandhi	18:6a4db94011d3	1148	*
sahilmgandhi	18:6a4db94011d3	1149	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1150	*/
sahilmgandhi	18:6a4db94011d3	1151	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	1152	{
sahilmgandhi	18:6a4db94011d3	1153	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1154	uint32_t tmpreg1 = 0U;
sahilmgandhi	18:6a4db94011d3	1155	uint32_t plli2sq = 0U;
sahilmgandhi	18:6a4db94011d3	1156	uint32_t plli2sused = 0U;
sahilmgandhi	18:6a4db94011d3	1157
sahilmgandhi	18:6a4db94011d3	1158	/* Check the peripheral clock selection parameters */
sahilmgandhi	18:6a4db94011d3	1159	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
sahilmgandhi	18:6a4db94011d3	1160
sahilmgandhi	18:6a4db94011d3	1161	/----------------------------------- I2S APB1 configuration ---------------/
sahilmgandhi	18:6a4db94011d3	1162	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
sahilmgandhi	18:6a4db94011d3	1163	{
sahilmgandhi	18:6a4db94011d3	1164	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1165	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
sahilmgandhi	18:6a4db94011d3	1166
sahilmgandhi	18:6a4db94011d3	1167	/* Configure I2S Clock source */
sahilmgandhi	18:6a4db94011d3	1168	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
sahilmgandhi	18:6a4db94011d3	1169	/* Enable the PLLI2S when it's used as clock source for I2S */
sahilmgandhi	18:6a4db94011d3	1170	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
sahilmgandhi	18:6a4db94011d3	1171	{
sahilmgandhi	18:6a4db94011d3	1172	plli2sused = 1U;
sahilmgandhi	18:6a4db94011d3	1173	}
sahilmgandhi	18:6a4db94011d3	1174	}
sahilmgandhi	18:6a4db94011d3	1175	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1176
sahilmgandhi	18:6a4db94011d3	1177	/----------------------------------- I2S APB2 configuration ---------------/
sahilmgandhi	18:6a4db94011d3	1178	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
sahilmgandhi	18:6a4db94011d3	1179	{
sahilmgandhi	18:6a4db94011d3	1180	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1181	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
sahilmgandhi	18:6a4db94011d3	1182
sahilmgandhi	18:6a4db94011d3	1183	/* Configure I2S Clock source */
sahilmgandhi	18:6a4db94011d3	1184	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
sahilmgandhi	18:6a4db94011d3	1185	/* Enable the PLLI2S when it's used as clock source for I2S */
sahilmgandhi	18:6a4db94011d3	1186	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
sahilmgandhi	18:6a4db94011d3	1187	{
sahilmgandhi	18:6a4db94011d3	1188	plli2sused = 1U;
sahilmgandhi	18:6a4db94011d3	1189	}
sahilmgandhi	18:6a4db94011d3	1190	}
sahilmgandhi	18:6a4db94011d3	1191	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1192
sahilmgandhi	18:6a4db94011d3	1193	/------------------------------------ RTC configuration -------------------/
sahilmgandhi	18:6a4db94011d3	1194	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
sahilmgandhi	18:6a4db94011d3	1195	{
sahilmgandhi	18:6a4db94011d3	1196	/* Check for RTC Parameters used to output RTCCLK */
sahilmgandhi	18:6a4db94011d3	1197	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
sahilmgandhi	18:6a4db94011d3	1198
sahilmgandhi	18:6a4db94011d3	1199	/* Enable Power Clock*/
sahilmgandhi	18:6a4db94011d3	1200	__HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	1201
sahilmgandhi	18:6a4db94011d3	1202	/* Enable write access to Backup domain */
sahilmgandhi	18:6a4db94011d3	1203	PWR->CR \|= PWR_CR_DBP;
sahilmgandhi	18:6a4db94011d3	1204
sahilmgandhi	18:6a4db94011d3	1205	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1206	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1207
sahilmgandhi	18:6a4db94011d3	1208	while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi	18:6a4db94011d3	1209	{
sahilmgandhi	18:6a4db94011d3	1210	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1211	{
sahilmgandhi	18:6a4db94011d3	1212	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1213	}
sahilmgandhi	18:6a4db94011d3	1214	}
sahilmgandhi	18:6a4db94011d3	1215	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
sahilmgandhi	18:6a4db94011d3	1216	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
sahilmgandhi	18:6a4db94011d3	1217	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
sahilmgandhi	18:6a4db94011d3	1218	{
sahilmgandhi	18:6a4db94011d3	1219	/* Store the content of BDCR register before the reset of Backup Domain */
sahilmgandhi	18:6a4db94011d3	1220	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1221	/* RTC Clock selection can be changed only if the Backup Domain is reset */
sahilmgandhi	18:6a4db94011d3	1222	__HAL_RCC_BACKUPRESET_FORCE();
sahilmgandhi	18:6a4db94011d3	1223	__HAL_RCC_BACKUPRESET_RELEASE();
sahilmgandhi	18:6a4db94011d3	1224	/* Restore the Content of BDCR register */
sahilmgandhi	18:6a4db94011d3	1225	RCC->BDCR = tmpreg1;
sahilmgandhi	18:6a4db94011d3	1226
sahilmgandhi	18:6a4db94011d3	1227	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
sahilmgandhi	18:6a4db94011d3	1228	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
sahilmgandhi	18:6a4db94011d3	1229	{
sahilmgandhi	18:6a4db94011d3	1230	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1231	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1232
sahilmgandhi	18:6a4db94011d3	1233	/* Wait till LSE is ready */
sahilmgandhi	18:6a4db94011d3	1234	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi	18:6a4db94011d3	1235	{
sahilmgandhi	18:6a4db94011d3	1236	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1237	{
sahilmgandhi	18:6a4db94011d3	1238	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1239	}
sahilmgandhi	18:6a4db94011d3	1240	}
sahilmgandhi	18:6a4db94011d3	1241	}
sahilmgandhi	18:6a4db94011d3	1242	}
sahilmgandhi	18:6a4db94011d3	1243	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
sahilmgandhi	18:6a4db94011d3	1244	}
sahilmgandhi	18:6a4db94011d3	1245	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1246
sahilmgandhi	18:6a4db94011d3	1247	/------------------------------------ TIM configuration -------------------/
sahilmgandhi	18:6a4db94011d3	1248	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
sahilmgandhi	18:6a4db94011d3	1249	{
sahilmgandhi	18:6a4db94011d3	1250	/* Configure Timer Prescaler */
sahilmgandhi	18:6a4db94011d3	1251	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
sahilmgandhi	18:6a4db94011d3	1252	}
sahilmgandhi	18:6a4db94011d3	1253	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1254
sahilmgandhi	18:6a4db94011d3	1255	/------------------------------------- FMPI2C1 Configuration --------------/
sahilmgandhi	18:6a4db94011d3	1256	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
sahilmgandhi	18:6a4db94011d3	1257	{
sahilmgandhi	18:6a4db94011d3	1258	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1259	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
sahilmgandhi	18:6a4db94011d3	1260
sahilmgandhi	18:6a4db94011d3	1261	/* Configure the FMPI2C1 clock source */
sahilmgandhi	18:6a4db94011d3	1262	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
sahilmgandhi	18:6a4db94011d3	1263	}
sahilmgandhi	18:6a4db94011d3	1264	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1265
sahilmgandhi	18:6a4db94011d3	1266	/------------------------------------- CLK48 Configuration ----------------/
sahilmgandhi	18:6a4db94011d3	1267	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
sahilmgandhi	18:6a4db94011d3	1268	{
sahilmgandhi	18:6a4db94011d3	1269	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1270	assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
sahilmgandhi	18:6a4db94011d3	1271
sahilmgandhi	18:6a4db94011d3	1272	/* Configure the SDIO clock source */
sahilmgandhi	18:6a4db94011d3	1273	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
sahilmgandhi	18:6a4db94011d3	1274
sahilmgandhi	18:6a4db94011d3	1275	/* Enable the PLLI2S when it's used as clock source for CLK48 */
sahilmgandhi	18:6a4db94011d3	1276	if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
sahilmgandhi	18:6a4db94011d3	1277	{
sahilmgandhi	18:6a4db94011d3	1278	plli2sused = 1U;
sahilmgandhi	18:6a4db94011d3	1279	}
sahilmgandhi	18:6a4db94011d3	1280	}
sahilmgandhi	18:6a4db94011d3	1281	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1282
sahilmgandhi	18:6a4db94011d3	1283	/------------------------------------- SDIO Configuration -----------------/
sahilmgandhi	18:6a4db94011d3	1284	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
sahilmgandhi	18:6a4db94011d3	1285	{
sahilmgandhi	18:6a4db94011d3	1286	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1287	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
sahilmgandhi	18:6a4db94011d3	1288
sahilmgandhi	18:6a4db94011d3	1289	/* Configure the SDIO clock source */
sahilmgandhi	18:6a4db94011d3	1290	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
sahilmgandhi	18:6a4db94011d3	1291	}
sahilmgandhi	18:6a4db94011d3	1292	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1293
sahilmgandhi	18:6a4db94011d3	1294	/-------------------------------------- PLLI2S Configuration --------------/
sahilmgandhi	18:6a4db94011d3	1295	/* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
sahilmgandhi	18:6a4db94011d3	1296	I2S on APB2*/
sahilmgandhi	18:6a4db94011d3	1297	if((plli2sused == 1U) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
sahilmgandhi	18:6a4db94011d3	1298	{
sahilmgandhi	18:6a4db94011d3	1299	/* Disable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	1300	__HAL_RCC_PLLI2S_DISABLE();
sahilmgandhi	18:6a4db94011d3	1301	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1302	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1303	/* Wait till PLLI2S is disabled */
sahilmgandhi	18:6a4db94011d3	1304	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	1305	{
sahilmgandhi	18:6a4db94011d3	1306	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1307	{
sahilmgandhi	18:6a4db94011d3	1308	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1309	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1310	}
sahilmgandhi	18:6a4db94011d3	1311	}
sahilmgandhi	18:6a4db94011d3	1312
sahilmgandhi	18:6a4db94011d3	1313	/* check for common PLLI2S Parameters */
sahilmgandhi	18:6a4db94011d3	1314	assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
sahilmgandhi	18:6a4db94011d3	1315	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
sahilmgandhi	18:6a4db94011d3	1316	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
sahilmgandhi	18:6a4db94011d3	1317	/-------------------- Set the PLL I2S clock -----------------------------/
sahilmgandhi	18:6a4db94011d3	1318	__HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
sahilmgandhi	18:6a4db94011d3	1319
sahilmgandhi	18:6a4db94011d3	1320	/------- In Case of PLLI2S is selected as source clock for I2S ----------/
sahilmgandhi	18:6a4db94011d3	1321	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
sahilmgandhi	18:6a4db94011d3	1322	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) \|\|
sahilmgandhi	18:6a4db94011d3	1323	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) \|\|
sahilmgandhi	18:6a4db94011d3	1324	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
sahilmgandhi	18:6a4db94011d3	1325	{
sahilmgandhi	18:6a4db94011d3	1326	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	1327	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
sahilmgandhi	18:6a4db94011d3	1328
sahilmgandhi	18:6a4db94011d3	1329	/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
sahilmgandhi	18:6a4db94011d3	1330	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	1331	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	1332	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
sahilmgandhi	18:6a4db94011d3	1333	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
sahilmgandhi	18:6a4db94011d3	1334	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	1335	}
sahilmgandhi	18:6a4db94011d3	1336
sahilmgandhi	18:6a4db94011d3	1337	/----------------- In Case of PLLI2S is just selected ------------------/
sahilmgandhi	18:6a4db94011d3	1338	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
sahilmgandhi	18:6a4db94011d3	1339	{
sahilmgandhi	18:6a4db94011d3	1340	/* Check for Parameters */
sahilmgandhi	18:6a4db94011d3	1341	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
sahilmgandhi	18:6a4db94011d3	1342	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	1343
sahilmgandhi	18:6a4db94011d3	1344	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	1345	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
sahilmgandhi	18:6a4db94011d3	1346	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
sahilmgandhi	18:6a4db94011d3	1347	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	1348	}
sahilmgandhi	18:6a4db94011d3	1349
sahilmgandhi	18:6a4db94011d3	1350	/* Enable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	1351	__HAL_RCC_PLLI2S_ENABLE();
sahilmgandhi	18:6a4db94011d3	1352	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1353	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1354	/* Wait till PLLI2S is ready */
sahilmgandhi	18:6a4db94011d3	1355	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
sahilmgandhi	18:6a4db94011d3	1356	{
sahilmgandhi	18:6a4db94011d3	1357	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1358	{
sahilmgandhi	18:6a4db94011d3	1359	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1360	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1361	}
sahilmgandhi	18:6a4db94011d3	1362	}
sahilmgandhi	18:6a4db94011d3	1363	}
sahilmgandhi	18:6a4db94011d3	1364	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1365
sahilmgandhi	18:6a4db94011d3	1366	/-------------------- DFSDM1 clock source configuration -------------------/
sahilmgandhi	18:6a4db94011d3	1367	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
sahilmgandhi	18:6a4db94011d3	1368	{
sahilmgandhi	18:6a4db94011d3	1369	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1370	assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
sahilmgandhi	18:6a4db94011d3	1371
sahilmgandhi	18:6a4db94011d3	1372	/* Configure the DFSDM1 interface clock source */
sahilmgandhi	18:6a4db94011d3	1373	__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
sahilmgandhi	18:6a4db94011d3	1374	}
sahilmgandhi	18:6a4db94011d3	1375	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1376
sahilmgandhi	18:6a4db94011d3	1377	/-------------------- DFSDM1 Audio clock source configuration -------------/
sahilmgandhi	18:6a4db94011d3	1378	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
sahilmgandhi	18:6a4db94011d3	1379	{
sahilmgandhi	18:6a4db94011d3	1380	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1381	assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
sahilmgandhi	18:6a4db94011d3	1382
sahilmgandhi	18:6a4db94011d3	1383	/* Configure the DFSDM1 Audio interface clock source */
sahilmgandhi	18:6a4db94011d3	1384	__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
sahilmgandhi	18:6a4db94011d3	1385	}
sahilmgandhi	18:6a4db94011d3	1386
sahilmgandhi	18:6a4db94011d3	1387	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1388	}
sahilmgandhi	18:6a4db94011d3	1389
sahilmgandhi	18:6a4db94011d3	1390	/**
sahilmgandhi	18:6a4db94011d3	1391	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
sahilmgandhi	18:6a4db94011d3	1392	* RCC configuration registers.
sahilmgandhi	18:6a4db94011d3	1393	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	1394	* will be configured.
sahilmgandhi	18:6a4db94011d3	1395	* @retval None
sahilmgandhi	18:6a4db94011d3	1396	*/
sahilmgandhi	18:6a4db94011d3	1397	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	1398	{
sahilmgandhi	18:6a4db94011d3	1399	uint32_t tempreg;
sahilmgandhi	18:6a4db94011d3	1400
sahilmgandhi	18:6a4db94011d3	1401	/* Set all possible values for the extended clock type parameter------------*/
sahilmgandhi	18:6a4db94011d3	1402	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
sahilmgandhi	18:6a4db94011d3	1403	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
sahilmgandhi	18:6a4db94011d3	1404	RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_CLK48 \|\
sahilmgandhi	18:6a4db94011d3	1405	RCC_PERIPHCLK_SDIO;
sahilmgandhi	18:6a4db94011d3	1406
sahilmgandhi	18:6a4db94011d3	1407	/* Get the PLLI2S Clock configuration --------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1408	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
sahilmgandhi	18:6a4db94011d3	1409	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
sahilmgandhi	18:6a4db94011d3	1410	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	1411	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	1412
sahilmgandhi	18:6a4db94011d3	1413	/* Get the I2S APB1 clock configuration ------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1414	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
sahilmgandhi	18:6a4db94011d3	1415
sahilmgandhi	18:6a4db94011d3	1416	/* Get the I2S APB2 clock configuration ------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1417	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
sahilmgandhi	18:6a4db94011d3	1418
sahilmgandhi	18:6a4db94011d3	1419	/* Get the RTC Clock configuration -----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1420	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
sahilmgandhi	18:6a4db94011d3	1421	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1422
sahilmgandhi	18:6a4db94011d3	1423	/* Get the FMPI2C1 clock configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1424	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
sahilmgandhi	18:6a4db94011d3	1425
sahilmgandhi	18:6a4db94011d3	1426	/* Get the CLK48 clock configuration ----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1427	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
sahilmgandhi	18:6a4db94011d3	1428
sahilmgandhi	18:6a4db94011d3	1429	/* Get the SDIO clock configuration ----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1430	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
sahilmgandhi	18:6a4db94011d3	1431
sahilmgandhi	18:6a4db94011d3	1432	/* Get the TIM Prescaler configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1433	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
sahilmgandhi	18:6a4db94011d3	1434	{
sahilmgandhi	18:6a4db94011d3	1435	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
sahilmgandhi	18:6a4db94011d3	1436	}
sahilmgandhi	18:6a4db94011d3	1437	else
sahilmgandhi	18:6a4db94011d3	1438	{
sahilmgandhi	18:6a4db94011d3	1439	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
sahilmgandhi	18:6a4db94011d3	1440	}
sahilmgandhi	18:6a4db94011d3	1441	}
sahilmgandhi	18:6a4db94011d3	1442	#endif /* STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	1443
sahilmgandhi	18:6a4db94011d3	1444	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	1445	/**
sahilmgandhi	18:6a4db94011d3	1446	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
sahilmgandhi	18:6a4db94011d3	1447	* RCC_PeriphCLKInitTypeDef.
sahilmgandhi	18:6a4db94011d3	1448	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	1449	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
sahilmgandhi	18:6a4db94011d3	1450	*
sahilmgandhi	18:6a4db94011d3	1451	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
sahilmgandhi	18:6a4db94011d3	1452	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
sahilmgandhi	18:6a4db94011d3	1453	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
sahilmgandhi	18:6a4db94011d3	1454	*
sahilmgandhi	18:6a4db94011d3	1455	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1456	*/
sahilmgandhi	18:6a4db94011d3	1457	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	1458	{
sahilmgandhi	18:6a4db94011d3	1459	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1460	uint32_t tmpreg1 = 0U;
sahilmgandhi	18:6a4db94011d3	1461
sahilmgandhi	18:6a4db94011d3	1462	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1463	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
sahilmgandhi	18:6a4db94011d3	1464
sahilmgandhi	18:6a4db94011d3	1465	/---------------------------- RTC configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1466	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
sahilmgandhi	18:6a4db94011d3	1467	{
sahilmgandhi	18:6a4db94011d3	1468	/* Check for RTC Parameters used to output RTCCLK */
sahilmgandhi	18:6a4db94011d3	1469	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
sahilmgandhi	18:6a4db94011d3	1470
sahilmgandhi	18:6a4db94011d3	1471	/* Enable Power Clock*/
sahilmgandhi	18:6a4db94011d3	1472	__HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	1473
sahilmgandhi	18:6a4db94011d3	1474	/* Enable write access to Backup domain */
sahilmgandhi	18:6a4db94011d3	1475	PWR->CR \|= PWR_CR_DBP;
sahilmgandhi	18:6a4db94011d3	1476
sahilmgandhi	18:6a4db94011d3	1477	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1478	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1479
sahilmgandhi	18:6a4db94011d3	1480	while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi	18:6a4db94011d3	1481	{
sahilmgandhi	18:6a4db94011d3	1482	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1483	{
sahilmgandhi	18:6a4db94011d3	1484	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1485	}
sahilmgandhi	18:6a4db94011d3	1486	}
sahilmgandhi	18:6a4db94011d3	1487	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
sahilmgandhi	18:6a4db94011d3	1488	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
sahilmgandhi	18:6a4db94011d3	1489	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
sahilmgandhi	18:6a4db94011d3	1490	{
sahilmgandhi	18:6a4db94011d3	1491	/* Store the content of BDCR register before the reset of Backup Domain */
sahilmgandhi	18:6a4db94011d3	1492	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1493	/* RTC Clock selection can be changed only if the Backup Domain is reset */
sahilmgandhi	18:6a4db94011d3	1494	__HAL_RCC_BACKUPRESET_FORCE();
sahilmgandhi	18:6a4db94011d3	1495	__HAL_RCC_BACKUPRESET_RELEASE();
sahilmgandhi	18:6a4db94011d3	1496	/* Restore the Content of BDCR register */
sahilmgandhi	18:6a4db94011d3	1497	RCC->BDCR = tmpreg1;
sahilmgandhi	18:6a4db94011d3	1498
sahilmgandhi	18:6a4db94011d3	1499	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
sahilmgandhi	18:6a4db94011d3	1500	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
sahilmgandhi	18:6a4db94011d3	1501	{
sahilmgandhi	18:6a4db94011d3	1502	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1503	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1504
sahilmgandhi	18:6a4db94011d3	1505	/* Wait till LSE is ready */
sahilmgandhi	18:6a4db94011d3	1506	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi	18:6a4db94011d3	1507	{
sahilmgandhi	18:6a4db94011d3	1508	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1509	{
sahilmgandhi	18:6a4db94011d3	1510	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1511	}
sahilmgandhi	18:6a4db94011d3	1512	}
sahilmgandhi	18:6a4db94011d3	1513	}
sahilmgandhi	18:6a4db94011d3	1514	}
sahilmgandhi	18:6a4db94011d3	1515	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
sahilmgandhi	18:6a4db94011d3	1516	}
sahilmgandhi	18:6a4db94011d3	1517	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1518
sahilmgandhi	18:6a4db94011d3	1519	/---------------------------- TIM configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1520	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
sahilmgandhi	18:6a4db94011d3	1521	{
sahilmgandhi	18:6a4db94011d3	1522	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
sahilmgandhi	18:6a4db94011d3	1523	}
sahilmgandhi	18:6a4db94011d3	1524	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1525
sahilmgandhi	18:6a4db94011d3	1526	/---------------------------- FMPI2C1 Configuration -----------------------/
sahilmgandhi	18:6a4db94011d3	1527	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
sahilmgandhi	18:6a4db94011d3	1528	{
sahilmgandhi	18:6a4db94011d3	1529	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1530	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
sahilmgandhi	18:6a4db94011d3	1531
sahilmgandhi	18:6a4db94011d3	1532	/* Configure the FMPI2C1 clock source */
sahilmgandhi	18:6a4db94011d3	1533	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
sahilmgandhi	18:6a4db94011d3	1534	}
sahilmgandhi	18:6a4db94011d3	1535	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1536
sahilmgandhi	18:6a4db94011d3	1537	/---------------------------- LPTIM1 Configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	1538	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
sahilmgandhi	18:6a4db94011d3	1539	{
sahilmgandhi	18:6a4db94011d3	1540	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1541	assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
sahilmgandhi	18:6a4db94011d3	1542
sahilmgandhi	18:6a4db94011d3	1543	/* Configure the LPTIM1 clock source */
sahilmgandhi	18:6a4db94011d3	1544	__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
sahilmgandhi	18:6a4db94011d3	1545	}
sahilmgandhi	18:6a4db94011d3	1546
sahilmgandhi	18:6a4db94011d3	1547	/---------------------------- I2S Configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	1548	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
sahilmgandhi	18:6a4db94011d3	1549	{
sahilmgandhi	18:6a4db94011d3	1550	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1551	assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
sahilmgandhi	18:6a4db94011d3	1552
sahilmgandhi	18:6a4db94011d3	1553	/* Configure the I2S clock source */
sahilmgandhi	18:6a4db94011d3	1554	__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
sahilmgandhi	18:6a4db94011d3	1555	}
sahilmgandhi	18:6a4db94011d3	1556
sahilmgandhi	18:6a4db94011d3	1557	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1558	}
sahilmgandhi	18:6a4db94011d3	1559
sahilmgandhi	18:6a4db94011d3	1560	/**
sahilmgandhi	18:6a4db94011d3	1561	* @brief Configures the RCC_OscInitStruct according to the internal
sahilmgandhi	18:6a4db94011d3	1562	* RCC configuration registers.
sahilmgandhi	18:6a4db94011d3	1563	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	1564	* will be configured.
sahilmgandhi	18:6a4db94011d3	1565	* @retval None
sahilmgandhi	18:6a4db94011d3	1566	*/
sahilmgandhi	18:6a4db94011d3	1567	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	1568	{
sahilmgandhi	18:6a4db94011d3	1569	uint32_t tempreg;
sahilmgandhi	18:6a4db94011d3	1570
sahilmgandhi	18:6a4db94011d3	1571	/* Set all possible values for the extended clock type parameter------------*/
sahilmgandhi	18:6a4db94011d3	1572	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
sahilmgandhi	18:6a4db94011d3	1573
sahilmgandhi	18:6a4db94011d3	1574	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
sahilmgandhi	18:6a4db94011d3	1575	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1576
sahilmgandhi	18:6a4db94011d3	1577	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
sahilmgandhi	18:6a4db94011d3	1578	{
sahilmgandhi	18:6a4db94011d3	1579	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
sahilmgandhi	18:6a4db94011d3	1580	}
sahilmgandhi	18:6a4db94011d3	1581	else
sahilmgandhi	18:6a4db94011d3	1582	{
sahilmgandhi	18:6a4db94011d3	1583	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
sahilmgandhi	18:6a4db94011d3	1584	}
sahilmgandhi	18:6a4db94011d3	1585	/* Get the FMPI2C1 clock configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1586	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
sahilmgandhi	18:6a4db94011d3	1587
sahilmgandhi	18:6a4db94011d3	1588	/* Get the I2S clock configuration -----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1589	PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
sahilmgandhi	18:6a4db94011d3	1590
sahilmgandhi	18:6a4db94011d3	1591
sahilmgandhi	18:6a4db94011d3	1592	}
sahilmgandhi	18:6a4db94011d3	1593	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	1594
sahilmgandhi	18:6a4db94011d3	1595	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
sahilmgandhi	18:6a4db94011d3	1596	/**
sahilmgandhi	18:6a4db94011d3	1597	* @brief Initializes the RCC extended peripherals clocks according to the specified
sahilmgandhi	18:6a4db94011d3	1598	* parameters in the RCC_PeriphCLKInitTypeDef.
sahilmgandhi	18:6a4db94011d3	1599	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	1600	* contains the configuration information for the Extended Peripherals
sahilmgandhi	18:6a4db94011d3	1601	* clocks(I2S, SAI, LTDC RTC and TIM).
sahilmgandhi	18:6a4db94011d3	1602	*
sahilmgandhi	18:6a4db94011d3	1603	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
sahilmgandhi	18:6a4db94011d3	1604	* the RTC clock source; in this case the Backup domain will be reset in
sahilmgandhi	18:6a4db94011d3	1605	* order to modify the RTC Clock source, as consequence RTC registers (including
sahilmgandhi	18:6a4db94011d3	1606	* the backup registers) and RCC_BDCR register are set to their reset values.
sahilmgandhi	18:6a4db94011d3	1607	*
sahilmgandhi	18:6a4db94011d3	1608	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1609	*/
sahilmgandhi	18:6a4db94011d3	1610	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	1611	{
sahilmgandhi	18:6a4db94011d3	1612	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1613	uint32_t tmpreg1 = 0U;
sahilmgandhi	18:6a4db94011d3	1614
sahilmgandhi	18:6a4db94011d3	1615	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1616	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
sahilmgandhi	18:6a4db94011d3	1617
sahilmgandhi	18:6a4db94011d3	1618	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------/
sahilmgandhi	18:6a4db94011d3	1619	/----------------------- Common configuration SAI/I2S ----------------------/
sahilmgandhi	18:6a4db94011d3	1620	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
sahilmgandhi	18:6a4db94011d3	1621	factor is common parameters for both peripherals */
sahilmgandhi	18:6a4db94011d3	1622	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
sahilmgandhi	18:6a4db94011d3	1623	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
sahilmgandhi	18:6a4db94011d3	1624	{
sahilmgandhi	18:6a4db94011d3	1625	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	1626	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
sahilmgandhi	18:6a4db94011d3	1627
sahilmgandhi	18:6a4db94011d3	1628	/* Disable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	1629	__HAL_RCC_PLLI2S_DISABLE();
sahilmgandhi	18:6a4db94011d3	1630	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1631	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1632	/* Wait till PLLI2S is disabled */
sahilmgandhi	18:6a4db94011d3	1633	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	1634	{
sahilmgandhi	18:6a4db94011d3	1635	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1636	{
sahilmgandhi	18:6a4db94011d3	1637	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1638	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1639	}
sahilmgandhi	18:6a4db94011d3	1640	}
sahilmgandhi	18:6a4db94011d3	1641
sahilmgandhi	18:6a4db94011d3	1642	/---------------------------- I2S configuration -------------------------------/
sahilmgandhi	18:6a4db94011d3	1643	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
sahilmgandhi	18:6a4db94011d3	1644	only for I2S configuration */
sahilmgandhi	18:6a4db94011d3	1645	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
sahilmgandhi	18:6a4db94011d3	1646	{
sahilmgandhi	18:6a4db94011d3	1647	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	1648	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
sahilmgandhi	18:6a4db94011d3	1649	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	1650	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
sahilmgandhi	18:6a4db94011d3	1651	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
sahilmgandhi	18:6a4db94011d3	1652	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	1653	}
sahilmgandhi	18:6a4db94011d3	1654
sahilmgandhi	18:6a4db94011d3	1655	/---------------------------- SAI configuration -------------------------------/
sahilmgandhi	18:6a4db94011d3	1656	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
sahilmgandhi	18:6a4db94011d3	1657	be added only for SAI configuration */
sahilmgandhi	18:6a4db94011d3	1658	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
sahilmgandhi	18:6a4db94011d3	1659	{
sahilmgandhi	18:6a4db94011d3	1660	/* Check the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	1661	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	1662	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
sahilmgandhi	18:6a4db94011d3	1663
sahilmgandhi	18:6a4db94011d3	1664	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	1665	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	1666	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	1667	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	1668	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
sahilmgandhi	18:6a4db94011d3	1669	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
sahilmgandhi	18:6a4db94011d3	1670	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
sahilmgandhi	18:6a4db94011d3	1671	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
sahilmgandhi	18:6a4db94011d3	1672	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
sahilmgandhi	18:6a4db94011d3	1673	}
sahilmgandhi	18:6a4db94011d3	1674
sahilmgandhi	18:6a4db94011d3	1675	/* Enable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	1676	__HAL_RCC_PLLI2S_ENABLE();
sahilmgandhi	18:6a4db94011d3	1677	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1678	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1679	/* Wait till PLLI2S is ready */
sahilmgandhi	18:6a4db94011d3	1680	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
sahilmgandhi	18:6a4db94011d3	1681	{
sahilmgandhi	18:6a4db94011d3	1682	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1683	{
sahilmgandhi	18:6a4db94011d3	1684	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1685	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1686	}
sahilmgandhi	18:6a4db94011d3	1687	}
sahilmgandhi	18:6a4db94011d3	1688	}
sahilmgandhi	18:6a4db94011d3	1689	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1690
sahilmgandhi	18:6a4db94011d3	1691	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
sahilmgandhi	18:6a4db94011d3	1692	/----------------------- Common configuration SAI/LTDC --------------------/
sahilmgandhi	18:6a4db94011d3	1693	/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
sahilmgandhi	18:6a4db94011d3	1694	factor is common parameters for both peripherals */
sahilmgandhi	18:6a4db94011d3	1695	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
sahilmgandhi	18:6a4db94011d3	1696	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
sahilmgandhi	18:6a4db94011d3	1697	{
sahilmgandhi	18:6a4db94011d3	1698	/* Check the PLLSAI division factors */
sahilmgandhi	18:6a4db94011d3	1699	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
sahilmgandhi	18:6a4db94011d3	1700
sahilmgandhi	18:6a4db94011d3	1701	/* Disable PLLSAI Clock */
sahilmgandhi	18:6a4db94011d3	1702	__HAL_RCC_PLLSAI_DISABLE();
sahilmgandhi	18:6a4db94011d3	1703	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1704	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1705	/* Wait till PLLSAI is disabled */
sahilmgandhi	18:6a4db94011d3	1706	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
sahilmgandhi	18:6a4db94011d3	1707	{
sahilmgandhi	18:6a4db94011d3	1708	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1709	{
sahilmgandhi	18:6a4db94011d3	1710	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1711	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1712	}
sahilmgandhi	18:6a4db94011d3	1713	}
sahilmgandhi	18:6a4db94011d3	1714
sahilmgandhi	18:6a4db94011d3	1715	/---------------------------- SAI configuration -------------------------/
sahilmgandhi	18:6a4db94011d3	1716	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
sahilmgandhi	18:6a4db94011d3	1717	be added only for SAI configuration */
sahilmgandhi	18:6a4db94011d3	1718	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
sahilmgandhi	18:6a4db94011d3	1719	{
sahilmgandhi	18:6a4db94011d3	1720	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	1721	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
sahilmgandhi	18:6a4db94011d3	1722
sahilmgandhi	18:6a4db94011d3	1723	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	1724	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
sahilmgandhi	18:6a4db94011d3	1725	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	1726	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
sahilmgandhi	18:6a4db94011d3	1727	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
sahilmgandhi	18:6a4db94011d3	1728	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
sahilmgandhi	18:6a4db94011d3	1729	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
sahilmgandhi	18:6a4db94011d3	1730	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
sahilmgandhi	18:6a4db94011d3	1731	}
sahilmgandhi	18:6a4db94011d3	1732
sahilmgandhi	18:6a4db94011d3	1733	/---------------------------- LTDC configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	1734	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
sahilmgandhi	18:6a4db94011d3	1735	{
sahilmgandhi	18:6a4db94011d3	1736	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
sahilmgandhi	18:6a4db94011d3	1737	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
sahilmgandhi	18:6a4db94011d3	1738
sahilmgandhi	18:6a4db94011d3	1739	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
sahilmgandhi	18:6a4db94011d3	1740	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	1741	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi	18:6a4db94011d3	1742	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
sahilmgandhi	18:6a4db94011d3	1743	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
sahilmgandhi	18:6a4db94011d3	1744	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
sahilmgandhi	18:6a4db94011d3	1745	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
sahilmgandhi	18:6a4db94011d3	1746	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
sahilmgandhi	18:6a4db94011d3	1747	}
sahilmgandhi	18:6a4db94011d3	1748	/* Enable PLLSAI Clock */
sahilmgandhi	18:6a4db94011d3	1749	__HAL_RCC_PLLSAI_ENABLE();
sahilmgandhi	18:6a4db94011d3	1750	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1751	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1752	/* Wait till PLLSAI is ready */
sahilmgandhi	18:6a4db94011d3	1753	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
sahilmgandhi	18:6a4db94011d3	1754	{
sahilmgandhi	18:6a4db94011d3	1755	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1756	{
sahilmgandhi	18:6a4db94011d3	1757	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1758	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1759	}
sahilmgandhi	18:6a4db94011d3	1760	}
sahilmgandhi	18:6a4db94011d3	1761	}
sahilmgandhi	18:6a4db94011d3	1762	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1763
sahilmgandhi	18:6a4db94011d3	1764	/---------------------------- RTC configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1765	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
sahilmgandhi	18:6a4db94011d3	1766	{
sahilmgandhi	18:6a4db94011d3	1767	/* Check for RTC Parameters used to output RTCCLK */
sahilmgandhi	18:6a4db94011d3	1768	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
sahilmgandhi	18:6a4db94011d3	1769
sahilmgandhi	18:6a4db94011d3	1770	/* Enable Power Clock*/
sahilmgandhi	18:6a4db94011d3	1771	__HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	1772
sahilmgandhi	18:6a4db94011d3	1773	/* Enable write access to Backup domain */
sahilmgandhi	18:6a4db94011d3	1774	PWR->CR \|= PWR_CR_DBP;
sahilmgandhi	18:6a4db94011d3	1775
sahilmgandhi	18:6a4db94011d3	1776	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1777	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1778
sahilmgandhi	18:6a4db94011d3	1779	while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi	18:6a4db94011d3	1780	{
sahilmgandhi	18:6a4db94011d3	1781	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1782	{
sahilmgandhi	18:6a4db94011d3	1783	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1784	}
sahilmgandhi	18:6a4db94011d3	1785	}
sahilmgandhi	18:6a4db94011d3	1786	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
sahilmgandhi	18:6a4db94011d3	1787	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
sahilmgandhi	18:6a4db94011d3	1788	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
sahilmgandhi	18:6a4db94011d3	1789	{
sahilmgandhi	18:6a4db94011d3	1790	/* Store the content of BDCR register before the reset of Backup Domain */
sahilmgandhi	18:6a4db94011d3	1791	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1792	/* RTC Clock selection can be changed only if the Backup Domain is reset */
sahilmgandhi	18:6a4db94011d3	1793	__HAL_RCC_BACKUPRESET_FORCE();
sahilmgandhi	18:6a4db94011d3	1794	__HAL_RCC_BACKUPRESET_RELEASE();
sahilmgandhi	18:6a4db94011d3	1795	/* Restore the Content of BDCR register */
sahilmgandhi	18:6a4db94011d3	1796	RCC->BDCR = tmpreg1;
sahilmgandhi	18:6a4db94011d3	1797
sahilmgandhi	18:6a4db94011d3	1798	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
sahilmgandhi	18:6a4db94011d3	1799	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
sahilmgandhi	18:6a4db94011d3	1800	{
sahilmgandhi	18:6a4db94011d3	1801	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1802	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1803
sahilmgandhi	18:6a4db94011d3	1804	/* Wait till LSE is ready */
sahilmgandhi	18:6a4db94011d3	1805	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi	18:6a4db94011d3	1806	{
sahilmgandhi	18:6a4db94011d3	1807	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1808	{
sahilmgandhi	18:6a4db94011d3	1809	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1810	}
sahilmgandhi	18:6a4db94011d3	1811	}
sahilmgandhi	18:6a4db94011d3	1812	}
sahilmgandhi	18:6a4db94011d3	1813	}
sahilmgandhi	18:6a4db94011d3	1814	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
sahilmgandhi	18:6a4db94011d3	1815	}
sahilmgandhi	18:6a4db94011d3	1816	/--------------------------------------------------------------------------/
sahilmgandhi	18:6a4db94011d3	1817
sahilmgandhi	18:6a4db94011d3	1818	/---------------------------- TIM configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1819	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
sahilmgandhi	18:6a4db94011d3	1820	{
sahilmgandhi	18:6a4db94011d3	1821	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
sahilmgandhi	18:6a4db94011d3	1822	}
sahilmgandhi	18:6a4db94011d3	1823	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1824	}
sahilmgandhi	18:6a4db94011d3	1825
sahilmgandhi	18:6a4db94011d3	1826	/**
sahilmgandhi	18:6a4db94011d3	1827	* @brief Configures the PeriphClkInit according to the internal
sahilmgandhi	18:6a4db94011d3	1828	* RCC configuration registers.
sahilmgandhi	18:6a4db94011d3	1829	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	1830	* will be configured.
sahilmgandhi	18:6a4db94011d3	1831	* @retval None
sahilmgandhi	18:6a4db94011d3	1832	*/
sahilmgandhi	18:6a4db94011d3	1833	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	1834	{
sahilmgandhi	18:6a4db94011d3	1835	uint32_t tempreg;
sahilmgandhi	18:6a4db94011d3	1836
sahilmgandhi	18:6a4db94011d3	1837	/* Set all possible values for the extended clock type parameter------------*/
sahilmgandhi	18:6a4db94011d3	1838	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \| RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
sahilmgandhi	18:6a4db94011d3	1839
sahilmgandhi	18:6a4db94011d3	1840	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1841	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
sahilmgandhi	18:6a4db94011d3	1842	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	1843	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
sahilmgandhi	18:6a4db94011d3	1844	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1845	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
sahilmgandhi	18:6a4db94011d3	1846	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
sahilmgandhi	18:6a4db94011d3	1847	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
sahilmgandhi	18:6a4db94011d3	1848	/* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1849	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
sahilmgandhi	18:6a4db94011d3	1850	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
sahilmgandhi	18:6a4db94011d3	1851	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
sahilmgandhi	18:6a4db94011d3	1852	/* Get the RTC Clock configuration -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1853	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
sahilmgandhi	18:6a4db94011d3	1854	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1855
sahilmgandhi	18:6a4db94011d3	1856	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
sahilmgandhi	18:6a4db94011d3	1857	{
sahilmgandhi	18:6a4db94011d3	1858	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
sahilmgandhi	18:6a4db94011d3	1859	}
sahilmgandhi	18:6a4db94011d3	1860	else
sahilmgandhi	18:6a4db94011d3	1861	{
sahilmgandhi	18:6a4db94011d3	1862	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
sahilmgandhi	18:6a4db94011d3	1863	}
sahilmgandhi	18:6a4db94011d3	1864	}
sahilmgandhi	18:6a4db94011d3	1865
sahilmgandhi	18:6a4db94011d3	1866	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
sahilmgandhi	18:6a4db94011d3	1867
sahilmgandhi	18:6a4db94011d3	1868	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
sahilmgandhi	18:6a4db94011d3	1869	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	1870	/**
sahilmgandhi	18:6a4db94011d3	1871	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
sahilmgandhi	18:6a4db94011d3	1872	* RCC_PeriphCLKInitTypeDef.
sahilmgandhi	18:6a4db94011d3	1873	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	1874	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
sahilmgandhi	18:6a4db94011d3	1875	*
sahilmgandhi	18:6a4db94011d3	1876	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
sahilmgandhi	18:6a4db94011d3	1877	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
sahilmgandhi	18:6a4db94011d3	1878	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
sahilmgandhi	18:6a4db94011d3	1879	*
sahilmgandhi	18:6a4db94011d3	1880	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1881	*/
sahilmgandhi	18:6a4db94011d3	1882	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	1883	{
sahilmgandhi	18:6a4db94011d3	1884	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	1885	uint32_t tmpreg1 = 0U;
sahilmgandhi	18:6a4db94011d3	1886
sahilmgandhi	18:6a4db94011d3	1887	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1888	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
sahilmgandhi	18:6a4db94011d3	1889
sahilmgandhi	18:6a4db94011d3	1890	/---------------------------- I2S configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1891	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
sahilmgandhi	18:6a4db94011d3	1892	{
sahilmgandhi	18:6a4db94011d3	1893	/* check for Parameters */
sahilmgandhi	18:6a4db94011d3	1894	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
sahilmgandhi	18:6a4db94011d3	1895	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
sahilmgandhi	18:6a4db94011d3	1896	#if defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	1897	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
sahilmgandhi	18:6a4db94011d3	1898	#endif /* STM32F411xE */
sahilmgandhi	18:6a4db94011d3	1899	/* Disable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	1900	__HAL_RCC_PLLI2S_DISABLE();
sahilmgandhi	18:6a4db94011d3	1901	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1902	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1903	/* Wait till PLLI2S is disabled */
sahilmgandhi	18:6a4db94011d3	1904	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	1905	{
sahilmgandhi	18:6a4db94011d3	1906	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1907	{
sahilmgandhi	18:6a4db94011d3	1908	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1909	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1910	}
sahilmgandhi	18:6a4db94011d3	1911	}
sahilmgandhi	18:6a4db94011d3	1912
sahilmgandhi	18:6a4db94011d3	1913	#if defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	1914	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	1915	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
sahilmgandhi	18:6a4db94011d3	1916	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
sahilmgandhi	18:6a4db94011d3	1917	__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	1918	#else
sahilmgandhi	18:6a4db94011d3	1919	/* Configure the PLLI2S division factors */
sahilmgandhi	18:6a4db94011d3	1920	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
sahilmgandhi	18:6a4db94011d3	1921	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
sahilmgandhi	18:6a4db94011d3	1922	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
sahilmgandhi	18:6a4db94011d3	1923	#endif /* STM32F411xE */
sahilmgandhi	18:6a4db94011d3	1924
sahilmgandhi	18:6a4db94011d3	1925	/* Enable the PLLI2S */
sahilmgandhi	18:6a4db94011d3	1926	__HAL_RCC_PLLI2S_ENABLE();
sahilmgandhi	18:6a4db94011d3	1927	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1928	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1929	/* Wait till PLLI2S is ready */
sahilmgandhi	18:6a4db94011d3	1930	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
sahilmgandhi	18:6a4db94011d3	1931	{
sahilmgandhi	18:6a4db94011d3	1932	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1933	{
sahilmgandhi	18:6a4db94011d3	1934	/* return in case of Timeout detected */
sahilmgandhi	18:6a4db94011d3	1935	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1936	}
sahilmgandhi	18:6a4db94011d3	1937	}
sahilmgandhi	18:6a4db94011d3	1938	}
sahilmgandhi	18:6a4db94011d3	1939
sahilmgandhi	18:6a4db94011d3	1940	/---------------------------- RTC configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1941	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
sahilmgandhi	18:6a4db94011d3	1942	{
sahilmgandhi	18:6a4db94011d3	1943	/* Check for RTC Parameters used to output RTCCLK */
sahilmgandhi	18:6a4db94011d3	1944	assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
sahilmgandhi	18:6a4db94011d3	1945
sahilmgandhi	18:6a4db94011d3	1946	/* Enable Power Clock*/
sahilmgandhi	18:6a4db94011d3	1947	__HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	1948
sahilmgandhi	18:6a4db94011d3	1949	/* Enable write access to Backup domain */
sahilmgandhi	18:6a4db94011d3	1950	PWR->CR \|= PWR_CR_DBP;
sahilmgandhi	18:6a4db94011d3	1951
sahilmgandhi	18:6a4db94011d3	1952	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1953	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1954
sahilmgandhi	18:6a4db94011d3	1955	while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi	18:6a4db94011d3	1956	{
sahilmgandhi	18:6a4db94011d3	1957	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1958	{
sahilmgandhi	18:6a4db94011d3	1959	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1960	}
sahilmgandhi	18:6a4db94011d3	1961	}
sahilmgandhi	18:6a4db94011d3	1962	/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
sahilmgandhi	18:6a4db94011d3	1963	tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
sahilmgandhi	18:6a4db94011d3	1964	if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
sahilmgandhi	18:6a4db94011d3	1965	{
sahilmgandhi	18:6a4db94011d3	1966	/* Store the content of BDCR register before the reset of Backup Domain */
sahilmgandhi	18:6a4db94011d3	1967	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	1968	/* RTC Clock selection can be changed only if the Backup Domain is reset */
sahilmgandhi	18:6a4db94011d3	1969	__HAL_RCC_BACKUPRESET_FORCE();
sahilmgandhi	18:6a4db94011d3	1970	__HAL_RCC_BACKUPRESET_RELEASE();
sahilmgandhi	18:6a4db94011d3	1971	/* Restore the Content of BDCR register */
sahilmgandhi	18:6a4db94011d3	1972	RCC->BDCR = tmpreg1;
sahilmgandhi	18:6a4db94011d3	1973
sahilmgandhi	18:6a4db94011d3	1974	/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
sahilmgandhi	18:6a4db94011d3	1975	if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
sahilmgandhi	18:6a4db94011d3	1976	{
sahilmgandhi	18:6a4db94011d3	1977	/* Get tick */
sahilmgandhi	18:6a4db94011d3	1978	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	1979
sahilmgandhi	18:6a4db94011d3	1980	/* Wait till LSE is ready */
sahilmgandhi	18:6a4db94011d3	1981	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi	18:6a4db94011d3	1982	{
sahilmgandhi	18:6a4db94011d3	1983	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	1984	{
sahilmgandhi	18:6a4db94011d3	1985	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	1986	}
sahilmgandhi	18:6a4db94011d3	1987	}
sahilmgandhi	18:6a4db94011d3	1988	}
sahilmgandhi	18:6a4db94011d3	1989	}
sahilmgandhi	18:6a4db94011d3	1990	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
sahilmgandhi	18:6a4db94011d3	1991	}
sahilmgandhi	18:6a4db94011d3	1992	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	1993	/---------------------------- TIM configuration ---------------------------/
sahilmgandhi	18:6a4db94011d3	1994	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
sahilmgandhi	18:6a4db94011d3	1995	{
sahilmgandhi	18:6a4db94011d3	1996	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
sahilmgandhi	18:6a4db94011d3	1997	}
sahilmgandhi	18:6a4db94011d3	1998	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
sahilmgandhi	18:6a4db94011d3	1999	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2000	}
sahilmgandhi	18:6a4db94011d3	2001
sahilmgandhi	18:6a4db94011d3	2002	/**
sahilmgandhi	18:6a4db94011d3	2003	* @brief Configures the RCC_OscInitStruct according to the internal
sahilmgandhi	18:6a4db94011d3	2004	* RCC configuration registers.
sahilmgandhi	18:6a4db94011d3	2005	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	2006	* will be configured.
sahilmgandhi	18:6a4db94011d3	2007	* @retval None
sahilmgandhi	18:6a4db94011d3	2008	*/
sahilmgandhi	18:6a4db94011d3	2009	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
sahilmgandhi	18:6a4db94011d3	2010	{
sahilmgandhi	18:6a4db94011d3	2011	uint32_t tempreg;
sahilmgandhi	18:6a4db94011d3	2012
sahilmgandhi	18:6a4db94011d3	2013	/* Set all possible values for the extended clock type parameter------------*/
sahilmgandhi	18:6a4db94011d3	2014	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_RTC;
sahilmgandhi	18:6a4db94011d3	2015
sahilmgandhi	18:6a4db94011d3	2016	/* Get the PLLI2S Clock configuration --------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2017	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
sahilmgandhi	18:6a4db94011d3	2018	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
sahilmgandhi	18:6a4db94011d3	2019	#if defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	2020	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
sahilmgandhi	18:6a4db94011d3	2021	#endif /* STM32F411xE */
sahilmgandhi	18:6a4db94011d3	2022	/* Get the RTC Clock configuration -----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2023	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
sahilmgandhi	18:6a4db94011d3	2024	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
sahilmgandhi	18:6a4db94011d3	2025
sahilmgandhi	18:6a4db94011d3	2026	#if defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
sahilmgandhi	18:6a4db94011d3	2027	/* Get the TIM Prescaler configuration -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2028	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
sahilmgandhi	18:6a4db94011d3	2029	{
sahilmgandhi	18:6a4db94011d3	2030	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
sahilmgandhi	18:6a4db94011d3	2031	}
sahilmgandhi	18:6a4db94011d3	2032	else
sahilmgandhi	18:6a4db94011d3	2033	{
sahilmgandhi	18:6a4db94011d3	2034	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
sahilmgandhi	18:6a4db94011d3	2035	}
sahilmgandhi	18:6a4db94011d3	2036	#endif /* STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
sahilmgandhi	18:6a4db94011d3	2037	}
sahilmgandhi	18:6a4db94011d3	2038	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
sahilmgandhi	18:6a4db94011d3	2039
sahilmgandhi	18:6a4db94011d3	2040	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
sahilmgandhi	18:6a4db94011d3	2041	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	2042	/**
sahilmgandhi	18:6a4db94011d3	2043	* @brief Initializes the RCC Oscillators according to the specified parameters in the
sahilmgandhi	18:6a4db94011d3	2044	* RCC_OscInitTypeDef.
sahilmgandhi	18:6a4db94011d3	2045	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
sahilmgandhi	18:6a4db94011d3	2046	* contains the configuration information for the RCC Oscillators.
sahilmgandhi	18:6a4db94011d3	2047	* @note The PLL is not disabled when used as system clock.
sahilmgandhi	18:6a4db94011d3	2048	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
sahilmgandhi	18:6a4db94011d3	2049	* supported by this API. User should request a transition to LSE Off
sahilmgandhi	18:6a4db94011d3	2050	* first and then LSE On or LSE Bypass.
sahilmgandhi	18:6a4db94011d3	2051	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
sahilmgandhi	18:6a4db94011d3	2052	* supported by this API. User should request a transition to HSE Off
sahilmgandhi	18:6a4db94011d3	2053	* first and then HSE On or HSE Bypass.
sahilmgandhi	18:6a4db94011d3	2054	* @note This function add the PLL/PLLR factor management during PLL configuration this feature
sahilmgandhi	18:6a4db94011d3	2055	* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
sahilmgandhi	18:6a4db94011d3	2056	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	2057	*/
sahilmgandhi	18:6a4db94011d3	2058	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
sahilmgandhi	18:6a4db94011d3	2059	{
sahilmgandhi	18:6a4db94011d3	2060	uint32_t tickstart = 0U;
sahilmgandhi	18:6a4db94011d3	2061
sahilmgandhi	18:6a4db94011d3	2062	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2063	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sahilmgandhi	18:6a4db94011d3	2064	/------------------------------- HSE Configuration ------------------------/
sahilmgandhi	18:6a4db94011d3	2065	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
sahilmgandhi	18:6a4db94011d3	2066	{
sahilmgandhi	18:6a4db94011d3	2067	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2068	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
sahilmgandhi	18:6a4db94011d3	2069	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
sahilmgandhi	18:6a4db94011d3	2070	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	2071	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
sahilmgandhi	18:6a4db94011d3	2072	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) \|\|\
sahilmgandhi	18:6a4db94011d3	2073	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
sahilmgandhi	18:6a4db94011d3	2074	#else
sahilmgandhi	18:6a4db94011d3	2075	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
sahilmgandhi	18:6a4db94011d3	2076	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
sahilmgandhi	18:6a4db94011d3	2077	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	2078	{
sahilmgandhi	18:6a4db94011d3	2079	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
sahilmgandhi	18:6a4db94011d3	2080	{
sahilmgandhi	18:6a4db94011d3	2081	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	2082	}
sahilmgandhi	18:6a4db94011d3	2083	}
sahilmgandhi	18:6a4db94011d3	2084	else
sahilmgandhi	18:6a4db94011d3	2085	{
sahilmgandhi	18:6a4db94011d3	2086	/* Set the new HSE configuration ---------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2087	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
sahilmgandhi	18:6a4db94011d3	2088
sahilmgandhi	18:6a4db94011d3	2089	/* Check the HSE State */
sahilmgandhi	18:6a4db94011d3	2090	if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
sahilmgandhi	18:6a4db94011d3	2091	{
sahilmgandhi	18:6a4db94011d3	2092	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2093	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2094
sahilmgandhi	18:6a4db94011d3	2095	/* Wait till HSE is ready */
sahilmgandhi	18:6a4db94011d3	2096	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
sahilmgandhi	18:6a4db94011d3	2097	{
sahilmgandhi	18:6a4db94011d3	2098	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2099	{
sahilmgandhi	18:6a4db94011d3	2100	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2101	}
sahilmgandhi	18:6a4db94011d3	2102	}
sahilmgandhi	18:6a4db94011d3	2103	}
sahilmgandhi	18:6a4db94011d3	2104	else
sahilmgandhi	18:6a4db94011d3	2105	{
sahilmgandhi	18:6a4db94011d3	2106	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2107	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2108
sahilmgandhi	18:6a4db94011d3	2109	/* Wait till HSE is bypassed or disabled */
sahilmgandhi	18:6a4db94011d3	2110	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
sahilmgandhi	18:6a4db94011d3	2111	{
sahilmgandhi	18:6a4db94011d3	2112	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2113	{
sahilmgandhi	18:6a4db94011d3	2114	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2115	}
sahilmgandhi	18:6a4db94011d3	2116	}
sahilmgandhi	18:6a4db94011d3	2117	}
sahilmgandhi	18:6a4db94011d3	2118	}
sahilmgandhi	18:6a4db94011d3	2119	}
sahilmgandhi	18:6a4db94011d3	2120	/----------------------------- HSI Configuration --------------------------/
sahilmgandhi	18:6a4db94011d3	2121	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
sahilmgandhi	18:6a4db94011d3	2122	{
sahilmgandhi	18:6a4db94011d3	2123	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2124	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
sahilmgandhi	18:6a4db94011d3	2125	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
sahilmgandhi	18:6a4db94011d3	2126
sahilmgandhi	18:6a4db94011d3	2127	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
sahilmgandhi	18:6a4db94011d3	2128	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	2129	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
sahilmgandhi	18:6a4db94011d3	2130	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) \|\|\
sahilmgandhi	18:6a4db94011d3	2131	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
sahilmgandhi	18:6a4db94011d3	2132	#else
sahilmgandhi	18:6a4db94011d3	2133	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
sahilmgandhi	18:6a4db94011d3	2134	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
sahilmgandhi	18:6a4db94011d3	2135	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	2136	{
sahilmgandhi	18:6a4db94011d3	2137	/* When HSI is used as system clock it will not disabled */
sahilmgandhi	18:6a4db94011d3	2138	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
sahilmgandhi	18:6a4db94011d3	2139	{
sahilmgandhi	18:6a4db94011d3	2140	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	2141	}
sahilmgandhi	18:6a4db94011d3	2142	/* Otherwise, just the calibration is allowed */
sahilmgandhi	18:6a4db94011d3	2143	else
sahilmgandhi	18:6a4db94011d3	2144	{
sahilmgandhi	18:6a4db94011d3	2145	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
sahilmgandhi	18:6a4db94011d3	2146	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
sahilmgandhi	18:6a4db94011d3	2147	}
sahilmgandhi	18:6a4db94011d3	2148	}
sahilmgandhi	18:6a4db94011d3	2149	else
sahilmgandhi	18:6a4db94011d3	2150	{
sahilmgandhi	18:6a4db94011d3	2151	/* Check the HSI State */
sahilmgandhi	18:6a4db94011d3	2152	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
sahilmgandhi	18:6a4db94011d3	2153	{
sahilmgandhi	18:6a4db94011d3	2154	/* Enable the Internal High Speed oscillator (HSI). */
sahilmgandhi	18:6a4db94011d3	2155	__HAL_RCC_HSI_ENABLE();
sahilmgandhi	18:6a4db94011d3	2156
sahilmgandhi	18:6a4db94011d3	2157	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2158	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2159
sahilmgandhi	18:6a4db94011d3	2160	/* Wait till HSI is ready */
sahilmgandhi	18:6a4db94011d3	2161	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
sahilmgandhi	18:6a4db94011d3	2162	{
sahilmgandhi	18:6a4db94011d3	2163	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2164	{
sahilmgandhi	18:6a4db94011d3	2165	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2166	}
sahilmgandhi	18:6a4db94011d3	2167	}
sahilmgandhi	18:6a4db94011d3	2168
sahilmgandhi	18:6a4db94011d3	2169	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
sahilmgandhi	18:6a4db94011d3	2170	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
sahilmgandhi	18:6a4db94011d3	2171	}
sahilmgandhi	18:6a4db94011d3	2172	else
sahilmgandhi	18:6a4db94011d3	2173	{
sahilmgandhi	18:6a4db94011d3	2174	/* Disable the Internal High Speed oscillator (HSI). */
sahilmgandhi	18:6a4db94011d3	2175	__HAL_RCC_HSI_DISABLE();
sahilmgandhi	18:6a4db94011d3	2176
sahilmgandhi	18:6a4db94011d3	2177	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2178	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2179
sahilmgandhi	18:6a4db94011d3	2180	/* Wait till HSI is ready */
sahilmgandhi	18:6a4db94011d3	2181	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	2182	{
sahilmgandhi	18:6a4db94011d3	2183	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2184	{
sahilmgandhi	18:6a4db94011d3	2185	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2186	}
sahilmgandhi	18:6a4db94011d3	2187	}
sahilmgandhi	18:6a4db94011d3	2188	}
sahilmgandhi	18:6a4db94011d3	2189	}
sahilmgandhi	18:6a4db94011d3	2190	}
sahilmgandhi	18:6a4db94011d3	2191	/------------------------------ LSI Configuration -------------------------/
sahilmgandhi	18:6a4db94011d3	2192	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
sahilmgandhi	18:6a4db94011d3	2193	{
sahilmgandhi	18:6a4db94011d3	2194	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2195	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
sahilmgandhi	18:6a4db94011d3	2196
sahilmgandhi	18:6a4db94011d3	2197	/* Check the LSI State */
sahilmgandhi	18:6a4db94011d3	2198	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
sahilmgandhi	18:6a4db94011d3	2199	{
sahilmgandhi	18:6a4db94011d3	2200	/* Enable the Internal Low Speed oscillator (LSI). */
sahilmgandhi	18:6a4db94011d3	2201	__HAL_RCC_LSI_ENABLE();
sahilmgandhi	18:6a4db94011d3	2202
sahilmgandhi	18:6a4db94011d3	2203	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2204	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2205
sahilmgandhi	18:6a4db94011d3	2206	/* Wait till LSI is ready */
sahilmgandhi	18:6a4db94011d3	2207	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
sahilmgandhi	18:6a4db94011d3	2208	{
sahilmgandhi	18:6a4db94011d3	2209	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2210	{
sahilmgandhi	18:6a4db94011d3	2211	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2212	}
sahilmgandhi	18:6a4db94011d3	2213	}
sahilmgandhi	18:6a4db94011d3	2214	}
sahilmgandhi	18:6a4db94011d3	2215	else
sahilmgandhi	18:6a4db94011d3	2216	{
sahilmgandhi	18:6a4db94011d3	2217	/* Disable the Internal Low Speed oscillator (LSI). */
sahilmgandhi	18:6a4db94011d3	2218	__HAL_RCC_LSI_DISABLE();
sahilmgandhi	18:6a4db94011d3	2219
sahilmgandhi	18:6a4db94011d3	2220	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2221	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2222
sahilmgandhi	18:6a4db94011d3	2223	/* Wait till LSI is ready */
sahilmgandhi	18:6a4db94011d3	2224	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	2225	{
sahilmgandhi	18:6a4db94011d3	2226	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2227	{
sahilmgandhi	18:6a4db94011d3	2228	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2229	}
sahilmgandhi	18:6a4db94011d3	2230	}
sahilmgandhi	18:6a4db94011d3	2231	}
sahilmgandhi	18:6a4db94011d3	2232	}
sahilmgandhi	18:6a4db94011d3	2233	/------------------------------ LSE Configuration -------------------------/
sahilmgandhi	18:6a4db94011d3	2234	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
sahilmgandhi	18:6a4db94011d3	2235	{
sahilmgandhi	18:6a4db94011d3	2236	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2237	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
sahilmgandhi	18:6a4db94011d3	2238
sahilmgandhi	18:6a4db94011d3	2239	/* Enable Power Clock*/
sahilmgandhi	18:6a4db94011d3	2240	__HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi	18:6a4db94011d3	2241
sahilmgandhi	18:6a4db94011d3	2242	/* Enable write access to Backup domain */
sahilmgandhi	18:6a4db94011d3	2243	PWR->CR \|= PWR_CR_DBP;
sahilmgandhi	18:6a4db94011d3	2244
sahilmgandhi	18:6a4db94011d3	2245	/* Wait for Backup domain Write protection disable */
sahilmgandhi	18:6a4db94011d3	2246	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2247
sahilmgandhi	18:6a4db94011d3	2248	while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi	18:6a4db94011d3	2249	{
sahilmgandhi	18:6a4db94011d3	2250	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2251	{
sahilmgandhi	18:6a4db94011d3	2252	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2253	}
sahilmgandhi	18:6a4db94011d3	2254	}
sahilmgandhi	18:6a4db94011d3	2255
sahilmgandhi	18:6a4db94011d3	2256	/* Set the new LSE configuration -----------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2257	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
sahilmgandhi	18:6a4db94011d3	2258	/* Check the LSE State */
sahilmgandhi	18:6a4db94011d3	2259	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
sahilmgandhi	18:6a4db94011d3	2260	{
sahilmgandhi	18:6a4db94011d3	2261	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2262	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2263
sahilmgandhi	18:6a4db94011d3	2264	/* Wait till LSE is ready */
sahilmgandhi	18:6a4db94011d3	2265	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi	18:6a4db94011d3	2266	{
sahilmgandhi	18:6a4db94011d3	2267	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2268	{
sahilmgandhi	18:6a4db94011d3	2269	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2270	}
sahilmgandhi	18:6a4db94011d3	2271	}
sahilmgandhi	18:6a4db94011d3	2272	}
sahilmgandhi	18:6a4db94011d3	2273	else
sahilmgandhi	18:6a4db94011d3	2274	{
sahilmgandhi	18:6a4db94011d3	2275	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2276	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2277
sahilmgandhi	18:6a4db94011d3	2278	/* Wait till LSE is ready */
sahilmgandhi	18:6a4db94011d3	2279	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
sahilmgandhi	18:6a4db94011d3	2280	{
sahilmgandhi	18:6a4db94011d3	2281	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2282	{
sahilmgandhi	18:6a4db94011d3	2283	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2284	}
sahilmgandhi	18:6a4db94011d3	2285	}
sahilmgandhi	18:6a4db94011d3	2286	}
sahilmgandhi	18:6a4db94011d3	2287	}
sahilmgandhi	18:6a4db94011d3	2288	/-------------------------------- PLL Configuration -----------------------/
sahilmgandhi	18:6a4db94011d3	2289	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2290	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
sahilmgandhi	18:6a4db94011d3	2291	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
sahilmgandhi	18:6a4db94011d3	2292	{
sahilmgandhi	18:6a4db94011d3	2293	/* Check if the PLL is used as system clock or not */
sahilmgandhi	18:6a4db94011d3	2294	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
sahilmgandhi	18:6a4db94011d3	2295	{
sahilmgandhi	18:6a4db94011d3	2296	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
sahilmgandhi	18:6a4db94011d3	2297	{
sahilmgandhi	18:6a4db94011d3	2298	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2299	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
sahilmgandhi	18:6a4db94011d3	2300	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
sahilmgandhi	18:6a4db94011d3	2301	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
sahilmgandhi	18:6a4db94011d3	2302	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
sahilmgandhi	18:6a4db94011d3	2303	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
sahilmgandhi	18:6a4db94011d3	2304	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
sahilmgandhi	18:6a4db94011d3	2305
sahilmgandhi	18:6a4db94011d3	2306	/* Disable the main PLL. */
sahilmgandhi	18:6a4db94011d3	2307	__HAL_RCC_PLL_DISABLE();
sahilmgandhi	18:6a4db94011d3	2308
sahilmgandhi	18:6a4db94011d3	2309	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2310	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2311
sahilmgandhi	18:6a4db94011d3	2312	/* Wait till PLL is ready */
sahilmgandhi	18:6a4db94011d3	2313	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	2314	{
sahilmgandhi	18:6a4db94011d3	2315	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2316	{
sahilmgandhi	18:6a4db94011d3	2317	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2318	}
sahilmgandhi	18:6a4db94011d3	2319	}
sahilmgandhi	18:6a4db94011d3	2320
sahilmgandhi	18:6a4db94011d3	2321	/* Configure the main PLL clock source, multiplication and division factors. */
sahilmgandhi	18:6a4db94011d3	2322	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
sahilmgandhi	18:6a4db94011d3	2323	RCC_OscInitStruct->PLL.PLLM,
sahilmgandhi	18:6a4db94011d3	2324	RCC_OscInitStruct->PLL.PLLN,
sahilmgandhi	18:6a4db94011d3	2325	RCC_OscInitStruct->PLL.PLLP,
sahilmgandhi	18:6a4db94011d3	2326	RCC_OscInitStruct->PLL.PLLQ,
sahilmgandhi	18:6a4db94011d3	2327	RCC_OscInitStruct->PLL.PLLR);
sahilmgandhi	18:6a4db94011d3	2328
sahilmgandhi	18:6a4db94011d3	2329	/* Enable the main PLL. */
sahilmgandhi	18:6a4db94011d3	2330	__HAL_RCC_PLL_ENABLE();
sahilmgandhi	18:6a4db94011d3	2331
sahilmgandhi	18:6a4db94011d3	2332	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2333	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2334
sahilmgandhi	18:6a4db94011d3	2335	/* Wait till PLL is ready */
sahilmgandhi	18:6a4db94011d3	2336	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
sahilmgandhi	18:6a4db94011d3	2337	{
sahilmgandhi	18:6a4db94011d3	2338	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2339	{
sahilmgandhi	18:6a4db94011d3	2340	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2341	}
sahilmgandhi	18:6a4db94011d3	2342	}
sahilmgandhi	18:6a4db94011d3	2343	}
sahilmgandhi	18:6a4db94011d3	2344	else
sahilmgandhi	18:6a4db94011d3	2345	{
sahilmgandhi	18:6a4db94011d3	2346	/* Disable the main PLL. */
sahilmgandhi	18:6a4db94011d3	2347	__HAL_RCC_PLL_DISABLE();
sahilmgandhi	18:6a4db94011d3	2348
sahilmgandhi	18:6a4db94011d3	2349	/* Get Start Tick*/
sahilmgandhi	18:6a4db94011d3	2350	tickstart = HAL_GetTick();
sahilmgandhi	18:6a4db94011d3	2351
sahilmgandhi	18:6a4db94011d3	2352	/* Wait till PLL is ready */
sahilmgandhi	18:6a4db94011d3	2353	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
sahilmgandhi	18:6a4db94011d3	2354	{
sahilmgandhi	18:6a4db94011d3	2355	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi	18:6a4db94011d3	2356	{
sahilmgandhi	18:6a4db94011d3	2357	return HAL_TIMEOUT;
sahilmgandhi	18:6a4db94011d3	2358	}
sahilmgandhi	18:6a4db94011d3	2359	}
sahilmgandhi	18:6a4db94011d3	2360	}
sahilmgandhi	18:6a4db94011d3	2361	}
sahilmgandhi	18:6a4db94011d3	2362	else
sahilmgandhi	18:6a4db94011d3	2363	{
sahilmgandhi	18:6a4db94011d3	2364	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	2365	}
sahilmgandhi	18:6a4db94011d3	2366	}
sahilmgandhi	18:6a4db94011d3	2367	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	2368	}
sahilmgandhi	18:6a4db94011d3	2369
sahilmgandhi	18:6a4db94011d3	2370	/**
sahilmgandhi	18:6a4db94011d3	2371	* @brief Configures the RCC_OscInitStruct according to the internal
sahilmgandhi	18:6a4db94011d3	2372	* RCC configuration registers.
sahilmgandhi	18:6a4db94011d3	2373	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
sahilmgandhi	18:6a4db94011d3	2374	*
sahilmgandhi	18:6a4db94011d3	2375	* @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
sahilmgandhi	18:6a4db94011d3	2376	* @note This function add the PLL/PLLR factor management
sahilmgandhi	18:6a4db94011d3	2377	* @retval None
sahilmgandhi	18:6a4db94011d3	2378	*/
sahilmgandhi	18:6a4db94011d3	2379	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
sahilmgandhi	18:6a4db94011d3	2380	{
sahilmgandhi	18:6a4db94011d3	2381	/* Set all possible values for the Oscillator type parameter ---------------*/
sahilmgandhi	18:6a4db94011d3	2382	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
sahilmgandhi	18:6a4db94011d3	2383
sahilmgandhi	18:6a4db94011d3	2384	/* Get the HSE configuration -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2385	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
sahilmgandhi	18:6a4db94011d3	2386	{
sahilmgandhi	18:6a4db94011d3	2387	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
sahilmgandhi	18:6a4db94011d3	2388	}
sahilmgandhi	18:6a4db94011d3	2389	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
sahilmgandhi	18:6a4db94011d3	2390	{
sahilmgandhi	18:6a4db94011d3	2391	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
sahilmgandhi	18:6a4db94011d3	2392	}
sahilmgandhi	18:6a4db94011d3	2393	else
sahilmgandhi	18:6a4db94011d3	2394	{
sahilmgandhi	18:6a4db94011d3	2395	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
sahilmgandhi	18:6a4db94011d3	2396	}
sahilmgandhi	18:6a4db94011d3	2397
sahilmgandhi	18:6a4db94011d3	2398	/* Get the HSI configuration -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2399	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
sahilmgandhi	18:6a4db94011d3	2400	{
sahilmgandhi	18:6a4db94011d3	2401	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
sahilmgandhi	18:6a4db94011d3	2402	}
sahilmgandhi	18:6a4db94011d3	2403	else
sahilmgandhi	18:6a4db94011d3	2404	{
sahilmgandhi	18:6a4db94011d3	2405	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
sahilmgandhi	18:6a4db94011d3	2406	}
sahilmgandhi	18:6a4db94011d3	2407
sahilmgandhi	18:6a4db94011d3	2408	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
sahilmgandhi	18:6a4db94011d3	2409
sahilmgandhi	18:6a4db94011d3	2410	/* Get the LSE configuration -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2411	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
sahilmgandhi	18:6a4db94011d3	2412	{
sahilmgandhi	18:6a4db94011d3	2413	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
sahilmgandhi	18:6a4db94011d3	2414	}
sahilmgandhi	18:6a4db94011d3	2415	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
sahilmgandhi	18:6a4db94011d3	2416	{
sahilmgandhi	18:6a4db94011d3	2417	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
sahilmgandhi	18:6a4db94011d3	2418	}
sahilmgandhi	18:6a4db94011d3	2419	else
sahilmgandhi	18:6a4db94011d3	2420	{
sahilmgandhi	18:6a4db94011d3	2421	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
sahilmgandhi	18:6a4db94011d3	2422	}
sahilmgandhi	18:6a4db94011d3	2423
sahilmgandhi	18:6a4db94011d3	2424	/* Get the LSI configuration -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2425	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
sahilmgandhi	18:6a4db94011d3	2426	{
sahilmgandhi	18:6a4db94011d3	2427	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
sahilmgandhi	18:6a4db94011d3	2428	}
sahilmgandhi	18:6a4db94011d3	2429	else
sahilmgandhi	18:6a4db94011d3	2430	{
sahilmgandhi	18:6a4db94011d3	2431	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
sahilmgandhi	18:6a4db94011d3	2432	}
sahilmgandhi	18:6a4db94011d3	2433
sahilmgandhi	18:6a4db94011d3	2434	/* Get the PLL configuration -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2435	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
sahilmgandhi	18:6a4db94011d3	2436	{
sahilmgandhi	18:6a4db94011d3	2437	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
sahilmgandhi	18:6a4db94011d3	2438	}
sahilmgandhi	18:6a4db94011d3	2439	else
sahilmgandhi	18:6a4db94011d3	2440	{
sahilmgandhi	18:6a4db94011d3	2441	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
sahilmgandhi	18:6a4db94011d3	2442	}
sahilmgandhi	18:6a4db94011d3	2443	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
sahilmgandhi	18:6a4db94011d3	2444	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
sahilmgandhi	18:6a4db94011d3	2445	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
sahilmgandhi	18:6a4db94011d3	2446	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
sahilmgandhi	18:6a4db94011d3	2447	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
sahilmgandhi	18:6a4db94011d3	2448	RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
sahilmgandhi	18:6a4db94011d3	2449	}
sahilmgandhi	18:6a4db94011d3	2450	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	2451
sahilmgandhi	18:6a4db94011d3	2452	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\|\
sahilmgandhi	18:6a4db94011d3	2453	defined(STM32F412Vx) \|\| defined(STM32F412Rx) \|\| defined(STM32F412Cx)
sahilmgandhi	18:6a4db94011d3	2454	/**
sahilmgandhi	18:6a4db94011d3	2455	* @brief Select LSE mode
sahilmgandhi	18:6a4db94011d3	2456	*
sahilmgandhi	18:6a4db94011d3	2457	* @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
sahilmgandhi	18:6a4db94011d3	2458	*
sahilmgandhi	18:6a4db94011d3	2459	* @param Mode: specifies the LSE mode.
sahilmgandhi	18:6a4db94011d3	2460	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	2461	* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
sahilmgandhi	18:6a4db94011d3	2462	* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
sahilmgandhi	18:6a4db94011d3	2463	* @retval None
sahilmgandhi	18:6a4db94011d3	2464	*/
sahilmgandhi	18:6a4db94011d3	2465	void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
sahilmgandhi	18:6a4db94011d3	2466	{
sahilmgandhi	18:6a4db94011d3	2467	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	2468	assert_param(IS_RCC_LSE_MODE(Mode));
sahilmgandhi	18:6a4db94011d3	2469	if(Mode == RCC_LSE_HIGHDRIVE_MODE)
sahilmgandhi	18:6a4db94011d3	2470	{
sahilmgandhi	18:6a4db94011d3	2471	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
sahilmgandhi	18:6a4db94011d3	2472	}
sahilmgandhi	18:6a4db94011d3	2473	else
sahilmgandhi	18:6a4db94011d3	2474	{
sahilmgandhi	18:6a4db94011d3	2475	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
sahilmgandhi	18:6a4db94011d3	2476	}
sahilmgandhi	18:6a4db94011d3	2477	}
sahilmgandhi	18:6a4db94011d3	2478
sahilmgandhi	18:6a4db94011d3	2479	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx \|\| STM32F412Cx */
sahilmgandhi	18:6a4db94011d3	2480
sahilmgandhi	18:6a4db94011d3	2481	#if defined(STM32F446xx)
sahilmgandhi	18:6a4db94011d3	2482	/**
sahilmgandhi	18:6a4db94011d3	2483	* @brief Returns the SYSCLK frequency
sahilmgandhi	18:6a4db94011d3	2484	*
sahilmgandhi	18:6a4db94011d3	2485	* @note This function implementation is valid only for STM32F446xx devices.
sahilmgandhi	18:6a4db94011d3	2486	* @note This function add the PLL/PLLR System clock source
sahilmgandhi	18:6a4db94011d3	2487	*
sahilmgandhi	18:6a4db94011d3	2488	* @note The system frequency computed by this function is not the real
sahilmgandhi	18:6a4db94011d3	2489	* frequency in the chip. It is calculated based on the predefined
sahilmgandhi	18:6a4db94011d3	2490	* constant and the selected clock source:
sahilmgandhi	18:6a4db94011d3	2491	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
sahilmgandhi	18:6a4db94011d3	2492	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
sahilmgandhi	18:6a4db94011d3	2493	* @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
sahilmgandhi	18:6a4db94011d3	2494	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
sahilmgandhi	18:6a4db94011d3	2495	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
sahilmgandhi	18:6a4db94011d3	2496	* 16 MHz) but the real value may vary depending on the variations
sahilmgandhi	18:6a4db94011d3	2497	* in voltage and temperature.
sahilmgandhi	18:6a4db94011d3	2498	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
sahilmgandhi	18:6a4db94011d3	2499	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
sahilmgandhi	18:6a4db94011d3	2500	* frequency of the crystal used. Otherwise, this function may
sahilmgandhi	18:6a4db94011d3	2501	* have wrong result.
sahilmgandhi	18:6a4db94011d3	2502	*
sahilmgandhi	18:6a4db94011d3	2503	* @note The result of this function could be not correct when using fractional
sahilmgandhi	18:6a4db94011d3	2504	* value for HSE crystal.
sahilmgandhi	18:6a4db94011d3	2505	*
sahilmgandhi	18:6a4db94011d3	2506	* @note This function can be used by the user application to compute the
sahilmgandhi	18:6a4db94011d3	2507	* baudrate for the communication peripherals or configure other parameters.
sahilmgandhi	18:6a4db94011d3	2508	*
sahilmgandhi	18:6a4db94011d3	2509	* @note Each time SYSCLK changes, this function must be called to update the
sahilmgandhi	18:6a4db94011d3	2510	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi	18:6a4db94011d3	2511	*
sahilmgandhi	18:6a4db94011d3	2512	*
sahilmgandhi	18:6a4db94011d3	2513	* @retval SYSCLK frequency
sahilmgandhi	18:6a4db94011d3	2514	*/
sahilmgandhi	18:6a4db94011d3	2515	uint32_t HAL_RCC_GetSysClockFreq(void)
sahilmgandhi	18:6a4db94011d3	2516	{
sahilmgandhi	18:6a4db94011d3	2517	uint32_t pllm = 0U;
sahilmgandhi	18:6a4db94011d3	2518	uint32_t pllvco = 0U;
sahilmgandhi	18:6a4db94011d3	2519	uint32_t pllp = 0U;
sahilmgandhi	18:6a4db94011d3	2520	uint32_t pllr = 0U;
sahilmgandhi	18:6a4db94011d3	2521	uint32_t sysclockfreq = 0U;
sahilmgandhi	18:6a4db94011d3	2522
sahilmgandhi	18:6a4db94011d3	2523	/* Get SYSCLK source -------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	2524	switch (RCC->CFGR & RCC_CFGR_SWS)
sahilmgandhi	18:6a4db94011d3	2525	{
sahilmgandhi	18:6a4db94011d3	2526	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
sahilmgandhi	18:6a4db94011d3	2527	{
sahilmgandhi	18:6a4db94011d3	2528	sysclockfreq = HSI_VALUE;
sahilmgandhi	18:6a4db94011d3	2529	break;
sahilmgandhi	18:6a4db94011d3	2530	}
sahilmgandhi	18:6a4db94011d3	2531	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
sahilmgandhi	18:6a4db94011d3	2532	{
sahilmgandhi	18:6a4db94011d3	2533	sysclockfreq = HSE_VALUE;
sahilmgandhi	18:6a4db94011d3	2534	break;
sahilmgandhi	18:6a4db94011d3	2535	}
sahilmgandhi	18:6a4db94011d3	2536	case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
sahilmgandhi	18:6a4db94011d3	2537	{
sahilmgandhi	18:6a4db94011d3	2538	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
sahilmgandhi	18:6a4db94011d3	2539	SYSCLK = PLL_VCO / PLLP */
sahilmgandhi	18:6a4db94011d3	2540	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
sahilmgandhi	18:6a4db94011d3	2541	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
sahilmgandhi	18:6a4db94011d3	2542	{
sahilmgandhi	18:6a4db94011d3	2543	/* HSE used as PLL clock source */
sahilmgandhi	18:6a4db94011d3	2544	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
sahilmgandhi	18:6a4db94011d3	2545	}
sahilmgandhi	18:6a4db94011d3	2546	else
sahilmgandhi	18:6a4db94011d3	2547	{
sahilmgandhi	18:6a4db94011d3	2548	/* HSI used as PLL clock source */
sahilmgandhi	18:6a4db94011d3	2549	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
sahilmgandhi	18:6a4db94011d3	2550	}
sahilmgandhi	18:6a4db94011d3	2551	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
sahilmgandhi	18:6a4db94011d3	2552
sahilmgandhi	18:6a4db94011d3	2553	sysclockfreq = pllvco/pllp;
sahilmgandhi	18:6a4db94011d3	2554	break;
sahilmgandhi	18:6a4db94011d3	2555	}
sahilmgandhi	18:6a4db94011d3	2556	case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
sahilmgandhi	18:6a4db94011d3	2557	{
sahilmgandhi	18:6a4db94011d3	2558	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
sahilmgandhi	18:6a4db94011d3	2559	SYSCLK = PLL_VCO / PLLR */
sahilmgandhi	18:6a4db94011d3	2560	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
sahilmgandhi	18:6a4db94011d3	2561	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
sahilmgandhi	18:6a4db94011d3	2562	{
sahilmgandhi	18:6a4db94011d3	2563	/* HSE used as PLL clock source */
sahilmgandhi	18:6a4db94011d3	2564	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
sahilmgandhi	18:6a4db94011d3	2565	}
sahilmgandhi	18:6a4db94011d3	2566	else
sahilmgandhi	18:6a4db94011d3	2567	{
sahilmgandhi	18:6a4db94011d3	2568	/* HSI used as PLL clock source */
sahilmgandhi	18:6a4db94011d3	2569	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
sahilmgandhi	18:6a4db94011d3	2570	}
sahilmgandhi	18:6a4db94011d3	2571	pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
sahilmgandhi	18:6a4db94011d3	2572
sahilmgandhi	18:6a4db94011d3	2573	sysclockfreq = pllvco/pllr;
sahilmgandhi	18:6a4db94011d3	2574	break;
sahilmgandhi	18:6a4db94011d3	2575	}
sahilmgandhi	18:6a4db94011d3	2576	default:
sahilmgandhi	18:6a4db94011d3	2577	{
sahilmgandhi	18:6a4db94011d3	2578	sysclockfreq = HSI_VALUE;
sahilmgandhi	18:6a4db94011d3	2579	break;
sahilmgandhi	18:6a4db94011d3	2580	}
sahilmgandhi	18:6a4db94011d3	2581	}
sahilmgandhi	18:6a4db94011d3	2582	return sysclockfreq;
sahilmgandhi	18:6a4db94011d3	2583	}
sahilmgandhi	18:6a4db94011d3	2584	#endif /* STM32F446xx */
sahilmgandhi	18:6a4db94011d3	2585
sahilmgandhi	18:6a4db94011d3	2586	/**
sahilmgandhi	18:6a4db94011d3	2587	* @}
sahilmgandhi	18:6a4db94011d3	2588	*/
sahilmgandhi	18:6a4db94011d3	2589
sahilmgandhi	18:6a4db94011d3	2590	/**
sahilmgandhi	18:6a4db94011d3	2591	* @}
sahilmgandhi	18:6a4db94011d3	2592	*/
sahilmgandhi	18:6a4db94011d3	2593
sahilmgandhi	18:6a4db94011d3	2594	#endif /* HAL_RCC_MODULE_ENABLED */
sahilmgandhi	18:6a4db94011d3	2595	/**
sahilmgandhi	18:6a4db94011d3	2596	* @}
sahilmgandhi	18:6a4db94011d3	2597	*/
sahilmgandhi	18:6a4db94011d3	2598
sahilmgandhi	18:6a4db94011d3	2599	/**
sahilmgandhi	18:6a4db94011d3	2600	* @}
sahilmgandhi	18:6a4db94011d3	2601	*/
sahilmgandhi	18:6a4db94011d3	2602
sahilmgandhi	18:6a4db94011d3	2603	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c@46:b156ef445742, 2017-06-03 (annotated)

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