MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_rcc.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief RCC HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
sahilmgandhi 18:6a4db94011d3 10 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 11 * + Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 @verbatim
sahilmgandhi 18:6a4db94011d3 14 ==============================================================================
sahilmgandhi 18:6a4db94011d3 15 ##### RCC specific features #####
sahilmgandhi 18:6a4db94011d3 16 ==============================================================================
sahilmgandhi 18:6a4db94011d3 17 [..]
sahilmgandhi 18:6a4db94011d3 18 After reset the device is running from Internal High Speed oscillator
sahilmgandhi 18:6a4db94011d3 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
sahilmgandhi 18:6a4db94011d3 20 and I-Cache are disabled, and all peripherals are off except internal
sahilmgandhi 18:6a4db94011d3 21 SRAM, Flash and JTAG.
sahilmgandhi 18:6a4db94011d3 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
sahilmgandhi 18:6a4db94011d3 23 all peripherals mapped on these busses are running at HSI speed.
sahilmgandhi 18:6a4db94011d3 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
sahilmgandhi 18:6a4db94011d3 25 (+) All GPIOs are in input floating state, except the JTAG pins which
sahilmgandhi 18:6a4db94011d3 26 are assigned to be used for debug purpose.
sahilmgandhi 18:6a4db94011d3 27
sahilmgandhi 18:6a4db94011d3 28 [..]
sahilmgandhi 18:6a4db94011d3 29 Once the device started from reset, the user application has to:
sahilmgandhi 18:6a4db94011d3 30 (+) Configure the clock source to be used to drive the System clock
sahilmgandhi 18:6a4db94011d3 31 (if the application needs higher frequency/performance)
sahilmgandhi 18:6a4db94011d3 32 (+) Configure the System clock frequency and Flash settings
sahilmgandhi 18:6a4db94011d3 33 (+) Configure the AHB and APB busses prescalers
sahilmgandhi 18:6a4db94011d3 34 (+) Enable the clock for the peripheral(s) to be used
sahilmgandhi 18:6a4db94011d3 35 (+) Configure the clock source(s) for peripherals which clocks are not
sahilmgandhi 18:6a4db94011d3 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 ##### RCC Limitations #####
sahilmgandhi 18:6a4db94011d3 39 ==============================================================================
sahilmgandhi 18:6a4db94011d3 40 [..]
sahilmgandhi 18:6a4db94011d3 41 A delay between an RCC peripheral clock enable and the effective peripheral
sahilmgandhi 18:6a4db94011d3 42 enabling should be taken into account in order to manage the peripheral read/write
sahilmgandhi 18:6a4db94011d3 43 from/to registers.
sahilmgandhi 18:6a4db94011d3 44 (+) This delay depends on the peripheral mapping.
sahilmgandhi 18:6a4db94011d3 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
sahilmgandhi 18:6a4db94011d3 46 after the clock enable bit is set on the hardware register
sahilmgandhi 18:6a4db94011d3 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
sahilmgandhi 18:6a4db94011d3 48 after the clock enable bit is set on the hardware register
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 [..]
sahilmgandhi 18:6a4db94011d3 51 Implemented Workaround:
sahilmgandhi 18:6a4db94011d3 52 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
sahilmgandhi 18:6a4db94011d3 53 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 @endverbatim
sahilmgandhi 18:6a4db94011d3 56 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 57 * @attention
sahilmgandhi 18:6a4db94011d3 58 *
sahilmgandhi 18:6a4db94011d3 59 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 60 *
sahilmgandhi 18:6a4db94011d3 61 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 62 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 63 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 64 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 65 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 66 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 67 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 69 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 70 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 71 *
sahilmgandhi 18:6a4db94011d3 72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 82 *
sahilmgandhi 18:6a4db94011d3 83 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 84 */
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 87 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 90 * @{
sahilmgandhi 18:6a4db94011d3 91 */
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 /** @defgroup RCC RCC
sahilmgandhi 18:6a4db94011d3 94 * @brief RCC HAL module driver
sahilmgandhi 18:6a4db94011d3 95 * @{
sahilmgandhi 18:6a4db94011d3 96 */
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 #ifdef HAL_RCC_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 99
sahilmgandhi 18:6a4db94011d3 100 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 101 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 102 /** @addtogroup RCC_Private_Constants
sahilmgandhi 18:6a4db94011d3 103 * @{
sahilmgandhi 18:6a4db94011d3 104 */
sahilmgandhi 18:6a4db94011d3 105 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 108 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
sahilmgandhi 18:6a4db94011d3 109 #define MCO1_GPIO_PORT GPIOA
sahilmgandhi 18:6a4db94011d3 110 #define MCO1_PIN GPIO_PIN_8
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
sahilmgandhi 18:6a4db94011d3 113 #define MCO2_GPIO_PORT GPIOC
sahilmgandhi 18:6a4db94011d3 114 #define MCO2_PIN GPIO_PIN_9
sahilmgandhi 18:6a4db94011d3 115 /**
sahilmgandhi 18:6a4db94011d3 116 * @}
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 120 /** @defgroup RCC_Private_Variables RCC Private Variables
sahilmgandhi 18:6a4db94011d3 121 * @{
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123 const uint8_t APBAHBPrescTable[16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
sahilmgandhi 18:6a4db94011d3 124 /**
sahilmgandhi 18:6a4db94011d3 125 * @}
sahilmgandhi 18:6a4db94011d3 126 */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 129 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 /** @defgroup RCC_Exported_Functions RCC Exported Functions
sahilmgandhi 18:6a4db94011d3 132 * @{
sahilmgandhi 18:6a4db94011d3 133 */
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 136 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 137 *
sahilmgandhi 18:6a4db94011d3 138 @verbatim
sahilmgandhi 18:6a4db94011d3 139 ===============================================================================
sahilmgandhi 18:6a4db94011d3 140 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 141 ===============================================================================
sahilmgandhi 18:6a4db94011d3 142 [..]
sahilmgandhi 18:6a4db94011d3 143 This section provides functions allowing to configure the internal/external oscillators
sahilmgandhi 18:6a4db94011d3 144 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
sahilmgandhi 18:6a4db94011d3 145 and APB2).
sahilmgandhi 18:6a4db94011d3 146
sahilmgandhi 18:6a4db94011d3 147 [..] Internal/external clock and PLL configuration
sahilmgandhi 18:6a4db94011d3 148 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
sahilmgandhi 18:6a4db94011d3 149 the PLL as System clock source.
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
sahilmgandhi 18:6a4db94011d3 152 clock source.
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
sahilmgandhi 18:6a4db94011d3 155 through the PLL as System clock source. Can be used also as RTC clock source.
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
sahilmgandhi 18:6a4db94011d3 160 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
sahilmgandhi 18:6a4db94011d3 161 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
sahilmgandhi 18:6a4db94011d3 162 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
sahilmgandhi 18:6a4db94011d3 163
sahilmgandhi 18:6a4db94011d3 164 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
sahilmgandhi 18:6a4db94011d3 165 and if a HSE clock failure occurs(HSE used directly or through PLL as System
sahilmgandhi 18:6a4db94011d3 166 clock source), the System clocks automatically switched to HSI and an interrupt
sahilmgandhi 18:6a4db94011d3 167 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
sahilmgandhi 18:6a4db94011d3 168 (Non-Maskable Interrupt) exception vector.
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
sahilmgandhi 18:6a4db94011d3 171 clock (through a configurable prescaler) on PA8 pin.
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
sahilmgandhi 18:6a4db94011d3 174 clock (through a configurable prescaler) on PC9 pin.
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 [..] System, AHB and APB busses clocks configuration
sahilmgandhi 18:6a4db94011d3 177 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
sahilmgandhi 18:6a4db94011d3 178 HSE and PLL.
sahilmgandhi 18:6a4db94011d3 179 The AHB clock (HCLK) is derived from System clock through configurable
sahilmgandhi 18:6a4db94011d3 180 prescaler and used to clock the CPU, memory and peripherals mapped
sahilmgandhi 18:6a4db94011d3 181 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
sahilmgandhi 18:6a4db94011d3 182 from AHB clock through configurable prescalers and used to clock
sahilmgandhi 18:6a4db94011d3 183 the peripherals mapped on these busses. You can use
sahilmgandhi 18:6a4db94011d3 184 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
sahilmgandhi 18:6a4db94011d3 187 frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
sahilmgandhi 18:6a4db94011d3 188 Depending on the device voltage range, the maximum frequency should
sahilmgandhi 18:6a4db94011d3 189 be adapted accordingly (refer to the product datasheets for more details).
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
sahilmgandhi 18:6a4db94011d3 192 the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
sahilmgandhi 18:6a4db94011d3 193 Depending on the device voltage range, the maximum frequency should
sahilmgandhi 18:6a4db94011d3 194 be adapted accordingly (refer to the product datasheets for more details).
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
sahilmgandhi 18:6a4db94011d3 197 PCLK2 84 MHz and PCLK1 42 MHz.
sahilmgandhi 18:6a4db94011d3 198 Depending on the device voltage range, the maximum frequency should
sahilmgandhi 18:6a4db94011d3 199 be adapted accordingly (refer to the product datasheets for more details).
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
sahilmgandhi 18:6a4db94011d3 202 PCLK2 100 MHz and PCLK1 50 MHz.
sahilmgandhi 18:6a4db94011d3 203 Depending on the device voltage range, the maximum frequency should
sahilmgandhi 18:6a4db94011d3 204 be adapted accordingly (refer to the product datasheets for more details).
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 @endverbatim
sahilmgandhi 18:6a4db94011d3 207 * @{
sahilmgandhi 18:6a4db94011d3 208 */
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 /**
sahilmgandhi 18:6a4db94011d3 211 * @brief Resets the RCC clock configuration to the default reset state.
sahilmgandhi 18:6a4db94011d3 212 * @note The default reset state of the clock configuration is given below:
sahilmgandhi 18:6a4db94011d3 213 * - HSI ON and used as system clock source
sahilmgandhi 18:6a4db94011d3 214 * - HSE and PLL OFF
sahilmgandhi 18:6a4db94011d3 215 * - AHB, APB1 and APB2 prescaler set to 1.
sahilmgandhi 18:6a4db94011d3 216 * - CSS, MCO1 and MCO2 OFF
sahilmgandhi 18:6a4db94011d3 217 * - All interrupts disabled
sahilmgandhi 18:6a4db94011d3 218 * @note This function doesn't modify the configuration of the
sahilmgandhi 18:6a4db94011d3 219 * - Peripheral clocks
sahilmgandhi 18:6a4db94011d3 220 * - LSI, LSE and RTC clocks
sahilmgandhi 18:6a4db94011d3 221 * @retval None
sahilmgandhi 18:6a4db94011d3 222 */
sahilmgandhi 18:6a4db94011d3 223 __weak void HAL_RCC_DeInit(void)
sahilmgandhi 18:6a4db94011d3 224 {}
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /**
sahilmgandhi 18:6a4db94011d3 227 * @brief Initializes the RCC Oscillators according to the specified parameters in the
sahilmgandhi 18:6a4db94011d3 228 * RCC_OscInitTypeDef.
sahilmgandhi 18:6a4db94011d3 229 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
sahilmgandhi 18:6a4db94011d3 230 * contains the configuration information for the RCC Oscillators.
sahilmgandhi 18:6a4db94011d3 231 * @note The PLL is not disabled when used as system clock.
sahilmgandhi 18:6a4db94011d3 232 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
sahilmgandhi 18:6a4db94011d3 233 * supported by this API. User should request a transition to LSE Off
sahilmgandhi 18:6a4db94011d3 234 * first and then LSE On or LSE Bypass.
sahilmgandhi 18:6a4db94011d3 235 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
sahilmgandhi 18:6a4db94011d3 236 * supported by this API. User should request a transition to HSE Off
sahilmgandhi 18:6a4db94011d3 237 * first and then HSE On or HSE Bypass.
sahilmgandhi 18:6a4db94011d3 238 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 239 */
sahilmgandhi 18:6a4db94011d3 240 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
sahilmgandhi 18:6a4db94011d3 241 {
sahilmgandhi 18:6a4db94011d3 242 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 245 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sahilmgandhi 18:6a4db94011d3 246 /*------------------------------- HSE Configuration ------------------------*/
sahilmgandhi 18:6a4db94011d3 247 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
sahilmgandhi 18:6a4db94011d3 248 {
sahilmgandhi 18:6a4db94011d3 249 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 250 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
sahilmgandhi 18:6a4db94011d3 251 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
sahilmgandhi 18:6a4db94011d3 252 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
sahilmgandhi 18:6a4db94011d3 253 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
sahilmgandhi 18:6a4db94011d3 254 {
sahilmgandhi 18:6a4db94011d3 255 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
sahilmgandhi 18:6a4db94011d3 256 {
sahilmgandhi 18:6a4db94011d3 257 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 258 }
sahilmgandhi 18:6a4db94011d3 259 }
sahilmgandhi 18:6a4db94011d3 260 else
sahilmgandhi 18:6a4db94011d3 261 {
sahilmgandhi 18:6a4db94011d3 262 /* Set the new HSE configuration ---------------------------------------*/
sahilmgandhi 18:6a4db94011d3 263 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /* Check the HSE State */
sahilmgandhi 18:6a4db94011d3 266 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
sahilmgandhi 18:6a4db94011d3 267 {
sahilmgandhi 18:6a4db94011d3 268 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 269 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 /* Wait till HSE is ready */
sahilmgandhi 18:6a4db94011d3 272 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
sahilmgandhi 18:6a4db94011d3 273 {
sahilmgandhi 18:6a4db94011d3 274 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 275 {
sahilmgandhi 18:6a4db94011d3 276 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 277 }
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279 }
sahilmgandhi 18:6a4db94011d3 280 else
sahilmgandhi 18:6a4db94011d3 281 {
sahilmgandhi 18:6a4db94011d3 282 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 283 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 /* Wait till HSE is bypassed or disabled */
sahilmgandhi 18:6a4db94011d3 286 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
sahilmgandhi 18:6a4db94011d3 287 {
sahilmgandhi 18:6a4db94011d3 288 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 289 {
sahilmgandhi 18:6a4db94011d3 290 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 291 }
sahilmgandhi 18:6a4db94011d3 292 }
sahilmgandhi 18:6a4db94011d3 293 }
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295 }
sahilmgandhi 18:6a4db94011d3 296 /*----------------------------- HSI Configuration --------------------------*/
sahilmgandhi 18:6a4db94011d3 297 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
sahilmgandhi 18:6a4db94011d3 298 {
sahilmgandhi 18:6a4db94011d3 299 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 300 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
sahilmgandhi 18:6a4db94011d3 301 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
sahilmgandhi 18:6a4db94011d3 304 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
sahilmgandhi 18:6a4db94011d3 305 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
sahilmgandhi 18:6a4db94011d3 306 {
sahilmgandhi 18:6a4db94011d3 307 /* When HSI is used as system clock it will not disabled */
sahilmgandhi 18:6a4db94011d3 308 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
sahilmgandhi 18:6a4db94011d3 309 {
sahilmgandhi 18:6a4db94011d3 310 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 311 }
sahilmgandhi 18:6a4db94011d3 312 /* Otherwise, just the calibration is allowed */
sahilmgandhi 18:6a4db94011d3 313 else
sahilmgandhi 18:6a4db94011d3 314 {
sahilmgandhi 18:6a4db94011d3 315 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
sahilmgandhi 18:6a4db94011d3 316 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
sahilmgandhi 18:6a4db94011d3 317 }
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319 else
sahilmgandhi 18:6a4db94011d3 320 {
sahilmgandhi 18:6a4db94011d3 321 /* Check the HSI State */
sahilmgandhi 18:6a4db94011d3 322 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
sahilmgandhi 18:6a4db94011d3 323 {
sahilmgandhi 18:6a4db94011d3 324 /* Enable the Internal High Speed oscillator (HSI). */
sahilmgandhi 18:6a4db94011d3 325 __HAL_RCC_HSI_ENABLE();
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 328 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 /* Wait till HSI is ready */
sahilmgandhi 18:6a4db94011d3 331 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 332 {
sahilmgandhi 18:6a4db94011d3 333 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 334 {
sahilmgandhi 18:6a4db94011d3 335 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 336 }
sahilmgandhi 18:6a4db94011d3 337 }
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
sahilmgandhi 18:6a4db94011d3 340 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
sahilmgandhi 18:6a4db94011d3 341 }
sahilmgandhi 18:6a4db94011d3 342 else
sahilmgandhi 18:6a4db94011d3 343 {
sahilmgandhi 18:6a4db94011d3 344 /* Disable the Internal High Speed oscillator (HSI). */
sahilmgandhi 18:6a4db94011d3 345 __HAL_RCC_HSI_DISABLE();
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 348 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /* Wait till HSI is ready */
sahilmgandhi 18:6a4db94011d3 351 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
sahilmgandhi 18:6a4db94011d3 352 {
sahilmgandhi 18:6a4db94011d3 353 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 354 {
sahilmgandhi 18:6a4db94011d3 355 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 356 }
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358 }
sahilmgandhi 18:6a4db94011d3 359 }
sahilmgandhi 18:6a4db94011d3 360 }
sahilmgandhi 18:6a4db94011d3 361 /*------------------------------ LSI Configuration -------------------------*/
sahilmgandhi 18:6a4db94011d3 362 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
sahilmgandhi 18:6a4db94011d3 363 {
sahilmgandhi 18:6a4db94011d3 364 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 365 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /* Check the LSI State */
sahilmgandhi 18:6a4db94011d3 368 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
sahilmgandhi 18:6a4db94011d3 369 {
sahilmgandhi 18:6a4db94011d3 370 /* Enable the Internal Low Speed oscillator (LSI). */
sahilmgandhi 18:6a4db94011d3 371 __HAL_RCC_LSI_ENABLE();
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 374 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /* Wait till LSI is ready */
sahilmgandhi 18:6a4db94011d3 377 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 378 {
sahilmgandhi 18:6a4db94011d3 379 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 380 {
sahilmgandhi 18:6a4db94011d3 381 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 382 }
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384 }
sahilmgandhi 18:6a4db94011d3 385 else
sahilmgandhi 18:6a4db94011d3 386 {
sahilmgandhi 18:6a4db94011d3 387 /* Disable the Internal Low Speed oscillator (LSI). */
sahilmgandhi 18:6a4db94011d3 388 __HAL_RCC_LSI_DISABLE();
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 391 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 /* Wait till LSI is ready */
sahilmgandhi 18:6a4db94011d3 394 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
sahilmgandhi 18:6a4db94011d3 395 {
sahilmgandhi 18:6a4db94011d3 396 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 397 {
sahilmgandhi 18:6a4db94011d3 398 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 399 }
sahilmgandhi 18:6a4db94011d3 400 }
sahilmgandhi 18:6a4db94011d3 401 }
sahilmgandhi 18:6a4db94011d3 402 }
sahilmgandhi 18:6a4db94011d3 403 /*------------------------------ LSE Configuration -------------------------*/
sahilmgandhi 18:6a4db94011d3 404 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
sahilmgandhi 18:6a4db94011d3 405 {
sahilmgandhi 18:6a4db94011d3 406 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 407 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 /* Enable Power Clock*/
sahilmgandhi 18:6a4db94011d3 410 __HAL_RCC_PWR_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 /* Enable write access to Backup domain */
sahilmgandhi 18:6a4db94011d3 413 PWR->CR |= PWR_CR_DBP;
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 /* Wait for Backup domain Write protection enable */
sahilmgandhi 18:6a4db94011d3 416 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 while((PWR->CR & PWR_CR_DBP) == RESET)
sahilmgandhi 18:6a4db94011d3 419 {
sahilmgandhi 18:6a4db94011d3 420 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 421 {
sahilmgandhi 18:6a4db94011d3 422 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 423 }
sahilmgandhi 18:6a4db94011d3 424 }
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426 /* Set the new LSE configuration -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 427 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
sahilmgandhi 18:6a4db94011d3 428 /* Check the LSE State */
sahilmgandhi 18:6a4db94011d3 429 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
sahilmgandhi 18:6a4db94011d3 430 {
sahilmgandhi 18:6a4db94011d3 431 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 432 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 /* Wait till LSE is ready */
sahilmgandhi 18:6a4db94011d3 435 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
sahilmgandhi 18:6a4db94011d3 436 {
sahilmgandhi 18:6a4db94011d3 437 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 438 {
sahilmgandhi 18:6a4db94011d3 439 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 440 }
sahilmgandhi 18:6a4db94011d3 441 }
sahilmgandhi 18:6a4db94011d3 442 }
sahilmgandhi 18:6a4db94011d3 443 else
sahilmgandhi 18:6a4db94011d3 444 {
sahilmgandhi 18:6a4db94011d3 445 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 446 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 /* Wait till LSE is ready */
sahilmgandhi 18:6a4db94011d3 449 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
sahilmgandhi 18:6a4db94011d3 450 {
sahilmgandhi 18:6a4db94011d3 451 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 452 {
sahilmgandhi 18:6a4db94011d3 453 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 454 }
sahilmgandhi 18:6a4db94011d3 455 }
sahilmgandhi 18:6a4db94011d3 456 }
sahilmgandhi 18:6a4db94011d3 457 }
sahilmgandhi 18:6a4db94011d3 458 /*-------------------------------- PLL Configuration -----------------------*/
sahilmgandhi 18:6a4db94011d3 459 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 460 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
sahilmgandhi 18:6a4db94011d3 461 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
sahilmgandhi 18:6a4db94011d3 462 {
sahilmgandhi 18:6a4db94011d3 463 /* Check if the PLL is used as system clock or not */
sahilmgandhi 18:6a4db94011d3 464 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
sahilmgandhi 18:6a4db94011d3 465 {
sahilmgandhi 18:6a4db94011d3 466 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
sahilmgandhi 18:6a4db94011d3 467 {
sahilmgandhi 18:6a4db94011d3 468 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 469 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
sahilmgandhi 18:6a4db94011d3 470 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
sahilmgandhi 18:6a4db94011d3 471 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
sahilmgandhi 18:6a4db94011d3 472 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
sahilmgandhi 18:6a4db94011d3 473 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /* Disable the main PLL. */
sahilmgandhi 18:6a4db94011d3 476 __HAL_RCC_PLL_DISABLE();
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 479 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 /* Wait till PLL is ready */
sahilmgandhi 18:6a4db94011d3 482 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
sahilmgandhi 18:6a4db94011d3 483 {
sahilmgandhi 18:6a4db94011d3 484 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 485 {
sahilmgandhi 18:6a4db94011d3 486 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 487 }
sahilmgandhi 18:6a4db94011d3 488 }
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 /* Configure the main PLL clock source, multiplication and division factors. */
sahilmgandhi 18:6a4db94011d3 491 WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
sahilmgandhi 18:6a4db94011d3 492 RCC_OscInitStruct->PLL.PLLM | \
sahilmgandhi 18:6a4db94011d3 493 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
sahilmgandhi 18:6a4db94011d3 494 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
sahilmgandhi 18:6a4db94011d3 495 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
sahilmgandhi 18:6a4db94011d3 496 /* Enable the main PLL. */
sahilmgandhi 18:6a4db94011d3 497 __HAL_RCC_PLL_ENABLE();
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 500 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 501
sahilmgandhi 18:6a4db94011d3 502 /* Wait till PLL is ready */
sahilmgandhi 18:6a4db94011d3 503 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 504 {
sahilmgandhi 18:6a4db94011d3 505 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 506 {
sahilmgandhi 18:6a4db94011d3 507 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 508 }
sahilmgandhi 18:6a4db94011d3 509 }
sahilmgandhi 18:6a4db94011d3 510 }
sahilmgandhi 18:6a4db94011d3 511 else
sahilmgandhi 18:6a4db94011d3 512 {
sahilmgandhi 18:6a4db94011d3 513 /* Disable the main PLL. */
sahilmgandhi 18:6a4db94011d3 514 __HAL_RCC_PLL_DISABLE();
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 517 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 /* Wait till PLL is ready */
sahilmgandhi 18:6a4db94011d3 520 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
sahilmgandhi 18:6a4db94011d3 521 {
sahilmgandhi 18:6a4db94011d3 522 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 523 {
sahilmgandhi 18:6a4db94011d3 524 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 525 }
sahilmgandhi 18:6a4db94011d3 526 }
sahilmgandhi 18:6a4db94011d3 527 }
sahilmgandhi 18:6a4db94011d3 528 }
sahilmgandhi 18:6a4db94011d3 529 else
sahilmgandhi 18:6a4db94011d3 530 {
sahilmgandhi 18:6a4db94011d3 531 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 532 }
sahilmgandhi 18:6a4db94011d3 533 }
sahilmgandhi 18:6a4db94011d3 534 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 535 }
sahilmgandhi 18:6a4db94011d3 536
sahilmgandhi 18:6a4db94011d3 537 /**
sahilmgandhi 18:6a4db94011d3 538 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
sahilmgandhi 18:6a4db94011d3 539 * parameters in the RCC_ClkInitStruct.
sahilmgandhi 18:6a4db94011d3 540 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
sahilmgandhi 18:6a4db94011d3 541 * contains the configuration information for the RCC peripheral.
sahilmgandhi 18:6a4db94011d3 542 * @param FLatency: FLASH Latency, this parameter depend on device selected
sahilmgandhi 18:6a4db94011d3 543 *
sahilmgandhi 18:6a4db94011d3 544 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
sahilmgandhi 18:6a4db94011d3 545 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
sahilmgandhi 18:6a4db94011d3 546 *
sahilmgandhi 18:6a4db94011d3 547 * @note The HSI is used (enabled by hardware) as system clock source after
sahilmgandhi 18:6a4db94011d3 548 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
sahilmgandhi 18:6a4db94011d3 549 * of failure of the HSE used directly or indirectly as system clock
sahilmgandhi 18:6a4db94011d3 550 * (if the Clock Security System CSS is enabled).
sahilmgandhi 18:6a4db94011d3 551 *
sahilmgandhi 18:6a4db94011d3 552 * @note A switch from one clock source to another occurs only if the target
sahilmgandhi 18:6a4db94011d3 553 * clock source is ready (clock stable after startup delay or PLL locked).
sahilmgandhi 18:6a4db94011d3 554 * If a clock source which is not yet ready is selected, the switch will
sahilmgandhi 18:6a4db94011d3 555 * occur when the clock source will be ready.
sahilmgandhi 18:6a4db94011d3 556 *
sahilmgandhi 18:6a4db94011d3 557 * @note Depending on the device voltage range, the software has to set correctly
sahilmgandhi 18:6a4db94011d3 558 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
sahilmgandhi 18:6a4db94011d3 559 * (for more details refer to section above "Initialization/de-initialization functions")
sahilmgandhi 18:6a4db94011d3 560 * @retval None
sahilmgandhi 18:6a4db94011d3 561 */
sahilmgandhi 18:6a4db94011d3 562 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
sahilmgandhi 18:6a4db94011d3 563 {
sahilmgandhi 18:6a4db94011d3 564 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 567 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
sahilmgandhi 18:6a4db94011d3 568 assert_param(IS_FLASH_LATENCY(FLatency));
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
sahilmgandhi 18:6a4db94011d3 571 must be correctly programmed according to the frequency of the CPU clock
sahilmgandhi 18:6a4db94011d3 572 (HCLK) and the supply voltage of the device. */
sahilmgandhi 18:6a4db94011d3 573
sahilmgandhi 18:6a4db94011d3 574 /* Increasing the number of wait states because of higher CPU frequency */
sahilmgandhi 18:6a4db94011d3 575 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
sahilmgandhi 18:6a4db94011d3 576 {
sahilmgandhi 18:6a4db94011d3 577 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
sahilmgandhi 18:6a4db94011d3 578 __HAL_FLASH_SET_LATENCY(FLatency);
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 /* Check that the new number of wait states is taken into account to access the Flash
sahilmgandhi 18:6a4db94011d3 581 memory by reading the FLASH_ACR register */
sahilmgandhi 18:6a4db94011d3 582 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
sahilmgandhi 18:6a4db94011d3 583 {
sahilmgandhi 18:6a4db94011d3 584 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 585 }
sahilmgandhi 18:6a4db94011d3 586 }
sahilmgandhi 18:6a4db94011d3 587
sahilmgandhi 18:6a4db94011d3 588 /*-------------------------- HCLK Configuration --------------------------*/
sahilmgandhi 18:6a4db94011d3 589 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
sahilmgandhi 18:6a4db94011d3 590 {
sahilmgandhi 18:6a4db94011d3 591 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
sahilmgandhi 18:6a4db94011d3 592 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
sahilmgandhi 18:6a4db94011d3 593 }
sahilmgandhi 18:6a4db94011d3 594
sahilmgandhi 18:6a4db94011d3 595 /*------------------------- SYSCLK Configuration ---------------------------*/
sahilmgandhi 18:6a4db94011d3 596 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
sahilmgandhi 18:6a4db94011d3 597 {
sahilmgandhi 18:6a4db94011d3 598 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 /* HSE is selected as System Clock Source */
sahilmgandhi 18:6a4db94011d3 601 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 602 {
sahilmgandhi 18:6a4db94011d3 603 /* Check the HSE ready flag */
sahilmgandhi 18:6a4db94011d3 604 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
sahilmgandhi 18:6a4db94011d3 605 {
sahilmgandhi 18:6a4db94011d3 606 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 607 }
sahilmgandhi 18:6a4db94011d3 608 }
sahilmgandhi 18:6a4db94011d3 609 /* PLL is selected as System Clock Source */
sahilmgandhi 18:6a4db94011d3 610 else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
sahilmgandhi 18:6a4db94011d3 611 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
sahilmgandhi 18:6a4db94011d3 612 {
sahilmgandhi 18:6a4db94011d3 613 /* Check the PLL ready flag */
sahilmgandhi 18:6a4db94011d3 614 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 615 {
sahilmgandhi 18:6a4db94011d3 616 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 617 }
sahilmgandhi 18:6a4db94011d3 618 }
sahilmgandhi 18:6a4db94011d3 619 /* HSI is selected as System Clock Source */
sahilmgandhi 18:6a4db94011d3 620 else
sahilmgandhi 18:6a4db94011d3 621 {
sahilmgandhi 18:6a4db94011d3 622 /* Check the HSI ready flag */
sahilmgandhi 18:6a4db94011d3 623 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
sahilmgandhi 18:6a4db94011d3 624 {
sahilmgandhi 18:6a4db94011d3 625 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 626 }
sahilmgandhi 18:6a4db94011d3 627 }
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
sahilmgandhi 18:6a4db94011d3 630 /* Get Start Tick*/
sahilmgandhi 18:6a4db94011d3 631 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 632
sahilmgandhi 18:6a4db94011d3 633 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 634 {
sahilmgandhi 18:6a4db94011d3 635 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
sahilmgandhi 18:6a4db94011d3 636 {
sahilmgandhi 18:6a4db94011d3 637 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 638 {
sahilmgandhi 18:6a4db94011d3 639 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 640 }
sahilmgandhi 18:6a4db94011d3 641 }
sahilmgandhi 18:6a4db94011d3 642 }
sahilmgandhi 18:6a4db94011d3 643 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
sahilmgandhi 18:6a4db94011d3 644 {
sahilmgandhi 18:6a4db94011d3 645 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
sahilmgandhi 18:6a4db94011d3 646 {
sahilmgandhi 18:6a4db94011d3 647 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 648 {
sahilmgandhi 18:6a4db94011d3 649 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 650 }
sahilmgandhi 18:6a4db94011d3 651 }
sahilmgandhi 18:6a4db94011d3 652 }
sahilmgandhi 18:6a4db94011d3 653 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
sahilmgandhi 18:6a4db94011d3 654 {
sahilmgandhi 18:6a4db94011d3 655 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
sahilmgandhi 18:6a4db94011d3 656 {
sahilmgandhi 18:6a4db94011d3 657 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 658 {
sahilmgandhi 18:6a4db94011d3 659 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 660 }
sahilmgandhi 18:6a4db94011d3 661 }
sahilmgandhi 18:6a4db94011d3 662 }
sahilmgandhi 18:6a4db94011d3 663 else
sahilmgandhi 18:6a4db94011d3 664 {
sahilmgandhi 18:6a4db94011d3 665 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
sahilmgandhi 18:6a4db94011d3 666 {
sahilmgandhi 18:6a4db94011d3 667 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
sahilmgandhi 18:6a4db94011d3 668 {
sahilmgandhi 18:6a4db94011d3 669 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 670 }
sahilmgandhi 18:6a4db94011d3 671 }
sahilmgandhi 18:6a4db94011d3 672 }
sahilmgandhi 18:6a4db94011d3 673 }
sahilmgandhi 18:6a4db94011d3 674
sahilmgandhi 18:6a4db94011d3 675 /* Decreasing the number of wait states because of lower CPU frequency */
sahilmgandhi 18:6a4db94011d3 676 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
sahilmgandhi 18:6a4db94011d3 677 {
sahilmgandhi 18:6a4db94011d3 678 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
sahilmgandhi 18:6a4db94011d3 679 __HAL_FLASH_SET_LATENCY(FLatency);
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 /* Check that the new number of wait states is taken into account to access the Flash
sahilmgandhi 18:6a4db94011d3 682 memory by reading the FLASH_ACR register */
sahilmgandhi 18:6a4db94011d3 683 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
sahilmgandhi 18:6a4db94011d3 684 {
sahilmgandhi 18:6a4db94011d3 685 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 686 }
sahilmgandhi 18:6a4db94011d3 687 }
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 /*-------------------------- PCLK1 Configuration ---------------------------*/
sahilmgandhi 18:6a4db94011d3 690 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
sahilmgandhi 18:6a4db94011d3 691 {
sahilmgandhi 18:6a4db94011d3 692 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
sahilmgandhi 18:6a4db94011d3 693 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
sahilmgandhi 18:6a4db94011d3 694 }
sahilmgandhi 18:6a4db94011d3 695
sahilmgandhi 18:6a4db94011d3 696 /*-------------------------- PCLK2 Configuration ---------------------------*/
sahilmgandhi 18:6a4db94011d3 697 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
sahilmgandhi 18:6a4db94011d3 698 {
sahilmgandhi 18:6a4db94011d3 699 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
sahilmgandhi 18:6a4db94011d3 700 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
sahilmgandhi 18:6a4db94011d3 701 }
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 /* Update the SystemCoreClock global variable */
sahilmgandhi 18:6a4db94011d3 704 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
sahilmgandhi 18:6a4db94011d3 705
sahilmgandhi 18:6a4db94011d3 706 /* Configure the source of time base considering new system clocks settings*/
sahilmgandhi 18:6a4db94011d3 707 HAL_InitTick (TICK_INT_PRIORITY);
sahilmgandhi 18:6a4db94011d3 708
sahilmgandhi 18:6a4db94011d3 709 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 710 }
sahilmgandhi 18:6a4db94011d3 711
sahilmgandhi 18:6a4db94011d3 712 /**
sahilmgandhi 18:6a4db94011d3 713 * @}
sahilmgandhi 18:6a4db94011d3 714 */
sahilmgandhi 18:6a4db94011d3 715
sahilmgandhi 18:6a4db94011d3 716 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 717 * @brief RCC clocks control functions
sahilmgandhi 18:6a4db94011d3 718 *
sahilmgandhi 18:6a4db94011d3 719 @verbatim
sahilmgandhi 18:6a4db94011d3 720 ===============================================================================
sahilmgandhi 18:6a4db94011d3 721 ##### Peripheral Control functions #####
sahilmgandhi 18:6a4db94011d3 722 ===============================================================================
sahilmgandhi 18:6a4db94011d3 723 [..]
sahilmgandhi 18:6a4db94011d3 724 This subsection provides a set of functions allowing to control the RCC Clocks
sahilmgandhi 18:6a4db94011d3 725 frequencies.
sahilmgandhi 18:6a4db94011d3 726
sahilmgandhi 18:6a4db94011d3 727 @endverbatim
sahilmgandhi 18:6a4db94011d3 728 * @{
sahilmgandhi 18:6a4db94011d3 729 */
sahilmgandhi 18:6a4db94011d3 730
sahilmgandhi 18:6a4db94011d3 731 /**
sahilmgandhi 18:6a4db94011d3 732 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
sahilmgandhi 18:6a4db94011d3 733 * @note PA8/PC9 should be configured in alternate function mode.
sahilmgandhi 18:6a4db94011d3 734 * @param RCC_MCOx: specifies the output direction for the clock source.
sahilmgandhi 18:6a4db94011d3 735 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 736 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
sahilmgandhi 18:6a4db94011d3 737 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
sahilmgandhi 18:6a4db94011d3 738 * @param RCC_MCOSource: specifies the clock source to output.
sahilmgandhi 18:6a4db94011d3 739 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 740 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 741 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 742 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 743 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
sahilmgandhi 18:6a4db94011d3 744 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 745 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
sahilmgandhi 18:6a4db94011d3 746 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
sahilmgandhi 18:6a4db94011d3 747 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 748 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
sahilmgandhi 18:6a4db94011d3 749 * @param RCC_MCODiv: specifies the MCOx prescaler.
sahilmgandhi 18:6a4db94011d3 750 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 751 * @arg RCC_MCODIV_1: no division applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 752 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 753 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 754 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 755 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
sahilmgandhi 18:6a4db94011d3 756 * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
sahilmgandhi 18:6a4db94011d3 757 * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
sahilmgandhi 18:6a4db94011d3 758 * @retval None
sahilmgandhi 18:6a4db94011d3 759 */
sahilmgandhi 18:6a4db94011d3 760 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
sahilmgandhi 18:6a4db94011d3 761 {
sahilmgandhi 18:6a4db94011d3 762 GPIO_InitTypeDef GPIO_InitStruct;
sahilmgandhi 18:6a4db94011d3 763 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 764 assert_param(IS_RCC_MCO(RCC_MCOx));
sahilmgandhi 18:6a4db94011d3 765 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
sahilmgandhi 18:6a4db94011d3 766 /* RCC_MCO1 */
sahilmgandhi 18:6a4db94011d3 767 if(RCC_MCOx == RCC_MCO1)
sahilmgandhi 18:6a4db94011d3 768 {
sahilmgandhi 18:6a4db94011d3 769 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
sahilmgandhi 18:6a4db94011d3 770
sahilmgandhi 18:6a4db94011d3 771 /* MCO1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 772 __MCO1_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 /* Configure the MCO1 pin in alternate function mode */
sahilmgandhi 18:6a4db94011d3 775 GPIO_InitStruct.Pin = MCO1_PIN;
sahilmgandhi 18:6a4db94011d3 776 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
sahilmgandhi 18:6a4db94011d3 777 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
sahilmgandhi 18:6a4db94011d3 778 GPIO_InitStruct.Pull = GPIO_NOPULL;
sahilmgandhi 18:6a4db94011d3 779 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
sahilmgandhi 18:6a4db94011d3 780 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
sahilmgandhi 18:6a4db94011d3 781
sahilmgandhi 18:6a4db94011d3 782 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
sahilmgandhi 18:6a4db94011d3 783 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
sahilmgandhi 18:6a4db94011d3 786 #if defined(RCC_CFGR_MCO1EN)
sahilmgandhi 18:6a4db94011d3 787 __HAL_RCC_MCO1_ENABLE();
sahilmgandhi 18:6a4db94011d3 788 #endif /* RCC_CFGR_MCO1EN */
sahilmgandhi 18:6a4db94011d3 789 }
sahilmgandhi 18:6a4db94011d3 790 #if defined(RCC_CFGR_MCO2)
sahilmgandhi 18:6a4db94011d3 791 else
sahilmgandhi 18:6a4db94011d3 792 {
sahilmgandhi 18:6a4db94011d3 793 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 /* MCO2 Clock Enable */
sahilmgandhi 18:6a4db94011d3 796 __MCO2_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 797
sahilmgandhi 18:6a4db94011d3 798 /* Configure the MCO2 pin in alternate function mode */
sahilmgandhi 18:6a4db94011d3 799 GPIO_InitStruct.Pin = MCO2_PIN;
sahilmgandhi 18:6a4db94011d3 800 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
sahilmgandhi 18:6a4db94011d3 801 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
sahilmgandhi 18:6a4db94011d3 802 GPIO_InitStruct.Pull = GPIO_NOPULL;
sahilmgandhi 18:6a4db94011d3 803 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
sahilmgandhi 18:6a4db94011d3 804 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
sahilmgandhi 18:6a4db94011d3 805
sahilmgandhi 18:6a4db94011d3 806 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
sahilmgandhi 18:6a4db94011d3 807 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
sahilmgandhi 18:6a4db94011d3 808
sahilmgandhi 18:6a4db94011d3 809 /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
sahilmgandhi 18:6a4db94011d3 810 #if defined(RCC_CFGR_MCO2EN)
sahilmgandhi 18:6a4db94011d3 811 __HAL_RCC_MCO2_ENABLE();
sahilmgandhi 18:6a4db94011d3 812 #endif /* RCC_CFGR_MCO2EN */
sahilmgandhi 18:6a4db94011d3 813 }
sahilmgandhi 18:6a4db94011d3 814 #endif /* RCC_CFGR_MCO2 */
sahilmgandhi 18:6a4db94011d3 815 }
sahilmgandhi 18:6a4db94011d3 816
sahilmgandhi 18:6a4db94011d3 817 /**
sahilmgandhi 18:6a4db94011d3 818 * @brief Enables the Clock Security System.
sahilmgandhi 18:6a4db94011d3 819 * @note If a failure is detected on the HSE oscillator clock, this oscillator
sahilmgandhi 18:6a4db94011d3 820 * is automatically disabled and an interrupt is generated to inform the
sahilmgandhi 18:6a4db94011d3 821 * software about the failure (Clock Security System Interrupt, CSSI),
sahilmgandhi 18:6a4db94011d3 822 * allowing the MCU to perform rescue operations. The CSSI is linked to
sahilmgandhi 18:6a4db94011d3 823 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
sahilmgandhi 18:6a4db94011d3 824 * @retval None
sahilmgandhi 18:6a4db94011d3 825 */
sahilmgandhi 18:6a4db94011d3 826 void HAL_RCC_EnableCSS(void)
sahilmgandhi 18:6a4db94011d3 827 {
sahilmgandhi 18:6a4db94011d3 828 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
sahilmgandhi 18:6a4db94011d3 829 }
sahilmgandhi 18:6a4db94011d3 830
sahilmgandhi 18:6a4db94011d3 831 /**
sahilmgandhi 18:6a4db94011d3 832 * @brief Disables the Clock Security System.
sahilmgandhi 18:6a4db94011d3 833 * @retval None
sahilmgandhi 18:6a4db94011d3 834 */
sahilmgandhi 18:6a4db94011d3 835 void HAL_RCC_DisableCSS(void)
sahilmgandhi 18:6a4db94011d3 836 {
sahilmgandhi 18:6a4db94011d3 837 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
sahilmgandhi 18:6a4db94011d3 838 }
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 /**
sahilmgandhi 18:6a4db94011d3 841 * @brief Returns the SYSCLK frequency
sahilmgandhi 18:6a4db94011d3 842 *
sahilmgandhi 18:6a4db94011d3 843 * @note The system frequency computed by this function is not the real
sahilmgandhi 18:6a4db94011d3 844 * frequency in the chip. It is calculated based on the predefined
sahilmgandhi 18:6a4db94011d3 845 * constant and the selected clock source:
sahilmgandhi 18:6a4db94011d3 846 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
sahilmgandhi 18:6a4db94011d3 847 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
sahilmgandhi 18:6a4db94011d3 848 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
sahilmgandhi 18:6a4db94011d3 849 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
sahilmgandhi 18:6a4db94011d3 850 * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
sahilmgandhi 18:6a4db94011d3 851 * 16 MHz) but the real value may vary depending on the variations
sahilmgandhi 18:6a4db94011d3 852 * in voltage and temperature.
sahilmgandhi 18:6a4db94011d3 853 * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
sahilmgandhi 18:6a4db94011d3 854 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
sahilmgandhi 18:6a4db94011d3 855 * frequency of the crystal used. Otherwise, this function may
sahilmgandhi 18:6a4db94011d3 856 * have wrong result.
sahilmgandhi 18:6a4db94011d3 857 *
sahilmgandhi 18:6a4db94011d3 858 * @note The result of this function could be not correct when using fractional
sahilmgandhi 18:6a4db94011d3 859 * value for HSE crystal.
sahilmgandhi 18:6a4db94011d3 860 *
sahilmgandhi 18:6a4db94011d3 861 * @note This function can be used by the user application to compute the
sahilmgandhi 18:6a4db94011d3 862 * baudrate for the communication peripherals or configure other parameters.
sahilmgandhi 18:6a4db94011d3 863 *
sahilmgandhi 18:6a4db94011d3 864 * @note Each time SYSCLK changes, this function must be called to update the
sahilmgandhi 18:6a4db94011d3 865 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi 18:6a4db94011d3 866 *
sahilmgandhi 18:6a4db94011d3 867 *
sahilmgandhi 18:6a4db94011d3 868 * @retval SYSCLK frequency
sahilmgandhi 18:6a4db94011d3 869 */
sahilmgandhi 18:6a4db94011d3 870 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
sahilmgandhi 18:6a4db94011d3 871 {
sahilmgandhi 18:6a4db94011d3 872 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
sahilmgandhi 18:6a4db94011d3 873 uint32_t sysclockfreq = 0U;
sahilmgandhi 18:6a4db94011d3 874
sahilmgandhi 18:6a4db94011d3 875 /* Get SYSCLK source -------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 876 switch (RCC->CFGR & RCC_CFGR_SWS)
sahilmgandhi 18:6a4db94011d3 877 {
sahilmgandhi 18:6a4db94011d3 878 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
sahilmgandhi 18:6a4db94011d3 879 {
sahilmgandhi 18:6a4db94011d3 880 sysclockfreq = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 881 break;
sahilmgandhi 18:6a4db94011d3 882 }
sahilmgandhi 18:6a4db94011d3 883 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
sahilmgandhi 18:6a4db94011d3 884 {
sahilmgandhi 18:6a4db94011d3 885 sysclockfreq = HSE_VALUE;
sahilmgandhi 18:6a4db94011d3 886 break;
sahilmgandhi 18:6a4db94011d3 887 }
sahilmgandhi 18:6a4db94011d3 888 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
sahilmgandhi 18:6a4db94011d3 889 {
sahilmgandhi 18:6a4db94011d3 890 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
sahilmgandhi 18:6a4db94011d3 891 SYSCLK = PLL_VCO / PLLP */
sahilmgandhi 18:6a4db94011d3 892 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
sahilmgandhi 18:6a4db94011d3 893 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
sahilmgandhi 18:6a4db94011d3 894 {
sahilmgandhi 18:6a4db94011d3 895 /* HSE used as PLL clock source */
sahilmgandhi 18:6a4db94011d3 896 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
sahilmgandhi 18:6a4db94011d3 897 }
sahilmgandhi 18:6a4db94011d3 898 else
sahilmgandhi 18:6a4db94011d3 899 {
sahilmgandhi 18:6a4db94011d3 900 /* HSI used as PLL clock source */
sahilmgandhi 18:6a4db94011d3 901 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
sahilmgandhi 18:6a4db94011d3 902 }
sahilmgandhi 18:6a4db94011d3 903 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
sahilmgandhi 18:6a4db94011d3 904
sahilmgandhi 18:6a4db94011d3 905 sysclockfreq = pllvco/pllp;
sahilmgandhi 18:6a4db94011d3 906 break;
sahilmgandhi 18:6a4db94011d3 907 }
sahilmgandhi 18:6a4db94011d3 908 default:
sahilmgandhi 18:6a4db94011d3 909 {
sahilmgandhi 18:6a4db94011d3 910 sysclockfreq = HSI_VALUE;
sahilmgandhi 18:6a4db94011d3 911 break;
sahilmgandhi 18:6a4db94011d3 912 }
sahilmgandhi 18:6a4db94011d3 913 }
sahilmgandhi 18:6a4db94011d3 914 return sysclockfreq;
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 /**
sahilmgandhi 18:6a4db94011d3 918 * @brief Returns the HCLK frequency
sahilmgandhi 18:6a4db94011d3 919 * @note Each time HCLK changes, this function must be called to update the
sahilmgandhi 18:6a4db94011d3 920 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi 18:6a4db94011d3 921 *
sahilmgandhi 18:6a4db94011d3 922 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
sahilmgandhi 18:6a4db94011d3 923 * and updated within this function
sahilmgandhi 18:6a4db94011d3 924 * @retval HCLK frequency
sahilmgandhi 18:6a4db94011d3 925 */
sahilmgandhi 18:6a4db94011d3 926 uint32_t HAL_RCC_GetHCLKFreq(void)
sahilmgandhi 18:6a4db94011d3 927 {
sahilmgandhi 18:6a4db94011d3 928 return SystemCoreClock;
sahilmgandhi 18:6a4db94011d3 929 }
sahilmgandhi 18:6a4db94011d3 930
sahilmgandhi 18:6a4db94011d3 931 /**
sahilmgandhi 18:6a4db94011d3 932 * @brief Returns the PCLK1 frequency
sahilmgandhi 18:6a4db94011d3 933 * @note Each time PCLK1 changes, this function must be called to update the
sahilmgandhi 18:6a4db94011d3 934 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi 18:6a4db94011d3 935 * @retval PCLK1 frequency
sahilmgandhi 18:6a4db94011d3 936 */
sahilmgandhi 18:6a4db94011d3 937 uint32_t HAL_RCC_GetPCLK1Freq(void)
sahilmgandhi 18:6a4db94011d3 938 {
sahilmgandhi 18:6a4db94011d3 939 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
sahilmgandhi 18:6a4db94011d3 940 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
sahilmgandhi 18:6a4db94011d3 941 }
sahilmgandhi 18:6a4db94011d3 942
sahilmgandhi 18:6a4db94011d3 943 /**
sahilmgandhi 18:6a4db94011d3 944 * @brief Returns the PCLK2 frequency
sahilmgandhi 18:6a4db94011d3 945 * @note Each time PCLK2 changes, this function must be called to update the
sahilmgandhi 18:6a4db94011d3 946 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
sahilmgandhi 18:6a4db94011d3 947 * @retval PCLK2 frequency
sahilmgandhi 18:6a4db94011d3 948 */
sahilmgandhi 18:6a4db94011d3 949 uint32_t HAL_RCC_GetPCLK2Freq(void)
sahilmgandhi 18:6a4db94011d3 950 {
sahilmgandhi 18:6a4db94011d3 951 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
sahilmgandhi 18:6a4db94011d3 952 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
sahilmgandhi 18:6a4db94011d3 953 }
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 /**
sahilmgandhi 18:6a4db94011d3 956 * @brief Configures the RCC_OscInitStruct according to the internal
sahilmgandhi 18:6a4db94011d3 957 * RCC configuration registers.
sahilmgandhi 18:6a4db94011d3 958 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
sahilmgandhi 18:6a4db94011d3 959 * will be configured.
sahilmgandhi 18:6a4db94011d3 960 * @retval None
sahilmgandhi 18:6a4db94011d3 961 */
sahilmgandhi 18:6a4db94011d3 962 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
sahilmgandhi 18:6a4db94011d3 963 {
sahilmgandhi 18:6a4db94011d3 964 /* Set all possible values for the Oscillator type parameter ---------------*/
sahilmgandhi 18:6a4db94011d3 965 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967 /* Get the HSE configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 968 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
sahilmgandhi 18:6a4db94011d3 969 {
sahilmgandhi 18:6a4db94011d3 970 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
sahilmgandhi 18:6a4db94011d3 971 }
sahilmgandhi 18:6a4db94011d3 972 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
sahilmgandhi 18:6a4db94011d3 973 {
sahilmgandhi 18:6a4db94011d3 974 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
sahilmgandhi 18:6a4db94011d3 975 }
sahilmgandhi 18:6a4db94011d3 976 else
sahilmgandhi 18:6a4db94011d3 977 {
sahilmgandhi 18:6a4db94011d3 978 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
sahilmgandhi 18:6a4db94011d3 979 }
sahilmgandhi 18:6a4db94011d3 980
sahilmgandhi 18:6a4db94011d3 981 /* Get the HSI configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 982 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
sahilmgandhi 18:6a4db94011d3 983 {
sahilmgandhi 18:6a4db94011d3 984 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
sahilmgandhi 18:6a4db94011d3 985 }
sahilmgandhi 18:6a4db94011d3 986 else
sahilmgandhi 18:6a4db94011d3 987 {
sahilmgandhi 18:6a4db94011d3 988 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
sahilmgandhi 18:6a4db94011d3 989 }
sahilmgandhi 18:6a4db94011d3 990
sahilmgandhi 18:6a4db94011d3 991 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
sahilmgandhi 18:6a4db94011d3 992
sahilmgandhi 18:6a4db94011d3 993 /* Get the LSE configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 994 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
sahilmgandhi 18:6a4db94011d3 995 {
sahilmgandhi 18:6a4db94011d3 996 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
sahilmgandhi 18:6a4db94011d3 997 }
sahilmgandhi 18:6a4db94011d3 998 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
sahilmgandhi 18:6a4db94011d3 999 {
sahilmgandhi 18:6a4db94011d3 1000 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
sahilmgandhi 18:6a4db94011d3 1001 }
sahilmgandhi 18:6a4db94011d3 1002 else
sahilmgandhi 18:6a4db94011d3 1003 {
sahilmgandhi 18:6a4db94011d3 1004 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
sahilmgandhi 18:6a4db94011d3 1005 }
sahilmgandhi 18:6a4db94011d3 1006
sahilmgandhi 18:6a4db94011d3 1007 /* Get the LSI configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1008 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
sahilmgandhi 18:6a4db94011d3 1009 {
sahilmgandhi 18:6a4db94011d3 1010 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
sahilmgandhi 18:6a4db94011d3 1011 }
sahilmgandhi 18:6a4db94011d3 1012 else
sahilmgandhi 18:6a4db94011d3 1013 {
sahilmgandhi 18:6a4db94011d3 1014 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
sahilmgandhi 18:6a4db94011d3 1015 }
sahilmgandhi 18:6a4db94011d3 1016
sahilmgandhi 18:6a4db94011d3 1017 /* Get the PLL configuration -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1018 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
sahilmgandhi 18:6a4db94011d3 1019 {
sahilmgandhi 18:6a4db94011d3 1020 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
sahilmgandhi 18:6a4db94011d3 1021 }
sahilmgandhi 18:6a4db94011d3 1022 else
sahilmgandhi 18:6a4db94011d3 1023 {
sahilmgandhi 18:6a4db94011d3 1024 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
sahilmgandhi 18:6a4db94011d3 1025 }
sahilmgandhi 18:6a4db94011d3 1026 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
sahilmgandhi 18:6a4db94011d3 1027 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
sahilmgandhi 18:6a4db94011d3 1028 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
sahilmgandhi 18:6a4db94011d3 1029 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
sahilmgandhi 18:6a4db94011d3 1030 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
sahilmgandhi 18:6a4db94011d3 1031 }
sahilmgandhi 18:6a4db94011d3 1032
sahilmgandhi 18:6a4db94011d3 1033 /**
sahilmgandhi 18:6a4db94011d3 1034 * @brief Configures the RCC_ClkInitStruct according to the internal
sahilmgandhi 18:6a4db94011d3 1035 * RCC configuration registers.
sahilmgandhi 18:6a4db94011d3 1036 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
sahilmgandhi 18:6a4db94011d3 1037 * will be configured.
sahilmgandhi 18:6a4db94011d3 1038 * @param pFLatency: Pointer on the Flash Latency.
sahilmgandhi 18:6a4db94011d3 1039 * @retval None
sahilmgandhi 18:6a4db94011d3 1040 */
sahilmgandhi 18:6a4db94011d3 1041 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
sahilmgandhi 18:6a4db94011d3 1042 {
sahilmgandhi 18:6a4db94011d3 1043 /* Set all possible values for the Clock type parameter --------------------*/
sahilmgandhi 18:6a4db94011d3 1044 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
sahilmgandhi 18:6a4db94011d3 1045
sahilmgandhi 18:6a4db94011d3 1046 /* Get the SYSCLK configuration --------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1047 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
sahilmgandhi 18:6a4db94011d3 1048
sahilmgandhi 18:6a4db94011d3 1049 /* Get the HCLK configuration ----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1050 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
sahilmgandhi 18:6a4db94011d3 1051
sahilmgandhi 18:6a4db94011d3 1052 /* Get the APB1 configuration ----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1053 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
sahilmgandhi 18:6a4db94011d3 1054
sahilmgandhi 18:6a4db94011d3 1055 /* Get the APB2 configuration ----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1056 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
sahilmgandhi 18:6a4db94011d3 1057
sahilmgandhi 18:6a4db94011d3 1058 /* Get the Flash Wait State (Latency) configuration ------------------------*/
sahilmgandhi 18:6a4db94011d3 1059 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
sahilmgandhi 18:6a4db94011d3 1060 }
sahilmgandhi 18:6a4db94011d3 1061
sahilmgandhi 18:6a4db94011d3 1062 /**
sahilmgandhi 18:6a4db94011d3 1063 * @brief This function handles the RCC CSS interrupt request.
sahilmgandhi 18:6a4db94011d3 1064 * @note This API should be called under the NMI_Handler().
sahilmgandhi 18:6a4db94011d3 1065 * @retval None
sahilmgandhi 18:6a4db94011d3 1066 */
sahilmgandhi 18:6a4db94011d3 1067 void HAL_RCC_NMI_IRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1068 {
sahilmgandhi 18:6a4db94011d3 1069 /* Check RCC CSSF flag */
sahilmgandhi 18:6a4db94011d3 1070 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
sahilmgandhi 18:6a4db94011d3 1071 {
sahilmgandhi 18:6a4db94011d3 1072 /* RCC Clock Security System interrupt user callback */
sahilmgandhi 18:6a4db94011d3 1073 HAL_RCC_CSSCallback();
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075 /* Clear RCC CSS pending bit */
sahilmgandhi 18:6a4db94011d3 1076 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
sahilmgandhi 18:6a4db94011d3 1077 }
sahilmgandhi 18:6a4db94011d3 1078 }
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 /**
sahilmgandhi 18:6a4db94011d3 1081 * @brief RCC Clock Security System interrupt callback
sahilmgandhi 18:6a4db94011d3 1082 * @retval None
sahilmgandhi 18:6a4db94011d3 1083 */
sahilmgandhi 18:6a4db94011d3 1084 __weak void HAL_RCC_CSSCallback(void)
sahilmgandhi 18:6a4db94011d3 1085 {
sahilmgandhi 18:6a4db94011d3 1086 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1087 the HAL_RCC_CSSCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1088 */
sahilmgandhi 18:6a4db94011d3 1089 }
sahilmgandhi 18:6a4db94011d3 1090
sahilmgandhi 18:6a4db94011d3 1091 /**
sahilmgandhi 18:6a4db94011d3 1092 * @}
sahilmgandhi 18:6a4db94011d3 1093 */
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 /**
sahilmgandhi 18:6a4db94011d3 1096 * @}
sahilmgandhi 18:6a4db94011d3 1097 */
sahilmgandhi 18:6a4db94011d3 1098
sahilmgandhi 18:6a4db94011d3 1099 #endif /* HAL_RCC_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1100 /**
sahilmgandhi 18:6a4db94011d3 1101 * @}
sahilmgandhi 18:6a4db94011d3 1102 */
sahilmgandhi 18:6a4db94011d3 1103
sahilmgandhi 18:6a4db94011d3 1104 /**
sahilmgandhi 18:6a4db94011d3 1105 * @}
sahilmgandhi 18:6a4db94011d3 1106 */
sahilmgandhi 18:6a4db94011d3 1107
sahilmgandhi 18:6a4db94011d3 1108 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/