MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_qspi.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief QSPI HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 9 * functionalities of the QuadSPI interface (QSPI).
sahilmgandhi 18:6a4db94011d3 10 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 11 * + Indirect functional mode management
sahilmgandhi 18:6a4db94011d3 12 * + Memory-mapped functional mode management
sahilmgandhi 18:6a4db94011d3 13 * + Auto-polling functional mode management
sahilmgandhi 18:6a4db94011d3 14 * + Interrupts and flags management
sahilmgandhi 18:6a4db94011d3 15 * + DMA channel configuration for indirect functional mode
sahilmgandhi 18:6a4db94011d3 16 * + Errors management and abort functionality
sahilmgandhi 18:6a4db94011d3 17 *
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 @verbatim
sahilmgandhi 18:6a4db94011d3 20 ===============================================================================
sahilmgandhi 18:6a4db94011d3 21 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 22 ===============================================================================
sahilmgandhi 18:6a4db94011d3 23 [..]
sahilmgandhi 18:6a4db94011d3 24 *** Initialization ***
sahilmgandhi 18:6a4db94011d3 25 ======================
sahilmgandhi 18:6a4db94011d3 26 [..]
sahilmgandhi 18:6a4db94011d3 27 (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
sahilmgandhi 18:6a4db94011d3 28 (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
sahilmgandhi 18:6a4db94011d3 29 (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
sahilmgandhi 18:6a4db94011d3 30 (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
sahilmgandhi 18:6a4db94011d3 31 (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
sahilmgandhi 18:6a4db94011d3 32 (++) If interrupt mode is used, enable and configure QuadSPI global
sahilmgandhi 18:6a4db94011d3 33 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
sahilmgandhi 18:6a4db94011d3 34 (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
sahilmgandhi 18:6a4db94011d3 35 with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
sahilmgandhi 18:6a4db94011d3 36 link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
sahilmgandhi 18:6a4db94011d3 37 DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
sahilmgandhi 18:6a4db94011d3 38 (#) Configure the flash size, the clock prescaler, the fifo threshold, the
sahilmgandhi 18:6a4db94011d3 39 clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 *** Indirect functional mode ***
sahilmgandhi 18:6a4db94011d3 42 ================================
sahilmgandhi 18:6a4db94011d3 43 [..]
sahilmgandhi 18:6a4db94011d3 44 (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
sahilmgandhi 18:6a4db94011d3 45 functions :
sahilmgandhi 18:6a4db94011d3 46 (++) Instruction phase : the mode used and if present the instruction opcode.
sahilmgandhi 18:6a4db94011d3 47 (++) Address phase : the mode used and if present the size and the address value.
sahilmgandhi 18:6a4db94011d3 48 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
sahilmgandhi 18:6a4db94011d3 49 bytes values.
sahilmgandhi 18:6a4db94011d3 50 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
sahilmgandhi 18:6a4db94011d3 51 (++) Data phase : the mode used and if present the number of bytes.
sahilmgandhi 18:6a4db94011d3 52 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
sahilmgandhi 18:6a4db94011d3 53 if activated.
sahilmgandhi 18:6a4db94011d3 54 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
sahilmgandhi 18:6a4db94011d3 55 (#) If no data is required for the command, it is sent directly to the memory :
sahilmgandhi 18:6a4db94011d3 56 (++) In polling mode, the output of the function is done when the transfer is complete.
sahilmgandhi 18:6a4db94011d3 57 (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
sahilmgandhi 18:6a4db94011d3 58 (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
sahilmgandhi 18:6a4db94011d3 59 HAL_QSPI_Transmit_IT() after the command configuration :
sahilmgandhi 18:6a4db94011d3 60 (++) In polling mode, the output of the function is done when the transfer is complete.
sahilmgandhi 18:6a4db94011d3 61 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
sahilmgandhi 18:6a4db94011d3 62 is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
sahilmgandhi 18:6a4db94011d3 63 (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
sahilmgandhi 18:6a4db94011d3 64 HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
sahilmgandhi 18:6a4db94011d3 65 (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
sahilmgandhi 18:6a4db94011d3 66 HAL_QSPI_Receive_IT() after the command configuration :
sahilmgandhi 18:6a4db94011d3 67 (++) In polling mode, the output of the function is done when the transfer is complete.
sahilmgandhi 18:6a4db94011d3 68 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
sahilmgandhi 18:6a4db94011d3 69 is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
sahilmgandhi 18:6a4db94011d3 70 (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
sahilmgandhi 18:6a4db94011d3 71 HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 *** Auto-polling functional mode ***
sahilmgandhi 18:6a4db94011d3 74 ====================================
sahilmgandhi 18:6a4db94011d3 75 [..]
sahilmgandhi 18:6a4db94011d3 76 (#) Configure the command sequence and the auto-polling functional mode using the
sahilmgandhi 18:6a4db94011d3 77 HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
sahilmgandhi 18:6a4db94011d3 78 (++) Instruction phase : the mode used and if present the instruction opcode.
sahilmgandhi 18:6a4db94011d3 79 (++) Address phase : the mode used and if present the size and the address value.
sahilmgandhi 18:6a4db94011d3 80 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
sahilmgandhi 18:6a4db94011d3 81 bytes values.
sahilmgandhi 18:6a4db94011d3 82 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
sahilmgandhi 18:6a4db94011d3 83 (++) Data phase : the mode used.
sahilmgandhi 18:6a4db94011d3 84 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
sahilmgandhi 18:6a4db94011d3 85 if activated.
sahilmgandhi 18:6a4db94011d3 86 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
sahilmgandhi 18:6a4db94011d3 87 (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
sahilmgandhi 18:6a4db94011d3 88 the polling interval and the automatic stop activation.
sahilmgandhi 18:6a4db94011d3 89 (#) After the configuration :
sahilmgandhi 18:6a4db94011d3 90 (++) In polling mode, the output of the function is done when the status match is reached. The
sahilmgandhi 18:6a4db94011d3 91 automatic stop is activated to avoid an infinite loop.
sahilmgandhi 18:6a4db94011d3 92 (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 *** Memory-mapped functional mode ***
sahilmgandhi 18:6a4db94011d3 95 =====================================
sahilmgandhi 18:6a4db94011d3 96 [..]
sahilmgandhi 18:6a4db94011d3 97 (#) Configure the command sequence and the memory-mapped functional mode using the
sahilmgandhi 18:6a4db94011d3 98 HAL_QSPI_MemoryMapped() functions :
sahilmgandhi 18:6a4db94011d3 99 (++) Instruction phase : the mode used and if present the instruction opcode.
sahilmgandhi 18:6a4db94011d3 100 (++) Address phase : the mode used and the size.
sahilmgandhi 18:6a4db94011d3 101 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
sahilmgandhi 18:6a4db94011d3 102 bytes values.
sahilmgandhi 18:6a4db94011d3 103 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
sahilmgandhi 18:6a4db94011d3 104 (++) Data phase : the mode used.
sahilmgandhi 18:6a4db94011d3 105 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
sahilmgandhi 18:6a4db94011d3 106 if activated.
sahilmgandhi 18:6a4db94011d3 107 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
sahilmgandhi 18:6a4db94011d3 108 (++) The timeout activation and the timeout period.
sahilmgandhi 18:6a4db94011d3 109 (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
sahilmgandhi 18:6a4db94011d3 110 the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 *** Errors management and abort functionality ***
sahilmgandhi 18:6a4db94011d3 113 ==================================================
sahilmgandhi 18:6a4db94011d3 114 [..]
sahilmgandhi 18:6a4db94011d3 115 (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
sahilmgandhi 18:6a4db94011d3 116 (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
sahilmgandhi 18:6a4db94011d3 117 flushes the fifo :
sahilmgandhi 18:6a4db94011d3 118 (++) In polling mode, the output of the function is done when the transfer
sahilmgandhi 18:6a4db94011d3 119 complete bit is set and the busy bit cleared.
sahilmgandhi 18:6a4db94011d3 120 (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
sahilmgandhi 18:6a4db94011d3 121 the transfer complete bi is set.
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 *** Control functions ***
sahilmgandhi 18:6a4db94011d3 124 =========================
sahilmgandhi 18:6a4db94011d3 125 [..]
sahilmgandhi 18:6a4db94011d3 126 (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
sahilmgandhi 18:6a4db94011d3 127 (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
sahilmgandhi 18:6a4db94011d3 128 (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
sahilmgandhi 18:6a4db94011d3 129 (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 *** Workarounds linked to Silicon Limitation ***
sahilmgandhi 18:6a4db94011d3 132 ====================================================
sahilmgandhi 18:6a4db94011d3 133 [..]
sahilmgandhi 18:6a4db94011d3 134 (#) Workarounds Implemented inside HAL Driver
sahilmgandhi 18:6a4db94011d3 135 (++) Extra data written in the FIFO at the end of a read transfer
sahilmgandhi 18:6a4db94011d3 136
sahilmgandhi 18:6a4db94011d3 137 @endverbatim
sahilmgandhi 18:6a4db94011d3 138 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 139 * @attention
sahilmgandhi 18:6a4db94011d3 140 *
sahilmgandhi 18:6a4db94011d3 141 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 142 *
sahilmgandhi 18:6a4db94011d3 143 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 144 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 145 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 146 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 147 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 148 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 149 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 150 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 151 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 152 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 153 *
sahilmgandhi 18:6a4db94011d3 154 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 155 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 156 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 157 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 158 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 159 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 160 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 161 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 162 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 163 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 164 *
sahilmgandhi 18:6a4db94011d3 165 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 166 */
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 169 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 172 * @{
sahilmgandhi 18:6a4db94011d3 173 */
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /** @defgroup QSPI QSPI
sahilmgandhi 18:6a4db94011d3 176 * @brief QSPI HAL module driver
sahilmgandhi 18:6a4db94011d3 177 * @{
sahilmgandhi 18:6a4db94011d3 178 */
sahilmgandhi 18:6a4db94011d3 179 #ifdef HAL_QSPI_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
sahilmgandhi 18:6a4db94011d3 182 defined(STM32F412Rx)
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 185 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 186 /** @addtogroup QSPI_Private_Constants
sahilmgandhi 18:6a4db94011d3 187 * @{
sahilmgandhi 18:6a4db94011d3 188 */
sahilmgandhi 18:6a4db94011d3 189 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U) /*!<Indirect write mode*/
sahilmgandhi 18:6a4db94011d3 190 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
sahilmgandhi 18:6a4db94011d3 191 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
sahilmgandhi 18:6a4db94011d3 192 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
sahilmgandhi 18:6a4db94011d3 193 /**
sahilmgandhi 18:6a4db94011d3 194 * @}
sahilmgandhi 18:6a4db94011d3 195 */
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 198 /** @addtogroup QSPI_Private_Macros QSPI Private Macros
sahilmgandhi 18:6a4db94011d3 199 * @{
sahilmgandhi 18:6a4db94011d3 200 */
sahilmgandhi 18:6a4db94011d3 201 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
sahilmgandhi 18:6a4db94011d3 202 ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
sahilmgandhi 18:6a4db94011d3 203 ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
sahilmgandhi 18:6a4db94011d3 204 ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
sahilmgandhi 18:6a4db94011d3 205 /**
sahilmgandhi 18:6a4db94011d3 206 * @}
sahilmgandhi 18:6a4db94011d3 207 */
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 210 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 211 /** @addtogroup QSPI_Private_Functions QSPI Private Functions
sahilmgandhi 18:6a4db94011d3 212 * @{
sahilmgandhi 18:6a4db94011d3 213 */
sahilmgandhi 18:6a4db94011d3 214 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 215 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 216 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 217 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 218 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 219 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 220 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 221 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
sahilmgandhi 18:6a4db94011d3 222 /**
sahilmgandhi 18:6a4db94011d3 223 * @}
sahilmgandhi 18:6a4db94011d3 224 */
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /* Exported functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
sahilmgandhi 18:6a4db94011d3 229 * @{
sahilmgandhi 18:6a4db94011d3 230 */
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
sahilmgandhi 18:6a4db94011d3 233 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 234 *
sahilmgandhi 18:6a4db94011d3 235 @verbatim
sahilmgandhi 18:6a4db94011d3 236 ===============================================================================
sahilmgandhi 18:6a4db94011d3 237 ##### Initialization and Configuration functions #####
sahilmgandhi 18:6a4db94011d3 238 ===============================================================================
sahilmgandhi 18:6a4db94011d3 239 [..]
sahilmgandhi 18:6a4db94011d3 240 This subsection provides a set of functions allowing to :
sahilmgandhi 18:6a4db94011d3 241 (+) Initialize the QuadSPI.
sahilmgandhi 18:6a4db94011d3 242 (+) De-initialize the QuadSPI.
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 @endverbatim
sahilmgandhi 18:6a4db94011d3 245 * @{
sahilmgandhi 18:6a4db94011d3 246 */
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /**
sahilmgandhi 18:6a4db94011d3 249 * @brief Initializes the QSPI mode according to the specified parameters
sahilmgandhi 18:6a4db94011d3 250 * in the QSPI_InitTypeDef and creates the associated handle.
sahilmgandhi 18:6a4db94011d3 251 * @param hqspi: qspi handle
sahilmgandhi 18:6a4db94011d3 252 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 253 */
sahilmgandhi 18:6a4db94011d3 254 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 255 {
sahilmgandhi 18:6a4db94011d3 256 HAL_StatusTypeDef status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 257 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 /* Check the QSPI handle allocation */
sahilmgandhi 18:6a4db94011d3 260 if(hqspi == NULL)
sahilmgandhi 18:6a4db94011d3 261 {
sahilmgandhi 18:6a4db94011d3 262 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 263 }
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 266 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
sahilmgandhi 18:6a4db94011d3 267 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
sahilmgandhi 18:6a4db94011d3 268 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
sahilmgandhi 18:6a4db94011d3 269 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
sahilmgandhi 18:6a4db94011d3 270 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
sahilmgandhi 18:6a4db94011d3 271 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
sahilmgandhi 18:6a4db94011d3 272 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
sahilmgandhi 18:6a4db94011d3 273 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
sahilmgandhi 18:6a4db94011d3 276 {
sahilmgandhi 18:6a4db94011d3 277 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 /* Process locked */
sahilmgandhi 18:6a4db94011d3 281 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 if(hqspi->State == HAL_QSPI_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 284 {
sahilmgandhi 18:6a4db94011d3 285 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 286 hqspi->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 /* Init the low level hardware : GPIO, CLOCK */
sahilmgandhi 18:6a4db94011d3 289 HAL_QSPI_MspInit(hqspi);
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /* Configure the default timeout for the QSPI memory access */
sahilmgandhi 18:6a4db94011d3 292 HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
sahilmgandhi 18:6a4db94011d3 293 }
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /* Configure QSPI FIFO Threshold */
sahilmgandhi 18:6a4db94011d3 296 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 /* Wait till BUSY flag reset */
sahilmgandhi 18:6a4db94011d3 299 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
sahilmgandhi 18:6a4db94011d3 300
sahilmgandhi 18:6a4db94011d3 301 if(status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 302 {
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 /* Configure QSPI Clock Prescaler and Sample Shift */
sahilmgandhi 18:6a4db94011d3 305 MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Configure QSPI Flash Size, CS High Time and Clock Mode */
sahilmgandhi 18:6a4db94011d3 308 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
sahilmgandhi 18:6a4db94011d3 309 ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 /* Enable the QSPI peripheral */
sahilmgandhi 18:6a4db94011d3 312 __HAL_QSPI_ENABLE(hqspi);
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 /* Set QSPI error code to none */
sahilmgandhi 18:6a4db94011d3 315 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /* Initialize the QSPI state */
sahilmgandhi 18:6a4db94011d3 318 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 319 }
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 322 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /* Return function status */
sahilmgandhi 18:6a4db94011d3 325 return status;
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /**
sahilmgandhi 18:6a4db94011d3 329 * @brief DeInitializes the QSPI peripheral
sahilmgandhi 18:6a4db94011d3 330 * @param hqspi: qspi handle
sahilmgandhi 18:6a4db94011d3 331 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 332 */
sahilmgandhi 18:6a4db94011d3 333 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 334 {
sahilmgandhi 18:6a4db94011d3 335 /* Check the QSPI handle allocation */
sahilmgandhi 18:6a4db94011d3 336 if(hqspi == NULL)
sahilmgandhi 18:6a4db94011d3 337 {
sahilmgandhi 18:6a4db94011d3 338 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 339 }
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 /* Process locked */
sahilmgandhi 18:6a4db94011d3 342 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 343
sahilmgandhi 18:6a4db94011d3 344 /* Disable the QSPI Peripheral Clock */
sahilmgandhi 18:6a4db94011d3 345 __HAL_QSPI_DISABLE(hqspi);
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
sahilmgandhi 18:6a4db94011d3 348 HAL_QSPI_MspDeInit(hqspi);
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 /* Set QSPI error code to none */
sahilmgandhi 18:6a4db94011d3 351 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 /* Initialize the QSPI state */
sahilmgandhi 18:6a4db94011d3 354 hqspi->State = HAL_QSPI_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 357 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 360 }
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 /**
sahilmgandhi 18:6a4db94011d3 363 * @brief QSPI MSP Init
sahilmgandhi 18:6a4db94011d3 364 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 365 * @retval None
sahilmgandhi 18:6a4db94011d3 366 */
sahilmgandhi 18:6a4db94011d3 367 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 368 {
sahilmgandhi 18:6a4db94011d3 369 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 370 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 /* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 373 the HAL_QSPI_MspInit can be implemented in the user file
sahilmgandhi 18:6a4db94011d3 374 */
sahilmgandhi 18:6a4db94011d3 375 }
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 /**
sahilmgandhi 18:6a4db94011d3 378 * @brief QSPI MSP DeInit
sahilmgandhi 18:6a4db94011d3 379 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 380 * @retval None
sahilmgandhi 18:6a4db94011d3 381 */
sahilmgandhi 18:6a4db94011d3 382 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 383 {
sahilmgandhi 18:6a4db94011d3 384 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 385 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 /* NOTE : This function should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 388 the HAL_QSPI_MspDeInit can be implemented in the user file
sahilmgandhi 18:6a4db94011d3 389 */
sahilmgandhi 18:6a4db94011d3 390 }
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 /**
sahilmgandhi 18:6a4db94011d3 393 * @}
sahilmgandhi 18:6a4db94011d3 394 */
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
sahilmgandhi 18:6a4db94011d3 397 * @brief QSPI Transmit/Receive functions
sahilmgandhi 18:6a4db94011d3 398 *
sahilmgandhi 18:6a4db94011d3 399 @verbatim
sahilmgandhi 18:6a4db94011d3 400 ===============================================================================
sahilmgandhi 18:6a4db94011d3 401 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 402 ===============================================================================
sahilmgandhi 18:6a4db94011d3 403 [..]
sahilmgandhi 18:6a4db94011d3 404 This subsection provides a set of functions allowing to :
sahilmgandhi 18:6a4db94011d3 405 (+) Handle the interrupts.
sahilmgandhi 18:6a4db94011d3 406 (+) Handle the command sequence.
sahilmgandhi 18:6a4db94011d3 407 (+) Transmit data in blocking, interrupt or DMA mode.
sahilmgandhi 18:6a4db94011d3 408 (+) Receive data in blocking, interrupt or DMA mode.
sahilmgandhi 18:6a4db94011d3 409 (+) Manage the auto-polling functional mode.
sahilmgandhi 18:6a4db94011d3 410 (+) Manage the memory-mapped functional mode.
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 @endverbatim
sahilmgandhi 18:6a4db94011d3 413 * @{
sahilmgandhi 18:6a4db94011d3 414 */
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 /**
sahilmgandhi 18:6a4db94011d3 417 * @brief This function handles QSPI interrupt request.
sahilmgandhi 18:6a4db94011d3 418 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 419 * @retval None.
sahilmgandhi 18:6a4db94011d3 420 */
sahilmgandhi 18:6a4db94011d3 421 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 422 {
sahilmgandhi 18:6a4db94011d3 423 __IO uint32_t *data_reg;
sahilmgandhi 18:6a4db94011d3 424 uint32_t flag = READ_REG(hqspi->Instance->SR);
sahilmgandhi 18:6a4db94011d3 425 uint32_t itsource = READ_REG(hqspi->Instance->CR);
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
sahilmgandhi 18:6a4db94011d3 428 if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
sahilmgandhi 18:6a4db94011d3 429 {
sahilmgandhi 18:6a4db94011d3 430 data_reg = &hqspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
sahilmgandhi 18:6a4db94011d3 433 {
sahilmgandhi 18:6a4db94011d3 434 /* Transmission process */
sahilmgandhi 18:6a4db94011d3 435 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
sahilmgandhi 18:6a4db94011d3 436 {
sahilmgandhi 18:6a4db94011d3 437 if (hqspi->TxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 438 {
sahilmgandhi 18:6a4db94011d3 439 /* Fill the FIFO until it is full */
sahilmgandhi 18:6a4db94011d3 440 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
sahilmgandhi 18:6a4db94011d3 441 hqspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 442 }
sahilmgandhi 18:6a4db94011d3 443 else
sahilmgandhi 18:6a4db94011d3 444 {
sahilmgandhi 18:6a4db94011d3 445 /* No more data available for the transfer */
sahilmgandhi 18:6a4db94011d3 446 /* Disable the QSPI FIFO Threshold Interrupt */
sahilmgandhi 18:6a4db94011d3 447 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
sahilmgandhi 18:6a4db94011d3 448 break;
sahilmgandhi 18:6a4db94011d3 449 }
sahilmgandhi 18:6a4db94011d3 450 }
sahilmgandhi 18:6a4db94011d3 451 }
sahilmgandhi 18:6a4db94011d3 452 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
sahilmgandhi 18:6a4db94011d3 453 {
sahilmgandhi 18:6a4db94011d3 454 /* Receiving Process */
sahilmgandhi 18:6a4db94011d3 455 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
sahilmgandhi 18:6a4db94011d3 456 {
sahilmgandhi 18:6a4db94011d3 457 if (hqspi->RxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 458 {
sahilmgandhi 18:6a4db94011d3 459 /* Read the FIFO until it is empty */
sahilmgandhi 18:6a4db94011d3 460 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
sahilmgandhi 18:6a4db94011d3 461 hqspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463 else
sahilmgandhi 18:6a4db94011d3 464 {
sahilmgandhi 18:6a4db94011d3 465 /* All data have been received for the transfer */
sahilmgandhi 18:6a4db94011d3 466 /* Disable the QSPI FIFO Threshold Interrupt */
sahilmgandhi 18:6a4db94011d3 467 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
sahilmgandhi 18:6a4db94011d3 468 break;
sahilmgandhi 18:6a4db94011d3 469 }
sahilmgandhi 18:6a4db94011d3 470 }
sahilmgandhi 18:6a4db94011d3 471 }
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 /* FIFO Threshold callback */
sahilmgandhi 18:6a4db94011d3 474 HAL_QSPI_FifoThresholdCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 475 }
sahilmgandhi 18:6a4db94011d3 476
sahilmgandhi 18:6a4db94011d3 477 /* QSPI Transfer Complete interrupt occurred -------------------------------*/
sahilmgandhi 18:6a4db94011d3 478 else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
sahilmgandhi 18:6a4db94011d3 479 {
sahilmgandhi 18:6a4db94011d3 480 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 481 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
sahilmgandhi 18:6a4db94011d3 484 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 /* Transfer complete callback */
sahilmgandhi 18:6a4db94011d3 487 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
sahilmgandhi 18:6a4db94011d3 488 {
sahilmgandhi 18:6a4db94011d3 489 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
sahilmgandhi 18:6a4db94011d3 490 {
sahilmgandhi 18:6a4db94011d3 491 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
sahilmgandhi 18:6a4db94011d3 492 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /* Disable the DMA channel */
sahilmgandhi 18:6a4db94011d3 495 __HAL_DMA_DISABLE(hqspi->hdma);
sahilmgandhi 18:6a4db94011d3 496 }
sahilmgandhi 18:6a4db94011d3 497
sahilmgandhi 18:6a4db94011d3 498 /* Clear Busy bit */
sahilmgandhi 18:6a4db94011d3 499 HAL_QSPI_Abort_IT(hqspi);
sahilmgandhi 18:6a4db94011d3 500
sahilmgandhi 18:6a4db94011d3 501 /* Change state of QSPI */
sahilmgandhi 18:6a4db94011d3 502 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 503
sahilmgandhi 18:6a4db94011d3 504 /* TX Complete callback */
sahilmgandhi 18:6a4db94011d3 505 HAL_QSPI_TxCpltCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 506 }
sahilmgandhi 18:6a4db94011d3 507 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
sahilmgandhi 18:6a4db94011d3 508 {
sahilmgandhi 18:6a4db94011d3 509 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
sahilmgandhi 18:6a4db94011d3 510 {
sahilmgandhi 18:6a4db94011d3 511 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
sahilmgandhi 18:6a4db94011d3 512 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
sahilmgandhi 18:6a4db94011d3 513
sahilmgandhi 18:6a4db94011d3 514 /* Disable the DMA channel */
sahilmgandhi 18:6a4db94011d3 515 __HAL_DMA_DISABLE(hqspi->hdma);
sahilmgandhi 18:6a4db94011d3 516 }
sahilmgandhi 18:6a4db94011d3 517 else
sahilmgandhi 18:6a4db94011d3 518 {
sahilmgandhi 18:6a4db94011d3 519 data_reg = &hqspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 520 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
sahilmgandhi 18:6a4db94011d3 521 {
sahilmgandhi 18:6a4db94011d3 522 if (hqspi->RxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 523 {
sahilmgandhi 18:6a4db94011d3 524 /* Read the last data received in the FIFO until it is empty */
sahilmgandhi 18:6a4db94011d3 525 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
sahilmgandhi 18:6a4db94011d3 526 hqspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 527 }
sahilmgandhi 18:6a4db94011d3 528 else
sahilmgandhi 18:6a4db94011d3 529 {
sahilmgandhi 18:6a4db94011d3 530 /* All data have been received for the transfer */
sahilmgandhi 18:6a4db94011d3 531 break;
sahilmgandhi 18:6a4db94011d3 532 }
sahilmgandhi 18:6a4db94011d3 533 }
sahilmgandhi 18:6a4db94011d3 534 }
sahilmgandhi 18:6a4db94011d3 535 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
sahilmgandhi 18:6a4db94011d3 536 HAL_QSPI_Abort_IT(hqspi);
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 /* Change state of QSPI */
sahilmgandhi 18:6a4db94011d3 539 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 /* RX Complete callback */
sahilmgandhi 18:6a4db94011d3 542 HAL_QSPI_RxCpltCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 543 }
sahilmgandhi 18:6a4db94011d3 544 else if(hqspi->State == HAL_QSPI_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 545 {
sahilmgandhi 18:6a4db94011d3 546 /* Change state of QSPI */
sahilmgandhi 18:6a4db94011d3 547 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 /* Command Complete callback */
sahilmgandhi 18:6a4db94011d3 550 HAL_QSPI_CmdCpltCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 551 }
sahilmgandhi 18:6a4db94011d3 552 else if(hqspi->State == HAL_QSPI_STATE_ABORT)
sahilmgandhi 18:6a4db94011d3 553 {
sahilmgandhi 18:6a4db94011d3 554 /* Change state of QSPI */
sahilmgandhi 18:6a4db94011d3 555 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 558 {
sahilmgandhi 18:6a4db94011d3 559 /* Abort called by the user */
sahilmgandhi 18:6a4db94011d3 560
sahilmgandhi 18:6a4db94011d3 561 /* Abort Complete callback */
sahilmgandhi 18:6a4db94011d3 562 HAL_QSPI_AbortCpltCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 563 }
sahilmgandhi 18:6a4db94011d3 564 else
sahilmgandhi 18:6a4db94011d3 565 {
sahilmgandhi 18:6a4db94011d3 566 /* Abort due to an error (eg : DMA error) */
sahilmgandhi 18:6a4db94011d3 567
sahilmgandhi 18:6a4db94011d3 568 /* Error callback */
sahilmgandhi 18:6a4db94011d3 569 HAL_QSPI_ErrorCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 570 }
sahilmgandhi 18:6a4db94011d3 571 }
sahilmgandhi 18:6a4db94011d3 572 }
sahilmgandhi 18:6a4db94011d3 573
sahilmgandhi 18:6a4db94011d3 574 /* QSPI Status Match interrupt occurred ------------------------------------*/
sahilmgandhi 18:6a4db94011d3 575 else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
sahilmgandhi 18:6a4db94011d3 576 {
sahilmgandhi 18:6a4db94011d3 577 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 578 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
sahilmgandhi 18:6a4db94011d3 579
sahilmgandhi 18:6a4db94011d3 580 /* Check if the automatic poll mode stop is activated */
sahilmgandhi 18:6a4db94011d3 581 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
sahilmgandhi 18:6a4db94011d3 582 {
sahilmgandhi 18:6a4db94011d3 583 /* Disable the QSPI Transfer Error and Status Match Interrupts */
sahilmgandhi 18:6a4db94011d3 584 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586 /* Change state of QSPI */
sahilmgandhi 18:6a4db94011d3 587 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 588 }
sahilmgandhi 18:6a4db94011d3 589
sahilmgandhi 18:6a4db94011d3 590 /* Status match callback */
sahilmgandhi 18:6a4db94011d3 591 HAL_QSPI_StatusMatchCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 592 }
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 /* QSPI Transfer Error interrupt occurred ----------------------------------*/
sahilmgandhi 18:6a4db94011d3 595 else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
sahilmgandhi 18:6a4db94011d3 596 {
sahilmgandhi 18:6a4db94011d3 597 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 598 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 /* Disable all the QSPI Interrupts */
sahilmgandhi 18:6a4db94011d3 601 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 /* Set error code */
sahilmgandhi 18:6a4db94011d3 604 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
sahilmgandhi 18:6a4db94011d3 605
sahilmgandhi 18:6a4db94011d3 606 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
sahilmgandhi 18:6a4db94011d3 607 {
sahilmgandhi 18:6a4db94011d3 608 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
sahilmgandhi 18:6a4db94011d3 609 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 /* Disable the DMA channel */
sahilmgandhi 18:6a4db94011d3 612 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
sahilmgandhi 18:6a4db94011d3 613 HAL_DMA_Abort_IT(hqspi->hdma);
sahilmgandhi 18:6a4db94011d3 614 }
sahilmgandhi 18:6a4db94011d3 615 else
sahilmgandhi 18:6a4db94011d3 616 {
sahilmgandhi 18:6a4db94011d3 617 /* Change state of QSPI */
sahilmgandhi 18:6a4db94011d3 618 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 /* Error callback */
sahilmgandhi 18:6a4db94011d3 621 HAL_QSPI_ErrorCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 622 }
sahilmgandhi 18:6a4db94011d3 623 }
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /* QSPI Timeout interrupt occurred -----------------------------------------*/
sahilmgandhi 18:6a4db94011d3 626 else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
sahilmgandhi 18:6a4db94011d3 627 {
sahilmgandhi 18:6a4db94011d3 628 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 629 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
sahilmgandhi 18:6a4db94011d3 630
sahilmgandhi 18:6a4db94011d3 631 /* Time out callback */
sahilmgandhi 18:6a4db94011d3 632 HAL_QSPI_TimeOutCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 633 }
sahilmgandhi 18:6a4db94011d3 634 }
sahilmgandhi 18:6a4db94011d3 635
sahilmgandhi 18:6a4db94011d3 636 /**
sahilmgandhi 18:6a4db94011d3 637 * @brief Sets the command configuration.
sahilmgandhi 18:6a4db94011d3 638 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 639 * @param cmd : structure that contains the command configuration information
sahilmgandhi 18:6a4db94011d3 640 * @param Timeout : Time out duration
sahilmgandhi 18:6a4db94011d3 641 * @note This function is used only in Indirect Read or Write Modes
sahilmgandhi 18:6a4db94011d3 642 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 643 */
sahilmgandhi 18:6a4db94011d3 644 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 645 {
sahilmgandhi 18:6a4db94011d3 646 HAL_StatusTypeDef status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 647 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 648
sahilmgandhi 18:6a4db94011d3 649 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 650 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
sahilmgandhi 18:6a4db94011d3 651 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
sahilmgandhi 18:6a4db94011d3 652 {
sahilmgandhi 18:6a4db94011d3 653 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
sahilmgandhi 18:6a4db94011d3 654 }
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
sahilmgandhi 18:6a4db94011d3 657 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 658 {
sahilmgandhi 18:6a4db94011d3 659 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
sahilmgandhi 18:6a4db94011d3 660 }
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
sahilmgandhi 18:6a4db94011d3 663 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
sahilmgandhi 18:6a4db94011d3 664 {
sahilmgandhi 18:6a4db94011d3 665 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
sahilmgandhi 18:6a4db94011d3 666 }
sahilmgandhi 18:6a4db94011d3 667
sahilmgandhi 18:6a4db94011d3 668 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
sahilmgandhi 18:6a4db94011d3 669 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
sahilmgandhi 18:6a4db94011d3 670
sahilmgandhi 18:6a4db94011d3 671 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
sahilmgandhi 18:6a4db94011d3 672 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
sahilmgandhi 18:6a4db94011d3 673 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
sahilmgandhi 18:6a4db94011d3 674
sahilmgandhi 18:6a4db94011d3 675 /* Process locked */
sahilmgandhi 18:6a4db94011d3 676 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 677
sahilmgandhi 18:6a4db94011d3 678 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 679 {
sahilmgandhi 18:6a4db94011d3 680 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 /* Update QSPI state */
sahilmgandhi 18:6a4db94011d3 683 hqspi->State = HAL_QSPI_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 /* Wait till BUSY flag reset */
sahilmgandhi 18:6a4db94011d3 686 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 689 {
sahilmgandhi 18:6a4db94011d3 690 /* Call the configuration function */
sahilmgandhi 18:6a4db94011d3 691 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
sahilmgandhi 18:6a4db94011d3 692
sahilmgandhi 18:6a4db94011d3 693 if (cmd->DataMode == QSPI_DATA_NONE)
sahilmgandhi 18:6a4db94011d3 694 {
sahilmgandhi 18:6a4db94011d3 695 /* When there is no data phase, the transfer start as soon as the configuration is done
sahilmgandhi 18:6a4db94011d3 696 so wait until TC flag is set to go back in idle state */
sahilmgandhi 18:6a4db94011d3 697 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
sahilmgandhi 18:6a4db94011d3 698
sahilmgandhi 18:6a4db94011d3 699 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 700 {
sahilmgandhi 18:6a4db94011d3 701 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 /* Update QSPI state */
sahilmgandhi 18:6a4db94011d3 704 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 705 }
sahilmgandhi 18:6a4db94011d3 706
sahilmgandhi 18:6a4db94011d3 707 }
sahilmgandhi 18:6a4db94011d3 708 else
sahilmgandhi 18:6a4db94011d3 709 {
sahilmgandhi 18:6a4db94011d3 710 /* Update QSPI state */
sahilmgandhi 18:6a4db94011d3 711 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 712 }
sahilmgandhi 18:6a4db94011d3 713 }
sahilmgandhi 18:6a4db94011d3 714 }
sahilmgandhi 18:6a4db94011d3 715 else
sahilmgandhi 18:6a4db94011d3 716 {
sahilmgandhi 18:6a4db94011d3 717 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 718 }
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 721 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 722
sahilmgandhi 18:6a4db94011d3 723 /* Return function status */
sahilmgandhi 18:6a4db94011d3 724 return status;
sahilmgandhi 18:6a4db94011d3 725 }
sahilmgandhi 18:6a4db94011d3 726
sahilmgandhi 18:6a4db94011d3 727 /**
sahilmgandhi 18:6a4db94011d3 728 * @brief Sets the command configuration in interrupt mode.
sahilmgandhi 18:6a4db94011d3 729 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 730 * @param cmd : structure that contains the command configuration information
sahilmgandhi 18:6a4db94011d3 731 * @note This function is used only in Indirect Read or Write Modes
sahilmgandhi 18:6a4db94011d3 732 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 733 */
sahilmgandhi 18:6a4db94011d3 734 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
sahilmgandhi 18:6a4db94011d3 735 {
sahilmgandhi 18:6a4db94011d3 736 __IO uint32_t count = 0U;
sahilmgandhi 18:6a4db94011d3 737 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 738
sahilmgandhi 18:6a4db94011d3 739 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 740 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
sahilmgandhi 18:6a4db94011d3 741 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
sahilmgandhi 18:6a4db94011d3 742 {
sahilmgandhi 18:6a4db94011d3 743 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
sahilmgandhi 18:6a4db94011d3 744 }
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
sahilmgandhi 18:6a4db94011d3 747 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 748 {
sahilmgandhi 18:6a4db94011d3 749 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
sahilmgandhi 18:6a4db94011d3 750 }
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
sahilmgandhi 18:6a4db94011d3 753 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
sahilmgandhi 18:6a4db94011d3 754 {
sahilmgandhi 18:6a4db94011d3 755 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
sahilmgandhi 18:6a4db94011d3 756 }
sahilmgandhi 18:6a4db94011d3 757
sahilmgandhi 18:6a4db94011d3 758 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
sahilmgandhi 18:6a4db94011d3 759 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
sahilmgandhi 18:6a4db94011d3 762 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
sahilmgandhi 18:6a4db94011d3 763 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 /* Process locked */
sahilmgandhi 18:6a4db94011d3 766 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 769 {
sahilmgandhi 18:6a4db94011d3 770 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 771
sahilmgandhi 18:6a4db94011d3 772 /* Update QSPI state */
sahilmgandhi 18:6a4db94011d3 773 hqspi->State = HAL_QSPI_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 774
sahilmgandhi 18:6a4db94011d3 775 /* Wait till BUSY flag reset */
sahilmgandhi 18:6a4db94011d3 776 count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
sahilmgandhi 18:6a4db94011d3 777 do
sahilmgandhi 18:6a4db94011d3 778 {
sahilmgandhi 18:6a4db94011d3 779 if (count-- == 0)
sahilmgandhi 18:6a4db94011d3 780 {
sahilmgandhi 18:6a4db94011d3 781 hqspi->State = HAL_QSPI_STATE_ERROR;
sahilmgandhi 18:6a4db94011d3 782 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 783 status = HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 784 }
sahilmgandhi 18:6a4db94011d3 785 }
sahilmgandhi 18:6a4db94011d3 786 while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 789 {
sahilmgandhi 18:6a4db94011d3 790 if (cmd->DataMode == QSPI_DATA_NONE)
sahilmgandhi 18:6a4db94011d3 791 {
sahilmgandhi 18:6a4db94011d3 792 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 793 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 794 }
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 /* Call the configuration function */
sahilmgandhi 18:6a4db94011d3 797 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 if (cmd->DataMode == QSPI_DATA_NONE)
sahilmgandhi 18:6a4db94011d3 800 {
sahilmgandhi 18:6a4db94011d3 801 /* When there is no data phase, the transfer start as soon as the configuration is done
sahilmgandhi 18:6a4db94011d3 802 so activate TC and TE interrupts */
sahilmgandhi 18:6a4db94011d3 803 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 804 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 805
sahilmgandhi 18:6a4db94011d3 806 /* Enable the QSPI Transfer Error Interrupt */
sahilmgandhi 18:6a4db94011d3 807 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
sahilmgandhi 18:6a4db94011d3 808 }
sahilmgandhi 18:6a4db94011d3 809 else
sahilmgandhi 18:6a4db94011d3 810 {
sahilmgandhi 18:6a4db94011d3 811 /* Update QSPI state */
sahilmgandhi 18:6a4db94011d3 812 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 815 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 816 }
sahilmgandhi 18:6a4db94011d3 817 }
sahilmgandhi 18:6a4db94011d3 818 else
sahilmgandhi 18:6a4db94011d3 819 {
sahilmgandhi 18:6a4db94011d3 820 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 821 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 822 }
sahilmgandhi 18:6a4db94011d3 823 }
sahilmgandhi 18:6a4db94011d3 824 else
sahilmgandhi 18:6a4db94011d3 825 {
sahilmgandhi 18:6a4db94011d3 826 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 827
sahilmgandhi 18:6a4db94011d3 828 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 829 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 830 }
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832 /* Return function status */
sahilmgandhi 18:6a4db94011d3 833 return status;
sahilmgandhi 18:6a4db94011d3 834 }
sahilmgandhi 18:6a4db94011d3 835
sahilmgandhi 18:6a4db94011d3 836 /**
sahilmgandhi 18:6a4db94011d3 837 * @brief Transmit an amount of data in blocking mode.
sahilmgandhi 18:6a4db94011d3 838 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 839 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 840 * @param Timeout : Time out duration
sahilmgandhi 18:6a4db94011d3 841 * @note This function is used only in Indirect Write Mode
sahilmgandhi 18:6a4db94011d3 842 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 843 */
sahilmgandhi 18:6a4db94011d3 844 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 845 {
sahilmgandhi 18:6a4db94011d3 846 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 847 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 848 __IO uint32_t *data_reg = &hqspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 849
sahilmgandhi 18:6a4db94011d3 850 /* Process locked */
sahilmgandhi 18:6a4db94011d3 851 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 852
sahilmgandhi 18:6a4db94011d3 853 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 854 {
sahilmgandhi 18:6a4db94011d3 855 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 856
sahilmgandhi 18:6a4db94011d3 857 if(pData != NULL )
sahilmgandhi 18:6a4db94011d3 858 {
sahilmgandhi 18:6a4db94011d3 859 /* Update state */
sahilmgandhi 18:6a4db94011d3 860 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
sahilmgandhi 18:6a4db94011d3 861
sahilmgandhi 18:6a4db94011d3 862 /* Configure counters and size of the handle */
sahilmgandhi 18:6a4db94011d3 863 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
sahilmgandhi 18:6a4db94011d3 864 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
sahilmgandhi 18:6a4db94011d3 865 hqspi->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 866
sahilmgandhi 18:6a4db94011d3 867 /* Configure QSPI: CCR register with functional as indirect write */
sahilmgandhi 18:6a4db94011d3 868 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 while(hqspi->TxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 871 {
sahilmgandhi 18:6a4db94011d3 872 /* Wait until FT flag is set to send data */
sahilmgandhi 18:6a4db94011d3 873 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
sahilmgandhi 18:6a4db94011d3 874
sahilmgandhi 18:6a4db94011d3 875 if (status != HAL_OK)
sahilmgandhi 18:6a4db94011d3 876 {
sahilmgandhi 18:6a4db94011d3 877 break;
sahilmgandhi 18:6a4db94011d3 878 }
sahilmgandhi 18:6a4db94011d3 879
sahilmgandhi 18:6a4db94011d3 880 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
sahilmgandhi 18:6a4db94011d3 881 hqspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 882 }
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 885 {
sahilmgandhi 18:6a4db94011d3 886 /* Wait until TC flag is set to go back in idle state */
sahilmgandhi 18:6a4db94011d3 887 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
sahilmgandhi 18:6a4db94011d3 888
sahilmgandhi 18:6a4db94011d3 889 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 890 {
sahilmgandhi 18:6a4db94011d3 891 /* Clear Transfer Complete bit */
sahilmgandhi 18:6a4db94011d3 892 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 /* Clear Busy bit */
sahilmgandhi 18:6a4db94011d3 895 status = HAL_QSPI_Abort(hqspi);
sahilmgandhi 18:6a4db94011d3 896 }
sahilmgandhi 18:6a4db94011d3 897 }
sahilmgandhi 18:6a4db94011d3 898
sahilmgandhi 18:6a4db94011d3 899 /* Update QSPI state */
sahilmgandhi 18:6a4db94011d3 900 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 901 }
sahilmgandhi 18:6a4db94011d3 902 else
sahilmgandhi 18:6a4db94011d3 903 {
sahilmgandhi 18:6a4db94011d3 904 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 905 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 906 }
sahilmgandhi 18:6a4db94011d3 907 }
sahilmgandhi 18:6a4db94011d3 908 else
sahilmgandhi 18:6a4db94011d3 909 {
sahilmgandhi 18:6a4db94011d3 910 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 911 }
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 914 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 return status;
sahilmgandhi 18:6a4db94011d3 917 }
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919
sahilmgandhi 18:6a4db94011d3 920 /**
sahilmgandhi 18:6a4db94011d3 921 * @brief Receive an amount of data in blocking mode
sahilmgandhi 18:6a4db94011d3 922 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 923 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 924 * @param Timeout : Time out duration
sahilmgandhi 18:6a4db94011d3 925 * @note This function is used only in Indirect Read Mode
sahilmgandhi 18:6a4db94011d3 926 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 927 */
sahilmgandhi 18:6a4db94011d3 928 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 929 {
sahilmgandhi 18:6a4db94011d3 930 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 931 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 932 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
sahilmgandhi 18:6a4db94011d3 933 __IO uint32_t *data_reg = &hqspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 934
sahilmgandhi 18:6a4db94011d3 935 /* Process locked */
sahilmgandhi 18:6a4db94011d3 936 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 937
sahilmgandhi 18:6a4db94011d3 938 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 939 {
sahilmgandhi 18:6a4db94011d3 940 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 941 if(pData != NULL )
sahilmgandhi 18:6a4db94011d3 942 {
sahilmgandhi 18:6a4db94011d3 943 /* Update state */
sahilmgandhi 18:6a4db94011d3 944 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
sahilmgandhi 18:6a4db94011d3 945
sahilmgandhi 18:6a4db94011d3 946 /* Configure counters and size of the handle */
sahilmgandhi 18:6a4db94011d3 947 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
sahilmgandhi 18:6a4db94011d3 948 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
sahilmgandhi 18:6a4db94011d3 949 hqspi->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 950
sahilmgandhi 18:6a4db94011d3 951 /* Configure QSPI: CCR register with functional as indirect read */
sahilmgandhi 18:6a4db94011d3 952 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
sahilmgandhi 18:6a4db94011d3 953
sahilmgandhi 18:6a4db94011d3 954 /* Start the transfer by re-writing the address in AR register */
sahilmgandhi 18:6a4db94011d3 955 WRITE_REG(hqspi->Instance->AR, addr_reg);
sahilmgandhi 18:6a4db94011d3 956
sahilmgandhi 18:6a4db94011d3 957 while(hqspi->RxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 /* Wait until FT or TC flag is set to read received data */
sahilmgandhi 18:6a4db94011d3 960 status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
sahilmgandhi 18:6a4db94011d3 961
sahilmgandhi 18:6a4db94011d3 962 if (status != HAL_OK)
sahilmgandhi 18:6a4db94011d3 963 {
sahilmgandhi 18:6a4db94011d3 964 break;
sahilmgandhi 18:6a4db94011d3 965 }
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
sahilmgandhi 18:6a4db94011d3 968 hqspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 969 }
sahilmgandhi 18:6a4db94011d3 970
sahilmgandhi 18:6a4db94011d3 971 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 972 {
sahilmgandhi 18:6a4db94011d3 973 /* Wait until TC flag is set to go back in idle state */
sahilmgandhi 18:6a4db94011d3 974 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 977 {
sahilmgandhi 18:6a4db94011d3 978 /* Clear Transfer Complete bit */
sahilmgandhi 18:6a4db94011d3 979 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 980
sahilmgandhi 18:6a4db94011d3 981 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
sahilmgandhi 18:6a4db94011d3 982 status = HAL_QSPI_Abort(hqspi);
sahilmgandhi 18:6a4db94011d3 983 }
sahilmgandhi 18:6a4db94011d3 984 }
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986 /* Update QSPI state */
sahilmgandhi 18:6a4db94011d3 987 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 988 }
sahilmgandhi 18:6a4db94011d3 989 else
sahilmgandhi 18:6a4db94011d3 990 {
sahilmgandhi 18:6a4db94011d3 991 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 992 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 993 }
sahilmgandhi 18:6a4db94011d3 994 }
sahilmgandhi 18:6a4db94011d3 995 else
sahilmgandhi 18:6a4db94011d3 996 {
sahilmgandhi 18:6a4db94011d3 997 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 998 }
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1001 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 return status;
sahilmgandhi 18:6a4db94011d3 1004 }
sahilmgandhi 18:6a4db94011d3 1005
sahilmgandhi 18:6a4db94011d3 1006 /**
sahilmgandhi 18:6a4db94011d3 1007 * @brief Send an amount of data in interrupt mode
sahilmgandhi 18:6a4db94011d3 1008 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1009 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 1010 * @note This function is used only in Indirect Write Mode
sahilmgandhi 18:6a4db94011d3 1011 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1012 */
sahilmgandhi 18:6a4db94011d3 1013 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
sahilmgandhi 18:6a4db94011d3 1014 {
sahilmgandhi 18:6a4db94011d3 1015 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1016
sahilmgandhi 18:6a4db94011d3 1017 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1018 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1019
sahilmgandhi 18:6a4db94011d3 1020 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1021 {
sahilmgandhi 18:6a4db94011d3 1022 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1023 if(pData != NULL )
sahilmgandhi 18:6a4db94011d3 1024 {
sahilmgandhi 18:6a4db94011d3 1025 /* Update state */
sahilmgandhi 18:6a4db94011d3 1026 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
sahilmgandhi 18:6a4db94011d3 1027
sahilmgandhi 18:6a4db94011d3 1028 /* Configure counters and size of the handle */
sahilmgandhi 18:6a4db94011d3 1029 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
sahilmgandhi 18:6a4db94011d3 1030 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
sahilmgandhi 18:6a4db94011d3 1031 hqspi->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 1032
sahilmgandhi 18:6a4db94011d3 1033 /* Configure QSPI: CCR register with functional as indirect write */
sahilmgandhi 18:6a4db94011d3 1034 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
sahilmgandhi 18:6a4db94011d3 1035
sahilmgandhi 18:6a4db94011d3 1036 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 1037 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1040 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1041
sahilmgandhi 18:6a4db94011d3 1042 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
sahilmgandhi 18:6a4db94011d3 1043 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 }
sahilmgandhi 18:6a4db94011d3 1046 else
sahilmgandhi 18:6a4db94011d3 1047 {
sahilmgandhi 18:6a4db94011d3 1048 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 1049 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1050
sahilmgandhi 18:6a4db94011d3 1051 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1052 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1053 }
sahilmgandhi 18:6a4db94011d3 1054 }
sahilmgandhi 18:6a4db94011d3 1055 else
sahilmgandhi 18:6a4db94011d3 1056 {
sahilmgandhi 18:6a4db94011d3 1057 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1058
sahilmgandhi 18:6a4db94011d3 1059 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1060 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1061 }
sahilmgandhi 18:6a4db94011d3 1062
sahilmgandhi 18:6a4db94011d3 1063 return status;
sahilmgandhi 18:6a4db94011d3 1064 }
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 /**
sahilmgandhi 18:6a4db94011d3 1067 * @brief Receive an amount of data in no-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 1068 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1069 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 1070 * @note This function is used only in Indirect Read Mode
sahilmgandhi 18:6a4db94011d3 1071 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1072 */
sahilmgandhi 18:6a4db94011d3 1073 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
sahilmgandhi 18:6a4db94011d3 1074 {
sahilmgandhi 18:6a4db94011d3 1075 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1076 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1079 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1080
sahilmgandhi 18:6a4db94011d3 1081 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1082 {
sahilmgandhi 18:6a4db94011d3 1083 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1084
sahilmgandhi 18:6a4db94011d3 1085 if(pData != NULL )
sahilmgandhi 18:6a4db94011d3 1086 {
sahilmgandhi 18:6a4db94011d3 1087 /* Update state */
sahilmgandhi 18:6a4db94011d3 1088 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
sahilmgandhi 18:6a4db94011d3 1089
sahilmgandhi 18:6a4db94011d3 1090 /* Configure counters and size of the handle */
sahilmgandhi 18:6a4db94011d3 1091 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
sahilmgandhi 18:6a4db94011d3 1092 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
sahilmgandhi 18:6a4db94011d3 1093 hqspi->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 /* Configure QSPI: CCR register with functional as indirect read */
sahilmgandhi 18:6a4db94011d3 1096 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 /* Start the transfer by re-writing the address in AR register */
sahilmgandhi 18:6a4db94011d3 1099 WRITE_REG(hqspi->Instance->AR, addr_reg);
sahilmgandhi 18:6a4db94011d3 1100
sahilmgandhi 18:6a4db94011d3 1101 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 1102 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 1103
sahilmgandhi 18:6a4db94011d3 1104 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1105 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1106
sahilmgandhi 18:6a4db94011d3 1107 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
sahilmgandhi 18:6a4db94011d3 1108 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
sahilmgandhi 18:6a4db94011d3 1109 }
sahilmgandhi 18:6a4db94011d3 1110 else
sahilmgandhi 18:6a4db94011d3 1111 {
sahilmgandhi 18:6a4db94011d3 1112 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 1113 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1114
sahilmgandhi 18:6a4db94011d3 1115 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1116 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1117 }
sahilmgandhi 18:6a4db94011d3 1118 }
sahilmgandhi 18:6a4db94011d3 1119 else
sahilmgandhi 18:6a4db94011d3 1120 {
sahilmgandhi 18:6a4db94011d3 1121 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1122
sahilmgandhi 18:6a4db94011d3 1123 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1124 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1125 }
sahilmgandhi 18:6a4db94011d3 1126
sahilmgandhi 18:6a4db94011d3 1127 return status;
sahilmgandhi 18:6a4db94011d3 1128 }
sahilmgandhi 18:6a4db94011d3 1129
sahilmgandhi 18:6a4db94011d3 1130 /**
sahilmgandhi 18:6a4db94011d3 1131 * @brief Sends an amount of data in non blocking mode with DMA.
sahilmgandhi 18:6a4db94011d3 1132 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1133 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 1134 * @note This function is used only in Indirect Write Mode
sahilmgandhi 18:6a4db94011d3 1135 * @note If DMA peripheral access is configured as halfword, the number
sahilmgandhi 18:6a4db94011d3 1136 * of data and the fifo threshold should be aligned on halfword
sahilmgandhi 18:6a4db94011d3 1137 * @note If DMA peripheral access is configured as word, the number
sahilmgandhi 18:6a4db94011d3 1138 * of data and the fifo threshold should be aligned on word
sahilmgandhi 18:6a4db94011d3 1139 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1140 */
sahilmgandhi 18:6a4db94011d3 1141 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
sahilmgandhi 18:6a4db94011d3 1142 {
sahilmgandhi 18:6a4db94011d3 1143 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1144 uint32_t *tmp;
sahilmgandhi 18:6a4db94011d3 1145 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
sahilmgandhi 18:6a4db94011d3 1146
sahilmgandhi 18:6a4db94011d3 1147 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1148 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1149
sahilmgandhi 18:6a4db94011d3 1150 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1151 {
sahilmgandhi 18:6a4db94011d3 1152 /* Clear the error code */
sahilmgandhi 18:6a4db94011d3 1153 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1154
sahilmgandhi 18:6a4db94011d3 1155 if(pData != NULL )
sahilmgandhi 18:6a4db94011d3 1156 {
sahilmgandhi 18:6a4db94011d3 1157 /* Configure counters of the handle */
sahilmgandhi 18:6a4db94011d3 1158 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
sahilmgandhi 18:6a4db94011d3 1159 {
sahilmgandhi 18:6a4db94011d3 1160 hqspi->TxXferCount = data_size;
sahilmgandhi 18:6a4db94011d3 1161 }
sahilmgandhi 18:6a4db94011d3 1162 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
sahilmgandhi 18:6a4db94011d3 1163 {
sahilmgandhi 18:6a4db94011d3 1164 if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
sahilmgandhi 18:6a4db94011d3 1165 {
sahilmgandhi 18:6a4db94011d3 1166 /* The number of data or the fifo threshold is not aligned on halfword
sahilmgandhi 18:6a4db94011d3 1167 => no transfer possible with DMA peripheral access configured as halfword */
sahilmgandhi 18:6a4db94011d3 1168 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 1169 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1170
sahilmgandhi 18:6a4db94011d3 1171 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1172 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1173 }
sahilmgandhi 18:6a4db94011d3 1174 else
sahilmgandhi 18:6a4db94011d3 1175 {
sahilmgandhi 18:6a4db94011d3 1176 hqspi->TxXferCount = (data_size >> 1);
sahilmgandhi 18:6a4db94011d3 1177 }
sahilmgandhi 18:6a4db94011d3 1178 }
sahilmgandhi 18:6a4db94011d3 1179 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
sahilmgandhi 18:6a4db94011d3 1180 {
sahilmgandhi 18:6a4db94011d3 1181 if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
sahilmgandhi 18:6a4db94011d3 1182 {
sahilmgandhi 18:6a4db94011d3 1183 /* The number of data or the fifo threshold is not aligned on word
sahilmgandhi 18:6a4db94011d3 1184 => no transfer possible with DMA peripheral access configured as word */
sahilmgandhi 18:6a4db94011d3 1185 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 1186 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1187
sahilmgandhi 18:6a4db94011d3 1188 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1189 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1190 }
sahilmgandhi 18:6a4db94011d3 1191 else
sahilmgandhi 18:6a4db94011d3 1192 {
sahilmgandhi 18:6a4db94011d3 1193 hqspi->TxXferCount = (data_size >> 2);
sahilmgandhi 18:6a4db94011d3 1194 }
sahilmgandhi 18:6a4db94011d3 1195 }
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 1198 {
sahilmgandhi 18:6a4db94011d3 1199
sahilmgandhi 18:6a4db94011d3 1200 /* Update state */
sahilmgandhi 18:6a4db94011d3 1201 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
sahilmgandhi 18:6a4db94011d3 1202
sahilmgandhi 18:6a4db94011d3 1203 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 1204 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
sahilmgandhi 18:6a4db94011d3 1205
sahilmgandhi 18:6a4db94011d3 1206 /* Configure size and pointer of the handle */
sahilmgandhi 18:6a4db94011d3 1207 hqspi->TxXferSize = hqspi->TxXferCount;
sahilmgandhi 18:6a4db94011d3 1208 hqspi->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 1209
sahilmgandhi 18:6a4db94011d3 1210 /* Configure QSPI: CCR register with functional mode as indirect write */
sahilmgandhi 18:6a4db94011d3 1211 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
sahilmgandhi 18:6a4db94011d3 1212
sahilmgandhi 18:6a4db94011d3 1213 /* Set the QSPI DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1214 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
sahilmgandhi 18:6a4db94011d3 1215
sahilmgandhi 18:6a4db94011d3 1216 /* Set the QSPI DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1217 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
sahilmgandhi 18:6a4db94011d3 1218
sahilmgandhi 18:6a4db94011d3 1219 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 1220 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
sahilmgandhi 18:6a4db94011d3 1221
sahilmgandhi 18:6a4db94011d3 1222 /* Clear the DMA abort callback */
sahilmgandhi 18:6a4db94011d3 1223 hqspi->hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1224
sahilmgandhi 18:6a4db94011d3 1225 /* Configure the direction of the DMA */
sahilmgandhi 18:6a4db94011d3 1226 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
sahilmgandhi 18:6a4db94011d3 1227 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
sahilmgandhi 18:6a4db94011d3 1228
sahilmgandhi 18:6a4db94011d3 1229 /* Enable the QSPI transmit DMA Channel */
sahilmgandhi 18:6a4db94011d3 1230 tmp = (uint32_t*)&pData;
sahilmgandhi 18:6a4db94011d3 1231 HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
sahilmgandhi 18:6a4db94011d3 1232
sahilmgandhi 18:6a4db94011d3 1233 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1234 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1235
sahilmgandhi 18:6a4db94011d3 1236 /* Enable the QSPI transfer error Interrupt */
sahilmgandhi 18:6a4db94011d3 1237 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
sahilmgandhi 18:6a4db94011d3 1238
sahilmgandhi 18:6a4db94011d3 1239 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
sahilmgandhi 18:6a4db94011d3 1240 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
sahilmgandhi 18:6a4db94011d3 1241 }
sahilmgandhi 18:6a4db94011d3 1242 }
sahilmgandhi 18:6a4db94011d3 1243 else
sahilmgandhi 18:6a4db94011d3 1244 {
sahilmgandhi 18:6a4db94011d3 1245 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 1246
sahilmgandhi 18:6a4db94011d3 1247 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1248
sahilmgandhi 18:6a4db94011d3 1249 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1250 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1251 }
sahilmgandhi 18:6a4db94011d3 1252 }
sahilmgandhi 18:6a4db94011d3 1253 else
sahilmgandhi 18:6a4db94011d3 1254 {
sahilmgandhi 18:6a4db94011d3 1255 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1256
sahilmgandhi 18:6a4db94011d3 1257 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1258 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1259 }
sahilmgandhi 18:6a4db94011d3 1260
sahilmgandhi 18:6a4db94011d3 1261 return status;
sahilmgandhi 18:6a4db94011d3 1262 }
sahilmgandhi 18:6a4db94011d3 1263
sahilmgandhi 18:6a4db94011d3 1264 /**
sahilmgandhi 18:6a4db94011d3 1265 * @brief Receives an amount of data in non blocking mode with DMA.
sahilmgandhi 18:6a4db94011d3 1266 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1267 * @param pData: pointer to data buffer.
sahilmgandhi 18:6a4db94011d3 1268 * @note This function is used only in Indirect Read Mode
sahilmgandhi 18:6a4db94011d3 1269 * @note If DMA peripheral access is configured as halfword, the number
sahilmgandhi 18:6a4db94011d3 1270 * of data and the fifo threshold should be aligned on halfword
sahilmgandhi 18:6a4db94011d3 1271 * @note If DMA peripheral access is configured as word, the number
sahilmgandhi 18:6a4db94011d3 1272 * of data and the fifo threshold should be aligned on word
sahilmgandhi 18:6a4db94011d3 1273 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1274 */
sahilmgandhi 18:6a4db94011d3 1275 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
sahilmgandhi 18:6a4db94011d3 1276 {
sahilmgandhi 18:6a4db94011d3 1277 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1278 uint32_t *tmp;
sahilmgandhi 18:6a4db94011d3 1279 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
sahilmgandhi 18:6a4db94011d3 1280 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
sahilmgandhi 18:6a4db94011d3 1281
sahilmgandhi 18:6a4db94011d3 1282 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1283 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1284
sahilmgandhi 18:6a4db94011d3 1285 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1286 {
sahilmgandhi 18:6a4db94011d3 1287 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1288
sahilmgandhi 18:6a4db94011d3 1289 if(pData != NULL )
sahilmgandhi 18:6a4db94011d3 1290 {
sahilmgandhi 18:6a4db94011d3 1291 /* Configure counters of the handle */
sahilmgandhi 18:6a4db94011d3 1292 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
sahilmgandhi 18:6a4db94011d3 1293 {
sahilmgandhi 18:6a4db94011d3 1294 hqspi->RxXferCount = data_size;
sahilmgandhi 18:6a4db94011d3 1295 }
sahilmgandhi 18:6a4db94011d3 1296 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
sahilmgandhi 18:6a4db94011d3 1297 {
sahilmgandhi 18:6a4db94011d3 1298 if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
sahilmgandhi 18:6a4db94011d3 1299 {
sahilmgandhi 18:6a4db94011d3 1300 /* The number of data or the fifo threshold is not aligned on halfword
sahilmgandhi 18:6a4db94011d3 1301 => no transfer possible with DMA peripheral access configured as halfword */
sahilmgandhi 18:6a4db94011d3 1302 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 1303 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1304
sahilmgandhi 18:6a4db94011d3 1305 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1306 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1307 }
sahilmgandhi 18:6a4db94011d3 1308 else
sahilmgandhi 18:6a4db94011d3 1309 {
sahilmgandhi 18:6a4db94011d3 1310 hqspi->RxXferCount = (data_size >> 1);
sahilmgandhi 18:6a4db94011d3 1311 }
sahilmgandhi 18:6a4db94011d3 1312 }
sahilmgandhi 18:6a4db94011d3 1313 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
sahilmgandhi 18:6a4db94011d3 1314 {
sahilmgandhi 18:6a4db94011d3 1315 if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
sahilmgandhi 18:6a4db94011d3 1316 {
sahilmgandhi 18:6a4db94011d3 1317 /* The number of data or the fifo threshold is not aligned on word
sahilmgandhi 18:6a4db94011d3 1318 => no transfer possible with DMA peripheral access configured as word */
sahilmgandhi 18:6a4db94011d3 1319 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 1320 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1321
sahilmgandhi 18:6a4db94011d3 1322 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1323 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1324 }
sahilmgandhi 18:6a4db94011d3 1325 else
sahilmgandhi 18:6a4db94011d3 1326 {
sahilmgandhi 18:6a4db94011d3 1327 hqspi->RxXferCount = (data_size >> 2);
sahilmgandhi 18:6a4db94011d3 1328 }
sahilmgandhi 18:6a4db94011d3 1329 }
sahilmgandhi 18:6a4db94011d3 1330
sahilmgandhi 18:6a4db94011d3 1331 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 1332 {
sahilmgandhi 18:6a4db94011d3 1333
sahilmgandhi 18:6a4db94011d3 1334 /* Update state */
sahilmgandhi 18:6a4db94011d3 1335 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
sahilmgandhi 18:6a4db94011d3 1336
sahilmgandhi 18:6a4db94011d3 1337 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 1338 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
sahilmgandhi 18:6a4db94011d3 1339
sahilmgandhi 18:6a4db94011d3 1340 /* Configure size and pointer of the handle */
sahilmgandhi 18:6a4db94011d3 1341 hqspi->RxXferSize = hqspi->RxXferCount;
sahilmgandhi 18:6a4db94011d3 1342 hqspi->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 1343
sahilmgandhi 18:6a4db94011d3 1344 /* Set the QSPI DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1345 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
sahilmgandhi 18:6a4db94011d3 1346
sahilmgandhi 18:6a4db94011d3 1347 /* Set the QSPI DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1348 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
sahilmgandhi 18:6a4db94011d3 1349
sahilmgandhi 18:6a4db94011d3 1350 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 1351 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
sahilmgandhi 18:6a4db94011d3 1352
sahilmgandhi 18:6a4db94011d3 1353 /* Clear the DMA abort callback */
sahilmgandhi 18:6a4db94011d3 1354 hqspi->hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1355
sahilmgandhi 18:6a4db94011d3 1356 /* Configure the direction of the DMA */
sahilmgandhi 18:6a4db94011d3 1357 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
sahilmgandhi 18:6a4db94011d3 1358 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
sahilmgandhi 18:6a4db94011d3 1359
sahilmgandhi 18:6a4db94011d3 1360 /* Enable the DMA Channel */
sahilmgandhi 18:6a4db94011d3 1361 tmp = (uint32_t*)&pData;
sahilmgandhi 18:6a4db94011d3 1362 HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
sahilmgandhi 18:6a4db94011d3 1363
sahilmgandhi 18:6a4db94011d3 1364 /* Configure QSPI: CCR register with functional as indirect read */
sahilmgandhi 18:6a4db94011d3 1365 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
sahilmgandhi 18:6a4db94011d3 1366
sahilmgandhi 18:6a4db94011d3 1367 /* Start the transfer by re-writing the address in AR register */
sahilmgandhi 18:6a4db94011d3 1368 WRITE_REG(hqspi->Instance->AR, addr_reg);
sahilmgandhi 18:6a4db94011d3 1369
sahilmgandhi 18:6a4db94011d3 1370 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1371 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1372
sahilmgandhi 18:6a4db94011d3 1373 /* Enable the QSPI transfer error Interrupt */
sahilmgandhi 18:6a4db94011d3 1374 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
sahilmgandhi 18:6a4db94011d3 1375
sahilmgandhi 18:6a4db94011d3 1376 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
sahilmgandhi 18:6a4db94011d3 1377 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
sahilmgandhi 18:6a4db94011d3 1378 }
sahilmgandhi 18:6a4db94011d3 1379 }
sahilmgandhi 18:6a4db94011d3 1380 else
sahilmgandhi 18:6a4db94011d3 1381 {
sahilmgandhi 18:6a4db94011d3 1382 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
sahilmgandhi 18:6a4db94011d3 1383 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1384
sahilmgandhi 18:6a4db94011d3 1385 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1386 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1387 }
sahilmgandhi 18:6a4db94011d3 1388 }
sahilmgandhi 18:6a4db94011d3 1389 else
sahilmgandhi 18:6a4db94011d3 1390 {
sahilmgandhi 18:6a4db94011d3 1391 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1392
sahilmgandhi 18:6a4db94011d3 1393 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1394 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1395 }
sahilmgandhi 18:6a4db94011d3 1396
sahilmgandhi 18:6a4db94011d3 1397 return status;
sahilmgandhi 18:6a4db94011d3 1398 }
sahilmgandhi 18:6a4db94011d3 1399
sahilmgandhi 18:6a4db94011d3 1400 /**
sahilmgandhi 18:6a4db94011d3 1401 * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
sahilmgandhi 18:6a4db94011d3 1402 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1403 * @param cmd: structure that contains the command configuration information.
sahilmgandhi 18:6a4db94011d3 1404 * @param cfg: structure that contains the polling configuration information.
sahilmgandhi 18:6a4db94011d3 1405 * @param Timeout : Time out duration
sahilmgandhi 18:6a4db94011d3 1406 * @note This function is used only in Automatic Polling Mode
sahilmgandhi 18:6a4db94011d3 1407 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1408 */
sahilmgandhi 18:6a4db94011d3 1409 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 1410 {
sahilmgandhi 18:6a4db94011d3 1411 HAL_StatusTypeDef status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1412 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 1413
sahilmgandhi 18:6a4db94011d3 1414 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1415 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
sahilmgandhi 18:6a4db94011d3 1416 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
sahilmgandhi 18:6a4db94011d3 1417 {
sahilmgandhi 18:6a4db94011d3 1418 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
sahilmgandhi 18:6a4db94011d3 1419 }
sahilmgandhi 18:6a4db94011d3 1420
sahilmgandhi 18:6a4db94011d3 1421 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
sahilmgandhi 18:6a4db94011d3 1422 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 1423 {
sahilmgandhi 18:6a4db94011d3 1424 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
sahilmgandhi 18:6a4db94011d3 1425 }
sahilmgandhi 18:6a4db94011d3 1426
sahilmgandhi 18:6a4db94011d3 1427 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
sahilmgandhi 18:6a4db94011d3 1428 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
sahilmgandhi 18:6a4db94011d3 1429 {
sahilmgandhi 18:6a4db94011d3 1430 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
sahilmgandhi 18:6a4db94011d3 1431 }
sahilmgandhi 18:6a4db94011d3 1432
sahilmgandhi 18:6a4db94011d3 1433 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
sahilmgandhi 18:6a4db94011d3 1434 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
sahilmgandhi 18:6a4db94011d3 1435
sahilmgandhi 18:6a4db94011d3 1436 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
sahilmgandhi 18:6a4db94011d3 1437 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
sahilmgandhi 18:6a4db94011d3 1438 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
sahilmgandhi 18:6a4db94011d3 1439
sahilmgandhi 18:6a4db94011d3 1440 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
sahilmgandhi 18:6a4db94011d3 1441 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
sahilmgandhi 18:6a4db94011d3 1442 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
sahilmgandhi 18:6a4db94011d3 1443
sahilmgandhi 18:6a4db94011d3 1444 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1445 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1446
sahilmgandhi 18:6a4db94011d3 1447 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1448 {
sahilmgandhi 18:6a4db94011d3 1449
sahilmgandhi 18:6a4db94011d3 1450 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1451
sahilmgandhi 18:6a4db94011d3 1452 /* Update state */
sahilmgandhi 18:6a4db94011d3 1453 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
sahilmgandhi 18:6a4db94011d3 1454
sahilmgandhi 18:6a4db94011d3 1455 /* Wait till BUSY flag reset */
sahilmgandhi 18:6a4db94011d3 1456 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
sahilmgandhi 18:6a4db94011d3 1457
sahilmgandhi 18:6a4db94011d3 1458 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 1459 {
sahilmgandhi 18:6a4db94011d3 1460 /* Configure QSPI: PSMAR register with the status match value */
sahilmgandhi 18:6a4db94011d3 1461 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
sahilmgandhi 18:6a4db94011d3 1462
sahilmgandhi 18:6a4db94011d3 1463 /* Configure QSPI: PSMKR register with the status mask value */
sahilmgandhi 18:6a4db94011d3 1464 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
sahilmgandhi 18:6a4db94011d3 1465
sahilmgandhi 18:6a4db94011d3 1466 /* Configure QSPI: PIR register with the interval value */
sahilmgandhi 18:6a4db94011d3 1467 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
sahilmgandhi 18:6a4db94011d3 1468
sahilmgandhi 18:6a4db94011d3 1469 /* Configure QSPI: CR register with Match mode and Automatic stop enabled
sahilmgandhi 18:6a4db94011d3 1470 (otherwise there will be an infinite loop in blocking mode) */
sahilmgandhi 18:6a4db94011d3 1471 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
sahilmgandhi 18:6a4db94011d3 1472 (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
sahilmgandhi 18:6a4db94011d3 1473
sahilmgandhi 18:6a4db94011d3 1474 /* Call the configuration function */
sahilmgandhi 18:6a4db94011d3 1475 cmd->NbData = cfg->StatusBytesSize;
sahilmgandhi 18:6a4db94011d3 1476 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
sahilmgandhi 18:6a4db94011d3 1477
sahilmgandhi 18:6a4db94011d3 1478 /* Wait until SM flag is set to go back in idle state */
sahilmgandhi 18:6a4db94011d3 1479 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
sahilmgandhi 18:6a4db94011d3 1480
sahilmgandhi 18:6a4db94011d3 1481 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 1482 {
sahilmgandhi 18:6a4db94011d3 1483 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
sahilmgandhi 18:6a4db94011d3 1484
sahilmgandhi 18:6a4db94011d3 1485 /* Update state */
sahilmgandhi 18:6a4db94011d3 1486 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1487 }
sahilmgandhi 18:6a4db94011d3 1488 }
sahilmgandhi 18:6a4db94011d3 1489 }
sahilmgandhi 18:6a4db94011d3 1490 else
sahilmgandhi 18:6a4db94011d3 1491 {
sahilmgandhi 18:6a4db94011d3 1492 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1493 }
sahilmgandhi 18:6a4db94011d3 1494 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1495 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1496
sahilmgandhi 18:6a4db94011d3 1497 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1498 return status;
sahilmgandhi 18:6a4db94011d3 1499 }
sahilmgandhi 18:6a4db94011d3 1500
sahilmgandhi 18:6a4db94011d3 1501 /**
sahilmgandhi 18:6a4db94011d3 1502 * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
sahilmgandhi 18:6a4db94011d3 1503 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1504 * @param cmd: structure that contains the command configuration information.
sahilmgandhi 18:6a4db94011d3 1505 * @param cfg: structure that contains the polling configuration information.
sahilmgandhi 18:6a4db94011d3 1506 * @note This function is used only in Automatic Polling Mode
sahilmgandhi 18:6a4db94011d3 1507 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1508 */
sahilmgandhi 18:6a4db94011d3 1509 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
sahilmgandhi 18:6a4db94011d3 1510 {
sahilmgandhi 18:6a4db94011d3 1511 __IO uint32_t count = 0U;
sahilmgandhi 18:6a4db94011d3 1512 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1513
sahilmgandhi 18:6a4db94011d3 1514 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1515 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
sahilmgandhi 18:6a4db94011d3 1516 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
sahilmgandhi 18:6a4db94011d3 1517 {
sahilmgandhi 18:6a4db94011d3 1518 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
sahilmgandhi 18:6a4db94011d3 1519 }
sahilmgandhi 18:6a4db94011d3 1520
sahilmgandhi 18:6a4db94011d3 1521 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
sahilmgandhi 18:6a4db94011d3 1522 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 1523 {
sahilmgandhi 18:6a4db94011d3 1524 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
sahilmgandhi 18:6a4db94011d3 1525 }
sahilmgandhi 18:6a4db94011d3 1526
sahilmgandhi 18:6a4db94011d3 1527 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
sahilmgandhi 18:6a4db94011d3 1528 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
sahilmgandhi 18:6a4db94011d3 1529 {
sahilmgandhi 18:6a4db94011d3 1530 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
sahilmgandhi 18:6a4db94011d3 1531 }
sahilmgandhi 18:6a4db94011d3 1532
sahilmgandhi 18:6a4db94011d3 1533 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
sahilmgandhi 18:6a4db94011d3 1534 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
sahilmgandhi 18:6a4db94011d3 1535
sahilmgandhi 18:6a4db94011d3 1536 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
sahilmgandhi 18:6a4db94011d3 1537 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
sahilmgandhi 18:6a4db94011d3 1538 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
sahilmgandhi 18:6a4db94011d3 1539
sahilmgandhi 18:6a4db94011d3 1540 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
sahilmgandhi 18:6a4db94011d3 1541 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
sahilmgandhi 18:6a4db94011d3 1542 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
sahilmgandhi 18:6a4db94011d3 1543 assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
sahilmgandhi 18:6a4db94011d3 1544
sahilmgandhi 18:6a4db94011d3 1545 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1546 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1547
sahilmgandhi 18:6a4db94011d3 1548 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1549 {
sahilmgandhi 18:6a4db94011d3 1550 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1551
sahilmgandhi 18:6a4db94011d3 1552 /* Update state */
sahilmgandhi 18:6a4db94011d3 1553 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
sahilmgandhi 18:6a4db94011d3 1554
sahilmgandhi 18:6a4db94011d3 1555 /* Wait till BUSY flag reset */
sahilmgandhi 18:6a4db94011d3 1556 count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
sahilmgandhi 18:6a4db94011d3 1557 do
sahilmgandhi 18:6a4db94011d3 1558 {
sahilmgandhi 18:6a4db94011d3 1559 if (count-- == 0)
sahilmgandhi 18:6a4db94011d3 1560 {
sahilmgandhi 18:6a4db94011d3 1561 hqspi->State = HAL_QSPI_STATE_ERROR;
sahilmgandhi 18:6a4db94011d3 1562 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1563 status = HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1564 }
sahilmgandhi 18:6a4db94011d3 1565 }
sahilmgandhi 18:6a4db94011d3 1566 while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
sahilmgandhi 18:6a4db94011d3 1567
sahilmgandhi 18:6a4db94011d3 1568 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 1569 {
sahilmgandhi 18:6a4db94011d3 1570 /* Configure QSPI: PSMAR register with the status match value */
sahilmgandhi 18:6a4db94011d3 1571 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
sahilmgandhi 18:6a4db94011d3 1572
sahilmgandhi 18:6a4db94011d3 1573 /* Configure QSPI: PSMKR register with the status mask value */
sahilmgandhi 18:6a4db94011d3 1574 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
sahilmgandhi 18:6a4db94011d3 1575
sahilmgandhi 18:6a4db94011d3 1576 /* Configure QSPI: PIR register with the interval value */
sahilmgandhi 18:6a4db94011d3 1577 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
sahilmgandhi 18:6a4db94011d3 1578
sahilmgandhi 18:6a4db94011d3 1579 /* Configure QSPI: CR register with Match mode and Automatic stop mode */
sahilmgandhi 18:6a4db94011d3 1580 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
sahilmgandhi 18:6a4db94011d3 1581 (cfg->MatchMode | cfg->AutomaticStop));
sahilmgandhi 18:6a4db94011d3 1582
sahilmgandhi 18:6a4db94011d3 1583 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 1584 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
sahilmgandhi 18:6a4db94011d3 1585
sahilmgandhi 18:6a4db94011d3 1586 /* Call the configuration function */
sahilmgandhi 18:6a4db94011d3 1587 cmd->NbData = cfg->StatusBytesSize;
sahilmgandhi 18:6a4db94011d3 1588 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
sahilmgandhi 18:6a4db94011d3 1589
sahilmgandhi 18:6a4db94011d3 1590 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1591 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1592
sahilmgandhi 18:6a4db94011d3 1593 /* Enable the QSPI Transfer Error and status match Interrupt */
sahilmgandhi 18:6a4db94011d3 1594 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
sahilmgandhi 18:6a4db94011d3 1595
sahilmgandhi 18:6a4db94011d3 1596 }
sahilmgandhi 18:6a4db94011d3 1597 else
sahilmgandhi 18:6a4db94011d3 1598 {
sahilmgandhi 18:6a4db94011d3 1599 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1600 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1601 }
sahilmgandhi 18:6a4db94011d3 1602 }
sahilmgandhi 18:6a4db94011d3 1603 else
sahilmgandhi 18:6a4db94011d3 1604 {
sahilmgandhi 18:6a4db94011d3 1605 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1606
sahilmgandhi 18:6a4db94011d3 1607 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1608 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1609 }
sahilmgandhi 18:6a4db94011d3 1610
sahilmgandhi 18:6a4db94011d3 1611 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1612 return status;
sahilmgandhi 18:6a4db94011d3 1613 }
sahilmgandhi 18:6a4db94011d3 1614
sahilmgandhi 18:6a4db94011d3 1615 /**
sahilmgandhi 18:6a4db94011d3 1616 * @brief Configure the Memory Mapped mode.
sahilmgandhi 18:6a4db94011d3 1617 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1618 * @param cmd: structure that contains the command configuration information.
sahilmgandhi 18:6a4db94011d3 1619 * @param cfg: structure that contains the memory mapped configuration information.
sahilmgandhi 18:6a4db94011d3 1620 * @note This function is used only in Memory mapped Mode
sahilmgandhi 18:6a4db94011d3 1621 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1622 */
sahilmgandhi 18:6a4db94011d3 1623 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
sahilmgandhi 18:6a4db94011d3 1624 {
sahilmgandhi 18:6a4db94011d3 1625 HAL_StatusTypeDef status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1626 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 1627
sahilmgandhi 18:6a4db94011d3 1628 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1629 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
sahilmgandhi 18:6a4db94011d3 1630 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
sahilmgandhi 18:6a4db94011d3 1631 {
sahilmgandhi 18:6a4db94011d3 1632 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
sahilmgandhi 18:6a4db94011d3 1633 }
sahilmgandhi 18:6a4db94011d3 1634
sahilmgandhi 18:6a4db94011d3 1635 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
sahilmgandhi 18:6a4db94011d3 1636 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 1637 {
sahilmgandhi 18:6a4db94011d3 1638 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
sahilmgandhi 18:6a4db94011d3 1639 }
sahilmgandhi 18:6a4db94011d3 1640
sahilmgandhi 18:6a4db94011d3 1641 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
sahilmgandhi 18:6a4db94011d3 1642 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
sahilmgandhi 18:6a4db94011d3 1643 {
sahilmgandhi 18:6a4db94011d3 1644 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
sahilmgandhi 18:6a4db94011d3 1645 }
sahilmgandhi 18:6a4db94011d3 1646
sahilmgandhi 18:6a4db94011d3 1647 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
sahilmgandhi 18:6a4db94011d3 1648 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
sahilmgandhi 18:6a4db94011d3 1649
sahilmgandhi 18:6a4db94011d3 1650 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
sahilmgandhi 18:6a4db94011d3 1651 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
sahilmgandhi 18:6a4db94011d3 1652 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
sahilmgandhi 18:6a4db94011d3 1653
sahilmgandhi 18:6a4db94011d3 1654 assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
sahilmgandhi 18:6a4db94011d3 1655
sahilmgandhi 18:6a4db94011d3 1656 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1657 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1658
sahilmgandhi 18:6a4db94011d3 1659 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1660 {
sahilmgandhi 18:6a4db94011d3 1661 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1662
sahilmgandhi 18:6a4db94011d3 1663 /* Update state */
sahilmgandhi 18:6a4db94011d3 1664 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
sahilmgandhi 18:6a4db94011d3 1665
sahilmgandhi 18:6a4db94011d3 1666 /* Wait till BUSY flag reset */
sahilmgandhi 18:6a4db94011d3 1667 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
sahilmgandhi 18:6a4db94011d3 1668
sahilmgandhi 18:6a4db94011d3 1669 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 1670 {
sahilmgandhi 18:6a4db94011d3 1671 /* Configure QSPI: CR register with timeout counter enable */
sahilmgandhi 18:6a4db94011d3 1672 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
sahilmgandhi 18:6a4db94011d3 1673
sahilmgandhi 18:6a4db94011d3 1674 if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
sahilmgandhi 18:6a4db94011d3 1675 {
sahilmgandhi 18:6a4db94011d3 1676 assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
sahilmgandhi 18:6a4db94011d3 1677
sahilmgandhi 18:6a4db94011d3 1678 /* Configure QSPI: LPTR register with the low-power timeout value */
sahilmgandhi 18:6a4db94011d3 1679 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
sahilmgandhi 18:6a4db94011d3 1680
sahilmgandhi 18:6a4db94011d3 1681 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 1682 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
sahilmgandhi 18:6a4db94011d3 1683
sahilmgandhi 18:6a4db94011d3 1684 /* Enable the QSPI TimeOut Interrupt */
sahilmgandhi 18:6a4db94011d3 1685 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
sahilmgandhi 18:6a4db94011d3 1686 }
sahilmgandhi 18:6a4db94011d3 1687
sahilmgandhi 18:6a4db94011d3 1688 /* Call the configuration function */
sahilmgandhi 18:6a4db94011d3 1689 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
sahilmgandhi 18:6a4db94011d3 1690 }
sahilmgandhi 18:6a4db94011d3 1691 }
sahilmgandhi 18:6a4db94011d3 1692 else
sahilmgandhi 18:6a4db94011d3 1693 {
sahilmgandhi 18:6a4db94011d3 1694 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1695 }
sahilmgandhi 18:6a4db94011d3 1696
sahilmgandhi 18:6a4db94011d3 1697 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1698 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1699
sahilmgandhi 18:6a4db94011d3 1700 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1701 return status;
sahilmgandhi 18:6a4db94011d3 1702 }
sahilmgandhi 18:6a4db94011d3 1703
sahilmgandhi 18:6a4db94011d3 1704 /**
sahilmgandhi 18:6a4db94011d3 1705 * @brief Transfer Error callbacks
sahilmgandhi 18:6a4db94011d3 1706 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1707 * @retval None
sahilmgandhi 18:6a4db94011d3 1708 */
sahilmgandhi 18:6a4db94011d3 1709 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1710 {
sahilmgandhi 18:6a4db94011d3 1711 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1712 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1713
sahilmgandhi 18:6a4db94011d3 1714 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1715 the HAL_QSPI_ErrorCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1716 */
sahilmgandhi 18:6a4db94011d3 1717 }
sahilmgandhi 18:6a4db94011d3 1718
sahilmgandhi 18:6a4db94011d3 1719 /**
sahilmgandhi 18:6a4db94011d3 1720 * @brief Abort completed callback.
sahilmgandhi 18:6a4db94011d3 1721 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1722 * @retval None
sahilmgandhi 18:6a4db94011d3 1723 */
sahilmgandhi 18:6a4db94011d3 1724 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1725 {
sahilmgandhi 18:6a4db94011d3 1726 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1727 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1728
sahilmgandhi 18:6a4db94011d3 1729 /* NOTE: This function should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1730 the HAL_QSPI_AbortCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1731 */
sahilmgandhi 18:6a4db94011d3 1732 }
sahilmgandhi 18:6a4db94011d3 1733
sahilmgandhi 18:6a4db94011d3 1734 /**
sahilmgandhi 18:6a4db94011d3 1735 * @brief Command completed callback.
sahilmgandhi 18:6a4db94011d3 1736 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1737 * @retval None
sahilmgandhi 18:6a4db94011d3 1738 */
sahilmgandhi 18:6a4db94011d3 1739 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1740 {
sahilmgandhi 18:6a4db94011d3 1741 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1742 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1743
sahilmgandhi 18:6a4db94011d3 1744 /* NOTE: This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1745 the HAL_QSPI_CmdCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1746 */
sahilmgandhi 18:6a4db94011d3 1747 }
sahilmgandhi 18:6a4db94011d3 1748
sahilmgandhi 18:6a4db94011d3 1749 /**
sahilmgandhi 18:6a4db94011d3 1750 * @brief Rx Transfer completed callbacks.
sahilmgandhi 18:6a4db94011d3 1751 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1752 * @retval None
sahilmgandhi 18:6a4db94011d3 1753 */
sahilmgandhi 18:6a4db94011d3 1754 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1755 {
sahilmgandhi 18:6a4db94011d3 1756 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1757 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1758
sahilmgandhi 18:6a4db94011d3 1759 /* NOTE: This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1760 the HAL_QSPI_RxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1761 */
sahilmgandhi 18:6a4db94011d3 1762 }
sahilmgandhi 18:6a4db94011d3 1763
sahilmgandhi 18:6a4db94011d3 1764 /**
sahilmgandhi 18:6a4db94011d3 1765 * @brief Tx Transfer completed callbacks.
sahilmgandhi 18:6a4db94011d3 1766 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1767 * @retval None
sahilmgandhi 18:6a4db94011d3 1768 */
sahilmgandhi 18:6a4db94011d3 1769 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1770 {
sahilmgandhi 18:6a4db94011d3 1771 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1772 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1773
sahilmgandhi 18:6a4db94011d3 1774 /* NOTE: This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1775 the HAL_QSPI_TxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1776 */
sahilmgandhi 18:6a4db94011d3 1777 }
sahilmgandhi 18:6a4db94011d3 1778
sahilmgandhi 18:6a4db94011d3 1779 /**
sahilmgandhi 18:6a4db94011d3 1780 * @brief Rx Half Transfer completed callbacks.
sahilmgandhi 18:6a4db94011d3 1781 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1782 * @retval None
sahilmgandhi 18:6a4db94011d3 1783 */
sahilmgandhi 18:6a4db94011d3 1784 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1785 {
sahilmgandhi 18:6a4db94011d3 1786 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1787 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1788
sahilmgandhi 18:6a4db94011d3 1789 /* NOTE: This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1790 the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1791 */
sahilmgandhi 18:6a4db94011d3 1792 }
sahilmgandhi 18:6a4db94011d3 1793
sahilmgandhi 18:6a4db94011d3 1794 /**
sahilmgandhi 18:6a4db94011d3 1795 * @brief Tx Half Transfer completed callbacks.
sahilmgandhi 18:6a4db94011d3 1796 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1797 * @retval None
sahilmgandhi 18:6a4db94011d3 1798 */
sahilmgandhi 18:6a4db94011d3 1799 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1800 {
sahilmgandhi 18:6a4db94011d3 1801 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1802 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1803
sahilmgandhi 18:6a4db94011d3 1804 /* NOTE: This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1805 the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1806 */
sahilmgandhi 18:6a4db94011d3 1807 }
sahilmgandhi 18:6a4db94011d3 1808
sahilmgandhi 18:6a4db94011d3 1809 /**
sahilmgandhi 18:6a4db94011d3 1810 * @brief FIFO Threshold callbacks
sahilmgandhi 18:6a4db94011d3 1811 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1812 * @retval None
sahilmgandhi 18:6a4db94011d3 1813 */
sahilmgandhi 18:6a4db94011d3 1814 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1815 {
sahilmgandhi 18:6a4db94011d3 1816 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1817 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1818
sahilmgandhi 18:6a4db94011d3 1819 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1820 the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1821 */
sahilmgandhi 18:6a4db94011d3 1822 }
sahilmgandhi 18:6a4db94011d3 1823
sahilmgandhi 18:6a4db94011d3 1824 /**
sahilmgandhi 18:6a4db94011d3 1825 * @brief Status Match callbacks
sahilmgandhi 18:6a4db94011d3 1826 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1827 * @retval None
sahilmgandhi 18:6a4db94011d3 1828 */
sahilmgandhi 18:6a4db94011d3 1829 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1830 {
sahilmgandhi 18:6a4db94011d3 1831 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1832 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1833
sahilmgandhi 18:6a4db94011d3 1834 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1835 the HAL_QSPI_StatusMatchCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1836 */
sahilmgandhi 18:6a4db94011d3 1837 }
sahilmgandhi 18:6a4db94011d3 1838
sahilmgandhi 18:6a4db94011d3 1839 /**
sahilmgandhi 18:6a4db94011d3 1840 * @brief Timeout callbacks
sahilmgandhi 18:6a4db94011d3 1841 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1842 * @retval None
sahilmgandhi 18:6a4db94011d3 1843 */
sahilmgandhi 18:6a4db94011d3 1844 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1845 {
sahilmgandhi 18:6a4db94011d3 1846 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1847 UNUSED(hqspi);
sahilmgandhi 18:6a4db94011d3 1848
sahilmgandhi 18:6a4db94011d3 1849 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1850 the HAL_QSPI_TimeOutCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1851 */
sahilmgandhi 18:6a4db94011d3 1852 }
sahilmgandhi 18:6a4db94011d3 1853
sahilmgandhi 18:6a4db94011d3 1854 /**
sahilmgandhi 18:6a4db94011d3 1855 * @}
sahilmgandhi 18:6a4db94011d3 1856 */
sahilmgandhi 18:6a4db94011d3 1857
sahilmgandhi 18:6a4db94011d3 1858 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
sahilmgandhi 18:6a4db94011d3 1859 * @brief QSPI control and State functions
sahilmgandhi 18:6a4db94011d3 1860 *
sahilmgandhi 18:6a4db94011d3 1861 @verbatim
sahilmgandhi 18:6a4db94011d3 1862 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1863 ##### Peripheral Control and State functions #####
sahilmgandhi 18:6a4db94011d3 1864 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1865 [..]
sahilmgandhi 18:6a4db94011d3 1866 This subsection provides a set of functions allowing to :
sahilmgandhi 18:6a4db94011d3 1867 (+) Check in run-time the state of the driver.
sahilmgandhi 18:6a4db94011d3 1868 (+) Check the error code set during last operation.
sahilmgandhi 18:6a4db94011d3 1869 (+) Abort any operation.
sahilmgandhi 18:6a4db94011d3 1870
sahilmgandhi 18:6a4db94011d3 1871 @endverbatim
sahilmgandhi 18:6a4db94011d3 1872 * @{
sahilmgandhi 18:6a4db94011d3 1873 */
sahilmgandhi 18:6a4db94011d3 1874
sahilmgandhi 18:6a4db94011d3 1875 /**
sahilmgandhi 18:6a4db94011d3 1876 * @brief Return the QSPI handle state.
sahilmgandhi 18:6a4db94011d3 1877 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1878 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1879 */
sahilmgandhi 18:6a4db94011d3 1880 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1881 {
sahilmgandhi 18:6a4db94011d3 1882 /* Return QSPI handle state */
sahilmgandhi 18:6a4db94011d3 1883 return hqspi->State;
sahilmgandhi 18:6a4db94011d3 1884 }
sahilmgandhi 18:6a4db94011d3 1885
sahilmgandhi 18:6a4db94011d3 1886 /**
sahilmgandhi 18:6a4db94011d3 1887 * @brief Return the QSPI error code
sahilmgandhi 18:6a4db94011d3 1888 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1889 * @retval QSPI Error Code
sahilmgandhi 18:6a4db94011d3 1890 */
sahilmgandhi 18:6a4db94011d3 1891 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1892 {
sahilmgandhi 18:6a4db94011d3 1893 return hqspi->ErrorCode;
sahilmgandhi 18:6a4db94011d3 1894 }
sahilmgandhi 18:6a4db94011d3 1895
sahilmgandhi 18:6a4db94011d3 1896 /**
sahilmgandhi 18:6a4db94011d3 1897 * @brief Abort the current transmission
sahilmgandhi 18:6a4db94011d3 1898 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1899 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1900 */
sahilmgandhi 18:6a4db94011d3 1901 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1902 {
sahilmgandhi 18:6a4db94011d3 1903 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1904 uint32_t tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 1905
sahilmgandhi 18:6a4db94011d3 1906 /* Check if the state is in one of the busy states */
sahilmgandhi 18:6a4db94011d3 1907 if ((hqspi->State & 0x2) != 0)
sahilmgandhi 18:6a4db94011d3 1908 {
sahilmgandhi 18:6a4db94011d3 1909 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1910 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1911
sahilmgandhi 18:6a4db94011d3 1912 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
sahilmgandhi 18:6a4db94011d3 1913 {
sahilmgandhi 18:6a4db94011d3 1914 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
sahilmgandhi 18:6a4db94011d3 1915 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
sahilmgandhi 18:6a4db94011d3 1916
sahilmgandhi 18:6a4db94011d3 1917 /* Abort DMA channel */
sahilmgandhi 18:6a4db94011d3 1918 status = HAL_DMA_Abort(hqspi->hdma);
sahilmgandhi 18:6a4db94011d3 1919 if(status != HAL_OK)
sahilmgandhi 18:6a4db94011d3 1920 {
sahilmgandhi 18:6a4db94011d3 1921 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
sahilmgandhi 18:6a4db94011d3 1922 }
sahilmgandhi 18:6a4db94011d3 1923 }
sahilmgandhi 18:6a4db94011d3 1924
sahilmgandhi 18:6a4db94011d3 1925 /* Configure QSPI: CR register with Abort request */
sahilmgandhi 18:6a4db94011d3 1926 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
sahilmgandhi 18:6a4db94011d3 1927
sahilmgandhi 18:6a4db94011d3 1928 /* Wait until TC flag is set to go back in idle state */
sahilmgandhi 18:6a4db94011d3 1929 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
sahilmgandhi 18:6a4db94011d3 1930
sahilmgandhi 18:6a4db94011d3 1931 if(status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 1932 {
sahilmgandhi 18:6a4db94011d3 1933 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 1934
sahilmgandhi 18:6a4db94011d3 1935 /* Wait until BUSY flag is reset */
sahilmgandhi 18:6a4db94011d3 1936 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
sahilmgandhi 18:6a4db94011d3 1937 }
sahilmgandhi 18:6a4db94011d3 1938
sahilmgandhi 18:6a4db94011d3 1939 if (status == HAL_OK)
sahilmgandhi 18:6a4db94011d3 1940 {
sahilmgandhi 18:6a4db94011d3 1941 /* Update state */
sahilmgandhi 18:6a4db94011d3 1942 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1943 }
sahilmgandhi 18:6a4db94011d3 1944 }
sahilmgandhi 18:6a4db94011d3 1945
sahilmgandhi 18:6a4db94011d3 1946 return status;
sahilmgandhi 18:6a4db94011d3 1947 }
sahilmgandhi 18:6a4db94011d3 1948
sahilmgandhi 18:6a4db94011d3 1949 /**
sahilmgandhi 18:6a4db94011d3 1950 * @brief Abort the current transmission (non-blocking function)
sahilmgandhi 18:6a4db94011d3 1951 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 1952 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1953 */
sahilmgandhi 18:6a4db94011d3 1954 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 1955 {
sahilmgandhi 18:6a4db94011d3 1956 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1957
sahilmgandhi 18:6a4db94011d3 1958 /* Check if the state is in one of the busy states */
sahilmgandhi 18:6a4db94011d3 1959 if ((hqspi->State & 0x2) != 0)
sahilmgandhi 18:6a4db94011d3 1960 {
sahilmgandhi 18:6a4db94011d3 1961 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 1962 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 1963
sahilmgandhi 18:6a4db94011d3 1964 /* Update QSPI state */
sahilmgandhi 18:6a4db94011d3 1965 hqspi->State = HAL_QSPI_STATE_ABORT;
sahilmgandhi 18:6a4db94011d3 1966
sahilmgandhi 18:6a4db94011d3 1967 /* Disable all interrupts */
sahilmgandhi 18:6a4db94011d3 1968 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
sahilmgandhi 18:6a4db94011d3 1969
sahilmgandhi 18:6a4db94011d3 1970 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
sahilmgandhi 18:6a4db94011d3 1971 {
sahilmgandhi 18:6a4db94011d3 1972 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
sahilmgandhi 18:6a4db94011d3 1973 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
sahilmgandhi 18:6a4db94011d3 1974
sahilmgandhi 18:6a4db94011d3 1975 /* Abort DMA channel */
sahilmgandhi 18:6a4db94011d3 1976 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
sahilmgandhi 18:6a4db94011d3 1977 HAL_DMA_Abort_IT(hqspi->hdma);
sahilmgandhi 18:6a4db94011d3 1978 }
sahilmgandhi 18:6a4db94011d3 1979 else
sahilmgandhi 18:6a4db94011d3 1980 {
sahilmgandhi 18:6a4db94011d3 1981 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 1982 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 1983
sahilmgandhi 18:6a4db94011d3 1984 /* Enable the QSPI Transfer Complete Interrupt */
sahilmgandhi 18:6a4db94011d3 1985 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
sahilmgandhi 18:6a4db94011d3 1986
sahilmgandhi 18:6a4db94011d3 1987 /* Configure QSPI: CR register with Abort request */
sahilmgandhi 18:6a4db94011d3 1988 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
sahilmgandhi 18:6a4db94011d3 1989 }
sahilmgandhi 18:6a4db94011d3 1990 }
sahilmgandhi 18:6a4db94011d3 1991
sahilmgandhi 18:6a4db94011d3 1992 return status;
sahilmgandhi 18:6a4db94011d3 1993 }
sahilmgandhi 18:6a4db94011d3 1994
sahilmgandhi 18:6a4db94011d3 1995 /** @brief Set QSPI timeout
sahilmgandhi 18:6a4db94011d3 1996 * @param hqspi: QSPI handle.
sahilmgandhi 18:6a4db94011d3 1997 * @param Timeout: Timeout for the QSPI memory access.
sahilmgandhi 18:6a4db94011d3 1998 * @retval None
sahilmgandhi 18:6a4db94011d3 1999 */
sahilmgandhi 18:6a4db94011d3 2000 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 2001 {
sahilmgandhi 18:6a4db94011d3 2002 hqspi->Timeout = Timeout;
sahilmgandhi 18:6a4db94011d3 2003 }
sahilmgandhi 18:6a4db94011d3 2004
sahilmgandhi 18:6a4db94011d3 2005 /** @brief Set QSPI Fifo threshold.
sahilmgandhi 18:6a4db94011d3 2006 * @param hqspi: QSPI handle.
sahilmgandhi 18:6a4db94011d3 2007 * @param Threshold: Threshold of the Fifo (value between 1 and 16).
sahilmgandhi 18:6a4db94011d3 2008 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 2009 */
sahilmgandhi 18:6a4db94011d3 2010 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
sahilmgandhi 18:6a4db94011d3 2011 {
sahilmgandhi 18:6a4db94011d3 2012 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 2013
sahilmgandhi 18:6a4db94011d3 2014 /* Process locked */
sahilmgandhi 18:6a4db94011d3 2015 __HAL_LOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 2016
sahilmgandhi 18:6a4db94011d3 2017 if(hqspi->State == HAL_QSPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 2018 {
sahilmgandhi 18:6a4db94011d3 2019 /* Synchronize init structure with new FIFO threshold value */
sahilmgandhi 18:6a4db94011d3 2020 hqspi->Init.FifoThreshold = Threshold;
sahilmgandhi 18:6a4db94011d3 2021
sahilmgandhi 18:6a4db94011d3 2022 /* Configure QSPI FIFO Threshold */
sahilmgandhi 18:6a4db94011d3 2023 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
sahilmgandhi 18:6a4db94011d3 2024 ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
sahilmgandhi 18:6a4db94011d3 2025 }
sahilmgandhi 18:6a4db94011d3 2026 else
sahilmgandhi 18:6a4db94011d3 2027 {
sahilmgandhi 18:6a4db94011d3 2028 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 2029 }
sahilmgandhi 18:6a4db94011d3 2030
sahilmgandhi 18:6a4db94011d3 2031 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 2032 __HAL_UNLOCK(hqspi);
sahilmgandhi 18:6a4db94011d3 2033
sahilmgandhi 18:6a4db94011d3 2034 /* Return function status */
sahilmgandhi 18:6a4db94011d3 2035 return status;
sahilmgandhi 18:6a4db94011d3 2036 }
sahilmgandhi 18:6a4db94011d3 2037
sahilmgandhi 18:6a4db94011d3 2038 /** @brief Get QSPI Fifo threshold.
sahilmgandhi 18:6a4db94011d3 2039 * @param hqspi: QSPI handle.
sahilmgandhi 18:6a4db94011d3 2040 * @retval Fifo threshold (value between 1 and 16)
sahilmgandhi 18:6a4db94011d3 2041 */
sahilmgandhi 18:6a4db94011d3 2042 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
sahilmgandhi 18:6a4db94011d3 2043 {
sahilmgandhi 18:6a4db94011d3 2044 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
sahilmgandhi 18:6a4db94011d3 2045 }
sahilmgandhi 18:6a4db94011d3 2046
sahilmgandhi 18:6a4db94011d3 2047 /**
sahilmgandhi 18:6a4db94011d3 2048 * @}
sahilmgandhi 18:6a4db94011d3 2049 */
sahilmgandhi 18:6a4db94011d3 2050
sahilmgandhi 18:6a4db94011d3 2051 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 2052
sahilmgandhi 18:6a4db94011d3 2053 /**
sahilmgandhi 18:6a4db94011d3 2054 * @brief DMA QSPI receive process complete callback.
sahilmgandhi 18:6a4db94011d3 2055 * @param hdma: DMA handle
sahilmgandhi 18:6a4db94011d3 2056 * @retval None
sahilmgandhi 18:6a4db94011d3 2057 */
sahilmgandhi 18:6a4db94011d3 2058 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2059 {
sahilmgandhi 18:6a4db94011d3 2060 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2061 hqspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2062
sahilmgandhi 18:6a4db94011d3 2063 /* Enable the QSPI transfer complete Interrupt */
sahilmgandhi 18:6a4db94011d3 2064 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
sahilmgandhi 18:6a4db94011d3 2065 }
sahilmgandhi 18:6a4db94011d3 2066
sahilmgandhi 18:6a4db94011d3 2067 /**
sahilmgandhi 18:6a4db94011d3 2068 * @brief DMA QSPI transmit process complete callback.
sahilmgandhi 18:6a4db94011d3 2069 * @param hdma: DMA handle
sahilmgandhi 18:6a4db94011d3 2070 * @retval None
sahilmgandhi 18:6a4db94011d3 2071 */
sahilmgandhi 18:6a4db94011d3 2072 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2073 {
sahilmgandhi 18:6a4db94011d3 2074 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2075 hqspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2076
sahilmgandhi 18:6a4db94011d3 2077 /* Enable the QSPI transfer complete Interrupt */
sahilmgandhi 18:6a4db94011d3 2078 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
sahilmgandhi 18:6a4db94011d3 2079 }
sahilmgandhi 18:6a4db94011d3 2080
sahilmgandhi 18:6a4db94011d3 2081 /**
sahilmgandhi 18:6a4db94011d3 2082 * @brief DMA QSPI receive process half complete callback
sahilmgandhi 18:6a4db94011d3 2083 * @param hdma : DMA handle
sahilmgandhi 18:6a4db94011d3 2084 * @retval None
sahilmgandhi 18:6a4db94011d3 2085 */
sahilmgandhi 18:6a4db94011d3 2086 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2087 {
sahilmgandhi 18:6a4db94011d3 2088 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2089
sahilmgandhi 18:6a4db94011d3 2090 HAL_QSPI_RxHalfCpltCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 2091 }
sahilmgandhi 18:6a4db94011d3 2092
sahilmgandhi 18:6a4db94011d3 2093 /**
sahilmgandhi 18:6a4db94011d3 2094 * @brief DMA QSPI transmit process half complete callback
sahilmgandhi 18:6a4db94011d3 2095 * @param hdma : DMA handle
sahilmgandhi 18:6a4db94011d3 2096 * @retval None
sahilmgandhi 18:6a4db94011d3 2097 */
sahilmgandhi 18:6a4db94011d3 2098 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2099 {
sahilmgandhi 18:6a4db94011d3 2100 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2101
sahilmgandhi 18:6a4db94011d3 2102 HAL_QSPI_TxHalfCpltCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 2103 }
sahilmgandhi 18:6a4db94011d3 2104
sahilmgandhi 18:6a4db94011d3 2105 /**
sahilmgandhi 18:6a4db94011d3 2106 * @brief DMA QSPI communication error callback.
sahilmgandhi 18:6a4db94011d3 2107 * @param hdma: DMA handle
sahilmgandhi 18:6a4db94011d3 2108 * @retval None
sahilmgandhi 18:6a4db94011d3 2109 */
sahilmgandhi 18:6a4db94011d3 2110 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2111 {
sahilmgandhi 18:6a4db94011d3 2112 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2113
sahilmgandhi 18:6a4db94011d3 2114 /* if DMA error is FIFO error ignore it */
sahilmgandhi 18:6a4db94011d3 2115 if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
sahilmgandhi 18:6a4db94011d3 2116 {
sahilmgandhi 18:6a4db94011d3 2117 hqspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2118 hqspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2119 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
sahilmgandhi 18:6a4db94011d3 2120
sahilmgandhi 18:6a4db94011d3 2121 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
sahilmgandhi 18:6a4db94011d3 2122 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
sahilmgandhi 18:6a4db94011d3 2123
sahilmgandhi 18:6a4db94011d3 2124 /* Abort the QSPI */
sahilmgandhi 18:6a4db94011d3 2125 HAL_QSPI_Abort_IT(hqspi);
sahilmgandhi 18:6a4db94011d3 2126 }
sahilmgandhi 18:6a4db94011d3 2127 }
sahilmgandhi 18:6a4db94011d3 2128
sahilmgandhi 18:6a4db94011d3 2129 /**
sahilmgandhi 18:6a4db94011d3 2130 * @brief DMA QSPI abort complete callback.
sahilmgandhi 18:6a4db94011d3 2131 * @param hdma: DMA handle
sahilmgandhi 18:6a4db94011d3 2132 * @retval None
sahilmgandhi 18:6a4db94011d3 2133 */
sahilmgandhi 18:6a4db94011d3 2134 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2135 {
sahilmgandhi 18:6a4db94011d3 2136 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2137
sahilmgandhi 18:6a4db94011d3 2138 hqspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2139 hqspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2140
sahilmgandhi 18:6a4db94011d3 2141 if(hqspi->State == HAL_QSPI_STATE_ABORT)
sahilmgandhi 18:6a4db94011d3 2142 {
sahilmgandhi 18:6a4db94011d3 2143 /* DMA Abort called by QSPI abort */
sahilmgandhi 18:6a4db94011d3 2144 /* Clear interrupt */
sahilmgandhi 18:6a4db94011d3 2145 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
sahilmgandhi 18:6a4db94011d3 2146
sahilmgandhi 18:6a4db94011d3 2147 /* Enable the QSPI Transfer Complete Interrupt */
sahilmgandhi 18:6a4db94011d3 2148 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
sahilmgandhi 18:6a4db94011d3 2149
sahilmgandhi 18:6a4db94011d3 2150 /* Configure QSPI: CR register with Abort request */
sahilmgandhi 18:6a4db94011d3 2151 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
sahilmgandhi 18:6a4db94011d3 2152 }
sahilmgandhi 18:6a4db94011d3 2153 else
sahilmgandhi 18:6a4db94011d3 2154 {
sahilmgandhi 18:6a4db94011d3 2155 /* DMA Abort called due to a transfer error interrupt */
sahilmgandhi 18:6a4db94011d3 2156 /* Change state of QSPI */
sahilmgandhi 18:6a4db94011d3 2157 hqspi->State = HAL_QSPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2158
sahilmgandhi 18:6a4db94011d3 2159 /* Error callback */
sahilmgandhi 18:6a4db94011d3 2160 HAL_QSPI_ErrorCallback(hqspi);
sahilmgandhi 18:6a4db94011d3 2161 }
sahilmgandhi 18:6a4db94011d3 2162 }
sahilmgandhi 18:6a4db94011d3 2163 /**
sahilmgandhi 18:6a4db94011d3 2164 * @brief Wait for a flag state until timeout.
sahilmgandhi 18:6a4db94011d3 2165 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 2166 * @param Flag: Flag checked
sahilmgandhi 18:6a4db94011d3 2167 * @param State: Value of the flag expected
sahilmgandhi 18:6a4db94011d3 2168 * @param Timeout: Duration of the time out
sahilmgandhi 18:6a4db94011d3 2169 * @param tickstart: tick start value
sahilmgandhi 18:6a4db94011d3 2170 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 2171 */
sahilmgandhi 18:6a4db94011d3 2172 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
sahilmgandhi 18:6a4db94011d3 2173 FlagStatus State, uint32_t tickstart, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 2174 {
sahilmgandhi 18:6a4db94011d3 2175 /* Wait until flag is in expected state */
sahilmgandhi 18:6a4db94011d3 2176 while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
sahilmgandhi 18:6a4db94011d3 2177 {
sahilmgandhi 18:6a4db94011d3 2178 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 2179 if (Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 2180 {
sahilmgandhi 18:6a4db94011d3 2181 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
sahilmgandhi 18:6a4db94011d3 2182 {
sahilmgandhi 18:6a4db94011d3 2183 hqspi->State = HAL_QSPI_STATE_ERROR;
sahilmgandhi 18:6a4db94011d3 2184 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 2185
sahilmgandhi 18:6a4db94011d3 2186 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 2187 }
sahilmgandhi 18:6a4db94011d3 2188 }
sahilmgandhi 18:6a4db94011d3 2189 }
sahilmgandhi 18:6a4db94011d3 2190 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 2191 }
sahilmgandhi 18:6a4db94011d3 2192
sahilmgandhi 18:6a4db94011d3 2193 /**
sahilmgandhi 18:6a4db94011d3 2194 * @brief Configure the communication registers.
sahilmgandhi 18:6a4db94011d3 2195 * @param hqspi: QSPI handle
sahilmgandhi 18:6a4db94011d3 2196 * @param cmd: structure that contains the command configuration information
sahilmgandhi 18:6a4db94011d3 2197 * @param FunctionalMode: functional mode to configured
sahilmgandhi 18:6a4db94011d3 2198 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 2199 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
sahilmgandhi 18:6a4db94011d3 2200 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
sahilmgandhi 18:6a4db94011d3 2201 * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
sahilmgandhi 18:6a4db94011d3 2202 * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
sahilmgandhi 18:6a4db94011d3 2203 * @retval None
sahilmgandhi 18:6a4db94011d3 2204 */
sahilmgandhi 18:6a4db94011d3 2205 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
sahilmgandhi 18:6a4db94011d3 2206 {
sahilmgandhi 18:6a4db94011d3 2207 assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2208
sahilmgandhi 18:6a4db94011d3 2209 if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
sahilmgandhi 18:6a4db94011d3 2210 {
sahilmgandhi 18:6a4db94011d3 2211 /* Configure QSPI: DLR register with the number of data to read or write */
sahilmgandhi 18:6a4db94011d3 2212 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
sahilmgandhi 18:6a4db94011d3 2213 }
sahilmgandhi 18:6a4db94011d3 2214
sahilmgandhi 18:6a4db94011d3 2215 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
sahilmgandhi 18:6a4db94011d3 2216 {
sahilmgandhi 18:6a4db94011d3 2217 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
sahilmgandhi 18:6a4db94011d3 2218 {
sahilmgandhi 18:6a4db94011d3 2219 /* Configure QSPI: ABR register with alternate bytes value */
sahilmgandhi 18:6a4db94011d3 2220 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
sahilmgandhi 18:6a4db94011d3 2221
sahilmgandhi 18:6a4db94011d3 2222 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 2223 {
sahilmgandhi 18:6a4db94011d3 2224 /*---- Command with instruction, address and alternate bytes ----*/
sahilmgandhi 18:6a4db94011d3 2225 /* Configure QSPI: CCR register with all communications parameters */
sahilmgandhi 18:6a4db94011d3 2226 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
sahilmgandhi 18:6a4db94011d3 2227 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
sahilmgandhi 18:6a4db94011d3 2228 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
sahilmgandhi 18:6a4db94011d3 2229 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2230
sahilmgandhi 18:6a4db94011d3 2231 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
sahilmgandhi 18:6a4db94011d3 2232 {
sahilmgandhi 18:6a4db94011d3 2233 /* Configure QSPI: AR register with address value */
sahilmgandhi 18:6a4db94011d3 2234 WRITE_REG(hqspi->Instance->AR, cmd->Address);
sahilmgandhi 18:6a4db94011d3 2235 }
sahilmgandhi 18:6a4db94011d3 2236 }
sahilmgandhi 18:6a4db94011d3 2237 else
sahilmgandhi 18:6a4db94011d3 2238 {
sahilmgandhi 18:6a4db94011d3 2239 /*---- Command with instruction and alternate bytes ----*/
sahilmgandhi 18:6a4db94011d3 2240 /* Configure QSPI: CCR register with all communications parameters */
sahilmgandhi 18:6a4db94011d3 2241 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
sahilmgandhi 18:6a4db94011d3 2242 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
sahilmgandhi 18:6a4db94011d3 2243 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
sahilmgandhi 18:6a4db94011d3 2244 cmd->Instruction | FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2245 }
sahilmgandhi 18:6a4db94011d3 2246 }
sahilmgandhi 18:6a4db94011d3 2247 else
sahilmgandhi 18:6a4db94011d3 2248 {
sahilmgandhi 18:6a4db94011d3 2249 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 2250 {
sahilmgandhi 18:6a4db94011d3 2251 /*---- Command with instruction and address ----*/
sahilmgandhi 18:6a4db94011d3 2252 /* Configure QSPI: CCR register with all communications parameters */
sahilmgandhi 18:6a4db94011d3 2253 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
sahilmgandhi 18:6a4db94011d3 2254 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
sahilmgandhi 18:6a4db94011d3 2255 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
sahilmgandhi 18:6a4db94011d3 2256 cmd->Instruction | FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2257
sahilmgandhi 18:6a4db94011d3 2258 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
sahilmgandhi 18:6a4db94011d3 2259 {
sahilmgandhi 18:6a4db94011d3 2260 /* Configure QSPI: AR register with address value */
sahilmgandhi 18:6a4db94011d3 2261 WRITE_REG(hqspi->Instance->AR, cmd->Address);
sahilmgandhi 18:6a4db94011d3 2262 }
sahilmgandhi 18:6a4db94011d3 2263 }
sahilmgandhi 18:6a4db94011d3 2264 else
sahilmgandhi 18:6a4db94011d3 2265 {
sahilmgandhi 18:6a4db94011d3 2266 /*---- Command with only instruction ----*/
sahilmgandhi 18:6a4db94011d3 2267 /* Configure QSPI: CCR register with all communications parameters */
sahilmgandhi 18:6a4db94011d3 2268 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
sahilmgandhi 18:6a4db94011d3 2269 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
sahilmgandhi 18:6a4db94011d3 2270 cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
sahilmgandhi 18:6a4db94011d3 2271 FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2272 }
sahilmgandhi 18:6a4db94011d3 2273 }
sahilmgandhi 18:6a4db94011d3 2274 }
sahilmgandhi 18:6a4db94011d3 2275 else
sahilmgandhi 18:6a4db94011d3 2276 {
sahilmgandhi 18:6a4db94011d3 2277 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
sahilmgandhi 18:6a4db94011d3 2278 {
sahilmgandhi 18:6a4db94011d3 2279 /* Configure QSPI: ABR register with alternate bytes value */
sahilmgandhi 18:6a4db94011d3 2280 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
sahilmgandhi 18:6a4db94011d3 2281
sahilmgandhi 18:6a4db94011d3 2282 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 2283 {
sahilmgandhi 18:6a4db94011d3 2284 /*---- Command with address and alternate bytes ----*/
sahilmgandhi 18:6a4db94011d3 2285 /* Configure QSPI: CCR register with all communications parameters */
sahilmgandhi 18:6a4db94011d3 2286 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
sahilmgandhi 18:6a4db94011d3 2287 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
sahilmgandhi 18:6a4db94011d3 2288 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
sahilmgandhi 18:6a4db94011d3 2289 cmd->InstructionMode | FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2290
sahilmgandhi 18:6a4db94011d3 2291 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
sahilmgandhi 18:6a4db94011d3 2292 {
sahilmgandhi 18:6a4db94011d3 2293 /* Configure QSPI: AR register with address value */
sahilmgandhi 18:6a4db94011d3 2294 WRITE_REG(hqspi->Instance->AR, cmd->Address);
sahilmgandhi 18:6a4db94011d3 2295 }
sahilmgandhi 18:6a4db94011d3 2296 }
sahilmgandhi 18:6a4db94011d3 2297 else
sahilmgandhi 18:6a4db94011d3 2298 {
sahilmgandhi 18:6a4db94011d3 2299 /*---- Command with only alternate bytes ----*/
sahilmgandhi 18:6a4db94011d3 2300 /* Configure QSPI: CCR register with all communications parameters */
sahilmgandhi 18:6a4db94011d3 2301 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
sahilmgandhi 18:6a4db94011d3 2302 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
sahilmgandhi 18:6a4db94011d3 2303 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
sahilmgandhi 18:6a4db94011d3 2304 FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2305 }
sahilmgandhi 18:6a4db94011d3 2306 }
sahilmgandhi 18:6a4db94011d3 2307 else
sahilmgandhi 18:6a4db94011d3 2308 {
sahilmgandhi 18:6a4db94011d3 2309 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
sahilmgandhi 18:6a4db94011d3 2310 {
sahilmgandhi 18:6a4db94011d3 2311 /*---- Command with only address ----*/
sahilmgandhi 18:6a4db94011d3 2312 /* Configure QSPI: CCR register with all communications parameters */
sahilmgandhi 18:6a4db94011d3 2313 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
sahilmgandhi 18:6a4db94011d3 2314 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
sahilmgandhi 18:6a4db94011d3 2315 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
sahilmgandhi 18:6a4db94011d3 2316 FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2317
sahilmgandhi 18:6a4db94011d3 2318 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
sahilmgandhi 18:6a4db94011d3 2319 {
sahilmgandhi 18:6a4db94011d3 2320 /* Configure QSPI: AR register with address value */
sahilmgandhi 18:6a4db94011d3 2321 WRITE_REG(hqspi->Instance->AR, cmd->Address);
sahilmgandhi 18:6a4db94011d3 2322 }
sahilmgandhi 18:6a4db94011d3 2323 }
sahilmgandhi 18:6a4db94011d3 2324 else
sahilmgandhi 18:6a4db94011d3 2325 {
sahilmgandhi 18:6a4db94011d3 2326 /*---- Command with only data phase ----*/
sahilmgandhi 18:6a4db94011d3 2327 if (cmd->DataMode != QSPI_DATA_NONE)
sahilmgandhi 18:6a4db94011d3 2328 {
sahilmgandhi 18:6a4db94011d3 2329 /* Configure QSPI: CCR register with all communications parameters */
sahilmgandhi 18:6a4db94011d3 2330 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
sahilmgandhi 18:6a4db94011d3 2331 cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
sahilmgandhi 18:6a4db94011d3 2332 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
sahilmgandhi 18:6a4db94011d3 2333 }
sahilmgandhi 18:6a4db94011d3 2334 }
sahilmgandhi 18:6a4db94011d3 2335 }
sahilmgandhi 18:6a4db94011d3 2336 }
sahilmgandhi 18:6a4db94011d3 2337 }
sahilmgandhi 18:6a4db94011d3 2338 /**
sahilmgandhi 18:6a4db94011d3 2339 * @}
sahilmgandhi 18:6a4db94011d3 2340 */
sahilmgandhi 18:6a4db94011d3 2341 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx */
sahilmgandhi 18:6a4db94011d3 2342
sahilmgandhi 18:6a4db94011d3 2343 #endif /* HAL_QSPI_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 2344 /**
sahilmgandhi 18:6a4db94011d3 2345 * @}
sahilmgandhi 18:6a4db94011d3 2346 */
sahilmgandhi 18:6a4db94011d3 2347
sahilmgandhi 18:6a4db94011d3 2348 /**
sahilmgandhi 18:6a4db94011d3 2349 * @}
sahilmgandhi 18:6a4db94011d3 2350 */
sahilmgandhi 18:6a4db94011d3 2351
sahilmgandhi 18:6a4db94011d3 2352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/