MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_pwr_ex.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of PWR HAL Extension module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_HAL_PWR_EX_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_HAL_PWR_EX_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f4xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup PWREx
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 58 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 59 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
sahilmgandhi 18:6a4db94011d3 60 * @{
sahilmgandhi 18:6a4db94011d3 61 */
sahilmgandhi 18:6a4db94011d3 62 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 63 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
sahilmgandhi 18:6a4db94011d3 66 * @{
sahilmgandhi 18:6a4db94011d3 67 */
sahilmgandhi 18:6a4db94011d3 68 #define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
sahilmgandhi 18:6a4db94011d3 69 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
sahilmgandhi 18:6a4db94011d3 70 /**
sahilmgandhi 18:6a4db94011d3 71 * @}
sahilmgandhi 18:6a4db94011d3 72 */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
sahilmgandhi 18:6a4db94011d3 75 * @{
sahilmgandhi 18:6a4db94011d3 76 */
sahilmgandhi 18:6a4db94011d3 77 #define PWR_FLAG_ODRDY PWR_CSR_ODRDY
sahilmgandhi 18:6a4db94011d3 78 #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
sahilmgandhi 18:6a4db94011d3 79 #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
sahilmgandhi 18:6a4db94011d3 80 /**
sahilmgandhi 18:6a4db94011d3 81 * @}
sahilmgandhi 18:6a4db94011d3 82 */
sahilmgandhi 18:6a4db94011d3 83 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
sahilmgandhi 18:6a4db94011d3 86 * @{
sahilmgandhi 18:6a4db94011d3 87 */
sahilmgandhi 18:6a4db94011d3 88 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
sahilmgandhi 18:6a4db94011d3 89 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
sahilmgandhi 18:6a4db94011d3 90 #define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00000000U) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
sahilmgandhi 18:6a4db94011d3 91 #else
sahilmgandhi 18:6a4db94011d3 92 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
sahilmgandhi 18:6a4db94011d3 93 180 MHz by activating the over-drive mode. */
sahilmgandhi 18:6a4db94011d3 94 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
sahilmgandhi 18:6a4db94011d3 95 168 MHz by activating the over-drive mode. */
sahilmgandhi 18:6a4db94011d3 96 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
sahilmgandhi 18:6a4db94011d3 97 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
sahilmgandhi 18:6a4db94011d3 98 /**
sahilmgandhi 18:6a4db94011d3 99 * @}
sahilmgandhi 18:6a4db94011d3 100 */
sahilmgandhi 18:6a4db94011d3 101 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
sahilmgandhi 18:6a4db94011d3 102 defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 103 /** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
sahilmgandhi 18:6a4db94011d3 104 * @{
sahilmgandhi 18:6a4db94011d3 105 */
sahilmgandhi 18:6a4db94011d3 106 #define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080U)
sahilmgandhi 18:6a4db94011d3 107 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
sahilmgandhi 18:6a4db94011d3 108 defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 109 #define PWR_WAKEUP_PIN3 ((uint32_t)0x00000040U)
sahilmgandhi 18:6a4db94011d3 110 #endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
sahilmgandhi 18:6a4db94011d3 111 STM32F412Rx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 112 /**
sahilmgandhi 18:6a4db94011d3 113 * @}
sahilmgandhi 18:6a4db94011d3 114 */
sahilmgandhi 18:6a4db94011d3 115 #endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 /**
sahilmgandhi 18:6a4db94011d3 118 * @}
sahilmgandhi 18:6a4db94011d3 119 */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 122 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
sahilmgandhi 18:6a4db94011d3 123 * @{
sahilmgandhi 18:6a4db94011d3 124 */
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
sahilmgandhi 18:6a4db94011d3 127 /** @brief macros configure the main internal regulator output voltage.
sahilmgandhi 18:6a4db94011d3 128 * @param __REGULATOR__: specifies the regulator output voltage to achieve
sahilmgandhi 18:6a4db94011d3 129 * a tradeoff between performance and power consumption when the device does
sahilmgandhi 18:6a4db94011d3 130 * not operate at the maximum frequency (refer to the datasheets for more details).
sahilmgandhi 18:6a4db94011d3 131 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 132 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
sahilmgandhi 18:6a4db94011d3 133 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
sahilmgandhi 18:6a4db94011d3 134 * @retval None
sahilmgandhi 18:6a4db94011d3 135 */
sahilmgandhi 18:6a4db94011d3 136 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
sahilmgandhi 18:6a4db94011d3 137 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 138 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
sahilmgandhi 18:6a4db94011d3 139 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 140 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
sahilmgandhi 18:6a4db94011d3 141 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 142 } while(0)
sahilmgandhi 18:6a4db94011d3 143 #else
sahilmgandhi 18:6a4db94011d3 144 /** @brief macros configure the main internal regulator output voltage.
sahilmgandhi 18:6a4db94011d3 145 * @param __REGULATOR__: specifies the regulator output voltage to achieve
sahilmgandhi 18:6a4db94011d3 146 * a tradeoff between performance and power consumption when the device does
sahilmgandhi 18:6a4db94011d3 147 * not operate at the maximum frequency (refer to the datasheets for more details).
sahilmgandhi 18:6a4db94011d3 148 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 149 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
sahilmgandhi 18:6a4db94011d3 150 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
sahilmgandhi 18:6a4db94011d3 151 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
sahilmgandhi 18:6a4db94011d3 152 * @retval None
sahilmgandhi 18:6a4db94011d3 153 */
sahilmgandhi 18:6a4db94011d3 154 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
sahilmgandhi 18:6a4db94011d3 155 __IO uint32_t tmpreg = 0x00U; \
sahilmgandhi 18:6a4db94011d3 156 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
sahilmgandhi 18:6a4db94011d3 157 /* Delay after an RCC peripheral clock enabling */ \
sahilmgandhi 18:6a4db94011d3 158 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
sahilmgandhi 18:6a4db94011d3 159 UNUSED(tmpreg); \
sahilmgandhi 18:6a4db94011d3 160 } while(0)
sahilmgandhi 18:6a4db94011d3 161 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
sahilmgandhi 18:6a4db94011d3 162
sahilmgandhi 18:6a4db94011d3 163 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 164 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 165 /** @brief Macros to enable or disable the Over drive mode.
sahilmgandhi 18:6a4db94011d3 166 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
sahilmgandhi 18:6a4db94011d3 167 */
sahilmgandhi 18:6a4db94011d3 168 #define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
sahilmgandhi 18:6a4db94011d3 169 #define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /** @brief Macros to enable or disable the Over drive switching.
sahilmgandhi 18:6a4db94011d3 172 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
sahilmgandhi 18:6a4db94011d3 173 */
sahilmgandhi 18:6a4db94011d3 174 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
sahilmgandhi 18:6a4db94011d3 175 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 /** @brief Macros to enable or disable the Under drive mode.
sahilmgandhi 18:6a4db94011d3 178 * @note This mode is enabled only with STOP low power mode.
sahilmgandhi 18:6a4db94011d3 179 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
sahilmgandhi 18:6a4db94011d3 180 * mode is only available when the main regulator or the low power regulator
sahilmgandhi 18:6a4db94011d3 181 * is in low voltage mode.
sahilmgandhi 18:6a4db94011d3 182 * @note If the Under-drive mode was enabled, it is automatically disabled after
sahilmgandhi 18:6a4db94011d3 183 * exiting Stop mode.
sahilmgandhi 18:6a4db94011d3 184 * When the voltage regulator operates in Under-drive mode, an additional
sahilmgandhi 18:6a4db94011d3 185 * startup delay is induced when waking up from Stop mode.
sahilmgandhi 18:6a4db94011d3 186 */
sahilmgandhi 18:6a4db94011d3 187 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
sahilmgandhi 18:6a4db94011d3 188 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /** @brief Check PWR flag is set or not.
sahilmgandhi 18:6a4db94011d3 191 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
sahilmgandhi 18:6a4db94011d3 192 * @param __FLAG__: specifies the flag to check.
sahilmgandhi 18:6a4db94011d3 193 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 194 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
sahilmgandhi 18:6a4db94011d3 195 * is ready
sahilmgandhi 18:6a4db94011d3 196 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
sahilmgandhi 18:6a4db94011d3 197 * switching is ready
sahilmgandhi 18:6a4db94011d3 198 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
sahilmgandhi 18:6a4db94011d3 199 * is enabled in Stop mode
sahilmgandhi 18:6a4db94011d3 200 * @retval The new state of __FLAG__ (TRUE or FALSE).
sahilmgandhi 18:6a4db94011d3 201 */
sahilmgandhi 18:6a4db94011d3 202 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 /** @brief Clear the Under-Drive Ready flag.
sahilmgandhi 18:6a4db94011d3 205 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
sahilmgandhi 18:6a4db94011d3 206 */
sahilmgandhi 18:6a4db94011d3 207 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 210 /**
sahilmgandhi 18:6a4db94011d3 211 * @}
sahilmgandhi 18:6a4db94011d3 212 */
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 215 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
sahilmgandhi 18:6a4db94011d3 216 * @{
sahilmgandhi 18:6a4db94011d3 217 */
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /** @addtogroup PWREx_Exported_Functions_Group1
sahilmgandhi 18:6a4db94011d3 220 * @{
sahilmgandhi 18:6a4db94011d3 221 */
sahilmgandhi 18:6a4db94011d3 222 void HAL_PWREx_EnableFlashPowerDown(void);
sahilmgandhi 18:6a4db94011d3 223 void HAL_PWREx_DisableFlashPowerDown(void);
sahilmgandhi 18:6a4db94011d3 224 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
sahilmgandhi 18:6a4db94011d3 225 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
sahilmgandhi 18:6a4db94011d3 226 uint32_t HAL_PWREx_GetVoltageRange(void);
sahilmgandhi 18:6a4db94011d3 227 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
sahilmgandhi 18:6a4db94011d3 228
sahilmgandhi 18:6a4db94011d3 229 #if defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 230 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
sahilmgandhi 18:6a4db94011d3 231 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
sahilmgandhi 18:6a4db94011d3 232 #endif /* STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
sahilmgandhi 18:6a4db94011d3 235 defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
sahilmgandhi 18:6a4db94011d3 236 defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 237 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
sahilmgandhi 18:6a4db94011d3 238 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
sahilmgandhi 18:6a4db94011d3 239 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
sahilmgandhi 18:6a4db94011d3 240 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
sahilmgandhi 18:6a4db94011d3 241 #endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
sahilmgandhi 18:6a4db94011d3 242 STM32F412Rx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
sahilmgandhi 18:6a4db94011d3 245 defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 246 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
sahilmgandhi 18:6a4db94011d3 247 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
sahilmgandhi 18:6a4db94011d3 248 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
sahilmgandhi 18:6a4db94011d3 249 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /**
sahilmgandhi 18:6a4db94011d3 252 * @}
sahilmgandhi 18:6a4db94011d3 253 */
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /**
sahilmgandhi 18:6a4db94011d3 256 * @}
sahilmgandhi 18:6a4db94011d3 257 */
sahilmgandhi 18:6a4db94011d3 258 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 259 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 260 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 261 /** @defgroup PWREx_Private_Constants PWREx Private Constants
sahilmgandhi 18:6a4db94011d3 262 * @{
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 /** @defgroup PWREx_register_alias_address PWREx Register alias address
sahilmgandhi 18:6a4db94011d3 266 * @{
sahilmgandhi 18:6a4db94011d3 267 */
sahilmgandhi 18:6a4db94011d3 268 /* ------------- PWR registers bit address in the alias region ---------------*/
sahilmgandhi 18:6a4db94011d3 269 /* --- CR Register ---*/
sahilmgandhi 18:6a4db94011d3 270 /* Alias word address of FPDS bit */
sahilmgandhi 18:6a4db94011d3 271 #define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
sahilmgandhi 18:6a4db94011d3 272 #define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /* Alias word address of ODEN bit */
sahilmgandhi 18:6a4db94011d3 275 #define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
sahilmgandhi 18:6a4db94011d3 276 #define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 /* Alias word address of ODSWEN bit */
sahilmgandhi 18:6a4db94011d3 279 #define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
sahilmgandhi 18:6a4db94011d3 280 #define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 281
sahilmgandhi 18:6a4db94011d3 282 /* Alias word address of MRLVDS bit */
sahilmgandhi 18:6a4db94011d3 283 #define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
sahilmgandhi 18:6a4db94011d3 284 #define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 285
sahilmgandhi 18:6a4db94011d3 286 /* Alias word address of LPLVDS bit */
sahilmgandhi 18:6a4db94011d3 287 #define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
sahilmgandhi 18:6a4db94011d3 288 #define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /**
sahilmgandhi 18:6a4db94011d3 291 * @}
sahilmgandhi 18:6a4db94011d3 292 */
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 /** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
sahilmgandhi 18:6a4db94011d3 295 * @{
sahilmgandhi 18:6a4db94011d3 296 */
sahilmgandhi 18:6a4db94011d3 297 /* --- CSR Register ---*/
sahilmgandhi 18:6a4db94011d3 298 /* Alias word address of BRE bit */
sahilmgandhi 18:6a4db94011d3 299 #define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
sahilmgandhi 18:6a4db94011d3 300 #define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 #if defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 303 /* Alias word address of WUPP bit */
sahilmgandhi 18:6a4db94011d3 304 #define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP)
sahilmgandhi 18:6a4db94011d3 305 #define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 306 #endif /* STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 307 /**
sahilmgandhi 18:6a4db94011d3 308 * @}
sahilmgandhi 18:6a4db94011d3 309 */
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 /**
sahilmgandhi 18:6a4db94011d3 312 * @}
sahilmgandhi 18:6a4db94011d3 313 */
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 316 /** @defgroup PWREx_Private_Macros PWREx Private Macros
sahilmgandhi 18:6a4db94011d3 317 * @{
sahilmgandhi 18:6a4db94011d3 318 */
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
sahilmgandhi 18:6a4db94011d3 321 * @{
sahilmgandhi 18:6a4db94011d3 322 */
sahilmgandhi 18:6a4db94011d3 323 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 324 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 325 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
sahilmgandhi 18:6a4db94011d3 326 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
sahilmgandhi 18:6a4db94011d3 327 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
sahilmgandhi 18:6a4db94011d3 330 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
sahilmgandhi 18:6a4db94011d3 331 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
sahilmgandhi 18:6a4db94011d3 332 #else
sahilmgandhi 18:6a4db94011d3 333 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
sahilmgandhi 18:6a4db94011d3 334 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
sahilmgandhi 18:6a4db94011d3 335 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
sahilmgandhi 18:6a4db94011d3 336 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 #if defined(STM32F446xx)
sahilmgandhi 18:6a4db94011d3 339 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
sahilmgandhi 18:6a4db94011d3 340 #elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
sahilmgandhi 18:6a4db94011d3 341 defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 342 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
sahilmgandhi 18:6a4db94011d3 343 ((PIN) == PWR_WAKEUP_PIN3))
sahilmgandhi 18:6a4db94011d3 344 #else
sahilmgandhi 18:6a4db94011d3 345 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
sahilmgandhi 18:6a4db94011d3 346 #endif /* STM32F446xx */
sahilmgandhi 18:6a4db94011d3 347 /**
sahilmgandhi 18:6a4db94011d3 348 * @}
sahilmgandhi 18:6a4db94011d3 349 */
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 /**
sahilmgandhi 18:6a4db94011d3 352 * @}
sahilmgandhi 18:6a4db94011d3 353 */
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 /**
sahilmgandhi 18:6a4db94011d3 356 * @}
sahilmgandhi 18:6a4db94011d3 357 */
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 /**
sahilmgandhi 18:6a4db94011d3 360 * @}
sahilmgandhi 18:6a4db94011d3 361 */
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 364 }
sahilmgandhi 18:6a4db94011d3 365 #endif
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 #endif /* __STM32F4xx_HAL_PWR_EX_H */
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/