MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_pwr.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of PWR HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32F4xx_HAL_PWR_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32F4xx_HAL_PWR_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 47 #include "stm32f4xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 50 * @{
sahilmgandhi 18:6a4db94011d3 51 */
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 /** @addtogroup PWR
sahilmgandhi 18:6a4db94011d3 54 * @{
sahilmgandhi 18:6a4db94011d3 55 */
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /** @defgroup PWR_Exported_Types PWR Exported Types
sahilmgandhi 18:6a4db94011d3 60 * @{
sahilmgandhi 18:6a4db94011d3 61 */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /**
sahilmgandhi 18:6a4db94011d3 64 * @brief PWR PVD configuration structure definition
sahilmgandhi 18:6a4db94011d3 65 */
sahilmgandhi 18:6a4db94011d3 66 typedef struct
sahilmgandhi 18:6a4db94011d3 67 {
sahilmgandhi 18:6a4db94011d3 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
sahilmgandhi 18:6a4db94011d3 69 This parameter can be a value of @ref PWR_PVD_detection_level */
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
sahilmgandhi 18:6a4db94011d3 72 This parameter can be a value of @ref PWR_PVD_Mode */
sahilmgandhi 18:6a4db94011d3 73 }PWR_PVDTypeDef;
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 /**
sahilmgandhi 18:6a4db94011d3 76 * @}
sahilmgandhi 18:6a4db94011d3 77 */
sahilmgandhi 18:6a4db94011d3 78
sahilmgandhi 18:6a4db94011d3 79 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 80 /** @defgroup PWR_Exported_Constants PWR Exported Constants
sahilmgandhi 18:6a4db94011d3 81 * @{
sahilmgandhi 18:6a4db94011d3 82 */
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
sahilmgandhi 18:6a4db94011d3 85 * @{
sahilmgandhi 18:6a4db94011d3 86 */
sahilmgandhi 18:6a4db94011d3 87 #define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100U)
sahilmgandhi 18:6a4db94011d3 88 /**
sahilmgandhi 18:6a4db94011d3 89 * @}
sahilmgandhi 18:6a4db94011d3 90 */
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
sahilmgandhi 18:6a4db94011d3 93 * @{
sahilmgandhi 18:6a4db94011d3 94 */
sahilmgandhi 18:6a4db94011d3 95 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
sahilmgandhi 18:6a4db94011d3 96 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
sahilmgandhi 18:6a4db94011d3 97 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
sahilmgandhi 18:6a4db94011d3 98 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
sahilmgandhi 18:6a4db94011d3 99 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
sahilmgandhi 18:6a4db94011d3 100 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
sahilmgandhi 18:6a4db94011d3 101 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
sahilmgandhi 18:6a4db94011d3 102 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
sahilmgandhi 18:6a4db94011d3 103 (Compare internally to VREFINT) */
sahilmgandhi 18:6a4db94011d3 104 /**
sahilmgandhi 18:6a4db94011d3 105 * @}
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /** @defgroup PWR_PVD_Mode PWR PVD Mode
sahilmgandhi 18:6a4db94011d3 109 * @{
sahilmgandhi 18:6a4db94011d3 110 */
sahilmgandhi 18:6a4db94011d3 111 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */
sahilmgandhi 18:6a4db94011d3 112 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
sahilmgandhi 18:6a4db94011d3 113 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
sahilmgandhi 18:6a4db94011d3 114 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
sahilmgandhi 18:6a4db94011d3 115 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
sahilmgandhi 18:6a4db94011d3 116 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
sahilmgandhi 18:6a4db94011d3 117 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
sahilmgandhi 18:6a4db94011d3 118 /**
sahilmgandhi 18:6a4db94011d3 119 * @}
sahilmgandhi 18:6a4db94011d3 120 */
sahilmgandhi 18:6a4db94011d3 121
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
sahilmgandhi 18:6a4db94011d3 124 * @{
sahilmgandhi 18:6a4db94011d3 125 */
sahilmgandhi 18:6a4db94011d3 126 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 127 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
sahilmgandhi 18:6a4db94011d3 128 /**
sahilmgandhi 18:6a4db94011d3 129 * @}
sahilmgandhi 18:6a4db94011d3 130 */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
sahilmgandhi 18:6a4db94011d3 133 * @{
sahilmgandhi 18:6a4db94011d3 134 */
sahilmgandhi 18:6a4db94011d3 135 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 136 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
sahilmgandhi 18:6a4db94011d3 137 /**
sahilmgandhi 18:6a4db94011d3 138 * @}
sahilmgandhi 18:6a4db94011d3 139 */
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
sahilmgandhi 18:6a4db94011d3 142 * @{
sahilmgandhi 18:6a4db94011d3 143 */
sahilmgandhi 18:6a4db94011d3 144 #define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
sahilmgandhi 18:6a4db94011d3 145 #define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
sahilmgandhi 18:6a4db94011d3 146 /**
sahilmgandhi 18:6a4db94011d3 147 * @}
sahilmgandhi 18:6a4db94011d3 148 */
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 /** @defgroup PWR_Flag PWR Flag
sahilmgandhi 18:6a4db94011d3 151 * @{
sahilmgandhi 18:6a4db94011d3 152 */
sahilmgandhi 18:6a4db94011d3 153 #define PWR_FLAG_WU PWR_CSR_WUF
sahilmgandhi 18:6a4db94011d3 154 #define PWR_FLAG_SB PWR_CSR_SBF
sahilmgandhi 18:6a4db94011d3 155 #define PWR_FLAG_PVDO PWR_CSR_PVDO
sahilmgandhi 18:6a4db94011d3 156 #define PWR_FLAG_BRR PWR_CSR_BRR
sahilmgandhi 18:6a4db94011d3 157 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
sahilmgandhi 18:6a4db94011d3 158 /**
sahilmgandhi 18:6a4db94011d3 159 * @}
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 /**
sahilmgandhi 18:6a4db94011d3 163 * @}
sahilmgandhi 18:6a4db94011d3 164 */
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 167 /** @defgroup PWR_Exported_Macro PWR Exported Macro
sahilmgandhi 18:6a4db94011d3 168 * @{
sahilmgandhi 18:6a4db94011d3 169 */
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /** @brief Check PWR flag is set or not.
sahilmgandhi 18:6a4db94011d3 172 * @param __FLAG__: specifies the flag to check.
sahilmgandhi 18:6a4db94011d3 173 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 174 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
sahilmgandhi 18:6a4db94011d3 175 * was received from the WKUP pin or from the RTC alarm (Alarm A
sahilmgandhi 18:6a4db94011d3 176 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
sahilmgandhi 18:6a4db94011d3 177 * An additional wakeup event is detected if the WKUP pin is enabled
sahilmgandhi 18:6a4db94011d3 178 * (by setting the EWUP bit) when the WKUP pin level is already high.
sahilmgandhi 18:6a4db94011d3 179 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
sahilmgandhi 18:6a4db94011d3 180 * resumed from StandBy mode.
sahilmgandhi 18:6a4db94011d3 181 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
sahilmgandhi 18:6a4db94011d3 182 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
sahilmgandhi 18:6a4db94011d3 183 * For this reason, this bit is equal to 0 after Standby or reset
sahilmgandhi 18:6a4db94011d3 184 * until the PVDE bit is set.
sahilmgandhi 18:6a4db94011d3 185 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
sahilmgandhi 18:6a4db94011d3 186 * when the device wakes up from Standby mode or by a system reset
sahilmgandhi 18:6a4db94011d3 187 * or power reset.
sahilmgandhi 18:6a4db94011d3 188 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
sahilmgandhi 18:6a4db94011d3 189 * scaling output selection is ready.
sahilmgandhi 18:6a4db94011d3 190 * @retval The new state of __FLAG__ (TRUE or FALSE).
sahilmgandhi 18:6a4db94011d3 191 */
sahilmgandhi 18:6a4db94011d3 192 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 /** @brief Clear the PWR's pending flags.
sahilmgandhi 18:6a4db94011d3 195 * @param __FLAG__: specifies the flag to clear.
sahilmgandhi 18:6a4db94011d3 196 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 197 * @arg PWR_FLAG_WU: Wake Up flag
sahilmgandhi 18:6a4db94011d3 198 * @arg PWR_FLAG_SB: StandBy flag
sahilmgandhi 18:6a4db94011d3 199 */
sahilmgandhi 18:6a4db94011d3 200 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 /**
sahilmgandhi 18:6a4db94011d3 203 * @brief Enable the PVD Exti Line 16.
sahilmgandhi 18:6a4db94011d3 204 * @retval None.
sahilmgandhi 18:6a4db94011d3 205 */
sahilmgandhi 18:6a4db94011d3 206 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 /**
sahilmgandhi 18:6a4db94011d3 209 * @brief Disable the PVD EXTI Line 16.
sahilmgandhi 18:6a4db94011d3 210 * @retval None.
sahilmgandhi 18:6a4db94011d3 211 */
sahilmgandhi 18:6a4db94011d3 212 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /**
sahilmgandhi 18:6a4db94011d3 215 * @brief Enable event on PVD Exti Line 16.
sahilmgandhi 18:6a4db94011d3 216 * @retval None.
sahilmgandhi 18:6a4db94011d3 217 */
sahilmgandhi 18:6a4db94011d3 218 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 /**
sahilmgandhi 18:6a4db94011d3 221 * @brief Disable event on PVD Exti Line 16.
sahilmgandhi 18:6a4db94011d3 222 * @retval None.
sahilmgandhi 18:6a4db94011d3 223 */
sahilmgandhi 18:6a4db94011d3 224 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 /**
sahilmgandhi 18:6a4db94011d3 227 * @brief Enable the PVD Extended Interrupt Rising Trigger.
sahilmgandhi 18:6a4db94011d3 228 * @retval None.
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /**
sahilmgandhi 18:6a4db94011d3 233 * @brief Disable the PVD Extended Interrupt Rising Trigger.
sahilmgandhi 18:6a4db94011d3 234 * @retval None.
sahilmgandhi 18:6a4db94011d3 235 */
sahilmgandhi 18:6a4db94011d3 236 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /**
sahilmgandhi 18:6a4db94011d3 239 * @brief Enable the PVD Extended Interrupt Falling Trigger.
sahilmgandhi 18:6a4db94011d3 240 * @retval None.
sahilmgandhi 18:6a4db94011d3 241 */
sahilmgandhi 18:6a4db94011d3 242 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /**
sahilmgandhi 18:6a4db94011d3 246 * @brief Disable the PVD Extended Interrupt Falling Trigger.
sahilmgandhi 18:6a4db94011d3 247 * @retval None.
sahilmgandhi 18:6a4db94011d3 248 */
sahilmgandhi 18:6a4db94011d3 249 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /**
sahilmgandhi 18:6a4db94011d3 253 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
sahilmgandhi 18:6a4db94011d3 254 * @retval None.
sahilmgandhi 18:6a4db94011d3 255 */
sahilmgandhi 18:6a4db94011d3 256 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
sahilmgandhi 18:6a4db94011d3 257 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
sahilmgandhi 18:6a4db94011d3 258 }while(0)
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 /**
sahilmgandhi 18:6a4db94011d3 261 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
sahilmgandhi 18:6a4db94011d3 262 * This parameter can be:
sahilmgandhi 18:6a4db94011d3 263 * @retval None.
sahilmgandhi 18:6a4db94011d3 264 */
sahilmgandhi 18:6a4db94011d3 265 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
sahilmgandhi 18:6a4db94011d3 266 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
sahilmgandhi 18:6a4db94011d3 267 }while(0)
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 /**
sahilmgandhi 18:6a4db94011d3 270 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
sahilmgandhi 18:6a4db94011d3 271 * @retval EXTI PVD Line Status.
sahilmgandhi 18:6a4db94011d3 272 */
sahilmgandhi 18:6a4db94011d3 273 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /**
sahilmgandhi 18:6a4db94011d3 276 * @brief Clear the PVD Exti flag.
sahilmgandhi 18:6a4db94011d3 277 * @retval None.
sahilmgandhi 18:6a4db94011d3 278 */
sahilmgandhi 18:6a4db94011d3 279 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 /**
sahilmgandhi 18:6a4db94011d3 282 * @brief Generates a Software interrupt on PVD EXTI line.
sahilmgandhi 18:6a4db94011d3 283 * @retval None
sahilmgandhi 18:6a4db94011d3 284 */
sahilmgandhi 18:6a4db94011d3 285 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 /**
sahilmgandhi 18:6a4db94011d3 288 * @}
sahilmgandhi 18:6a4db94011d3 289 */
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /* Include PWR HAL Extension module */
sahilmgandhi 18:6a4db94011d3 292 #include "stm32f4xx_hal_pwr_ex.h"
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 295 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
sahilmgandhi 18:6a4db94011d3 296 * @{
sahilmgandhi 18:6a4db94011d3 297 */
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 300 * @{
sahilmgandhi 18:6a4db94011d3 301 */
sahilmgandhi 18:6a4db94011d3 302 /* Initialization and de-initialization functions *****************************/
sahilmgandhi 18:6a4db94011d3 303 void HAL_PWR_DeInit(void);
sahilmgandhi 18:6a4db94011d3 304 void HAL_PWR_EnableBkUpAccess(void);
sahilmgandhi 18:6a4db94011d3 305 void HAL_PWR_DisableBkUpAccess(void);
sahilmgandhi 18:6a4db94011d3 306 /**
sahilmgandhi 18:6a4db94011d3 307 * @}
sahilmgandhi 18:6a4db94011d3 308 */
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 311 * @{
sahilmgandhi 18:6a4db94011d3 312 */
sahilmgandhi 18:6a4db94011d3 313 /* Peripheral Control functions **********************************************/
sahilmgandhi 18:6a4db94011d3 314 /* PVD configuration */
sahilmgandhi 18:6a4db94011d3 315 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
sahilmgandhi 18:6a4db94011d3 316 void HAL_PWR_EnablePVD(void);
sahilmgandhi 18:6a4db94011d3 317 void HAL_PWR_DisablePVD(void);
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 /* WakeUp pins configuration */
sahilmgandhi 18:6a4db94011d3 320 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
sahilmgandhi 18:6a4db94011d3 321 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 /* Low Power modes entry */
sahilmgandhi 18:6a4db94011d3 324 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
sahilmgandhi 18:6a4db94011d3 325 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
sahilmgandhi 18:6a4db94011d3 326 void HAL_PWR_EnterSTANDBYMode(void);
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 /* Power PVD IRQ Handler */
sahilmgandhi 18:6a4db94011d3 329 void HAL_PWR_PVD_IRQHandler(void);
sahilmgandhi 18:6a4db94011d3 330 void HAL_PWR_PVDCallback(void);
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 /* Cortex System Control functions *******************************************/
sahilmgandhi 18:6a4db94011d3 333 void HAL_PWR_EnableSleepOnExit(void);
sahilmgandhi 18:6a4db94011d3 334 void HAL_PWR_DisableSleepOnExit(void);
sahilmgandhi 18:6a4db94011d3 335 void HAL_PWR_EnableSEVOnPend(void);
sahilmgandhi 18:6a4db94011d3 336 void HAL_PWR_DisableSEVOnPend(void);
sahilmgandhi 18:6a4db94011d3 337 /**
sahilmgandhi 18:6a4db94011d3 338 * @}
sahilmgandhi 18:6a4db94011d3 339 */
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 /**
sahilmgandhi 18:6a4db94011d3 342 * @}
sahilmgandhi 18:6a4db94011d3 343 */
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 346 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 347 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 348 /** @defgroup PWR_Private_Constants PWR Private Constants
sahilmgandhi 18:6a4db94011d3 349 * @{
sahilmgandhi 18:6a4db94011d3 350 */
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
sahilmgandhi 18:6a4db94011d3 353 * @{
sahilmgandhi 18:6a4db94011d3 354 */
sahilmgandhi 18:6a4db94011d3 355 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
sahilmgandhi 18:6a4db94011d3 356 /**
sahilmgandhi 18:6a4db94011d3 357 * @}
sahilmgandhi 18:6a4db94011d3 358 */
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 /** @defgroup PWR_register_alias_address PWR Register alias address
sahilmgandhi 18:6a4db94011d3 361 * @{
sahilmgandhi 18:6a4db94011d3 362 */
sahilmgandhi 18:6a4db94011d3 363 /* ------------- PWR registers bit address in the alias region ---------------*/
sahilmgandhi 18:6a4db94011d3 364 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
sahilmgandhi 18:6a4db94011d3 365 #define PWR_CR_OFFSET 0x00U
sahilmgandhi 18:6a4db94011d3 366 #define PWR_CSR_OFFSET 0x04U
sahilmgandhi 18:6a4db94011d3 367 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
sahilmgandhi 18:6a4db94011d3 368 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
sahilmgandhi 18:6a4db94011d3 369 /**
sahilmgandhi 18:6a4db94011d3 370 * @}
sahilmgandhi 18:6a4db94011d3 371 */
sahilmgandhi 18:6a4db94011d3 372
sahilmgandhi 18:6a4db94011d3 373 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
sahilmgandhi 18:6a4db94011d3 374 * @{
sahilmgandhi 18:6a4db94011d3 375 */
sahilmgandhi 18:6a4db94011d3 376 /* --- CR Register ---*/
sahilmgandhi 18:6a4db94011d3 377 /* Alias word address of DBP bit */
sahilmgandhi 18:6a4db94011d3 378 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
sahilmgandhi 18:6a4db94011d3 379 #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 /* Alias word address of PVDE bit */
sahilmgandhi 18:6a4db94011d3 382 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
sahilmgandhi 18:6a4db94011d3 383 #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /* Alias word address of PMODE bit */
sahilmgandhi 18:6a4db94011d3 386 #define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
sahilmgandhi 18:6a4db94011d3 387 #define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 388 /**
sahilmgandhi 18:6a4db94011d3 389 * @}
sahilmgandhi 18:6a4db94011d3 390 */
sahilmgandhi 18:6a4db94011d3 391
sahilmgandhi 18:6a4db94011d3 392 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
sahilmgandhi 18:6a4db94011d3 393 * @{
sahilmgandhi 18:6a4db94011d3 394 */
sahilmgandhi 18:6a4db94011d3 395 /* --- CSR Register ---*/
sahilmgandhi 18:6a4db94011d3 396 /* Alias word address of EWUP bit */
sahilmgandhi 18:6a4db94011d3 397 #define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
sahilmgandhi 18:6a4db94011d3 398 #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
sahilmgandhi 18:6a4db94011d3 399 /**
sahilmgandhi 18:6a4db94011d3 400 * @}
sahilmgandhi 18:6a4db94011d3 401 */
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 /**
sahilmgandhi 18:6a4db94011d3 404 * @}
sahilmgandhi 18:6a4db94011d3 405 */
sahilmgandhi 18:6a4db94011d3 406 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 407 /** @defgroup PWR_Private_Macros PWR Private Macros
sahilmgandhi 18:6a4db94011d3 408 * @{
sahilmgandhi 18:6a4db94011d3 409 */
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
sahilmgandhi 18:6a4db94011d3 412 * @{
sahilmgandhi 18:6a4db94011d3 413 */
sahilmgandhi 18:6a4db94011d3 414 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
sahilmgandhi 18:6a4db94011d3 415 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
sahilmgandhi 18:6a4db94011d3 416 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
sahilmgandhi 18:6a4db94011d3 417 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
sahilmgandhi 18:6a4db94011d3 418 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
sahilmgandhi 18:6a4db94011d3 419 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
sahilmgandhi 18:6a4db94011d3 420 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
sahilmgandhi 18:6a4db94011d3 421 ((MODE) == PWR_PVD_MODE_NORMAL))
sahilmgandhi 18:6a4db94011d3 422 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
sahilmgandhi 18:6a4db94011d3 423 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
sahilmgandhi 18:6a4db94011d3 424 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
sahilmgandhi 18:6a4db94011d3 425 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
sahilmgandhi 18:6a4db94011d3 426 /**
sahilmgandhi 18:6a4db94011d3 427 * @}
sahilmgandhi 18:6a4db94011d3 428 */
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 /**
sahilmgandhi 18:6a4db94011d3 431 * @}
sahilmgandhi 18:6a4db94011d3 432 */
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 /**
sahilmgandhi 18:6a4db94011d3 435 * @}
sahilmgandhi 18:6a4db94011d3 436 */
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 /**
sahilmgandhi 18:6a4db94011d3 439 * @}
sahilmgandhi 18:6a4db94011d3 440 */
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 443 }
sahilmgandhi 18:6a4db94011d3 444 #endif
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446
sahilmgandhi 18:6a4db94011d3 447 #endif /* __STM32F4xx_HAL_PWR_H */
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/