Mouse code for the MacroRat
mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c@46:b156ef445742, 2017-06-03 (annotated)
- Committer:
- sahilmgandhi
- Date:
- Sat Jun 03 00:22:44 2017 +0000
- Revision:
- 46:b156ef445742
- Parent:
- 18:6a4db94011d3
Final code for internal battlebot competition.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
sahilmgandhi | 18:6a4db94011d3 | 1 | /** |
sahilmgandhi | 18:6a4db94011d3 | 2 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 3 | * @file stm32f4xx_hal_nor.c |
sahilmgandhi | 18:6a4db94011d3 | 4 | * @author MCD Application Team |
sahilmgandhi | 18:6a4db94011d3 | 5 | * @version V1.5.0 |
sahilmgandhi | 18:6a4db94011d3 | 6 | * @date 06-May-2016 |
sahilmgandhi | 18:6a4db94011d3 | 7 | * @brief NOR HAL module driver. |
sahilmgandhi | 18:6a4db94011d3 | 8 | * This file provides a generic firmware to drive NOR memories mounted |
sahilmgandhi | 18:6a4db94011d3 | 9 | * as external device. |
sahilmgandhi | 18:6a4db94011d3 | 10 | * |
sahilmgandhi | 18:6a4db94011d3 | 11 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 12 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 13 | ##### How to use this driver ##### |
sahilmgandhi | 18:6a4db94011d3 | 14 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 15 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 16 | This driver is a generic layered driver which contains a set of APIs used to |
sahilmgandhi | 18:6a4db94011d3 | 17 | control NOR flash memories. It uses the FMC/FSMC layer functions to interface |
sahilmgandhi | 18:6a4db94011d3 | 18 | with NOR devices. This driver is used as follows: |
sahilmgandhi | 18:6a4db94011d3 | 19 | |
sahilmgandhi | 18:6a4db94011d3 | 20 | (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() |
sahilmgandhi | 18:6a4db94011d3 | 21 | with control and timing parameters for both normal and extended mode. |
sahilmgandhi | 18:6a4db94011d3 | 22 | |
sahilmgandhi | 18:6a4db94011d3 | 23 | (+) Read NOR flash memory manufacturer code and device IDs using the function |
sahilmgandhi | 18:6a4db94011d3 | 24 | HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef |
sahilmgandhi | 18:6a4db94011d3 | 25 | structure declared by the function caller. |
sahilmgandhi | 18:6a4db94011d3 | 26 | |
sahilmgandhi | 18:6a4db94011d3 | 27 | (+) Access NOR flash memory by read/write data unit operations using the functions |
sahilmgandhi | 18:6a4db94011d3 | 28 | HAL_NOR_Read(), HAL_NOR_Program(). |
sahilmgandhi | 18:6a4db94011d3 | 29 | |
sahilmgandhi | 18:6a4db94011d3 | 30 | (+) Perform NOR flash erase block/chip operations using the functions |
sahilmgandhi | 18:6a4db94011d3 | 31 | HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). |
sahilmgandhi | 18:6a4db94011d3 | 32 | |
sahilmgandhi | 18:6a4db94011d3 | 33 | (+) Read the NOR flash CFI (common flash interface) IDs using the function |
sahilmgandhi | 18:6a4db94011d3 | 34 | HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef |
sahilmgandhi | 18:6a4db94011d3 | 35 | structure declared by the function caller. |
sahilmgandhi | 18:6a4db94011d3 | 36 | |
sahilmgandhi | 18:6a4db94011d3 | 37 | (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ |
sahilmgandhi | 18:6a4db94011d3 | 38 | HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation |
sahilmgandhi | 18:6a4db94011d3 | 39 | |
sahilmgandhi | 18:6a4db94011d3 | 40 | (+) You can monitor the NOR device HAL state by calling the function |
sahilmgandhi | 18:6a4db94011d3 | 41 | HAL_NOR_GetState() |
sahilmgandhi | 18:6a4db94011d3 | 42 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 43 | (@) This driver is a set of generic APIs which handle standard NOR flash operations. |
sahilmgandhi | 18:6a4db94011d3 | 44 | If a NOR flash device contains different operations and/or implementations, |
sahilmgandhi | 18:6a4db94011d3 | 45 | it should be implemented separately. |
sahilmgandhi | 18:6a4db94011d3 | 46 | |
sahilmgandhi | 18:6a4db94011d3 | 47 | *** NOR HAL driver macros list *** |
sahilmgandhi | 18:6a4db94011d3 | 48 | ============================================= |
sahilmgandhi | 18:6a4db94011d3 | 49 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 50 | Below the list of most used macros in NOR HAL driver. |
sahilmgandhi | 18:6a4db94011d3 | 51 | |
sahilmgandhi | 18:6a4db94011d3 | 52 | (+) NOR_WRITE : NOR memory write data to specified address |
sahilmgandhi | 18:6a4db94011d3 | 53 | |
sahilmgandhi | 18:6a4db94011d3 | 54 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 55 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 56 | * @attention |
sahilmgandhi | 18:6a4db94011d3 | 57 | * |
sahilmgandhi | 18:6a4db94011d3 | 58 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
sahilmgandhi | 18:6a4db94011d3 | 59 | * |
sahilmgandhi | 18:6a4db94011d3 | 60 | * Redistribution and use in source and binary forms, with or without modification, |
sahilmgandhi | 18:6a4db94011d3 | 61 | * are permitted provided that the following conditions are met: |
sahilmgandhi | 18:6a4db94011d3 | 62 | * 1. Redistributions of source code must retain the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 63 | * this list of conditions and the following disclaimer. |
sahilmgandhi | 18:6a4db94011d3 | 64 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
sahilmgandhi | 18:6a4db94011d3 | 65 | * this list of conditions and the following disclaimer in the documentation |
sahilmgandhi | 18:6a4db94011d3 | 66 | * and/or other materials provided with the distribution. |
sahilmgandhi | 18:6a4db94011d3 | 67 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
sahilmgandhi | 18:6a4db94011d3 | 68 | * may be used to endorse or promote products derived from this software |
sahilmgandhi | 18:6a4db94011d3 | 69 | * without specific prior written permission. |
sahilmgandhi | 18:6a4db94011d3 | 70 | * |
sahilmgandhi | 18:6a4db94011d3 | 71 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
sahilmgandhi | 18:6a4db94011d3 | 72 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
sahilmgandhi | 18:6a4db94011d3 | 73 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
sahilmgandhi | 18:6a4db94011d3 | 74 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
sahilmgandhi | 18:6a4db94011d3 | 75 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
sahilmgandhi | 18:6a4db94011d3 | 76 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
sahilmgandhi | 18:6a4db94011d3 | 77 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
sahilmgandhi | 18:6a4db94011d3 | 78 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
sahilmgandhi | 18:6a4db94011d3 | 79 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
sahilmgandhi | 18:6a4db94011d3 | 80 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
sahilmgandhi | 18:6a4db94011d3 | 81 | * |
sahilmgandhi | 18:6a4db94011d3 | 82 | ****************************************************************************** |
sahilmgandhi | 18:6a4db94011d3 | 83 | */ |
sahilmgandhi | 18:6a4db94011d3 | 84 | |
sahilmgandhi | 18:6a4db94011d3 | 85 | /* Includes ------------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 86 | #include "stm32f4xx_hal.h" |
sahilmgandhi | 18:6a4db94011d3 | 87 | |
sahilmgandhi | 18:6a4db94011d3 | 88 | /** @addtogroup STM32F4xx_HAL_Driver |
sahilmgandhi | 18:6a4db94011d3 | 89 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 90 | */ |
sahilmgandhi | 18:6a4db94011d3 | 91 | |
sahilmgandhi | 18:6a4db94011d3 | 92 | /** @defgroup NOR NOR |
sahilmgandhi | 18:6a4db94011d3 | 93 | * @brief NOR driver modules |
sahilmgandhi | 18:6a4db94011d3 | 94 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 95 | */ |
sahilmgandhi | 18:6a4db94011d3 | 96 | #ifdef HAL_NOR_MODULE_ENABLED |
sahilmgandhi | 18:6a4db94011d3 | 97 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ |
sahilmgandhi | 18:6a4db94011d3 | 98 | defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ |
sahilmgandhi | 18:6a4db94011d3 | 99 | defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ |
sahilmgandhi | 18:6a4db94011d3 | 100 | defined(STM32F412Vx) |
sahilmgandhi | 18:6a4db94011d3 | 101 | /* Private typedef -----------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 102 | /* Private define ------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 103 | |
sahilmgandhi | 18:6a4db94011d3 | 104 | /** @defgroup NOR_Private_Defines NOR Private Defines |
sahilmgandhi | 18:6a4db94011d3 | 105 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 106 | */ |
sahilmgandhi | 18:6a4db94011d3 | 107 | |
sahilmgandhi | 18:6a4db94011d3 | 108 | /* Constants to define address to set to write a command */ |
sahilmgandhi | 18:6a4db94011d3 | 109 | #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U |
sahilmgandhi | 18:6a4db94011d3 | 110 | #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U |
sahilmgandhi | 18:6a4db94011d3 | 111 | #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU |
sahilmgandhi | 18:6a4db94011d3 | 112 | #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U |
sahilmgandhi | 18:6a4db94011d3 | 113 | #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U |
sahilmgandhi | 18:6a4db94011d3 | 114 | #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU |
sahilmgandhi | 18:6a4db94011d3 | 115 | #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U |
sahilmgandhi | 18:6a4db94011d3 | 116 | |
sahilmgandhi | 18:6a4db94011d3 | 117 | /* Constants to define data to program a command */ |
sahilmgandhi | 18:6a4db94011d3 | 118 | #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U |
sahilmgandhi | 18:6a4db94011d3 | 119 | #define NOR_CMD_DATA_FIRST (uint16_t)0x00AAU |
sahilmgandhi | 18:6a4db94011d3 | 120 | #define NOR_CMD_DATA_SECOND (uint16_t)0x0055U |
sahilmgandhi | 18:6a4db94011d3 | 121 | #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U |
sahilmgandhi | 18:6a4db94011d3 | 122 | #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U |
sahilmgandhi | 18:6a4db94011d3 | 123 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U |
sahilmgandhi | 18:6a4db94011d3 | 124 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU |
sahilmgandhi | 18:6a4db94011d3 | 125 | #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U |
sahilmgandhi | 18:6a4db94011d3 | 126 | #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U |
sahilmgandhi | 18:6a4db94011d3 | 127 | #define NOR_CMD_DATA_CFI (uint16_t)0x0098U |
sahilmgandhi | 18:6a4db94011d3 | 128 | |
sahilmgandhi | 18:6a4db94011d3 | 129 | #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U |
sahilmgandhi | 18:6a4db94011d3 | 130 | #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U |
sahilmgandhi | 18:6a4db94011d3 | 131 | #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U |
sahilmgandhi | 18:6a4db94011d3 | 132 | |
sahilmgandhi | 18:6a4db94011d3 | 133 | /* Mask on NOR STATUS REGISTER */ |
sahilmgandhi | 18:6a4db94011d3 | 134 | #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U |
sahilmgandhi | 18:6a4db94011d3 | 135 | #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U |
sahilmgandhi | 18:6a4db94011d3 | 136 | |
sahilmgandhi | 18:6a4db94011d3 | 137 | /** |
sahilmgandhi | 18:6a4db94011d3 | 138 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 139 | */ |
sahilmgandhi | 18:6a4db94011d3 | 140 | |
sahilmgandhi | 18:6a4db94011d3 | 141 | /* Private macro -------------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 142 | /* Private variables ---------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 143 | /** @defgroup NOR_Private_Variables NOR Private Variables |
sahilmgandhi | 18:6a4db94011d3 | 144 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 145 | */ |
sahilmgandhi | 18:6a4db94011d3 | 146 | |
sahilmgandhi | 18:6a4db94011d3 | 147 | static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; |
sahilmgandhi | 18:6a4db94011d3 | 148 | |
sahilmgandhi | 18:6a4db94011d3 | 149 | /** |
sahilmgandhi | 18:6a4db94011d3 | 150 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 151 | */ |
sahilmgandhi | 18:6a4db94011d3 | 152 | |
sahilmgandhi | 18:6a4db94011d3 | 153 | /* Private functions ---------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 154 | /* Exported functions --------------------------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 155 | /** @defgroup NOR_Exported_Functions NOR Exported Functions |
sahilmgandhi | 18:6a4db94011d3 | 156 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 157 | */ |
sahilmgandhi | 18:6a4db94011d3 | 158 | |
sahilmgandhi | 18:6a4db94011d3 | 159 | /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions |
sahilmgandhi | 18:6a4db94011d3 | 160 | * @brief Initialization and Configuration functions |
sahilmgandhi | 18:6a4db94011d3 | 161 | * |
sahilmgandhi | 18:6a4db94011d3 | 162 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 163 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 164 | ##### NOR Initialization and de_initialization functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 165 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 166 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 167 | This section provides functions allowing to initialize/de-initialize |
sahilmgandhi | 18:6a4db94011d3 | 168 | the NOR memory |
sahilmgandhi | 18:6a4db94011d3 | 169 | |
sahilmgandhi | 18:6a4db94011d3 | 170 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 171 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 172 | */ |
sahilmgandhi | 18:6a4db94011d3 | 173 | |
sahilmgandhi | 18:6a4db94011d3 | 174 | /** |
sahilmgandhi | 18:6a4db94011d3 | 175 | * @brief Perform the NOR memory Initialization sequence |
sahilmgandhi | 18:6a4db94011d3 | 176 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 177 | * @param Timing: pointer to NOR control timing structure |
sahilmgandhi | 18:6a4db94011d3 | 178 | * @param ExtTiming: pointer to NOR extended mode timing structure |
sahilmgandhi | 18:6a4db94011d3 | 179 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 180 | */ |
sahilmgandhi | 18:6a4db94011d3 | 181 | HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) |
sahilmgandhi | 18:6a4db94011d3 | 182 | { |
sahilmgandhi | 18:6a4db94011d3 | 183 | /* Check the NOR handle parameter */ |
sahilmgandhi | 18:6a4db94011d3 | 184 | if(hnor == NULL) |
sahilmgandhi | 18:6a4db94011d3 | 185 | { |
sahilmgandhi | 18:6a4db94011d3 | 186 | return HAL_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 187 | } |
sahilmgandhi | 18:6a4db94011d3 | 188 | |
sahilmgandhi | 18:6a4db94011d3 | 189 | if(hnor->State == HAL_NOR_STATE_RESET) |
sahilmgandhi | 18:6a4db94011d3 | 190 | { |
sahilmgandhi | 18:6a4db94011d3 | 191 | /* Allocate lock resource and initialize it */ |
sahilmgandhi | 18:6a4db94011d3 | 192 | hnor->Lock = HAL_UNLOCKED; |
sahilmgandhi | 18:6a4db94011d3 | 193 | /* Initialize the low level hardware (MSP) */ |
sahilmgandhi | 18:6a4db94011d3 | 194 | HAL_NOR_MspInit(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 195 | } |
sahilmgandhi | 18:6a4db94011d3 | 196 | |
sahilmgandhi | 18:6a4db94011d3 | 197 | /* Initialize NOR control Interface */ |
sahilmgandhi | 18:6a4db94011d3 | 198 | FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); |
sahilmgandhi | 18:6a4db94011d3 | 199 | |
sahilmgandhi | 18:6a4db94011d3 | 200 | /* Initialize NOR timing Interface */ |
sahilmgandhi | 18:6a4db94011d3 | 201 | FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); |
sahilmgandhi | 18:6a4db94011d3 | 202 | |
sahilmgandhi | 18:6a4db94011d3 | 203 | /* Initialize NOR extended mode timing Interface */ |
sahilmgandhi | 18:6a4db94011d3 | 204 | FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); |
sahilmgandhi | 18:6a4db94011d3 | 205 | |
sahilmgandhi | 18:6a4db94011d3 | 206 | /* Enable the NORSRAM device */ |
sahilmgandhi | 18:6a4db94011d3 | 207 | __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); |
sahilmgandhi | 18:6a4db94011d3 | 208 | |
sahilmgandhi | 18:6a4db94011d3 | 209 | /* Initialize NOR Memory Data Width*/ |
sahilmgandhi | 18:6a4db94011d3 | 210 | if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) |
sahilmgandhi | 18:6a4db94011d3 | 211 | { |
sahilmgandhi | 18:6a4db94011d3 | 212 | uwNORMemoryDataWidth = NOR_MEMORY_8B; |
sahilmgandhi | 18:6a4db94011d3 | 213 | } |
sahilmgandhi | 18:6a4db94011d3 | 214 | else |
sahilmgandhi | 18:6a4db94011d3 | 215 | { |
sahilmgandhi | 18:6a4db94011d3 | 216 | uwNORMemoryDataWidth = NOR_MEMORY_16B; |
sahilmgandhi | 18:6a4db94011d3 | 217 | } |
sahilmgandhi | 18:6a4db94011d3 | 218 | |
sahilmgandhi | 18:6a4db94011d3 | 219 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 220 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 221 | |
sahilmgandhi | 18:6a4db94011d3 | 222 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 223 | } |
sahilmgandhi | 18:6a4db94011d3 | 224 | |
sahilmgandhi | 18:6a4db94011d3 | 225 | /** |
sahilmgandhi | 18:6a4db94011d3 | 226 | * @brief Perform NOR memory De-Initialization sequence |
sahilmgandhi | 18:6a4db94011d3 | 227 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 228 | * the configuration information for NOR module. |
sahilmgandhi | 18:6a4db94011d3 | 229 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 230 | */ |
sahilmgandhi | 18:6a4db94011d3 | 231 | HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) |
sahilmgandhi | 18:6a4db94011d3 | 232 | { |
sahilmgandhi | 18:6a4db94011d3 | 233 | /* De-Initialize the low level hardware (MSP) */ |
sahilmgandhi | 18:6a4db94011d3 | 234 | HAL_NOR_MspDeInit(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 235 | |
sahilmgandhi | 18:6a4db94011d3 | 236 | /* Configure the NOR registers with their reset values */ |
sahilmgandhi | 18:6a4db94011d3 | 237 | FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); |
sahilmgandhi | 18:6a4db94011d3 | 238 | |
sahilmgandhi | 18:6a4db94011d3 | 239 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 240 | hnor->State = HAL_NOR_STATE_RESET; |
sahilmgandhi | 18:6a4db94011d3 | 241 | |
sahilmgandhi | 18:6a4db94011d3 | 242 | /* Release Lock */ |
sahilmgandhi | 18:6a4db94011d3 | 243 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 244 | |
sahilmgandhi | 18:6a4db94011d3 | 245 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 246 | } |
sahilmgandhi | 18:6a4db94011d3 | 247 | |
sahilmgandhi | 18:6a4db94011d3 | 248 | /** |
sahilmgandhi | 18:6a4db94011d3 | 249 | * @brief NOR MSP Init |
sahilmgandhi | 18:6a4db94011d3 | 250 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 251 | * the configuration information for NOR module. |
sahilmgandhi | 18:6a4db94011d3 | 252 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 253 | */ |
sahilmgandhi | 18:6a4db94011d3 | 254 | __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) |
sahilmgandhi | 18:6a4db94011d3 | 255 | { |
sahilmgandhi | 18:6a4db94011d3 | 256 | /* Prevent unused argument(s) compilation warning */ |
sahilmgandhi | 18:6a4db94011d3 | 257 | UNUSED(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 258 | /* NOTE : This function Should not be modified, when the callback is needed, |
sahilmgandhi | 18:6a4db94011d3 | 259 | the HAL_NOR_MspInit could be implemented in the user file |
sahilmgandhi | 18:6a4db94011d3 | 260 | */ |
sahilmgandhi | 18:6a4db94011d3 | 261 | } |
sahilmgandhi | 18:6a4db94011d3 | 262 | |
sahilmgandhi | 18:6a4db94011d3 | 263 | /** |
sahilmgandhi | 18:6a4db94011d3 | 264 | * @brief NOR MSP DeInit |
sahilmgandhi | 18:6a4db94011d3 | 265 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 266 | * the configuration information for NOR module. |
sahilmgandhi | 18:6a4db94011d3 | 267 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 268 | */ |
sahilmgandhi | 18:6a4db94011d3 | 269 | __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) |
sahilmgandhi | 18:6a4db94011d3 | 270 | { |
sahilmgandhi | 18:6a4db94011d3 | 271 | /* Prevent unused argument(s) compilation warning */ |
sahilmgandhi | 18:6a4db94011d3 | 272 | UNUSED(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 273 | /* NOTE : This function Should not be modified, when the callback is needed, |
sahilmgandhi | 18:6a4db94011d3 | 274 | the HAL_NOR_MspDeInit could be implemented in the user file |
sahilmgandhi | 18:6a4db94011d3 | 275 | */ |
sahilmgandhi | 18:6a4db94011d3 | 276 | } |
sahilmgandhi | 18:6a4db94011d3 | 277 | |
sahilmgandhi | 18:6a4db94011d3 | 278 | /** |
sahilmgandhi | 18:6a4db94011d3 | 279 | * @brief NOR BSP Wait for Ready/Busy signal |
sahilmgandhi | 18:6a4db94011d3 | 280 | * @param hnor: pointer to a NOR_HandleTypeDef structure that contains |
sahilmgandhi | 18:6a4db94011d3 | 281 | * the configuration information for NOR module. |
sahilmgandhi | 18:6a4db94011d3 | 282 | * @param Timeout: Maximum timeout value |
sahilmgandhi | 18:6a4db94011d3 | 283 | * @retval None |
sahilmgandhi | 18:6a4db94011d3 | 284 | */ |
sahilmgandhi | 18:6a4db94011d3 | 285 | __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) |
sahilmgandhi | 18:6a4db94011d3 | 286 | { |
sahilmgandhi | 18:6a4db94011d3 | 287 | /* Prevent unused argument(s) compilation warning */ |
sahilmgandhi | 18:6a4db94011d3 | 288 | UNUSED(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 289 | /* NOTE : This function Should not be modified, when the callback is needed, |
sahilmgandhi | 18:6a4db94011d3 | 290 | the HAL_NOR_BspWait could be implemented in the user file |
sahilmgandhi | 18:6a4db94011d3 | 291 | */ |
sahilmgandhi | 18:6a4db94011d3 | 292 | } |
sahilmgandhi | 18:6a4db94011d3 | 293 | |
sahilmgandhi | 18:6a4db94011d3 | 294 | /** |
sahilmgandhi | 18:6a4db94011d3 | 295 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 296 | */ |
sahilmgandhi | 18:6a4db94011d3 | 297 | |
sahilmgandhi | 18:6a4db94011d3 | 298 | /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions |
sahilmgandhi | 18:6a4db94011d3 | 299 | * @brief Input Output and memory control functions |
sahilmgandhi | 18:6a4db94011d3 | 300 | * |
sahilmgandhi | 18:6a4db94011d3 | 301 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 302 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 303 | ##### NOR Input and Output functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 304 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 305 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 306 | This section provides functions allowing to use and control the NOR memory |
sahilmgandhi | 18:6a4db94011d3 | 307 | |
sahilmgandhi | 18:6a4db94011d3 | 308 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 309 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 310 | */ |
sahilmgandhi | 18:6a4db94011d3 | 311 | |
sahilmgandhi | 18:6a4db94011d3 | 312 | /** |
sahilmgandhi | 18:6a4db94011d3 | 313 | * @brief Read NOR flash IDs |
sahilmgandhi | 18:6a4db94011d3 | 314 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 315 | * @param pNOR_ID : pointer to NOR ID structure |
sahilmgandhi | 18:6a4db94011d3 | 316 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 317 | */ |
sahilmgandhi | 18:6a4db94011d3 | 318 | HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) |
sahilmgandhi | 18:6a4db94011d3 | 319 | { |
sahilmgandhi | 18:6a4db94011d3 | 320 | uint32_t deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 321 | |
sahilmgandhi | 18:6a4db94011d3 | 322 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 323 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 324 | |
sahilmgandhi | 18:6a4db94011d3 | 325 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 326 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 327 | { |
sahilmgandhi | 18:6a4db94011d3 | 328 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 329 | } |
sahilmgandhi | 18:6a4db94011d3 | 330 | |
sahilmgandhi | 18:6a4db94011d3 | 331 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 332 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 333 | { |
sahilmgandhi | 18:6a4db94011d3 | 334 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 335 | } |
sahilmgandhi | 18:6a4db94011d3 | 336 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 337 | { |
sahilmgandhi | 18:6a4db94011d3 | 338 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 339 | } |
sahilmgandhi | 18:6a4db94011d3 | 340 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 341 | { |
sahilmgandhi | 18:6a4db94011d3 | 342 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 343 | } |
sahilmgandhi | 18:6a4db94011d3 | 344 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 345 | { |
sahilmgandhi | 18:6a4db94011d3 | 346 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 347 | } |
sahilmgandhi | 18:6a4db94011d3 | 348 | |
sahilmgandhi | 18:6a4db94011d3 | 349 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 350 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 351 | |
sahilmgandhi | 18:6a4db94011d3 | 352 | /* Send read ID command */ |
sahilmgandhi | 18:6a4db94011d3 | 353 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
sahilmgandhi | 18:6a4db94011d3 | 354 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
sahilmgandhi | 18:6a4db94011d3 | 355 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); |
sahilmgandhi | 18:6a4db94011d3 | 356 | |
sahilmgandhi | 18:6a4db94011d3 | 357 | /* Read the NOR IDs */ |
sahilmgandhi | 18:6a4db94011d3 | 358 | pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); |
sahilmgandhi | 18:6a4db94011d3 | 359 | pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); |
sahilmgandhi | 18:6a4db94011d3 | 360 | pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); |
sahilmgandhi | 18:6a4db94011d3 | 361 | pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); |
sahilmgandhi | 18:6a4db94011d3 | 362 | |
sahilmgandhi | 18:6a4db94011d3 | 363 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 364 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 365 | |
sahilmgandhi | 18:6a4db94011d3 | 366 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 367 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 368 | |
sahilmgandhi | 18:6a4db94011d3 | 369 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 370 | } |
sahilmgandhi | 18:6a4db94011d3 | 371 | |
sahilmgandhi | 18:6a4db94011d3 | 372 | /** |
sahilmgandhi | 18:6a4db94011d3 | 373 | * @brief Returns the NOR memory to Read mode. |
sahilmgandhi | 18:6a4db94011d3 | 374 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 375 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 376 | */ |
sahilmgandhi | 18:6a4db94011d3 | 377 | HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) |
sahilmgandhi | 18:6a4db94011d3 | 378 | { |
sahilmgandhi | 18:6a4db94011d3 | 379 | uint32_t deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 380 | |
sahilmgandhi | 18:6a4db94011d3 | 381 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 382 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 383 | |
sahilmgandhi | 18:6a4db94011d3 | 384 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 385 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 386 | { |
sahilmgandhi | 18:6a4db94011d3 | 387 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 388 | } |
sahilmgandhi | 18:6a4db94011d3 | 389 | |
sahilmgandhi | 18:6a4db94011d3 | 390 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 391 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 392 | { |
sahilmgandhi | 18:6a4db94011d3 | 393 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 394 | } |
sahilmgandhi | 18:6a4db94011d3 | 395 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 396 | { |
sahilmgandhi | 18:6a4db94011d3 | 397 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 398 | } |
sahilmgandhi | 18:6a4db94011d3 | 399 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 400 | { |
sahilmgandhi | 18:6a4db94011d3 | 401 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 402 | } |
sahilmgandhi | 18:6a4db94011d3 | 403 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 404 | { |
sahilmgandhi | 18:6a4db94011d3 | 405 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 406 | } |
sahilmgandhi | 18:6a4db94011d3 | 407 | |
sahilmgandhi | 18:6a4db94011d3 | 408 | NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); |
sahilmgandhi | 18:6a4db94011d3 | 409 | |
sahilmgandhi | 18:6a4db94011d3 | 410 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 411 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 412 | |
sahilmgandhi | 18:6a4db94011d3 | 413 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 414 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 415 | |
sahilmgandhi | 18:6a4db94011d3 | 416 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 417 | } |
sahilmgandhi | 18:6a4db94011d3 | 418 | |
sahilmgandhi | 18:6a4db94011d3 | 419 | /** |
sahilmgandhi | 18:6a4db94011d3 | 420 | * @brief Read data from NOR memory |
sahilmgandhi | 18:6a4db94011d3 | 421 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 422 | * @param pAddress: pointer to Device address |
sahilmgandhi | 18:6a4db94011d3 | 423 | * @param pData : pointer to read data |
sahilmgandhi | 18:6a4db94011d3 | 424 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 425 | */ |
sahilmgandhi | 18:6a4db94011d3 | 426 | HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) |
sahilmgandhi | 18:6a4db94011d3 | 427 | { |
sahilmgandhi | 18:6a4db94011d3 | 428 | uint32_t deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 429 | |
sahilmgandhi | 18:6a4db94011d3 | 430 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 431 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 432 | |
sahilmgandhi | 18:6a4db94011d3 | 433 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 434 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 435 | { |
sahilmgandhi | 18:6a4db94011d3 | 436 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 437 | } |
sahilmgandhi | 18:6a4db94011d3 | 438 | |
sahilmgandhi | 18:6a4db94011d3 | 439 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 440 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 441 | { |
sahilmgandhi | 18:6a4db94011d3 | 442 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 443 | } |
sahilmgandhi | 18:6a4db94011d3 | 444 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 445 | { |
sahilmgandhi | 18:6a4db94011d3 | 446 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 447 | } |
sahilmgandhi | 18:6a4db94011d3 | 448 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 449 | { |
sahilmgandhi | 18:6a4db94011d3 | 450 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 451 | } |
sahilmgandhi | 18:6a4db94011d3 | 452 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 453 | { |
sahilmgandhi | 18:6a4db94011d3 | 454 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 455 | } |
sahilmgandhi | 18:6a4db94011d3 | 456 | |
sahilmgandhi | 18:6a4db94011d3 | 457 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 458 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 459 | |
sahilmgandhi | 18:6a4db94011d3 | 460 | /* Send read data command */ |
sahilmgandhi | 18:6a4db94011d3 | 461 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
sahilmgandhi | 18:6a4db94011d3 | 462 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
sahilmgandhi | 18:6a4db94011d3 | 463 | NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET); |
sahilmgandhi | 18:6a4db94011d3 | 464 | |
sahilmgandhi | 18:6a4db94011d3 | 465 | /* Read the data */ |
sahilmgandhi | 18:6a4db94011d3 | 466 | *pData = *(__IO uint32_t *)(uint32_t)pAddress; |
sahilmgandhi | 18:6a4db94011d3 | 467 | |
sahilmgandhi | 18:6a4db94011d3 | 468 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 469 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 470 | |
sahilmgandhi | 18:6a4db94011d3 | 471 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 472 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 473 | |
sahilmgandhi | 18:6a4db94011d3 | 474 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 475 | } |
sahilmgandhi | 18:6a4db94011d3 | 476 | |
sahilmgandhi | 18:6a4db94011d3 | 477 | /** |
sahilmgandhi | 18:6a4db94011d3 | 478 | * @brief Program data to NOR memory |
sahilmgandhi | 18:6a4db94011d3 | 479 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 480 | * @param pAddress: Device address |
sahilmgandhi | 18:6a4db94011d3 | 481 | * @param pData : pointer to the data to write |
sahilmgandhi | 18:6a4db94011d3 | 482 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 483 | */ |
sahilmgandhi | 18:6a4db94011d3 | 484 | HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) |
sahilmgandhi | 18:6a4db94011d3 | 485 | { |
sahilmgandhi | 18:6a4db94011d3 | 486 | uint32_t deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 487 | |
sahilmgandhi | 18:6a4db94011d3 | 488 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 489 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 490 | |
sahilmgandhi | 18:6a4db94011d3 | 491 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 492 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 493 | { |
sahilmgandhi | 18:6a4db94011d3 | 494 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 495 | } |
sahilmgandhi | 18:6a4db94011d3 | 496 | |
sahilmgandhi | 18:6a4db94011d3 | 497 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 498 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 499 | { |
sahilmgandhi | 18:6a4db94011d3 | 500 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 501 | } |
sahilmgandhi | 18:6a4db94011d3 | 502 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 503 | { |
sahilmgandhi | 18:6a4db94011d3 | 504 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 505 | } |
sahilmgandhi | 18:6a4db94011d3 | 506 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 507 | { |
sahilmgandhi | 18:6a4db94011d3 | 508 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 509 | } |
sahilmgandhi | 18:6a4db94011d3 | 510 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 511 | { |
sahilmgandhi | 18:6a4db94011d3 | 512 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 513 | } |
sahilmgandhi | 18:6a4db94011d3 | 514 | |
sahilmgandhi | 18:6a4db94011d3 | 515 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 516 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 517 | |
sahilmgandhi | 18:6a4db94011d3 | 518 | /* Send program data command */ |
sahilmgandhi | 18:6a4db94011d3 | 519 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
sahilmgandhi | 18:6a4db94011d3 | 520 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
sahilmgandhi | 18:6a4db94011d3 | 521 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); |
sahilmgandhi | 18:6a4db94011d3 | 522 | |
sahilmgandhi | 18:6a4db94011d3 | 523 | /* Write the data */ |
sahilmgandhi | 18:6a4db94011d3 | 524 | NOR_WRITE(pAddress, *pData); |
sahilmgandhi | 18:6a4db94011d3 | 525 | |
sahilmgandhi | 18:6a4db94011d3 | 526 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 527 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 528 | |
sahilmgandhi | 18:6a4db94011d3 | 529 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 530 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 531 | |
sahilmgandhi | 18:6a4db94011d3 | 532 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 533 | } |
sahilmgandhi | 18:6a4db94011d3 | 534 | |
sahilmgandhi | 18:6a4db94011d3 | 535 | /** |
sahilmgandhi | 18:6a4db94011d3 | 536 | * @brief Reads a half-word buffer from the NOR memory. |
sahilmgandhi | 18:6a4db94011d3 | 537 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 538 | * @param uwAddress: NOR memory internal address to read from. |
sahilmgandhi | 18:6a4db94011d3 | 539 | * @param pData: pointer to the buffer that receives the data read from the |
sahilmgandhi | 18:6a4db94011d3 | 540 | * NOR memory. |
sahilmgandhi | 18:6a4db94011d3 | 541 | * @param uwBufferSize : number of Half word to read. |
sahilmgandhi | 18:6a4db94011d3 | 542 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 543 | */ |
sahilmgandhi | 18:6a4db94011d3 | 544 | HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 545 | { |
sahilmgandhi | 18:6a4db94011d3 | 546 | uint32_t deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 547 | |
sahilmgandhi | 18:6a4db94011d3 | 548 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 549 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 550 | |
sahilmgandhi | 18:6a4db94011d3 | 551 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 552 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 553 | { |
sahilmgandhi | 18:6a4db94011d3 | 554 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 555 | } |
sahilmgandhi | 18:6a4db94011d3 | 556 | |
sahilmgandhi | 18:6a4db94011d3 | 557 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 558 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 559 | { |
sahilmgandhi | 18:6a4db94011d3 | 560 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 561 | } |
sahilmgandhi | 18:6a4db94011d3 | 562 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 563 | { |
sahilmgandhi | 18:6a4db94011d3 | 564 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 565 | } |
sahilmgandhi | 18:6a4db94011d3 | 566 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 567 | { |
sahilmgandhi | 18:6a4db94011d3 | 568 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 569 | } |
sahilmgandhi | 18:6a4db94011d3 | 570 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 571 | { |
sahilmgandhi | 18:6a4db94011d3 | 572 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 573 | } |
sahilmgandhi | 18:6a4db94011d3 | 574 | |
sahilmgandhi | 18:6a4db94011d3 | 575 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 576 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 577 | |
sahilmgandhi | 18:6a4db94011d3 | 578 | /* Send read data command */ |
sahilmgandhi | 18:6a4db94011d3 | 579 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
sahilmgandhi | 18:6a4db94011d3 | 580 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
sahilmgandhi | 18:6a4db94011d3 | 581 | NOR_WRITE(uwAddress, 0x00F0U); |
sahilmgandhi | 18:6a4db94011d3 | 582 | |
sahilmgandhi | 18:6a4db94011d3 | 583 | /* Read buffer */ |
sahilmgandhi | 18:6a4db94011d3 | 584 | while( uwBufferSize > 0U) |
sahilmgandhi | 18:6a4db94011d3 | 585 | { |
sahilmgandhi | 18:6a4db94011d3 | 586 | *pData++ = *(__IO uint16_t *)uwAddress; |
sahilmgandhi | 18:6a4db94011d3 | 587 | uwAddress += 2U; |
sahilmgandhi | 18:6a4db94011d3 | 588 | uwBufferSize--; |
sahilmgandhi | 18:6a4db94011d3 | 589 | } |
sahilmgandhi | 18:6a4db94011d3 | 590 | |
sahilmgandhi | 18:6a4db94011d3 | 591 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 592 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 593 | |
sahilmgandhi | 18:6a4db94011d3 | 594 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 595 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 596 | |
sahilmgandhi | 18:6a4db94011d3 | 597 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 598 | } |
sahilmgandhi | 18:6a4db94011d3 | 599 | |
sahilmgandhi | 18:6a4db94011d3 | 600 | /** |
sahilmgandhi | 18:6a4db94011d3 | 601 | * @brief Writes a half-word buffer to the NOR memory. This function must be used |
sahilmgandhi | 18:6a4db94011d3 | 602 | only with S29GL128P NOR memory. |
sahilmgandhi | 18:6a4db94011d3 | 603 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 604 | * @param uwAddress: NOR memory internal start write address |
sahilmgandhi | 18:6a4db94011d3 | 605 | * @param pData: pointer to source data buffer. |
sahilmgandhi | 18:6a4db94011d3 | 606 | * @param uwBufferSize: Size of the buffer to write |
sahilmgandhi | 18:6a4db94011d3 | 607 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 608 | */ |
sahilmgandhi | 18:6a4db94011d3 | 609 | HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) |
sahilmgandhi | 18:6a4db94011d3 | 610 | { |
sahilmgandhi | 18:6a4db94011d3 | 611 | uint16_t * p_currentaddress = (uint16_t *)NULL; |
sahilmgandhi | 18:6a4db94011d3 | 612 | uint16_t * p_endaddress = (uint16_t *)NULL; |
sahilmgandhi | 18:6a4db94011d3 | 613 | uint32_t lastloadedaddress = 0U, deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 614 | |
sahilmgandhi | 18:6a4db94011d3 | 615 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 616 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 617 | |
sahilmgandhi | 18:6a4db94011d3 | 618 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 619 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 620 | { |
sahilmgandhi | 18:6a4db94011d3 | 621 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 622 | } |
sahilmgandhi | 18:6a4db94011d3 | 623 | |
sahilmgandhi | 18:6a4db94011d3 | 624 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 625 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 626 | { |
sahilmgandhi | 18:6a4db94011d3 | 627 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 628 | } |
sahilmgandhi | 18:6a4db94011d3 | 629 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 630 | { |
sahilmgandhi | 18:6a4db94011d3 | 631 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 632 | } |
sahilmgandhi | 18:6a4db94011d3 | 633 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 634 | { |
sahilmgandhi | 18:6a4db94011d3 | 635 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 636 | } |
sahilmgandhi | 18:6a4db94011d3 | 637 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 638 | { |
sahilmgandhi | 18:6a4db94011d3 | 639 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 640 | } |
sahilmgandhi | 18:6a4db94011d3 | 641 | |
sahilmgandhi | 18:6a4db94011d3 | 642 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 643 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 644 | |
sahilmgandhi | 18:6a4db94011d3 | 645 | /* Initialize variables */ |
sahilmgandhi | 18:6a4db94011d3 | 646 | p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); |
sahilmgandhi | 18:6a4db94011d3 | 647 | p_endaddress = p_currentaddress + (uwBufferSize-1U); |
sahilmgandhi | 18:6a4db94011d3 | 648 | lastloadedaddress = (uint32_t)(uwAddress); |
sahilmgandhi | 18:6a4db94011d3 | 649 | |
sahilmgandhi | 18:6a4db94011d3 | 650 | /* Issue unlock command sequence */ |
sahilmgandhi | 18:6a4db94011d3 | 651 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
sahilmgandhi | 18:6a4db94011d3 | 652 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
sahilmgandhi | 18:6a4db94011d3 | 653 | |
sahilmgandhi | 18:6a4db94011d3 | 654 | /* Write Buffer Load Command */ |
sahilmgandhi | 18:6a4db94011d3 | 655 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); |
sahilmgandhi | 18:6a4db94011d3 | 656 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U)); |
sahilmgandhi | 18:6a4db94011d3 | 657 | |
sahilmgandhi | 18:6a4db94011d3 | 658 | /* Load Data into NOR Buffer */ |
sahilmgandhi | 18:6a4db94011d3 | 659 | while(p_currentaddress <= p_endaddress) |
sahilmgandhi | 18:6a4db94011d3 | 660 | { |
sahilmgandhi | 18:6a4db94011d3 | 661 | /* Store last loaded address & data value (for polling) */ |
sahilmgandhi | 18:6a4db94011d3 | 662 | lastloadedaddress = (uint32_t)p_currentaddress; |
sahilmgandhi | 18:6a4db94011d3 | 663 | |
sahilmgandhi | 18:6a4db94011d3 | 664 | NOR_WRITE(p_currentaddress, *pData++); |
sahilmgandhi | 18:6a4db94011d3 | 665 | |
sahilmgandhi | 18:6a4db94011d3 | 666 | p_currentaddress ++; |
sahilmgandhi | 18:6a4db94011d3 | 667 | } |
sahilmgandhi | 18:6a4db94011d3 | 668 | |
sahilmgandhi | 18:6a4db94011d3 | 669 | NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); |
sahilmgandhi | 18:6a4db94011d3 | 670 | |
sahilmgandhi | 18:6a4db94011d3 | 671 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 672 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 673 | |
sahilmgandhi | 18:6a4db94011d3 | 674 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 675 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 676 | |
sahilmgandhi | 18:6a4db94011d3 | 677 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 678 | |
sahilmgandhi | 18:6a4db94011d3 | 679 | } |
sahilmgandhi | 18:6a4db94011d3 | 680 | |
sahilmgandhi | 18:6a4db94011d3 | 681 | /** |
sahilmgandhi | 18:6a4db94011d3 | 682 | * @brief Erase the specified block of the NOR memory |
sahilmgandhi | 18:6a4db94011d3 | 683 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 684 | * @param BlockAddress : Block to erase address |
sahilmgandhi | 18:6a4db94011d3 | 685 | * @param Address: Device address |
sahilmgandhi | 18:6a4db94011d3 | 686 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 687 | */ |
sahilmgandhi | 18:6a4db94011d3 | 688 | HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) |
sahilmgandhi | 18:6a4db94011d3 | 689 | { |
sahilmgandhi | 18:6a4db94011d3 | 690 | uint32_t deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 691 | |
sahilmgandhi | 18:6a4db94011d3 | 692 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 693 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 694 | |
sahilmgandhi | 18:6a4db94011d3 | 695 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 696 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 697 | { |
sahilmgandhi | 18:6a4db94011d3 | 698 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 699 | } |
sahilmgandhi | 18:6a4db94011d3 | 700 | |
sahilmgandhi | 18:6a4db94011d3 | 701 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 702 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 703 | { |
sahilmgandhi | 18:6a4db94011d3 | 704 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 705 | } |
sahilmgandhi | 18:6a4db94011d3 | 706 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 707 | { |
sahilmgandhi | 18:6a4db94011d3 | 708 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 709 | } |
sahilmgandhi | 18:6a4db94011d3 | 710 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 711 | { |
sahilmgandhi | 18:6a4db94011d3 | 712 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 713 | } |
sahilmgandhi | 18:6a4db94011d3 | 714 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 715 | { |
sahilmgandhi | 18:6a4db94011d3 | 716 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 717 | } |
sahilmgandhi | 18:6a4db94011d3 | 718 | |
sahilmgandhi | 18:6a4db94011d3 | 719 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 720 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 721 | |
sahilmgandhi | 18:6a4db94011d3 | 722 | /* Send block erase command sequence */ |
sahilmgandhi | 18:6a4db94011d3 | 723 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
sahilmgandhi | 18:6a4db94011d3 | 724 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
sahilmgandhi | 18:6a4db94011d3 | 725 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); |
sahilmgandhi | 18:6a4db94011d3 | 726 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); |
sahilmgandhi | 18:6a4db94011d3 | 727 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); |
sahilmgandhi | 18:6a4db94011d3 | 728 | NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); |
sahilmgandhi | 18:6a4db94011d3 | 729 | |
sahilmgandhi | 18:6a4db94011d3 | 730 | /* Check the NOR memory status and update the controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 731 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 732 | |
sahilmgandhi | 18:6a4db94011d3 | 733 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 734 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 735 | |
sahilmgandhi | 18:6a4db94011d3 | 736 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 737 | |
sahilmgandhi | 18:6a4db94011d3 | 738 | } |
sahilmgandhi | 18:6a4db94011d3 | 739 | |
sahilmgandhi | 18:6a4db94011d3 | 740 | /** |
sahilmgandhi | 18:6a4db94011d3 | 741 | * @brief Erase the entire NOR chip. |
sahilmgandhi | 18:6a4db94011d3 | 742 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 743 | * @param Address : Device address |
sahilmgandhi | 18:6a4db94011d3 | 744 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 745 | */ |
sahilmgandhi | 18:6a4db94011d3 | 746 | HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) |
sahilmgandhi | 18:6a4db94011d3 | 747 | { |
sahilmgandhi | 18:6a4db94011d3 | 748 | uint32_t deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 749 | |
sahilmgandhi | 18:6a4db94011d3 | 750 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 751 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 752 | |
sahilmgandhi | 18:6a4db94011d3 | 753 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 754 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 755 | { |
sahilmgandhi | 18:6a4db94011d3 | 756 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 757 | } |
sahilmgandhi | 18:6a4db94011d3 | 758 | |
sahilmgandhi | 18:6a4db94011d3 | 759 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 760 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 761 | { |
sahilmgandhi | 18:6a4db94011d3 | 762 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 763 | } |
sahilmgandhi | 18:6a4db94011d3 | 764 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 765 | { |
sahilmgandhi | 18:6a4db94011d3 | 766 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 767 | } |
sahilmgandhi | 18:6a4db94011d3 | 768 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 769 | { |
sahilmgandhi | 18:6a4db94011d3 | 770 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 771 | } |
sahilmgandhi | 18:6a4db94011d3 | 772 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 773 | { |
sahilmgandhi | 18:6a4db94011d3 | 774 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 775 | } |
sahilmgandhi | 18:6a4db94011d3 | 776 | |
sahilmgandhi | 18:6a4db94011d3 | 777 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 778 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 779 | |
sahilmgandhi | 18:6a4db94011d3 | 780 | /* Send NOR chip erase command sequence */ |
sahilmgandhi | 18:6a4db94011d3 | 781 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); |
sahilmgandhi | 18:6a4db94011d3 | 782 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); |
sahilmgandhi | 18:6a4db94011d3 | 783 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); |
sahilmgandhi | 18:6a4db94011d3 | 784 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); |
sahilmgandhi | 18:6a4db94011d3 | 785 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); |
sahilmgandhi | 18:6a4db94011d3 | 786 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); |
sahilmgandhi | 18:6a4db94011d3 | 787 | |
sahilmgandhi | 18:6a4db94011d3 | 788 | /* Check the NOR memory status and update the controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 789 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 790 | |
sahilmgandhi | 18:6a4db94011d3 | 791 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 792 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 793 | |
sahilmgandhi | 18:6a4db94011d3 | 794 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 795 | } |
sahilmgandhi | 18:6a4db94011d3 | 796 | |
sahilmgandhi | 18:6a4db94011d3 | 797 | /** |
sahilmgandhi | 18:6a4db94011d3 | 798 | * @brief Read NOR flash CFI IDs |
sahilmgandhi | 18:6a4db94011d3 | 799 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 800 | * @param pNOR_CFI : pointer to NOR CFI IDs structure |
sahilmgandhi | 18:6a4db94011d3 | 801 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 802 | */ |
sahilmgandhi | 18:6a4db94011d3 | 803 | HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) |
sahilmgandhi | 18:6a4db94011d3 | 804 | { |
sahilmgandhi | 18:6a4db94011d3 | 805 | uint32_t deviceaddress = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 806 | |
sahilmgandhi | 18:6a4db94011d3 | 807 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 808 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 809 | |
sahilmgandhi | 18:6a4db94011d3 | 810 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 811 | if(hnor->State == HAL_NOR_STATE_BUSY) |
sahilmgandhi | 18:6a4db94011d3 | 812 | { |
sahilmgandhi | 18:6a4db94011d3 | 813 | return HAL_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 814 | } |
sahilmgandhi | 18:6a4db94011d3 | 815 | |
sahilmgandhi | 18:6a4db94011d3 | 816 | /* Select the NOR device address */ |
sahilmgandhi | 18:6a4db94011d3 | 817 | if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) |
sahilmgandhi | 18:6a4db94011d3 | 818 | { |
sahilmgandhi | 18:6a4db94011d3 | 819 | deviceaddress = NOR_MEMORY_ADRESS1; |
sahilmgandhi | 18:6a4db94011d3 | 820 | } |
sahilmgandhi | 18:6a4db94011d3 | 821 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) |
sahilmgandhi | 18:6a4db94011d3 | 822 | { |
sahilmgandhi | 18:6a4db94011d3 | 823 | deviceaddress = NOR_MEMORY_ADRESS2; |
sahilmgandhi | 18:6a4db94011d3 | 824 | } |
sahilmgandhi | 18:6a4db94011d3 | 825 | else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) |
sahilmgandhi | 18:6a4db94011d3 | 826 | { |
sahilmgandhi | 18:6a4db94011d3 | 827 | deviceaddress = NOR_MEMORY_ADRESS3; |
sahilmgandhi | 18:6a4db94011d3 | 828 | } |
sahilmgandhi | 18:6a4db94011d3 | 829 | else /* FMC_NORSRAM_BANK4 */ |
sahilmgandhi | 18:6a4db94011d3 | 830 | { |
sahilmgandhi | 18:6a4db94011d3 | 831 | deviceaddress = NOR_MEMORY_ADRESS4; |
sahilmgandhi | 18:6a4db94011d3 | 832 | } |
sahilmgandhi | 18:6a4db94011d3 | 833 | |
sahilmgandhi | 18:6a4db94011d3 | 834 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 835 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 836 | |
sahilmgandhi | 18:6a4db94011d3 | 837 | /* Send read CFI query command */ |
sahilmgandhi | 18:6a4db94011d3 | 838 | NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); |
sahilmgandhi | 18:6a4db94011d3 | 839 | |
sahilmgandhi | 18:6a4db94011d3 | 840 | /* read the NOR CFI information */ |
sahilmgandhi | 18:6a4db94011d3 | 841 | pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); |
sahilmgandhi | 18:6a4db94011d3 | 842 | pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); |
sahilmgandhi | 18:6a4db94011d3 | 843 | pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); |
sahilmgandhi | 18:6a4db94011d3 | 844 | pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); |
sahilmgandhi | 18:6a4db94011d3 | 845 | |
sahilmgandhi | 18:6a4db94011d3 | 846 | /* Check the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 847 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 848 | |
sahilmgandhi | 18:6a4db94011d3 | 849 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 850 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 851 | |
sahilmgandhi | 18:6a4db94011d3 | 852 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 853 | } |
sahilmgandhi | 18:6a4db94011d3 | 854 | |
sahilmgandhi | 18:6a4db94011d3 | 855 | /** |
sahilmgandhi | 18:6a4db94011d3 | 856 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 857 | */ |
sahilmgandhi | 18:6a4db94011d3 | 858 | |
sahilmgandhi | 18:6a4db94011d3 | 859 | /** @defgroup NOR_Exported_Functions_Group3 Control functions |
sahilmgandhi | 18:6a4db94011d3 | 860 | * @brief management functions |
sahilmgandhi | 18:6a4db94011d3 | 861 | * |
sahilmgandhi | 18:6a4db94011d3 | 862 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 863 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 864 | ##### NOR Control functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 865 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 866 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 867 | This subsection provides a set of functions allowing to control dynamically |
sahilmgandhi | 18:6a4db94011d3 | 868 | the NOR interface. |
sahilmgandhi | 18:6a4db94011d3 | 869 | |
sahilmgandhi | 18:6a4db94011d3 | 870 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 871 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 872 | */ |
sahilmgandhi | 18:6a4db94011d3 | 873 | |
sahilmgandhi | 18:6a4db94011d3 | 874 | /** |
sahilmgandhi | 18:6a4db94011d3 | 875 | * @brief Enables dynamically NOR write operation. |
sahilmgandhi | 18:6a4db94011d3 | 876 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 877 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 878 | */ |
sahilmgandhi | 18:6a4db94011d3 | 879 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) |
sahilmgandhi | 18:6a4db94011d3 | 880 | { |
sahilmgandhi | 18:6a4db94011d3 | 881 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 882 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 883 | |
sahilmgandhi | 18:6a4db94011d3 | 884 | /* Enable write operation */ |
sahilmgandhi | 18:6a4db94011d3 | 885 | FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); |
sahilmgandhi | 18:6a4db94011d3 | 886 | |
sahilmgandhi | 18:6a4db94011d3 | 887 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 888 | hnor->State = HAL_NOR_STATE_READY; |
sahilmgandhi | 18:6a4db94011d3 | 889 | |
sahilmgandhi | 18:6a4db94011d3 | 890 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 891 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 892 | |
sahilmgandhi | 18:6a4db94011d3 | 893 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 894 | } |
sahilmgandhi | 18:6a4db94011d3 | 895 | |
sahilmgandhi | 18:6a4db94011d3 | 896 | /** |
sahilmgandhi | 18:6a4db94011d3 | 897 | * @brief Disables dynamically NOR write operation. |
sahilmgandhi | 18:6a4db94011d3 | 898 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 899 | * @retval HAL status |
sahilmgandhi | 18:6a4db94011d3 | 900 | */ |
sahilmgandhi | 18:6a4db94011d3 | 901 | HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) |
sahilmgandhi | 18:6a4db94011d3 | 902 | { |
sahilmgandhi | 18:6a4db94011d3 | 903 | /* Process Locked */ |
sahilmgandhi | 18:6a4db94011d3 | 904 | __HAL_LOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 905 | |
sahilmgandhi | 18:6a4db94011d3 | 906 | /* Update the SRAM controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 907 | hnor->State = HAL_NOR_STATE_BUSY; |
sahilmgandhi | 18:6a4db94011d3 | 908 | |
sahilmgandhi | 18:6a4db94011d3 | 909 | /* Disable write operation */ |
sahilmgandhi | 18:6a4db94011d3 | 910 | FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); |
sahilmgandhi | 18:6a4db94011d3 | 911 | |
sahilmgandhi | 18:6a4db94011d3 | 912 | /* Update the NOR controller state */ |
sahilmgandhi | 18:6a4db94011d3 | 913 | hnor->State = HAL_NOR_STATE_PROTECTED; |
sahilmgandhi | 18:6a4db94011d3 | 914 | |
sahilmgandhi | 18:6a4db94011d3 | 915 | /* Process unlocked */ |
sahilmgandhi | 18:6a4db94011d3 | 916 | __HAL_UNLOCK(hnor); |
sahilmgandhi | 18:6a4db94011d3 | 917 | |
sahilmgandhi | 18:6a4db94011d3 | 918 | return HAL_OK; |
sahilmgandhi | 18:6a4db94011d3 | 919 | } |
sahilmgandhi | 18:6a4db94011d3 | 920 | |
sahilmgandhi | 18:6a4db94011d3 | 921 | /** |
sahilmgandhi | 18:6a4db94011d3 | 922 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 923 | */ |
sahilmgandhi | 18:6a4db94011d3 | 924 | |
sahilmgandhi | 18:6a4db94011d3 | 925 | /** @defgroup NOR_Exported_Functions_Group4 State functions |
sahilmgandhi | 18:6a4db94011d3 | 926 | * @brief Peripheral State functions |
sahilmgandhi | 18:6a4db94011d3 | 927 | * |
sahilmgandhi | 18:6a4db94011d3 | 928 | @verbatim |
sahilmgandhi | 18:6a4db94011d3 | 929 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 930 | ##### NOR State functions ##### |
sahilmgandhi | 18:6a4db94011d3 | 931 | ============================================================================== |
sahilmgandhi | 18:6a4db94011d3 | 932 | [..] |
sahilmgandhi | 18:6a4db94011d3 | 933 | This subsection permits to get in run-time the status of the NOR controller |
sahilmgandhi | 18:6a4db94011d3 | 934 | and the data flow. |
sahilmgandhi | 18:6a4db94011d3 | 935 | |
sahilmgandhi | 18:6a4db94011d3 | 936 | @endverbatim |
sahilmgandhi | 18:6a4db94011d3 | 937 | * @{ |
sahilmgandhi | 18:6a4db94011d3 | 938 | */ |
sahilmgandhi | 18:6a4db94011d3 | 939 | |
sahilmgandhi | 18:6a4db94011d3 | 940 | /** |
sahilmgandhi | 18:6a4db94011d3 | 941 | * @brief return the NOR controller state |
sahilmgandhi | 18:6a4db94011d3 | 942 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 943 | * @retval NOR controller state |
sahilmgandhi | 18:6a4db94011d3 | 944 | */ |
sahilmgandhi | 18:6a4db94011d3 | 945 | HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) |
sahilmgandhi | 18:6a4db94011d3 | 946 | { |
sahilmgandhi | 18:6a4db94011d3 | 947 | return hnor->State; |
sahilmgandhi | 18:6a4db94011d3 | 948 | } |
sahilmgandhi | 18:6a4db94011d3 | 949 | |
sahilmgandhi | 18:6a4db94011d3 | 950 | /** |
sahilmgandhi | 18:6a4db94011d3 | 951 | * @brief Returns the NOR operation status. |
sahilmgandhi | 18:6a4db94011d3 | 952 | * @param hnor: pointer to the NOR handle |
sahilmgandhi | 18:6a4db94011d3 | 953 | * @param Address: Device address |
sahilmgandhi | 18:6a4db94011d3 | 954 | * @param Timeout: NOR programming Timeout |
sahilmgandhi | 18:6a4db94011d3 | 955 | * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR |
sahilmgandhi | 18:6a4db94011d3 | 956 | * or HAL_NOR_STATUS_TIMEOUT |
sahilmgandhi | 18:6a4db94011d3 | 957 | */ |
sahilmgandhi | 18:6a4db94011d3 | 958 | HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) |
sahilmgandhi | 18:6a4db94011d3 | 959 | { |
sahilmgandhi | 18:6a4db94011d3 | 960 | HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; |
sahilmgandhi | 18:6a4db94011d3 | 961 | uint16_t tmpSR1 = 0U, tmpSR2 = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 962 | uint32_t tickstart = 0U; |
sahilmgandhi | 18:6a4db94011d3 | 963 | |
sahilmgandhi | 18:6a4db94011d3 | 964 | /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 965 | HAL_NOR_MspWait(hnor, Timeout); |
sahilmgandhi | 18:6a4db94011d3 | 966 | |
sahilmgandhi | 18:6a4db94011d3 | 967 | /* Get the NOR memory operation status -------------------------------------*/ |
sahilmgandhi | 18:6a4db94011d3 | 968 | |
sahilmgandhi | 18:6a4db94011d3 | 969 | /* Get tick */ |
sahilmgandhi | 18:6a4db94011d3 | 970 | tickstart = HAL_GetTick(); |
sahilmgandhi | 18:6a4db94011d3 | 971 | while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT)) |
sahilmgandhi | 18:6a4db94011d3 | 972 | { |
sahilmgandhi | 18:6a4db94011d3 | 973 | /* Check for the Timeout */ |
sahilmgandhi | 18:6a4db94011d3 | 974 | if(Timeout != HAL_MAX_DELAY) |
sahilmgandhi | 18:6a4db94011d3 | 975 | { |
sahilmgandhi | 18:6a4db94011d3 | 976 | if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) |
sahilmgandhi | 18:6a4db94011d3 | 977 | { |
sahilmgandhi | 18:6a4db94011d3 | 978 | status = HAL_NOR_STATUS_TIMEOUT; |
sahilmgandhi | 18:6a4db94011d3 | 979 | } |
sahilmgandhi | 18:6a4db94011d3 | 980 | } |
sahilmgandhi | 18:6a4db94011d3 | 981 | |
sahilmgandhi | 18:6a4db94011d3 | 982 | /* Read NOR status register (DQ6 and DQ5) */ |
sahilmgandhi | 18:6a4db94011d3 | 983 | tmpSR1 = *(__IO uint16_t *)Address; |
sahilmgandhi | 18:6a4db94011d3 | 984 | tmpSR2 = *(__IO uint16_t *)Address; |
sahilmgandhi | 18:6a4db94011d3 | 985 | |
sahilmgandhi | 18:6a4db94011d3 | 986 | /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ |
sahilmgandhi | 18:6a4db94011d3 | 987 | if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) |
sahilmgandhi | 18:6a4db94011d3 | 988 | { |
sahilmgandhi | 18:6a4db94011d3 | 989 | return HAL_NOR_STATUS_SUCCESS ; |
sahilmgandhi | 18:6a4db94011d3 | 990 | } |
sahilmgandhi | 18:6a4db94011d3 | 991 | |
sahilmgandhi | 18:6a4db94011d3 | 992 | if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) |
sahilmgandhi | 18:6a4db94011d3 | 993 | { |
sahilmgandhi | 18:6a4db94011d3 | 994 | status = HAL_NOR_STATUS_ONGOING; |
sahilmgandhi | 18:6a4db94011d3 | 995 | } |
sahilmgandhi | 18:6a4db94011d3 | 996 | |
sahilmgandhi | 18:6a4db94011d3 | 997 | tmpSR1 = *(__IO uint16_t *)Address; |
sahilmgandhi | 18:6a4db94011d3 | 998 | tmpSR2 = *(__IO uint16_t *)Address; |
sahilmgandhi | 18:6a4db94011d3 | 999 | |
sahilmgandhi | 18:6a4db94011d3 | 1000 | /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ |
sahilmgandhi | 18:6a4db94011d3 | 1001 | if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) |
sahilmgandhi | 18:6a4db94011d3 | 1002 | { |
sahilmgandhi | 18:6a4db94011d3 | 1003 | return HAL_NOR_STATUS_SUCCESS; |
sahilmgandhi | 18:6a4db94011d3 | 1004 | } |
sahilmgandhi | 18:6a4db94011d3 | 1005 | if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) |
sahilmgandhi | 18:6a4db94011d3 | 1006 | { |
sahilmgandhi | 18:6a4db94011d3 | 1007 | return HAL_NOR_STATUS_ERROR; |
sahilmgandhi | 18:6a4db94011d3 | 1008 | } |
sahilmgandhi | 18:6a4db94011d3 | 1009 | } |
sahilmgandhi | 18:6a4db94011d3 | 1010 | |
sahilmgandhi | 18:6a4db94011d3 | 1011 | /* Return the operation status */ |
sahilmgandhi | 18:6a4db94011d3 | 1012 | return status; |
sahilmgandhi | 18:6a4db94011d3 | 1013 | } |
sahilmgandhi | 18:6a4db94011d3 | 1014 | |
sahilmgandhi | 18:6a4db94011d3 | 1015 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1016 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1017 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1018 | |
sahilmgandhi | 18:6a4db94011d3 | 1019 | |
sahilmgandhi | 18:6a4db94011d3 | 1020 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1021 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1022 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1023 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ |
sahilmgandhi | 18:6a4db94011d3 | 1024 | STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
sahilmgandhi | 18:6a4db94011d3 | 1025 | STM32F479xx || STM32F412Zx || STM32F412Vx */ |
sahilmgandhi | 18:6a4db94011d3 | 1026 | #endif /* HAL_NOR_MODULE_ENABLED */ |
sahilmgandhi | 18:6a4db94011d3 | 1027 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1028 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1029 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1030 | |
sahilmgandhi | 18:6a4db94011d3 | 1031 | /** |
sahilmgandhi | 18:6a4db94011d3 | 1032 | * @} |
sahilmgandhi | 18:6a4db94011d3 | 1033 | */ |
sahilmgandhi | 18:6a4db94011d3 | 1034 | |
sahilmgandhi | 18:6a4db94011d3 | 1035 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |