MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_nand.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief NAND HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides a generic firmware to drive NAND memories mounted
sahilmgandhi 18:6a4db94011d3 9 * as external device.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 @verbatim
sahilmgandhi 18:6a4db94011d3 12 ==============================================================================
sahilmgandhi 18:6a4db94011d3 13 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 14 ==============================================================================
sahilmgandhi 18:6a4db94011d3 15 [..]
sahilmgandhi 18:6a4db94011d3 16 This driver is a generic layered driver which contains a set of APIs used to
sahilmgandhi 18:6a4db94011d3 17 control NAND flash memories. It uses the FMC/FSMC layer functions to interface
sahilmgandhi 18:6a4db94011d3 18 with NAND devices. This driver is used as follows:
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
sahilmgandhi 18:6a4db94011d3 21 with control and timing parameters for both common and attribute spaces.
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 (+) Read NAND flash memory maker and device IDs using the function
sahilmgandhi 18:6a4db94011d3 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
sahilmgandhi 18:6a4db94011d3 25 structure declared by the function caller.
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 (+) Access NAND flash memory by read/write operations using the functions
sahilmgandhi 18:6a4db94011d3 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
sahilmgandhi 18:6a4db94011d3 29 to read/write page(s)/spare area(s). These functions use specific device
sahilmgandhi 18:6a4db94011d3 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
sahilmgandhi 18:6a4db94011d3 31 structure. The read/write address information is contained by the Nand_Address_Typedef
sahilmgandhi 18:6a4db94011d3 32 structure passed as parameter.
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
sahilmgandhi 18:6a4db94011d3 35
sahilmgandhi 18:6a4db94011d3 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
sahilmgandhi 18:6a4db94011d3 37 The erase block address information is contained in the Nand_Address_Typedef
sahilmgandhi 18:6a4db94011d3 38 structure passed as parameter.
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
sahilmgandhi 18:6a4db94011d3 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
sahilmgandhi 18:6a4db94011d3 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 (+) You can monitor the NAND device HAL state by calling the function
sahilmgandhi 18:6a4db94011d3 47 HAL_NAND_GetState()
sahilmgandhi 18:6a4db94011d3 48
sahilmgandhi 18:6a4db94011d3 49 [..]
sahilmgandhi 18:6a4db94011d3 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
sahilmgandhi 18:6a4db94011d3 51 If a NAND flash device contains different operations and/or implementations,
sahilmgandhi 18:6a4db94011d3 52 it should be implemented separately.
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 @endverbatim
sahilmgandhi 18:6a4db94011d3 55 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 56 * @attention
sahilmgandhi 18:6a4db94011d3 57 *
sahilmgandhi 18:6a4db94011d3 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 59 *
sahilmgandhi 18:6a4db94011d3 60 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 61 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 62 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 63 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 65 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 66 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 68 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 69 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 70 *
sahilmgandhi 18:6a4db94011d3 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 81 *
sahilmgandhi 18:6a4db94011d3 82 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 83 */
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 86 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 89 * @{
sahilmgandhi 18:6a4db94011d3 90 */
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 #ifdef HAL_NAND_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
sahilmgandhi 18:6a4db94011d3 96 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 97 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 /** @defgroup NAND NAND
sahilmgandhi 18:6a4db94011d3 100 * @brief NAND HAL module driver
sahilmgandhi 18:6a4db94011d3 101 * @{
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 105 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 106 /** @defgroup NAND_Private_Constants NAND Private Constants
sahilmgandhi 18:6a4db94011d3 107 * @{
sahilmgandhi 18:6a4db94011d3 108 */
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /**
sahilmgandhi 18:6a4db94011d3 111 * @}
sahilmgandhi 18:6a4db94011d3 112 */
sahilmgandhi 18:6a4db94011d3 113
sahilmgandhi 18:6a4db94011d3 114 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 115 /** @defgroup NAND_Private_Macros NAND Private Macros
sahilmgandhi 18:6a4db94011d3 116 * @{
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 /**
sahilmgandhi 18:6a4db94011d3 120 * @}
sahilmgandhi 18:6a4db94011d3 121 */
sahilmgandhi 18:6a4db94011d3 122 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 123 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 124 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 125 /** @defgroup NAND_Exported_Functions NAND Exported Functions
sahilmgandhi 18:6a4db94011d3 126 * @{
sahilmgandhi 18:6a4db94011d3 127 */
sahilmgandhi 18:6a4db94011d3 128
sahilmgandhi 18:6a4db94011d3 129 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 130 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 131 *
sahilmgandhi 18:6a4db94011d3 132 @verbatim
sahilmgandhi 18:6a4db94011d3 133 ==============================================================================
sahilmgandhi 18:6a4db94011d3 134 ##### NAND Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 135 ==============================================================================
sahilmgandhi 18:6a4db94011d3 136 [..]
sahilmgandhi 18:6a4db94011d3 137 This section provides functions allowing to initialize/de-initialize
sahilmgandhi 18:6a4db94011d3 138 the NAND memory
sahilmgandhi 18:6a4db94011d3 139
sahilmgandhi 18:6a4db94011d3 140 @endverbatim
sahilmgandhi 18:6a4db94011d3 141 * @{
sahilmgandhi 18:6a4db94011d3 142 */
sahilmgandhi 18:6a4db94011d3 143
sahilmgandhi 18:6a4db94011d3 144 /**
sahilmgandhi 18:6a4db94011d3 145 * @brief Perform NAND memory Initialization sequence
sahilmgandhi 18:6a4db94011d3 146 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 147 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 148 * @param ComSpace_Timing: pointer to Common space timing structure
sahilmgandhi 18:6a4db94011d3 149 * @param AttSpace_Timing: pointer to Attribute space timing structure
sahilmgandhi 18:6a4db94011d3 150 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
sahilmgandhi 18:6a4db94011d3 153 {
sahilmgandhi 18:6a4db94011d3 154 /* Check the NAND handle state */
sahilmgandhi 18:6a4db94011d3 155 if(hnand == NULL)
sahilmgandhi 18:6a4db94011d3 156 {
sahilmgandhi 18:6a4db94011d3 157 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 if(hnand->State == HAL_NAND_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 161 {
sahilmgandhi 18:6a4db94011d3 162 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 163 hnand->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 164 /* Initialize the low level hardware (MSP) */
sahilmgandhi 18:6a4db94011d3 165 HAL_NAND_MspInit(hnand);
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167
sahilmgandhi 18:6a4db94011d3 168 /* Initialize NAND control Interface */
sahilmgandhi 18:6a4db94011d3 169 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /* Initialize NAND common space timing Interface */
sahilmgandhi 18:6a4db94011d3 172 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 /* Initialize NAND attribute space timing Interface */
sahilmgandhi 18:6a4db94011d3 175 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 176
sahilmgandhi 18:6a4db94011d3 177 /* Enable the NAND device */
sahilmgandhi 18:6a4db94011d3 178 __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 181 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 184 }
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 /**
sahilmgandhi 18:6a4db94011d3 187 * @brief Perform NAND memory De-Initialization sequence
sahilmgandhi 18:6a4db94011d3 188 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 189 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 190 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 191 */
sahilmgandhi 18:6a4db94011d3 192 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 193 {
sahilmgandhi 18:6a4db94011d3 194 /* Initialize the low level hardware (MSP) */
sahilmgandhi 18:6a4db94011d3 195 HAL_NAND_MspDeInit(hnand);
sahilmgandhi 18:6a4db94011d3 196
sahilmgandhi 18:6a4db94011d3 197 /* Configure the NAND registers with their reset values */
sahilmgandhi 18:6a4db94011d3 198 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /* Reset the NAND controller state */
sahilmgandhi 18:6a4db94011d3 201 hnand->State = HAL_NAND_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 202
sahilmgandhi 18:6a4db94011d3 203 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 204 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 207 }
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /**
sahilmgandhi 18:6a4db94011d3 210 * @brief NAND MSP Init
sahilmgandhi 18:6a4db94011d3 211 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 212 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 213 * @retval None
sahilmgandhi 18:6a4db94011d3 214 */
sahilmgandhi 18:6a4db94011d3 215 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 216 {
sahilmgandhi 18:6a4db94011d3 217 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 218 UNUSED(hnand);
sahilmgandhi 18:6a4db94011d3 219 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 220 the HAL_NAND_MspInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 221 */
sahilmgandhi 18:6a4db94011d3 222 }
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 /**
sahilmgandhi 18:6a4db94011d3 225 * @brief NAND MSP DeInit
sahilmgandhi 18:6a4db94011d3 226 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 227 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 228 * @retval None
sahilmgandhi 18:6a4db94011d3 229 */
sahilmgandhi 18:6a4db94011d3 230 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 231 {
sahilmgandhi 18:6a4db94011d3 232 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 233 UNUSED(hnand);
sahilmgandhi 18:6a4db94011d3 234 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 235 the HAL_NAND_MspDeInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 236 */
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 /**
sahilmgandhi 18:6a4db94011d3 241 * @brief This function handles NAND device interrupt request.
sahilmgandhi 18:6a4db94011d3 242 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 243 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 244 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 245 */
sahilmgandhi 18:6a4db94011d3 246 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 247 {
sahilmgandhi 18:6a4db94011d3 248 /* Check NAND interrupt Rising edge flag */
sahilmgandhi 18:6a4db94011d3 249 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
sahilmgandhi 18:6a4db94011d3 250 {
sahilmgandhi 18:6a4db94011d3 251 /* NAND interrupt callback*/
sahilmgandhi 18:6a4db94011d3 252 HAL_NAND_ITCallback(hnand);
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /* Clear NAND interrupt Rising edge pending bit */
sahilmgandhi 18:6a4db94011d3 255 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
sahilmgandhi 18:6a4db94011d3 256 }
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /* Check NAND interrupt Level flag */
sahilmgandhi 18:6a4db94011d3 259 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
sahilmgandhi 18:6a4db94011d3 260 {
sahilmgandhi 18:6a4db94011d3 261 /* NAND interrupt callback*/
sahilmgandhi 18:6a4db94011d3 262 HAL_NAND_ITCallback(hnand);
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 /* Clear NAND interrupt Level pending bit */
sahilmgandhi 18:6a4db94011d3 265 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
sahilmgandhi 18:6a4db94011d3 266 }
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /* Check NAND interrupt Falling edge flag */
sahilmgandhi 18:6a4db94011d3 269 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
sahilmgandhi 18:6a4db94011d3 270 {
sahilmgandhi 18:6a4db94011d3 271 /* NAND interrupt callback*/
sahilmgandhi 18:6a4db94011d3 272 HAL_NAND_ITCallback(hnand);
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /* Clear NAND interrupt Falling edge pending bit */
sahilmgandhi 18:6a4db94011d3 275 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
sahilmgandhi 18:6a4db94011d3 276 }
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 /* Check NAND interrupt FIFO empty flag */
sahilmgandhi 18:6a4db94011d3 279 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
sahilmgandhi 18:6a4db94011d3 280 {
sahilmgandhi 18:6a4db94011d3 281 /* NAND interrupt callback*/
sahilmgandhi 18:6a4db94011d3 282 HAL_NAND_ITCallback(hnand);
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 /* Clear NAND interrupt FIFO empty pending bit */
sahilmgandhi 18:6a4db94011d3 285 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 }
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 /**
sahilmgandhi 18:6a4db94011d3 291 * @brief NAND interrupt feature callback
sahilmgandhi 18:6a4db94011d3 292 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 293 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 294 * @retval None
sahilmgandhi 18:6a4db94011d3 295 */
sahilmgandhi 18:6a4db94011d3 296 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 297 {
sahilmgandhi 18:6a4db94011d3 298 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 299 UNUSED(hnand);
sahilmgandhi 18:6a4db94011d3 300 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 301 the HAL_NAND_ITCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 302 */
sahilmgandhi 18:6a4db94011d3 303 }
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 /**
sahilmgandhi 18:6a4db94011d3 306 * @}
sahilmgandhi 18:6a4db94011d3 307 */
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
sahilmgandhi 18:6a4db94011d3 310 * @brief Input Output and memory control functions
sahilmgandhi 18:6a4db94011d3 311 *
sahilmgandhi 18:6a4db94011d3 312 @verbatim
sahilmgandhi 18:6a4db94011d3 313 ==============================================================================
sahilmgandhi 18:6a4db94011d3 314 ##### NAND Input and Output functions #####
sahilmgandhi 18:6a4db94011d3 315 ==============================================================================
sahilmgandhi 18:6a4db94011d3 316 [..]
sahilmgandhi 18:6a4db94011d3 317 This section provides functions allowing to use and control the NAND
sahilmgandhi 18:6a4db94011d3 318 memory
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 @endverbatim
sahilmgandhi 18:6a4db94011d3 321 * @{
sahilmgandhi 18:6a4db94011d3 322 */
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /**
sahilmgandhi 18:6a4db94011d3 325 * @brief Read the NAND memory electronic signature
sahilmgandhi 18:6a4db94011d3 326 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 327 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 328 * @param pNAND_ID: NAND ID structure
sahilmgandhi 18:6a4db94011d3 329 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 330 */
sahilmgandhi 18:6a4db94011d3 331 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
sahilmgandhi 18:6a4db94011d3 332 {
sahilmgandhi 18:6a4db94011d3 333 __IO uint32_t data = 0U;
sahilmgandhi 18:6a4db94011d3 334 uint32_t deviceaddress = 0U;
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 337 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 340 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 341 {
sahilmgandhi 18:6a4db94011d3 342 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 343 }
sahilmgandhi 18:6a4db94011d3 344
sahilmgandhi 18:6a4db94011d3 345 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 346 if(hnand->Init.NandBank == FMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 347 {
sahilmgandhi 18:6a4db94011d3 348 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 349 }
sahilmgandhi 18:6a4db94011d3 350 else
sahilmgandhi 18:6a4db94011d3 351 {
sahilmgandhi 18:6a4db94011d3 352 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 353 }
sahilmgandhi 18:6a4db94011d3 354
sahilmgandhi 18:6a4db94011d3 355 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 356 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 /* Send Read ID command sequence */
sahilmgandhi 18:6a4db94011d3 359 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
sahilmgandhi 18:6a4db94011d3 360 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 /* Read the electronic signature from NAND flash */
sahilmgandhi 18:6a4db94011d3 363 data = *(__IO uint32_t *)deviceaddress;
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 /* Return the data read */
sahilmgandhi 18:6a4db94011d3 366 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
sahilmgandhi 18:6a4db94011d3 367 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
sahilmgandhi 18:6a4db94011d3 368 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
sahilmgandhi 18:6a4db94011d3 369 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 372 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 373
sahilmgandhi 18:6a4db94011d3 374 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 375 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 378 }
sahilmgandhi 18:6a4db94011d3 379
sahilmgandhi 18:6a4db94011d3 380 /**
sahilmgandhi 18:6a4db94011d3 381 * @brief NAND memory reset
sahilmgandhi 18:6a4db94011d3 382 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 383 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 384 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 385 */
sahilmgandhi 18:6a4db94011d3 386 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 387 {
sahilmgandhi 18:6a4db94011d3 388 uint32_t deviceaddress = 0U;
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 391 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 392
sahilmgandhi 18:6a4db94011d3 393 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 394 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 395 {
sahilmgandhi 18:6a4db94011d3 396 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 397 }
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 400 if(hnand->Init.NandBank == FMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 401 {
sahilmgandhi 18:6a4db94011d3 402 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 403 }
sahilmgandhi 18:6a4db94011d3 404 else
sahilmgandhi 18:6a4db94011d3 405 {
sahilmgandhi 18:6a4db94011d3 406 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 407 }
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 410 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 /* Send NAND reset command */
sahilmgandhi 18:6a4db94011d3 413 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFFU;
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 417 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 420 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 }
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426 /**
sahilmgandhi 18:6a4db94011d3 427 * @brief Read Page(s) from NAND memory block
sahilmgandhi 18:6a4db94011d3 428 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 429 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 430 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 431 * @param pBuffer : pointer to destination read buffer
sahilmgandhi 18:6a4db94011d3 432 * @param NumPageToRead : number of pages to read from block
sahilmgandhi 18:6a4db94011d3 433 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 434 */
sahilmgandhi 18:6a4db94011d3 435 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
sahilmgandhi 18:6a4db94011d3 436 {
sahilmgandhi 18:6a4db94011d3 437 __IO uint32_t index = 0U;
sahilmgandhi 18:6a4db94011d3 438 uint32_t deviceaddress = 0U, size = 0U, numpagesread = 0U, addressstatus = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 439 NAND_AddressTypeDef nandaddress;
sahilmgandhi 18:6a4db94011d3 440 uint32_t addressoffset = 0U;
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 443 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 446 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 447 {
sahilmgandhi 18:6a4db94011d3 448 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 449 }
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 452 if(hnand->Init.NandBank == FMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 453 {
sahilmgandhi 18:6a4db94011d3 454 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 455 }
sahilmgandhi 18:6a4db94011d3 456 else
sahilmgandhi 18:6a4db94011d3 457 {
sahilmgandhi 18:6a4db94011d3 458 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 459 }
sahilmgandhi 18:6a4db94011d3 460
sahilmgandhi 18:6a4db94011d3 461 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 462 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 /* Save the content of pAddress as it will be modified */
sahilmgandhi 18:6a4db94011d3 465 nandaddress.Block = pAddress->Block;
sahilmgandhi 18:6a4db94011d3 466 nandaddress.Page = pAddress->Page;
sahilmgandhi 18:6a4db94011d3 467 nandaddress.Zone = pAddress->Zone;
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 /* Page(s) read loop */
sahilmgandhi 18:6a4db94011d3 470 while((NumPageToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
sahilmgandhi 18:6a4db94011d3 471 {
sahilmgandhi 18:6a4db94011d3 472 /* update the buffer size */
sahilmgandhi 18:6a4db94011d3 473 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /* Get the address offset */
sahilmgandhi 18:6a4db94011d3 476 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 /* Send read page command sequence */
sahilmgandhi 18:6a4db94011d3 479 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 482 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 483 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 484 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 487 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 488 {
sahilmgandhi 18:6a4db94011d3 489 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 490 }
sahilmgandhi 18:6a4db94011d3 491
sahilmgandhi 18:6a4db94011d3 492 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
sahilmgandhi 18:6a4db94011d3 493
sahilmgandhi 18:6a4db94011d3 494 /* Get Data into Buffer */
sahilmgandhi 18:6a4db94011d3 495 for(; index < size; index++)
sahilmgandhi 18:6a4db94011d3 496 {
sahilmgandhi 18:6a4db94011d3 497 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
sahilmgandhi 18:6a4db94011d3 498 }
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 /* Increment read pages number */
sahilmgandhi 18:6a4db94011d3 501 numpagesread++;
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 /* Decrement pages to read */
sahilmgandhi 18:6a4db94011d3 504 NumPageToRead--;
sahilmgandhi 18:6a4db94011d3 505
sahilmgandhi 18:6a4db94011d3 506 /* Increment the NAND address */
sahilmgandhi 18:6a4db94011d3 507 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
sahilmgandhi 18:6a4db94011d3 508 }
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 511 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 512
sahilmgandhi 18:6a4db94011d3 513 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 514 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 517
sahilmgandhi 18:6a4db94011d3 518 }
sahilmgandhi 18:6a4db94011d3 519
sahilmgandhi 18:6a4db94011d3 520 /**
sahilmgandhi 18:6a4db94011d3 521 * @brief Write Page(s) to NAND memory block
sahilmgandhi 18:6a4db94011d3 522 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 523 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 524 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 525 * @param pBuffer : pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 526 * @param NumPageToWrite : number of pages to write to block
sahilmgandhi 18:6a4db94011d3 527 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 528 */
sahilmgandhi 18:6a4db94011d3 529 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
sahilmgandhi 18:6a4db94011d3 530 {
sahilmgandhi 18:6a4db94011d3 531 __IO uint32_t index = 0U;
sahilmgandhi 18:6a4db94011d3 532 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 533 uint32_t deviceaddress = 0U , size = 0U, numpageswritten = 0U, addressstatus = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 534 NAND_AddressTypeDef nandaddress;
sahilmgandhi 18:6a4db94011d3 535 uint32_t addressoffset = 0U;
sahilmgandhi 18:6a4db94011d3 536
sahilmgandhi 18:6a4db94011d3 537 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 538 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 539
sahilmgandhi 18:6a4db94011d3 540 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 541 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 542 {
sahilmgandhi 18:6a4db94011d3 543 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 544 }
sahilmgandhi 18:6a4db94011d3 545
sahilmgandhi 18:6a4db94011d3 546 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 547 if(hnand->Init.NandBank == FMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 548 {
sahilmgandhi 18:6a4db94011d3 549 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 550 }
sahilmgandhi 18:6a4db94011d3 551 else
sahilmgandhi 18:6a4db94011d3 552 {
sahilmgandhi 18:6a4db94011d3 553 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 554 }
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 557 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 /* Save the content of pAddress as it will be modified */
sahilmgandhi 18:6a4db94011d3 560 nandaddress.Block = pAddress->Block;
sahilmgandhi 18:6a4db94011d3 561 nandaddress.Page = pAddress->Page;
sahilmgandhi 18:6a4db94011d3 562 nandaddress.Zone = pAddress->Zone;
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564 /* Page(s) write loop */
sahilmgandhi 18:6a4db94011d3 565 while((NumPageToWrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
sahilmgandhi 18:6a4db94011d3 566 {
sahilmgandhi 18:6a4db94011d3 567 /* update the buffer size */
sahilmgandhi 18:6a4db94011d3 568 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /* Get the address offset */
sahilmgandhi 18:6a4db94011d3 571 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
sahilmgandhi 18:6a4db94011d3 572
sahilmgandhi 18:6a4db94011d3 573 /* Send write page command sequence */
sahilmgandhi 18:6a4db94011d3 574 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
sahilmgandhi 18:6a4db94011d3 575 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
sahilmgandhi 18:6a4db94011d3 576
sahilmgandhi 18:6a4db94011d3 577 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 578 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 579 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 580 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 581
sahilmgandhi 18:6a4db94011d3 582 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 583 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 584 {
sahilmgandhi 18:6a4db94011d3 585 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 586 }
sahilmgandhi 18:6a4db94011d3 587
sahilmgandhi 18:6a4db94011d3 588 /* Write data to memory */
sahilmgandhi 18:6a4db94011d3 589 for(; index < size; index++)
sahilmgandhi 18:6a4db94011d3 590 {
sahilmgandhi 18:6a4db94011d3 591 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
sahilmgandhi 18:6a4db94011d3 592 }
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 /* Get tick */
sahilmgandhi 18:6a4db94011d3 597 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 /* Read status until NAND is ready */
sahilmgandhi 18:6a4db94011d3 600 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
sahilmgandhi 18:6a4db94011d3 601 {
sahilmgandhi 18:6a4db94011d3 602 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
sahilmgandhi 18:6a4db94011d3 603 {
sahilmgandhi 18:6a4db94011d3 604 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 605 }
sahilmgandhi 18:6a4db94011d3 606 }
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /* Increment written pages number */
sahilmgandhi 18:6a4db94011d3 609 numpageswritten++;
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 /* Decrement pages to write */
sahilmgandhi 18:6a4db94011d3 612 NumPageToWrite--;
sahilmgandhi 18:6a4db94011d3 613
sahilmgandhi 18:6a4db94011d3 614 /* Increment the NAND address */
sahilmgandhi 18:6a4db94011d3 615 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
sahilmgandhi 18:6a4db94011d3 616 }
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 619 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 620
sahilmgandhi 18:6a4db94011d3 621 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 622 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 623
sahilmgandhi 18:6a4db94011d3 624 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 625 }
sahilmgandhi 18:6a4db94011d3 626
sahilmgandhi 18:6a4db94011d3 627 /**
sahilmgandhi 18:6a4db94011d3 628 * @brief Read Spare area(s) from NAND memory
sahilmgandhi 18:6a4db94011d3 629 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 630 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 631 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 632 * @param pBuffer: pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 633 * @param NumSpareAreaToRead: Number of spare area to read
sahilmgandhi 18:6a4db94011d3 634 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 635 */
sahilmgandhi 18:6a4db94011d3 636 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
sahilmgandhi 18:6a4db94011d3 637 {
sahilmgandhi 18:6a4db94011d3 638 __IO uint32_t index = 0U;
sahilmgandhi 18:6a4db94011d3 639 uint32_t deviceaddress = 0U, size = 0U, num_spare_area_read = 0U, addressstatus = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 640 NAND_AddressTypeDef nandaddress;
sahilmgandhi 18:6a4db94011d3 641 uint32_t addressoffset = 0U;
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 644 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 647 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 648 {
sahilmgandhi 18:6a4db94011d3 649 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 650 }
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 653 if(hnand->Init.NandBank == FMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 654 {
sahilmgandhi 18:6a4db94011d3 655 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 656 }
sahilmgandhi 18:6a4db94011d3 657 else
sahilmgandhi 18:6a4db94011d3 658 {
sahilmgandhi 18:6a4db94011d3 659 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 660 }
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 663 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 664
sahilmgandhi 18:6a4db94011d3 665 /* Save the content of pAddress as it will be modified */
sahilmgandhi 18:6a4db94011d3 666 nandaddress.Block = pAddress->Block;
sahilmgandhi 18:6a4db94011d3 667 nandaddress.Page = pAddress->Page;
sahilmgandhi 18:6a4db94011d3 668 nandaddress.Zone = pAddress->Zone;
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 /* Spare area(s) read loop */
sahilmgandhi 18:6a4db94011d3 671 while((NumSpareAreaToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
sahilmgandhi 18:6a4db94011d3 672 {
sahilmgandhi 18:6a4db94011d3 673 /* update the buffer size */
sahilmgandhi 18:6a4db94011d3 674 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 /* Get the address offset */
sahilmgandhi 18:6a4db94011d3 677 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 /* Send read spare area command sequence */
sahilmgandhi 18:6a4db94011d3 680 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 683 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 684 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 685 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 686
sahilmgandhi 18:6a4db94011d3 687 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 688 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 689 {
sahilmgandhi 18:6a4db94011d3 690 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 691 }
sahilmgandhi 18:6a4db94011d3 692
sahilmgandhi 18:6a4db94011d3 693 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 /* Get Data into Buffer */
sahilmgandhi 18:6a4db94011d3 696 for(; index < size; index++)
sahilmgandhi 18:6a4db94011d3 697 {
sahilmgandhi 18:6a4db94011d3 698 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
sahilmgandhi 18:6a4db94011d3 699 }
sahilmgandhi 18:6a4db94011d3 700
sahilmgandhi 18:6a4db94011d3 701 /* Increment read spare areas number */
sahilmgandhi 18:6a4db94011d3 702 num_spare_area_read++;
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 /* Decrement spare areas to read */
sahilmgandhi 18:6a4db94011d3 705 NumSpareAreaToRead--;
sahilmgandhi 18:6a4db94011d3 706
sahilmgandhi 18:6a4db94011d3 707 /* Increment the NAND address */
sahilmgandhi 18:6a4db94011d3 708 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
sahilmgandhi 18:6a4db94011d3 709 }
sahilmgandhi 18:6a4db94011d3 710
sahilmgandhi 18:6a4db94011d3 711 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 712 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 713
sahilmgandhi 18:6a4db94011d3 714 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 715 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 718 }
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 /**
sahilmgandhi 18:6a4db94011d3 721 * @brief Write Spare area(s) to NAND memory
sahilmgandhi 18:6a4db94011d3 722 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 723 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 724 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 725 * @param pBuffer : pointer to source buffer to write
sahilmgandhi 18:6a4db94011d3 726 * @param NumSpareAreaTowrite : number of spare areas to write to block
sahilmgandhi 18:6a4db94011d3 727 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 728 */
sahilmgandhi 18:6a4db94011d3 729 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
sahilmgandhi 18:6a4db94011d3 730 {
sahilmgandhi 18:6a4db94011d3 731 __IO uint32_t index = 0U;
sahilmgandhi 18:6a4db94011d3 732 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 733 uint32_t deviceaddress = 0U, size = 0U, num_spare_area_written = 0U, addressstatus = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 734 NAND_AddressTypeDef nandaddress;
sahilmgandhi 18:6a4db94011d3 735 uint32_t addressoffset = 0U;
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 738 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 739
sahilmgandhi 18:6a4db94011d3 740 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 741 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 742 {
sahilmgandhi 18:6a4db94011d3 743 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 744 }
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 747 if(hnand->Init.NandBank == FMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 748 {
sahilmgandhi 18:6a4db94011d3 749 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 750 }
sahilmgandhi 18:6a4db94011d3 751 else
sahilmgandhi 18:6a4db94011d3 752 {
sahilmgandhi 18:6a4db94011d3 753 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 754 }
sahilmgandhi 18:6a4db94011d3 755
sahilmgandhi 18:6a4db94011d3 756 /* Update the FMC_NAND controller state */
sahilmgandhi 18:6a4db94011d3 757 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 /* Save the content of pAddress as it will be modified */
sahilmgandhi 18:6a4db94011d3 760 nandaddress.Block = pAddress->Block;
sahilmgandhi 18:6a4db94011d3 761 nandaddress.Page = pAddress->Page;
sahilmgandhi 18:6a4db94011d3 762 nandaddress.Zone = pAddress->Zone;
sahilmgandhi 18:6a4db94011d3 763
sahilmgandhi 18:6a4db94011d3 764 /* Spare area(s) write loop */
sahilmgandhi 18:6a4db94011d3 765 while((NumSpareAreaTowrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
sahilmgandhi 18:6a4db94011d3 766 {
sahilmgandhi 18:6a4db94011d3 767 /* update the buffer size */
sahilmgandhi 18:6a4db94011d3 768 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 /* Get the address offset */
sahilmgandhi 18:6a4db94011d3 771 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773 /* Send write Spare area command sequence */
sahilmgandhi 18:6a4db94011d3 774 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
sahilmgandhi 18:6a4db94011d3 775 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
sahilmgandhi 18:6a4db94011d3 776
sahilmgandhi 18:6a4db94011d3 777 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
sahilmgandhi 18:6a4db94011d3 778 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 779 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 780 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 781
sahilmgandhi 18:6a4db94011d3 782 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 783 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 784 {
sahilmgandhi 18:6a4db94011d3 785 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
sahilmgandhi 18:6a4db94011d3 786 }
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 /* Write data to memory */
sahilmgandhi 18:6a4db94011d3 789 for(; index < size; index++)
sahilmgandhi 18:6a4db94011d3 790 {
sahilmgandhi 18:6a4db94011d3 791 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
sahilmgandhi 18:6a4db94011d3 792 }
sahilmgandhi 18:6a4db94011d3 793
sahilmgandhi 18:6a4db94011d3 794 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 /* Get tick */
sahilmgandhi 18:6a4db94011d3 797 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 798
sahilmgandhi 18:6a4db94011d3 799 /* Read status until NAND is ready */
sahilmgandhi 18:6a4db94011d3 800 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
sahilmgandhi 18:6a4db94011d3 801 {
sahilmgandhi 18:6a4db94011d3 802 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
sahilmgandhi 18:6a4db94011d3 803 {
sahilmgandhi 18:6a4db94011d3 804 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 805 }
sahilmgandhi 18:6a4db94011d3 806 }
sahilmgandhi 18:6a4db94011d3 807
sahilmgandhi 18:6a4db94011d3 808 /* Increment written spare areas number */
sahilmgandhi 18:6a4db94011d3 809 num_spare_area_written++;
sahilmgandhi 18:6a4db94011d3 810
sahilmgandhi 18:6a4db94011d3 811 /* Decrement spare areas to write */
sahilmgandhi 18:6a4db94011d3 812 NumSpareAreaTowrite--;
sahilmgandhi 18:6a4db94011d3 813
sahilmgandhi 18:6a4db94011d3 814 /* Increment the NAND address */
sahilmgandhi 18:6a4db94011d3 815 addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
sahilmgandhi 18:6a4db94011d3 816 }
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 819 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 820
sahilmgandhi 18:6a4db94011d3 821 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 822 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 823
sahilmgandhi 18:6a4db94011d3 824 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 825 }
sahilmgandhi 18:6a4db94011d3 826
sahilmgandhi 18:6a4db94011d3 827 /**
sahilmgandhi 18:6a4db94011d3 828 * @brief NAND memory Block erase
sahilmgandhi 18:6a4db94011d3 829 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 830 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 831 * @param pAddress : pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 832 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 833 */
sahilmgandhi 18:6a4db94011d3 834 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
sahilmgandhi 18:6a4db94011d3 835 {
sahilmgandhi 18:6a4db94011d3 836 uint32_t deviceaddress = 0U;
sahilmgandhi 18:6a4db94011d3 837 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 838
sahilmgandhi 18:6a4db94011d3 839 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 840 __HAL_LOCK(hnand);
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 843 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 844 {
sahilmgandhi 18:6a4db94011d3 845 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 846 }
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 849 if(hnand->Init.NandBank == FMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 850 {
sahilmgandhi 18:6a4db94011d3 851 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 852 }
sahilmgandhi 18:6a4db94011d3 853 else
sahilmgandhi 18:6a4db94011d3 854 {
sahilmgandhi 18:6a4db94011d3 855 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 856 }
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 859 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 860
sahilmgandhi 18:6a4db94011d3 861 /* Send Erase block command sequence */
sahilmgandhi 18:6a4db94011d3 862 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
sahilmgandhi 18:6a4db94011d3 863
sahilmgandhi 18:6a4db94011d3 864 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
sahilmgandhi 18:6a4db94011d3 865 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
sahilmgandhi 18:6a4db94011d3 866 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
sahilmgandhi 18:6a4db94011d3 867
sahilmgandhi 18:6a4db94011d3 868 /* for 512 and 1 GB devices, 4th cycle is required */
sahilmgandhi 18:6a4db94011d3 869 if(hnand->Info.BlockNbr >= 1024U)
sahilmgandhi 18:6a4db94011d3 870 {
sahilmgandhi 18:6a4db94011d3 871 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
sahilmgandhi 18:6a4db94011d3 872 }
sahilmgandhi 18:6a4db94011d3 873
sahilmgandhi 18:6a4db94011d3 874 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
sahilmgandhi 18:6a4db94011d3 875
sahilmgandhi 18:6a4db94011d3 876 /* Update the NAND controller state */
sahilmgandhi 18:6a4db94011d3 877 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 878
sahilmgandhi 18:6a4db94011d3 879 /* Get tick */
sahilmgandhi 18:6a4db94011d3 880 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 881
sahilmgandhi 18:6a4db94011d3 882 /* Read status until NAND is ready */
sahilmgandhi 18:6a4db94011d3 883 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
sahilmgandhi 18:6a4db94011d3 884 {
sahilmgandhi 18:6a4db94011d3 885 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
sahilmgandhi 18:6a4db94011d3 886 {
sahilmgandhi 18:6a4db94011d3 887 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 888 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 889
sahilmgandhi 18:6a4db94011d3 890 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 891 }
sahilmgandhi 18:6a4db94011d3 892 }
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 895 __HAL_UNLOCK(hnand);
sahilmgandhi 18:6a4db94011d3 896
sahilmgandhi 18:6a4db94011d3 897 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 898 }
sahilmgandhi 18:6a4db94011d3 899
sahilmgandhi 18:6a4db94011d3 900 /**
sahilmgandhi 18:6a4db94011d3 901 * @brief NAND memory read status
sahilmgandhi 18:6a4db94011d3 902 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 903 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 904 * @retval NAND status
sahilmgandhi 18:6a4db94011d3 905 */
sahilmgandhi 18:6a4db94011d3 906 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 907 {
sahilmgandhi 18:6a4db94011d3 908 uint32_t data = 0U;
sahilmgandhi 18:6a4db94011d3 909 uint32_t deviceaddress = 0U;
sahilmgandhi 18:6a4db94011d3 910
sahilmgandhi 18:6a4db94011d3 911 /* Identify the device address */
sahilmgandhi 18:6a4db94011d3 912 if(hnand->Init.NandBank == FMC_NAND_BANK2)
sahilmgandhi 18:6a4db94011d3 913 {
sahilmgandhi 18:6a4db94011d3 914 deviceaddress = NAND_DEVICE1;
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916 else
sahilmgandhi 18:6a4db94011d3 917 {
sahilmgandhi 18:6a4db94011d3 918 deviceaddress = NAND_DEVICE2;
sahilmgandhi 18:6a4db94011d3 919 }
sahilmgandhi 18:6a4db94011d3 920
sahilmgandhi 18:6a4db94011d3 921 /* Send Read status operation command */
sahilmgandhi 18:6a4db94011d3 922 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
sahilmgandhi 18:6a4db94011d3 923
sahilmgandhi 18:6a4db94011d3 924 /* Read status register data */
sahilmgandhi 18:6a4db94011d3 925 data = *(__IO uint8_t *)deviceaddress;
sahilmgandhi 18:6a4db94011d3 926
sahilmgandhi 18:6a4db94011d3 927 /* Return the status */
sahilmgandhi 18:6a4db94011d3 928 if((data & NAND_ERROR) == NAND_ERROR)
sahilmgandhi 18:6a4db94011d3 929 {
sahilmgandhi 18:6a4db94011d3 930 return NAND_ERROR;
sahilmgandhi 18:6a4db94011d3 931 }
sahilmgandhi 18:6a4db94011d3 932 else if((data & NAND_READY) == NAND_READY)
sahilmgandhi 18:6a4db94011d3 933 {
sahilmgandhi 18:6a4db94011d3 934 return NAND_READY;
sahilmgandhi 18:6a4db94011d3 935 }
sahilmgandhi 18:6a4db94011d3 936
sahilmgandhi 18:6a4db94011d3 937 return NAND_BUSY;
sahilmgandhi 18:6a4db94011d3 938 }
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 /**
sahilmgandhi 18:6a4db94011d3 941 * @brief Increment the NAND memory address
sahilmgandhi 18:6a4db94011d3 942 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 943 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 944 * @param pAddress: pointer to NAND address structure
sahilmgandhi 18:6a4db94011d3 945 * @retval The new status of the increment address operation. It can be:
sahilmgandhi 18:6a4db94011d3 946 * - NAND_VALID_ADDRESS: When the new address is valid address
sahilmgandhi 18:6a4db94011d3 947 * - NAND_INVALID_ADDRESS: When the new address is invalid address
sahilmgandhi 18:6a4db94011d3 948 */
sahilmgandhi 18:6a4db94011d3 949 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
sahilmgandhi 18:6a4db94011d3 950 {
sahilmgandhi 18:6a4db94011d3 951 uint32_t status = NAND_VALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 952
sahilmgandhi 18:6a4db94011d3 953 /* Increment page address */
sahilmgandhi 18:6a4db94011d3 954 pAddress->Page++;
sahilmgandhi 18:6a4db94011d3 955
sahilmgandhi 18:6a4db94011d3 956 /* Check NAND address is valid */
sahilmgandhi 18:6a4db94011d3 957 if(pAddress->Page == hnand->Info.BlockSize)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 pAddress->Page = 0U;
sahilmgandhi 18:6a4db94011d3 960 pAddress->Block++;
sahilmgandhi 18:6a4db94011d3 961
sahilmgandhi 18:6a4db94011d3 962 if(pAddress->Block == hnand->Info.ZoneSize)
sahilmgandhi 18:6a4db94011d3 963 {
sahilmgandhi 18:6a4db94011d3 964 pAddress->Block = 0U;
sahilmgandhi 18:6a4db94011d3 965 pAddress->Zone++;
sahilmgandhi 18:6a4db94011d3 966
sahilmgandhi 18:6a4db94011d3 967 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
sahilmgandhi 18:6a4db94011d3 968 {
sahilmgandhi 18:6a4db94011d3 969 status = NAND_INVALID_ADDRESS;
sahilmgandhi 18:6a4db94011d3 970 }
sahilmgandhi 18:6a4db94011d3 971 }
sahilmgandhi 18:6a4db94011d3 972 }
sahilmgandhi 18:6a4db94011d3 973
sahilmgandhi 18:6a4db94011d3 974 return (status);
sahilmgandhi 18:6a4db94011d3 975 }
sahilmgandhi 18:6a4db94011d3 976 /**
sahilmgandhi 18:6a4db94011d3 977 * @}
sahilmgandhi 18:6a4db94011d3 978 */
sahilmgandhi 18:6a4db94011d3 979
sahilmgandhi 18:6a4db94011d3 980 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 981 * @brief management functions
sahilmgandhi 18:6a4db94011d3 982 *
sahilmgandhi 18:6a4db94011d3 983 @verbatim
sahilmgandhi 18:6a4db94011d3 984 ==============================================================================
sahilmgandhi 18:6a4db94011d3 985 ##### NAND Control functions #####
sahilmgandhi 18:6a4db94011d3 986 ==============================================================================
sahilmgandhi 18:6a4db94011d3 987 [..]
sahilmgandhi 18:6a4db94011d3 988 This subsection provides a set of functions allowing to control dynamically
sahilmgandhi 18:6a4db94011d3 989 the NAND interface.
sahilmgandhi 18:6a4db94011d3 990
sahilmgandhi 18:6a4db94011d3 991 @endverbatim
sahilmgandhi 18:6a4db94011d3 992 * @{
sahilmgandhi 18:6a4db94011d3 993 */
sahilmgandhi 18:6a4db94011d3 994
sahilmgandhi 18:6a4db94011d3 995
sahilmgandhi 18:6a4db94011d3 996 /**
sahilmgandhi 18:6a4db94011d3 997 * @brief Enables dynamically NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 998 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 999 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 1000 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1001 */
sahilmgandhi 18:6a4db94011d3 1002 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 1003 {
sahilmgandhi 18:6a4db94011d3 1004 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 1005 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 1006 {
sahilmgandhi 18:6a4db94011d3 1007 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1008 }
sahilmgandhi 18:6a4db94011d3 1009
sahilmgandhi 18:6a4db94011d3 1010 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1011 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 /* Enable ECC feature */
sahilmgandhi 18:6a4db94011d3 1014 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 1015
sahilmgandhi 18:6a4db94011d3 1016 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1017 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1018
sahilmgandhi 18:6a4db94011d3 1019 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1020 }
sahilmgandhi 18:6a4db94011d3 1021
sahilmgandhi 18:6a4db94011d3 1022 /**
sahilmgandhi 18:6a4db94011d3 1023 * @brief Disables dynamically FMC_NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 1024 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1025 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 1026 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1027 */
sahilmgandhi 18:6a4db94011d3 1028 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 1029 {
sahilmgandhi 18:6a4db94011d3 1030 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 1031 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 1032 {
sahilmgandhi 18:6a4db94011d3 1033 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1034 }
sahilmgandhi 18:6a4db94011d3 1035
sahilmgandhi 18:6a4db94011d3 1036 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1037 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1038
sahilmgandhi 18:6a4db94011d3 1039 /* Disable ECC feature */
sahilmgandhi 18:6a4db94011d3 1040 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
sahilmgandhi 18:6a4db94011d3 1041
sahilmgandhi 18:6a4db94011d3 1042 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1043 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1044
sahilmgandhi 18:6a4db94011d3 1045 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1046 }
sahilmgandhi 18:6a4db94011d3 1047
sahilmgandhi 18:6a4db94011d3 1048 /**
sahilmgandhi 18:6a4db94011d3 1049 * @brief Disables dynamically NAND ECC feature.
sahilmgandhi 18:6a4db94011d3 1050 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1051 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 1052 * @param ECCval: pointer to ECC value
sahilmgandhi 18:6a4db94011d3 1053 * @param Timeout: maximum timeout to wait
sahilmgandhi 18:6a4db94011d3 1054 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1055 */
sahilmgandhi 18:6a4db94011d3 1056 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 1057 {
sahilmgandhi 18:6a4db94011d3 1058 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 1059
sahilmgandhi 18:6a4db94011d3 1060 /* Check the NAND controller state */
sahilmgandhi 18:6a4db94011d3 1061 if(hnand->State == HAL_NAND_STATE_BUSY)
sahilmgandhi 18:6a4db94011d3 1062 {
sahilmgandhi 18:6a4db94011d3 1063 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1064 }
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1067 hnand->State = HAL_NAND_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 /* Get NAND ECC value */
sahilmgandhi 18:6a4db94011d3 1070 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
sahilmgandhi 18:6a4db94011d3 1071
sahilmgandhi 18:6a4db94011d3 1072 /* Update the NAND state */
sahilmgandhi 18:6a4db94011d3 1073 hnand->State = HAL_NAND_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075 return status;
sahilmgandhi 18:6a4db94011d3 1076 }
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 /**
sahilmgandhi 18:6a4db94011d3 1079 * @}
sahilmgandhi 18:6a4db94011d3 1080 */
sahilmgandhi 18:6a4db94011d3 1081
sahilmgandhi 18:6a4db94011d3 1082
sahilmgandhi 18:6a4db94011d3 1083 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1084 * @brief Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1085 *
sahilmgandhi 18:6a4db94011d3 1086 @verbatim
sahilmgandhi 18:6a4db94011d3 1087 ==============================================================================
sahilmgandhi 18:6a4db94011d3 1088 ##### NAND State functions #####
sahilmgandhi 18:6a4db94011d3 1089 ==============================================================================
sahilmgandhi 18:6a4db94011d3 1090 [..]
sahilmgandhi 18:6a4db94011d3 1091 This subsection permits to get in run-time the status of the NAND controller
sahilmgandhi 18:6a4db94011d3 1092 and the data flow.
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094 @endverbatim
sahilmgandhi 18:6a4db94011d3 1095 * @{
sahilmgandhi 18:6a4db94011d3 1096 */
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 /**
sahilmgandhi 18:6a4db94011d3 1099 * @brief return the NAND state
sahilmgandhi 18:6a4db94011d3 1100 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1101 * the configuration information for NAND module.
sahilmgandhi 18:6a4db94011d3 1102 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1103 */
sahilmgandhi 18:6a4db94011d3 1104 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
sahilmgandhi 18:6a4db94011d3 1105 {
sahilmgandhi 18:6a4db94011d3 1106 return hnand->State;
sahilmgandhi 18:6a4db94011d3 1107 }
sahilmgandhi 18:6a4db94011d3 1108
sahilmgandhi 18:6a4db94011d3 1109 /**
sahilmgandhi 18:6a4db94011d3 1110 * @}
sahilmgandhi 18:6a4db94011d3 1111 */
sahilmgandhi 18:6a4db94011d3 1112
sahilmgandhi 18:6a4db94011d3 1113 /**
sahilmgandhi 18:6a4db94011d3 1114 * @}
sahilmgandhi 18:6a4db94011d3 1115 */
sahilmgandhi 18:6a4db94011d3 1116
sahilmgandhi 18:6a4db94011d3 1117 /**
sahilmgandhi 18:6a4db94011d3 1118 * @}
sahilmgandhi 18:6a4db94011d3 1119 */
sahilmgandhi 18:6a4db94011d3 1120
sahilmgandhi 18:6a4db94011d3 1121 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
sahilmgandhi 18:6a4db94011d3 1122 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
sahilmgandhi 18:6a4db94011d3 1123 STM32F446xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 1124 #endif /* HAL_NAND_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1125
sahilmgandhi 18:6a4db94011d3 1126 /**
sahilmgandhi 18:6a4db94011d3 1127 * @}
sahilmgandhi 18:6a4db94011d3 1128 */
sahilmgandhi 18:6a4db94011d3 1129
sahilmgandhi 18:6a4db94011d3 1130 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/