MouseCode - Mouse code for the MacroRat

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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f4xx_hal_lptim.c
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.5.0
sahilmgandhi	18:6a4db94011d3	6	* @date 06-May-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief LPTIM HAL module driver.
sahilmgandhi	18:6a4db94011d3	8	* This file provides firmware functions to manage the following
sahilmgandhi	18:6a4db94011d3	9	* functionalities of the Low Power Timer (LPTIM) peripheral:
sahilmgandhi	18:6a4db94011d3	10	* + Initialization and de-initialization functions.
sahilmgandhi	18:6a4db94011d3	11	* + Start/Stop operation functions in polling mode.
sahilmgandhi	18:6a4db94011d3	12	* + Start/Stop operation functions in interrupt mode.
sahilmgandhi	18:6a4db94011d3	13	* + Reading operation functions.
sahilmgandhi	18:6a4db94011d3	14	* + Peripheral State functions.
sahilmgandhi	18:6a4db94011d3	15	*
sahilmgandhi	18:6a4db94011d3	16	@verbatim
sahilmgandhi	18:6a4db94011d3	17	==============================================================================
sahilmgandhi	18:6a4db94011d3	18	##### How to use this driver #####
sahilmgandhi	18:6a4db94011d3	19	==============================================================================
sahilmgandhi	18:6a4db94011d3	20	[..]
sahilmgandhi	18:6a4db94011d3	21	The LPTIM HAL driver can be used as follows:
sahilmgandhi	18:6a4db94011d3	22
sahilmgandhi	18:6a4db94011d3	23	(#)Initialize the LPTIM low level resources by implementing the
sahilmgandhi	18:6a4db94011d3	24	HAL_LPTIM_MspInit():
sahilmgandhi	18:6a4db94011d3	25	(##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE().
sahilmgandhi	18:6a4db94011d3	26	(##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
sahilmgandhi	18:6a4db94011d3	27	(+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
sahilmgandhi	18:6a4db94011d3	28	(+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
sahilmgandhi	18:6a4db94011d3	29	(+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
sahilmgandhi	18:6a4db94011d3	30
sahilmgandhi	18:6a4db94011d3	31	(#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
sahilmgandhi	18:6a4db94011d3	32	configures mainly:
sahilmgandhi	18:6a4db94011d3	33	(##) The instance: LPTIM1.
sahilmgandhi	18:6a4db94011d3	34	(##) Clock: the counter clock.
sahilmgandhi	18:6a4db94011d3	35	(+++) Source : it can be either the ULPTIM input (IN1) or one of
sahilmgandhi	18:6a4db94011d3	36	the internal clock; (APB, LSE or LSI).
sahilmgandhi	18:6a4db94011d3	37	(+++) Prescaler: select the clock divider.
sahilmgandhi	18:6a4db94011d3	38	(##) UltraLowPowerClock : To be used only if the ULPTIM is selected
sahilmgandhi	18:6a4db94011d3	39	as counter clock source.
sahilmgandhi	18:6a4db94011d3	40	(+++) Polarity: polarity of the active edge for the counter unit
sahilmgandhi	18:6a4db94011d3	41	if the ULPTIM input is selected.
sahilmgandhi	18:6a4db94011d3	42	(+++) SampleTime: clock sampling time to configure the clock glitch
sahilmgandhi	18:6a4db94011d3	43	filter.
sahilmgandhi	18:6a4db94011d3	44	(##) Trigger: How the counter start.
sahilmgandhi	18:6a4db94011d3	45	(+++) Source: trigger can be software or one of the hardware triggers.
sahilmgandhi	18:6a4db94011d3	46	(+++) ActiveEdge : only for hardware trigger.
sahilmgandhi	18:6a4db94011d3	47	(+++) SampleTime : trigger sampling time to configure the trigger
sahilmgandhi	18:6a4db94011d3	48	glitch filter.
sahilmgandhi	18:6a4db94011d3	49	(##) OutputPolarity : 2 opposite polarities are possibles.
sahilmgandhi	18:6a4db94011d3	50	(##) UpdateMode: specifies whether the update of the autoreload and
sahilmgandhi	18:6a4db94011d3	51	the compare values is done immediately or after the end of current
sahilmgandhi	18:6a4db94011d3	52	period.
sahilmgandhi	18:6a4db94011d3	53
sahilmgandhi	18:6a4db94011d3	54	(#)Six modes are available:
sahilmgandhi	18:6a4db94011d3	55
sahilmgandhi	18:6a4db94011d3	56	(##) PWM Mode: To generate a PWM signal with specified period and pulse,
sahilmgandhi	18:6a4db94011d3	57	call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
sahilmgandhi	18:6a4db94011d3	58	mode.
sahilmgandhi	18:6a4db94011d3	59
sahilmgandhi	18:6a4db94011d3	60	(##) One Pulse Mode: To generate pulse with specified width in response
sahilmgandhi	18:6a4db94011d3	61	to a stimulus, call HAL_LPTIM_OnePulse_Start() or
sahilmgandhi	18:6a4db94011d3	62	HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
sahilmgandhi	18:6a4db94011d3	63
sahilmgandhi	18:6a4db94011d3	64	(##) Set once Mode: In this mode, the output changes the level (from
sahilmgandhi	18:6a4db94011d3	65	low level to high level if the output polarity is configured high, else
sahilmgandhi	18:6a4db94011d3	66	the opposite) when a compare match occurs. To start this mode, call
sahilmgandhi	18:6a4db94011d3	67	HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
sahilmgandhi	18:6a4db94011d3	68	interruption mode.
sahilmgandhi	18:6a4db94011d3	69
sahilmgandhi	18:6a4db94011d3	70	(##) Encoder Mode: To use the encoder interface call
sahilmgandhi	18:6a4db94011d3	71	HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
sahilmgandhi	18:6a4db94011d3	72	interruption mode.
sahilmgandhi	18:6a4db94011d3	73
sahilmgandhi	18:6a4db94011d3	74	(##) Time out Mode: an active edge on one selected trigger input rests
sahilmgandhi	18:6a4db94011d3	75	the counter. The first trigger event will start the timer, any
sahilmgandhi	18:6a4db94011d3	76	successive trigger event will reset the counter and the timer will
sahilmgandhi	18:6a4db94011d3	77	restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
sahilmgandhi	18:6a4db94011d3	78	HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
sahilmgandhi	18:6a4db94011d3	79
sahilmgandhi	18:6a4db94011d3	80	(##) Counter Mode: counter can be used to count external events on
sahilmgandhi	18:6a4db94011d3	81	the LPTIM Input1 or it can be used to count internal clock cycles.
sahilmgandhi	18:6a4db94011d3	82	To start this mode, call HAL_LPTIM_Counter_Start() or
sahilmgandhi	18:6a4db94011d3	83	HAL_LPTIM_Counter_Start_IT() for interruption mode.
sahilmgandhi	18:6a4db94011d3	84
sahilmgandhi	18:6a4db94011d3	85	(#) User can stop any process by calling the corresponding API:
sahilmgandhi	18:6a4db94011d3	86	HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
sahilmgandhi	18:6a4db94011d3	87	already started in interruption mode.
sahilmgandhi	18:6a4db94011d3	88
sahilmgandhi	18:6a4db94011d3	89	(#)Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
sahilmgandhi	18:6a4db94011d3	90
sahilmgandhi	18:6a4db94011d3	91	@endverbatim
sahilmgandhi	18:6a4db94011d3	92	******************************************************************************
sahilmgandhi	18:6a4db94011d3	93	* @attention
sahilmgandhi	18:6a4db94011d3	94	*
sahilmgandhi	18:6a4db94011d3	95	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	96	*
sahilmgandhi	18:6a4db94011d3	97	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	98	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	99	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	100	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	101	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	102	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	103	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	104	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	105	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	106	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	107	*
sahilmgandhi	18:6a4db94011d3	108	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	109	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	110	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	111	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	112	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	113	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	114	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	115	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	116	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	117	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	118	*
sahilmgandhi	18:6a4db94011d3	119	******************************************************************************
sahilmgandhi	18:6a4db94011d3	120	*/
sahilmgandhi	18:6a4db94011d3	121
sahilmgandhi	18:6a4db94011d3	122	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	123	#include "stm32f4xx_hal.h"
sahilmgandhi	18:6a4db94011d3	124
sahilmgandhi	18:6a4db94011d3	125	/** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	126	* @{
sahilmgandhi	18:6a4db94011d3	127	*/
sahilmgandhi	18:6a4db94011d3	128
sahilmgandhi	18:6a4db94011d3	129	/** @defgroup LPTIM LPTIM
sahilmgandhi	18:6a4db94011d3	130	* @brief LPTIM HAL module driver.
sahilmgandhi	18:6a4db94011d3	131	* @{
sahilmgandhi	18:6a4db94011d3	132	*/
sahilmgandhi	18:6a4db94011d3	133
sahilmgandhi	18:6a4db94011d3	134	#ifdef HAL_LPTIM_MODULE_ENABLED
sahilmgandhi	18:6a4db94011d3	135	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
sahilmgandhi	18:6a4db94011d3	136	/* Private types -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	137	/** @defgroup LPTIM_Private_Types LPTIM Private Types
sahilmgandhi	18:6a4db94011d3	138	* @{
sahilmgandhi	18:6a4db94011d3	139	*/
sahilmgandhi	18:6a4db94011d3	140
sahilmgandhi	18:6a4db94011d3	141	/**
sahilmgandhi	18:6a4db94011d3	142	* @}
sahilmgandhi	18:6a4db94011d3	143	*/
sahilmgandhi	18:6a4db94011d3	144
sahilmgandhi	18:6a4db94011d3	145	/* Private defines -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	146	/** @defgroup LPTIM_Private_Defines LPTIM Private Defines
sahilmgandhi	18:6a4db94011d3	147	* @{
sahilmgandhi	18:6a4db94011d3	148	*/
sahilmgandhi	18:6a4db94011d3	149
sahilmgandhi	18:6a4db94011d3	150	/**
sahilmgandhi	18:6a4db94011d3	151	* @}
sahilmgandhi	18:6a4db94011d3	152	*/
sahilmgandhi	18:6a4db94011d3	153
sahilmgandhi	18:6a4db94011d3	154	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	155	/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables
sahilmgandhi	18:6a4db94011d3	156	* @{
sahilmgandhi	18:6a4db94011d3	157	*/
sahilmgandhi	18:6a4db94011d3	158
sahilmgandhi	18:6a4db94011d3	159	/**
sahilmgandhi	18:6a4db94011d3	160	* @}
sahilmgandhi	18:6a4db94011d3	161	*/
sahilmgandhi	18:6a4db94011d3	162
sahilmgandhi	18:6a4db94011d3	163	/* Private constants ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	164	/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants
sahilmgandhi	18:6a4db94011d3	165	* @{
sahilmgandhi	18:6a4db94011d3	166	*/
sahilmgandhi	18:6a4db94011d3	167
sahilmgandhi	18:6a4db94011d3	168	/**
sahilmgandhi	18:6a4db94011d3	169	* @}
sahilmgandhi	18:6a4db94011d3	170	*/
sahilmgandhi	18:6a4db94011d3	171
sahilmgandhi	18:6a4db94011d3	172	/* Private macros ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	173	/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros
sahilmgandhi	18:6a4db94011d3	174	* @{
sahilmgandhi	18:6a4db94011d3	175	*/
sahilmgandhi	18:6a4db94011d3	176
sahilmgandhi	18:6a4db94011d3	177	/**
sahilmgandhi	18:6a4db94011d3	178	* @}
sahilmgandhi	18:6a4db94011d3	179	*/
sahilmgandhi	18:6a4db94011d3	180
sahilmgandhi	18:6a4db94011d3	181	/* Private function prototypes -----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	182	/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes
sahilmgandhi	18:6a4db94011d3	183	* @{
sahilmgandhi	18:6a4db94011d3	184	*/
sahilmgandhi	18:6a4db94011d3	185
sahilmgandhi	18:6a4db94011d3	186	/**
sahilmgandhi	18:6a4db94011d3	187	* @}
sahilmgandhi	18:6a4db94011d3	188	*/
sahilmgandhi	18:6a4db94011d3	189
sahilmgandhi	18:6a4db94011d3	190	/* Private functions ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	191	/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions
sahilmgandhi	18:6a4db94011d3	192	* @{
sahilmgandhi	18:6a4db94011d3	193	*/
sahilmgandhi	18:6a4db94011d3	194
sahilmgandhi	18:6a4db94011d3	195	/**
sahilmgandhi	18:6a4db94011d3	196	* @}
sahilmgandhi	18:6a4db94011d3	197	*/
sahilmgandhi	18:6a4db94011d3	198
sahilmgandhi	18:6a4db94011d3	199	/* Exported functions ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	200	/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
sahilmgandhi	18:6a4db94011d3	201	* @{
sahilmgandhi	18:6a4db94011d3	202	*/
sahilmgandhi	18:6a4db94011d3	203
sahilmgandhi	18:6a4db94011d3	204	/** @defgroup LPTIM_Group1 Initialization/de-initialization functions
sahilmgandhi	18:6a4db94011d3	205	* @brief Initialization and Configuration functions.
sahilmgandhi	18:6a4db94011d3	206	*
sahilmgandhi	18:6a4db94011d3	207	@verbatim
sahilmgandhi	18:6a4db94011d3	208	==============================================================================
sahilmgandhi	18:6a4db94011d3	209	##### Initialization and de-initialization functions #####
sahilmgandhi	18:6a4db94011d3	210	==============================================================================
sahilmgandhi	18:6a4db94011d3	211	[..] This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	212	(+) Initialize the LPTIM according to the specified parameters in the
sahilmgandhi	18:6a4db94011d3	213	LPTIM_InitTypeDef and creates the associated handle.
sahilmgandhi	18:6a4db94011d3	214	(+) DeInitialize the LPTIM peripheral.
sahilmgandhi	18:6a4db94011d3	215	(+) Initialize the LPTIM MSP.
sahilmgandhi	18:6a4db94011d3	216	(+) DeInitialize LPTIM MSP.
sahilmgandhi	18:6a4db94011d3	217
sahilmgandhi	18:6a4db94011d3	218	@endverbatim
sahilmgandhi	18:6a4db94011d3	219	* @{
sahilmgandhi	18:6a4db94011d3	220	*/
sahilmgandhi	18:6a4db94011d3	221
sahilmgandhi	18:6a4db94011d3	222	/**
sahilmgandhi	18:6a4db94011d3	223	* @brief Initializes the LPTIM according to the specified parameters in the
sahilmgandhi	18:6a4db94011d3	224	* LPTIM_InitTypeDef and creates the associated handle.
sahilmgandhi	18:6a4db94011d3	225	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	226	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	227	*/
sahilmgandhi	18:6a4db94011d3	228	HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	229	{
sahilmgandhi	18:6a4db94011d3	230	uint32_t tmpcfgr = 0U;
sahilmgandhi	18:6a4db94011d3	231
sahilmgandhi	18:6a4db94011d3	232	/* Check the LPTIM handle allocation */
sahilmgandhi	18:6a4db94011d3	233	if(hlptim == NULL)
sahilmgandhi	18:6a4db94011d3	234	{
sahilmgandhi	18:6a4db94011d3	235	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	236	}
sahilmgandhi	18:6a4db94011d3	237
sahilmgandhi	18:6a4db94011d3	238	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	239	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	240
sahilmgandhi	18:6a4db94011d3	241	assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
sahilmgandhi	18:6a4db94011d3	242	assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
sahilmgandhi	18:6a4db94011d3	243	if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
sahilmgandhi	18:6a4db94011d3	244	{
sahilmgandhi	18:6a4db94011d3	245	assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
sahilmgandhi	18:6a4db94011d3	246	assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
sahilmgandhi	18:6a4db94011d3	247	}
sahilmgandhi	18:6a4db94011d3	248	assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
sahilmgandhi	18:6a4db94011d3	249	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	250	{
sahilmgandhi	18:6a4db94011d3	251	assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
sahilmgandhi	18:6a4db94011d3	252	assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
sahilmgandhi	18:6a4db94011d3	253	}
sahilmgandhi	18:6a4db94011d3	254	assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
sahilmgandhi	18:6a4db94011d3	255	assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
sahilmgandhi	18:6a4db94011d3	256	assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
sahilmgandhi	18:6a4db94011d3	257
sahilmgandhi	18:6a4db94011d3	258	if(hlptim->State == HAL_LPTIM_STATE_RESET)
sahilmgandhi	18:6a4db94011d3	259	{
sahilmgandhi	18:6a4db94011d3	260	/* Allocate lock resource and initialize it */
sahilmgandhi	18:6a4db94011d3	261	hlptim->Lock = HAL_UNLOCKED;
sahilmgandhi	18:6a4db94011d3	262	/* Init the low level hardware */
sahilmgandhi	18:6a4db94011d3	263	HAL_LPTIM_MspInit(hlptim);
sahilmgandhi	18:6a4db94011d3	264	}
sahilmgandhi	18:6a4db94011d3	265
sahilmgandhi	18:6a4db94011d3	266	/* Change the LPTIM state */
sahilmgandhi	18:6a4db94011d3	267	hlptim->State = HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	268
sahilmgandhi	18:6a4db94011d3	269	/* Get the LPTIMx CFGR value */
sahilmgandhi	18:6a4db94011d3	270	tmpcfgr = hlptim->Instance->CFGR;
sahilmgandhi	18:6a4db94011d3	271
sahilmgandhi	18:6a4db94011d3	272	if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
sahilmgandhi	18:6a4db94011d3	273	{
sahilmgandhi	18:6a4db94011d3	274	tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL \| LPTIM_CFGR_CKFLT));
sahilmgandhi	18:6a4db94011d3	275	}
sahilmgandhi	18:6a4db94011d3	276	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	277	{
sahilmgandhi	18:6a4db94011d3	278	tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT \| LPTIM_CFGR_TRIGSEL));
sahilmgandhi	18:6a4db94011d3	279	}
sahilmgandhi	18:6a4db94011d3	280
sahilmgandhi	18:6a4db94011d3	281	/* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
sahilmgandhi	18:6a4db94011d3	282	tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL \| LPTIM_CFGR_TRIGEN \| LPTIM_CFGR_PRELOAD \|
sahilmgandhi	18:6a4db94011d3	283	LPTIM_CFGR_WAVPOL \| LPTIM_CFGR_PRESC \| LPTIM_CFGR_COUNTMODE ));
sahilmgandhi	18:6a4db94011d3	284
sahilmgandhi	18:6a4db94011d3	285	/* Set initialization parameters */
sahilmgandhi	18:6a4db94011d3	286	tmpcfgr \|= (hlptim->Init.Clock.Source \|
sahilmgandhi	18:6a4db94011d3	287	hlptim->Init.Clock.Prescaler \|
sahilmgandhi	18:6a4db94011d3	288	hlptim->Init.OutputPolarity \|
sahilmgandhi	18:6a4db94011d3	289	hlptim->Init.UpdateMode \|
sahilmgandhi	18:6a4db94011d3	290	hlptim->Init.CounterSource);
sahilmgandhi	18:6a4db94011d3	291
sahilmgandhi	18:6a4db94011d3	292	if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM)
sahilmgandhi	18:6a4db94011d3	293	{
sahilmgandhi	18:6a4db94011d3	294	tmpcfgr \|= (hlptim->Init.UltraLowPowerClock.Polarity \|
sahilmgandhi	18:6a4db94011d3	295	hlptim->Init.UltraLowPowerClock.SampleTime);
sahilmgandhi	18:6a4db94011d3	296	}
sahilmgandhi	18:6a4db94011d3	297
sahilmgandhi	18:6a4db94011d3	298	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	299	{
sahilmgandhi	18:6a4db94011d3	300	/* Enable External trigger and set the trigger source */
sahilmgandhi	18:6a4db94011d3	301	tmpcfgr \|= (hlptim->Init.Trigger.Source \|
sahilmgandhi	18:6a4db94011d3	302	hlptim->Init.Trigger.ActiveEdge \|
sahilmgandhi	18:6a4db94011d3	303	hlptim->Init.Trigger.SampleTime);
sahilmgandhi	18:6a4db94011d3	304	}
sahilmgandhi	18:6a4db94011d3	305
sahilmgandhi	18:6a4db94011d3	306	/* Write to LPTIMx CFGR */
sahilmgandhi	18:6a4db94011d3	307	hlptim->Instance->CFGR = tmpcfgr;
sahilmgandhi	18:6a4db94011d3	308
sahilmgandhi	18:6a4db94011d3	309	/* Change the LPTIM state */
sahilmgandhi	18:6a4db94011d3	310	hlptim->State = HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	311
sahilmgandhi	18:6a4db94011d3	312	/* Return function status */
sahilmgandhi	18:6a4db94011d3	313	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	314	}
sahilmgandhi	18:6a4db94011d3	315
sahilmgandhi	18:6a4db94011d3	316	/**
sahilmgandhi	18:6a4db94011d3	317	* @brief DeInitializes the LPTIM peripheral.
sahilmgandhi	18:6a4db94011d3	318	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	319	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	320	*/
sahilmgandhi	18:6a4db94011d3	321	HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	322	{
sahilmgandhi	18:6a4db94011d3	323	/* Check the LPTIM handle allocation */
sahilmgandhi	18:6a4db94011d3	324	if(hlptim == NULL)
sahilmgandhi	18:6a4db94011d3	325	{
sahilmgandhi	18:6a4db94011d3	326	return HAL_ERROR;
sahilmgandhi	18:6a4db94011d3	327	}
sahilmgandhi	18:6a4db94011d3	328
sahilmgandhi	18:6a4db94011d3	329	/* Change the LPTIM state */
sahilmgandhi	18:6a4db94011d3	330	hlptim->State = HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	331
sahilmgandhi	18:6a4db94011d3	332	/* Disable the LPTIM Peripheral Clock */
sahilmgandhi	18:6a4db94011d3	333	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	334
sahilmgandhi	18:6a4db94011d3	335	/* DeInit the low level hardware: CLOCK, NVIC.*/
sahilmgandhi	18:6a4db94011d3	336	HAL_LPTIM_MspDeInit(hlptim);
sahilmgandhi	18:6a4db94011d3	337
sahilmgandhi	18:6a4db94011d3	338	/* Change the LPTIM state */
sahilmgandhi	18:6a4db94011d3	339	hlptim->State = HAL_LPTIM_STATE_RESET;
sahilmgandhi	18:6a4db94011d3	340
sahilmgandhi	18:6a4db94011d3	341	/* Release Lock */
sahilmgandhi	18:6a4db94011d3	342	__HAL_UNLOCK(hlptim);
sahilmgandhi	18:6a4db94011d3	343
sahilmgandhi	18:6a4db94011d3	344	/* Return function status */
sahilmgandhi	18:6a4db94011d3	345	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	346	}
sahilmgandhi	18:6a4db94011d3	347
sahilmgandhi	18:6a4db94011d3	348	/**
sahilmgandhi	18:6a4db94011d3	349	* @brief Initializes the LPTIM MSP.
sahilmgandhi	18:6a4db94011d3	350	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	351	* @retval None
sahilmgandhi	18:6a4db94011d3	352	*/
sahilmgandhi	18:6a4db94011d3	353	__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	354	{
sahilmgandhi	18:6a4db94011d3	355	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	356	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	357	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	358	the HAL_LPTIM_MspInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	359	*/
sahilmgandhi	18:6a4db94011d3	360	}
sahilmgandhi	18:6a4db94011d3	361
sahilmgandhi	18:6a4db94011d3	362	/**
sahilmgandhi	18:6a4db94011d3	363	* @brief DeInitializes LPTIM MSP.
sahilmgandhi	18:6a4db94011d3	364	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	365	* @retval None
sahilmgandhi	18:6a4db94011d3	366	*/
sahilmgandhi	18:6a4db94011d3	367	__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	368	{
sahilmgandhi	18:6a4db94011d3	369	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	370	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	371	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	372	the HAL_LPTIM_MspDeInit could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	373	*/
sahilmgandhi	18:6a4db94011d3	374	}
sahilmgandhi	18:6a4db94011d3	375
sahilmgandhi	18:6a4db94011d3	376	/**
sahilmgandhi	18:6a4db94011d3	377	* @}
sahilmgandhi	18:6a4db94011d3	378	*/
sahilmgandhi	18:6a4db94011d3	379
sahilmgandhi	18:6a4db94011d3	380	/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions
sahilmgandhi	18:6a4db94011d3	381	* @brief Start-Stop operation functions.
sahilmgandhi	18:6a4db94011d3	382	*
sahilmgandhi	18:6a4db94011d3	383	@verbatim
sahilmgandhi	18:6a4db94011d3	384	==============================================================================
sahilmgandhi	18:6a4db94011d3	385	##### LPTIM Start Stop operation functions #####
sahilmgandhi	18:6a4db94011d3	386	==============================================================================
sahilmgandhi	18:6a4db94011d3	387	[..] This section provides functions allowing to:
sahilmgandhi	18:6a4db94011d3	388	(+) Start the PWM mode.
sahilmgandhi	18:6a4db94011d3	389	(+) Stop the PWM mode.
sahilmgandhi	18:6a4db94011d3	390	(+) Start the One pulse mode.
sahilmgandhi	18:6a4db94011d3	391	(+) Stop the One pulse mode.
sahilmgandhi	18:6a4db94011d3	392	(+) Start the Set once mode.
sahilmgandhi	18:6a4db94011d3	393	(+) Stop the Set once mode.
sahilmgandhi	18:6a4db94011d3	394	(+) Start the Encoder mode.
sahilmgandhi	18:6a4db94011d3	395	(+) Stop the Encoder mode.
sahilmgandhi	18:6a4db94011d3	396	(+) Start the Timeout mode.
sahilmgandhi	18:6a4db94011d3	397	(+) Stop the Timeout mode.
sahilmgandhi	18:6a4db94011d3	398	(+) Start the Counter mode.
sahilmgandhi	18:6a4db94011d3	399	(+) Stop the Counter mode.
sahilmgandhi	18:6a4db94011d3	400
sahilmgandhi	18:6a4db94011d3	401
sahilmgandhi	18:6a4db94011d3	402	@endverbatim
sahilmgandhi	18:6a4db94011d3	403	* @{
sahilmgandhi	18:6a4db94011d3	404	*/
sahilmgandhi	18:6a4db94011d3	405
sahilmgandhi	18:6a4db94011d3	406	/**
sahilmgandhi	18:6a4db94011d3	407	* @brief Starts the LPTIM PWM generation.
sahilmgandhi	18:6a4db94011d3	408	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	409	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	410	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	411	* @param Pulse : Specifies the compare value.
sahilmgandhi	18:6a4db94011d3	412	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	413	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	414	*/
sahilmgandhi	18:6a4db94011d3	415	HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
sahilmgandhi	18:6a4db94011d3	416	{
sahilmgandhi	18:6a4db94011d3	417	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	418	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	419	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	420	assert_param(IS_LPTIM_PULSE(Pulse));
sahilmgandhi	18:6a4db94011d3	421
sahilmgandhi	18:6a4db94011d3	422	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	423	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	424
sahilmgandhi	18:6a4db94011d3	425	/* Reset WAVE bit to set PWM mode */
sahilmgandhi	18:6a4db94011d3	426	hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
sahilmgandhi	18:6a4db94011d3	427
sahilmgandhi	18:6a4db94011d3	428	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	429	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	430
sahilmgandhi	18:6a4db94011d3	431	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	432	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	433
sahilmgandhi	18:6a4db94011d3	434	/* Load the pulse value in the compare register */
sahilmgandhi	18:6a4db94011d3	435	__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
sahilmgandhi	18:6a4db94011d3	436
sahilmgandhi	18:6a4db94011d3	437	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	438	__HAL_LPTIM_START_CONTINUOUS(hlptim);
sahilmgandhi	18:6a4db94011d3	439
sahilmgandhi	18:6a4db94011d3	440	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	441	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	442
sahilmgandhi	18:6a4db94011d3	443	/* Return function status */
sahilmgandhi	18:6a4db94011d3	444	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	445	}
sahilmgandhi	18:6a4db94011d3	446
sahilmgandhi	18:6a4db94011d3	447	/**
sahilmgandhi	18:6a4db94011d3	448	* @brief Stops the LPTIM PWM generation.
sahilmgandhi	18:6a4db94011d3	449	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	450	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	451	*/
sahilmgandhi	18:6a4db94011d3	452	HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	453	{
sahilmgandhi	18:6a4db94011d3	454	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	455	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	456
sahilmgandhi	18:6a4db94011d3	457	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	458	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	459
sahilmgandhi	18:6a4db94011d3	460	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	461	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	462
sahilmgandhi	18:6a4db94011d3	463	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	464	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	465
sahilmgandhi	18:6a4db94011d3	466	/* Return function status */
sahilmgandhi	18:6a4db94011d3	467	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	468	}
sahilmgandhi	18:6a4db94011d3	469
sahilmgandhi	18:6a4db94011d3	470	/**
sahilmgandhi	18:6a4db94011d3	471	* @brief Starts the LPTIM PWM generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	472	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	473	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	474	* This parameter must be a value between 0x0000 and 0xFFFF
sahilmgandhi	18:6a4db94011d3	475	* @param Pulse : Specifies the compare value.
sahilmgandhi	18:6a4db94011d3	476	* This parameter must be a value between 0x0000 and 0xFFFF
sahilmgandhi	18:6a4db94011d3	477	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	478	*/
sahilmgandhi	18:6a4db94011d3	479	HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
sahilmgandhi	18:6a4db94011d3	480	{
sahilmgandhi	18:6a4db94011d3	481	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	482	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	483	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	484	assert_param(IS_LPTIM_PULSE(Pulse));
sahilmgandhi	18:6a4db94011d3	485
sahilmgandhi	18:6a4db94011d3	486	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	487	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	488
sahilmgandhi	18:6a4db94011d3	489	/* Reset WAVE bit to set PWM mode */
sahilmgandhi	18:6a4db94011d3	490	hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
sahilmgandhi	18:6a4db94011d3	491
sahilmgandhi	18:6a4db94011d3	492	/* Enable Autoreload write complete interrupt */
sahilmgandhi	18:6a4db94011d3	493	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
sahilmgandhi	18:6a4db94011d3	494
sahilmgandhi	18:6a4db94011d3	495	/* Enable Compare write complete interrupt */
sahilmgandhi	18:6a4db94011d3	496	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
sahilmgandhi	18:6a4db94011d3	497
sahilmgandhi	18:6a4db94011d3	498	/* Enable Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	499	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
sahilmgandhi	18:6a4db94011d3	500
sahilmgandhi	18:6a4db94011d3	501	/* Enable Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	502	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
sahilmgandhi	18:6a4db94011d3	503
sahilmgandhi	18:6a4db94011d3	504	/* If external trigger source is used, then enable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	505	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	506	{
sahilmgandhi	18:6a4db94011d3	507	/* Enable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	508	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
sahilmgandhi	18:6a4db94011d3	509	}
sahilmgandhi	18:6a4db94011d3	510
sahilmgandhi	18:6a4db94011d3	511	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	512	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	513
sahilmgandhi	18:6a4db94011d3	514	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	515	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	516
sahilmgandhi	18:6a4db94011d3	517	/* Load the pulse value in the compare register */
sahilmgandhi	18:6a4db94011d3	518	__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
sahilmgandhi	18:6a4db94011d3	519
sahilmgandhi	18:6a4db94011d3	520	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	521	__HAL_LPTIM_START_CONTINUOUS(hlptim);
sahilmgandhi	18:6a4db94011d3	522
sahilmgandhi	18:6a4db94011d3	523	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	524	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	525
sahilmgandhi	18:6a4db94011d3	526	/* Return function status */
sahilmgandhi	18:6a4db94011d3	527	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	528	}
sahilmgandhi	18:6a4db94011d3	529
sahilmgandhi	18:6a4db94011d3	530	/**
sahilmgandhi	18:6a4db94011d3	531	* @brief Stops the LPTIM PWM generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	532	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	533	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	534	*/
sahilmgandhi	18:6a4db94011d3	535	HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	536	{
sahilmgandhi	18:6a4db94011d3	537	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	538	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	539
sahilmgandhi	18:6a4db94011d3	540	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	541	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	542
sahilmgandhi	18:6a4db94011d3	543	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	544	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	545
sahilmgandhi	18:6a4db94011d3	546	/* Disable Autoreload write complete interrupt */
sahilmgandhi	18:6a4db94011d3	547	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
sahilmgandhi	18:6a4db94011d3	548
sahilmgandhi	18:6a4db94011d3	549	/* Disable Compare write complete interrupt */
sahilmgandhi	18:6a4db94011d3	550	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
sahilmgandhi	18:6a4db94011d3	551
sahilmgandhi	18:6a4db94011d3	552	/* Disable Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	553	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
sahilmgandhi	18:6a4db94011d3	554
sahilmgandhi	18:6a4db94011d3	555	/* Disable Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	556	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
sahilmgandhi	18:6a4db94011d3	557
sahilmgandhi	18:6a4db94011d3	558	/* If external trigger source is used, then disable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	559	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	560	{
sahilmgandhi	18:6a4db94011d3	561	/* Disable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	562	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
sahilmgandhi	18:6a4db94011d3	563	}
sahilmgandhi	18:6a4db94011d3	564
sahilmgandhi	18:6a4db94011d3	565	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	566	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	567
sahilmgandhi	18:6a4db94011d3	568	/* Return function status */
sahilmgandhi	18:6a4db94011d3	569	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	570	}
sahilmgandhi	18:6a4db94011d3	571
sahilmgandhi	18:6a4db94011d3	572	/**
sahilmgandhi	18:6a4db94011d3	573	* @brief Starts the LPTIM One pulse generation.
sahilmgandhi	18:6a4db94011d3	574	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	575	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	576	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	577	* @param Pulse : Specifies the compare value.
sahilmgandhi	18:6a4db94011d3	578	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	579	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	580	*/
sahilmgandhi	18:6a4db94011d3	581	HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
sahilmgandhi	18:6a4db94011d3	582	{
sahilmgandhi	18:6a4db94011d3	583	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	584	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	585	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	586	assert_param(IS_LPTIM_PULSE(Pulse));
sahilmgandhi	18:6a4db94011d3	587
sahilmgandhi	18:6a4db94011d3	588	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	589	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	590
sahilmgandhi	18:6a4db94011d3	591	/* Reset WAVE bit to set one pulse mode */
sahilmgandhi	18:6a4db94011d3	592	hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
sahilmgandhi	18:6a4db94011d3	593
sahilmgandhi	18:6a4db94011d3	594	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	595	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	596
sahilmgandhi	18:6a4db94011d3	597	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	598	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	599
sahilmgandhi	18:6a4db94011d3	600	/* Load the pulse value in the compare register */
sahilmgandhi	18:6a4db94011d3	601	__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
sahilmgandhi	18:6a4db94011d3	602
sahilmgandhi	18:6a4db94011d3	603	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	604	__HAL_LPTIM_START_SINGLE(hlptim);
sahilmgandhi	18:6a4db94011d3	605
sahilmgandhi	18:6a4db94011d3	606	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	607	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	608
sahilmgandhi	18:6a4db94011d3	609	/* Return function status */
sahilmgandhi	18:6a4db94011d3	610	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	611	}
sahilmgandhi	18:6a4db94011d3	612
sahilmgandhi	18:6a4db94011d3	613	/**
sahilmgandhi	18:6a4db94011d3	614	* @brief Stops the LPTIM One pulse generation.
sahilmgandhi	18:6a4db94011d3	615	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	616	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	617	*/
sahilmgandhi	18:6a4db94011d3	618	HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	619	{
sahilmgandhi	18:6a4db94011d3	620	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	621	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	622
sahilmgandhi	18:6a4db94011d3	623	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	624	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	625
sahilmgandhi	18:6a4db94011d3	626	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	627	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	628
sahilmgandhi	18:6a4db94011d3	629	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	630	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	631
sahilmgandhi	18:6a4db94011d3	632	/* Return function status */
sahilmgandhi	18:6a4db94011d3	633	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	634	}
sahilmgandhi	18:6a4db94011d3	635
sahilmgandhi	18:6a4db94011d3	636	/**
sahilmgandhi	18:6a4db94011d3	637	* @brief Starts the LPTIM One pulse generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	638	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	639	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	640	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	641	* @param Pulse : Specifies the compare value.
sahilmgandhi	18:6a4db94011d3	642	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	643	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	644	*/
sahilmgandhi	18:6a4db94011d3	645	HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
sahilmgandhi	18:6a4db94011d3	646	{
sahilmgandhi	18:6a4db94011d3	647	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	648	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	649	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	650	assert_param(IS_LPTIM_PULSE(Pulse));
sahilmgandhi	18:6a4db94011d3	651
sahilmgandhi	18:6a4db94011d3	652	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	653	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	654
sahilmgandhi	18:6a4db94011d3	655	/* Reset WAVE bit to set one pulse mode */
sahilmgandhi	18:6a4db94011d3	656	hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
sahilmgandhi	18:6a4db94011d3	657
sahilmgandhi	18:6a4db94011d3	658	/* Enable Autoreload write complete interrupt */
sahilmgandhi	18:6a4db94011d3	659	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
sahilmgandhi	18:6a4db94011d3	660
sahilmgandhi	18:6a4db94011d3	661	/* Enable Compare write complete interrupt */
sahilmgandhi	18:6a4db94011d3	662	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
sahilmgandhi	18:6a4db94011d3	663
sahilmgandhi	18:6a4db94011d3	664	/* Enable Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	665	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
sahilmgandhi	18:6a4db94011d3	666
sahilmgandhi	18:6a4db94011d3	667	/* Enable Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	668	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
sahilmgandhi	18:6a4db94011d3	669
sahilmgandhi	18:6a4db94011d3	670	/* If external trigger source is used, then enable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	671	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	672	{
sahilmgandhi	18:6a4db94011d3	673	/* Enable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	674	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
sahilmgandhi	18:6a4db94011d3	675	}
sahilmgandhi	18:6a4db94011d3	676
sahilmgandhi	18:6a4db94011d3	677	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	678	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	679
sahilmgandhi	18:6a4db94011d3	680	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	681	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	682
sahilmgandhi	18:6a4db94011d3	683	/* Load the pulse value in the compare register */
sahilmgandhi	18:6a4db94011d3	684	__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
sahilmgandhi	18:6a4db94011d3	685
sahilmgandhi	18:6a4db94011d3	686	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	687	__HAL_LPTIM_START_SINGLE(hlptim);
sahilmgandhi	18:6a4db94011d3	688
sahilmgandhi	18:6a4db94011d3	689	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	690	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	691
sahilmgandhi	18:6a4db94011d3	692	/* Return function status */
sahilmgandhi	18:6a4db94011d3	693	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	694	}
sahilmgandhi	18:6a4db94011d3	695
sahilmgandhi	18:6a4db94011d3	696	/**
sahilmgandhi	18:6a4db94011d3	697	* @brief Stops the LPTIM One pulse generation in interrupt mode.
sahilmgandhi	18:6a4db94011d3	698	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	699	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	700	*/
sahilmgandhi	18:6a4db94011d3	701	HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	702	{
sahilmgandhi	18:6a4db94011d3	703	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	704	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	705
sahilmgandhi	18:6a4db94011d3	706	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	707	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	708
sahilmgandhi	18:6a4db94011d3	709	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	710	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	711
sahilmgandhi	18:6a4db94011d3	712	/* Disable Autoreload write complete interrupt */
sahilmgandhi	18:6a4db94011d3	713	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
sahilmgandhi	18:6a4db94011d3	714
sahilmgandhi	18:6a4db94011d3	715	/* Disable Compare write complete interrupt */
sahilmgandhi	18:6a4db94011d3	716	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
sahilmgandhi	18:6a4db94011d3	717
sahilmgandhi	18:6a4db94011d3	718	/* Disable Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	719	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
sahilmgandhi	18:6a4db94011d3	720
sahilmgandhi	18:6a4db94011d3	721	/* Disable Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	722	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
sahilmgandhi	18:6a4db94011d3	723
sahilmgandhi	18:6a4db94011d3	724	/* If external trigger source is used, then disable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	725	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	726	{
sahilmgandhi	18:6a4db94011d3	727	/* Disable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	728	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
sahilmgandhi	18:6a4db94011d3	729	}
sahilmgandhi	18:6a4db94011d3	730
sahilmgandhi	18:6a4db94011d3	731	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	732	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	733
sahilmgandhi	18:6a4db94011d3	734	/* Return function status */
sahilmgandhi	18:6a4db94011d3	735	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	736	}
sahilmgandhi	18:6a4db94011d3	737
sahilmgandhi	18:6a4db94011d3	738	/**
sahilmgandhi	18:6a4db94011d3	739	* @brief Starts the LPTIM in Set once mode.
sahilmgandhi	18:6a4db94011d3	740	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	741	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	742	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	743	* @param Pulse : Specifies the compare value.
sahilmgandhi	18:6a4db94011d3	744	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	745	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	746	*/
sahilmgandhi	18:6a4db94011d3	747	HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
sahilmgandhi	18:6a4db94011d3	748	{
sahilmgandhi	18:6a4db94011d3	749	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	750	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	751	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	752	assert_param(IS_LPTIM_PULSE(Pulse));
sahilmgandhi	18:6a4db94011d3	753
sahilmgandhi	18:6a4db94011d3	754	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	755	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	756
sahilmgandhi	18:6a4db94011d3	757	/* Set WAVE bit to enable the set once mode */
sahilmgandhi	18:6a4db94011d3	758	hlptim->Instance->CFGR \|= LPTIM_CFGR_WAVE;
sahilmgandhi	18:6a4db94011d3	759
sahilmgandhi	18:6a4db94011d3	760	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	761	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	762
sahilmgandhi	18:6a4db94011d3	763	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	764	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	765
sahilmgandhi	18:6a4db94011d3	766	/* Load the pulse value in the compare register */
sahilmgandhi	18:6a4db94011d3	767	__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
sahilmgandhi	18:6a4db94011d3	768
sahilmgandhi	18:6a4db94011d3	769	/* Start timer in single mode */
sahilmgandhi	18:6a4db94011d3	770	__HAL_LPTIM_START_SINGLE(hlptim);
sahilmgandhi	18:6a4db94011d3	771
sahilmgandhi	18:6a4db94011d3	772	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	773	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	774
sahilmgandhi	18:6a4db94011d3	775	/* Return function status */
sahilmgandhi	18:6a4db94011d3	776	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	777	}
sahilmgandhi	18:6a4db94011d3	778
sahilmgandhi	18:6a4db94011d3	779	/**
sahilmgandhi	18:6a4db94011d3	780	* @brief Stops the LPTIM Set once mode.
sahilmgandhi	18:6a4db94011d3	781	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	782	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	783	*/
sahilmgandhi	18:6a4db94011d3	784	HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	785	{
sahilmgandhi	18:6a4db94011d3	786	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	787	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	788
sahilmgandhi	18:6a4db94011d3	789	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	790	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	791
sahilmgandhi	18:6a4db94011d3	792	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	793	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	794
sahilmgandhi	18:6a4db94011d3	795	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	796	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	797
sahilmgandhi	18:6a4db94011d3	798	/* Return function status */
sahilmgandhi	18:6a4db94011d3	799	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	800	}
sahilmgandhi	18:6a4db94011d3	801
sahilmgandhi	18:6a4db94011d3	802	/**
sahilmgandhi	18:6a4db94011d3	803	* @brief Starts the LPTIM Set once mode in interrupt mode.
sahilmgandhi	18:6a4db94011d3	804	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	805	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	806	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	807	* @param Pulse : Specifies the compare value.
sahilmgandhi	18:6a4db94011d3	808	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	809	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	810	*/
sahilmgandhi	18:6a4db94011d3	811	HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse)
sahilmgandhi	18:6a4db94011d3	812	{
sahilmgandhi	18:6a4db94011d3	813	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	814	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	815	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	816	assert_param(IS_LPTIM_PULSE(Pulse));
sahilmgandhi	18:6a4db94011d3	817
sahilmgandhi	18:6a4db94011d3	818	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	819	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	820
sahilmgandhi	18:6a4db94011d3	821	/* Set WAVE bit to enable the set once mode */
sahilmgandhi	18:6a4db94011d3	822	hlptim->Instance->CFGR \|= LPTIM_CFGR_WAVE;
sahilmgandhi	18:6a4db94011d3	823
sahilmgandhi	18:6a4db94011d3	824	/* Enable Autoreload write complete interrupt */
sahilmgandhi	18:6a4db94011d3	825	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
sahilmgandhi	18:6a4db94011d3	826
sahilmgandhi	18:6a4db94011d3	827	/* Enable Compare write complete interrupt */
sahilmgandhi	18:6a4db94011d3	828	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK);
sahilmgandhi	18:6a4db94011d3	829
sahilmgandhi	18:6a4db94011d3	830	/* Enable Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	831	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
sahilmgandhi	18:6a4db94011d3	832
sahilmgandhi	18:6a4db94011d3	833	/* Enable Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	834	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
sahilmgandhi	18:6a4db94011d3	835
sahilmgandhi	18:6a4db94011d3	836	/* If external trigger source is used, then enable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	837	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	838	{
sahilmgandhi	18:6a4db94011d3	839	/* Enable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	840	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
sahilmgandhi	18:6a4db94011d3	841	}
sahilmgandhi	18:6a4db94011d3	842
sahilmgandhi	18:6a4db94011d3	843	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	844	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	845
sahilmgandhi	18:6a4db94011d3	846	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	847	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	848
sahilmgandhi	18:6a4db94011d3	849	/* Load the pulse value in the compare register */
sahilmgandhi	18:6a4db94011d3	850	__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
sahilmgandhi	18:6a4db94011d3	851
sahilmgandhi	18:6a4db94011d3	852	/* Start timer in single mode */
sahilmgandhi	18:6a4db94011d3	853	__HAL_LPTIM_START_SINGLE(hlptim);
sahilmgandhi	18:6a4db94011d3	854
sahilmgandhi	18:6a4db94011d3	855	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	856	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	857
sahilmgandhi	18:6a4db94011d3	858	/* Return function status */
sahilmgandhi	18:6a4db94011d3	859	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	860	}
sahilmgandhi	18:6a4db94011d3	861
sahilmgandhi	18:6a4db94011d3	862	/**
sahilmgandhi	18:6a4db94011d3	863	* @brief Stops the LPTIM Set once mode in interrupt mode.
sahilmgandhi	18:6a4db94011d3	864	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	865	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	866	*/
sahilmgandhi	18:6a4db94011d3	867	HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	868	{
sahilmgandhi	18:6a4db94011d3	869	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	870	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	871
sahilmgandhi	18:6a4db94011d3	872	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	873	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	874
sahilmgandhi	18:6a4db94011d3	875	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	876	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	877
sahilmgandhi	18:6a4db94011d3	878	/* Disable Autoreload write complete interrupt */
sahilmgandhi	18:6a4db94011d3	879	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
sahilmgandhi	18:6a4db94011d3	880
sahilmgandhi	18:6a4db94011d3	881	/* Disable Compare write complete interrupt */
sahilmgandhi	18:6a4db94011d3	882	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK);
sahilmgandhi	18:6a4db94011d3	883
sahilmgandhi	18:6a4db94011d3	884	/* Disable Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	885	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
sahilmgandhi	18:6a4db94011d3	886
sahilmgandhi	18:6a4db94011d3	887	/* Disable Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	888	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
sahilmgandhi	18:6a4db94011d3	889
sahilmgandhi	18:6a4db94011d3	890	/* If external trigger source is used, then disable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	891	if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
sahilmgandhi	18:6a4db94011d3	892	{
sahilmgandhi	18:6a4db94011d3	893	/* Disable external trigger interrupt */
sahilmgandhi	18:6a4db94011d3	894	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
sahilmgandhi	18:6a4db94011d3	895	}
sahilmgandhi	18:6a4db94011d3	896
sahilmgandhi	18:6a4db94011d3	897	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	898	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	899
sahilmgandhi	18:6a4db94011d3	900	/* Return function status */
sahilmgandhi	18:6a4db94011d3	901	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	902	}
sahilmgandhi	18:6a4db94011d3	903
sahilmgandhi	18:6a4db94011d3	904	/**
sahilmgandhi	18:6a4db94011d3	905	* @brief Starts the Encoder interface.
sahilmgandhi	18:6a4db94011d3	906	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	907	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	908	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	909	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	910	*/
sahilmgandhi	18:6a4db94011d3	911	HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
sahilmgandhi	18:6a4db94011d3	912	{
sahilmgandhi	18:6a4db94011d3	913	uint32_t tmpcfgr = 0U;
sahilmgandhi	18:6a4db94011d3	914
sahilmgandhi	18:6a4db94011d3	915	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	916	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	917	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	918	assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
sahilmgandhi	18:6a4db94011d3	919	assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
sahilmgandhi	18:6a4db94011d3	920	assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
sahilmgandhi	18:6a4db94011d3	921
sahilmgandhi	18:6a4db94011d3	922	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	923	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	924
sahilmgandhi	18:6a4db94011d3	925	/* Get the LPTIMx CFGR value */
sahilmgandhi	18:6a4db94011d3	926	tmpcfgr = hlptim->Instance->CFGR;
sahilmgandhi	18:6a4db94011d3	927
sahilmgandhi	18:6a4db94011d3	928	/* Clear CKPOL bits */
sahilmgandhi	18:6a4db94011d3	929	tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
sahilmgandhi	18:6a4db94011d3	930
sahilmgandhi	18:6a4db94011d3	931	/* Set Input polarity */
sahilmgandhi	18:6a4db94011d3	932	tmpcfgr \|= hlptim->Init.UltraLowPowerClock.Polarity;
sahilmgandhi	18:6a4db94011d3	933
sahilmgandhi	18:6a4db94011d3	934	/* Write to LPTIMx CFGR */
sahilmgandhi	18:6a4db94011d3	935	hlptim->Instance->CFGR = tmpcfgr;
sahilmgandhi	18:6a4db94011d3	936
sahilmgandhi	18:6a4db94011d3	937	/* Set ENC bit to enable the encoder interface */
sahilmgandhi	18:6a4db94011d3	938	hlptim->Instance->CFGR \|= LPTIM_CFGR_ENC;
sahilmgandhi	18:6a4db94011d3	939
sahilmgandhi	18:6a4db94011d3	940	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	941	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	942
sahilmgandhi	18:6a4db94011d3	943	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	944	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	945
sahilmgandhi	18:6a4db94011d3	946	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	947	__HAL_LPTIM_START_CONTINUOUS(hlptim);
sahilmgandhi	18:6a4db94011d3	948
sahilmgandhi	18:6a4db94011d3	949	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	950	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	951
sahilmgandhi	18:6a4db94011d3	952	/* Return function status */
sahilmgandhi	18:6a4db94011d3	953	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	954	}
sahilmgandhi	18:6a4db94011d3	955
sahilmgandhi	18:6a4db94011d3	956	/**
sahilmgandhi	18:6a4db94011d3	957	* @brief Stops the Encoder interface.
sahilmgandhi	18:6a4db94011d3	958	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	959	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	960	*/
sahilmgandhi	18:6a4db94011d3	961	HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	962	{
sahilmgandhi	18:6a4db94011d3	963	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	964	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	965
sahilmgandhi	18:6a4db94011d3	966	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	967	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	968
sahilmgandhi	18:6a4db94011d3	969	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	970	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	971
sahilmgandhi	18:6a4db94011d3	972	/* Reset ENC bit to disable the encoder interface */
sahilmgandhi	18:6a4db94011d3	973	hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
sahilmgandhi	18:6a4db94011d3	974
sahilmgandhi	18:6a4db94011d3	975	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	976	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	977
sahilmgandhi	18:6a4db94011d3	978	/* Return function status */
sahilmgandhi	18:6a4db94011d3	979	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	980	}
sahilmgandhi	18:6a4db94011d3	981
sahilmgandhi	18:6a4db94011d3	982	/**
sahilmgandhi	18:6a4db94011d3	983	* @brief Starts the Encoder interface in interrupt mode.
sahilmgandhi	18:6a4db94011d3	984	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	985	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	986	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	987	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	988	*/
sahilmgandhi	18:6a4db94011d3	989	HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
sahilmgandhi	18:6a4db94011d3	990	{
sahilmgandhi	18:6a4db94011d3	991	uint32_t tmpcfgr = 0U;
sahilmgandhi	18:6a4db94011d3	992
sahilmgandhi	18:6a4db94011d3	993	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	994	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	995	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	996	assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
sahilmgandhi	18:6a4db94011d3	997	assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
sahilmgandhi	18:6a4db94011d3	998	assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
sahilmgandhi	18:6a4db94011d3	999
sahilmgandhi	18:6a4db94011d3	1000	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1001	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1002
sahilmgandhi	18:6a4db94011d3	1003	/* Configure edge sensitivity for encoder mode */
sahilmgandhi	18:6a4db94011d3	1004	/* Get the LPTIMx CFGR value */
sahilmgandhi	18:6a4db94011d3	1005	tmpcfgr = hlptim->Instance->CFGR;
sahilmgandhi	18:6a4db94011d3	1006
sahilmgandhi	18:6a4db94011d3	1007	/* Clear CKPOL bits */
sahilmgandhi	18:6a4db94011d3	1008	tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
sahilmgandhi	18:6a4db94011d3	1009
sahilmgandhi	18:6a4db94011d3	1010	/* Set Input polarity */
sahilmgandhi	18:6a4db94011d3	1011	tmpcfgr \|= hlptim->Init.UltraLowPowerClock.Polarity;
sahilmgandhi	18:6a4db94011d3	1012
sahilmgandhi	18:6a4db94011d3	1013	/* Write to LPTIMx CFGR */
sahilmgandhi	18:6a4db94011d3	1014	hlptim->Instance->CFGR = tmpcfgr;
sahilmgandhi	18:6a4db94011d3	1015
sahilmgandhi	18:6a4db94011d3	1016	/* Set ENC bit to enable the encoder interface */
sahilmgandhi	18:6a4db94011d3	1017	hlptim->Instance->CFGR \|= LPTIM_CFGR_ENC;
sahilmgandhi	18:6a4db94011d3	1018
sahilmgandhi	18:6a4db94011d3	1019	/* Enable "switch to down direction" interrupt */
sahilmgandhi	18:6a4db94011d3	1020	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
sahilmgandhi	18:6a4db94011d3	1021
sahilmgandhi	18:6a4db94011d3	1022	/* Enable "switch to up direction" interrupt */
sahilmgandhi	18:6a4db94011d3	1023	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP);
sahilmgandhi	18:6a4db94011d3	1024
sahilmgandhi	18:6a4db94011d3	1025	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1026	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1027
sahilmgandhi	18:6a4db94011d3	1028	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	1029	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	1030
sahilmgandhi	18:6a4db94011d3	1031	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	1032	__HAL_LPTIM_START_CONTINUOUS(hlptim);
sahilmgandhi	18:6a4db94011d3	1033
sahilmgandhi	18:6a4db94011d3	1034	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1035	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1036
sahilmgandhi	18:6a4db94011d3	1037	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1038	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1039	}
sahilmgandhi	18:6a4db94011d3	1040
sahilmgandhi	18:6a4db94011d3	1041	/**
sahilmgandhi	18:6a4db94011d3	1042	* @brief Stops the Encoder interface in interrupt mode.
sahilmgandhi	18:6a4db94011d3	1043	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1044	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1045	*/
sahilmgandhi	18:6a4db94011d3	1046	HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1047	{
sahilmgandhi	18:6a4db94011d3	1048	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1049	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1050
sahilmgandhi	18:6a4db94011d3	1051	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1052	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1053
sahilmgandhi	18:6a4db94011d3	1054	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1055	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1056
sahilmgandhi	18:6a4db94011d3	1057	/* Reset ENC bit to disable the encoder interface */
sahilmgandhi	18:6a4db94011d3	1058	hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
sahilmgandhi	18:6a4db94011d3	1059
sahilmgandhi	18:6a4db94011d3	1060	/* Disable "switch to down direction" interrupt */
sahilmgandhi	18:6a4db94011d3	1061	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN);
sahilmgandhi	18:6a4db94011d3	1062
sahilmgandhi	18:6a4db94011d3	1063	/* Disable "switch to up direction" interrupt */
sahilmgandhi	18:6a4db94011d3	1064	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
sahilmgandhi	18:6a4db94011d3	1065
sahilmgandhi	18:6a4db94011d3	1066	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1067	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1068
sahilmgandhi	18:6a4db94011d3	1069	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1070	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1071	}
sahilmgandhi	18:6a4db94011d3	1072
sahilmgandhi	18:6a4db94011d3	1073	/**
sahilmgandhi	18:6a4db94011d3	1074	* @brief Starts the Timeout function. The first trigger event will start the
sahilmgandhi	18:6a4db94011d3	1075	* timer, any successive trigger event will reset the counter and
sahilmgandhi	18:6a4db94011d3	1076	* the timer restarts.
sahilmgandhi	18:6a4db94011d3	1077	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1078	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	1079	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	1080	* @param Timeout : Specifies the TimeOut value to rest the counter.
sahilmgandhi	18:6a4db94011d3	1081	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	1082	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1083	*/
sahilmgandhi	18:6a4db94011d3	1084	HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
sahilmgandhi	18:6a4db94011d3	1085	{
sahilmgandhi	18:6a4db94011d3	1086	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1087	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1088	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	1089	assert_param(IS_LPTIM_PULSE(Timeout));
sahilmgandhi	18:6a4db94011d3	1090
sahilmgandhi	18:6a4db94011d3	1091	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1092	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1093
sahilmgandhi	18:6a4db94011d3	1094	/* Set TIMOUT bit to enable the timeout function */
sahilmgandhi	18:6a4db94011d3	1095	hlptim->Instance->CFGR \|= LPTIM_CFGR_TIMOUT;
sahilmgandhi	18:6a4db94011d3	1096
sahilmgandhi	18:6a4db94011d3	1097	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1098	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1099
sahilmgandhi	18:6a4db94011d3	1100	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	1101	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	1102
sahilmgandhi	18:6a4db94011d3	1103	/* Load the Timeout value in the compare register */
sahilmgandhi	18:6a4db94011d3	1104	__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
sahilmgandhi	18:6a4db94011d3	1105
sahilmgandhi	18:6a4db94011d3	1106	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	1107	__HAL_LPTIM_START_CONTINUOUS(hlptim);
sahilmgandhi	18:6a4db94011d3	1108
sahilmgandhi	18:6a4db94011d3	1109	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1110	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1111
sahilmgandhi	18:6a4db94011d3	1112	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1113	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1114	}
sahilmgandhi	18:6a4db94011d3	1115
sahilmgandhi	18:6a4db94011d3	1116	/**
sahilmgandhi	18:6a4db94011d3	1117	* @brief Stops the Timeout function.
sahilmgandhi	18:6a4db94011d3	1118	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1119	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1120	*/
sahilmgandhi	18:6a4db94011d3	1121	HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1122	{
sahilmgandhi	18:6a4db94011d3	1123	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1124	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1125
sahilmgandhi	18:6a4db94011d3	1126	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1127	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1128
sahilmgandhi	18:6a4db94011d3	1129	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1130	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1131
sahilmgandhi	18:6a4db94011d3	1132	/* Reset TIMOUT bit to enable the timeout function */
sahilmgandhi	18:6a4db94011d3	1133	hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
sahilmgandhi	18:6a4db94011d3	1134
sahilmgandhi	18:6a4db94011d3	1135	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1136	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1137
sahilmgandhi	18:6a4db94011d3	1138	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1139	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1140	}
sahilmgandhi	18:6a4db94011d3	1141
sahilmgandhi	18:6a4db94011d3	1142	/**
sahilmgandhi	18:6a4db94011d3	1143	* @brief Starts the Timeout function in interrupt mode. The first trigger
sahilmgandhi	18:6a4db94011d3	1144	* event will start the timer, any successive trigger event will reset
sahilmgandhi	18:6a4db94011d3	1145	* the counter and the timer restarts.
sahilmgandhi	18:6a4db94011d3	1146	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1147	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	1148	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	1149	* @param Timeout : Specifies the TimeOut value to rest the counter.
sahilmgandhi	18:6a4db94011d3	1150	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	1151	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1152	*/
sahilmgandhi	18:6a4db94011d3	1153	HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout)
sahilmgandhi	18:6a4db94011d3	1154	{
sahilmgandhi	18:6a4db94011d3	1155	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1156	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1157	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	1158	assert_param(IS_LPTIM_PULSE(Timeout));
sahilmgandhi	18:6a4db94011d3	1159
sahilmgandhi	18:6a4db94011d3	1160	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1161	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1162
sahilmgandhi	18:6a4db94011d3	1163	/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
sahilmgandhi	18:6a4db94011d3	1164	__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
sahilmgandhi	18:6a4db94011d3	1165
sahilmgandhi	18:6a4db94011d3	1166	/* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
sahilmgandhi	18:6a4db94011d3	1167	__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
sahilmgandhi	18:6a4db94011d3	1168
sahilmgandhi	18:6a4db94011d3	1169	/* Set TIMOUT bit to enable the timeout function */
sahilmgandhi	18:6a4db94011d3	1170	hlptim->Instance->CFGR \|= LPTIM_CFGR_TIMOUT;
sahilmgandhi	18:6a4db94011d3	1171
sahilmgandhi	18:6a4db94011d3	1172	/* Enable Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	1173	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
sahilmgandhi	18:6a4db94011d3	1174
sahilmgandhi	18:6a4db94011d3	1175	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1176	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1177
sahilmgandhi	18:6a4db94011d3	1178	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	1179	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	1180
sahilmgandhi	18:6a4db94011d3	1181	/* Load the Timeout value in the compare register */
sahilmgandhi	18:6a4db94011d3	1182	__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
sahilmgandhi	18:6a4db94011d3	1183
sahilmgandhi	18:6a4db94011d3	1184	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	1185	__HAL_LPTIM_START_CONTINUOUS(hlptim);
sahilmgandhi	18:6a4db94011d3	1186
sahilmgandhi	18:6a4db94011d3	1187	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1188	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1189
sahilmgandhi	18:6a4db94011d3	1190	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1191	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1192	}
sahilmgandhi	18:6a4db94011d3	1193
sahilmgandhi	18:6a4db94011d3	1194	/**
sahilmgandhi	18:6a4db94011d3	1195	* @brief Stops the Timeout function in interrupt mode.
sahilmgandhi	18:6a4db94011d3	1196	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1197	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1198	*/
sahilmgandhi	18:6a4db94011d3	1199	HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1200	{
sahilmgandhi	18:6a4db94011d3	1201	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1202	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1203
sahilmgandhi	18:6a4db94011d3	1204	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1205	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1206
sahilmgandhi	18:6a4db94011d3	1207	/* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
sahilmgandhi	18:6a4db94011d3	1208	__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
sahilmgandhi	18:6a4db94011d3	1209
sahilmgandhi	18:6a4db94011d3	1210	/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
sahilmgandhi	18:6a4db94011d3	1211	__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
sahilmgandhi	18:6a4db94011d3	1212
sahilmgandhi	18:6a4db94011d3	1213	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1214	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1215
sahilmgandhi	18:6a4db94011d3	1216	/* Reset TIMOUT bit to enable the timeout function */
sahilmgandhi	18:6a4db94011d3	1217	hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
sahilmgandhi	18:6a4db94011d3	1218
sahilmgandhi	18:6a4db94011d3	1219	/* Disable Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	1220	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
sahilmgandhi	18:6a4db94011d3	1221
sahilmgandhi	18:6a4db94011d3	1222	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1223	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1224
sahilmgandhi	18:6a4db94011d3	1225	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1226	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1227	}
sahilmgandhi	18:6a4db94011d3	1228
sahilmgandhi	18:6a4db94011d3	1229	/**
sahilmgandhi	18:6a4db94011d3	1230	* @brief Starts the Counter mode.
sahilmgandhi	18:6a4db94011d3	1231	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1232	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	1233	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	1234	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1235	*/
sahilmgandhi	18:6a4db94011d3	1236	HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
sahilmgandhi	18:6a4db94011d3	1237	{
sahilmgandhi	18:6a4db94011d3	1238	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1239	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1240	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	1241
sahilmgandhi	18:6a4db94011d3	1242	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1243	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1244
sahilmgandhi	18:6a4db94011d3	1245	/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
sahilmgandhi	18:6a4db94011d3	1246	if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
sahilmgandhi	18:6a4db94011d3	1247	{
sahilmgandhi	18:6a4db94011d3	1248	/* Check if clock is prescaled */
sahilmgandhi	18:6a4db94011d3	1249	assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
sahilmgandhi	18:6a4db94011d3	1250	/* Set clock prescaler to 0 */
sahilmgandhi	18:6a4db94011d3	1251	hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
sahilmgandhi	18:6a4db94011d3	1252	}
sahilmgandhi	18:6a4db94011d3	1253
sahilmgandhi	18:6a4db94011d3	1254	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1255	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1256
sahilmgandhi	18:6a4db94011d3	1257	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	1258	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	1259
sahilmgandhi	18:6a4db94011d3	1260	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	1261	__HAL_LPTIM_START_CONTINUOUS(hlptim);
sahilmgandhi	18:6a4db94011d3	1262
sahilmgandhi	18:6a4db94011d3	1263	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1264	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1265
sahilmgandhi	18:6a4db94011d3	1266	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1267	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1268	}
sahilmgandhi	18:6a4db94011d3	1269
sahilmgandhi	18:6a4db94011d3	1270	/**
sahilmgandhi	18:6a4db94011d3	1271	* @brief Stops the Counter mode.
sahilmgandhi	18:6a4db94011d3	1272	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1273	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1274	*/
sahilmgandhi	18:6a4db94011d3	1275	HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1276	{
sahilmgandhi	18:6a4db94011d3	1277	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1278	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1279
sahilmgandhi	18:6a4db94011d3	1280	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1281	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1282
sahilmgandhi	18:6a4db94011d3	1283	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1284	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1285
sahilmgandhi	18:6a4db94011d3	1286	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1287	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1288
sahilmgandhi	18:6a4db94011d3	1289	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1290	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1291	}
sahilmgandhi	18:6a4db94011d3	1292
sahilmgandhi	18:6a4db94011d3	1293	/**
sahilmgandhi	18:6a4db94011d3	1294	* @brief Starts the Counter mode in interrupt mode.
sahilmgandhi	18:6a4db94011d3	1295	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1296	* @param Period : Specifies the Autoreload value.
sahilmgandhi	18:6a4db94011d3	1297	* This parameter must be a value between 0x0000 and 0xFFFF.
sahilmgandhi	18:6a4db94011d3	1298	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1299	*/
sahilmgandhi	18:6a4db94011d3	1300	HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
sahilmgandhi	18:6a4db94011d3	1301	{
sahilmgandhi	18:6a4db94011d3	1302	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1303	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1304	assert_param(IS_LPTIM_PERIOD(Period));
sahilmgandhi	18:6a4db94011d3	1305
sahilmgandhi	18:6a4db94011d3	1306	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1307	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1308
sahilmgandhi	18:6a4db94011d3	1309	/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
sahilmgandhi	18:6a4db94011d3	1310	__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
sahilmgandhi	18:6a4db94011d3	1311
sahilmgandhi	18:6a4db94011d3	1312	/* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
sahilmgandhi	18:6a4db94011d3	1313	__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
sahilmgandhi	18:6a4db94011d3	1314
sahilmgandhi	18:6a4db94011d3	1315	/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
sahilmgandhi	18:6a4db94011d3	1316	if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
sahilmgandhi	18:6a4db94011d3	1317	{
sahilmgandhi	18:6a4db94011d3	1318	/* Check if clock is prescaled */
sahilmgandhi	18:6a4db94011d3	1319	assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
sahilmgandhi	18:6a4db94011d3	1320	/* Set clock prescaler to 0 */
sahilmgandhi	18:6a4db94011d3	1321	hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
sahilmgandhi	18:6a4db94011d3	1322	}
sahilmgandhi	18:6a4db94011d3	1323
sahilmgandhi	18:6a4db94011d3	1324	/* Enable Autoreload write complete interrupt */
sahilmgandhi	18:6a4db94011d3	1325	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
sahilmgandhi	18:6a4db94011d3	1326
sahilmgandhi	18:6a4db94011d3	1327	/* Enable Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	1328	__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM);
sahilmgandhi	18:6a4db94011d3	1329
sahilmgandhi	18:6a4db94011d3	1330	/* Enable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1331	__HAL_LPTIM_ENABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1332
sahilmgandhi	18:6a4db94011d3	1333	/* Load the period value in the autoreload register */
sahilmgandhi	18:6a4db94011d3	1334	__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
sahilmgandhi	18:6a4db94011d3	1335
sahilmgandhi	18:6a4db94011d3	1336	/* Start timer in continuous mode */
sahilmgandhi	18:6a4db94011d3	1337	__HAL_LPTIM_START_CONTINUOUS(hlptim);
sahilmgandhi	18:6a4db94011d3	1338
sahilmgandhi	18:6a4db94011d3	1339	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1340	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1341
sahilmgandhi	18:6a4db94011d3	1342	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1343	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1344	}
sahilmgandhi	18:6a4db94011d3	1345
sahilmgandhi	18:6a4db94011d3	1346	/**
sahilmgandhi	18:6a4db94011d3	1347	* @brief Stops the Counter mode in interrupt mode.
sahilmgandhi	18:6a4db94011d3	1348	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1349	* @retval HAL status
sahilmgandhi	18:6a4db94011d3	1350	*/
sahilmgandhi	18:6a4db94011d3	1351	HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1352	{
sahilmgandhi	18:6a4db94011d3	1353	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1354	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1355
sahilmgandhi	18:6a4db94011d3	1356	/* Set the LPTIM state */
sahilmgandhi	18:6a4db94011d3	1357	hlptim->State= HAL_LPTIM_STATE_BUSY;
sahilmgandhi	18:6a4db94011d3	1358
sahilmgandhi	18:6a4db94011d3	1359	/* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
sahilmgandhi	18:6a4db94011d3	1360	__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
sahilmgandhi	18:6a4db94011d3	1361
sahilmgandhi	18:6a4db94011d3	1362	/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
sahilmgandhi	18:6a4db94011d3	1363	__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
sahilmgandhi	18:6a4db94011d3	1364
sahilmgandhi	18:6a4db94011d3	1365	/* Disable the Peripheral */
sahilmgandhi	18:6a4db94011d3	1366	__HAL_LPTIM_DISABLE(hlptim);
sahilmgandhi	18:6a4db94011d3	1367
sahilmgandhi	18:6a4db94011d3	1368	/* Disable Autoreload write complete interrupt */
sahilmgandhi	18:6a4db94011d3	1369	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
sahilmgandhi	18:6a4db94011d3	1370
sahilmgandhi	18:6a4db94011d3	1371	/* Disable Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	1372	__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
sahilmgandhi	18:6a4db94011d3	1373
sahilmgandhi	18:6a4db94011d3	1374	/* Change the TIM state*/
sahilmgandhi	18:6a4db94011d3	1375	hlptim->State= HAL_LPTIM_STATE_READY;
sahilmgandhi	18:6a4db94011d3	1376
sahilmgandhi	18:6a4db94011d3	1377	/* Return function status */
sahilmgandhi	18:6a4db94011d3	1378	return HAL_OK;
sahilmgandhi	18:6a4db94011d3	1379	}
sahilmgandhi	18:6a4db94011d3	1380
sahilmgandhi	18:6a4db94011d3	1381	/**
sahilmgandhi	18:6a4db94011d3	1382	* @}
sahilmgandhi	18:6a4db94011d3	1383	*/
sahilmgandhi	18:6a4db94011d3	1384
sahilmgandhi	18:6a4db94011d3	1385	/** @defgroup LPTIM_Group3 LPTIM Read operation functions
sahilmgandhi	18:6a4db94011d3	1386	* @brief Read operation functions.
sahilmgandhi	18:6a4db94011d3	1387	*
sahilmgandhi	18:6a4db94011d3	1388	@verbatim
sahilmgandhi	18:6a4db94011d3	1389	==============================================================================
sahilmgandhi	18:6a4db94011d3	1390	##### LPTIM Read operation functions #####
sahilmgandhi	18:6a4db94011d3	1391	==============================================================================
sahilmgandhi	18:6a4db94011d3	1392	[..] This section provides LPTIM Reading functions.
sahilmgandhi	18:6a4db94011d3	1393	(+) Read the counter value.
sahilmgandhi	18:6a4db94011d3	1394	(+) Read the period (Auto-reload) value.
sahilmgandhi	18:6a4db94011d3	1395	(+) Read the pulse (Compare)value.
sahilmgandhi	18:6a4db94011d3	1396	@endverbatim
sahilmgandhi	18:6a4db94011d3	1397	* @{
sahilmgandhi	18:6a4db94011d3	1398	*/
sahilmgandhi	18:6a4db94011d3	1399
sahilmgandhi	18:6a4db94011d3	1400	/**
sahilmgandhi	18:6a4db94011d3	1401	* @brief This function returns the current counter value.
sahilmgandhi	18:6a4db94011d3	1402	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	1403	* @retval Counter value.
sahilmgandhi	18:6a4db94011d3	1404	*/
sahilmgandhi	18:6a4db94011d3	1405	uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1406	{
sahilmgandhi	18:6a4db94011d3	1407	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1408	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1409
sahilmgandhi	18:6a4db94011d3	1410	return (hlptim->Instance->CNT);
sahilmgandhi	18:6a4db94011d3	1411	}
sahilmgandhi	18:6a4db94011d3	1412
sahilmgandhi	18:6a4db94011d3	1413	/**
sahilmgandhi	18:6a4db94011d3	1414	* @brief This function return the current Autoreload (Period) value.
sahilmgandhi	18:6a4db94011d3	1415	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	1416	* @retval Autoreload value.
sahilmgandhi	18:6a4db94011d3	1417	*/
sahilmgandhi	18:6a4db94011d3	1418	uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1419	{
sahilmgandhi	18:6a4db94011d3	1420	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1421	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1422
sahilmgandhi	18:6a4db94011d3	1423	return (hlptim->Instance->ARR);
sahilmgandhi	18:6a4db94011d3	1424	}
sahilmgandhi	18:6a4db94011d3	1425
sahilmgandhi	18:6a4db94011d3	1426	/**
sahilmgandhi	18:6a4db94011d3	1427	* @brief This function return the current Compare (Pulse) value.
sahilmgandhi	18:6a4db94011d3	1428	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	1429	* @retval Compare value.
sahilmgandhi	18:6a4db94011d3	1430	*/
sahilmgandhi	18:6a4db94011d3	1431	uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1432	{
sahilmgandhi	18:6a4db94011d3	1433	/* Check the parameters */
sahilmgandhi	18:6a4db94011d3	1434	assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
sahilmgandhi	18:6a4db94011d3	1435
sahilmgandhi	18:6a4db94011d3	1436	return (hlptim->Instance->CMP);
sahilmgandhi	18:6a4db94011d3	1437	}
sahilmgandhi	18:6a4db94011d3	1438
sahilmgandhi	18:6a4db94011d3	1439	/**
sahilmgandhi	18:6a4db94011d3	1440	* @}
sahilmgandhi	18:6a4db94011d3	1441	*/
sahilmgandhi	18:6a4db94011d3	1442
sahilmgandhi	18:6a4db94011d3	1443
sahilmgandhi	18:6a4db94011d3	1444
sahilmgandhi	18:6a4db94011d3	1445	/** @defgroup LPTIM_Group4 LPTIM IRQ handler
sahilmgandhi	18:6a4db94011d3	1446	* @brief LPTIM IRQ handler.
sahilmgandhi	18:6a4db94011d3	1447	*
sahilmgandhi	18:6a4db94011d3	1448	@verbatim
sahilmgandhi	18:6a4db94011d3	1449	==============================================================================
sahilmgandhi	18:6a4db94011d3	1450	##### LPTIM IRQ handler #####
sahilmgandhi	18:6a4db94011d3	1451	==============================================================================
sahilmgandhi	18:6a4db94011d3	1452	[..] This section provides LPTIM IRQ handler function.
sahilmgandhi	18:6a4db94011d3	1453
sahilmgandhi	18:6a4db94011d3	1454	@endverbatim
sahilmgandhi	18:6a4db94011d3	1455	* @{
sahilmgandhi	18:6a4db94011d3	1456	*/
sahilmgandhi	18:6a4db94011d3	1457
sahilmgandhi	18:6a4db94011d3	1458	/**
sahilmgandhi	18:6a4db94011d3	1459	* @brief This function handles LPTIM interrupt request.
sahilmgandhi	18:6a4db94011d3	1460	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	1461	* @retval None
sahilmgandhi	18:6a4db94011d3	1462	*/
sahilmgandhi	18:6a4db94011d3	1463	void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1464	{
sahilmgandhi	18:6a4db94011d3	1465	/* Compare match interrupt */
sahilmgandhi	18:6a4db94011d3	1466	if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET)
sahilmgandhi	18:6a4db94011d3	1467	{
sahilmgandhi	18:6a4db94011d3	1468	if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET)
sahilmgandhi	18:6a4db94011d3	1469	{
sahilmgandhi	18:6a4db94011d3	1470	/* Clear Compare match flag */
sahilmgandhi	18:6a4db94011d3	1471	__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
sahilmgandhi	18:6a4db94011d3	1472	/* Compare match Callback */
sahilmgandhi	18:6a4db94011d3	1473	HAL_LPTIM_CompareMatchCallback(hlptim);
sahilmgandhi	18:6a4db94011d3	1474	}
sahilmgandhi	18:6a4db94011d3	1475	}
sahilmgandhi	18:6a4db94011d3	1476
sahilmgandhi	18:6a4db94011d3	1477	/* Autoreload match interrupt */
sahilmgandhi	18:6a4db94011d3	1478	if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
sahilmgandhi	18:6a4db94011d3	1479	{
sahilmgandhi	18:6a4db94011d3	1480	if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET)
sahilmgandhi	18:6a4db94011d3	1481	{
sahilmgandhi	18:6a4db94011d3	1482	/* Clear Autoreload match flag */
sahilmgandhi	18:6a4db94011d3	1483	__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
sahilmgandhi	18:6a4db94011d3	1484	/* Autoreload match Callback */
sahilmgandhi	18:6a4db94011d3	1485	HAL_LPTIM_AutoReloadMatchCallback(hlptim);
sahilmgandhi	18:6a4db94011d3	1486	}
sahilmgandhi	18:6a4db94011d3	1487	}
sahilmgandhi	18:6a4db94011d3	1488
sahilmgandhi	18:6a4db94011d3	1489	/* Trigger detected interrupt */
sahilmgandhi	18:6a4db94011d3	1490	if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
sahilmgandhi	18:6a4db94011d3	1491	{
sahilmgandhi	18:6a4db94011d3	1492	if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET)
sahilmgandhi	18:6a4db94011d3	1493	{
sahilmgandhi	18:6a4db94011d3	1494	/* Clear Trigger detected flag */
sahilmgandhi	18:6a4db94011d3	1495	__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
sahilmgandhi	18:6a4db94011d3	1496	/* Trigger detected callback */
sahilmgandhi	18:6a4db94011d3	1497	HAL_LPTIM_TriggerCallback(hlptim);
sahilmgandhi	18:6a4db94011d3	1498	}
sahilmgandhi	18:6a4db94011d3	1499	}
sahilmgandhi	18:6a4db94011d3	1500
sahilmgandhi	18:6a4db94011d3	1501	/* Compare write interrupt */
sahilmgandhi	18:6a4db94011d3	1502	if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET)
sahilmgandhi	18:6a4db94011d3	1503	{
sahilmgandhi	18:6a4db94011d3	1504	if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET)
sahilmgandhi	18:6a4db94011d3	1505	{
sahilmgandhi	18:6a4db94011d3	1506	/* Clear Compare write flag */
sahilmgandhi	18:6a4db94011d3	1507	__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
sahilmgandhi	18:6a4db94011d3	1508	/* Compare write Callback */
sahilmgandhi	18:6a4db94011d3	1509	HAL_LPTIM_CompareWriteCallback(hlptim);
sahilmgandhi	18:6a4db94011d3	1510	}
sahilmgandhi	18:6a4db94011d3	1511	}
sahilmgandhi	18:6a4db94011d3	1512
sahilmgandhi	18:6a4db94011d3	1513	/* Autoreload write interrupt */
sahilmgandhi	18:6a4db94011d3	1514	if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
sahilmgandhi	18:6a4db94011d3	1515	{
sahilmgandhi	18:6a4db94011d3	1516	if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET)
sahilmgandhi	18:6a4db94011d3	1517	{
sahilmgandhi	18:6a4db94011d3	1518	/* Clear Autoreload write flag */
sahilmgandhi	18:6a4db94011d3	1519	__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
sahilmgandhi	18:6a4db94011d3	1520	/* Autoreload write Callback */
sahilmgandhi	18:6a4db94011d3	1521	HAL_LPTIM_AutoReloadWriteCallback(hlptim);
sahilmgandhi	18:6a4db94011d3	1522	}
sahilmgandhi	18:6a4db94011d3	1523	}
sahilmgandhi	18:6a4db94011d3	1524
sahilmgandhi	18:6a4db94011d3	1525	/* Direction counter changed from Down to Up interrupt */
sahilmgandhi	18:6a4db94011d3	1526	if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
sahilmgandhi	18:6a4db94011d3	1527	{
sahilmgandhi	18:6a4db94011d3	1528	if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET)
sahilmgandhi	18:6a4db94011d3	1529	{
sahilmgandhi	18:6a4db94011d3	1530	/* Clear Direction counter changed from Down to Up flag */
sahilmgandhi	18:6a4db94011d3	1531	__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
sahilmgandhi	18:6a4db94011d3	1532	/* Direction counter changed from Down to Up Callback */
sahilmgandhi	18:6a4db94011d3	1533	HAL_LPTIM_DirectionUpCallback(hlptim);
sahilmgandhi	18:6a4db94011d3	1534	}
sahilmgandhi	18:6a4db94011d3	1535	}
sahilmgandhi	18:6a4db94011d3	1536
sahilmgandhi	18:6a4db94011d3	1537	/* Direction counter changed from Up to Down interrupt */
sahilmgandhi	18:6a4db94011d3	1538	if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
sahilmgandhi	18:6a4db94011d3	1539	{
sahilmgandhi	18:6a4db94011d3	1540	if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET)
sahilmgandhi	18:6a4db94011d3	1541	{
sahilmgandhi	18:6a4db94011d3	1542	/* Clear Direction counter changed from Up to Down flag */
sahilmgandhi	18:6a4db94011d3	1543	__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
sahilmgandhi	18:6a4db94011d3	1544	/* Direction counter changed from Up to Down Callback */
sahilmgandhi	18:6a4db94011d3	1545	HAL_LPTIM_DirectionDownCallback(hlptim);
sahilmgandhi	18:6a4db94011d3	1546	}
sahilmgandhi	18:6a4db94011d3	1547	}
sahilmgandhi	18:6a4db94011d3	1548	__HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
sahilmgandhi	18:6a4db94011d3	1549	}
sahilmgandhi	18:6a4db94011d3	1550
sahilmgandhi	18:6a4db94011d3	1551	/**
sahilmgandhi	18:6a4db94011d3	1552	* @brief Compare match callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	1553	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1554	* @retval None
sahilmgandhi	18:6a4db94011d3	1555	*/
sahilmgandhi	18:6a4db94011d3	1556	__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1557	{
sahilmgandhi	18:6a4db94011d3	1558	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1559	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	1560	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1561	the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1562	*/
sahilmgandhi	18:6a4db94011d3	1563	}
sahilmgandhi	18:6a4db94011d3	1564
sahilmgandhi	18:6a4db94011d3	1565	/**
sahilmgandhi	18:6a4db94011d3	1566	* @brief Autoreload match callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	1567	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1568	* @retval None
sahilmgandhi	18:6a4db94011d3	1569	*/
sahilmgandhi	18:6a4db94011d3	1570	__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1571	{
sahilmgandhi	18:6a4db94011d3	1572	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1573	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	1574	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1575	the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1576	*/
sahilmgandhi	18:6a4db94011d3	1577	}
sahilmgandhi	18:6a4db94011d3	1578
sahilmgandhi	18:6a4db94011d3	1579	/**
sahilmgandhi	18:6a4db94011d3	1580	* @brief Trigger detected callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	1581	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1582	* @retval None
sahilmgandhi	18:6a4db94011d3	1583	*/
sahilmgandhi	18:6a4db94011d3	1584	__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1585	{
sahilmgandhi	18:6a4db94011d3	1586	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1587	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	1588	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1589	the HAL_LPTIM_TriggerCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1590	*/
sahilmgandhi	18:6a4db94011d3	1591	}
sahilmgandhi	18:6a4db94011d3	1592
sahilmgandhi	18:6a4db94011d3	1593	/**
sahilmgandhi	18:6a4db94011d3	1594	* @brief Compare write callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	1595	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1596	* @retval None
sahilmgandhi	18:6a4db94011d3	1597	*/
sahilmgandhi	18:6a4db94011d3	1598	__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1599	{
sahilmgandhi	18:6a4db94011d3	1600	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1601	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	1602	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1603	the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1604	*/
sahilmgandhi	18:6a4db94011d3	1605	}
sahilmgandhi	18:6a4db94011d3	1606
sahilmgandhi	18:6a4db94011d3	1607	/**
sahilmgandhi	18:6a4db94011d3	1608	* @brief Autoreload write callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	1609	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1610	* @retval None
sahilmgandhi	18:6a4db94011d3	1611	*/
sahilmgandhi	18:6a4db94011d3	1612	__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1613	{
sahilmgandhi	18:6a4db94011d3	1614	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1615	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	1616	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1617	the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1618	*/
sahilmgandhi	18:6a4db94011d3	1619	}
sahilmgandhi	18:6a4db94011d3	1620
sahilmgandhi	18:6a4db94011d3	1621	/**
sahilmgandhi	18:6a4db94011d3	1622	* @brief Direction counter changed from Down to Up callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	1623	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1624	* @retval None
sahilmgandhi	18:6a4db94011d3	1625	*/
sahilmgandhi	18:6a4db94011d3	1626	__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1627	{
sahilmgandhi	18:6a4db94011d3	1628	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1629	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	1630	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1631	the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1632	*/
sahilmgandhi	18:6a4db94011d3	1633	}
sahilmgandhi	18:6a4db94011d3	1634
sahilmgandhi	18:6a4db94011d3	1635	/**
sahilmgandhi	18:6a4db94011d3	1636	* @brief Direction counter changed from Up to Down callback in non blocking mode
sahilmgandhi	18:6a4db94011d3	1637	* @param hlptim : LPTIM handle
sahilmgandhi	18:6a4db94011d3	1638	* @retval None
sahilmgandhi	18:6a4db94011d3	1639	*/
sahilmgandhi	18:6a4db94011d3	1640	__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1641	{
sahilmgandhi	18:6a4db94011d3	1642	/* Prevent unused argument(s) compilation warning */
sahilmgandhi	18:6a4db94011d3	1643	UNUSED(hlptim);
sahilmgandhi	18:6a4db94011d3	1644	/* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi	18:6a4db94011d3	1645	the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
sahilmgandhi	18:6a4db94011d3	1646	*/
sahilmgandhi	18:6a4db94011d3	1647	}
sahilmgandhi	18:6a4db94011d3	1648
sahilmgandhi	18:6a4db94011d3	1649	/**
sahilmgandhi	18:6a4db94011d3	1650	* @}
sahilmgandhi	18:6a4db94011d3	1651	*/
sahilmgandhi	18:6a4db94011d3	1652
sahilmgandhi	18:6a4db94011d3	1653	/** @defgroup LPTIM_Group5 Peripheral State functions
sahilmgandhi	18:6a4db94011d3	1654	* @brief Peripheral State functions.
sahilmgandhi	18:6a4db94011d3	1655	*
sahilmgandhi	18:6a4db94011d3	1656	@verbatim
sahilmgandhi	18:6a4db94011d3	1657	==============================================================================
sahilmgandhi	18:6a4db94011d3	1658	##### Peripheral State functions #####
sahilmgandhi	18:6a4db94011d3	1659	==============================================================================
sahilmgandhi	18:6a4db94011d3	1660	[..]
sahilmgandhi	18:6a4db94011d3	1661	This subsection permits to get in run-time the status of the peripheral.
sahilmgandhi	18:6a4db94011d3	1662
sahilmgandhi	18:6a4db94011d3	1663	@endverbatim
sahilmgandhi	18:6a4db94011d3	1664	* @{
sahilmgandhi	18:6a4db94011d3	1665	*/
sahilmgandhi	18:6a4db94011d3	1666
sahilmgandhi	18:6a4db94011d3	1667	/**
sahilmgandhi	18:6a4db94011d3	1668	* @brief Returns the LPTIM state.
sahilmgandhi	18:6a4db94011d3	1669	* @param hlptim: LPTIM handle
sahilmgandhi	18:6a4db94011d3	1670	* @retval HAL state
sahilmgandhi	18:6a4db94011d3	1671	*/
sahilmgandhi	18:6a4db94011d3	1672	HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
sahilmgandhi	18:6a4db94011d3	1673	{
sahilmgandhi	18:6a4db94011d3	1674	return hlptim->State;
sahilmgandhi	18:6a4db94011d3	1675	}
sahilmgandhi	18:6a4db94011d3	1676
sahilmgandhi	18:6a4db94011d3	1677	/**
sahilmgandhi	18:6a4db94011d3	1678	* @}
sahilmgandhi	18:6a4db94011d3	1679	*/
sahilmgandhi	18:6a4db94011d3	1680
sahilmgandhi	18:6a4db94011d3	1681
sahilmgandhi	18:6a4db94011d3	1682	/**
sahilmgandhi	18:6a4db94011d3	1683	* @}
sahilmgandhi	18:6a4db94011d3	1684	*/
sahilmgandhi	18:6a4db94011d3	1685
sahilmgandhi	18:6a4db94011d3	1686	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
sahilmgandhi	18:6a4db94011d3	1687	#endif /* HAL_LPTIM_MODULE_ENABLED */
sahilmgandhi	18:6a4db94011d3	1688	/**
sahilmgandhi	18:6a4db94011d3	1689	* @}
sahilmgandhi	18:6a4db94011d3	1690	*/
sahilmgandhi	18:6a4db94011d3	1691
sahilmgandhi	18:6a4db94011d3	1692	/**
sahilmgandhi	18:6a4db94011d3	1693	* @}
sahilmgandhi	18:6a4db94011d3	1694	*/
sahilmgandhi	18:6a4db94011d3	1695
sahilmgandhi	18:6a4db94011d3	1696	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c@46:b156ef445742, 2017-06-03 (annotated)

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