MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_i2s_ex.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief I2S HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 9 * functionalities of I2S extension peripheral:
sahilmgandhi 18:6a4db94011d3 10 * + Extension features Functions
sahilmgandhi 18:6a4db94011d3 11 *
sahilmgandhi 18:6a4db94011d3 12 @verbatim
sahilmgandhi 18:6a4db94011d3 13 ==============================================================================
sahilmgandhi 18:6a4db94011d3 14 ##### I2S Extension features #####
sahilmgandhi 18:6a4db94011d3 15 ==============================================================================
sahilmgandhi 18:6a4db94011d3 16 [..]
sahilmgandhi 18:6a4db94011d3 17 (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
sahilmgandhi 18:6a4db94011d3 18 data simultaneously using two data lines. Each SPI peripheral has an extended block
sahilmgandhi 18:6a4db94011d3 19 called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
sahilmgandhi 18:6a4db94011d3 20 (#) The extension block is not a full SPI IP, it is used only as I2S slave to
sahilmgandhi 18:6a4db94011d3 21 implement full duplex mode. The extension block uses the same clock sources
sahilmgandhi 18:6a4db94011d3 22 as its master.
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
sahilmgandhi 18:6a4db94011d3 25
sahilmgandhi 18:6a4db94011d3 26 [..]
sahilmgandhi 18:6a4db94011d3 27 (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
sahilmgandhi 18:6a4db94011d3 28 I2Sx can be I2S2 or I2S3.
sahilmgandhi 18:6a4db94011d3 29
sahilmgandhi 18:6a4db94011d3 30 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 31 ===============================================================================
sahilmgandhi 18:6a4db94011d3 32 [..]
sahilmgandhi 18:6a4db94011d3 33 Three operation modes are available within this driver :
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 *** Polling mode IO operation ***
sahilmgandhi 18:6a4db94011d3 36 =================================
sahilmgandhi 18:6a4db94011d3 37 [..]
sahilmgandhi 18:6a4db94011d3 38 (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 *** Interrupt mode IO operation ***
sahilmgandhi 18:6a4db94011d3 41 ===================================
sahilmgandhi 18:6a4db94011d3 42 [..]
sahilmgandhi 18:6a4db94011d3 43 (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
sahilmgandhi 18:6a4db94011d3 44 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 45 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 46 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 47 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
sahilmgandhi 18:6a4db94011d3 48 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 49 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 50 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 51 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
sahilmgandhi 18:6a4db94011d3 52 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 53 add his own code by customization of function pointer HAL_I2S_ErrorCallback
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 *** DMA mode IO operation ***
sahilmgandhi 18:6a4db94011d3 56 ==============================
sahilmgandhi 18:6a4db94011d3 57 [..]
sahilmgandhi 18:6a4db94011d3 58 (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
sahilmgandhi 18:6a4db94011d3 59 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 60 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 61 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 62 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
sahilmgandhi 18:6a4db94011d3 63 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 64 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 65 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 66 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
sahilmgandhi 18:6a4db94011d3 67 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 68 add his own code by customization of function pointer HAL_I2S_ErrorCallback
sahilmgandhi 18:6a4db94011d3 69 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
sahilmgandhi 18:6a4db94011d3 70 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
sahilmgandhi 18:6a4db94011d3 71 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 @endverbatim
sahilmgandhi 18:6a4db94011d3 74 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 75 * @attention
sahilmgandhi 18:6a4db94011d3 76 *
sahilmgandhi 18:6a4db94011d3 77 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 78 *
sahilmgandhi 18:6a4db94011d3 79 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 80 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 81 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 82 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 83 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 84 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 85 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 86 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 87 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 88 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 89 *
sahilmgandhi 18:6a4db94011d3 90 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 91 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 92 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 93 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 94 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 95 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 96 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 97 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 98 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 99 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 100 *
sahilmgandhi 18:6a4db94011d3 101 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 102 */
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 105 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 106
sahilmgandhi 18:6a4db94011d3 107 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 108 * @{
sahilmgandhi 18:6a4db94011d3 109 */
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /** @defgroup I2SEx I2SEx
sahilmgandhi 18:6a4db94011d3 112 * @brief I2S HAL module driver
sahilmgandhi 18:6a4db94011d3 113 * @{
sahilmgandhi 18:6a4db94011d3 114 */
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 #ifdef HAL_I2S_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 117 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 118 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 119 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 120 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 121 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 122 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 123 /** @addtogroup I2SEx_Private_Functions
sahilmgandhi 18:6a4db94011d3 124 * @{
sahilmgandhi 18:6a4db94011d3 125 */
sahilmgandhi 18:6a4db94011d3 126 /**
sahilmgandhi 18:6a4db94011d3 127 * @}
sahilmgandhi 18:6a4db94011d3 128 */
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 131 /** @defgroup I2SEx_Exported_Functions I2S Exported Functions
sahilmgandhi 18:6a4db94011d3 132 * @{
sahilmgandhi 18:6a4db94011d3 133 */
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 /** @defgroup I2SEx_Group1 Extension features functions
sahilmgandhi 18:6a4db94011d3 136 * @brief Extension features functions
sahilmgandhi 18:6a4db94011d3 137 *
sahilmgandhi 18:6a4db94011d3 138 @verbatim
sahilmgandhi 18:6a4db94011d3 139 ===============================================================================
sahilmgandhi 18:6a4db94011d3 140 ##### Extension features Functions #####
sahilmgandhi 18:6a4db94011d3 141 ===============================================================================
sahilmgandhi 18:6a4db94011d3 142 [..]
sahilmgandhi 18:6a4db94011d3 143 This subsection provides a set of functions allowing to manage the I2S data
sahilmgandhi 18:6a4db94011d3 144 transfers.
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 (#) There are two modes of transfer:
sahilmgandhi 18:6a4db94011d3 147 (++) Blocking mode : The communication is performed in the polling mode.
sahilmgandhi 18:6a4db94011d3 148 The status of all data processing is returned by the same function
sahilmgandhi 18:6a4db94011d3 149 after finishing transfer.
sahilmgandhi 18:6a4db94011d3 150 (++) No-Blocking mode : The communication is performed using Interrupts
sahilmgandhi 18:6a4db94011d3 151 or DMA. These functions return the status of the transfer startup.
sahilmgandhi 18:6a4db94011d3 152 The end of the data processing will be indicated through the
sahilmgandhi 18:6a4db94011d3 153 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
sahilmgandhi 18:6a4db94011d3 154 using DMA mode.
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 (#) Blocking mode functions are :
sahilmgandhi 18:6a4db94011d3 157 (++) HAL_I2S_TransmitReceive()
sahilmgandhi 18:6a4db94011d3 158
sahilmgandhi 18:6a4db94011d3 159 (#) No-Blocking mode functions with Interrupt are :
sahilmgandhi 18:6a4db94011d3 160 (++) HAL_I2S_TransmitReceive_IT()
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 (#) No-Blocking mode functions with DMA are :
sahilmgandhi 18:6a4db94011d3 163 (++) HAL_I2S_TransmitReceive_DMA()
sahilmgandhi 18:6a4db94011d3 164
sahilmgandhi 18:6a4db94011d3 165 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
sahilmgandhi 18:6a4db94011d3 166 (++) HAL_I2S_TxCpltCallback()
sahilmgandhi 18:6a4db94011d3 167 (++) HAL_I2S_RxCpltCallback()
sahilmgandhi 18:6a4db94011d3 168 (++) HAL_I2S_ErrorCallback()
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 @endverbatim
sahilmgandhi 18:6a4db94011d3 171 * @{
sahilmgandhi 18:6a4db94011d3 172 */
sahilmgandhi 18:6a4db94011d3 173 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
sahilmgandhi 18:6a4db94011d3 174 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 175 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
sahilmgandhi 18:6a4db94011d3 176 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
sahilmgandhi 18:6a4db94011d3 177 defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 178 /**
sahilmgandhi 18:6a4db94011d3 179 * @brief Initializes the I2S according to the specified parameters
sahilmgandhi 18:6a4db94011d3 180 * in the I2S_InitTypeDef and create the associated handle.
sahilmgandhi 18:6a4db94011d3 181 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 182 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 183 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 184 */
sahilmgandhi 18:6a4db94011d3 185 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 186 {
sahilmgandhi 18:6a4db94011d3 187 uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
sahilmgandhi 18:6a4db94011d3 188 uint32_t tmp = 0U, i2sclk = 0U;
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /* Check the I2S handle allocation */
sahilmgandhi 18:6a4db94011d3 191 if(hi2s == NULL)
sahilmgandhi 18:6a4db94011d3 192 {
sahilmgandhi 18:6a4db94011d3 193 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 194 }
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 /* Check the I2S parameters */
sahilmgandhi 18:6a4db94011d3 197 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
sahilmgandhi 18:6a4db94011d3 198 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
sahilmgandhi 18:6a4db94011d3 199 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
sahilmgandhi 18:6a4db94011d3 200 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
sahilmgandhi 18:6a4db94011d3 201 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
sahilmgandhi 18:6a4db94011d3 202 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
sahilmgandhi 18:6a4db94011d3 203 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 if(hi2s->State == HAL_I2S_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 206 {
sahilmgandhi 18:6a4db94011d3 207 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 208 hi2s->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 209 /* Init the low level hardware : GPIO, CLOCK, CORTEX */
sahilmgandhi 18:6a4db94011d3 210 HAL_I2S_MspInit(hi2s);
sahilmgandhi 18:6a4db94011d3 211 }
sahilmgandhi 18:6a4db94011d3 212
sahilmgandhi 18:6a4db94011d3 213 hi2s->State = HAL_I2S_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
sahilmgandhi 18:6a4db94011d3 216 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
sahilmgandhi 18:6a4db94011d3 217 hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
sahilmgandhi 18:6a4db94011d3 218 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
sahilmgandhi 18:6a4db94011d3 219 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
sahilmgandhi 18:6a4db94011d3 220 hi2s->Instance->I2SPR = 0x0002U;
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 /* Get the I2SCFGR register value */
sahilmgandhi 18:6a4db94011d3 223 tmpreg = hi2s->Instance->I2SCFGR;
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
sahilmgandhi 18:6a4db94011d3 226 /* If the requested audio frequency is not the default, compute the prescaler */
sahilmgandhi 18:6a4db94011d3 227 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229 /* Check the frame length (For the Prescaler computing) *******************/
sahilmgandhi 18:6a4db94011d3 230 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
sahilmgandhi 18:6a4db94011d3 231 {
sahilmgandhi 18:6a4db94011d3 232 /* Packet length is 32 bits */
sahilmgandhi 18:6a4db94011d3 233 packetlength = 2U;
sahilmgandhi 18:6a4db94011d3 234 }
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 /* Get I2S source Clock frequency ****************************************/
sahilmgandhi 18:6a4db94011d3 237 i2sclk = I2S_GetInputClock(hi2s);
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 /* Compute the Real divider depending on the MCLK output state, with a floating point */
sahilmgandhi 18:6a4db94011d3 240 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
sahilmgandhi 18:6a4db94011d3 241 {
sahilmgandhi 18:6a4db94011d3 242 /* MCLK output is enabled */
sahilmgandhi 18:6a4db94011d3 243 tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
sahilmgandhi 18:6a4db94011d3 244 }
sahilmgandhi 18:6a4db94011d3 245 else
sahilmgandhi 18:6a4db94011d3 246 {
sahilmgandhi 18:6a4db94011d3 247 /* MCLK output is disabled */
sahilmgandhi 18:6a4db94011d3 248 tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
sahilmgandhi 18:6a4db94011d3 249 }
sahilmgandhi 18:6a4db94011d3 250
sahilmgandhi 18:6a4db94011d3 251 /* Remove the flatting point */
sahilmgandhi 18:6a4db94011d3 252 tmp = tmp / 10U;
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 /* Check the parity of the divider */
sahilmgandhi 18:6a4db94011d3 255 i2sodd = (uint32_t)(tmp & (uint32_t)1U);
sahilmgandhi 18:6a4db94011d3 256
sahilmgandhi 18:6a4db94011d3 257 /* Compute the i2sdiv prescaler */
sahilmgandhi 18:6a4db94011d3 258 i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
sahilmgandhi 18:6a4db94011d3 261 i2sodd = (uint32_t) (i2sodd << 8U);
sahilmgandhi 18:6a4db94011d3 262 }
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 /* Test if the divider is 1 or 0 or greater than 0xFF */
sahilmgandhi 18:6a4db94011d3 265 if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
sahilmgandhi 18:6a4db94011d3 266 {
sahilmgandhi 18:6a4db94011d3 267 /* Set the default values */
sahilmgandhi 18:6a4db94011d3 268 i2sdiv = 2U;
sahilmgandhi 18:6a4db94011d3 269 i2sodd = 0U;
sahilmgandhi 18:6a4db94011d3 270 }
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /* Write to SPIx I2SPR register the computed value */
sahilmgandhi 18:6a4db94011d3 273 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /* Configure the I2S with the I2S_InitStruct values */
sahilmgandhi 18:6a4db94011d3 276 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 #if defined(SPI_I2SCFGR_ASTRTEN)
sahilmgandhi 18:6a4db94011d3 279 if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
sahilmgandhi 18:6a4db94011d3 280 {
sahilmgandhi 18:6a4db94011d3 281 /* Write to SPIx I2SCFGR */
sahilmgandhi 18:6a4db94011d3 282 hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
sahilmgandhi 18:6a4db94011d3 283 }
sahilmgandhi 18:6a4db94011d3 284 else
sahilmgandhi 18:6a4db94011d3 285 {
sahilmgandhi 18:6a4db94011d3 286 /* Write to SPIx I2SCFGR */
sahilmgandhi 18:6a4db94011d3 287 hi2s->Instance->I2SCFGR = tmpreg;
sahilmgandhi 18:6a4db94011d3 288 }
sahilmgandhi 18:6a4db94011d3 289 #else
sahilmgandhi 18:6a4db94011d3 290 /* Write to SPIx I2SCFGR */
sahilmgandhi 18:6a4db94011d3 291 hi2s->Instance->I2SCFGR = tmpreg;
sahilmgandhi 18:6a4db94011d3 292 #endif
sahilmgandhi 18:6a4db94011d3 293
sahilmgandhi 18:6a4db94011d3 294 /* Configure the I2S extended if the full duplex mode is enabled */
sahilmgandhi 18:6a4db94011d3 295 assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
sahilmgandhi 18:6a4db94011d3 296 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 297 {
sahilmgandhi 18:6a4db94011d3 298 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
sahilmgandhi 18:6a4db94011d3 299 I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
sahilmgandhi 18:6a4db94011d3 300 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
sahilmgandhi 18:6a4db94011d3 301 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
sahilmgandhi 18:6a4db94011d3 302 I2SxEXT(hi2s->Instance)->I2SPR = 2U;
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 /* Get the I2SCFGR register value */
sahilmgandhi 18:6a4db94011d3 305 tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Get the mode to be configured for the extended I2S */
sahilmgandhi 18:6a4db94011d3 308 if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
sahilmgandhi 18:6a4db94011d3 309 {
sahilmgandhi 18:6a4db94011d3 310 tmp = I2S_MODE_SLAVE_RX;
sahilmgandhi 18:6a4db94011d3 311 }
sahilmgandhi 18:6a4db94011d3 312 else
sahilmgandhi 18:6a4db94011d3 313 {
sahilmgandhi 18:6a4db94011d3 314 if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
sahilmgandhi 18:6a4db94011d3 315 {
sahilmgandhi 18:6a4db94011d3 316 tmp = I2S_MODE_SLAVE_TX;
sahilmgandhi 18:6a4db94011d3 317 }
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 /* Configure the I2S Slave with the I2S Master parameter values */
sahilmgandhi 18:6a4db94011d3 321 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 /* Write to SPIx I2SCFGR */
sahilmgandhi 18:6a4db94011d3 324 I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 328 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 331 }
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 /**
sahilmgandhi 18:6a4db94011d3 334 * @brief Full-Duplex Transmit/Receive data in blocking mode.
sahilmgandhi 18:6a4db94011d3 335 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 336 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 337 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
sahilmgandhi 18:6a4db94011d3 338 * @param pRxData: a 16-bit pointer to the Receive data buffer.
sahilmgandhi 18:6a4db94011d3 339 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 340 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 341 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 342 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 343 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 344 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 345 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 346 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 347 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 348 */
sahilmgandhi 18:6a4db94011d3 349 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 350 {
sahilmgandhi 18:6a4db94011d3 351 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 352 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 355 {
sahilmgandhi 18:6a4db94011d3 356 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 357 }
sahilmgandhi 18:6a4db94011d3 358
sahilmgandhi 18:6a4db94011d3 359 /* Check the I2S State */
sahilmgandhi 18:6a4db94011d3 360 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 361 {
sahilmgandhi 18:6a4db94011d3 362 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 363 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
sahilmgandhi 18:6a4db94011d3 364 is selected during the I2S configuration phase, the Size parameter means the number
sahilmgandhi 18:6a4db94011d3 365 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
sahilmgandhi 18:6a4db94011d3 366 frame is selected the Size parameter means the number of 16-bit data length. */
sahilmgandhi 18:6a4db94011d3 367 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 368 {
sahilmgandhi 18:6a4db94011d3 369 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 370 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 371 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 372 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 373 }
sahilmgandhi 18:6a4db94011d3 374 else
sahilmgandhi 18:6a4db94011d3 375 {
sahilmgandhi 18:6a4db94011d3 376 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 377 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 378 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 379 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 380 }
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 383 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /* Set the I2S State busy TX/RX */
sahilmgandhi 18:6a4db94011d3 386 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
sahilmgandhi 18:6a4db94011d3 389 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
sahilmgandhi 18:6a4db94011d3 390 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
sahilmgandhi 18:6a4db94011d3 391 {
sahilmgandhi 18:6a4db94011d3 392 /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
sahilmgandhi 18:6a4db94011d3 393 to avoid the clock de-synchronization between Master and Slave. */
sahilmgandhi 18:6a4db94011d3 394 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 395 {
sahilmgandhi 18:6a4db94011d3 396 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
sahilmgandhi 18:6a4db94011d3 397 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
sahilmgandhi 18:6a4db94011d3 398
sahilmgandhi 18:6a4db94011d3 399 /* Enable I2Sx peripheral */
sahilmgandhi 18:6a4db94011d3 400 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 401 }
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 while(hi2s->TxXferCount > 0U)
sahilmgandhi 18:6a4db94011d3 404 {
sahilmgandhi 18:6a4db94011d3 405 /* Wait until TXE flag is set */
sahilmgandhi 18:6a4db94011d3 406 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 407 {
sahilmgandhi 18:6a4db94011d3 408 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 409 }
sahilmgandhi 18:6a4db94011d3 410 hi2s->Instance->DR = (*pTxData++);
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 /* Get tick */
sahilmgandhi 18:6a4db94011d3 413 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 416 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
sahilmgandhi 18:6a4db94011d3 417 {
sahilmgandhi 18:6a4db94011d3 418 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 419 {
sahilmgandhi 18:6a4db94011d3 420 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 421 {
sahilmgandhi 18:6a4db94011d3 422 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 423 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 426 }
sahilmgandhi 18:6a4db94011d3 427 }
sahilmgandhi 18:6a4db94011d3 428 }
sahilmgandhi 18:6a4db94011d3 429 (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 432 hi2s->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 433 }
sahilmgandhi 18:6a4db94011d3 434 }
sahilmgandhi 18:6a4db94011d3 435 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
sahilmgandhi 18:6a4db94011d3 436 else
sahilmgandhi 18:6a4db94011d3 437 {
sahilmgandhi 18:6a4db94011d3 438 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 439 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 440 {
sahilmgandhi 18:6a4db94011d3 441 /* Enable I2S peripheral before the I2Sext*/
sahilmgandhi 18:6a4db94011d3 442 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
sahilmgandhi 18:6a4db94011d3 445 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
sahilmgandhi 18:6a4db94011d3 446 }
sahilmgandhi 18:6a4db94011d3 447 else
sahilmgandhi 18:6a4db94011d3 448 {
sahilmgandhi 18:6a4db94011d3 449 /* Check if Master Receiver mode is selected */
sahilmgandhi 18:6a4db94011d3 450 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 451 {
sahilmgandhi 18:6a4db94011d3 452 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
sahilmgandhi 18:6a4db94011d3 453 access to the SPI_SR register. */
sahilmgandhi 18:6a4db94011d3 454 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 455 }
sahilmgandhi 18:6a4db94011d3 456 }
sahilmgandhi 18:6a4db94011d3 457 while(hi2s->TxXferCount > 0U)
sahilmgandhi 18:6a4db94011d3 458 {
sahilmgandhi 18:6a4db94011d3 459 /* Get tick */
sahilmgandhi 18:6a4db94011d3 460 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 /* Wait until TXE flag is set */
sahilmgandhi 18:6a4db94011d3 463 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
sahilmgandhi 18:6a4db94011d3 464 {
sahilmgandhi 18:6a4db94011d3 465 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 466 {
sahilmgandhi 18:6a4db94011d3 467 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 468 {
sahilmgandhi 18:6a4db94011d3 469 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 470 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474 }
sahilmgandhi 18:6a4db94011d3 475 }
sahilmgandhi 18:6a4db94011d3 476 I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
sahilmgandhi 18:6a4db94011d3 477
sahilmgandhi 18:6a4db94011d3 478 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 479 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 480 {
sahilmgandhi 18:6a4db94011d3 481 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 482 }
sahilmgandhi 18:6a4db94011d3 483 (*pRxData++) = hi2s->Instance->DR;
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 486 hi2s->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 487 }
sahilmgandhi 18:6a4db94011d3 488 }
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 /* Set the I2S State ready */
sahilmgandhi 18:6a4db94011d3 491 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 494 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 495
sahilmgandhi 18:6a4db94011d3 496 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 497 }
sahilmgandhi 18:6a4db94011d3 498 else
sahilmgandhi 18:6a4db94011d3 499 {
sahilmgandhi 18:6a4db94011d3 500 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 501 }
sahilmgandhi 18:6a4db94011d3 502 }
sahilmgandhi 18:6a4db94011d3 503
sahilmgandhi 18:6a4db94011d3 504 /**
sahilmgandhi 18:6a4db94011d3 505 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
sahilmgandhi 18:6a4db94011d3 506 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 507 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 508 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
sahilmgandhi 18:6a4db94011d3 509 * @param pRxData: a 16-bit pointer to the Receive data buffer.
sahilmgandhi 18:6a4db94011d3 510 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 511 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 512 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 513 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 514 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 515 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 516 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 517 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 518 */
sahilmgandhi 18:6a4db94011d3 519 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 520 {
sahilmgandhi 18:6a4db94011d3 521 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 524 {
sahilmgandhi 18:6a4db94011d3 525 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 526 {
sahilmgandhi 18:6a4db94011d3 527 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 528 }
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 hi2s->pTxBuffPtr = pTxData;
sahilmgandhi 18:6a4db94011d3 531 hi2s->pRxBuffPtr = pRxData;
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 534 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
sahilmgandhi 18:6a4db94011d3 535 is selected during the I2S configuration phase, the Size parameter means the number
sahilmgandhi 18:6a4db94011d3 536 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
sahilmgandhi 18:6a4db94011d3 537 frame is selected the Size parameter means the number of 16-bit data length. */
sahilmgandhi 18:6a4db94011d3 538 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 539 {
sahilmgandhi 18:6a4db94011d3 540 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 541 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 542 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 543 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 544 }
sahilmgandhi 18:6a4db94011d3 545 else
sahilmgandhi 18:6a4db94011d3 546 {
sahilmgandhi 18:6a4db94011d3 547 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 548 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 549 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 550 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 551 }
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 554 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
sahilmgandhi 18:6a4db94011d3 557 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
sahilmgandhi 18:6a4db94011d3 560 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
sahilmgandhi 18:6a4db94011d3 561 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
sahilmgandhi 18:6a4db94011d3 562 {
sahilmgandhi 18:6a4db94011d3 563 /* Enable I2Sext RXNE and ERR interrupts */
sahilmgandhi 18:6a4db94011d3 564 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /* Enable I2Sx TXE and ERR interrupts */
sahilmgandhi 18:6a4db94011d3 567 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 570 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 571 {
sahilmgandhi 18:6a4db94011d3 572 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
sahilmgandhi 18:6a4db94011d3 573 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 /* Enable I2Sx peripheral */
sahilmgandhi 18:6a4db94011d3 576 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 577 }
sahilmgandhi 18:6a4db94011d3 578 }
sahilmgandhi 18:6a4db94011d3 579 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
sahilmgandhi 18:6a4db94011d3 580 else
sahilmgandhi 18:6a4db94011d3 581 {
sahilmgandhi 18:6a4db94011d3 582 /* Enable I2Sext TXE and ERR interrupts */
sahilmgandhi 18:6a4db94011d3 583 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 584
sahilmgandhi 18:6a4db94011d3 585 /* Enable I2Sext RXNE and ERR interrupts */
sahilmgandhi 18:6a4db94011d3 586 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
sahilmgandhi 18:6a4db94011d3 587
sahilmgandhi 18:6a4db94011d3 588 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 589 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 590 {
sahilmgandhi 18:6a4db94011d3 591 /* Check if the I2S_MODE_MASTER_RX is selected */
sahilmgandhi 18:6a4db94011d3 592 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 593 {
sahilmgandhi 18:6a4db94011d3 594 /* Prepare the First Data before enabling the I2S */
sahilmgandhi 18:6a4db94011d3 595 if(hi2s->TxXferCount != 0U)
sahilmgandhi 18:6a4db94011d3 596 {
sahilmgandhi 18:6a4db94011d3 597 /* Transmit First data */
sahilmgandhi 18:6a4db94011d3 598 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 599 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 600
sahilmgandhi 18:6a4db94011d3 601 if(hi2s->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 602 {
sahilmgandhi 18:6a4db94011d3 603 /* Disable I2Sext TXE interrupt */
sahilmgandhi 18:6a4db94011d3 604 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
sahilmgandhi 18:6a4db94011d3 605 }
sahilmgandhi 18:6a4db94011d3 606 }
sahilmgandhi 18:6a4db94011d3 607 }
sahilmgandhi 18:6a4db94011d3 608 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 609 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
sahilmgandhi 18:6a4db94011d3 612 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
sahilmgandhi 18:6a4db94011d3 613 }
sahilmgandhi 18:6a4db94011d3 614 }
sahilmgandhi 18:6a4db94011d3 615 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 616 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 619 }
sahilmgandhi 18:6a4db94011d3 620 else
sahilmgandhi 18:6a4db94011d3 621 {
sahilmgandhi 18:6a4db94011d3 622 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 623 }
sahilmgandhi 18:6a4db94011d3 624 }
sahilmgandhi 18:6a4db94011d3 625
sahilmgandhi 18:6a4db94011d3 626 /**
sahilmgandhi 18:6a4db94011d3 627 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
sahilmgandhi 18:6a4db94011d3 628 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 629 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 630 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
sahilmgandhi 18:6a4db94011d3 631 * @param pRxData: a 16-bit pointer to the Receive data buffer.
sahilmgandhi 18:6a4db94011d3 632 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 633 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 634 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 635 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 636 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 637 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 638 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 639 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 640 */
sahilmgandhi 18:6a4db94011d3 641 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 642 {
sahilmgandhi 18:6a4db94011d3 643 uint32_t *tmp;
sahilmgandhi 18:6a4db94011d3 644 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 647 {
sahilmgandhi 18:6a4db94011d3 648 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 649 }
sahilmgandhi 18:6a4db94011d3 650
sahilmgandhi 18:6a4db94011d3 651 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 652 {
sahilmgandhi 18:6a4db94011d3 653 hi2s->pTxBuffPtr = pTxData;
sahilmgandhi 18:6a4db94011d3 654 hi2s->pRxBuffPtr = pRxData;
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 657 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
sahilmgandhi 18:6a4db94011d3 658 is selected during the I2S configuration phase, the Size parameter means the number
sahilmgandhi 18:6a4db94011d3 659 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
sahilmgandhi 18:6a4db94011d3 660 frame is selected the Size parameter means the number of 16-bit data length. */
sahilmgandhi 18:6a4db94011d3 661 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 662 {
sahilmgandhi 18:6a4db94011d3 663 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 664 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 665 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 666 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 667 }
sahilmgandhi 18:6a4db94011d3 668 else
sahilmgandhi 18:6a4db94011d3 669 {
sahilmgandhi 18:6a4db94011d3 670 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 671 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 672 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 673 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 674 }
sahilmgandhi 18:6a4db94011d3 675
sahilmgandhi 18:6a4db94011d3 676 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 677 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 678
sahilmgandhi 18:6a4db94011d3 679 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
sahilmgandhi 18:6a4db94011d3 680 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 /* Set the I2S Rx DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 683 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
sahilmgandhi 18:6a4db94011d3 684
sahilmgandhi 18:6a4db94011d3 685 /* Set the I2S Rx DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 686 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 /* Set the I2S Rx DMA error callback */
sahilmgandhi 18:6a4db94011d3 689 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 /* Set the I2S Tx DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 692 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694 /* Set the I2S Tx DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 695 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
sahilmgandhi 18:6a4db94011d3 696
sahilmgandhi 18:6a4db94011d3 697 /* Set the I2S Tx DMA error callback */
sahilmgandhi 18:6a4db94011d3 698 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
sahilmgandhi 18:6a4db94011d3 699
sahilmgandhi 18:6a4db94011d3 700 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
sahilmgandhi 18:6a4db94011d3 701 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
sahilmgandhi 18:6a4db94011d3 702 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
sahilmgandhi 18:6a4db94011d3 703 {
sahilmgandhi 18:6a4db94011d3 704 /* Enable the Rx DMA Stream */
sahilmgandhi 18:6a4db94011d3 705 tmp = (uint32_t*)&pRxData;
sahilmgandhi 18:6a4db94011d3 706 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708 /* Enable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 709 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 710
sahilmgandhi 18:6a4db94011d3 711 /* Enable the Tx DMA Stream */
sahilmgandhi 18:6a4db94011d3 712 tmp = (uint32_t*)&pTxData;
sahilmgandhi 18:6a4db94011d3 713 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
sahilmgandhi 18:6a4db94011d3 714
sahilmgandhi 18:6a4db94011d3 715 /* Enable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 716 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 717
sahilmgandhi 18:6a4db94011d3 718 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 719 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 720 {
sahilmgandhi 18:6a4db94011d3 721 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
sahilmgandhi 18:6a4db94011d3 722 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
sahilmgandhi 18:6a4db94011d3 723
sahilmgandhi 18:6a4db94011d3 724 /* Enable I2S peripheral after the I2Sext */
sahilmgandhi 18:6a4db94011d3 725 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 726 }
sahilmgandhi 18:6a4db94011d3 727 }
sahilmgandhi 18:6a4db94011d3 728 else
sahilmgandhi 18:6a4db94011d3 729 {
sahilmgandhi 18:6a4db94011d3 730 /* Enable the Tx DMA Stream */
sahilmgandhi 18:6a4db94011d3 731 tmp = (uint32_t*)&pTxData;
sahilmgandhi 18:6a4db94011d3 732 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
sahilmgandhi 18:6a4db94011d3 733
sahilmgandhi 18:6a4db94011d3 734 /* Enable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 735 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 736
sahilmgandhi 18:6a4db94011d3 737 /* Enable the Rx DMA Stream */
sahilmgandhi 18:6a4db94011d3 738 tmp = (uint32_t*)&pRxData;
sahilmgandhi 18:6a4db94011d3 739 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 /* Enable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 742 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 743
sahilmgandhi 18:6a4db94011d3 744 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 745 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 746 {
sahilmgandhi 18:6a4db94011d3 747 /* Enable I2S peripheral before the I2Sext */
sahilmgandhi 18:6a4db94011d3 748 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 749
sahilmgandhi 18:6a4db94011d3 750 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
sahilmgandhi 18:6a4db94011d3 751 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
sahilmgandhi 18:6a4db94011d3 752 }
sahilmgandhi 18:6a4db94011d3 753 else
sahilmgandhi 18:6a4db94011d3 754 {
sahilmgandhi 18:6a4db94011d3 755 /* Check if Master Receiver mode is selected */
sahilmgandhi 18:6a4db94011d3 756 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 757 {
sahilmgandhi 18:6a4db94011d3 758 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
sahilmgandhi 18:6a4db94011d3 759 access to the SPI_SR register. */
sahilmgandhi 18:6a4db94011d3 760 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 761 }
sahilmgandhi 18:6a4db94011d3 762 }
sahilmgandhi 18:6a4db94011d3 763 }
sahilmgandhi 18:6a4db94011d3 764
sahilmgandhi 18:6a4db94011d3 765 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 766 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 769 }
sahilmgandhi 18:6a4db94011d3 770 else
sahilmgandhi 18:6a4db94011d3 771 {
sahilmgandhi 18:6a4db94011d3 772 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 773 }
sahilmgandhi 18:6a4db94011d3 774 }
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 /**
sahilmgandhi 18:6a4db94011d3 777 * @brief Pauses the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 778 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 779 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 780 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 781 */
sahilmgandhi 18:6a4db94011d3 782 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 783 {
sahilmgandhi 18:6a4db94011d3 784 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 785 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 786
sahilmgandhi 18:6a4db94011d3 787 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 788 {
sahilmgandhi 18:6a4db94011d3 789 /* Disable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 790 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 791 }
sahilmgandhi 18:6a4db94011d3 792 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 793 {
sahilmgandhi 18:6a4db94011d3 794 /* Disable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 795 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 796 }
sahilmgandhi 18:6a4db94011d3 797 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 798 {
sahilmgandhi 18:6a4db94011d3 799 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
sahilmgandhi 18:6a4db94011d3 800 {
sahilmgandhi 18:6a4db94011d3 801 /* Disable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 802 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 803 /* Disable the I2SEx Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 804 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 805 }
sahilmgandhi 18:6a4db94011d3 806 else
sahilmgandhi 18:6a4db94011d3 807 {
sahilmgandhi 18:6a4db94011d3 808 /* Disable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 809 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 810 /* Disable the I2SEx Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 811 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 812 }
sahilmgandhi 18:6a4db94011d3 813 }
sahilmgandhi 18:6a4db94011d3 814
sahilmgandhi 18:6a4db94011d3 815 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 816 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 817
sahilmgandhi 18:6a4db94011d3 818 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 819 }
sahilmgandhi 18:6a4db94011d3 820
sahilmgandhi 18:6a4db94011d3 821 /**
sahilmgandhi 18:6a4db94011d3 822 * @brief Resumes the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 823 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 824 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 825 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 826 */
sahilmgandhi 18:6a4db94011d3 827 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 828 {
sahilmgandhi 18:6a4db94011d3 829 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 830 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 831
sahilmgandhi 18:6a4db94011d3 832 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 833 {
sahilmgandhi 18:6a4db94011d3 834 /* Enable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 835 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 836 }
sahilmgandhi 18:6a4db94011d3 837 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 838 {
sahilmgandhi 18:6a4db94011d3 839 /* Enable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 840 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 841 }
sahilmgandhi 18:6a4db94011d3 842 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 843 {
sahilmgandhi 18:6a4db94011d3 844 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
sahilmgandhi 18:6a4db94011d3 845 {
sahilmgandhi 18:6a4db94011d3 846 /* Enable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 847 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 848 /* Disable the I2SEx Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 849 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 850 }
sahilmgandhi 18:6a4db94011d3 851 else
sahilmgandhi 18:6a4db94011d3 852 {
sahilmgandhi 18:6a4db94011d3 853 /* Enable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 854 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 855 /* Enable the I2SEx Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 856 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 857 }
sahilmgandhi 18:6a4db94011d3 858 }
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860 /* If the I2S peripheral is still not enabled, enable it */
sahilmgandhi 18:6a4db94011d3 861 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
sahilmgandhi 18:6a4db94011d3 862 {
sahilmgandhi 18:6a4db94011d3 863 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 864 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 865 }
sahilmgandhi 18:6a4db94011d3 866
sahilmgandhi 18:6a4db94011d3 867 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 868 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 871 }
sahilmgandhi 18:6a4db94011d3 872
sahilmgandhi 18:6a4db94011d3 873 /**
sahilmgandhi 18:6a4db94011d3 874 * @brief Resumes the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 875 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 876 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 877 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 878 */
sahilmgandhi 18:6a4db94011d3 879 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 880 {
sahilmgandhi 18:6a4db94011d3 881 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 882 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 /* Disable the I2S Tx/Rx DMA requests */
sahilmgandhi 18:6a4db94011d3 885 hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 886 hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 887
sahilmgandhi 18:6a4db94011d3 888 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 889 {
sahilmgandhi 18:6a4db94011d3 890 /* Disable the I2S extended Tx/Rx DMA requests */
sahilmgandhi 18:6a4db94011d3 891 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 892 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 893 }
sahilmgandhi 18:6a4db94011d3 894
sahilmgandhi 18:6a4db94011d3 895 /* Abort the I2S DMA Stream tx */
sahilmgandhi 18:6a4db94011d3 896 if(hi2s->hdmatx != NULL)
sahilmgandhi 18:6a4db94011d3 897 {
sahilmgandhi 18:6a4db94011d3 898 HAL_DMA_Abort(hi2s->hdmatx);
sahilmgandhi 18:6a4db94011d3 899 }
sahilmgandhi 18:6a4db94011d3 900 /* Abort the I2S DMA Stream rx */
sahilmgandhi 18:6a4db94011d3 901 if(hi2s->hdmarx != NULL)
sahilmgandhi 18:6a4db94011d3 902 {
sahilmgandhi 18:6a4db94011d3 903 HAL_DMA_Abort(hi2s->hdmarx);
sahilmgandhi 18:6a4db94011d3 904 }
sahilmgandhi 18:6a4db94011d3 905
sahilmgandhi 18:6a4db94011d3 906 /* Disable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 907 __HAL_I2S_DISABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 908
sahilmgandhi 18:6a4db94011d3 909 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 910 {
sahilmgandhi 18:6a4db94011d3 911 /* Disable the I2Sext peripheral */
sahilmgandhi 18:6a4db94011d3 912 I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
sahilmgandhi 18:6a4db94011d3 913 }
sahilmgandhi 18:6a4db94011d3 914 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 917 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 920 }
sahilmgandhi 18:6a4db94011d3 921
sahilmgandhi 18:6a4db94011d3 922 /**
sahilmgandhi 18:6a4db94011d3 923 * @brief This function handles I2S interrupt request.
sahilmgandhi 18:6a4db94011d3 924 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 925 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 926 * @retval None
sahilmgandhi 18:6a4db94011d3 927 */
sahilmgandhi 18:6a4db94011d3 928 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 929 {
sahilmgandhi 18:6a4db94011d3 930 uint32_t tmp1 = 0U, tmp2 = 0U;
sahilmgandhi 18:6a4db94011d3 931 __IO uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 932 if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 933 {
sahilmgandhi 18:6a4db94011d3 934 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 935 {
sahilmgandhi 18:6a4db94011d3 936 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
sahilmgandhi 18:6a4db94011d3 937 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
sahilmgandhi 18:6a4db94011d3 938 /* I2S in mode Receiver ------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 939 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 940 {
sahilmgandhi 18:6a4db94011d3 941 I2S_Receive_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 942 }
sahilmgandhi 18:6a4db94011d3 943
sahilmgandhi 18:6a4db94011d3 944 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 945 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 946 /* I2S Overrun error interrupt occurred ---------------------------------*/
sahilmgandhi 18:6a4db94011d3 947 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 948 {
sahilmgandhi 18:6a4db94011d3 949 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 950 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
sahilmgandhi 18:6a4db94011d3 951 }
sahilmgandhi 18:6a4db94011d3 952 }
sahilmgandhi 18:6a4db94011d3 953
sahilmgandhi 18:6a4db94011d3 954 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 955 {
sahilmgandhi 18:6a4db94011d3 956 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
sahilmgandhi 18:6a4db94011d3 957 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
sahilmgandhi 18:6a4db94011d3 958 /* I2S in mode Tramitter -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 959 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 960 {
sahilmgandhi 18:6a4db94011d3 961 I2S_Transmit_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 962 }
sahilmgandhi 18:6a4db94011d3 963
sahilmgandhi 18:6a4db94011d3 964 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
sahilmgandhi 18:6a4db94011d3 965 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 966 /* I2S Underrun error interrupt occurred --------------------------------*/
sahilmgandhi 18:6a4db94011d3 967 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 968 {
sahilmgandhi 18:6a4db94011d3 969 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 970 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
sahilmgandhi 18:6a4db94011d3 971 }
sahilmgandhi 18:6a4db94011d3 972 }
sahilmgandhi 18:6a4db94011d3 973 }
sahilmgandhi 18:6a4db94011d3 974 else
sahilmgandhi 18:6a4db94011d3 975 {
sahilmgandhi 18:6a4db94011d3 976 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
sahilmgandhi 18:6a4db94011d3 977 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
sahilmgandhi 18:6a4db94011d3 978 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
sahilmgandhi 18:6a4db94011d3 979 {
sahilmgandhi 18:6a4db94011d3 980 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
sahilmgandhi 18:6a4db94011d3 981 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
sahilmgandhi 18:6a4db94011d3 982 /* I2Sext in mode Receiver ---------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 983 if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
sahilmgandhi 18:6a4db94011d3 984 {
sahilmgandhi 18:6a4db94011d3 985 /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
sahilmgandhi 18:6a4db94011d3 986 the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
sahilmgandhi 18:6a4db94011d3 987 I2SEx_TransmitReceive_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 988 }
sahilmgandhi 18:6a4db94011d3 989
sahilmgandhi 18:6a4db94011d3 990 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
sahilmgandhi 18:6a4db94011d3 991 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
sahilmgandhi 18:6a4db94011d3 992 /* I2Sext Overrun error interrupt occurred -----------------------------*/
sahilmgandhi 18:6a4db94011d3 993 if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
sahilmgandhi 18:6a4db94011d3 994 {
sahilmgandhi 18:6a4db94011d3 995 /* Clear I2Sext OVR Flag */
sahilmgandhi 18:6a4db94011d3 996 tmpreg1 = I2SxEXT(hi2s->Instance)->DR;
sahilmgandhi 18:6a4db94011d3 997 tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
sahilmgandhi 18:6a4db94011d3 998 hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
sahilmgandhi 18:6a4db94011d3 999 UNUSED(tmpreg1);
sahilmgandhi 18:6a4db94011d3 1000 }
sahilmgandhi 18:6a4db94011d3 1001
sahilmgandhi 18:6a4db94011d3 1002 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
sahilmgandhi 18:6a4db94011d3 1003 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
sahilmgandhi 18:6a4db94011d3 1004 /* I2S in mode Tramitter -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1005 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1006 {
sahilmgandhi 18:6a4db94011d3 1007 /* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
sahilmgandhi 18:6a4db94011d3 1008 the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
sahilmgandhi 18:6a4db94011d3 1009 I2SEx_TransmitReceive_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 1010 }
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
sahilmgandhi 18:6a4db94011d3 1013 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1014 /* I2S Underrun error interrupt occurred -------------------------------*/
sahilmgandhi 18:6a4db94011d3 1015 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1016 {
sahilmgandhi 18:6a4db94011d3 1017 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 1018 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
sahilmgandhi 18:6a4db94011d3 1019 }
sahilmgandhi 18:6a4db94011d3 1020 }
sahilmgandhi 18:6a4db94011d3 1021 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
sahilmgandhi 18:6a4db94011d3 1022 else
sahilmgandhi 18:6a4db94011d3 1023 {
sahilmgandhi 18:6a4db94011d3 1024 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
sahilmgandhi 18:6a4db94011d3 1025 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
sahilmgandhi 18:6a4db94011d3 1026 /* I2S in mode Receiver ------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1027 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1028 {
sahilmgandhi 18:6a4db94011d3 1029 /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
sahilmgandhi 18:6a4db94011d3 1030 the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
sahilmgandhi 18:6a4db94011d3 1031 I2SEx_TransmitReceive_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 1032 }
sahilmgandhi 18:6a4db94011d3 1033
sahilmgandhi 18:6a4db94011d3 1034 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 1035 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1036 /* I2S Overrun error interrupt occurred --------------------------------*/
sahilmgandhi 18:6a4db94011d3 1037 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1038 {
sahilmgandhi 18:6a4db94011d3 1039 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 1040 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
sahilmgandhi 18:6a4db94011d3 1041 }
sahilmgandhi 18:6a4db94011d3 1042
sahilmgandhi 18:6a4db94011d3 1043 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
sahilmgandhi 18:6a4db94011d3 1044 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
sahilmgandhi 18:6a4db94011d3 1045 /* I2Sext in mode Tramitter --------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1046 if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
sahilmgandhi 18:6a4db94011d3 1047 {
sahilmgandhi 18:6a4db94011d3 1048 /* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
sahilmgandhi 18:6a4db94011d3 1049 the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
sahilmgandhi 18:6a4db94011d3 1050 I2SEx_TransmitReceive_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 1051 }
sahilmgandhi 18:6a4db94011d3 1052
sahilmgandhi 18:6a4db94011d3 1053 tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
sahilmgandhi 18:6a4db94011d3 1054 tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
sahilmgandhi 18:6a4db94011d3 1055 /* I2Sext Underrun error interrupt occurred ----------------------------*/
sahilmgandhi 18:6a4db94011d3 1056 if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
sahilmgandhi 18:6a4db94011d3 1057 {
sahilmgandhi 18:6a4db94011d3 1058 /* Clear I2Sext UDR Flag */
sahilmgandhi 18:6a4db94011d3 1059 tmpreg1 = I2SxEXT(hi2s->Instance)->SR;
sahilmgandhi 18:6a4db94011d3 1060 hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
sahilmgandhi 18:6a4db94011d3 1061 UNUSED(tmpreg1);
sahilmgandhi 18:6a4db94011d3 1062 }
sahilmgandhi 18:6a4db94011d3 1063 }
sahilmgandhi 18:6a4db94011d3 1064 }
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 /* Call the Error call Back in case of Errors */
sahilmgandhi 18:6a4db94011d3 1067 if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 1068 {
sahilmgandhi 18:6a4db94011d3 1069 /* Set the I2S state ready to be able to start again the process */
sahilmgandhi 18:6a4db94011d3 1070 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1071 HAL_I2S_ErrorCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1072 }
sahilmgandhi 18:6a4db94011d3 1073 }
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075 /**
sahilmgandhi 18:6a4db94011d3 1076 * @}
sahilmgandhi 18:6a4db94011d3 1077 */
sahilmgandhi 18:6a4db94011d3 1078
sahilmgandhi 18:6a4db94011d3 1079 /**
sahilmgandhi 18:6a4db94011d3 1080 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
sahilmgandhi 18:6a4db94011d3 1081 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1082 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1083 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1084 */
sahilmgandhi 18:6a4db94011d3 1085 HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1086 {
sahilmgandhi 18:6a4db94011d3 1087 uint32_t tmp1 = 0U, tmp2 = 0U;
sahilmgandhi 18:6a4db94011d3 1088
sahilmgandhi 18:6a4db94011d3 1089 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 1090 {
sahilmgandhi 18:6a4db94011d3 1091 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1092 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
sahilmgandhi 18:6a4db94011d3 1095 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
sahilmgandhi 18:6a4db94011d3 1096 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp1 == I2S_MODE_SLAVE_TX))
sahilmgandhi 18:6a4db94011d3 1097 {
sahilmgandhi 18:6a4db94011d3 1098 if(hi2s->TxXferCount != 0U)
sahilmgandhi 18:6a4db94011d3 1099 {
sahilmgandhi 18:6a4db94011d3 1100 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
sahilmgandhi 18:6a4db94011d3 1101 {
sahilmgandhi 18:6a4db94011d3 1102 /* Transmit data */
sahilmgandhi 18:6a4db94011d3 1103 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 1104 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 1105
sahilmgandhi 18:6a4db94011d3 1106 if(hi2s->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1107 {
sahilmgandhi 18:6a4db94011d3 1108 /* Disable TXE interrupt */
sahilmgandhi 18:6a4db94011d3 1109 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
sahilmgandhi 18:6a4db94011d3 1110 }
sahilmgandhi 18:6a4db94011d3 1111 }
sahilmgandhi 18:6a4db94011d3 1112 }
sahilmgandhi 18:6a4db94011d3 1113
sahilmgandhi 18:6a4db94011d3 1114 if(hi2s->RxXferCount != 0U)
sahilmgandhi 18:6a4db94011d3 1115 {
sahilmgandhi 18:6a4db94011d3 1116 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
sahilmgandhi 18:6a4db94011d3 1117 {
sahilmgandhi 18:6a4db94011d3 1118 /* Receive data */
sahilmgandhi 18:6a4db94011d3 1119 (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
sahilmgandhi 18:6a4db94011d3 1120 hi2s->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 1121
sahilmgandhi 18:6a4db94011d3 1122 if(hi2s->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1123 {
sahilmgandhi 18:6a4db94011d3 1124 /* Disable I2Sext RXNE interrupt */
sahilmgandhi 18:6a4db94011d3 1125 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
sahilmgandhi 18:6a4db94011d3 1126 }
sahilmgandhi 18:6a4db94011d3 1127 }
sahilmgandhi 18:6a4db94011d3 1128 }
sahilmgandhi 18:6a4db94011d3 1129 }
sahilmgandhi 18:6a4db94011d3 1130 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
sahilmgandhi 18:6a4db94011d3 1131 else
sahilmgandhi 18:6a4db94011d3 1132 {
sahilmgandhi 18:6a4db94011d3 1133 if(hi2s->TxXferCount != 0U)
sahilmgandhi 18:6a4db94011d3 1134 {
sahilmgandhi 18:6a4db94011d3 1135 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
sahilmgandhi 18:6a4db94011d3 1136 {
sahilmgandhi 18:6a4db94011d3 1137 /* Transmit data */
sahilmgandhi 18:6a4db94011d3 1138 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 1139 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 1140
sahilmgandhi 18:6a4db94011d3 1141 if(hi2s->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1142 {
sahilmgandhi 18:6a4db94011d3 1143 /* Disable I2Sext TXE interrupt */
sahilmgandhi 18:6a4db94011d3 1144 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
sahilmgandhi 18:6a4db94011d3 1145
sahilmgandhi 18:6a4db94011d3 1146 HAL_I2S_TxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1147 }
sahilmgandhi 18:6a4db94011d3 1148 }
sahilmgandhi 18:6a4db94011d3 1149 }
sahilmgandhi 18:6a4db94011d3 1150 if(hi2s->RxXferCount != 0U)
sahilmgandhi 18:6a4db94011d3 1151 {
sahilmgandhi 18:6a4db94011d3 1152 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
sahilmgandhi 18:6a4db94011d3 1153 {
sahilmgandhi 18:6a4db94011d3 1154 /* Receive data */
sahilmgandhi 18:6a4db94011d3 1155 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
sahilmgandhi 18:6a4db94011d3 1156 hi2s->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 1157
sahilmgandhi 18:6a4db94011d3 1158 if(hi2s->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1159 {
sahilmgandhi 18:6a4db94011d3 1160 /* Disable RXNE interrupt */
sahilmgandhi 18:6a4db94011d3 1161 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
sahilmgandhi 18:6a4db94011d3 1162
sahilmgandhi 18:6a4db94011d3 1163 HAL_I2S_RxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1164 }
sahilmgandhi 18:6a4db94011d3 1165 }
sahilmgandhi 18:6a4db94011d3 1166 }
sahilmgandhi 18:6a4db94011d3 1167 }
sahilmgandhi 18:6a4db94011d3 1168
sahilmgandhi 18:6a4db94011d3 1169 tmp1 = hi2s->RxXferCount;
sahilmgandhi 18:6a4db94011d3 1170 tmp2 = hi2s->TxXferCount;
sahilmgandhi 18:6a4db94011d3 1171 if((tmp1 == 0U) && (tmp2 == 0U))
sahilmgandhi 18:6a4db94011d3 1172 {
sahilmgandhi 18:6a4db94011d3 1173 /* Disable I2Sx ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1174 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1175 /* Disable I2Sext ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1176 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
sahilmgandhi 18:6a4db94011d3 1177
sahilmgandhi 18:6a4db94011d3 1178 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1179 }
sahilmgandhi 18:6a4db94011d3 1180
sahilmgandhi 18:6a4db94011d3 1181 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1182 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1185 }
sahilmgandhi 18:6a4db94011d3 1186 else
sahilmgandhi 18:6a4db94011d3 1187 {
sahilmgandhi 18:6a4db94011d3 1188 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1189 }
sahilmgandhi 18:6a4db94011d3 1190 }
sahilmgandhi 18:6a4db94011d3 1191 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx ||\
sahilmgandhi 18:6a4db94011d3 1192 STM32F411xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
sahilmgandhi 18:6a4db94011d3 1193 STM32F412Rx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 1194 /**
sahilmgandhi 18:6a4db94011d3 1195 * @brief DMA I2S transmit process complete callback
sahilmgandhi 18:6a4db94011d3 1196 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1197 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1198 * @retval None
sahilmgandhi 18:6a4db94011d3 1199 */
sahilmgandhi 18:6a4db94011d3 1200 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1201 {
sahilmgandhi 18:6a4db94011d3 1202 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1203
sahilmgandhi 18:6a4db94011d3 1204 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
sahilmgandhi 18:6a4db94011d3 1205 {
sahilmgandhi 18:6a4db94011d3 1206 if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 1207 {
sahilmgandhi 18:6a4db94011d3 1208 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1209 }
sahilmgandhi 18:6a4db94011d3 1210 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 1211 defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
sahilmgandhi 18:6a4db94011d3 1212 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
sahilmgandhi 18:6a4db94011d3 1213 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
sahilmgandhi 18:6a4db94011d3 1214 defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 1215
sahilmgandhi 18:6a4db94011d3 1216 /* FullDuplexMode feature enabled */
sahilmgandhi 18:6a4db94011d3 1217 else
sahilmgandhi 18:6a4db94011d3 1218 {
sahilmgandhi 18:6a4db94011d3 1219 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
sahilmgandhi 18:6a4db94011d3 1220 {
sahilmgandhi 18:6a4db94011d3 1221 /* Disable Tx DMA Request for the I2S Master*/
sahilmgandhi 18:6a4db94011d3 1222 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1223 }
sahilmgandhi 18:6a4db94011d3 1224 else
sahilmgandhi 18:6a4db94011d3 1225 {
sahilmgandhi 18:6a4db94011d3 1226 /* Disable Tx DMA Request for the I2SEx Slave */
sahilmgandhi 18:6a4db94011d3 1227 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1228 }
sahilmgandhi 18:6a4db94011d3 1229 }
sahilmgandhi 18:6a4db94011d3 1230 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
sahilmgandhi 18:6a4db94011d3 1231 STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 1232 hi2s->TxXferCount = 0U;
sahilmgandhi 18:6a4db94011d3 1233 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 1234 {
sahilmgandhi 18:6a4db94011d3 1235 if(hi2s->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1236 {
sahilmgandhi 18:6a4db94011d3 1237 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1238 }
sahilmgandhi 18:6a4db94011d3 1239 }
sahilmgandhi 18:6a4db94011d3 1240 else
sahilmgandhi 18:6a4db94011d3 1241 {
sahilmgandhi 18:6a4db94011d3 1242 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1243 }
sahilmgandhi 18:6a4db94011d3 1244 }
sahilmgandhi 18:6a4db94011d3 1245 HAL_I2S_TxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1246 }
sahilmgandhi 18:6a4db94011d3 1247
sahilmgandhi 18:6a4db94011d3 1248 /**
sahilmgandhi 18:6a4db94011d3 1249 * @brief DMA I2S receive process complete callback
sahilmgandhi 18:6a4db94011d3 1250 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1251 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1252 * @retval None
sahilmgandhi 18:6a4db94011d3 1253 */
sahilmgandhi 18:6a4db94011d3 1254 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1255 {
sahilmgandhi 18:6a4db94011d3 1256 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1257
sahilmgandhi 18:6a4db94011d3 1258 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
sahilmgandhi 18:6a4db94011d3 1259 {
sahilmgandhi 18:6a4db94011d3 1260 if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
sahilmgandhi 18:6a4db94011d3 1261 {
sahilmgandhi 18:6a4db94011d3 1262 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1263 }
sahilmgandhi 18:6a4db94011d3 1264 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 1265 defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
sahilmgandhi 18:6a4db94011d3 1266 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
sahilmgandhi 18:6a4db94011d3 1267 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
sahilmgandhi 18:6a4db94011d3 1268 defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 1269 /* FullDuplexMode feature enabled */
sahilmgandhi 18:6a4db94011d3 1270 else
sahilmgandhi 18:6a4db94011d3 1271 {
sahilmgandhi 18:6a4db94011d3 1272 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
sahilmgandhi 18:6a4db94011d3 1273 {
sahilmgandhi 18:6a4db94011d3 1274 /* Disable Rx DMA Request for the I2SEx Slave */
sahilmgandhi 18:6a4db94011d3 1275 I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1276 }
sahilmgandhi 18:6a4db94011d3 1277 else
sahilmgandhi 18:6a4db94011d3 1278 {
sahilmgandhi 18:6a4db94011d3 1279 /* Disable Rx DMA Request for the I2S Master*/
sahilmgandhi 18:6a4db94011d3 1280 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1281 }
sahilmgandhi 18:6a4db94011d3 1282 }
sahilmgandhi 18:6a4db94011d3 1283 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F401xx || STM32F411xx ||\
sahilmgandhi 18:6a4db94011d3 1284 STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 1285 hi2s->RxXferCount = 0U;
sahilmgandhi 18:6a4db94011d3 1286 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 1287 {
sahilmgandhi 18:6a4db94011d3 1288 if(hi2s->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1289 {
sahilmgandhi 18:6a4db94011d3 1290 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1291 }
sahilmgandhi 18:6a4db94011d3 1292 }
sahilmgandhi 18:6a4db94011d3 1293 else
sahilmgandhi 18:6a4db94011d3 1294 {
sahilmgandhi 18:6a4db94011d3 1295 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1296 }
sahilmgandhi 18:6a4db94011d3 1297 }
sahilmgandhi 18:6a4db94011d3 1298 HAL_I2S_RxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1299 }
sahilmgandhi 18:6a4db94011d3 1300
sahilmgandhi 18:6a4db94011d3 1301 /**
sahilmgandhi 18:6a4db94011d3 1302 * @brief Get I2S clock Input based on Source clock selection in RCC
sahilmgandhi 18:6a4db94011d3 1303 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1304 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1305 * @retval I2S Clock Input
sahilmgandhi 18:6a4db94011d3 1306 */
sahilmgandhi 18:6a4db94011d3 1307 uint32_t I2S_GetInputClock(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1308 {
sahilmgandhi 18:6a4db94011d3 1309 /* This variable used to store the VCO Input (value in Hz) */
sahilmgandhi 18:6a4db94011d3 1310 uint32_t vcoinput = 0U;
sahilmgandhi 18:6a4db94011d3 1311 /* This variable used to store the VCO Output (value in Hz) */
sahilmgandhi 18:6a4db94011d3 1312 uint32_t vcooutput = 0U;
sahilmgandhi 18:6a4db94011d3 1313 /* This variable used to store the I2S_CK_x (value in Hz) */
sahilmgandhi 18:6a4db94011d3 1314 uint32_t i2ssourceclock = 0U;
sahilmgandhi 18:6a4db94011d3 1315
sahilmgandhi 18:6a4db94011d3 1316 /* Configure 12S Clock based on I2S source clock selection */
sahilmgandhi 18:6a4db94011d3 1317 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
sahilmgandhi 18:6a4db94011d3 1318 defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 1319 switch(hi2s->Init.ClockSource)
sahilmgandhi 18:6a4db94011d3 1320 {
sahilmgandhi 18:6a4db94011d3 1321 case I2S_CLOCK_EXTERNAL :
sahilmgandhi 18:6a4db94011d3 1322 {
sahilmgandhi 18:6a4db94011d3 1323 /* Set the I2S clock to the external clock value */
sahilmgandhi 18:6a4db94011d3 1324 i2ssourceclock = EXTERNAL_CLOCK_VALUE;
sahilmgandhi 18:6a4db94011d3 1325 break;
sahilmgandhi 18:6a4db94011d3 1326 }
sahilmgandhi 18:6a4db94011d3 1327 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
sahilmgandhi 18:6a4db94011d3 1328 case I2S_CLOCK_PLL :
sahilmgandhi 18:6a4db94011d3 1329 {
sahilmgandhi 18:6a4db94011d3 1330 /* Configure the PLLI2S division factor */
sahilmgandhi 18:6a4db94011d3 1331 /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
sahilmgandhi 18:6a4db94011d3 1332 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 1333 {
sahilmgandhi 18:6a4db94011d3 1334 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1335 vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
sahilmgandhi 18:6a4db94011d3 1336 }
sahilmgandhi 18:6a4db94011d3 1337 else
sahilmgandhi 18:6a4db94011d3 1338 {
sahilmgandhi 18:6a4db94011d3 1339 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1340 vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
sahilmgandhi 18:6a4db94011d3 1341 }
sahilmgandhi 18:6a4db94011d3 1342
sahilmgandhi 18:6a4db94011d3 1343 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
sahilmgandhi 18:6a4db94011d3 1344 vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
sahilmgandhi 18:6a4db94011d3 1345 /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
sahilmgandhi 18:6a4db94011d3 1346 i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
sahilmgandhi 18:6a4db94011d3 1347 break;
sahilmgandhi 18:6a4db94011d3 1348 }
sahilmgandhi 18:6a4db94011d3 1349 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 1350 case I2S_CLOCK_PLLR :
sahilmgandhi 18:6a4db94011d3 1351 {
sahilmgandhi 18:6a4db94011d3 1352 /* Configure the PLLI2S division factor */
sahilmgandhi 18:6a4db94011d3 1353 /* PLL_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi 18:6a4db94011d3 1354 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 1355 {
sahilmgandhi 18:6a4db94011d3 1356 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1357 vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
sahilmgandhi 18:6a4db94011d3 1358 }
sahilmgandhi 18:6a4db94011d3 1359 else
sahilmgandhi 18:6a4db94011d3 1360 {
sahilmgandhi 18:6a4db94011d3 1361 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1362 vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
sahilmgandhi 18:6a4db94011d3 1363 }
sahilmgandhi 18:6a4db94011d3 1364
sahilmgandhi 18:6a4db94011d3 1365 /* PLL_VCO Output = PLL_VCO Input * PLLN */
sahilmgandhi 18:6a4db94011d3 1366 vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
sahilmgandhi 18:6a4db94011d3 1367 /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
sahilmgandhi 18:6a4db94011d3 1368 i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
sahilmgandhi 18:6a4db94011d3 1369 break;
sahilmgandhi 18:6a4db94011d3 1370 }
sahilmgandhi 18:6a4db94011d3 1371 case I2S_CLOCK_PLLSRC :
sahilmgandhi 18:6a4db94011d3 1372 {
sahilmgandhi 18:6a4db94011d3 1373 /* Configure the PLLI2S division factor */
sahilmgandhi 18:6a4db94011d3 1374 /* PLL_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi 18:6a4db94011d3 1375 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 1376 {
sahilmgandhi 18:6a4db94011d3 1377 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1378 i2ssourceclock = (uint32_t)(HSE_VALUE);
sahilmgandhi 18:6a4db94011d3 1379 }
sahilmgandhi 18:6a4db94011d3 1380 else
sahilmgandhi 18:6a4db94011d3 1381 {
sahilmgandhi 18:6a4db94011d3 1382 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1383 i2ssourceclock = (uint32_t)(HSI_VALUE);
sahilmgandhi 18:6a4db94011d3 1384 }
sahilmgandhi 18:6a4db94011d3 1385 break;
sahilmgandhi 18:6a4db94011d3 1386 }
sahilmgandhi 18:6a4db94011d3 1387 default :
sahilmgandhi 18:6a4db94011d3 1388 {
sahilmgandhi 18:6a4db94011d3 1389 break;
sahilmgandhi 18:6a4db94011d3 1390 }
sahilmgandhi 18:6a4db94011d3 1391 }
sahilmgandhi 18:6a4db94011d3 1392 #endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
sahilmgandhi 18:6a4db94011d3 1393
sahilmgandhi 18:6a4db94011d3 1394 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
sahilmgandhi 18:6a4db94011d3 1395 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
sahilmgandhi 18:6a4db94011d3 1396 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 1397
sahilmgandhi 18:6a4db94011d3 1398 /* If an external I2S clock has to be used, the specific define should be set
sahilmgandhi 18:6a4db94011d3 1399 in the project configuration or in the stm32f4xx_conf.h file */
sahilmgandhi 18:6a4db94011d3 1400 if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
sahilmgandhi 18:6a4db94011d3 1401 {
sahilmgandhi 18:6a4db94011d3 1402 /* Set the I2S clock to the external clock value */
sahilmgandhi 18:6a4db94011d3 1403 i2ssourceclock = EXTERNAL_CLOCK_VALUE;
sahilmgandhi 18:6a4db94011d3 1404 }
sahilmgandhi 18:6a4db94011d3 1405 else
sahilmgandhi 18:6a4db94011d3 1406 {
sahilmgandhi 18:6a4db94011d3 1407 /* Configure the PLLI2S division factor */
sahilmgandhi 18:6a4db94011d3 1408 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
sahilmgandhi 18:6a4db94011d3 1409 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 1410 {
sahilmgandhi 18:6a4db94011d3 1411 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1412 vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
sahilmgandhi 18:6a4db94011d3 1413 }
sahilmgandhi 18:6a4db94011d3 1414 else
sahilmgandhi 18:6a4db94011d3 1415 {
sahilmgandhi 18:6a4db94011d3 1416 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1417 vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
sahilmgandhi 18:6a4db94011d3 1418 }
sahilmgandhi 18:6a4db94011d3 1419
sahilmgandhi 18:6a4db94011d3 1420 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
sahilmgandhi 18:6a4db94011d3 1421 vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
sahilmgandhi 18:6a4db94011d3 1422 /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
sahilmgandhi 18:6a4db94011d3 1423 i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
sahilmgandhi 18:6a4db94011d3 1424 }
sahilmgandhi 18:6a4db94011d3 1425 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 1426
sahilmgandhi 18:6a4db94011d3 1427 #if defined(STM32F411xE)
sahilmgandhi 18:6a4db94011d3 1428
sahilmgandhi 18:6a4db94011d3 1429 /* If an external I2S clock has to be used, the specific define should be set
sahilmgandhi 18:6a4db94011d3 1430 in the project configuration or in the stm32f4xx_conf.h file */
sahilmgandhi 18:6a4db94011d3 1431 if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
sahilmgandhi 18:6a4db94011d3 1432 {
sahilmgandhi 18:6a4db94011d3 1433 /* Set the I2S clock to the external clock value */
sahilmgandhi 18:6a4db94011d3 1434 i2ssourceclock = EXTERNAL_CLOCK_VALUE;
sahilmgandhi 18:6a4db94011d3 1435 }
sahilmgandhi 18:6a4db94011d3 1436 else
sahilmgandhi 18:6a4db94011d3 1437 {
sahilmgandhi 18:6a4db94011d3 1438 /* Configure the PLLI2S division factor */
sahilmgandhi 18:6a4db94011d3 1439 /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
sahilmgandhi 18:6a4db94011d3 1440 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
sahilmgandhi 18:6a4db94011d3 1441 {
sahilmgandhi 18:6a4db94011d3 1442 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1443 vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
sahilmgandhi 18:6a4db94011d3 1444 }
sahilmgandhi 18:6a4db94011d3 1445 else
sahilmgandhi 18:6a4db94011d3 1446 {
sahilmgandhi 18:6a4db94011d3 1447 /* Get the I2S source clock value */
sahilmgandhi 18:6a4db94011d3 1448 vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
sahilmgandhi 18:6a4db94011d3 1449 }
sahilmgandhi 18:6a4db94011d3 1450
sahilmgandhi 18:6a4db94011d3 1451 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
sahilmgandhi 18:6a4db94011d3 1452 vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
sahilmgandhi 18:6a4db94011d3 1453 /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
sahilmgandhi 18:6a4db94011d3 1454 i2ssourceclock = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
sahilmgandhi 18:6a4db94011d3 1455 }
sahilmgandhi 18:6a4db94011d3 1456 #endif /* STM32F411xE */
sahilmgandhi 18:6a4db94011d3 1457
sahilmgandhi 18:6a4db94011d3 1458 /* the return result is the value of I2S clock */
sahilmgandhi 18:6a4db94011d3 1459 return i2ssourceclock;
sahilmgandhi 18:6a4db94011d3 1460 }
sahilmgandhi 18:6a4db94011d3 1461 /**
sahilmgandhi 18:6a4db94011d3 1462 * @}
sahilmgandhi 18:6a4db94011d3 1463 */
sahilmgandhi 18:6a4db94011d3 1464
sahilmgandhi 18:6a4db94011d3 1465 /**
sahilmgandhi 18:6a4db94011d3 1466 * @}
sahilmgandhi 18:6a4db94011d3 1467 */
sahilmgandhi 18:6a4db94011d3 1468
sahilmgandhi 18:6a4db94011d3 1469 #endif /* HAL_I2S_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1470 /**
sahilmgandhi 18:6a4db94011d3 1471 * @}
sahilmgandhi 18:6a4db94011d3 1472 */
sahilmgandhi 18:6a4db94011d3 1473
sahilmgandhi 18:6a4db94011d3 1474 /**
sahilmgandhi 18:6a4db94011d3 1475 * @}
sahilmgandhi 18:6a4db94011d3 1476 */
sahilmgandhi 18:6a4db94011d3 1477
sahilmgandhi 18:6a4db94011d3 1478 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/