MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_i2s.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief I2S HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
sahilmgandhi 18:6a4db94011d3 10 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 11 * + IO operation functions
sahilmgandhi 18:6a4db94011d3 12 * + Peripheral State and Errors functions
sahilmgandhi 18:6a4db94011d3 13 @verbatim
sahilmgandhi 18:6a4db94011d3 14 ===============================================================================
sahilmgandhi 18:6a4db94011d3 15 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 16 ===============================================================================
sahilmgandhi 18:6a4db94011d3 17 [..]
sahilmgandhi 18:6a4db94011d3 18 The I2S HAL driver can be used as follow:
sahilmgandhi 18:6a4db94011d3 19
sahilmgandhi 18:6a4db94011d3 20 (#) Declare a I2S_HandleTypeDef handle structure.
sahilmgandhi 18:6a4db94011d3 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
sahilmgandhi 18:6a4db94011d3 22 (##) Enable the SPIx interface clock.
sahilmgandhi 18:6a4db94011d3 23 (##) I2S pins configuration:
sahilmgandhi 18:6a4db94011d3 24 (+++) Enable the clock for the I2S GPIOs.
sahilmgandhi 18:6a4db94011d3 25 (+++) Configure these I2S pins as alternate function pull-up.
sahilmgandhi 18:6a4db94011d3 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
sahilmgandhi 18:6a4db94011d3 27 and HAL_I2S_Receive_IT() APIs).
sahilmgandhi 18:6a4db94011d3 28 (+++) Configure the I2Sx interrupt priority.
sahilmgandhi 18:6a4db94011d3 29 (+++) Enable the NVIC I2S IRQ handle.
sahilmgandhi 18:6a4db94011d3 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
sahilmgandhi 18:6a4db94011d3 31 and HAL_I2S_Receive_DMA() APIs:
sahilmgandhi 18:6a4db94011d3 32 (+++) Declare a DMA handle structure for the Tx/Rx stream.
sahilmgandhi 18:6a4db94011d3 33 (+++) Enable the DMAx interface clock.
sahilmgandhi 18:6a4db94011d3 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
sahilmgandhi 18:6a4db94011d3 35 (+++) Configure the DMA Tx/Rx Stream.
sahilmgandhi 18:6a4db94011d3 36 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
sahilmgandhi 18:6a4db94011d3 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
sahilmgandhi 18:6a4db94011d3 38 DMA Tx/Rx Stream.
sahilmgandhi 18:6a4db94011d3 39
sahilmgandhi 18:6a4db94011d3 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
sahilmgandhi 18:6a4db94011d3 41 using HAL_I2S_Init() function.
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 -@- The specific I2S interrupts (Transmission complete interrupt,
sahilmgandhi 18:6a4db94011d3 44 RXNE interrupt and Error Interrupts) will be managed using the macros
sahilmgandhi 18:6a4db94011d3 45 __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
sahilmgandhi 18:6a4db94011d3 46 -@- Make sure that either:
sahilmgandhi 18:6a4db94011d3 47 (+@) I2S PLL is configured or
sahilmgandhi 18:6a4db94011d3 48 (+@) External clock source is configured after setting correctly
sahilmgandhi 18:6a4db94011d3 49 the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 (#) Three operation modes are available within this driver :
sahilmgandhi 18:6a4db94011d3 52
sahilmgandhi 18:6a4db94011d3 53 *** Polling mode IO operation ***
sahilmgandhi 18:6a4db94011d3 54 =================================
sahilmgandhi 18:6a4db94011d3 55 [..]
sahilmgandhi 18:6a4db94011d3 56 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
sahilmgandhi 18:6a4db94011d3 57 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 *** Interrupt mode IO operation ***
sahilmgandhi 18:6a4db94011d3 60 ===================================
sahilmgandhi 18:6a4db94011d3 61 [..]
sahilmgandhi 18:6a4db94011d3 62 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
sahilmgandhi 18:6a4db94011d3 63 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 64 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 65 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 66 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
sahilmgandhi 18:6a4db94011d3 67 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
sahilmgandhi 18:6a4db94011d3 68 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 69 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 70 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 71 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
sahilmgandhi 18:6a4db94011d3 72 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 73 add his own code by customization of function pointer HAL_I2S_ErrorCallback
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 *** DMA mode IO operation ***
sahilmgandhi 18:6a4db94011d3 76 ==============================
sahilmgandhi 18:6a4db94011d3 77 [..]
sahilmgandhi 18:6a4db94011d3 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
sahilmgandhi 18:6a4db94011d3 79 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 80 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 81 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 82 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
sahilmgandhi 18:6a4db94011d3 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
sahilmgandhi 18:6a4db94011d3 84 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 85 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
sahilmgandhi 18:6a4db94011d3 86 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
sahilmgandhi 18:6a4db94011d3 87 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
sahilmgandhi 18:6a4db94011d3 88 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
sahilmgandhi 18:6a4db94011d3 89 add his own code by customization of function pointer HAL_I2S_ErrorCallback
sahilmgandhi 18:6a4db94011d3 90 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
sahilmgandhi 18:6a4db94011d3 91 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
sahilmgandhi 18:6a4db94011d3 92 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
sahilmgandhi 18:6a4db94011d3 93
sahilmgandhi 18:6a4db94011d3 94 *** I2S HAL driver macros list ***
sahilmgandhi 18:6a4db94011d3 95 =============================================
sahilmgandhi 18:6a4db94011d3 96 [..]
sahilmgandhi 18:6a4db94011d3 97 Below the list of most used macros in USART HAL driver.
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
sahilmgandhi 18:6a4db94011d3 100 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
sahilmgandhi 18:6a4db94011d3 101 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
sahilmgandhi 18:6a4db94011d3 102 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
sahilmgandhi 18:6a4db94011d3 103 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 [..]
sahilmgandhi 18:6a4db94011d3 106 (@) You can refer to the I2S HAL driver header file for more useful macros
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 @endverbatim
sahilmgandhi 18:6a4db94011d3 109 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 110 * @attention
sahilmgandhi 18:6a4db94011d3 111 *
sahilmgandhi 18:6a4db94011d3 112 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 113 *
sahilmgandhi 18:6a4db94011d3 114 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 115 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 116 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 117 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 118 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 119 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 120 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 121 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 122 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 123 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 124 *
sahilmgandhi 18:6a4db94011d3 125 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 126 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 127 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 128 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 129 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 130 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 131 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 132 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 133 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 134 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 135 *
sahilmgandhi 18:6a4db94011d3 136 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 137 */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 140 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 143 * @{
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /** @defgroup I2S I2S
sahilmgandhi 18:6a4db94011d3 147 * @brief I2S HAL module driver
sahilmgandhi 18:6a4db94011d3 148 * @{
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 #ifdef HAL_I2S_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 154 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 155 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 156 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 157 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 158 /** @addtogroup I2S_Private_Functions
sahilmgandhi 18:6a4db94011d3 159 * @{
sahilmgandhi 18:6a4db94011d3 160 */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 /**
sahilmgandhi 18:6a4db94011d3 163 * @}
sahilmgandhi 18:6a4db94011d3 164 */
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 167 /** @defgroup I2S_Exported_Functions I2S Exported Functions
sahilmgandhi 18:6a4db94011d3 168 * @{
sahilmgandhi 18:6a4db94011d3 169 */
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 172 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 173 *
sahilmgandhi 18:6a4db94011d3 174 @verbatim
sahilmgandhi 18:6a4db94011d3 175 ===============================================================================
sahilmgandhi 18:6a4db94011d3 176 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 177 ===============================================================================
sahilmgandhi 18:6a4db94011d3 178 [..] This subsection provides a set of functions allowing to initialize and
sahilmgandhi 18:6a4db94011d3 179 de-initialize the I2Sx peripheral in simplex mode:
sahilmgandhi 18:6a4db94011d3 180
sahilmgandhi 18:6a4db94011d3 181 (+) User must Implement HAL_I2S_MspInit() function in which he configures
sahilmgandhi 18:6a4db94011d3 182 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
sahilmgandhi 18:6a4db94011d3 183
sahilmgandhi 18:6a4db94011d3 184 (+) Call the function HAL_I2S_Init() to configure the selected device with
sahilmgandhi 18:6a4db94011d3 185 the selected configuration:
sahilmgandhi 18:6a4db94011d3 186 (++) Mode
sahilmgandhi 18:6a4db94011d3 187 (++) Standard
sahilmgandhi 18:6a4db94011d3 188 (++) Data Format
sahilmgandhi 18:6a4db94011d3 189 (++) MCLK Output
sahilmgandhi 18:6a4db94011d3 190 (++) Audio frequency
sahilmgandhi 18:6a4db94011d3 191 (++) Polarity
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
sahilmgandhi 18:6a4db94011d3 194 of the selected I2Sx peripheral.
sahilmgandhi 18:6a4db94011d3 195 @endverbatim
sahilmgandhi 18:6a4db94011d3 196 * @{
sahilmgandhi 18:6a4db94011d3 197 */
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 /**
sahilmgandhi 18:6a4db94011d3 200 * @brief Initializes the I2S according to the specified parameters
sahilmgandhi 18:6a4db94011d3 201 * in the I2S_InitTypeDef and create the associated handle.
sahilmgandhi 18:6a4db94011d3 202 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 203 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 204 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 205 */
sahilmgandhi 18:6a4db94011d3 206 __weak HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 207 {
sahilmgandhi 18:6a4db94011d3 208 uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
sahilmgandhi 18:6a4db94011d3 209 uint32_t tmp = 0U, i2sclk = 0U;
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 /* Check the I2S handle allocation */
sahilmgandhi 18:6a4db94011d3 212 if(hi2s == NULL)
sahilmgandhi 18:6a4db94011d3 213 {
sahilmgandhi 18:6a4db94011d3 214 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 215 }
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 /* Check the I2S parameters */
sahilmgandhi 18:6a4db94011d3 218 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
sahilmgandhi 18:6a4db94011d3 219 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
sahilmgandhi 18:6a4db94011d3 220 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
sahilmgandhi 18:6a4db94011d3 221 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
sahilmgandhi 18:6a4db94011d3 222 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
sahilmgandhi 18:6a4db94011d3 223 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
sahilmgandhi 18:6a4db94011d3 224 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
sahilmgandhi 18:6a4db94011d3 225 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 if(hi2s->State == HAL_I2S_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 230 hi2s->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 231 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
sahilmgandhi 18:6a4db94011d3 232 HAL_I2S_MspInit(hi2s);
sahilmgandhi 18:6a4db94011d3 233 }
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 hi2s->State = HAL_I2S_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 236
sahilmgandhi 18:6a4db94011d3 237 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
sahilmgandhi 18:6a4db94011d3 238 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
sahilmgandhi 18:6a4db94011d3 239 hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
sahilmgandhi 18:6a4db94011d3 240 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
sahilmgandhi 18:6a4db94011d3 241 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
sahilmgandhi 18:6a4db94011d3 242 hi2s->Instance->I2SPR = 0x0002U;
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /* Get the I2SCFGR register value */
sahilmgandhi 18:6a4db94011d3 245 tmpreg = hi2s->Instance->I2SCFGR;
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
sahilmgandhi 18:6a4db94011d3 248 /* If the requested audio frequency is not the default, compute the prescaler */
sahilmgandhi 18:6a4db94011d3 249 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
sahilmgandhi 18:6a4db94011d3 250 {
sahilmgandhi 18:6a4db94011d3 251 /* Check the frame length (For the Prescaler computing) *******************/
sahilmgandhi 18:6a4db94011d3 252 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
sahilmgandhi 18:6a4db94011d3 253 {
sahilmgandhi 18:6a4db94011d3 254 /* Packet length is 32 bits */
sahilmgandhi 18:6a4db94011d3 255 packetlength = 2U;
sahilmgandhi 18:6a4db94011d3 256 }
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /* Get I2S source Clock frequency ****************************************/
sahilmgandhi 18:6a4db94011d3 259 /* If an external I2S clock has to be used, the specific define should be set
sahilmgandhi 18:6a4db94011d3 260 in the project configuration or in the stm32f4xx_conf.h file */
sahilmgandhi 18:6a4db94011d3 261 i2sclk = I2S_GetInputClock(hi2s);
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 /* Compute the Real divider depending on the MCLK output state, with a floating point */
sahilmgandhi 18:6a4db94011d3 264 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
sahilmgandhi 18:6a4db94011d3 265 {
sahilmgandhi 18:6a4db94011d3 266 /* MCLK output is enabled */
sahilmgandhi 18:6a4db94011d3 267 tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
sahilmgandhi 18:6a4db94011d3 268 }
sahilmgandhi 18:6a4db94011d3 269 else
sahilmgandhi 18:6a4db94011d3 270 {
sahilmgandhi 18:6a4db94011d3 271 /* MCLK output is disabled */
sahilmgandhi 18:6a4db94011d3 272 tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U) / hi2s->Init.AudioFreq)) + 5U);
sahilmgandhi 18:6a4db94011d3 273 }
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /* Remove the flatting point */
sahilmgandhi 18:6a4db94011d3 276 tmp = tmp / 10U;
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 /* Check the parity of the divider */
sahilmgandhi 18:6a4db94011d3 279 i2sodd = (uint32_t)(tmp & (uint32_t)1U);
sahilmgandhi 18:6a4db94011d3 280
sahilmgandhi 18:6a4db94011d3 281 /* Compute the i2sdiv prescaler */
sahilmgandhi 18:6a4db94011d3 282 i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
sahilmgandhi 18:6a4db94011d3 285 i2sodd = (uint32_t) (i2sodd << 8U);
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 /* Test if the divider is 1 or 0 or greater than 0xFF */
sahilmgandhi 18:6a4db94011d3 289 if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
sahilmgandhi 18:6a4db94011d3 290 {
sahilmgandhi 18:6a4db94011d3 291 /* Set the default values */
sahilmgandhi 18:6a4db94011d3 292 i2sdiv = 2U;
sahilmgandhi 18:6a4db94011d3 293 i2sodd = 0U;
sahilmgandhi 18:6a4db94011d3 294 }
sahilmgandhi 18:6a4db94011d3 295
sahilmgandhi 18:6a4db94011d3 296 /* Write to SPIx I2SPR register the computed value */
sahilmgandhi 18:6a4db94011d3 297 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 /* Configure the I2S with the I2S_InitStruct values */
sahilmgandhi 18:6a4db94011d3 300 tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 #if defined(SPI_I2SCFGR_ASTRTEN)
sahilmgandhi 18:6a4db94011d3 303 if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT)
sahilmgandhi 18:6a4db94011d3 304 {
sahilmgandhi 18:6a4db94011d3 305 /* Write to SPIx I2SCFGR */
sahilmgandhi 18:6a4db94011d3 306 hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
sahilmgandhi 18:6a4db94011d3 307 }
sahilmgandhi 18:6a4db94011d3 308 else
sahilmgandhi 18:6a4db94011d3 309 {
sahilmgandhi 18:6a4db94011d3 310 /* Write to SPIx I2SCFGR */
sahilmgandhi 18:6a4db94011d3 311 hi2s->Instance->I2SCFGR = tmpreg;
sahilmgandhi 18:6a4db94011d3 312 }
sahilmgandhi 18:6a4db94011d3 313 #else
sahilmgandhi 18:6a4db94011d3 314 /* Write to SPIx I2SCFGR */
sahilmgandhi 18:6a4db94011d3 315 hi2s->Instance->I2SCFGR = tmpreg;
sahilmgandhi 18:6a4db94011d3 316 #endif
sahilmgandhi 18:6a4db94011d3 317
sahilmgandhi 18:6a4db94011d3 318 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 319 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 322 }
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /**
sahilmgandhi 18:6a4db94011d3 325 * @brief DeInitializes the I2S peripheral
sahilmgandhi 18:6a4db94011d3 326 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 327 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 328 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 329 */
sahilmgandhi 18:6a4db94011d3 330 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 331 {
sahilmgandhi 18:6a4db94011d3 332 /* Check the I2S handle allocation */
sahilmgandhi 18:6a4db94011d3 333 if(hi2s == NULL)
sahilmgandhi 18:6a4db94011d3 334 {
sahilmgandhi 18:6a4db94011d3 335 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 336 }
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 hi2s->State = HAL_I2S_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
sahilmgandhi 18:6a4db94011d3 341 HAL_I2S_MspDeInit(hi2s);
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 344 hi2s->State = HAL_I2S_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 347 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 348
sahilmgandhi 18:6a4db94011d3 349 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 350 }
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 /**
sahilmgandhi 18:6a4db94011d3 353 * @brief I2S MSP Init
sahilmgandhi 18:6a4db94011d3 354 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 355 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 356 * @retval None
sahilmgandhi 18:6a4db94011d3 357 */
sahilmgandhi 18:6a4db94011d3 358 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 359 {
sahilmgandhi 18:6a4db94011d3 360 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 361 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 362 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 363 the HAL_I2S_MspInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 364 */
sahilmgandhi 18:6a4db94011d3 365 }
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /**
sahilmgandhi 18:6a4db94011d3 368 * @brief I2S MSP DeInit
sahilmgandhi 18:6a4db94011d3 369 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 370 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 371 * @retval None
sahilmgandhi 18:6a4db94011d3 372 */
sahilmgandhi 18:6a4db94011d3 373 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 374 {
sahilmgandhi 18:6a4db94011d3 375 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 376 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 377 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 378 the HAL_I2S_MspDeInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 379 */
sahilmgandhi 18:6a4db94011d3 380 }
sahilmgandhi 18:6a4db94011d3 381 /**
sahilmgandhi 18:6a4db94011d3 382 * @}
sahilmgandhi 18:6a4db94011d3 383 */
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
sahilmgandhi 18:6a4db94011d3 386 * @brief Data transfers functions
sahilmgandhi 18:6a4db94011d3 387 *
sahilmgandhi 18:6a4db94011d3 388 @verbatim
sahilmgandhi 18:6a4db94011d3 389 ===============================================================================
sahilmgandhi 18:6a4db94011d3 390 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 391 ===============================================================================
sahilmgandhi 18:6a4db94011d3 392 [..]
sahilmgandhi 18:6a4db94011d3 393 This subsection provides a set of functions allowing to manage the I2S data
sahilmgandhi 18:6a4db94011d3 394 transfers.
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 (#) There are two modes of transfer:
sahilmgandhi 18:6a4db94011d3 397 (++) Blocking mode : The communication is performed in the polling mode.
sahilmgandhi 18:6a4db94011d3 398 The status of all data processing is returned by the same function
sahilmgandhi 18:6a4db94011d3 399 after finishing transfer.
sahilmgandhi 18:6a4db94011d3 400 (++) No-Blocking mode : The communication is performed using Interrupts
sahilmgandhi 18:6a4db94011d3 401 or DMA. These functions return the status of the transfer startup.
sahilmgandhi 18:6a4db94011d3 402 The end of the data processing will be indicated through the
sahilmgandhi 18:6a4db94011d3 403 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
sahilmgandhi 18:6a4db94011d3 404 using DMA mode.
sahilmgandhi 18:6a4db94011d3 405
sahilmgandhi 18:6a4db94011d3 406 (#) Blocking mode functions are :
sahilmgandhi 18:6a4db94011d3 407 (++) HAL_I2S_Transmit()
sahilmgandhi 18:6a4db94011d3 408 (++) HAL_I2S_Receive()
sahilmgandhi 18:6a4db94011d3 409
sahilmgandhi 18:6a4db94011d3 410 (#) No-Blocking mode functions with Interrupt are :
sahilmgandhi 18:6a4db94011d3 411 (++) HAL_I2S_Transmit_IT()
sahilmgandhi 18:6a4db94011d3 412 (++) HAL_I2S_Receive_IT()
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 (#) No-Blocking mode functions with DMA are :
sahilmgandhi 18:6a4db94011d3 415 (++) HAL_I2S_Transmit_DMA()
sahilmgandhi 18:6a4db94011d3 416 (++) HAL_I2S_Receive_DMA()
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
sahilmgandhi 18:6a4db94011d3 419 (++) HAL_I2S_TxCpltCallback()
sahilmgandhi 18:6a4db94011d3 420 (++) HAL_I2S_RxCpltCallback()
sahilmgandhi 18:6a4db94011d3 421 (++) HAL_I2S_ErrorCallback()
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 @endverbatim
sahilmgandhi 18:6a4db94011d3 424 * @{
sahilmgandhi 18:6a4db94011d3 425 */
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 /**
sahilmgandhi 18:6a4db94011d3 428 * @brief Transmit an amount of data in blocking mode
sahilmgandhi 18:6a4db94011d3 429 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 430 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 431 * @param pData: a 16-bit pointer to data buffer.
sahilmgandhi 18:6a4db94011d3 432 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 433 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 434 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 435 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 436 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 437 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 438 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 439 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 440 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 441 */
sahilmgandhi 18:6a4db94011d3 442 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 443 {
sahilmgandhi 18:6a4db94011d3 444 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 445 if((pData == NULL ) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 446 {
sahilmgandhi 18:6a4db94011d3 447 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 448 }
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 451 {
sahilmgandhi 18:6a4db94011d3 452 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 453 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 454 {
sahilmgandhi 18:6a4db94011d3 455 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 456 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 457 }
sahilmgandhi 18:6a4db94011d3 458 else
sahilmgandhi 18:6a4db94011d3 459 {
sahilmgandhi 18:6a4db94011d3 460 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 461 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 465 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 hi2s->State = HAL_I2S_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 470 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 471 {
sahilmgandhi 18:6a4db94011d3 472 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 473 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 474 }
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 while(hi2s->TxXferCount > 0U)
sahilmgandhi 18:6a4db94011d3 477 {
sahilmgandhi 18:6a4db94011d3 478 hi2s->Instance->DR = (*pData++);
sahilmgandhi 18:6a4db94011d3 479 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 480 /* Wait until TXE flag is set */
sahilmgandhi 18:6a4db94011d3 481 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 482 {
sahilmgandhi 18:6a4db94011d3 483 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 484 }
sahilmgandhi 18:6a4db94011d3 485 }
sahilmgandhi 18:6a4db94011d3 486 /* Check if Slave mode is selected */
sahilmgandhi 18:6a4db94011d3 487 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
sahilmgandhi 18:6a4db94011d3 488 {
sahilmgandhi 18:6a4db94011d3 489 /* Wait until Busy flag is reset */
sahilmgandhi 18:6a4db94011d3 490 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 491 {
sahilmgandhi 18:6a4db94011d3 492 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 493 }
sahilmgandhi 18:6a4db94011d3 494 }
sahilmgandhi 18:6a4db94011d3 495 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 498 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 501 }
sahilmgandhi 18:6a4db94011d3 502 else
sahilmgandhi 18:6a4db94011d3 503 {
sahilmgandhi 18:6a4db94011d3 504 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 505 }
sahilmgandhi 18:6a4db94011d3 506 }
sahilmgandhi 18:6a4db94011d3 507
sahilmgandhi 18:6a4db94011d3 508 /**
sahilmgandhi 18:6a4db94011d3 509 * @brief Receive an amount of data in blocking mode
sahilmgandhi 18:6a4db94011d3 510 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 511 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 512 * @param pData: a 16-bit pointer to data buffer.
sahilmgandhi 18:6a4db94011d3 513 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 514 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 515 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 516 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 517 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 518 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 519 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 520 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 521 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
sahilmgandhi 18:6a4db94011d3 522 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
sahilmgandhi 18:6a4db94011d3 523 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 524 */
sahilmgandhi 18:6a4db94011d3 525 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 526 {
sahilmgandhi 18:6a4db94011d3 527 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 528 if((pData == NULL ) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 529 {
sahilmgandhi 18:6a4db94011d3 530 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 531 }
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 534 {
sahilmgandhi 18:6a4db94011d3 535 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 536 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 537 {
sahilmgandhi 18:6a4db94011d3 538 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 539 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 540 }
sahilmgandhi 18:6a4db94011d3 541 else
sahilmgandhi 18:6a4db94011d3 542 {
sahilmgandhi 18:6a4db94011d3 543 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 544 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 545 }
sahilmgandhi 18:6a4db94011d3 546 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 547 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 hi2s->State = HAL_I2S_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 552 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 553 {
sahilmgandhi 18:6a4db94011d3 554 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 555 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 556 }
sahilmgandhi 18:6a4db94011d3 557
sahilmgandhi 18:6a4db94011d3 558 /* Check if Master Receiver mode is selected */
sahilmgandhi 18:6a4db94011d3 559 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 560 {
sahilmgandhi 18:6a4db94011d3 561 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
sahilmgandhi 18:6a4db94011d3 562 access to the SPI_SR register. */
sahilmgandhi 18:6a4db94011d3 563 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 564 }
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /* Receive data */
sahilmgandhi 18:6a4db94011d3 567 while(hi2s->RxXferCount > 0U)
sahilmgandhi 18:6a4db94011d3 568 {
sahilmgandhi 18:6a4db94011d3 569 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 570 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 571 {
sahilmgandhi 18:6a4db94011d3 572 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 573 }
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 (*pData++) = hi2s->Instance->DR;
sahilmgandhi 18:6a4db94011d3 576 hi2s->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 577 }
sahilmgandhi 18:6a4db94011d3 578
sahilmgandhi 18:6a4db94011d3 579 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 582 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 583
sahilmgandhi 18:6a4db94011d3 584 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 585 }
sahilmgandhi 18:6a4db94011d3 586 else
sahilmgandhi 18:6a4db94011d3 587 {
sahilmgandhi 18:6a4db94011d3 588 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590 }
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592 /**
sahilmgandhi 18:6a4db94011d3 593 * @brief Transmit an amount of data in non-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 594 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 595 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 596 * @param pData: a 16-bit pointer to data buffer.
sahilmgandhi 18:6a4db94011d3 597 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 598 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 599 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 600 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 601 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 602 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 603 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 604 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 605 */
sahilmgandhi 18:6a4db94011d3 606 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 607 {
sahilmgandhi 18:6a4db94011d3 608 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 609 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 610 {
sahilmgandhi 18:6a4db94011d3 611 if((pData == NULL) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 612 {
sahilmgandhi 18:6a4db94011d3 613 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 614 }
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 hi2s->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 617 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 618 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 619 {
sahilmgandhi 18:6a4db94011d3 620 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 621 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 622 }
sahilmgandhi 18:6a4db94011d3 623 else
sahilmgandhi 18:6a4db94011d3 624 {
sahilmgandhi 18:6a4db94011d3 625 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 626 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 627 }
sahilmgandhi 18:6a4db94011d3 628
sahilmgandhi 18:6a4db94011d3 629 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 630 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 631
sahilmgandhi 18:6a4db94011d3 632 hi2s->State = HAL_I2S_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 633 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 /* Enable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 636 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 639 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 640 {
sahilmgandhi 18:6a4db94011d3 641 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 642 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 643 }
sahilmgandhi 18:6a4db94011d3 644
sahilmgandhi 18:6a4db94011d3 645 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 646 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 647
sahilmgandhi 18:6a4db94011d3 648 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 649 }
sahilmgandhi 18:6a4db94011d3 650 else
sahilmgandhi 18:6a4db94011d3 651 {
sahilmgandhi 18:6a4db94011d3 652 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 653 }
sahilmgandhi 18:6a4db94011d3 654 }
sahilmgandhi 18:6a4db94011d3 655
sahilmgandhi 18:6a4db94011d3 656 /**
sahilmgandhi 18:6a4db94011d3 657 * @brief Receive an amount of data in non-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 658 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 659 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 660 * @param pData: a 16-bit pointer to the Receive data buffer.
sahilmgandhi 18:6a4db94011d3 661 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 662 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 663 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 664 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 665 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 666 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 667 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 668 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
sahilmgandhi 18:6a4db94011d3 669 * between Master and Slave otherwise the I2S interrupt should be optimized.
sahilmgandhi 18:6a4db94011d3 670 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 671 */
sahilmgandhi 18:6a4db94011d3 672 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 673 {
sahilmgandhi 18:6a4db94011d3 674 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 675 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 676 {
sahilmgandhi 18:6a4db94011d3 677 if((pData == NULL) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 678 {
sahilmgandhi 18:6a4db94011d3 679 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 680 }
sahilmgandhi 18:6a4db94011d3 681
sahilmgandhi 18:6a4db94011d3 682 hi2s->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 683 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 684 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 685 {
sahilmgandhi 18:6a4db94011d3 686 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 687 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 688 }
sahilmgandhi 18:6a4db94011d3 689 else
sahilmgandhi 18:6a4db94011d3 690 {
sahilmgandhi 18:6a4db94011d3 691 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 692 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 693 }
sahilmgandhi 18:6a4db94011d3 694 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 695 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 696
sahilmgandhi 18:6a4db94011d3 697 hi2s->State = HAL_I2S_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 698 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 699
sahilmgandhi 18:6a4db94011d3 700 /* Enable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 701 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 704 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 705 {
sahilmgandhi 18:6a4db94011d3 706 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 707 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 708 }
sahilmgandhi 18:6a4db94011d3 709
sahilmgandhi 18:6a4db94011d3 710 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 711 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 712
sahilmgandhi 18:6a4db94011d3 713 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 714 }
sahilmgandhi 18:6a4db94011d3 715
sahilmgandhi 18:6a4db94011d3 716 else
sahilmgandhi 18:6a4db94011d3 717 {
sahilmgandhi 18:6a4db94011d3 718 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 719 }
sahilmgandhi 18:6a4db94011d3 720 }
sahilmgandhi 18:6a4db94011d3 721
sahilmgandhi 18:6a4db94011d3 722 /**
sahilmgandhi 18:6a4db94011d3 723 * @brief Transmit an amount of data in non-blocking mode with DMA
sahilmgandhi 18:6a4db94011d3 724 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 725 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 726 * @param pData: a 16-bit pointer to the Transmit data buffer.
sahilmgandhi 18:6a4db94011d3 727 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 728 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 729 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 730 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 731 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 732 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 733 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 734 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 735 */
sahilmgandhi 18:6a4db94011d3 736 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 737 {
sahilmgandhi 18:6a4db94011d3 738 uint32_t *tmp;
sahilmgandhi 18:6a4db94011d3 739 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 if((pData == NULL) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 742 {
sahilmgandhi 18:6a4db94011d3 743 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 744 }
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 747 {
sahilmgandhi 18:6a4db94011d3 748 hi2s->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 749 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 750 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 751 {
sahilmgandhi 18:6a4db94011d3 752 hi2s->TxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 753 hi2s->TxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 754 }
sahilmgandhi 18:6a4db94011d3 755 else
sahilmgandhi 18:6a4db94011d3 756 {
sahilmgandhi 18:6a4db94011d3 757 hi2s->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 758 hi2s->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 759 }
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 762 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 763
sahilmgandhi 18:6a4db94011d3 764 hi2s->State = HAL_I2S_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 765 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 766
sahilmgandhi 18:6a4db94011d3 767 /* Set the I2S Tx DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 768 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
sahilmgandhi 18:6a4db94011d3 769
sahilmgandhi 18:6a4db94011d3 770 /* Set the I2S Tx DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 771 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 774 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 /* Enable the Tx DMA Stream */
sahilmgandhi 18:6a4db94011d3 777 tmp = (uint32_t*)&pData;
sahilmgandhi 18:6a4db94011d3 778 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
sahilmgandhi 18:6a4db94011d3 779
sahilmgandhi 18:6a4db94011d3 780 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 781 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 782 {
sahilmgandhi 18:6a4db94011d3 783 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 784 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 785 }
sahilmgandhi 18:6a4db94011d3 786
sahilmgandhi 18:6a4db94011d3 787 /* Check if the I2S Tx request is already enabled */
sahilmgandhi 18:6a4db94011d3 788 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
sahilmgandhi 18:6a4db94011d3 789 {
sahilmgandhi 18:6a4db94011d3 790 /* Enable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 791 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 792 }
sahilmgandhi 18:6a4db94011d3 793
sahilmgandhi 18:6a4db94011d3 794 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 795 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 796
sahilmgandhi 18:6a4db94011d3 797 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 798 }
sahilmgandhi 18:6a4db94011d3 799 else
sahilmgandhi 18:6a4db94011d3 800 {
sahilmgandhi 18:6a4db94011d3 801 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 802 }
sahilmgandhi 18:6a4db94011d3 803 }
sahilmgandhi 18:6a4db94011d3 804
sahilmgandhi 18:6a4db94011d3 805 /**
sahilmgandhi 18:6a4db94011d3 806 * @brief Receive an amount of data in non-blocking mode with DMA
sahilmgandhi 18:6a4db94011d3 807 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 808 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 809 * @param pData: a 16-bit pointer to the Receive data buffer.
sahilmgandhi 18:6a4db94011d3 810 * @param Size: number of data sample to be sent:
sahilmgandhi 18:6a4db94011d3 811 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
sahilmgandhi 18:6a4db94011d3 812 * configuration phase, the Size parameter means the number of 16-bit data length
sahilmgandhi 18:6a4db94011d3 813 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
sahilmgandhi 18:6a4db94011d3 814 * the Size parameter means the number of 16-bit data length.
sahilmgandhi 18:6a4db94011d3 815 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
sahilmgandhi 18:6a4db94011d3 816 * between Master and Slave(example: audio streaming).
sahilmgandhi 18:6a4db94011d3 817 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 818 */
sahilmgandhi 18:6a4db94011d3 819 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 820 {
sahilmgandhi 18:6a4db94011d3 821 uint32_t *tmp;
sahilmgandhi 18:6a4db94011d3 822 uint32_t tmp1 = 0U;
sahilmgandhi 18:6a4db94011d3 823
sahilmgandhi 18:6a4db94011d3 824 if((pData == NULL) || (Size == 0U))
sahilmgandhi 18:6a4db94011d3 825 {
sahilmgandhi 18:6a4db94011d3 826 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 827 }
sahilmgandhi 18:6a4db94011d3 828
sahilmgandhi 18:6a4db94011d3 829 if(hi2s->State == HAL_I2S_STATE_READY)
sahilmgandhi 18:6a4db94011d3 830 {
sahilmgandhi 18:6a4db94011d3 831 hi2s->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 832 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
sahilmgandhi 18:6a4db94011d3 833 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 834 {
sahilmgandhi 18:6a4db94011d3 835 hi2s->RxXferSize = Size*2U;
sahilmgandhi 18:6a4db94011d3 836 hi2s->RxXferCount = Size*2U;
sahilmgandhi 18:6a4db94011d3 837 }
sahilmgandhi 18:6a4db94011d3 838 else
sahilmgandhi 18:6a4db94011d3 839 {
sahilmgandhi 18:6a4db94011d3 840 hi2s->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 841 hi2s->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 842 }
sahilmgandhi 18:6a4db94011d3 843 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 844 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 hi2s->State = HAL_I2S_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 847 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 848
sahilmgandhi 18:6a4db94011d3 849 /* Set the I2S Rx DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 850 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 /* Set the I2S Rx DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 853 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 856 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /* Check if Master Receiver mode is selected */
sahilmgandhi 18:6a4db94011d3 859 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 860 {
sahilmgandhi 18:6a4db94011d3 861 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
sahilmgandhi 18:6a4db94011d3 862 access to the SPI_SR register. */
sahilmgandhi 18:6a4db94011d3 863 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 864 }
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /* Enable the Rx DMA Stream */
sahilmgandhi 18:6a4db94011d3 867 tmp = (uint32_t*)&pData;
sahilmgandhi 18:6a4db94011d3 868 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 /* Check if the I2S is already enabled */
sahilmgandhi 18:6a4db94011d3 871 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
sahilmgandhi 18:6a4db94011d3 872 {
sahilmgandhi 18:6a4db94011d3 873 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 874 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 875 }
sahilmgandhi 18:6a4db94011d3 876
sahilmgandhi 18:6a4db94011d3 877 /* Check if the I2S Rx request is already enabled */
sahilmgandhi 18:6a4db94011d3 878 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
sahilmgandhi 18:6a4db94011d3 879 {
sahilmgandhi 18:6a4db94011d3 880 /* Enable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 881 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 882 }
sahilmgandhi 18:6a4db94011d3 883
sahilmgandhi 18:6a4db94011d3 884 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 885 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 886
sahilmgandhi 18:6a4db94011d3 887 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 888 }
sahilmgandhi 18:6a4db94011d3 889 else
sahilmgandhi 18:6a4db94011d3 890 {
sahilmgandhi 18:6a4db94011d3 891 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 892 }
sahilmgandhi 18:6a4db94011d3 893 }
sahilmgandhi 18:6a4db94011d3 894
sahilmgandhi 18:6a4db94011d3 895 /**
sahilmgandhi 18:6a4db94011d3 896 * @brief Pauses the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 897 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 898 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 899 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 900 */
sahilmgandhi 18:6a4db94011d3 901 __weak HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 902 {
sahilmgandhi 18:6a4db94011d3 903 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 904 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 905
sahilmgandhi 18:6a4db94011d3 906 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 907 {
sahilmgandhi 18:6a4db94011d3 908 /* Disable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 909 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 910 }
sahilmgandhi 18:6a4db94011d3 911 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 912 {
sahilmgandhi 18:6a4db94011d3 913 /* Disable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 914 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 915 }
sahilmgandhi 18:6a4db94011d3 916 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 917 {
sahilmgandhi 18:6a4db94011d3 918 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
sahilmgandhi 18:6a4db94011d3 919 {
sahilmgandhi 18:6a4db94011d3 920 /* Disable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 921 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 922 }
sahilmgandhi 18:6a4db94011d3 923 else
sahilmgandhi 18:6a4db94011d3 924 {
sahilmgandhi 18:6a4db94011d3 925 /* Disable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 926 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 927 }
sahilmgandhi 18:6a4db94011d3 928 }
sahilmgandhi 18:6a4db94011d3 929
sahilmgandhi 18:6a4db94011d3 930 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 931 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 932
sahilmgandhi 18:6a4db94011d3 933 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 934 }
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936 /**
sahilmgandhi 18:6a4db94011d3 937 * @brief Resumes the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 938 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 939 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 940 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 941 */
sahilmgandhi 18:6a4db94011d3 942 __weak HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 943 {
sahilmgandhi 18:6a4db94011d3 944 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 945 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 946
sahilmgandhi 18:6a4db94011d3 947 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 948 {
sahilmgandhi 18:6a4db94011d3 949 /* Enable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 950 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 951 }
sahilmgandhi 18:6a4db94011d3 952 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 953 {
sahilmgandhi 18:6a4db94011d3 954 /* Enable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 955 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 956 }
sahilmgandhi 18:6a4db94011d3 957 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 958 {
sahilmgandhi 18:6a4db94011d3 959 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
sahilmgandhi 18:6a4db94011d3 960 {
sahilmgandhi 18:6a4db94011d3 961 /* Enable the I2S DMA Tx request */
sahilmgandhi 18:6a4db94011d3 962 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 963 }
sahilmgandhi 18:6a4db94011d3 964 else
sahilmgandhi 18:6a4db94011d3 965 {
sahilmgandhi 18:6a4db94011d3 966 /* Enable the I2S DMA Rx request */
sahilmgandhi 18:6a4db94011d3 967 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 968 }
sahilmgandhi 18:6a4db94011d3 969 }
sahilmgandhi 18:6a4db94011d3 970
sahilmgandhi 18:6a4db94011d3 971 /* If the I2S peripheral is still not enabled, enable it */
sahilmgandhi 18:6a4db94011d3 972 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
sahilmgandhi 18:6a4db94011d3 973 {
sahilmgandhi 18:6a4db94011d3 974 /* Enable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 975 __HAL_I2S_ENABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 976 }
sahilmgandhi 18:6a4db94011d3 977
sahilmgandhi 18:6a4db94011d3 978 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 979 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 980
sahilmgandhi 18:6a4db94011d3 981 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 982 }
sahilmgandhi 18:6a4db94011d3 983
sahilmgandhi 18:6a4db94011d3 984 /**
sahilmgandhi 18:6a4db94011d3 985 * @brief Resumes the audio stream playing from the Media.
sahilmgandhi 18:6a4db94011d3 986 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 987 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 988 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 989 */
sahilmgandhi 18:6a4db94011d3 990 __weak HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 991 {
sahilmgandhi 18:6a4db94011d3 992 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 993 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 994
sahilmgandhi 18:6a4db94011d3 995 /* Disable the I2S Tx/Rx DMA requests */
sahilmgandhi 18:6a4db94011d3 996 hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
sahilmgandhi 18:6a4db94011d3 997 hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
sahilmgandhi 18:6a4db94011d3 998
sahilmgandhi 18:6a4db94011d3 999 /* Abort the I2S DMA Stream tx */
sahilmgandhi 18:6a4db94011d3 1000 if(hi2s->hdmatx != NULL)
sahilmgandhi 18:6a4db94011d3 1001 {
sahilmgandhi 18:6a4db94011d3 1002 HAL_DMA_Abort(hi2s->hdmatx);
sahilmgandhi 18:6a4db94011d3 1003 }
sahilmgandhi 18:6a4db94011d3 1004 /* Abort the I2S DMA Stream rx */
sahilmgandhi 18:6a4db94011d3 1005 if(hi2s->hdmarx != NULL)
sahilmgandhi 18:6a4db94011d3 1006 {
sahilmgandhi 18:6a4db94011d3 1007 HAL_DMA_Abort(hi2s->hdmarx);
sahilmgandhi 18:6a4db94011d3 1008 }
sahilmgandhi 18:6a4db94011d3 1009
sahilmgandhi 18:6a4db94011d3 1010 /* Disable I2S peripheral */
sahilmgandhi 18:6a4db94011d3 1011 __HAL_I2S_DISABLE(hi2s);
sahilmgandhi 18:6a4db94011d3 1012
sahilmgandhi 18:6a4db94011d3 1013 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1014
sahilmgandhi 18:6a4db94011d3 1015 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1016 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1017
sahilmgandhi 18:6a4db94011d3 1018 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1019 }
sahilmgandhi 18:6a4db94011d3 1020
sahilmgandhi 18:6a4db94011d3 1021 /**
sahilmgandhi 18:6a4db94011d3 1022 * @brief This function handles I2S interrupt request.
sahilmgandhi 18:6a4db94011d3 1023 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1024 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1025 * @retval None
sahilmgandhi 18:6a4db94011d3 1026 */
sahilmgandhi 18:6a4db94011d3 1027 __weak void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1028 {
sahilmgandhi 18:6a4db94011d3 1029 uint32_t tmp1 = 0U, tmp2 = 0U;
sahilmgandhi 18:6a4db94011d3 1030
sahilmgandhi 18:6a4db94011d3 1031 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 1032 {
sahilmgandhi 18:6a4db94011d3 1033 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
sahilmgandhi 18:6a4db94011d3 1034 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
sahilmgandhi 18:6a4db94011d3 1035 /* I2S in mode Receiver ------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1036 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1037 {
sahilmgandhi 18:6a4db94011d3 1038 I2S_Receive_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 1039 }
sahilmgandhi 18:6a4db94011d3 1040
sahilmgandhi 18:6a4db94011d3 1041 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
sahilmgandhi 18:6a4db94011d3 1042 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1043 /* I2S Overrun error interrupt occurred ---------------------------------*/
sahilmgandhi 18:6a4db94011d3 1044 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1045 {
sahilmgandhi 18:6a4db94011d3 1046 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 1047 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
sahilmgandhi 18:6a4db94011d3 1048 }
sahilmgandhi 18:6a4db94011d3 1049 }
sahilmgandhi 18:6a4db94011d3 1050
sahilmgandhi 18:6a4db94011d3 1051 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 1052 {
sahilmgandhi 18:6a4db94011d3 1053 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
sahilmgandhi 18:6a4db94011d3 1054 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
sahilmgandhi 18:6a4db94011d3 1055 /* I2S in mode Transmitter -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1056 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1057 {
sahilmgandhi 18:6a4db94011d3 1058 I2S_Transmit_IT(hi2s);
sahilmgandhi 18:6a4db94011d3 1059 }
sahilmgandhi 18:6a4db94011d3 1060
sahilmgandhi 18:6a4db94011d3 1061 tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
sahilmgandhi 18:6a4db94011d3 1062 tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1063 /* I2S Underrun error interrupt occurred --------------------------------*/
sahilmgandhi 18:6a4db94011d3 1064 if((tmp1 != RESET) && (tmp2 != RESET))
sahilmgandhi 18:6a4db94011d3 1065 {
sahilmgandhi 18:6a4db94011d3 1066 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 1067 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
sahilmgandhi 18:6a4db94011d3 1068 }
sahilmgandhi 18:6a4db94011d3 1069 }
sahilmgandhi 18:6a4db94011d3 1070
sahilmgandhi 18:6a4db94011d3 1071 /* Call the Error call Back in case of Errors */
sahilmgandhi 18:6a4db94011d3 1072 if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 1073 {
sahilmgandhi 18:6a4db94011d3 1074 /* Set the I2S state ready to be able to start again the process */
sahilmgandhi 18:6a4db94011d3 1075 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1076 HAL_I2S_ErrorCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1077 }
sahilmgandhi 18:6a4db94011d3 1078 }
sahilmgandhi 18:6a4db94011d3 1079
sahilmgandhi 18:6a4db94011d3 1080 /**
sahilmgandhi 18:6a4db94011d3 1081 * @brief Tx Transfer Half completed callbacks
sahilmgandhi 18:6a4db94011d3 1082 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1083 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1084 * @retval None
sahilmgandhi 18:6a4db94011d3 1085 */
sahilmgandhi 18:6a4db94011d3 1086 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1087 {
sahilmgandhi 18:6a4db94011d3 1088 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1089 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1090 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1091 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1092 */
sahilmgandhi 18:6a4db94011d3 1093 }
sahilmgandhi 18:6a4db94011d3 1094
sahilmgandhi 18:6a4db94011d3 1095 /**
sahilmgandhi 18:6a4db94011d3 1096 * @brief Tx Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1097 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1098 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1099 * @retval None
sahilmgandhi 18:6a4db94011d3 1100 */
sahilmgandhi 18:6a4db94011d3 1101 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1102 {
sahilmgandhi 18:6a4db94011d3 1103 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1104 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1105 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1106 the HAL_I2S_TxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1107 */
sahilmgandhi 18:6a4db94011d3 1108 }
sahilmgandhi 18:6a4db94011d3 1109
sahilmgandhi 18:6a4db94011d3 1110 /**
sahilmgandhi 18:6a4db94011d3 1111 * @brief Rx Transfer half completed callbacks
sahilmgandhi 18:6a4db94011d3 1112 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1113 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1114 * @retval None
sahilmgandhi 18:6a4db94011d3 1115 */
sahilmgandhi 18:6a4db94011d3 1116 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1117 {
sahilmgandhi 18:6a4db94011d3 1118 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1119 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1120 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1121 the HAL_I2S_RxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1122 */
sahilmgandhi 18:6a4db94011d3 1123 }
sahilmgandhi 18:6a4db94011d3 1124
sahilmgandhi 18:6a4db94011d3 1125 /**
sahilmgandhi 18:6a4db94011d3 1126 * @brief Rx Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1127 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1128 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1129 * @retval None
sahilmgandhi 18:6a4db94011d3 1130 */
sahilmgandhi 18:6a4db94011d3 1131 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1132 {
sahilmgandhi 18:6a4db94011d3 1133 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1134 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1135 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1136 the HAL_I2S_RxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1137 */
sahilmgandhi 18:6a4db94011d3 1138 }
sahilmgandhi 18:6a4db94011d3 1139
sahilmgandhi 18:6a4db94011d3 1140 /**
sahilmgandhi 18:6a4db94011d3 1141 * @brief I2S error callbacks
sahilmgandhi 18:6a4db94011d3 1142 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1143 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1144 * @retval None
sahilmgandhi 18:6a4db94011d3 1145 */
sahilmgandhi 18:6a4db94011d3 1146 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1147 {
sahilmgandhi 18:6a4db94011d3 1148 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1149 UNUSED(hi2s);
sahilmgandhi 18:6a4db94011d3 1150 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1151 the HAL_I2S_ErrorCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1152 */
sahilmgandhi 18:6a4db94011d3 1153 }
sahilmgandhi 18:6a4db94011d3 1154
sahilmgandhi 18:6a4db94011d3 1155 /**
sahilmgandhi 18:6a4db94011d3 1156 * @}
sahilmgandhi 18:6a4db94011d3 1157 */
sahilmgandhi 18:6a4db94011d3 1158
sahilmgandhi 18:6a4db94011d3 1159 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
sahilmgandhi 18:6a4db94011d3 1160 * @brief Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1161 @verbatim
sahilmgandhi 18:6a4db94011d3 1162 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1163 ##### Peripheral State and Errors functions #####
sahilmgandhi 18:6a4db94011d3 1164 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1165 [..]
sahilmgandhi 18:6a4db94011d3 1166 This subsection permits to get in run-time the status of the peripheral
sahilmgandhi 18:6a4db94011d3 1167 and the data flow.
sahilmgandhi 18:6a4db94011d3 1168
sahilmgandhi 18:6a4db94011d3 1169 @endverbatim
sahilmgandhi 18:6a4db94011d3 1170 * @{
sahilmgandhi 18:6a4db94011d3 1171 */
sahilmgandhi 18:6a4db94011d3 1172
sahilmgandhi 18:6a4db94011d3 1173 /**
sahilmgandhi 18:6a4db94011d3 1174 * @brief Return the I2S state
sahilmgandhi 18:6a4db94011d3 1175 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1176 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1177 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1178 */
sahilmgandhi 18:6a4db94011d3 1179 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1180 {
sahilmgandhi 18:6a4db94011d3 1181 return hi2s->State;
sahilmgandhi 18:6a4db94011d3 1182 }
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 /**
sahilmgandhi 18:6a4db94011d3 1185 * @brief Return the I2S error code
sahilmgandhi 18:6a4db94011d3 1186 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1187 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1188 * @retval I2S Error Code
sahilmgandhi 18:6a4db94011d3 1189 */
sahilmgandhi 18:6a4db94011d3 1190 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1191 {
sahilmgandhi 18:6a4db94011d3 1192 return hi2s->ErrorCode;
sahilmgandhi 18:6a4db94011d3 1193 }
sahilmgandhi 18:6a4db94011d3 1194 /**
sahilmgandhi 18:6a4db94011d3 1195 * @}
sahilmgandhi 18:6a4db94011d3 1196 */
sahilmgandhi 18:6a4db94011d3 1197
sahilmgandhi 18:6a4db94011d3 1198 /**
sahilmgandhi 18:6a4db94011d3 1199 * @brief DMA I2S transmit process half complete callback
sahilmgandhi 18:6a4db94011d3 1200 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1201 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1202 * @retval None
sahilmgandhi 18:6a4db94011d3 1203 */
sahilmgandhi 18:6a4db94011d3 1204 void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1205 {
sahilmgandhi 18:6a4db94011d3 1206 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1207
sahilmgandhi 18:6a4db94011d3 1208 HAL_I2S_TxHalfCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1209 }
sahilmgandhi 18:6a4db94011d3 1210
sahilmgandhi 18:6a4db94011d3 1211 /**
sahilmgandhi 18:6a4db94011d3 1212 * @brief DMA I2S receive process half complete callback
sahilmgandhi 18:6a4db94011d3 1213 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1214 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1215 * @retval None
sahilmgandhi 18:6a4db94011d3 1216 */
sahilmgandhi 18:6a4db94011d3 1217 void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1218 {
sahilmgandhi 18:6a4db94011d3 1219 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1220
sahilmgandhi 18:6a4db94011d3 1221 HAL_I2S_RxHalfCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1222 }
sahilmgandhi 18:6a4db94011d3 1223
sahilmgandhi 18:6a4db94011d3 1224 /**
sahilmgandhi 18:6a4db94011d3 1225 * @brief DMA I2S communication error callback
sahilmgandhi 18:6a4db94011d3 1226 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1227 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 1228 * @retval None
sahilmgandhi 18:6a4db94011d3 1229 */
sahilmgandhi 18:6a4db94011d3 1230 void I2S_DMAError(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 1231 {
sahilmgandhi 18:6a4db94011d3 1232 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 1233
sahilmgandhi 18:6a4db94011d3 1234 hi2s->TxXferCount = 0U;
sahilmgandhi 18:6a4db94011d3 1235 hi2s->RxXferCount = 0U;
sahilmgandhi 18:6a4db94011d3 1236
sahilmgandhi 18:6a4db94011d3 1237 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1238
sahilmgandhi 18:6a4db94011d3 1239 hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
sahilmgandhi 18:6a4db94011d3 1240 HAL_I2S_ErrorCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1241 }
sahilmgandhi 18:6a4db94011d3 1242
sahilmgandhi 18:6a4db94011d3 1243 /**
sahilmgandhi 18:6a4db94011d3 1244 * @brief Transmit an amount of data in non-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 1245 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1246 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1247 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1248 */
sahilmgandhi 18:6a4db94011d3 1249 HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1250 {
sahilmgandhi 18:6a4db94011d3 1251 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 1252 {
sahilmgandhi 18:6a4db94011d3 1253 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1254 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1255
sahilmgandhi 18:6a4db94011d3 1256 /* Transmit data */
sahilmgandhi 18:6a4db94011d3 1257 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 1258
sahilmgandhi 18:6a4db94011d3 1259 hi2s->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 1260
sahilmgandhi 18:6a4db94011d3 1261 if(hi2s->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1262 {
sahilmgandhi 18:6a4db94011d3 1263 /* Disable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1264 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
sahilmgandhi 18:6a4db94011d3 1265
sahilmgandhi 18:6a4db94011d3 1266 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1267
sahilmgandhi 18:6a4db94011d3 1268 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1269 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1270 HAL_I2S_TxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1271 }
sahilmgandhi 18:6a4db94011d3 1272 else
sahilmgandhi 18:6a4db94011d3 1273 {
sahilmgandhi 18:6a4db94011d3 1274 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1275 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1276 }
sahilmgandhi 18:6a4db94011d3 1277
sahilmgandhi 18:6a4db94011d3 1278 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1279 }
sahilmgandhi 18:6a4db94011d3 1280
sahilmgandhi 18:6a4db94011d3 1281 else
sahilmgandhi 18:6a4db94011d3 1282 {
sahilmgandhi 18:6a4db94011d3 1283 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1284 }
sahilmgandhi 18:6a4db94011d3 1285 }
sahilmgandhi 18:6a4db94011d3 1286
sahilmgandhi 18:6a4db94011d3 1287 /**
sahilmgandhi 18:6a4db94011d3 1288 * @brief Receive an amount of data in non-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 1289 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1290 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1291 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1292 */
sahilmgandhi 18:6a4db94011d3 1293 HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
sahilmgandhi 18:6a4db94011d3 1294 {
sahilmgandhi 18:6a4db94011d3 1295 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 1296 {
sahilmgandhi 18:6a4db94011d3 1297 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1298 __HAL_LOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1299
sahilmgandhi 18:6a4db94011d3 1300 /* Receive data */
sahilmgandhi 18:6a4db94011d3 1301 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
sahilmgandhi 18:6a4db94011d3 1302
sahilmgandhi 18:6a4db94011d3 1303 hi2s->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 1304
sahilmgandhi 18:6a4db94011d3 1305 /* Check if Master Receiver mode is selected */
sahilmgandhi 18:6a4db94011d3 1306 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
sahilmgandhi 18:6a4db94011d3 1307 {
sahilmgandhi 18:6a4db94011d3 1308 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
sahilmgandhi 18:6a4db94011d3 1309 access to the SPI_SR register. */
sahilmgandhi 18:6a4db94011d3 1310 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
sahilmgandhi 18:6a4db94011d3 1311 }
sahilmgandhi 18:6a4db94011d3 1312
sahilmgandhi 18:6a4db94011d3 1313 if(hi2s->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1314 {
sahilmgandhi 18:6a4db94011d3 1315 /* Disable RXNE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1316 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1317
sahilmgandhi 18:6a4db94011d3 1318 hi2s->State = HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1319
sahilmgandhi 18:6a4db94011d3 1320 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1321 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1322
sahilmgandhi 18:6a4db94011d3 1323 HAL_I2S_RxCpltCallback(hi2s);
sahilmgandhi 18:6a4db94011d3 1324 }
sahilmgandhi 18:6a4db94011d3 1325 else
sahilmgandhi 18:6a4db94011d3 1326 {
sahilmgandhi 18:6a4db94011d3 1327 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1328 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1329 }
sahilmgandhi 18:6a4db94011d3 1330
sahilmgandhi 18:6a4db94011d3 1331 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1332 }
sahilmgandhi 18:6a4db94011d3 1333 else
sahilmgandhi 18:6a4db94011d3 1334 {
sahilmgandhi 18:6a4db94011d3 1335 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1336 }
sahilmgandhi 18:6a4db94011d3 1337 }
sahilmgandhi 18:6a4db94011d3 1338
sahilmgandhi 18:6a4db94011d3 1339 /**
sahilmgandhi 18:6a4db94011d3 1340 * @brief This function handles I2S Communication Timeout.
sahilmgandhi 18:6a4db94011d3 1341 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1342 * the configuration information for I2S module
sahilmgandhi 18:6a4db94011d3 1343 * @param Flag: Flag checked
sahilmgandhi 18:6a4db94011d3 1344 * @param Status: Value of the flag expected
sahilmgandhi 18:6a4db94011d3 1345 * @param Timeout: Duration of the timeout
sahilmgandhi 18:6a4db94011d3 1346 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1347 */
sahilmgandhi 18:6a4db94011d3 1348 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 1349 {
sahilmgandhi 18:6a4db94011d3 1350 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 1351
sahilmgandhi 18:6a4db94011d3 1352 /* Get tick */
sahilmgandhi 18:6a4db94011d3 1353 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 1354
sahilmgandhi 18:6a4db94011d3 1355 /* Wait until flag is set */
sahilmgandhi 18:6a4db94011d3 1356 if(Status == RESET)
sahilmgandhi 18:6a4db94011d3 1357 {
sahilmgandhi 18:6a4db94011d3 1358 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
sahilmgandhi 18:6a4db94011d3 1359 {
sahilmgandhi 18:6a4db94011d3 1360 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 1361 {
sahilmgandhi 18:6a4db94011d3 1362 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 1363 {
sahilmgandhi 18:6a4db94011d3 1364 /* Set the I2S State ready */
sahilmgandhi 18:6a4db94011d3 1365 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1366
sahilmgandhi 18:6a4db94011d3 1367 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1368 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1369
sahilmgandhi 18:6a4db94011d3 1370 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1371 }
sahilmgandhi 18:6a4db94011d3 1372 }
sahilmgandhi 18:6a4db94011d3 1373 }
sahilmgandhi 18:6a4db94011d3 1374 }
sahilmgandhi 18:6a4db94011d3 1375 else
sahilmgandhi 18:6a4db94011d3 1376 {
sahilmgandhi 18:6a4db94011d3 1377 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
sahilmgandhi 18:6a4db94011d3 1378 {
sahilmgandhi 18:6a4db94011d3 1379 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 1380 {
sahilmgandhi 18:6a4db94011d3 1381 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 1382 {
sahilmgandhi 18:6a4db94011d3 1383 /* Set the I2S State ready */
sahilmgandhi 18:6a4db94011d3 1384 hi2s->State= HAL_I2S_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1385
sahilmgandhi 18:6a4db94011d3 1386 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1387 __HAL_UNLOCK(hi2s);
sahilmgandhi 18:6a4db94011d3 1388
sahilmgandhi 18:6a4db94011d3 1389 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1390 }
sahilmgandhi 18:6a4db94011d3 1391 }
sahilmgandhi 18:6a4db94011d3 1392 }
sahilmgandhi 18:6a4db94011d3 1393 }
sahilmgandhi 18:6a4db94011d3 1394 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1395 }
sahilmgandhi 18:6a4db94011d3 1396
sahilmgandhi 18:6a4db94011d3 1397 /**
sahilmgandhi 18:6a4db94011d3 1398 * @}
sahilmgandhi 18:6a4db94011d3 1399 */
sahilmgandhi 18:6a4db94011d3 1400
sahilmgandhi 18:6a4db94011d3 1401 #endif /* HAL_I2S_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 1402 /**
sahilmgandhi 18:6a4db94011d3 1403 * @}
sahilmgandhi 18:6a4db94011d3 1404 */
sahilmgandhi 18:6a4db94011d3 1405
sahilmgandhi 18:6a4db94011d3 1406 /**
sahilmgandhi 18:6a4db94011d3 1407 * @}
sahilmgandhi 18:6a4db94011d3 1408 */
sahilmgandhi 18:6a4db94011d3 1409
sahilmgandhi 18:6a4db94011d3 1410 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/