MacroRat / MouseCode

Mouse code for the MacroRat

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f4xx_hal_eth.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 06-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief ETH HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 9 * functionalities of the Ethernet (ETH) peripheral:
sahilmgandhi 18:6a4db94011d3 10 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 11 * + IO operation functions
sahilmgandhi 18:6a4db94011d3 12 * + Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 13 * + Peripheral State and Errors functions
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 @verbatim
sahilmgandhi 18:6a4db94011d3 16 ==============================================================================
sahilmgandhi 18:6a4db94011d3 17 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 18 ==============================================================================
sahilmgandhi 18:6a4db94011d3 19 [..]
sahilmgandhi 18:6a4db94011d3 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
sahilmgandhi 18:6a4db94011d3 21 ETH_HandleTypeDef heth;
sahilmgandhi 18:6a4db94011d3 22
sahilmgandhi 18:6a4db94011d3 23 (#)Fill parameters of Init structure in heth handle
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
sahilmgandhi 18:6a4db94011d3 26
sahilmgandhi 18:6a4db94011d3 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
sahilmgandhi 18:6a4db94011d3 28 (##) Enable the Ethernet interface clock using
sahilmgandhi 18:6a4db94011d3 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 (##) Initialize the related GPIO clocks
sahilmgandhi 18:6a4db94011d3 34 (##) Configure Ethernet pin-out
sahilmgandhi 18:6a4db94011d3 35 (##) Configure Ethernet NVIC interrupt (IT mode)
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
sahilmgandhi 18:6a4db94011d3 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
sahilmgandhi 18:6a4db94011d3 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 (#)Enable MAC and DMA transmission and reception:
sahilmgandhi 18:6a4db94011d3 42 (##) HAL_ETH_Start();
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
sahilmgandhi 18:6a4db94011d3 45 the frame to MAC TX FIFO:
sahilmgandhi 18:6a4db94011d3 46 (##) HAL_ETH_TransmitFrame();
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
sahilmgandhi 18:6a4db94011d3 49 frame parameters
sahilmgandhi 18:6a4db94011d3 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 (#) Get a received frame when an ETH RX interrupt occurs:
sahilmgandhi 18:6a4db94011d3 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 (#) Communicate with external PHY device:
sahilmgandhi 18:6a4db94011d3 56 (##) Read a specific register from the PHY
sahilmgandhi 18:6a4db94011d3 57 HAL_ETH_ReadPHYRegister();
sahilmgandhi 18:6a4db94011d3 58 (##) Write data to a specific RHY register:
sahilmgandhi 18:6a4db94011d3 59 HAL_ETH_WritePHYRegister();
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
sahilmgandhi 18:6a4db94011d3 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
sahilmgandhi 18:6a4db94011d3 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
sahilmgandhi 18:6a4db94011d3 66
sahilmgandhi 18:6a4db94011d3 67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
sahilmgandhi 18:6a4db94011d3 68 in this driver
sahilmgandhi 18:6a4db94011d3 69
sahilmgandhi 18:6a4db94011d3 70 @endverbatim
sahilmgandhi 18:6a4db94011d3 71 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 72 * @attention
sahilmgandhi 18:6a4db94011d3 73 *
sahilmgandhi 18:6a4db94011d3 74 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 75 *
sahilmgandhi 18:6a4db94011d3 76 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 77 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 78 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 79 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 81 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 82 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 84 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 85 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 86 *
sahilmgandhi 18:6a4db94011d3 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 97 *
sahilmgandhi 18:6a4db94011d3 98 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 99 */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 102 #include "stm32f4xx_hal.h"
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 105 * @{
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /** @defgroup ETH ETH
sahilmgandhi 18:6a4db94011d3 109 * @brief ETH HAL module driver
sahilmgandhi 18:6a4db94011d3 110 * @{
sahilmgandhi 18:6a4db94011d3 111 */
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 #ifdef HAL_ETH_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
sahilmgandhi 18:6a4db94011d3 116 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 119 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 120 /** @defgroup ETH_Private_Constants ETH Private Constants
sahilmgandhi 18:6a4db94011d3 121 * @{
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123 #define ETH_TIMEOUT_SWRESET ((uint32_t)500U)
sahilmgandhi 18:6a4db94011d3 124 #define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000U)
sahilmgandhi 18:6a4db94011d3 125 #define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000U)
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 /**
sahilmgandhi 18:6a4db94011d3 128 * @}
sahilmgandhi 18:6a4db94011d3 129 */
sahilmgandhi 18:6a4db94011d3 130 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 131 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 132 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 133 /** @defgroup ETH_Private_Functions ETH Private Functions
sahilmgandhi 18:6a4db94011d3 134 * @{
sahilmgandhi 18:6a4db94011d3 135 */
sahilmgandhi 18:6a4db94011d3 136 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
sahilmgandhi 18:6a4db94011d3 137 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
sahilmgandhi 18:6a4db94011d3 138 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 139 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 140 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 141 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 142 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 143 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 144 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 145 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 146 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
sahilmgandhi 18:6a4db94011d3 147 static void ETH_Delay(uint32_t mdelay);
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 /**
sahilmgandhi 18:6a4db94011d3 150 * @}
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152 /* Private functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 /** @defgroup ETH_Exported_Functions ETH Exported Functions
sahilmgandhi 18:6a4db94011d3 155 * @{
sahilmgandhi 18:6a4db94011d3 156 */
sahilmgandhi 18:6a4db94011d3 157
sahilmgandhi 18:6a4db94011d3 158 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 159 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 160 *
sahilmgandhi 18:6a4db94011d3 161 @verbatim
sahilmgandhi 18:6a4db94011d3 162 ===============================================================================
sahilmgandhi 18:6a4db94011d3 163 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 164 ===============================================================================
sahilmgandhi 18:6a4db94011d3 165 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 166 (+) Initialize and configure the Ethernet peripheral
sahilmgandhi 18:6a4db94011d3 167 (+) De-initialize the Ethernet peripheral
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 @endverbatim
sahilmgandhi 18:6a4db94011d3 170 * @{
sahilmgandhi 18:6a4db94011d3 171 */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /**
sahilmgandhi 18:6a4db94011d3 174 * @brief Initializes the Ethernet MAC and DMA according to default
sahilmgandhi 18:6a4db94011d3 175 * parameters.
sahilmgandhi 18:6a4db94011d3 176 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 177 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 178 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 179 */
sahilmgandhi 18:6a4db94011d3 180 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 181 {
sahilmgandhi 18:6a4db94011d3 182 uint32_t tmpreg1 = 0U, phyreg = 0U;
sahilmgandhi 18:6a4db94011d3 183 uint32_t hclk = 60000000U;
sahilmgandhi 18:6a4db94011d3 184 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 185 uint32_t err = ETH_SUCCESS;
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /* Check the ETH peripheral state */
sahilmgandhi 18:6a4db94011d3 188 if(heth == NULL)
sahilmgandhi 18:6a4db94011d3 189 {
sahilmgandhi 18:6a4db94011d3 190 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 191 }
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /* Check parameters */
sahilmgandhi 18:6a4db94011d3 194 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
sahilmgandhi 18:6a4db94011d3 195 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
sahilmgandhi 18:6a4db94011d3 196 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
sahilmgandhi 18:6a4db94011d3 197 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
sahilmgandhi 18:6a4db94011d3 198
sahilmgandhi 18:6a4db94011d3 199 if(heth->State == HAL_ETH_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 200 {
sahilmgandhi 18:6a4db94011d3 201 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 202 heth->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 203 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
sahilmgandhi 18:6a4db94011d3 204 HAL_ETH_MspInit(heth);
sahilmgandhi 18:6a4db94011d3 205 }
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 /* Enable SYSCFG Clock */
sahilmgandhi 18:6a4db94011d3 208 __HAL_RCC_SYSCFG_CLK_ENABLE();
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 /* Select MII or RMII Mode*/
sahilmgandhi 18:6a4db94011d3 211 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
sahilmgandhi 18:6a4db94011d3 212 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /* Ethernet Software reset */
sahilmgandhi 18:6a4db94011d3 215 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
sahilmgandhi 18:6a4db94011d3 216 /* After reset all the registers holds their respective reset values */
sahilmgandhi 18:6a4db94011d3 217 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /* Get tick */
sahilmgandhi 18:6a4db94011d3 220 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 /* Wait for software reset */
sahilmgandhi 18:6a4db94011d3 223 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
sahilmgandhi 18:6a4db94011d3 224 {
sahilmgandhi 18:6a4db94011d3 225 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 226 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
sahilmgandhi 18:6a4db94011d3 227 {
sahilmgandhi 18:6a4db94011d3 228 heth->State= HAL_ETH_STATE_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 229
sahilmgandhi 18:6a4db94011d3 230 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 231 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
sahilmgandhi 18:6a4db94011d3 234 not available, please check your external PHY or the IO configuration */
sahilmgandhi 18:6a4db94011d3 235 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 236 }
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238
sahilmgandhi 18:6a4db94011d3 239 /*-------------------------------- MAC Initialization ----------------------*/
sahilmgandhi 18:6a4db94011d3 240 /* Get the ETHERNET MACMIIAR value */
sahilmgandhi 18:6a4db94011d3 241 tmpreg1 = (heth->Instance)->MACMIIAR;
sahilmgandhi 18:6a4db94011d3 242 /* Clear CSR Clock Range CR[2:0] bits */
sahilmgandhi 18:6a4db94011d3 243 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /* Get hclk frequency value */
sahilmgandhi 18:6a4db94011d3 246 hclk = HAL_RCC_GetHCLKFreq();
sahilmgandhi 18:6a4db94011d3 247
sahilmgandhi 18:6a4db94011d3 248 /* Set CR bits depending on hclk value */
sahilmgandhi 18:6a4db94011d3 249 if((hclk >= 20000000U)&&(hclk < 35000000U))
sahilmgandhi 18:6a4db94011d3 250 {
sahilmgandhi 18:6a4db94011d3 251 /* CSR Clock Range between 20-35 MHz */
sahilmgandhi 18:6a4db94011d3 252 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
sahilmgandhi 18:6a4db94011d3 253 }
sahilmgandhi 18:6a4db94011d3 254 else if((hclk >= 35000000U)&&(hclk < 60000000U))
sahilmgandhi 18:6a4db94011d3 255 {
sahilmgandhi 18:6a4db94011d3 256 /* CSR Clock Range between 35-60 MHz */
sahilmgandhi 18:6a4db94011d3 257 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
sahilmgandhi 18:6a4db94011d3 258 }
sahilmgandhi 18:6a4db94011d3 259 else if((hclk >= 60000000U)&&(hclk < 100000000U))
sahilmgandhi 18:6a4db94011d3 260 {
sahilmgandhi 18:6a4db94011d3 261 /* CSR Clock Range between 60-100 MHz */
sahilmgandhi 18:6a4db94011d3 262 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
sahilmgandhi 18:6a4db94011d3 263 }
sahilmgandhi 18:6a4db94011d3 264 else if((hclk >= 100000000U)&&(hclk < 150000000U))
sahilmgandhi 18:6a4db94011d3 265 {
sahilmgandhi 18:6a4db94011d3 266 /* CSR Clock Range between 100-150 MHz */
sahilmgandhi 18:6a4db94011d3 267 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
sahilmgandhi 18:6a4db94011d3 268 }
sahilmgandhi 18:6a4db94011d3 269 else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */
sahilmgandhi 18:6a4db94011d3 270 {
sahilmgandhi 18:6a4db94011d3 271 /* CSR Clock Range between 150-183 MHz */
sahilmgandhi 18:6a4db94011d3 272 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
sahilmgandhi 18:6a4db94011d3 273 }
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
sahilmgandhi 18:6a4db94011d3 276 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
sahilmgandhi 18:6a4db94011d3 277
sahilmgandhi 18:6a4db94011d3 278 /*-------------------- PHY initialization and configuration ----------------*/
sahilmgandhi 18:6a4db94011d3 279 /* Put the PHY in reset mode */
sahilmgandhi 18:6a4db94011d3 280 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 281 {
sahilmgandhi 18:6a4db94011d3 282 /* In case of write timeout */
sahilmgandhi 18:6a4db94011d3 283 err = ETH_ERROR;
sahilmgandhi 18:6a4db94011d3 284
sahilmgandhi 18:6a4db94011d3 285 /* Config MAC and DMA */
sahilmgandhi 18:6a4db94011d3 286 ETH_MACDMAConfig(heth, err);
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 /* Set the ETH peripheral state to READY */
sahilmgandhi 18:6a4db94011d3 289 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /* Return HAL_ERROR */
sahilmgandhi 18:6a4db94011d3 292 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 293 }
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /* Delay to assure PHY reset */
sahilmgandhi 18:6a4db94011d3 296 HAL_Delay(PHY_RESET_DELAY);
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
sahilmgandhi 18:6a4db94011d3 299 {
sahilmgandhi 18:6a4db94011d3 300 /* Get tick */
sahilmgandhi 18:6a4db94011d3 301 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 /* We wait for linked status */
sahilmgandhi 18:6a4db94011d3 304 do
sahilmgandhi 18:6a4db94011d3 305 {
sahilmgandhi 18:6a4db94011d3 306 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 309 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
sahilmgandhi 18:6a4db94011d3 310 {
sahilmgandhi 18:6a4db94011d3 311 /* In case of write timeout */
sahilmgandhi 18:6a4db94011d3 312 err = ETH_ERROR;
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 /* Config MAC and DMA */
sahilmgandhi 18:6a4db94011d3 315 ETH_MACDMAConfig(heth, err);
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 318
sahilmgandhi 18:6a4db94011d3 319 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 320 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 323 }
sahilmgandhi 18:6a4db94011d3 324 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
sahilmgandhi 18:6a4db94011d3 325
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 /* Enable Auto-Negotiation */
sahilmgandhi 18:6a4db94011d3 328 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 329 {
sahilmgandhi 18:6a4db94011d3 330 /* In case of write timeout */
sahilmgandhi 18:6a4db94011d3 331 err = ETH_ERROR;
sahilmgandhi 18:6a4db94011d3 332
sahilmgandhi 18:6a4db94011d3 333 /* Config MAC and DMA */
sahilmgandhi 18:6a4db94011d3 334 ETH_MACDMAConfig(heth, err);
sahilmgandhi 18:6a4db94011d3 335
sahilmgandhi 18:6a4db94011d3 336 /* Set the ETH peripheral state to READY */
sahilmgandhi 18:6a4db94011d3 337 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 /* Return HAL_ERROR */
sahilmgandhi 18:6a4db94011d3 340 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 341 }
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 /* Get tick */
sahilmgandhi 18:6a4db94011d3 344 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 345
sahilmgandhi 18:6a4db94011d3 346 /* Wait until the auto-negotiation will be completed */
sahilmgandhi 18:6a4db94011d3 347 do
sahilmgandhi 18:6a4db94011d3 348 {
sahilmgandhi 18:6a4db94011d3 349 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 352 if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
sahilmgandhi 18:6a4db94011d3 353 {
sahilmgandhi 18:6a4db94011d3 354 /* In case of write timeout */
sahilmgandhi 18:6a4db94011d3 355 err = ETH_ERROR;
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 /* Config MAC and DMA */
sahilmgandhi 18:6a4db94011d3 358 ETH_MACDMAConfig(heth, err);
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 363 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 366 }
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 /* Read the result of the auto-negotiation */
sahilmgandhi 18:6a4db94011d3 371 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 372 {
sahilmgandhi 18:6a4db94011d3 373 /* In case of write timeout */
sahilmgandhi 18:6a4db94011d3 374 err = ETH_ERROR;
sahilmgandhi 18:6a4db94011d3 375
sahilmgandhi 18:6a4db94011d3 376 /* Config MAC and DMA */
sahilmgandhi 18:6a4db94011d3 377 ETH_MACDMAConfig(heth, err);
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 /* Set the ETH peripheral state to READY */
sahilmgandhi 18:6a4db94011d3 380 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 /* Return HAL_ERROR */
sahilmgandhi 18:6a4db94011d3 383 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 384 }
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
sahilmgandhi 18:6a4db94011d3 387 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
sahilmgandhi 18:6a4db94011d3 388 {
sahilmgandhi 18:6a4db94011d3 389 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
sahilmgandhi 18:6a4db94011d3 390 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
sahilmgandhi 18:6a4db94011d3 391 }
sahilmgandhi 18:6a4db94011d3 392 else
sahilmgandhi 18:6a4db94011d3 393 {
sahilmgandhi 18:6a4db94011d3 394 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
sahilmgandhi 18:6a4db94011d3 395 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
sahilmgandhi 18:6a4db94011d3 396 }
sahilmgandhi 18:6a4db94011d3 397 /* Configure the MAC with the speed fixed by the auto-negotiation process */
sahilmgandhi 18:6a4db94011d3 398 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
sahilmgandhi 18:6a4db94011d3 399 {
sahilmgandhi 18:6a4db94011d3 400 /* Set Ethernet speed to 10M following the auto-negotiation */
sahilmgandhi 18:6a4db94011d3 401 (heth->Init).Speed = ETH_SPEED_10M;
sahilmgandhi 18:6a4db94011d3 402 }
sahilmgandhi 18:6a4db94011d3 403 else
sahilmgandhi 18:6a4db94011d3 404 {
sahilmgandhi 18:6a4db94011d3 405 /* Set Ethernet speed to 100M following the auto-negotiation */
sahilmgandhi 18:6a4db94011d3 406 (heth->Init).Speed = ETH_SPEED_100M;
sahilmgandhi 18:6a4db94011d3 407 }
sahilmgandhi 18:6a4db94011d3 408 }
sahilmgandhi 18:6a4db94011d3 409 else /* AutoNegotiation Disable */
sahilmgandhi 18:6a4db94011d3 410 {
sahilmgandhi 18:6a4db94011d3 411 /* Check parameters */
sahilmgandhi 18:6a4db94011d3 412 assert_param(IS_ETH_SPEED(heth->Init.Speed));
sahilmgandhi 18:6a4db94011d3 413 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 /* Set MAC Speed and Duplex Mode */
sahilmgandhi 18:6a4db94011d3 416 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
sahilmgandhi 18:6a4db94011d3 417 (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 418 {
sahilmgandhi 18:6a4db94011d3 419 /* In case of write timeout */
sahilmgandhi 18:6a4db94011d3 420 err = ETH_ERROR;
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 /* Config MAC and DMA */
sahilmgandhi 18:6a4db94011d3 423 ETH_MACDMAConfig(heth, err);
sahilmgandhi 18:6a4db94011d3 424
sahilmgandhi 18:6a4db94011d3 425 /* Set the ETH peripheral state to READY */
sahilmgandhi 18:6a4db94011d3 426 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 /* Return HAL_ERROR */
sahilmgandhi 18:6a4db94011d3 429 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 /* Delay to assure PHY configuration */
sahilmgandhi 18:6a4db94011d3 433 HAL_Delay(PHY_CONFIG_DELAY);
sahilmgandhi 18:6a4db94011d3 434 }
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 /* Config MAC and DMA */
sahilmgandhi 18:6a4db94011d3 437 ETH_MACDMAConfig(heth, err);
sahilmgandhi 18:6a4db94011d3 438
sahilmgandhi 18:6a4db94011d3 439 /* Set ETH HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 440 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 /* Return function status */
sahilmgandhi 18:6a4db94011d3 443 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 444 }
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 /**
sahilmgandhi 18:6a4db94011d3 447 * @brief De-Initializes the ETH peripheral.
sahilmgandhi 18:6a4db94011d3 448 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 449 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 450 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 451 */
sahilmgandhi 18:6a4db94011d3 452 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 453 {
sahilmgandhi 18:6a4db94011d3 454 /* Set the ETH peripheral state to BUSY */
sahilmgandhi 18:6a4db94011d3 455 heth->State = HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
sahilmgandhi 18:6a4db94011d3 458 HAL_ETH_MspDeInit(heth);
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 /* Set ETH HAL state to Disabled */
sahilmgandhi 18:6a4db94011d3 461 heth->State= HAL_ETH_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 464 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 /* Return function status */
sahilmgandhi 18:6a4db94011d3 467 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 468 }
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 /**
sahilmgandhi 18:6a4db94011d3 471 * @brief Initializes the DMA Tx descriptors in chain mode.
sahilmgandhi 18:6a4db94011d3 472 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 473 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 474 * @param DMATxDescTab: Pointer to the first Tx desc list
sahilmgandhi 18:6a4db94011d3 475 * @param TxBuff: Pointer to the first TxBuffer list
sahilmgandhi 18:6a4db94011d3 476 * @param TxBuffCount: Number of the used Tx desc in the list
sahilmgandhi 18:6a4db94011d3 477 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 478 */
sahilmgandhi 18:6a4db94011d3 479 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
sahilmgandhi 18:6a4db94011d3 480 {
sahilmgandhi 18:6a4db94011d3 481 uint32_t i = 0U;
sahilmgandhi 18:6a4db94011d3 482 ETH_DMADescTypeDef *dmatxdesc;
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 485 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 486
sahilmgandhi 18:6a4db94011d3 487 /* Set the ETH peripheral state to BUSY */
sahilmgandhi 18:6a4db94011d3 488 heth->State = HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 489
sahilmgandhi 18:6a4db94011d3 490 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
sahilmgandhi 18:6a4db94011d3 491 heth->TxDesc = DMATxDescTab;
sahilmgandhi 18:6a4db94011d3 492
sahilmgandhi 18:6a4db94011d3 493 /* Fill each DMATxDesc descriptor with the right values */
sahilmgandhi 18:6a4db94011d3 494 for(i=0U; i < TxBuffCount; i++)
sahilmgandhi 18:6a4db94011d3 495 {
sahilmgandhi 18:6a4db94011d3 496 /* Get the pointer on the ith member of the Tx Desc list */
sahilmgandhi 18:6a4db94011d3 497 dmatxdesc = DMATxDescTab + i;
sahilmgandhi 18:6a4db94011d3 498
sahilmgandhi 18:6a4db94011d3 499 /* Set Second Address Chained bit */
sahilmgandhi 18:6a4db94011d3 500 dmatxdesc->Status = ETH_DMATXDESC_TCH;
sahilmgandhi 18:6a4db94011d3 501
sahilmgandhi 18:6a4db94011d3 502 /* Set Buffer1 address pointer */
sahilmgandhi 18:6a4db94011d3 503 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
sahilmgandhi 18:6a4db94011d3 506 {
sahilmgandhi 18:6a4db94011d3 507 /* Set the DMA Tx descriptors checksum insertion */
sahilmgandhi 18:6a4db94011d3 508 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
sahilmgandhi 18:6a4db94011d3 509 }
sahilmgandhi 18:6a4db94011d3 510
sahilmgandhi 18:6a4db94011d3 511 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
sahilmgandhi 18:6a4db94011d3 512 if(i < (TxBuffCount-1U))
sahilmgandhi 18:6a4db94011d3 513 {
sahilmgandhi 18:6a4db94011d3 514 /* Set next descriptor address register with next descriptor base address */
sahilmgandhi 18:6a4db94011d3 515 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
sahilmgandhi 18:6a4db94011d3 516 }
sahilmgandhi 18:6a4db94011d3 517 else
sahilmgandhi 18:6a4db94011d3 518 {
sahilmgandhi 18:6a4db94011d3 519 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
sahilmgandhi 18:6a4db94011d3 520 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
sahilmgandhi 18:6a4db94011d3 521 }
sahilmgandhi 18:6a4db94011d3 522 }
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /* Set Transmit Descriptor List Address Register */
sahilmgandhi 18:6a4db94011d3 525 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 /* Set ETH HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 528 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 529
sahilmgandhi 18:6a4db94011d3 530 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 531 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 532
sahilmgandhi 18:6a4db94011d3 533 /* Return function status */
sahilmgandhi 18:6a4db94011d3 534 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 535 }
sahilmgandhi 18:6a4db94011d3 536
sahilmgandhi 18:6a4db94011d3 537 /**
sahilmgandhi 18:6a4db94011d3 538 * @brief Initializes the DMA Rx descriptors in chain mode.
sahilmgandhi 18:6a4db94011d3 539 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 540 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 541 * @param DMARxDescTab: Pointer to the first Rx desc list
sahilmgandhi 18:6a4db94011d3 542 * @param RxBuff: Pointer to the first RxBuffer list
sahilmgandhi 18:6a4db94011d3 543 * @param RxBuffCount: Number of the used Rx desc in the list
sahilmgandhi 18:6a4db94011d3 544 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 545 */
sahilmgandhi 18:6a4db94011d3 546 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
sahilmgandhi 18:6a4db94011d3 547 {
sahilmgandhi 18:6a4db94011d3 548 uint32_t i = 0U;
sahilmgandhi 18:6a4db94011d3 549 ETH_DMADescTypeDef *DMARxDesc;
sahilmgandhi 18:6a4db94011d3 550
sahilmgandhi 18:6a4db94011d3 551 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 552 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 553
sahilmgandhi 18:6a4db94011d3 554 /* Set the ETH peripheral state to BUSY */
sahilmgandhi 18:6a4db94011d3 555 heth->State = HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 556
sahilmgandhi 18:6a4db94011d3 557 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
sahilmgandhi 18:6a4db94011d3 558 heth->RxDesc = DMARxDescTab;
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 /* Fill each DMARxDesc descriptor with the right values */
sahilmgandhi 18:6a4db94011d3 561 for(i=0U; i < RxBuffCount; i++)
sahilmgandhi 18:6a4db94011d3 562 {
sahilmgandhi 18:6a4db94011d3 563 /* Get the pointer on the ith member of the Rx Desc list */
sahilmgandhi 18:6a4db94011d3 564 DMARxDesc = DMARxDescTab+i;
sahilmgandhi 18:6a4db94011d3 565
sahilmgandhi 18:6a4db94011d3 566 /* Set Own bit of the Rx descriptor Status */
sahilmgandhi 18:6a4db94011d3 567 DMARxDesc->Status = ETH_DMARXDESC_OWN;
sahilmgandhi 18:6a4db94011d3 568
sahilmgandhi 18:6a4db94011d3 569 /* Set Buffer1 size and Second Address Chained bit */
sahilmgandhi 18:6a4db94011d3 570 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 /* Set Buffer1 address pointer */
sahilmgandhi 18:6a4db94011d3 573 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
sahilmgandhi 18:6a4db94011d3 574
sahilmgandhi 18:6a4db94011d3 575 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
sahilmgandhi 18:6a4db94011d3 576 {
sahilmgandhi 18:6a4db94011d3 577 /* Enable Ethernet DMA Rx Descriptor interrupt */
sahilmgandhi 18:6a4db94011d3 578 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
sahilmgandhi 18:6a4db94011d3 582 if(i < (RxBuffCount-1U))
sahilmgandhi 18:6a4db94011d3 583 {
sahilmgandhi 18:6a4db94011d3 584 /* Set next descriptor address register with next descriptor base address */
sahilmgandhi 18:6a4db94011d3 585 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
sahilmgandhi 18:6a4db94011d3 586 }
sahilmgandhi 18:6a4db94011d3 587 else
sahilmgandhi 18:6a4db94011d3 588 {
sahilmgandhi 18:6a4db94011d3 589 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
sahilmgandhi 18:6a4db94011d3 590 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
sahilmgandhi 18:6a4db94011d3 591 }
sahilmgandhi 18:6a4db94011d3 592 }
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 /* Set Receive Descriptor List Address Register */
sahilmgandhi 18:6a4db94011d3 595 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
sahilmgandhi 18:6a4db94011d3 596
sahilmgandhi 18:6a4db94011d3 597 /* Set ETH HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 598 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 599
sahilmgandhi 18:6a4db94011d3 600 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 601 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 602
sahilmgandhi 18:6a4db94011d3 603 /* Return function status */
sahilmgandhi 18:6a4db94011d3 604 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 605 }
sahilmgandhi 18:6a4db94011d3 606
sahilmgandhi 18:6a4db94011d3 607 /**
sahilmgandhi 18:6a4db94011d3 608 * @brief Initializes the ETH MSP.
sahilmgandhi 18:6a4db94011d3 609 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 610 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 611 * @retval None
sahilmgandhi 18:6a4db94011d3 612 */
sahilmgandhi 18:6a4db94011d3 613 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 614 {
sahilmgandhi 18:6a4db94011d3 615 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 616 UNUSED(heth);
sahilmgandhi 18:6a4db94011d3 617 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 618 the HAL_ETH_MspInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 619 */
sahilmgandhi 18:6a4db94011d3 620 }
sahilmgandhi 18:6a4db94011d3 621
sahilmgandhi 18:6a4db94011d3 622 /**
sahilmgandhi 18:6a4db94011d3 623 * @brief DeInitializes ETH MSP.
sahilmgandhi 18:6a4db94011d3 624 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 625 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 626 * @retval None
sahilmgandhi 18:6a4db94011d3 627 */
sahilmgandhi 18:6a4db94011d3 628 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 629 {
sahilmgandhi 18:6a4db94011d3 630 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 631 UNUSED(heth);
sahilmgandhi 18:6a4db94011d3 632 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 633 the HAL_ETH_MspDeInit could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 634 */
sahilmgandhi 18:6a4db94011d3 635 }
sahilmgandhi 18:6a4db94011d3 636
sahilmgandhi 18:6a4db94011d3 637 /**
sahilmgandhi 18:6a4db94011d3 638 * @}
sahilmgandhi 18:6a4db94011d3 639 */
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
sahilmgandhi 18:6a4db94011d3 642 * @brief Data transfers functions
sahilmgandhi 18:6a4db94011d3 643 *
sahilmgandhi 18:6a4db94011d3 644 @verbatim
sahilmgandhi 18:6a4db94011d3 645 ==============================================================================
sahilmgandhi 18:6a4db94011d3 646 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 647 ==============================================================================
sahilmgandhi 18:6a4db94011d3 648 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 649 (+) Transmit a frame
sahilmgandhi 18:6a4db94011d3 650 HAL_ETH_TransmitFrame();
sahilmgandhi 18:6a4db94011d3 651 (+) Receive a frame
sahilmgandhi 18:6a4db94011d3 652 HAL_ETH_GetReceivedFrame();
sahilmgandhi 18:6a4db94011d3 653 HAL_ETH_GetReceivedFrame_IT();
sahilmgandhi 18:6a4db94011d3 654 (+) Read from an External PHY register
sahilmgandhi 18:6a4db94011d3 655 HAL_ETH_ReadPHYRegister();
sahilmgandhi 18:6a4db94011d3 656 (+) Write to an External PHY register
sahilmgandhi 18:6a4db94011d3 657 HAL_ETH_WritePHYRegister();
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 @endverbatim
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 * @{
sahilmgandhi 18:6a4db94011d3 662 */
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 /**
sahilmgandhi 18:6a4db94011d3 665 * @brief Sends an Ethernet frame.
sahilmgandhi 18:6a4db94011d3 666 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 667 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 668 * @param FrameLength: Amount of data to be sent
sahilmgandhi 18:6a4db94011d3 669 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 670 */
sahilmgandhi 18:6a4db94011d3 671 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
sahilmgandhi 18:6a4db94011d3 672 {
sahilmgandhi 18:6a4db94011d3 673 uint32_t bufcount = 0U, size = 0U, i = 0U;
sahilmgandhi 18:6a4db94011d3 674
sahilmgandhi 18:6a4db94011d3 675 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 676 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 677
sahilmgandhi 18:6a4db94011d3 678 /* Set the ETH peripheral state to BUSY */
sahilmgandhi 18:6a4db94011d3 679 heth->State = HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 680
sahilmgandhi 18:6a4db94011d3 681 if (FrameLength == 0U)
sahilmgandhi 18:6a4db94011d3 682 {
sahilmgandhi 18:6a4db94011d3 683 /* Set ETH HAL state to READY */
sahilmgandhi 18:6a4db94011d3 684 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 685
sahilmgandhi 18:6a4db94011d3 686 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 687 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 688
sahilmgandhi 18:6a4db94011d3 689 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 690 }
sahilmgandhi 18:6a4db94011d3 691
sahilmgandhi 18:6a4db94011d3 692 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
sahilmgandhi 18:6a4db94011d3 693 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
sahilmgandhi 18:6a4db94011d3 694 {
sahilmgandhi 18:6a4db94011d3 695 /* OWN bit set */
sahilmgandhi 18:6a4db94011d3 696 heth->State = HAL_ETH_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 699 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 700
sahilmgandhi 18:6a4db94011d3 701 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 702 }
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 /* Get the number of needed Tx buffers for the current frame */
sahilmgandhi 18:6a4db94011d3 705 if (FrameLength > ETH_TX_BUF_SIZE)
sahilmgandhi 18:6a4db94011d3 706 {
sahilmgandhi 18:6a4db94011d3 707 bufcount = FrameLength/ETH_TX_BUF_SIZE;
sahilmgandhi 18:6a4db94011d3 708 if (FrameLength % ETH_TX_BUF_SIZE)
sahilmgandhi 18:6a4db94011d3 709 {
sahilmgandhi 18:6a4db94011d3 710 bufcount++;
sahilmgandhi 18:6a4db94011d3 711 }
sahilmgandhi 18:6a4db94011d3 712 }
sahilmgandhi 18:6a4db94011d3 713 else
sahilmgandhi 18:6a4db94011d3 714 {
sahilmgandhi 18:6a4db94011d3 715 bufcount = 1U;
sahilmgandhi 18:6a4db94011d3 716 }
sahilmgandhi 18:6a4db94011d3 717 if (bufcount == 1U)
sahilmgandhi 18:6a4db94011d3 718 {
sahilmgandhi 18:6a4db94011d3 719 /* Set LAST and FIRST segment */
sahilmgandhi 18:6a4db94011d3 720 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
sahilmgandhi 18:6a4db94011d3 721 /* Set frame size */
sahilmgandhi 18:6a4db94011d3 722 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
sahilmgandhi 18:6a4db94011d3 723 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
sahilmgandhi 18:6a4db94011d3 724 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
sahilmgandhi 18:6a4db94011d3 725 /* Point to next descriptor */
sahilmgandhi 18:6a4db94011d3 726 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
sahilmgandhi 18:6a4db94011d3 727 }
sahilmgandhi 18:6a4db94011d3 728 else
sahilmgandhi 18:6a4db94011d3 729 {
sahilmgandhi 18:6a4db94011d3 730 for (i=0U; i< bufcount; i++)
sahilmgandhi 18:6a4db94011d3 731 {
sahilmgandhi 18:6a4db94011d3 732 /* Clear FIRST and LAST segment bits */
sahilmgandhi 18:6a4db94011d3 733 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 if (i == 0U)
sahilmgandhi 18:6a4db94011d3 736 {
sahilmgandhi 18:6a4db94011d3 737 /* Setting the first segment bit */
sahilmgandhi 18:6a4db94011d3 738 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
sahilmgandhi 18:6a4db94011d3 739 }
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 /* Program size */
sahilmgandhi 18:6a4db94011d3 742 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
sahilmgandhi 18:6a4db94011d3 743
sahilmgandhi 18:6a4db94011d3 744 if (i == (bufcount-1U))
sahilmgandhi 18:6a4db94011d3 745 {
sahilmgandhi 18:6a4db94011d3 746 /* Setting the last segment bit */
sahilmgandhi 18:6a4db94011d3 747 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
sahilmgandhi 18:6a4db94011d3 748 size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
sahilmgandhi 18:6a4db94011d3 749 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
sahilmgandhi 18:6a4db94011d3 750 }
sahilmgandhi 18:6a4db94011d3 751
sahilmgandhi 18:6a4db94011d3 752 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
sahilmgandhi 18:6a4db94011d3 753 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
sahilmgandhi 18:6a4db94011d3 754 /* point to next descriptor */
sahilmgandhi 18:6a4db94011d3 755 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
sahilmgandhi 18:6a4db94011d3 756 }
sahilmgandhi 18:6a4db94011d3 757 }
sahilmgandhi 18:6a4db94011d3 758
sahilmgandhi 18:6a4db94011d3 759 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
sahilmgandhi 18:6a4db94011d3 760 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
sahilmgandhi 18:6a4db94011d3 761 {
sahilmgandhi 18:6a4db94011d3 762 /* Clear TBUS ETHERNET DMA flag */
sahilmgandhi 18:6a4db94011d3 763 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
sahilmgandhi 18:6a4db94011d3 764 /* Resume DMA transmission*/
sahilmgandhi 18:6a4db94011d3 765 (heth->Instance)->DMATPDR = 0U;
sahilmgandhi 18:6a4db94011d3 766 }
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 /* Set ETH HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 769 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 770
sahilmgandhi 18:6a4db94011d3 771 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 772 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 /* Return function status */
sahilmgandhi 18:6a4db94011d3 775 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 776 }
sahilmgandhi 18:6a4db94011d3 777
sahilmgandhi 18:6a4db94011d3 778 /**
sahilmgandhi 18:6a4db94011d3 779 * @brief Checks for received frames.
sahilmgandhi 18:6a4db94011d3 780 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 781 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 782 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 783 */
sahilmgandhi 18:6a4db94011d3 784 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 785 {
sahilmgandhi 18:6a4db94011d3 786 uint32_t framelength = 0U;
sahilmgandhi 18:6a4db94011d3 787
sahilmgandhi 18:6a4db94011d3 788 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 789 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 790
sahilmgandhi 18:6a4db94011d3 791 /* Check the ETH state to BUSY */
sahilmgandhi 18:6a4db94011d3 792 heth->State = HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 793
sahilmgandhi 18:6a4db94011d3 794 /* Check if segment is not owned by DMA */
sahilmgandhi 18:6a4db94011d3 795 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
sahilmgandhi 18:6a4db94011d3 796 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
sahilmgandhi 18:6a4db94011d3 797 {
sahilmgandhi 18:6a4db94011d3 798 /* Check if last segment */
sahilmgandhi 18:6a4db94011d3 799 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
sahilmgandhi 18:6a4db94011d3 800 {
sahilmgandhi 18:6a4db94011d3 801 /* increment segment count */
sahilmgandhi 18:6a4db94011d3 802 (heth->RxFrameInfos).SegCount++;
sahilmgandhi 18:6a4db94011d3 803
sahilmgandhi 18:6a4db94011d3 804 /* Check if last segment is first segment: one segment contains the frame */
sahilmgandhi 18:6a4db94011d3 805 if ((heth->RxFrameInfos).SegCount == 1U)
sahilmgandhi 18:6a4db94011d3 806 {
sahilmgandhi 18:6a4db94011d3 807 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
sahilmgandhi 18:6a4db94011d3 808 }
sahilmgandhi 18:6a4db94011d3 809
sahilmgandhi 18:6a4db94011d3 810 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
sahilmgandhi 18:6a4db94011d3 811
sahilmgandhi 18:6a4db94011d3 812 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
sahilmgandhi 18:6a4db94011d3 813 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
sahilmgandhi 18:6a4db94011d3 814 heth->RxFrameInfos.length = framelength;
sahilmgandhi 18:6a4db94011d3 815
sahilmgandhi 18:6a4db94011d3 816 /* Get the address of the buffer start address */
sahilmgandhi 18:6a4db94011d3 817 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
sahilmgandhi 18:6a4db94011d3 818 /* point to next descriptor */
sahilmgandhi 18:6a4db94011d3 819 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
sahilmgandhi 18:6a4db94011d3 820
sahilmgandhi 18:6a4db94011d3 821 /* Set HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 822 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 823
sahilmgandhi 18:6a4db94011d3 824 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 825 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 826
sahilmgandhi 18:6a4db94011d3 827 /* Return function status */
sahilmgandhi 18:6a4db94011d3 828 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 829 }
sahilmgandhi 18:6a4db94011d3 830 /* Check if first segment */
sahilmgandhi 18:6a4db94011d3 831 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
sahilmgandhi 18:6a4db94011d3 832 {
sahilmgandhi 18:6a4db94011d3 833 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
sahilmgandhi 18:6a4db94011d3 834 (heth->RxFrameInfos).LSRxDesc = NULL;
sahilmgandhi 18:6a4db94011d3 835 (heth->RxFrameInfos).SegCount = 1U;
sahilmgandhi 18:6a4db94011d3 836 /* Point to next descriptor */
sahilmgandhi 18:6a4db94011d3 837 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
sahilmgandhi 18:6a4db94011d3 838 }
sahilmgandhi 18:6a4db94011d3 839 /* Check if intermediate segment */
sahilmgandhi 18:6a4db94011d3 840 else
sahilmgandhi 18:6a4db94011d3 841 {
sahilmgandhi 18:6a4db94011d3 842 (heth->RxFrameInfos).SegCount++;
sahilmgandhi 18:6a4db94011d3 843 /* Point to next descriptor */
sahilmgandhi 18:6a4db94011d3 844 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
sahilmgandhi 18:6a4db94011d3 845 }
sahilmgandhi 18:6a4db94011d3 846 }
sahilmgandhi 18:6a4db94011d3 847
sahilmgandhi 18:6a4db94011d3 848 /* Set ETH HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 849 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 850
sahilmgandhi 18:6a4db94011d3 851 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 852 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 853
sahilmgandhi 18:6a4db94011d3 854 /* Return function status */
sahilmgandhi 18:6a4db94011d3 855 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 856 }
sahilmgandhi 18:6a4db94011d3 857
sahilmgandhi 18:6a4db94011d3 858 /**
sahilmgandhi 18:6a4db94011d3 859 * @brief Gets the Received frame in interrupt mode.
sahilmgandhi 18:6a4db94011d3 860 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 861 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 862 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 863 */
sahilmgandhi 18:6a4db94011d3 864 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 865 {
sahilmgandhi 18:6a4db94011d3 866 uint32_t descriptorscancounter = 0U;
sahilmgandhi 18:6a4db94011d3 867
sahilmgandhi 18:6a4db94011d3 868 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 869 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 870
sahilmgandhi 18:6a4db94011d3 871 /* Set ETH HAL State to BUSY */
sahilmgandhi 18:6a4db94011d3 872 heth->State = HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 873
sahilmgandhi 18:6a4db94011d3 874 /* Scan descriptors owned by CPU */
sahilmgandhi 18:6a4db94011d3 875 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
sahilmgandhi 18:6a4db94011d3 876 {
sahilmgandhi 18:6a4db94011d3 877 /* Just for security */
sahilmgandhi 18:6a4db94011d3 878 descriptorscancounter++;
sahilmgandhi 18:6a4db94011d3 879
sahilmgandhi 18:6a4db94011d3 880 /* Check if first segment in frame */
sahilmgandhi 18:6a4db94011d3 881 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
sahilmgandhi 18:6a4db94011d3 882 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
sahilmgandhi 18:6a4db94011d3 883 {
sahilmgandhi 18:6a4db94011d3 884 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
sahilmgandhi 18:6a4db94011d3 885 heth->RxFrameInfos.SegCount = 1U;
sahilmgandhi 18:6a4db94011d3 886 /* Point to next descriptor */
sahilmgandhi 18:6a4db94011d3 887 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
sahilmgandhi 18:6a4db94011d3 888 }
sahilmgandhi 18:6a4db94011d3 889 /* Check if intermediate segment */
sahilmgandhi 18:6a4db94011d3 890 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
sahilmgandhi 18:6a4db94011d3 891 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
sahilmgandhi 18:6a4db94011d3 892 {
sahilmgandhi 18:6a4db94011d3 893 /* Increment segment count */
sahilmgandhi 18:6a4db94011d3 894 (heth->RxFrameInfos.SegCount)++;
sahilmgandhi 18:6a4db94011d3 895 /* Point to next descriptor */
sahilmgandhi 18:6a4db94011d3 896 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
sahilmgandhi 18:6a4db94011d3 897 }
sahilmgandhi 18:6a4db94011d3 898 /* Should be last segment */
sahilmgandhi 18:6a4db94011d3 899 else
sahilmgandhi 18:6a4db94011d3 900 {
sahilmgandhi 18:6a4db94011d3 901 /* Last segment */
sahilmgandhi 18:6a4db94011d3 902 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
sahilmgandhi 18:6a4db94011d3 903
sahilmgandhi 18:6a4db94011d3 904 /* Increment segment count */
sahilmgandhi 18:6a4db94011d3 905 (heth->RxFrameInfos.SegCount)++;
sahilmgandhi 18:6a4db94011d3 906
sahilmgandhi 18:6a4db94011d3 907 /* Check if last segment is first segment: one segment contains the frame */
sahilmgandhi 18:6a4db94011d3 908 if ((heth->RxFrameInfos.SegCount) == 1U)
sahilmgandhi 18:6a4db94011d3 909 {
sahilmgandhi 18:6a4db94011d3 910 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
sahilmgandhi 18:6a4db94011d3 911 }
sahilmgandhi 18:6a4db94011d3 912
sahilmgandhi 18:6a4db94011d3 913 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
sahilmgandhi 18:6a4db94011d3 914 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
sahilmgandhi 18:6a4db94011d3 915
sahilmgandhi 18:6a4db94011d3 916 /* Get the address of the buffer start address */
sahilmgandhi 18:6a4db94011d3 917 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 /* Point to next descriptor */
sahilmgandhi 18:6a4db94011d3 920 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
sahilmgandhi 18:6a4db94011d3 921
sahilmgandhi 18:6a4db94011d3 922 /* Set HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 923 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 924
sahilmgandhi 18:6a4db94011d3 925 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 926 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 927
sahilmgandhi 18:6a4db94011d3 928 /* Return function status */
sahilmgandhi 18:6a4db94011d3 929 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 930 }
sahilmgandhi 18:6a4db94011d3 931 }
sahilmgandhi 18:6a4db94011d3 932
sahilmgandhi 18:6a4db94011d3 933 /* Set HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 934 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 937 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 938
sahilmgandhi 18:6a4db94011d3 939 /* Return function status */
sahilmgandhi 18:6a4db94011d3 940 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 941 }
sahilmgandhi 18:6a4db94011d3 942
sahilmgandhi 18:6a4db94011d3 943 /**
sahilmgandhi 18:6a4db94011d3 944 * @brief This function handles ETH interrupt request.
sahilmgandhi 18:6a4db94011d3 945 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 946 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 947 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 948 */
sahilmgandhi 18:6a4db94011d3 949 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 950 {
sahilmgandhi 18:6a4db94011d3 951 /* Frame received */
sahilmgandhi 18:6a4db94011d3 952 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
sahilmgandhi 18:6a4db94011d3 953 {
sahilmgandhi 18:6a4db94011d3 954 /* Receive complete callback */
sahilmgandhi 18:6a4db94011d3 955 HAL_ETH_RxCpltCallback(heth);
sahilmgandhi 18:6a4db94011d3 956
sahilmgandhi 18:6a4db94011d3 957 /* Clear the Eth DMA Rx IT pending bits */
sahilmgandhi 18:6a4db94011d3 958 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
sahilmgandhi 18:6a4db94011d3 959
sahilmgandhi 18:6a4db94011d3 960 /* Set HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 961 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 962
sahilmgandhi 18:6a4db94011d3 963 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 964 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 965
sahilmgandhi 18:6a4db94011d3 966 }
sahilmgandhi 18:6a4db94011d3 967 /* Frame transmitted */
sahilmgandhi 18:6a4db94011d3 968 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
sahilmgandhi 18:6a4db94011d3 969 {
sahilmgandhi 18:6a4db94011d3 970 /* Transfer complete callback */
sahilmgandhi 18:6a4db94011d3 971 HAL_ETH_TxCpltCallback(heth);
sahilmgandhi 18:6a4db94011d3 972
sahilmgandhi 18:6a4db94011d3 973 /* Clear the Eth DMA Tx IT pending bits */
sahilmgandhi 18:6a4db94011d3 974 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
sahilmgandhi 18:6a4db94011d3 975
sahilmgandhi 18:6a4db94011d3 976 /* Set HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 977 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 978
sahilmgandhi 18:6a4db94011d3 979 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 980 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 981 }
sahilmgandhi 18:6a4db94011d3 982
sahilmgandhi 18:6a4db94011d3 983 /* Clear the interrupt flags */
sahilmgandhi 18:6a4db94011d3 984 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
sahilmgandhi 18:6a4db94011d3 985
sahilmgandhi 18:6a4db94011d3 986 /* ETH DMA Error */
sahilmgandhi 18:6a4db94011d3 987 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
sahilmgandhi 18:6a4db94011d3 988 {
sahilmgandhi 18:6a4db94011d3 989 /* Ethernet Error callback */
sahilmgandhi 18:6a4db94011d3 990 HAL_ETH_ErrorCallback(heth);
sahilmgandhi 18:6a4db94011d3 991
sahilmgandhi 18:6a4db94011d3 992 /* Clear the interrupt flags */
sahilmgandhi 18:6a4db94011d3 993 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
sahilmgandhi 18:6a4db94011d3 994
sahilmgandhi 18:6a4db94011d3 995 /* Set HAL State to Ready */
sahilmgandhi 18:6a4db94011d3 996 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 997
sahilmgandhi 18:6a4db94011d3 998 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 999 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 1000 }
sahilmgandhi 18:6a4db94011d3 1001 }
sahilmgandhi 18:6a4db94011d3 1002
sahilmgandhi 18:6a4db94011d3 1003 /**
sahilmgandhi 18:6a4db94011d3 1004 * @brief Tx Transfer completed callbacks.
sahilmgandhi 18:6a4db94011d3 1005 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1006 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1007 * @retval None
sahilmgandhi 18:6a4db94011d3 1008 */
sahilmgandhi 18:6a4db94011d3 1009 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1010 {
sahilmgandhi 18:6a4db94011d3 1011 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1012 UNUSED(heth);
sahilmgandhi 18:6a4db94011d3 1013 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1014 the HAL_ETH_TxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1015 */
sahilmgandhi 18:6a4db94011d3 1016 }
sahilmgandhi 18:6a4db94011d3 1017
sahilmgandhi 18:6a4db94011d3 1018 /**
sahilmgandhi 18:6a4db94011d3 1019 * @brief Rx Transfer completed callbacks.
sahilmgandhi 18:6a4db94011d3 1020 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1021 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1022 * @retval None
sahilmgandhi 18:6a4db94011d3 1023 */
sahilmgandhi 18:6a4db94011d3 1024 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1025 {
sahilmgandhi 18:6a4db94011d3 1026 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1027 UNUSED(heth);
sahilmgandhi 18:6a4db94011d3 1028 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1029 the HAL_ETH_TxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1030 */
sahilmgandhi 18:6a4db94011d3 1031 }
sahilmgandhi 18:6a4db94011d3 1032
sahilmgandhi 18:6a4db94011d3 1033 /**
sahilmgandhi 18:6a4db94011d3 1034 * @brief Ethernet transfer error callbacks
sahilmgandhi 18:6a4db94011d3 1035 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1036 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1037 * @retval None
sahilmgandhi 18:6a4db94011d3 1038 */
sahilmgandhi 18:6a4db94011d3 1039 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1040 {
sahilmgandhi 18:6a4db94011d3 1041 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1042 UNUSED(heth);
sahilmgandhi 18:6a4db94011d3 1043 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1044 the HAL_ETH_TxCpltCallback could be implemented in the user file
sahilmgandhi 18:6a4db94011d3 1045 */
sahilmgandhi 18:6a4db94011d3 1046 }
sahilmgandhi 18:6a4db94011d3 1047
sahilmgandhi 18:6a4db94011d3 1048 /**
sahilmgandhi 18:6a4db94011d3 1049 * @brief Reads a PHY register
sahilmgandhi 18:6a4db94011d3 1050 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1051 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1052 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
sahilmgandhi 18:6a4db94011d3 1053 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1054 * PHY_BCR: Transceiver Basic Control Register,
sahilmgandhi 18:6a4db94011d3 1055 * PHY_BSR: Transceiver Basic Status Register.
sahilmgandhi 18:6a4db94011d3 1056 * More PHY register could be read depending on the used PHY
sahilmgandhi 18:6a4db94011d3 1057 * @param RegValue: PHY register value
sahilmgandhi 18:6a4db94011d3 1058 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1059 */
sahilmgandhi 18:6a4db94011d3 1060 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
sahilmgandhi 18:6a4db94011d3 1061 {
sahilmgandhi 18:6a4db94011d3 1062 uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1063 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 1064
sahilmgandhi 18:6a4db94011d3 1065 /* Check parameters */
sahilmgandhi 18:6a4db94011d3 1066 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
sahilmgandhi 18:6a4db94011d3 1067
sahilmgandhi 18:6a4db94011d3 1068 /* Check the ETH peripheral state */
sahilmgandhi 18:6a4db94011d3 1069 if(heth->State == HAL_ETH_STATE_BUSY_RD)
sahilmgandhi 18:6a4db94011d3 1070 {
sahilmgandhi 18:6a4db94011d3 1071 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1072 }
sahilmgandhi 18:6a4db94011d3 1073 /* Set ETH HAL State to BUSY_RD */
sahilmgandhi 18:6a4db94011d3 1074 heth->State = HAL_ETH_STATE_BUSY_RD;
sahilmgandhi 18:6a4db94011d3 1075
sahilmgandhi 18:6a4db94011d3 1076 /* Get the ETHERNET MACMIIAR value */
sahilmgandhi 18:6a4db94011d3 1077 tmpreg1 = heth->Instance->MACMIIAR;
sahilmgandhi 18:6a4db94011d3 1078
sahilmgandhi 18:6a4db94011d3 1079 /* Keep only the CSR Clock Range CR[2:0] bits value */
sahilmgandhi 18:6a4db94011d3 1080 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
sahilmgandhi 18:6a4db94011d3 1081
sahilmgandhi 18:6a4db94011d3 1082 /* Prepare the MII address register value */
sahilmgandhi 18:6a4db94011d3 1083 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
sahilmgandhi 18:6a4db94011d3 1084 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
sahilmgandhi 18:6a4db94011d3 1085 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
sahilmgandhi 18:6a4db94011d3 1086 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
sahilmgandhi 18:6a4db94011d3 1087
sahilmgandhi 18:6a4db94011d3 1088 /* Write the result value into the MII Address register */
sahilmgandhi 18:6a4db94011d3 1089 heth->Instance->MACMIIAR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1090
sahilmgandhi 18:6a4db94011d3 1091 /* Get tick */
sahilmgandhi 18:6a4db94011d3 1092 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 1093
sahilmgandhi 18:6a4db94011d3 1094 /* Check for the Busy flag */
sahilmgandhi 18:6a4db94011d3 1095 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
sahilmgandhi 18:6a4db94011d3 1096 {
sahilmgandhi 18:6a4db94011d3 1097 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 1098 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
sahilmgandhi 18:6a4db94011d3 1099 {
sahilmgandhi 18:6a4db94011d3 1100 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1101
sahilmgandhi 18:6a4db94011d3 1102 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1103 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 1104
sahilmgandhi 18:6a4db94011d3 1105 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1106 }
sahilmgandhi 18:6a4db94011d3 1107
sahilmgandhi 18:6a4db94011d3 1108 tmpreg1 = heth->Instance->MACMIIAR;
sahilmgandhi 18:6a4db94011d3 1109 }
sahilmgandhi 18:6a4db94011d3 1110
sahilmgandhi 18:6a4db94011d3 1111 /* Get MACMIIDR value */
sahilmgandhi 18:6a4db94011d3 1112 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
sahilmgandhi 18:6a4db94011d3 1113
sahilmgandhi 18:6a4db94011d3 1114 /* Set ETH HAL State to READY */
sahilmgandhi 18:6a4db94011d3 1115 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1116
sahilmgandhi 18:6a4db94011d3 1117 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1118 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1119 }
sahilmgandhi 18:6a4db94011d3 1120
sahilmgandhi 18:6a4db94011d3 1121 /**
sahilmgandhi 18:6a4db94011d3 1122 * @brief Writes to a PHY register.
sahilmgandhi 18:6a4db94011d3 1123 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1124 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1125 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
sahilmgandhi 18:6a4db94011d3 1126 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1127 * PHY_BCR: Transceiver Control Register.
sahilmgandhi 18:6a4db94011d3 1128 * More PHY register could be written depending on the used PHY
sahilmgandhi 18:6a4db94011d3 1129 * @param RegValue: the value to write
sahilmgandhi 18:6a4db94011d3 1130 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1131 */
sahilmgandhi 18:6a4db94011d3 1132 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
sahilmgandhi 18:6a4db94011d3 1133 {
sahilmgandhi 18:6a4db94011d3 1134 uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1135 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 1136
sahilmgandhi 18:6a4db94011d3 1137 /* Check parameters */
sahilmgandhi 18:6a4db94011d3 1138 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
sahilmgandhi 18:6a4db94011d3 1139
sahilmgandhi 18:6a4db94011d3 1140 /* Check the ETH peripheral state */
sahilmgandhi 18:6a4db94011d3 1141 if(heth->State == HAL_ETH_STATE_BUSY_WR)
sahilmgandhi 18:6a4db94011d3 1142 {
sahilmgandhi 18:6a4db94011d3 1143 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1144 }
sahilmgandhi 18:6a4db94011d3 1145 /* Set ETH HAL State to BUSY_WR */
sahilmgandhi 18:6a4db94011d3 1146 heth->State = HAL_ETH_STATE_BUSY_WR;
sahilmgandhi 18:6a4db94011d3 1147
sahilmgandhi 18:6a4db94011d3 1148 /* Get the ETHERNET MACMIIAR value */
sahilmgandhi 18:6a4db94011d3 1149 tmpreg1 = heth->Instance->MACMIIAR;
sahilmgandhi 18:6a4db94011d3 1150
sahilmgandhi 18:6a4db94011d3 1151 /* Keep only the CSR Clock Range CR[2:0] bits value */
sahilmgandhi 18:6a4db94011d3 1152 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
sahilmgandhi 18:6a4db94011d3 1153
sahilmgandhi 18:6a4db94011d3 1154 /* Prepare the MII register address value */
sahilmgandhi 18:6a4db94011d3 1155 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
sahilmgandhi 18:6a4db94011d3 1156 tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
sahilmgandhi 18:6a4db94011d3 1157 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
sahilmgandhi 18:6a4db94011d3 1158 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
sahilmgandhi 18:6a4db94011d3 1159
sahilmgandhi 18:6a4db94011d3 1160 /* Give the value to the MII data register */
sahilmgandhi 18:6a4db94011d3 1161 heth->Instance->MACMIIDR = (uint16_t)RegValue;
sahilmgandhi 18:6a4db94011d3 1162
sahilmgandhi 18:6a4db94011d3 1163 /* Write the result value into the MII Address register */
sahilmgandhi 18:6a4db94011d3 1164 heth->Instance->MACMIIAR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1165
sahilmgandhi 18:6a4db94011d3 1166 /* Get tick */
sahilmgandhi 18:6a4db94011d3 1167 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 1168
sahilmgandhi 18:6a4db94011d3 1169 /* Check for the Busy flag */
sahilmgandhi 18:6a4db94011d3 1170 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
sahilmgandhi 18:6a4db94011d3 1171 {
sahilmgandhi 18:6a4db94011d3 1172 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 1173 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
sahilmgandhi 18:6a4db94011d3 1174 {
sahilmgandhi 18:6a4db94011d3 1175 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1176
sahilmgandhi 18:6a4db94011d3 1177 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1178 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 1179
sahilmgandhi 18:6a4db94011d3 1180 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 1181 }
sahilmgandhi 18:6a4db94011d3 1182
sahilmgandhi 18:6a4db94011d3 1183 tmpreg1 = heth->Instance->MACMIIAR;
sahilmgandhi 18:6a4db94011d3 1184 }
sahilmgandhi 18:6a4db94011d3 1185
sahilmgandhi 18:6a4db94011d3 1186 /* Set ETH HAL State to READY */
sahilmgandhi 18:6a4db94011d3 1187 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1188
sahilmgandhi 18:6a4db94011d3 1189 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1190 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1191 }
sahilmgandhi 18:6a4db94011d3 1192
sahilmgandhi 18:6a4db94011d3 1193 /**
sahilmgandhi 18:6a4db94011d3 1194 * @}
sahilmgandhi 18:6a4db94011d3 1195 */
sahilmgandhi 18:6a4db94011d3 1196
sahilmgandhi 18:6a4db94011d3 1197 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 1198 * @brief Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 1199 *
sahilmgandhi 18:6a4db94011d3 1200 @verbatim
sahilmgandhi 18:6a4db94011d3 1201 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1202 ##### Peripheral Control functions #####
sahilmgandhi 18:6a4db94011d3 1203 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1204 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 1205 (+) Enable MAC and DMA transmission and reception.
sahilmgandhi 18:6a4db94011d3 1206 HAL_ETH_Start();
sahilmgandhi 18:6a4db94011d3 1207 (+) Disable MAC and DMA transmission and reception.
sahilmgandhi 18:6a4db94011d3 1208 HAL_ETH_Stop();
sahilmgandhi 18:6a4db94011d3 1209 (+) Set the MAC configuration in runtime mode
sahilmgandhi 18:6a4db94011d3 1210 HAL_ETH_ConfigMAC();
sahilmgandhi 18:6a4db94011d3 1211 (+) Set the DMA configuration in runtime mode
sahilmgandhi 18:6a4db94011d3 1212 HAL_ETH_ConfigDMA();
sahilmgandhi 18:6a4db94011d3 1213
sahilmgandhi 18:6a4db94011d3 1214 @endverbatim
sahilmgandhi 18:6a4db94011d3 1215 * @{
sahilmgandhi 18:6a4db94011d3 1216 */
sahilmgandhi 18:6a4db94011d3 1217
sahilmgandhi 18:6a4db94011d3 1218 /**
sahilmgandhi 18:6a4db94011d3 1219 * @brief Enables Ethernet MAC and DMA reception/transmission
sahilmgandhi 18:6a4db94011d3 1220 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1221 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1222 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1223 */
sahilmgandhi 18:6a4db94011d3 1224 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1225 {
sahilmgandhi 18:6a4db94011d3 1226 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1227 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 1228
sahilmgandhi 18:6a4db94011d3 1229 /* Set the ETH peripheral state to BUSY */
sahilmgandhi 18:6a4db94011d3 1230 heth->State = HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1231
sahilmgandhi 18:6a4db94011d3 1232 /* Enable transmit state machine of the MAC for transmission on the MII */
sahilmgandhi 18:6a4db94011d3 1233 ETH_MACTransmissionEnable(heth);
sahilmgandhi 18:6a4db94011d3 1234
sahilmgandhi 18:6a4db94011d3 1235 /* Enable receive state machine of the MAC for reception from the MII */
sahilmgandhi 18:6a4db94011d3 1236 ETH_MACReceptionEnable(heth);
sahilmgandhi 18:6a4db94011d3 1237
sahilmgandhi 18:6a4db94011d3 1238 /* Flush Transmit FIFO */
sahilmgandhi 18:6a4db94011d3 1239 ETH_FlushTransmitFIFO(heth);
sahilmgandhi 18:6a4db94011d3 1240
sahilmgandhi 18:6a4db94011d3 1241 /* Start DMA transmission */
sahilmgandhi 18:6a4db94011d3 1242 ETH_DMATransmissionEnable(heth);
sahilmgandhi 18:6a4db94011d3 1243
sahilmgandhi 18:6a4db94011d3 1244 /* Start DMA reception */
sahilmgandhi 18:6a4db94011d3 1245 ETH_DMAReceptionEnable(heth);
sahilmgandhi 18:6a4db94011d3 1246
sahilmgandhi 18:6a4db94011d3 1247 /* Set the ETH state to READY*/
sahilmgandhi 18:6a4db94011d3 1248 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1249
sahilmgandhi 18:6a4db94011d3 1250 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1251 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 1252
sahilmgandhi 18:6a4db94011d3 1253 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1254 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1255 }
sahilmgandhi 18:6a4db94011d3 1256
sahilmgandhi 18:6a4db94011d3 1257 /**
sahilmgandhi 18:6a4db94011d3 1258 * @brief Stop Ethernet MAC and DMA reception/transmission
sahilmgandhi 18:6a4db94011d3 1259 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1260 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1261 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1262 */
sahilmgandhi 18:6a4db94011d3 1263 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1264 {
sahilmgandhi 18:6a4db94011d3 1265 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1266 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 1267
sahilmgandhi 18:6a4db94011d3 1268 /* Set the ETH peripheral state to BUSY */
sahilmgandhi 18:6a4db94011d3 1269 heth->State = HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1270
sahilmgandhi 18:6a4db94011d3 1271 /* Stop DMA transmission */
sahilmgandhi 18:6a4db94011d3 1272 ETH_DMATransmissionDisable(heth);
sahilmgandhi 18:6a4db94011d3 1273
sahilmgandhi 18:6a4db94011d3 1274 /* Stop DMA reception */
sahilmgandhi 18:6a4db94011d3 1275 ETH_DMAReceptionDisable(heth);
sahilmgandhi 18:6a4db94011d3 1276
sahilmgandhi 18:6a4db94011d3 1277 /* Disable receive state machine of the MAC for reception from the MII */
sahilmgandhi 18:6a4db94011d3 1278 ETH_MACReceptionDisable(heth);
sahilmgandhi 18:6a4db94011d3 1279
sahilmgandhi 18:6a4db94011d3 1280 /* Flush Transmit FIFO */
sahilmgandhi 18:6a4db94011d3 1281 ETH_FlushTransmitFIFO(heth);
sahilmgandhi 18:6a4db94011d3 1282
sahilmgandhi 18:6a4db94011d3 1283 /* Disable transmit state machine of the MAC for transmission on the MII */
sahilmgandhi 18:6a4db94011d3 1284 ETH_MACTransmissionDisable(heth);
sahilmgandhi 18:6a4db94011d3 1285
sahilmgandhi 18:6a4db94011d3 1286 /* Set the ETH state*/
sahilmgandhi 18:6a4db94011d3 1287 heth->State = HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1288
sahilmgandhi 18:6a4db94011d3 1289 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1290 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 1291
sahilmgandhi 18:6a4db94011d3 1292 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1293 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1294 }
sahilmgandhi 18:6a4db94011d3 1295
sahilmgandhi 18:6a4db94011d3 1296 /**
sahilmgandhi 18:6a4db94011d3 1297 * @brief Set ETH MAC Configuration.
sahilmgandhi 18:6a4db94011d3 1298 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1299 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1300 * @param macconf: MAC Configuration structure
sahilmgandhi 18:6a4db94011d3 1301 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1302 */
sahilmgandhi 18:6a4db94011d3 1303 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
sahilmgandhi 18:6a4db94011d3 1304 {
sahilmgandhi 18:6a4db94011d3 1305 uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1306
sahilmgandhi 18:6a4db94011d3 1307 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1308 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 1309
sahilmgandhi 18:6a4db94011d3 1310 /* Set the ETH peripheral state to BUSY */
sahilmgandhi 18:6a4db94011d3 1311 heth->State= HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1312
sahilmgandhi 18:6a4db94011d3 1313 assert_param(IS_ETH_SPEED(heth->Init.Speed));
sahilmgandhi 18:6a4db94011d3 1314 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
sahilmgandhi 18:6a4db94011d3 1315
sahilmgandhi 18:6a4db94011d3 1316 if (macconf != NULL)
sahilmgandhi 18:6a4db94011d3 1317 {
sahilmgandhi 18:6a4db94011d3 1318 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1319 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
sahilmgandhi 18:6a4db94011d3 1320 assert_param(IS_ETH_JABBER(macconf->Jabber));
sahilmgandhi 18:6a4db94011d3 1321 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
sahilmgandhi 18:6a4db94011d3 1322 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
sahilmgandhi 18:6a4db94011d3 1323 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
sahilmgandhi 18:6a4db94011d3 1324 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
sahilmgandhi 18:6a4db94011d3 1325 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
sahilmgandhi 18:6a4db94011d3 1326 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
sahilmgandhi 18:6a4db94011d3 1327 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
sahilmgandhi 18:6a4db94011d3 1328 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
sahilmgandhi 18:6a4db94011d3 1329 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
sahilmgandhi 18:6a4db94011d3 1330 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
sahilmgandhi 18:6a4db94011d3 1331 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
sahilmgandhi 18:6a4db94011d3 1332 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
sahilmgandhi 18:6a4db94011d3 1333 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
sahilmgandhi 18:6a4db94011d3 1334 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
sahilmgandhi 18:6a4db94011d3 1335 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
sahilmgandhi 18:6a4db94011d3 1336 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
sahilmgandhi 18:6a4db94011d3 1337 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
sahilmgandhi 18:6a4db94011d3 1338 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
sahilmgandhi 18:6a4db94011d3 1339 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
sahilmgandhi 18:6a4db94011d3 1340 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
sahilmgandhi 18:6a4db94011d3 1341 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
sahilmgandhi 18:6a4db94011d3 1342 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
sahilmgandhi 18:6a4db94011d3 1343 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
sahilmgandhi 18:6a4db94011d3 1344 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
sahilmgandhi 18:6a4db94011d3 1345 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
sahilmgandhi 18:6a4db94011d3 1346
sahilmgandhi 18:6a4db94011d3 1347 /*------------------------ ETHERNET MACCR Configuration --------------------*/
sahilmgandhi 18:6a4db94011d3 1348 /* Get the ETHERNET MACCR value */
sahilmgandhi 18:6a4db94011d3 1349 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1350 /* Clear WD, PCE, PS, TE and RE bits */
sahilmgandhi 18:6a4db94011d3 1351 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
sahilmgandhi 18:6a4db94011d3 1352
sahilmgandhi 18:6a4db94011d3 1353 tmpreg1 |= (uint32_t)(macconf->Watchdog |
sahilmgandhi 18:6a4db94011d3 1354 macconf->Jabber |
sahilmgandhi 18:6a4db94011d3 1355 macconf->InterFrameGap |
sahilmgandhi 18:6a4db94011d3 1356 macconf->CarrierSense |
sahilmgandhi 18:6a4db94011d3 1357 (heth->Init).Speed |
sahilmgandhi 18:6a4db94011d3 1358 macconf->ReceiveOwn |
sahilmgandhi 18:6a4db94011d3 1359 macconf->LoopbackMode |
sahilmgandhi 18:6a4db94011d3 1360 (heth->Init).DuplexMode |
sahilmgandhi 18:6a4db94011d3 1361 macconf->ChecksumOffload |
sahilmgandhi 18:6a4db94011d3 1362 macconf->RetryTransmission |
sahilmgandhi 18:6a4db94011d3 1363 macconf->AutomaticPadCRCStrip |
sahilmgandhi 18:6a4db94011d3 1364 macconf->BackOffLimit |
sahilmgandhi 18:6a4db94011d3 1365 macconf->DeferralCheck);
sahilmgandhi 18:6a4db94011d3 1366
sahilmgandhi 18:6a4db94011d3 1367 /* Write to ETHERNET MACCR */
sahilmgandhi 18:6a4db94011d3 1368 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
sahilmgandhi 18:6a4db94011d3 1369
sahilmgandhi 18:6a4db94011d3 1370 /* Wait until the write operation will be taken into account :
sahilmgandhi 18:6a4db94011d3 1371 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1372 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1373 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1374 (heth->Instance)->MACCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1375
sahilmgandhi 18:6a4db94011d3 1376 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
sahilmgandhi 18:6a4db94011d3 1377 /* Write to ETHERNET MACFFR */
sahilmgandhi 18:6a4db94011d3 1378 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
sahilmgandhi 18:6a4db94011d3 1379 macconf->SourceAddrFilter |
sahilmgandhi 18:6a4db94011d3 1380 macconf->PassControlFrames |
sahilmgandhi 18:6a4db94011d3 1381 macconf->BroadcastFramesReception |
sahilmgandhi 18:6a4db94011d3 1382 macconf->DestinationAddrFilter |
sahilmgandhi 18:6a4db94011d3 1383 macconf->PromiscuousMode |
sahilmgandhi 18:6a4db94011d3 1384 macconf->MulticastFramesFilter |
sahilmgandhi 18:6a4db94011d3 1385 macconf->UnicastFramesFilter);
sahilmgandhi 18:6a4db94011d3 1386
sahilmgandhi 18:6a4db94011d3 1387 /* Wait until the write operation will be taken into account :
sahilmgandhi 18:6a4db94011d3 1388 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1389 tmpreg1 = (heth->Instance)->MACFFR;
sahilmgandhi 18:6a4db94011d3 1390 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1391 (heth->Instance)->MACFFR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1392
sahilmgandhi 18:6a4db94011d3 1393 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
sahilmgandhi 18:6a4db94011d3 1394 /* Write to ETHERNET MACHTHR */
sahilmgandhi 18:6a4db94011d3 1395 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
sahilmgandhi 18:6a4db94011d3 1396
sahilmgandhi 18:6a4db94011d3 1397 /* Write to ETHERNET MACHTLR */
sahilmgandhi 18:6a4db94011d3 1398 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
sahilmgandhi 18:6a4db94011d3 1399 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
sahilmgandhi 18:6a4db94011d3 1400
sahilmgandhi 18:6a4db94011d3 1401 /* Get the ETHERNET MACFCR value */
sahilmgandhi 18:6a4db94011d3 1402 tmpreg1 = (heth->Instance)->MACFCR;
sahilmgandhi 18:6a4db94011d3 1403 /* Clear xx bits */
sahilmgandhi 18:6a4db94011d3 1404 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
sahilmgandhi 18:6a4db94011d3 1405
sahilmgandhi 18:6a4db94011d3 1406 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
sahilmgandhi 18:6a4db94011d3 1407 macconf->ZeroQuantaPause |
sahilmgandhi 18:6a4db94011d3 1408 macconf->PauseLowThreshold |
sahilmgandhi 18:6a4db94011d3 1409 macconf->UnicastPauseFrameDetect |
sahilmgandhi 18:6a4db94011d3 1410 macconf->ReceiveFlowControl |
sahilmgandhi 18:6a4db94011d3 1411 macconf->TransmitFlowControl);
sahilmgandhi 18:6a4db94011d3 1412
sahilmgandhi 18:6a4db94011d3 1413 /* Write to ETHERNET MACFCR */
sahilmgandhi 18:6a4db94011d3 1414 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
sahilmgandhi 18:6a4db94011d3 1415
sahilmgandhi 18:6a4db94011d3 1416 /* Wait until the write operation will be taken into account :
sahilmgandhi 18:6a4db94011d3 1417 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1418 tmpreg1 = (heth->Instance)->MACFCR;
sahilmgandhi 18:6a4db94011d3 1419 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1420 (heth->Instance)->MACFCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1421
sahilmgandhi 18:6a4db94011d3 1422 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
sahilmgandhi 18:6a4db94011d3 1423 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
sahilmgandhi 18:6a4db94011d3 1424 macconf->VLANTagIdentifier);
sahilmgandhi 18:6a4db94011d3 1425
sahilmgandhi 18:6a4db94011d3 1426 /* Wait until the write operation will be taken into account :
sahilmgandhi 18:6a4db94011d3 1427 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1428 tmpreg1 = (heth->Instance)->MACVLANTR;
sahilmgandhi 18:6a4db94011d3 1429 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1430 (heth->Instance)->MACVLANTR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1431 }
sahilmgandhi 18:6a4db94011d3 1432 else /* macconf == NULL : here we just configure Speed and Duplex mode */
sahilmgandhi 18:6a4db94011d3 1433 {
sahilmgandhi 18:6a4db94011d3 1434 /*------------------------ ETHERNET MACCR Configuration --------------------*/
sahilmgandhi 18:6a4db94011d3 1435 /* Get the ETHERNET MACCR value */
sahilmgandhi 18:6a4db94011d3 1436 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1437
sahilmgandhi 18:6a4db94011d3 1438 /* Clear FES and DM bits */
sahilmgandhi 18:6a4db94011d3 1439 tmpreg1 &= ~((uint32_t)0x00004800U);
sahilmgandhi 18:6a4db94011d3 1440
sahilmgandhi 18:6a4db94011d3 1441 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
sahilmgandhi 18:6a4db94011d3 1442
sahilmgandhi 18:6a4db94011d3 1443 /* Write to ETHERNET MACCR */
sahilmgandhi 18:6a4db94011d3 1444 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
sahilmgandhi 18:6a4db94011d3 1445
sahilmgandhi 18:6a4db94011d3 1446 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1447 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1448 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1449 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1450 (heth->Instance)->MACCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1451 }
sahilmgandhi 18:6a4db94011d3 1452
sahilmgandhi 18:6a4db94011d3 1453 /* Set the ETH state to Ready */
sahilmgandhi 18:6a4db94011d3 1454 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1455
sahilmgandhi 18:6a4db94011d3 1456 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1457 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 1458
sahilmgandhi 18:6a4db94011d3 1459 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1460 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1461 }
sahilmgandhi 18:6a4db94011d3 1462
sahilmgandhi 18:6a4db94011d3 1463 /**
sahilmgandhi 18:6a4db94011d3 1464 * @brief Sets ETH DMA Configuration.
sahilmgandhi 18:6a4db94011d3 1465 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1466 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1467 * @param dmaconf: DMA Configuration structure
sahilmgandhi 18:6a4db94011d3 1468 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1469 */
sahilmgandhi 18:6a4db94011d3 1470 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
sahilmgandhi 18:6a4db94011d3 1471 {
sahilmgandhi 18:6a4db94011d3 1472 uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1473
sahilmgandhi 18:6a4db94011d3 1474 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1475 __HAL_LOCK(heth);
sahilmgandhi 18:6a4db94011d3 1476
sahilmgandhi 18:6a4db94011d3 1477 /* Set the ETH peripheral state to BUSY */
sahilmgandhi 18:6a4db94011d3 1478 heth->State= HAL_ETH_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 1479
sahilmgandhi 18:6a4db94011d3 1480 /* Check parameters */
sahilmgandhi 18:6a4db94011d3 1481 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
sahilmgandhi 18:6a4db94011d3 1482 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
sahilmgandhi 18:6a4db94011d3 1483 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
sahilmgandhi 18:6a4db94011d3 1484 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
sahilmgandhi 18:6a4db94011d3 1485 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
sahilmgandhi 18:6a4db94011d3 1486 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
sahilmgandhi 18:6a4db94011d3 1487 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
sahilmgandhi 18:6a4db94011d3 1488 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
sahilmgandhi 18:6a4db94011d3 1489 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
sahilmgandhi 18:6a4db94011d3 1490 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
sahilmgandhi 18:6a4db94011d3 1491 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
sahilmgandhi 18:6a4db94011d3 1492 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
sahilmgandhi 18:6a4db94011d3 1493 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
sahilmgandhi 18:6a4db94011d3 1494 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
sahilmgandhi 18:6a4db94011d3 1495 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
sahilmgandhi 18:6a4db94011d3 1496 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
sahilmgandhi 18:6a4db94011d3 1497
sahilmgandhi 18:6a4db94011d3 1498 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
sahilmgandhi 18:6a4db94011d3 1499 /* Get the ETHERNET DMAOMR value */
sahilmgandhi 18:6a4db94011d3 1500 tmpreg1 = (heth->Instance)->DMAOMR;
sahilmgandhi 18:6a4db94011d3 1501 /* Clear xx bits */
sahilmgandhi 18:6a4db94011d3 1502 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
sahilmgandhi 18:6a4db94011d3 1503
sahilmgandhi 18:6a4db94011d3 1504 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
sahilmgandhi 18:6a4db94011d3 1505 dmaconf->ReceiveStoreForward |
sahilmgandhi 18:6a4db94011d3 1506 dmaconf->FlushReceivedFrame |
sahilmgandhi 18:6a4db94011d3 1507 dmaconf->TransmitStoreForward |
sahilmgandhi 18:6a4db94011d3 1508 dmaconf->TransmitThresholdControl |
sahilmgandhi 18:6a4db94011d3 1509 dmaconf->ForwardErrorFrames |
sahilmgandhi 18:6a4db94011d3 1510 dmaconf->ForwardUndersizedGoodFrames |
sahilmgandhi 18:6a4db94011d3 1511 dmaconf->ReceiveThresholdControl |
sahilmgandhi 18:6a4db94011d3 1512 dmaconf->SecondFrameOperate);
sahilmgandhi 18:6a4db94011d3 1513
sahilmgandhi 18:6a4db94011d3 1514 /* Write to ETHERNET DMAOMR */
sahilmgandhi 18:6a4db94011d3 1515 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
sahilmgandhi 18:6a4db94011d3 1516
sahilmgandhi 18:6a4db94011d3 1517 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1518 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1519 tmpreg1 = (heth->Instance)->DMAOMR;
sahilmgandhi 18:6a4db94011d3 1520 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1521 (heth->Instance)->DMAOMR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1522
sahilmgandhi 18:6a4db94011d3 1523 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
sahilmgandhi 18:6a4db94011d3 1524 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
sahilmgandhi 18:6a4db94011d3 1525 dmaconf->FixedBurst |
sahilmgandhi 18:6a4db94011d3 1526 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
sahilmgandhi 18:6a4db94011d3 1527 dmaconf->TxDMABurstLength |
sahilmgandhi 18:6a4db94011d3 1528 dmaconf->EnhancedDescriptorFormat |
sahilmgandhi 18:6a4db94011d3 1529 (dmaconf->DescriptorSkipLength << 2U) |
sahilmgandhi 18:6a4db94011d3 1530 dmaconf->DMAArbitration |
sahilmgandhi 18:6a4db94011d3 1531 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
sahilmgandhi 18:6a4db94011d3 1532
sahilmgandhi 18:6a4db94011d3 1533 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1534 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1535 tmpreg1 = (heth->Instance)->DMABMR;
sahilmgandhi 18:6a4db94011d3 1536 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1537 (heth->Instance)->DMABMR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1538
sahilmgandhi 18:6a4db94011d3 1539 /* Set the ETH state to Ready */
sahilmgandhi 18:6a4db94011d3 1540 heth->State= HAL_ETH_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1541
sahilmgandhi 18:6a4db94011d3 1542 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1543 __HAL_UNLOCK(heth);
sahilmgandhi 18:6a4db94011d3 1544
sahilmgandhi 18:6a4db94011d3 1545 /* Return function status */
sahilmgandhi 18:6a4db94011d3 1546 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1547 }
sahilmgandhi 18:6a4db94011d3 1548
sahilmgandhi 18:6a4db94011d3 1549 /**
sahilmgandhi 18:6a4db94011d3 1550 * @}
sahilmgandhi 18:6a4db94011d3 1551 */
sahilmgandhi 18:6a4db94011d3 1552
sahilmgandhi 18:6a4db94011d3 1553 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1554 * @brief Peripheral State functions
sahilmgandhi 18:6a4db94011d3 1555 *
sahilmgandhi 18:6a4db94011d3 1556 @verbatim
sahilmgandhi 18:6a4db94011d3 1557 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1558 ##### Peripheral State functions #####
sahilmgandhi 18:6a4db94011d3 1559 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1560 [..]
sahilmgandhi 18:6a4db94011d3 1561 This subsection permits to get in run-time the status of the peripheral
sahilmgandhi 18:6a4db94011d3 1562 and the data flow.
sahilmgandhi 18:6a4db94011d3 1563 (+) Get the ETH handle state:
sahilmgandhi 18:6a4db94011d3 1564 HAL_ETH_GetState();
sahilmgandhi 18:6a4db94011d3 1565
sahilmgandhi 18:6a4db94011d3 1566
sahilmgandhi 18:6a4db94011d3 1567 @endverbatim
sahilmgandhi 18:6a4db94011d3 1568 * @{
sahilmgandhi 18:6a4db94011d3 1569 */
sahilmgandhi 18:6a4db94011d3 1570
sahilmgandhi 18:6a4db94011d3 1571 /**
sahilmgandhi 18:6a4db94011d3 1572 * @brief Return the ETH HAL state
sahilmgandhi 18:6a4db94011d3 1573 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1574 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1575 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1576 */
sahilmgandhi 18:6a4db94011d3 1577 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1578 {
sahilmgandhi 18:6a4db94011d3 1579 /* Return ETH state */
sahilmgandhi 18:6a4db94011d3 1580 return heth->State;
sahilmgandhi 18:6a4db94011d3 1581 }
sahilmgandhi 18:6a4db94011d3 1582
sahilmgandhi 18:6a4db94011d3 1583 /**
sahilmgandhi 18:6a4db94011d3 1584 * @}
sahilmgandhi 18:6a4db94011d3 1585 */
sahilmgandhi 18:6a4db94011d3 1586
sahilmgandhi 18:6a4db94011d3 1587 /**
sahilmgandhi 18:6a4db94011d3 1588 * @}
sahilmgandhi 18:6a4db94011d3 1589 */
sahilmgandhi 18:6a4db94011d3 1590
sahilmgandhi 18:6a4db94011d3 1591 /** @addtogroup ETH_Private_Functions
sahilmgandhi 18:6a4db94011d3 1592 * @{
sahilmgandhi 18:6a4db94011d3 1593 */
sahilmgandhi 18:6a4db94011d3 1594
sahilmgandhi 18:6a4db94011d3 1595 /**
sahilmgandhi 18:6a4db94011d3 1596 * @brief Configures Ethernet MAC and DMA with default parameters.
sahilmgandhi 18:6a4db94011d3 1597 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1598 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1599 * @param err: Ethernet Init error
sahilmgandhi 18:6a4db94011d3 1600 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1601 */
sahilmgandhi 18:6a4db94011d3 1602 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
sahilmgandhi 18:6a4db94011d3 1603 {
sahilmgandhi 18:6a4db94011d3 1604 ETH_MACInitTypeDef macinit;
sahilmgandhi 18:6a4db94011d3 1605 ETH_DMAInitTypeDef dmainit;
sahilmgandhi 18:6a4db94011d3 1606 uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1607
sahilmgandhi 18:6a4db94011d3 1608 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
sahilmgandhi 18:6a4db94011d3 1609 {
sahilmgandhi 18:6a4db94011d3 1610 /* Set Ethernet duplex mode to Full-duplex */
sahilmgandhi 18:6a4db94011d3 1611 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
sahilmgandhi 18:6a4db94011d3 1612
sahilmgandhi 18:6a4db94011d3 1613 /* Set Ethernet speed to 100M */
sahilmgandhi 18:6a4db94011d3 1614 (heth->Init).Speed = ETH_SPEED_100M;
sahilmgandhi 18:6a4db94011d3 1615 }
sahilmgandhi 18:6a4db94011d3 1616
sahilmgandhi 18:6a4db94011d3 1617 /* Ethernet MAC default initialization **************************************/
sahilmgandhi 18:6a4db94011d3 1618 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
sahilmgandhi 18:6a4db94011d3 1619 macinit.Jabber = ETH_JABBER_ENABLE;
sahilmgandhi 18:6a4db94011d3 1620 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
sahilmgandhi 18:6a4db94011d3 1621 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
sahilmgandhi 18:6a4db94011d3 1622 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
sahilmgandhi 18:6a4db94011d3 1623 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
sahilmgandhi 18:6a4db94011d3 1624 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
sahilmgandhi 18:6a4db94011d3 1625 {
sahilmgandhi 18:6a4db94011d3 1626 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
sahilmgandhi 18:6a4db94011d3 1627 }
sahilmgandhi 18:6a4db94011d3 1628 else
sahilmgandhi 18:6a4db94011d3 1629 {
sahilmgandhi 18:6a4db94011d3 1630 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
sahilmgandhi 18:6a4db94011d3 1631 }
sahilmgandhi 18:6a4db94011d3 1632 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
sahilmgandhi 18:6a4db94011d3 1633 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
sahilmgandhi 18:6a4db94011d3 1634 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
sahilmgandhi 18:6a4db94011d3 1635 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
sahilmgandhi 18:6a4db94011d3 1636 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
sahilmgandhi 18:6a4db94011d3 1637 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
sahilmgandhi 18:6a4db94011d3 1638 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
sahilmgandhi 18:6a4db94011d3 1639 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
sahilmgandhi 18:6a4db94011d3 1640 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
sahilmgandhi 18:6a4db94011d3 1641 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
sahilmgandhi 18:6a4db94011d3 1642 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
sahilmgandhi 18:6a4db94011d3 1643 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
sahilmgandhi 18:6a4db94011d3 1644 macinit.HashTableHigh = 0x0U;
sahilmgandhi 18:6a4db94011d3 1645 macinit.HashTableLow = 0x0U;
sahilmgandhi 18:6a4db94011d3 1646 macinit.PauseTime = 0x0U;
sahilmgandhi 18:6a4db94011d3 1647 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
sahilmgandhi 18:6a4db94011d3 1648 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
sahilmgandhi 18:6a4db94011d3 1649 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
sahilmgandhi 18:6a4db94011d3 1650 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
sahilmgandhi 18:6a4db94011d3 1651 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
sahilmgandhi 18:6a4db94011d3 1652 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
sahilmgandhi 18:6a4db94011d3 1653 macinit.VLANTagIdentifier = 0x0U;
sahilmgandhi 18:6a4db94011d3 1654
sahilmgandhi 18:6a4db94011d3 1655 /*------------------------ ETHERNET MACCR Configuration --------------------*/
sahilmgandhi 18:6a4db94011d3 1656 /* Get the ETHERNET MACCR value */
sahilmgandhi 18:6a4db94011d3 1657 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1658 /* Clear WD, PCE, PS, TE and RE bits */
sahilmgandhi 18:6a4db94011d3 1659 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
sahilmgandhi 18:6a4db94011d3 1660 /* Set the WD bit according to ETH Watchdog value */
sahilmgandhi 18:6a4db94011d3 1661 /* Set the JD: bit according to ETH Jabber value */
sahilmgandhi 18:6a4db94011d3 1662 /* Set the IFG bit according to ETH InterFrameGap value */
sahilmgandhi 18:6a4db94011d3 1663 /* Set the DCRS bit according to ETH CarrierSense value */
sahilmgandhi 18:6a4db94011d3 1664 /* Set the FES bit according to ETH Speed value */
sahilmgandhi 18:6a4db94011d3 1665 /* Set the DO bit according to ETH ReceiveOwn value */
sahilmgandhi 18:6a4db94011d3 1666 /* Set the LM bit according to ETH LoopbackMode value */
sahilmgandhi 18:6a4db94011d3 1667 /* Set the DM bit according to ETH Mode value */
sahilmgandhi 18:6a4db94011d3 1668 /* Set the IPCO bit according to ETH ChecksumOffload value */
sahilmgandhi 18:6a4db94011d3 1669 /* Set the DR bit according to ETH RetryTransmission value */
sahilmgandhi 18:6a4db94011d3 1670 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
sahilmgandhi 18:6a4db94011d3 1671 /* Set the BL bit according to ETH BackOffLimit value */
sahilmgandhi 18:6a4db94011d3 1672 /* Set the DC bit according to ETH DeferralCheck value */
sahilmgandhi 18:6a4db94011d3 1673 tmpreg1 |= (uint32_t)(macinit.Watchdog |
sahilmgandhi 18:6a4db94011d3 1674 macinit.Jabber |
sahilmgandhi 18:6a4db94011d3 1675 macinit.InterFrameGap |
sahilmgandhi 18:6a4db94011d3 1676 macinit.CarrierSense |
sahilmgandhi 18:6a4db94011d3 1677 (heth->Init).Speed |
sahilmgandhi 18:6a4db94011d3 1678 macinit.ReceiveOwn |
sahilmgandhi 18:6a4db94011d3 1679 macinit.LoopbackMode |
sahilmgandhi 18:6a4db94011d3 1680 (heth->Init).DuplexMode |
sahilmgandhi 18:6a4db94011d3 1681 macinit.ChecksumOffload |
sahilmgandhi 18:6a4db94011d3 1682 macinit.RetryTransmission |
sahilmgandhi 18:6a4db94011d3 1683 macinit.AutomaticPadCRCStrip |
sahilmgandhi 18:6a4db94011d3 1684 macinit.BackOffLimit |
sahilmgandhi 18:6a4db94011d3 1685 macinit.DeferralCheck);
sahilmgandhi 18:6a4db94011d3 1686
sahilmgandhi 18:6a4db94011d3 1687 /* Write to ETHERNET MACCR */
sahilmgandhi 18:6a4db94011d3 1688 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
sahilmgandhi 18:6a4db94011d3 1689
sahilmgandhi 18:6a4db94011d3 1690 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1691 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1692 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1693 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1694 (heth->Instance)->MACCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1695
sahilmgandhi 18:6a4db94011d3 1696 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
sahilmgandhi 18:6a4db94011d3 1697 /* Set the RA bit according to ETH ReceiveAll value */
sahilmgandhi 18:6a4db94011d3 1698 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
sahilmgandhi 18:6a4db94011d3 1699 /* Set the PCF bit according to ETH PassControlFrames value */
sahilmgandhi 18:6a4db94011d3 1700 /* Set the DBF bit according to ETH BroadcastFramesReception value */
sahilmgandhi 18:6a4db94011d3 1701 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
sahilmgandhi 18:6a4db94011d3 1702 /* Set the PR bit according to ETH PromiscuousMode value */
sahilmgandhi 18:6a4db94011d3 1703 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
sahilmgandhi 18:6a4db94011d3 1704 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
sahilmgandhi 18:6a4db94011d3 1705 /* Write to ETHERNET MACFFR */
sahilmgandhi 18:6a4db94011d3 1706 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
sahilmgandhi 18:6a4db94011d3 1707 macinit.SourceAddrFilter |
sahilmgandhi 18:6a4db94011d3 1708 macinit.PassControlFrames |
sahilmgandhi 18:6a4db94011d3 1709 macinit.BroadcastFramesReception |
sahilmgandhi 18:6a4db94011d3 1710 macinit.DestinationAddrFilter |
sahilmgandhi 18:6a4db94011d3 1711 macinit.PromiscuousMode |
sahilmgandhi 18:6a4db94011d3 1712 macinit.MulticastFramesFilter |
sahilmgandhi 18:6a4db94011d3 1713 macinit.UnicastFramesFilter);
sahilmgandhi 18:6a4db94011d3 1714
sahilmgandhi 18:6a4db94011d3 1715 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1716 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1717 tmpreg1 = (heth->Instance)->MACFFR;
sahilmgandhi 18:6a4db94011d3 1718 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1719 (heth->Instance)->MACFFR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1720
sahilmgandhi 18:6a4db94011d3 1721 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
sahilmgandhi 18:6a4db94011d3 1722 /* Write to ETHERNET MACHTHR */
sahilmgandhi 18:6a4db94011d3 1723 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
sahilmgandhi 18:6a4db94011d3 1724
sahilmgandhi 18:6a4db94011d3 1725 /* Write to ETHERNET MACHTLR */
sahilmgandhi 18:6a4db94011d3 1726 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
sahilmgandhi 18:6a4db94011d3 1727 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
sahilmgandhi 18:6a4db94011d3 1728
sahilmgandhi 18:6a4db94011d3 1729 /* Get the ETHERNET MACFCR value */
sahilmgandhi 18:6a4db94011d3 1730 tmpreg1 = (heth->Instance)->MACFCR;
sahilmgandhi 18:6a4db94011d3 1731 /* Clear xx bits */
sahilmgandhi 18:6a4db94011d3 1732 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
sahilmgandhi 18:6a4db94011d3 1733
sahilmgandhi 18:6a4db94011d3 1734 /* Set the PT bit according to ETH PauseTime value */
sahilmgandhi 18:6a4db94011d3 1735 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
sahilmgandhi 18:6a4db94011d3 1736 /* Set the PLT bit according to ETH PauseLowThreshold value */
sahilmgandhi 18:6a4db94011d3 1737 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
sahilmgandhi 18:6a4db94011d3 1738 /* Set the RFE bit according to ETH ReceiveFlowControl value */
sahilmgandhi 18:6a4db94011d3 1739 /* Set the TFE bit according to ETH TransmitFlowControl value */
sahilmgandhi 18:6a4db94011d3 1740 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
sahilmgandhi 18:6a4db94011d3 1741 macinit.ZeroQuantaPause |
sahilmgandhi 18:6a4db94011d3 1742 macinit.PauseLowThreshold |
sahilmgandhi 18:6a4db94011d3 1743 macinit.UnicastPauseFrameDetect |
sahilmgandhi 18:6a4db94011d3 1744 macinit.ReceiveFlowControl |
sahilmgandhi 18:6a4db94011d3 1745 macinit.TransmitFlowControl);
sahilmgandhi 18:6a4db94011d3 1746
sahilmgandhi 18:6a4db94011d3 1747 /* Write to ETHERNET MACFCR */
sahilmgandhi 18:6a4db94011d3 1748 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
sahilmgandhi 18:6a4db94011d3 1749
sahilmgandhi 18:6a4db94011d3 1750 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1751 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1752 tmpreg1 = (heth->Instance)->MACFCR;
sahilmgandhi 18:6a4db94011d3 1753 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1754 (heth->Instance)->MACFCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1755
sahilmgandhi 18:6a4db94011d3 1756 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
sahilmgandhi 18:6a4db94011d3 1757 /* Set the ETV bit according to ETH VLANTagComparison value */
sahilmgandhi 18:6a4db94011d3 1758 /* Set the VL bit according to ETH VLANTagIdentifier value */
sahilmgandhi 18:6a4db94011d3 1759 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
sahilmgandhi 18:6a4db94011d3 1760 macinit.VLANTagIdentifier);
sahilmgandhi 18:6a4db94011d3 1761
sahilmgandhi 18:6a4db94011d3 1762 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1763 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1764 tmpreg1 = (heth->Instance)->MACVLANTR;
sahilmgandhi 18:6a4db94011d3 1765 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1766 (heth->Instance)->MACVLANTR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1767
sahilmgandhi 18:6a4db94011d3 1768 /* Ethernet DMA default initialization ************************************/
sahilmgandhi 18:6a4db94011d3 1769 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
sahilmgandhi 18:6a4db94011d3 1770 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
sahilmgandhi 18:6a4db94011d3 1771 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
sahilmgandhi 18:6a4db94011d3 1772 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
sahilmgandhi 18:6a4db94011d3 1773 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
sahilmgandhi 18:6a4db94011d3 1774 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
sahilmgandhi 18:6a4db94011d3 1775 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
sahilmgandhi 18:6a4db94011d3 1776 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
sahilmgandhi 18:6a4db94011d3 1777 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
sahilmgandhi 18:6a4db94011d3 1778 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
sahilmgandhi 18:6a4db94011d3 1779 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
sahilmgandhi 18:6a4db94011d3 1780 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
sahilmgandhi 18:6a4db94011d3 1781 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
sahilmgandhi 18:6a4db94011d3 1782 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
sahilmgandhi 18:6a4db94011d3 1783 dmainit.DescriptorSkipLength = 0x0U;
sahilmgandhi 18:6a4db94011d3 1784 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
sahilmgandhi 18:6a4db94011d3 1785
sahilmgandhi 18:6a4db94011d3 1786 /* Get the ETHERNET DMAOMR value */
sahilmgandhi 18:6a4db94011d3 1787 tmpreg1 = (heth->Instance)->DMAOMR;
sahilmgandhi 18:6a4db94011d3 1788 /* Clear xx bits */
sahilmgandhi 18:6a4db94011d3 1789 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
sahilmgandhi 18:6a4db94011d3 1790
sahilmgandhi 18:6a4db94011d3 1791 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
sahilmgandhi 18:6a4db94011d3 1792 /* Set the RSF bit according to ETH ReceiveStoreForward value */
sahilmgandhi 18:6a4db94011d3 1793 /* Set the DFF bit according to ETH FlushReceivedFrame value */
sahilmgandhi 18:6a4db94011d3 1794 /* Set the TSF bit according to ETH TransmitStoreForward value */
sahilmgandhi 18:6a4db94011d3 1795 /* Set the TTC bit according to ETH TransmitThresholdControl value */
sahilmgandhi 18:6a4db94011d3 1796 /* Set the FEF bit according to ETH ForwardErrorFrames value */
sahilmgandhi 18:6a4db94011d3 1797 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
sahilmgandhi 18:6a4db94011d3 1798 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
sahilmgandhi 18:6a4db94011d3 1799 /* Set the OSF bit according to ETH SecondFrameOperate value */
sahilmgandhi 18:6a4db94011d3 1800 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
sahilmgandhi 18:6a4db94011d3 1801 dmainit.ReceiveStoreForward |
sahilmgandhi 18:6a4db94011d3 1802 dmainit.FlushReceivedFrame |
sahilmgandhi 18:6a4db94011d3 1803 dmainit.TransmitStoreForward |
sahilmgandhi 18:6a4db94011d3 1804 dmainit.TransmitThresholdControl |
sahilmgandhi 18:6a4db94011d3 1805 dmainit.ForwardErrorFrames |
sahilmgandhi 18:6a4db94011d3 1806 dmainit.ForwardUndersizedGoodFrames |
sahilmgandhi 18:6a4db94011d3 1807 dmainit.ReceiveThresholdControl |
sahilmgandhi 18:6a4db94011d3 1808 dmainit.SecondFrameOperate);
sahilmgandhi 18:6a4db94011d3 1809
sahilmgandhi 18:6a4db94011d3 1810 /* Write to ETHERNET DMAOMR */
sahilmgandhi 18:6a4db94011d3 1811 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
sahilmgandhi 18:6a4db94011d3 1812
sahilmgandhi 18:6a4db94011d3 1813 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1814 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1815 tmpreg1 = (heth->Instance)->DMAOMR;
sahilmgandhi 18:6a4db94011d3 1816 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1817 (heth->Instance)->DMAOMR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1818
sahilmgandhi 18:6a4db94011d3 1819 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
sahilmgandhi 18:6a4db94011d3 1820 /* Set the AAL bit according to ETH AddressAlignedBeats value */
sahilmgandhi 18:6a4db94011d3 1821 /* Set the FB bit according to ETH FixedBurst value */
sahilmgandhi 18:6a4db94011d3 1822 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
sahilmgandhi 18:6a4db94011d3 1823 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
sahilmgandhi 18:6a4db94011d3 1824 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
sahilmgandhi 18:6a4db94011d3 1825 /* Set the DSL bit according to ETH DesciptorSkipLength value */
sahilmgandhi 18:6a4db94011d3 1826 /* Set the PR and DA bits according to ETH DMAArbitration value */
sahilmgandhi 18:6a4db94011d3 1827 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
sahilmgandhi 18:6a4db94011d3 1828 dmainit.FixedBurst |
sahilmgandhi 18:6a4db94011d3 1829 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
sahilmgandhi 18:6a4db94011d3 1830 dmainit.TxDMABurstLength |
sahilmgandhi 18:6a4db94011d3 1831 dmainit.EnhancedDescriptorFormat |
sahilmgandhi 18:6a4db94011d3 1832 (dmainit.DescriptorSkipLength << 2U) |
sahilmgandhi 18:6a4db94011d3 1833 dmainit.DMAArbitration |
sahilmgandhi 18:6a4db94011d3 1834 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
sahilmgandhi 18:6a4db94011d3 1835
sahilmgandhi 18:6a4db94011d3 1836 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1837 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1838 tmpreg1 = (heth->Instance)->DMABMR;
sahilmgandhi 18:6a4db94011d3 1839 HAL_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1840 (heth->Instance)->DMABMR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1841
sahilmgandhi 18:6a4db94011d3 1842 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
sahilmgandhi 18:6a4db94011d3 1843 {
sahilmgandhi 18:6a4db94011d3 1844 /* Enable the Ethernet Rx Interrupt */
sahilmgandhi 18:6a4db94011d3 1845 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
sahilmgandhi 18:6a4db94011d3 1846 }
sahilmgandhi 18:6a4db94011d3 1847
sahilmgandhi 18:6a4db94011d3 1848 /* Initialize MAC address in ethernet MAC */
sahilmgandhi 18:6a4db94011d3 1849 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
sahilmgandhi 18:6a4db94011d3 1850 }
sahilmgandhi 18:6a4db94011d3 1851
sahilmgandhi 18:6a4db94011d3 1852 /**
sahilmgandhi 18:6a4db94011d3 1853 * @brief Configures the selected MAC address.
sahilmgandhi 18:6a4db94011d3 1854 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1855 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1856 * @param MacAddr: The MAC address to configure
sahilmgandhi 18:6a4db94011d3 1857 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 1858 * @arg ETH_MAC_Address0: MAC Address0
sahilmgandhi 18:6a4db94011d3 1859 * @arg ETH_MAC_Address1: MAC Address1
sahilmgandhi 18:6a4db94011d3 1860 * @arg ETH_MAC_Address2: MAC Address2
sahilmgandhi 18:6a4db94011d3 1861 * @arg ETH_MAC_Address3: MAC Address3
sahilmgandhi 18:6a4db94011d3 1862 * @param Addr: Pointer to MAC address buffer data (6 bytes)
sahilmgandhi 18:6a4db94011d3 1863 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1864 */
sahilmgandhi 18:6a4db94011d3 1865 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
sahilmgandhi 18:6a4db94011d3 1866 {
sahilmgandhi 18:6a4db94011d3 1867 uint32_t tmpreg1;
sahilmgandhi 18:6a4db94011d3 1868
sahilmgandhi 18:6a4db94011d3 1869 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1870 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
sahilmgandhi 18:6a4db94011d3 1871
sahilmgandhi 18:6a4db94011d3 1872 /* Calculate the selected MAC address high register */
sahilmgandhi 18:6a4db94011d3 1873 tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
sahilmgandhi 18:6a4db94011d3 1874 /* Load the selected MAC address high register */
sahilmgandhi 18:6a4db94011d3 1875 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1876 /* Calculate the selected MAC address low register */
sahilmgandhi 18:6a4db94011d3 1877 tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
sahilmgandhi 18:6a4db94011d3 1878
sahilmgandhi 18:6a4db94011d3 1879 /* Load the selected MAC address low register */
sahilmgandhi 18:6a4db94011d3 1880 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1881 }
sahilmgandhi 18:6a4db94011d3 1882
sahilmgandhi 18:6a4db94011d3 1883 /**
sahilmgandhi 18:6a4db94011d3 1884 * @brief Enables the MAC transmission.
sahilmgandhi 18:6a4db94011d3 1885 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1886 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1887 * @retval None
sahilmgandhi 18:6a4db94011d3 1888 */
sahilmgandhi 18:6a4db94011d3 1889 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1890 {
sahilmgandhi 18:6a4db94011d3 1891 __IO uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1892
sahilmgandhi 18:6a4db94011d3 1893 /* Enable the MAC transmission */
sahilmgandhi 18:6a4db94011d3 1894 (heth->Instance)->MACCR |= ETH_MACCR_TE;
sahilmgandhi 18:6a4db94011d3 1895
sahilmgandhi 18:6a4db94011d3 1896 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1897 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1898 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1899 ETH_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1900 (heth->Instance)->MACCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1901 }
sahilmgandhi 18:6a4db94011d3 1902
sahilmgandhi 18:6a4db94011d3 1903 /**
sahilmgandhi 18:6a4db94011d3 1904 * @brief Disables the MAC transmission.
sahilmgandhi 18:6a4db94011d3 1905 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1906 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1907 * @retval None
sahilmgandhi 18:6a4db94011d3 1908 */
sahilmgandhi 18:6a4db94011d3 1909 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1910 {
sahilmgandhi 18:6a4db94011d3 1911 __IO uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1912
sahilmgandhi 18:6a4db94011d3 1913 /* Disable the MAC transmission */
sahilmgandhi 18:6a4db94011d3 1914 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
sahilmgandhi 18:6a4db94011d3 1915
sahilmgandhi 18:6a4db94011d3 1916 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1917 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1918 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1919 ETH_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1920 (heth->Instance)->MACCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1921 }
sahilmgandhi 18:6a4db94011d3 1922
sahilmgandhi 18:6a4db94011d3 1923 /**
sahilmgandhi 18:6a4db94011d3 1924 * @brief Enables the MAC reception.
sahilmgandhi 18:6a4db94011d3 1925 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1926 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1927 * @retval None
sahilmgandhi 18:6a4db94011d3 1928 */
sahilmgandhi 18:6a4db94011d3 1929 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1930 {
sahilmgandhi 18:6a4db94011d3 1931 __IO uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1932
sahilmgandhi 18:6a4db94011d3 1933 /* Enable the MAC reception */
sahilmgandhi 18:6a4db94011d3 1934 (heth->Instance)->MACCR |= ETH_MACCR_RE;
sahilmgandhi 18:6a4db94011d3 1935
sahilmgandhi 18:6a4db94011d3 1936 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1937 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1938 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1939 ETH_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1940 (heth->Instance)->MACCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1941 }
sahilmgandhi 18:6a4db94011d3 1942
sahilmgandhi 18:6a4db94011d3 1943 /**
sahilmgandhi 18:6a4db94011d3 1944 * @brief Disables the MAC reception.
sahilmgandhi 18:6a4db94011d3 1945 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1946 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1947 * @retval None
sahilmgandhi 18:6a4db94011d3 1948 */
sahilmgandhi 18:6a4db94011d3 1949 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1950 {
sahilmgandhi 18:6a4db94011d3 1951 __IO uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 1952
sahilmgandhi 18:6a4db94011d3 1953 /* Disable the MAC reception */
sahilmgandhi 18:6a4db94011d3 1954 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
sahilmgandhi 18:6a4db94011d3 1955
sahilmgandhi 18:6a4db94011d3 1956 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 1957 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 1958 tmpreg1 = (heth->Instance)->MACCR;
sahilmgandhi 18:6a4db94011d3 1959 ETH_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 1960 (heth->Instance)->MACCR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 1961 }
sahilmgandhi 18:6a4db94011d3 1962
sahilmgandhi 18:6a4db94011d3 1963 /**
sahilmgandhi 18:6a4db94011d3 1964 * @brief Enables the DMA transmission.
sahilmgandhi 18:6a4db94011d3 1965 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1966 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1967 * @retval None
sahilmgandhi 18:6a4db94011d3 1968 */
sahilmgandhi 18:6a4db94011d3 1969 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1970 {
sahilmgandhi 18:6a4db94011d3 1971 /* Enable the DMA transmission */
sahilmgandhi 18:6a4db94011d3 1972 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
sahilmgandhi 18:6a4db94011d3 1973 }
sahilmgandhi 18:6a4db94011d3 1974
sahilmgandhi 18:6a4db94011d3 1975 /**
sahilmgandhi 18:6a4db94011d3 1976 * @brief Disables the DMA transmission.
sahilmgandhi 18:6a4db94011d3 1977 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1978 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1979 * @retval None
sahilmgandhi 18:6a4db94011d3 1980 */
sahilmgandhi 18:6a4db94011d3 1981 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1982 {
sahilmgandhi 18:6a4db94011d3 1983 /* Disable the DMA transmission */
sahilmgandhi 18:6a4db94011d3 1984 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
sahilmgandhi 18:6a4db94011d3 1985 }
sahilmgandhi 18:6a4db94011d3 1986
sahilmgandhi 18:6a4db94011d3 1987 /**
sahilmgandhi 18:6a4db94011d3 1988 * @brief Enables the DMA reception.
sahilmgandhi 18:6a4db94011d3 1989 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1990 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 1991 * @retval None
sahilmgandhi 18:6a4db94011d3 1992 */
sahilmgandhi 18:6a4db94011d3 1993 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 1994 {
sahilmgandhi 18:6a4db94011d3 1995 /* Enable the DMA reception */
sahilmgandhi 18:6a4db94011d3 1996 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
sahilmgandhi 18:6a4db94011d3 1997 }
sahilmgandhi 18:6a4db94011d3 1998
sahilmgandhi 18:6a4db94011d3 1999 /**
sahilmgandhi 18:6a4db94011d3 2000 * @brief Disables the DMA reception.
sahilmgandhi 18:6a4db94011d3 2001 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2002 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 2003 * @retval None
sahilmgandhi 18:6a4db94011d3 2004 */
sahilmgandhi 18:6a4db94011d3 2005 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 2006 {
sahilmgandhi 18:6a4db94011d3 2007 /* Disable the DMA reception */
sahilmgandhi 18:6a4db94011d3 2008 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
sahilmgandhi 18:6a4db94011d3 2009 }
sahilmgandhi 18:6a4db94011d3 2010
sahilmgandhi 18:6a4db94011d3 2011 /**
sahilmgandhi 18:6a4db94011d3 2012 * @brief Clears the ETHERNET transmit FIFO.
sahilmgandhi 18:6a4db94011d3 2013 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2014 * the configuration information for ETHERNET module
sahilmgandhi 18:6a4db94011d3 2015 * @retval None
sahilmgandhi 18:6a4db94011d3 2016 */
sahilmgandhi 18:6a4db94011d3 2017 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
sahilmgandhi 18:6a4db94011d3 2018 {
sahilmgandhi 18:6a4db94011d3 2019 __IO uint32_t tmpreg1 = 0U;
sahilmgandhi 18:6a4db94011d3 2020
sahilmgandhi 18:6a4db94011d3 2021 /* Set the Flush Transmit FIFO bit */
sahilmgandhi 18:6a4db94011d3 2022 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
sahilmgandhi 18:6a4db94011d3 2023
sahilmgandhi 18:6a4db94011d3 2024 /* Wait until the write operation will be taken into account:
sahilmgandhi 18:6a4db94011d3 2025 at least four TX_CLK/RX_CLK clock cycles */
sahilmgandhi 18:6a4db94011d3 2026 tmpreg1 = (heth->Instance)->DMAOMR;
sahilmgandhi 18:6a4db94011d3 2027 ETH_Delay(ETH_REG_WRITE_DELAY);
sahilmgandhi 18:6a4db94011d3 2028 (heth->Instance)->DMAOMR = tmpreg1;
sahilmgandhi 18:6a4db94011d3 2029 }
sahilmgandhi 18:6a4db94011d3 2030
sahilmgandhi 18:6a4db94011d3 2031 /**
sahilmgandhi 18:6a4db94011d3 2032 * @brief This function provides delay (in milliseconds) based on CPU cycles method.
sahilmgandhi 18:6a4db94011d3 2033 * @param mdelay: specifies the delay time length, in milliseconds.
sahilmgandhi 18:6a4db94011d3 2034 * @retval None
sahilmgandhi 18:6a4db94011d3 2035 */
sahilmgandhi 18:6a4db94011d3 2036 static void ETH_Delay(uint32_t mdelay)
sahilmgandhi 18:6a4db94011d3 2037 {
sahilmgandhi 18:6a4db94011d3 2038 __IO uint32_t Delay = mdelay * (SystemCoreClock / 8 / 1000);
sahilmgandhi 18:6a4db94011d3 2039 do
sahilmgandhi 18:6a4db94011d3 2040 {
sahilmgandhi 18:6a4db94011d3 2041 __NOP();
sahilmgandhi 18:6a4db94011d3 2042 }
sahilmgandhi 18:6a4db94011d3 2043 while (Delay --);
sahilmgandhi 18:6a4db94011d3 2044 }
sahilmgandhi 18:6a4db94011d3 2045
sahilmgandhi 18:6a4db94011d3 2046 /**
sahilmgandhi 18:6a4db94011d3 2047 * @}
sahilmgandhi 18:6a4db94011d3 2048 */
sahilmgandhi 18:6a4db94011d3 2049
sahilmgandhi 18:6a4db94011d3 2050 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
sahilmgandhi 18:6a4db94011d3 2051 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
sahilmgandhi 18:6a4db94011d3 2052 #endif /* HAL_ETH_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 2053 /**
sahilmgandhi 18:6a4db94011d3 2054 * @}
sahilmgandhi 18:6a4db94011d3 2055 */
sahilmgandhi 18:6a4db94011d3 2056
sahilmgandhi 18:6a4db94011d3 2057 /**
sahilmgandhi 18:6a4db94011d3 2058 * @}
sahilmgandhi 18:6a4db94011d3 2059 */
sahilmgandhi 18:6a4db94011d3 2060
sahilmgandhi 18:6a4db94011d3 2061 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/