MouseCode - Mouse code for the MacroRat

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Mouse code for the MacroRat

Dependencies: ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:: sahilmgandhi
Date:: Sat Jun 03 00:22:44 2017 +0000
Revision:: 46:b156ef445742
Parent:: 18:6a4db94011d3

Final code for internal battlebot competition.

Who changed what in which revision?

User	Revision	Line number	New contents of line
sahilmgandhi	18:6a4db94011d3	1	/**
sahilmgandhi	18:6a4db94011d3	2	******************************************************************************
sahilmgandhi	18:6a4db94011d3	3	* @file stm32f4xx_hal_dsi.h
sahilmgandhi	18:6a4db94011d3	4	* @author MCD Application Team
sahilmgandhi	18:6a4db94011d3	5	* @version V1.5.0
sahilmgandhi	18:6a4db94011d3	6	* @date 06-May-2016
sahilmgandhi	18:6a4db94011d3	7	* @brief Header file of DSI HAL module.
sahilmgandhi	18:6a4db94011d3	8	******************************************************************************
sahilmgandhi	18:6a4db94011d3	9	* @attention
sahilmgandhi	18:6a4db94011d3	10	*
sahilmgandhi	18:6a4db94011d3	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi	18:6a4db94011d3	12	*
sahilmgandhi	18:6a4db94011d3	13	* Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi	18:6a4db94011d3	14	* are permitted provided that the following conditions are met:
sahilmgandhi	18:6a4db94011d3	15	* 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi	18:6a4db94011d3	16	* this list of conditions and the following disclaimer.
sahilmgandhi	18:6a4db94011d3	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi	18:6a4db94011d3	18	* this list of conditions and the following disclaimer in the documentation
sahilmgandhi	18:6a4db94011d3	19	* and/or other materials provided with the distribution.
sahilmgandhi	18:6a4db94011d3	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi	18:6a4db94011d3	21	* may be used to endorse or promote products derived from this software
sahilmgandhi	18:6a4db94011d3	22	* without specific prior written permission.
sahilmgandhi	18:6a4db94011d3	23	*
sahilmgandhi	18:6a4db94011d3	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi	18:6a4db94011d3	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi	18:6a4db94011d3	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi	18:6a4db94011d3	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi	18:6a4db94011d3	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi	18:6a4db94011d3	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi	18:6a4db94011d3	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi	18:6a4db94011d3	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi	18:6a4db94011d3	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi	18:6a4db94011d3	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi	18:6a4db94011d3	34	*
sahilmgandhi	18:6a4db94011d3	35	******************************************************************************
sahilmgandhi	18:6a4db94011d3	36	*/
sahilmgandhi	18:6a4db94011d3	37
sahilmgandhi	18:6a4db94011d3	38	/* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi	18:6a4db94011d3	39	#ifndef __STM32F4xx_HAL_DSI_H
sahilmgandhi	18:6a4db94011d3	40	#define __STM32F4xx_HAL_DSI_H
sahilmgandhi	18:6a4db94011d3	41
sahilmgandhi	18:6a4db94011d3	42	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	43	extern "C" {
sahilmgandhi	18:6a4db94011d3	44	#endif
sahilmgandhi	18:6a4db94011d3	45
sahilmgandhi	18:6a4db94011d3	46	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
sahilmgandhi	18:6a4db94011d3	47	/* Includes ------------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	48	#include "stm32f4xx_hal_def.h"
sahilmgandhi	18:6a4db94011d3	49
sahilmgandhi	18:6a4db94011d3	50	/** @addtogroup STM32F4xx_HAL_Driver
sahilmgandhi	18:6a4db94011d3	51	* @{
sahilmgandhi	18:6a4db94011d3	52	*/
sahilmgandhi	18:6a4db94011d3	53
sahilmgandhi	18:6a4db94011d3	54	/** @defgroup DSI DSI
sahilmgandhi	18:6a4db94011d3	55	* @brief DSI HAL module driver
sahilmgandhi	18:6a4db94011d3	56	* @{
sahilmgandhi	18:6a4db94011d3	57	*/
sahilmgandhi	18:6a4db94011d3	58
sahilmgandhi	18:6a4db94011d3	59	/* Exported types ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	60	/**
sahilmgandhi	18:6a4db94011d3	61	* @brief DSI Init Structure definition
sahilmgandhi	18:6a4db94011d3	62	*/
sahilmgandhi	18:6a4db94011d3	63	typedef struct
sahilmgandhi	18:6a4db94011d3	64	{
sahilmgandhi	18:6a4db94011d3	65	uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
sahilmgandhi	18:6a4db94011d3	66	This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
sahilmgandhi	18:6a4db94011d3	67
sahilmgandhi	18:6a4db94011d3	68	uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
sahilmgandhi	18:6a4db94011d3	69	The values 0 and 1 stop the TX_ESC clock generation */
sahilmgandhi	18:6a4db94011d3	70
sahilmgandhi	18:6a4db94011d3	71	uint32_t NumberOfLanes; /*!< Number of lanes
sahilmgandhi	18:6a4db94011d3	72	This parameter can be any value of @ref DSI_Number_Of_Lanes */
sahilmgandhi	18:6a4db94011d3	73
sahilmgandhi	18:6a4db94011d3	74	}DSI_InitTypeDef;
sahilmgandhi	18:6a4db94011d3	75
sahilmgandhi	18:6a4db94011d3	76	/**
sahilmgandhi	18:6a4db94011d3	77	* @brief DSI PLL Clock structure definition
sahilmgandhi	18:6a4db94011d3	78	*/
sahilmgandhi	18:6a4db94011d3	79	typedef struct
sahilmgandhi	18:6a4db94011d3	80	{
sahilmgandhi	18:6a4db94011d3	81	uint32_t PLLNDIV; /*!< PLL Loop Division Factor
sahilmgandhi	18:6a4db94011d3	82	This parameter must be a value between 10 and 125 */
sahilmgandhi	18:6a4db94011d3	83
sahilmgandhi	18:6a4db94011d3	84	uint32_t PLLIDF; /*!< PLL Input Division Factor
sahilmgandhi	18:6a4db94011d3	85	This parameter can be any value of @ref DSI_PLL_IDF */
sahilmgandhi	18:6a4db94011d3	86
sahilmgandhi	18:6a4db94011d3	87	uint32_t PLLODF; /*!< PLL Output Division Factor
sahilmgandhi	18:6a4db94011d3	88	This parameter can be any value of @ref DSI_PLL_ODF */
sahilmgandhi	18:6a4db94011d3	89
sahilmgandhi	18:6a4db94011d3	90	}DSI_PLLInitTypeDef;
sahilmgandhi	18:6a4db94011d3	91
sahilmgandhi	18:6a4db94011d3	92	/**
sahilmgandhi	18:6a4db94011d3	93	* @brief DSI Video mode configuration
sahilmgandhi	18:6a4db94011d3	94	*/
sahilmgandhi	18:6a4db94011d3	95	typedef struct
sahilmgandhi	18:6a4db94011d3	96	{
sahilmgandhi	18:6a4db94011d3	97	uint32_t VirtualChannelID; /!< Virtual channel ID /
sahilmgandhi	18:6a4db94011d3	98
sahilmgandhi	18:6a4db94011d3	99	uint32_t ColorCoding; /*!< Color coding for LTDC interface
sahilmgandhi	18:6a4db94011d3	100	This parameter can be any value of @ref DSI_Color_Coding */
sahilmgandhi	18:6a4db94011d3	101
sahilmgandhi	18:6a4db94011d3	102	uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
sahilmgandhi	18:6a4db94011d3	103	18-bit configuration).
sahilmgandhi	18:6a4db94011d3	104	This parameter can be any value of @ref DSI_LooselyPacked */
sahilmgandhi	18:6a4db94011d3	105
sahilmgandhi	18:6a4db94011d3	106	uint32_t Mode; /*!< Video mode type
sahilmgandhi	18:6a4db94011d3	107	This parameter can be any value of @ref DSI_Video_Mode_Type */
sahilmgandhi	18:6a4db94011d3	108
sahilmgandhi	18:6a4db94011d3	109	uint32_t PacketSize; /!< Video packet size /
sahilmgandhi	18:6a4db94011d3	110
sahilmgandhi	18:6a4db94011d3	111	uint32_t NumberOfChunks; /!< Number of chunks /
sahilmgandhi	18:6a4db94011d3	112
sahilmgandhi	18:6a4db94011d3	113	uint32_t NullPacketSize; /!< Null packet size /
sahilmgandhi	18:6a4db94011d3	114
sahilmgandhi	18:6a4db94011d3	115	uint32_t HSPolarity; /*!< HSYNC pin polarity
sahilmgandhi	18:6a4db94011d3	116	This parameter can be any value of @ref DSI_HSYNC_Polarity */
sahilmgandhi	18:6a4db94011d3	117
sahilmgandhi	18:6a4db94011d3	118	uint32_t VSPolarity; /*!< VSYNC pin polarity
sahilmgandhi	18:6a4db94011d3	119	This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
sahilmgandhi	18:6a4db94011d3	120
sahilmgandhi	18:6a4db94011d3	121	uint32_t DEPolarity; /*!< Data Enable pin polarity
sahilmgandhi	18:6a4db94011d3	122	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
sahilmgandhi	18:6a4db94011d3	123
sahilmgandhi	18:6a4db94011d3	124	uint32_t HorizontalSyncActive; /!< Horizontal synchronism active duration (in lane byte clock cycles) /
sahilmgandhi	18:6a4db94011d3	125
sahilmgandhi	18:6a4db94011d3	126	uint32_t HorizontalBackPorch; /!< Horizontal back-porch duration (in lane byte clock cycles) /
sahilmgandhi	18:6a4db94011d3	127
sahilmgandhi	18:6a4db94011d3	128	uint32_t HorizontalLine; /!< Horizontal line duration (in lane byte clock cycles) /
sahilmgandhi	18:6a4db94011d3	129
sahilmgandhi	18:6a4db94011d3	130	uint32_t VerticalSyncActive; /!< Vertical synchronism active duration /
sahilmgandhi	18:6a4db94011d3	131
sahilmgandhi	18:6a4db94011d3	132	uint32_t VerticalBackPorch; /!< Vertical back-porch duration /
sahilmgandhi	18:6a4db94011d3	133
sahilmgandhi	18:6a4db94011d3	134	uint32_t VerticalFrontPorch; /!< Vertical front-porch duration /
sahilmgandhi	18:6a4db94011d3	135
sahilmgandhi	18:6a4db94011d3	136	uint32_t VerticalActive; /!< Vertical active duration /
sahilmgandhi	18:6a4db94011d3	137
sahilmgandhi	18:6a4db94011d3	138	uint32_t LPCommandEnable; /*!< Low-power command enable
sahilmgandhi	18:6a4db94011d3	139	This parameter can be any value of @ref DSI_LP_Command */
sahilmgandhi	18:6a4db94011d3	140
sahilmgandhi	18:6a4db94011d3	141	uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
sahilmgandhi	18:6a4db94011d3	142	can fit in a line during VSA, VBP and VFP regions */
sahilmgandhi	18:6a4db94011d3	143
sahilmgandhi	18:6a4db94011d3	144	uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
sahilmgandhi	18:6a4db94011d3	145	can fit in a line during VACT region */
sahilmgandhi	18:6a4db94011d3	146
sahilmgandhi	18:6a4db94011d3	147	uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
sahilmgandhi	18:6a4db94011d3	148	This parameter can be any value of @ref DSI_LP_HFP */
sahilmgandhi	18:6a4db94011d3	149
sahilmgandhi	18:6a4db94011d3	150	uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
sahilmgandhi	18:6a4db94011d3	151	This parameter can be any value of @ref DSI_LP_HBP */
sahilmgandhi	18:6a4db94011d3	152
sahilmgandhi	18:6a4db94011d3	153	uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
sahilmgandhi	18:6a4db94011d3	154	This parameter can be any value of @ref DSI_LP_VACT */
sahilmgandhi	18:6a4db94011d3	155
sahilmgandhi	18:6a4db94011d3	156	uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
sahilmgandhi	18:6a4db94011d3	157	This parameter can be any value of @ref DSI_LP_VFP */
sahilmgandhi	18:6a4db94011d3	158
sahilmgandhi	18:6a4db94011d3	159	uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
sahilmgandhi	18:6a4db94011d3	160	This parameter can be any value of @ref DSI_LP_VBP */
sahilmgandhi	18:6a4db94011d3	161
sahilmgandhi	18:6a4db94011d3	162	uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
sahilmgandhi	18:6a4db94011d3	163	This parameter can be any value of @ref DSI_LP_VSYNC */
sahilmgandhi	18:6a4db94011d3	164
sahilmgandhi	18:6a4db94011d3	165	uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
sahilmgandhi	18:6a4db94011d3	166	This parameter can be any value of @ref DSI_FBTA_acknowledge */
sahilmgandhi	18:6a4db94011d3	167
sahilmgandhi	18:6a4db94011d3	168	}DSI_VidCfgTypeDef;
sahilmgandhi	18:6a4db94011d3	169
sahilmgandhi	18:6a4db94011d3	170	/**
sahilmgandhi	18:6a4db94011d3	171	* @brief DSI Adapted command mode configuration
sahilmgandhi	18:6a4db94011d3	172	*/
sahilmgandhi	18:6a4db94011d3	173	typedef struct
sahilmgandhi	18:6a4db94011d3	174	{
sahilmgandhi	18:6a4db94011d3	175	uint32_t VirtualChannelID; /!< Virtual channel ID /
sahilmgandhi	18:6a4db94011d3	176
sahilmgandhi	18:6a4db94011d3	177	uint32_t ColorCoding; /*!< Color coding for LTDC interface
sahilmgandhi	18:6a4db94011d3	178	This parameter can be any value of @ref DSI_Color_Coding */
sahilmgandhi	18:6a4db94011d3	179
sahilmgandhi	18:6a4db94011d3	180	uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
sahilmgandhi	18:6a4db94011d3	181	pixels. This parameter can be any value between 0x00 and 0xFFFFU */
sahilmgandhi	18:6a4db94011d3	182
sahilmgandhi	18:6a4db94011d3	183	uint32_t TearingEffectSource; /*!< Tearing effect source
sahilmgandhi	18:6a4db94011d3	184	This parameter can be any value of @ref DSI_TearingEffectSource */
sahilmgandhi	18:6a4db94011d3	185
sahilmgandhi	18:6a4db94011d3	186	uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
sahilmgandhi	18:6a4db94011d3	187	This parameter can be any value of @ref DSI_TearingEffectPolarity */
sahilmgandhi	18:6a4db94011d3	188
sahilmgandhi	18:6a4db94011d3	189	uint32_t HSPolarity; /*!< HSYNC pin polarity
sahilmgandhi	18:6a4db94011d3	190	This parameter can be any value of @ref DSI_HSYNC_Polarity */
sahilmgandhi	18:6a4db94011d3	191
sahilmgandhi	18:6a4db94011d3	192	uint32_t VSPolarity; /*!< VSYNC pin polarity
sahilmgandhi	18:6a4db94011d3	193	This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
sahilmgandhi	18:6a4db94011d3	194
sahilmgandhi	18:6a4db94011d3	195	uint32_t DEPolarity; /*!< Data Enable pin polarity
sahilmgandhi	18:6a4db94011d3	196	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
sahilmgandhi	18:6a4db94011d3	197
sahilmgandhi	18:6a4db94011d3	198	uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
sahilmgandhi	18:6a4db94011d3	199	This parameter can be any value of @ref DSI_Vsync_Polarity */
sahilmgandhi	18:6a4db94011d3	200
sahilmgandhi	18:6a4db94011d3	201	uint32_t AutomaticRefresh; /*!< Automatic refresh mode
sahilmgandhi	18:6a4db94011d3	202	This parameter can be any value of @ref DSI_AutomaticRefresh */
sahilmgandhi	18:6a4db94011d3	203
sahilmgandhi	18:6a4db94011d3	204	uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
sahilmgandhi	18:6a4db94011d3	205	This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
sahilmgandhi	18:6a4db94011d3	206
sahilmgandhi	18:6a4db94011d3	207	}DSI_CmdCfgTypeDef;
sahilmgandhi	18:6a4db94011d3	208
sahilmgandhi	18:6a4db94011d3	209	/**
sahilmgandhi	18:6a4db94011d3	210	* @brief DSI command transmission mode configuration
sahilmgandhi	18:6a4db94011d3	211	*/
sahilmgandhi	18:6a4db94011d3	212	typedef struct
sahilmgandhi	18:6a4db94011d3	213	{
sahilmgandhi	18:6a4db94011d3	214	uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
sahilmgandhi	18:6a4db94011d3	215	This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
sahilmgandhi	18:6a4db94011d3	216
sahilmgandhi	18:6a4db94011d3	217	uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
sahilmgandhi	18:6a4db94011d3	218	This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
sahilmgandhi	18:6a4db94011d3	219
sahilmgandhi	18:6a4db94011d3	220	uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
sahilmgandhi	18:6a4db94011d3	221	This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
sahilmgandhi	18:6a4db94011d3	222
sahilmgandhi	18:6a4db94011d3	223	uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
sahilmgandhi	18:6a4db94011d3	224	This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
sahilmgandhi	18:6a4db94011d3	225
sahilmgandhi	18:6a4db94011d3	226	uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
sahilmgandhi	18:6a4db94011d3	227	This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
sahilmgandhi	18:6a4db94011d3	228
sahilmgandhi	18:6a4db94011d3	229	uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
sahilmgandhi	18:6a4db94011d3	230	This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
sahilmgandhi	18:6a4db94011d3	231
sahilmgandhi	18:6a4db94011d3	232	uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
sahilmgandhi	18:6a4db94011d3	233	This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
sahilmgandhi	18:6a4db94011d3	234
sahilmgandhi	18:6a4db94011d3	235	uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
sahilmgandhi	18:6a4db94011d3	236	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
sahilmgandhi	18:6a4db94011d3	237
sahilmgandhi	18:6a4db94011d3	238	uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
sahilmgandhi	18:6a4db94011d3	239	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
sahilmgandhi	18:6a4db94011d3	240
sahilmgandhi	18:6a4db94011d3	241	uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
sahilmgandhi	18:6a4db94011d3	242	This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
sahilmgandhi	18:6a4db94011d3	243
sahilmgandhi	18:6a4db94011d3	244	uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
sahilmgandhi	18:6a4db94011d3	245	This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
sahilmgandhi	18:6a4db94011d3	246
sahilmgandhi	18:6a4db94011d3	247	uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
sahilmgandhi	18:6a4db94011d3	248	This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
sahilmgandhi	18:6a4db94011d3	249
sahilmgandhi	18:6a4db94011d3	250	uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
sahilmgandhi	18:6a4db94011d3	251	This parameter can be any value of @ref DSI_AcknowledgeRequest */
sahilmgandhi	18:6a4db94011d3	252
sahilmgandhi	18:6a4db94011d3	253	}DSI_LPCmdTypeDef;
sahilmgandhi	18:6a4db94011d3	254
sahilmgandhi	18:6a4db94011d3	255	/**
sahilmgandhi	18:6a4db94011d3	256	* @brief DSI PHY Timings definition
sahilmgandhi	18:6a4db94011d3	257	*/
sahilmgandhi	18:6a4db94011d3	258	typedef struct
sahilmgandhi	18:6a4db94011d3	259	{
sahilmgandhi	18:6a4db94011d3	260	uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
sahilmgandhi	18:6a4db94011d3	261	to low-power transmission */
sahilmgandhi	18:6a4db94011d3	262
sahilmgandhi	18:6a4db94011d3	263	uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
sahilmgandhi	18:6a4db94011d3	264	to high-speed transmission */
sahilmgandhi	18:6a4db94011d3	265
sahilmgandhi	18:6a4db94011d3	266	uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
sahilmgandhi	18:6a4db94011d3	267	to low-power transmission */
sahilmgandhi	18:6a4db94011d3	268
sahilmgandhi	18:6a4db94011d3	269	uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
sahilmgandhi	18:6a4db94011d3	270	to high-speed transmission */
sahilmgandhi	18:6a4db94011d3	271
sahilmgandhi	18:6a4db94011d3	272	uint32_t DataLaneMaxReadTime; /!< The maximum time required to perform a read command /
sahilmgandhi	18:6a4db94011d3	273
sahilmgandhi	18:6a4db94011d3	274	uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
sahilmgandhi	18:6a4db94011d3	275	Stop state */
sahilmgandhi	18:6a4db94011d3	276
sahilmgandhi	18:6a4db94011d3	277	}DSI_PHY_TimerTypeDef;
sahilmgandhi	18:6a4db94011d3	278
sahilmgandhi	18:6a4db94011d3	279	/**
sahilmgandhi	18:6a4db94011d3	280	* @brief DSI HOST Timeouts definition
sahilmgandhi	18:6a4db94011d3	281	*/
sahilmgandhi	18:6a4db94011d3	282	typedef struct
sahilmgandhi	18:6a4db94011d3	283	{
sahilmgandhi	18:6a4db94011d3	284	uint32_t TimeoutCkdiv; /!< Time-out clock division /
sahilmgandhi	18:6a4db94011d3	285
sahilmgandhi	18:6a4db94011d3	286	uint32_t HighSpeedTransmissionTimeout; /!< High-speed transmission time-out /
sahilmgandhi	18:6a4db94011d3	287
sahilmgandhi	18:6a4db94011d3	288	uint32_t LowPowerReceptionTimeout; /!< Low-power reception time-out /
sahilmgandhi	18:6a4db94011d3	289
sahilmgandhi	18:6a4db94011d3	290	uint32_t HighSpeedReadTimeout; /!< High-speed read time-out /
sahilmgandhi	18:6a4db94011d3	291
sahilmgandhi	18:6a4db94011d3	292	uint32_t LowPowerReadTimeout; /!< Low-power read time-out /
sahilmgandhi	18:6a4db94011d3	293
sahilmgandhi	18:6a4db94011d3	294	uint32_t HighSpeedWriteTimeout; /!< High-speed write time-out /
sahilmgandhi	18:6a4db94011d3	295
sahilmgandhi	18:6a4db94011d3	296	uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
sahilmgandhi	18:6a4db94011d3	297	This parameter can be any value of @ref DSI_HS_PrespMode */
sahilmgandhi	18:6a4db94011d3	298
sahilmgandhi	18:6a4db94011d3	299	uint32_t LowPowerWriteTimeout; /!< Low-speed write time-out /
sahilmgandhi	18:6a4db94011d3	300
sahilmgandhi	18:6a4db94011d3	301	uint32_t BTATimeout; /!< BTA time-out /
sahilmgandhi	18:6a4db94011d3	302
sahilmgandhi	18:6a4db94011d3	303	}DSI_HOST_TimeoutTypeDef;
sahilmgandhi	18:6a4db94011d3	304
sahilmgandhi	18:6a4db94011d3	305	/**
sahilmgandhi	18:6a4db94011d3	306	* @brief DSI States Structure definition
sahilmgandhi	18:6a4db94011d3	307	*/
sahilmgandhi	18:6a4db94011d3	308	typedef enum
sahilmgandhi	18:6a4db94011d3	309	{
sahilmgandhi	18:6a4db94011d3	310	HAL_DSI_STATE_RESET = 0x00U,
sahilmgandhi	18:6a4db94011d3	311	HAL_DSI_STATE_READY = 0x01U,
sahilmgandhi	18:6a4db94011d3	312	HAL_DSI_STATE_ERROR = 0x02U,
sahilmgandhi	18:6a4db94011d3	313	HAL_DSI_STATE_BUSY = 0x03U,
sahilmgandhi	18:6a4db94011d3	314	HAL_DSI_STATE_TIMEOUT = 0x04U
sahilmgandhi	18:6a4db94011d3	315	}HAL_DSI_StateTypeDef;
sahilmgandhi	18:6a4db94011d3	316
sahilmgandhi	18:6a4db94011d3	317	/**
sahilmgandhi	18:6a4db94011d3	318	* @brief DSI Handle Structure definition
sahilmgandhi	18:6a4db94011d3	319	*/
sahilmgandhi	18:6a4db94011d3	320	typedef struct
sahilmgandhi	18:6a4db94011d3	321	{
sahilmgandhi	18:6a4db94011d3	322	DSI_TypeDef Instance; /!< Register base address */
sahilmgandhi	18:6a4db94011d3	323	DSI_InitTypeDef Init; /!< DSI required parameters /
sahilmgandhi	18:6a4db94011d3	324	HAL_LockTypeDef Lock; /!< DSI peripheral status /
sahilmgandhi	18:6a4db94011d3	325	__IO HAL_DSI_StateTypeDef State; /!< DSI communication state /
sahilmgandhi	18:6a4db94011d3	326	__IO uint32_t ErrorCode; /!< DSI Error code /
sahilmgandhi	18:6a4db94011d3	327	uint32_t ErrorMsk; /!< DSI Error monitoring mask /
sahilmgandhi	18:6a4db94011d3	328	}DSI_HandleTypeDef;
sahilmgandhi	18:6a4db94011d3	329
sahilmgandhi	18:6a4db94011d3	330	/* Exported constants --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	331	/** @defgroup DSI_DCS_Command DSI DCS Command
sahilmgandhi	18:6a4db94011d3	332	* @{
sahilmgandhi	18:6a4db94011d3	333	*/
sahilmgandhi	18:6a4db94011d3	334	#define DSI_ENTER_IDLE_MODE 0x39U
sahilmgandhi	18:6a4db94011d3	335	#define DSI_ENTER_INVERT_MODE 0x21U
sahilmgandhi	18:6a4db94011d3	336	#define DSI_ENTER_NORMAL_MODE 0x13U
sahilmgandhi	18:6a4db94011d3	337	#define DSI_ENTER_PARTIAL_MODE 0x12U
sahilmgandhi	18:6a4db94011d3	338	#define DSI_ENTER_SLEEP_MODE 0x10U
sahilmgandhi	18:6a4db94011d3	339	#define DSI_EXIT_IDLE_MODE 0x38U
sahilmgandhi	18:6a4db94011d3	340	#define DSI_EXIT_INVERT_MODE 0x20U
sahilmgandhi	18:6a4db94011d3	341	#define DSI_EXIT_SLEEP_MODE 0x11U
sahilmgandhi	18:6a4db94011d3	342	#define DSI_GET_3D_CONTROL 0x3FU
sahilmgandhi	18:6a4db94011d3	343	#define DSI_GET_ADDRESS_MODE 0x0BU
sahilmgandhi	18:6a4db94011d3	344	#define DSI_GET_BLUE_CHANNEL 0x08U
sahilmgandhi	18:6a4db94011d3	345	#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
sahilmgandhi	18:6a4db94011d3	346	#define DSI_GET_DISPLAY_MODE 0x0DU
sahilmgandhi	18:6a4db94011d3	347	#define DSI_GET_GREEN_CHANNEL 0x07U
sahilmgandhi	18:6a4db94011d3	348	#define DSI_GET_PIXEL_FORMAT 0x0CU
sahilmgandhi	18:6a4db94011d3	349	#define DSI_GET_POWER_MODE 0x0AU
sahilmgandhi	18:6a4db94011d3	350	#define DSI_GET_RED_CHANNEL 0x06U
sahilmgandhi	18:6a4db94011d3	351	#define DSI_GET_SCANLINE 0x45U
sahilmgandhi	18:6a4db94011d3	352	#define DSI_GET_SIGNAL_MODE 0x0EU
sahilmgandhi	18:6a4db94011d3	353	#define DSI_NOP 0x00U
sahilmgandhi	18:6a4db94011d3	354	#define DSI_READ_DDB_CONTINUE 0xA8U
sahilmgandhi	18:6a4db94011d3	355	#define DSI_READ_DDB_START 0xA1U
sahilmgandhi	18:6a4db94011d3	356	#define DSI_READ_MEMORY_CONTINUE 0x3EU
sahilmgandhi	18:6a4db94011d3	357	#define DSI_READ_MEMORY_START 0x2EU
sahilmgandhi	18:6a4db94011d3	358	#define DSI_SET_3D_CONTROL 0x3DU
sahilmgandhi	18:6a4db94011d3	359	#define DSI_SET_ADDRESS_MODE 0x36U
sahilmgandhi	18:6a4db94011d3	360	#define DSI_SET_COLUMN_ADDRESS 0x2AU
sahilmgandhi	18:6a4db94011d3	361	#define DSI_SET_DISPLAY_OFF 0x28U
sahilmgandhi	18:6a4db94011d3	362	#define DSI_SET_DISPLAY_ON 0x29U
sahilmgandhi	18:6a4db94011d3	363	#define DSI_SET_GAMMA_CURVE 0x26U
sahilmgandhi	18:6a4db94011d3	364	#define DSI_SET_PAGE_ADDRESS 0x2BU
sahilmgandhi	18:6a4db94011d3	365	#define DSI_SET_PARTIAL_COLUMNS 0x31U
sahilmgandhi	18:6a4db94011d3	366	#define DSI_SET_PARTIAL_ROWS 0x30U
sahilmgandhi	18:6a4db94011d3	367	#define DSI_SET_PIXEL_FORMAT 0x3AU
sahilmgandhi	18:6a4db94011d3	368	#define DSI_SET_SCROLL_AREA 0x33U
sahilmgandhi	18:6a4db94011d3	369	#define DSI_SET_SCROLL_START 0x37U
sahilmgandhi	18:6a4db94011d3	370	#define DSI_SET_TEAR_OFF 0x34U
sahilmgandhi	18:6a4db94011d3	371	#define DSI_SET_TEAR_ON 0x35U
sahilmgandhi	18:6a4db94011d3	372	#define DSI_SET_TEAR_SCANLINE 0x44U
sahilmgandhi	18:6a4db94011d3	373	#define DSI_SET_VSYNC_TIMING 0x40U
sahilmgandhi	18:6a4db94011d3	374	#define DSI_SOFT_RESET 0x01U
sahilmgandhi	18:6a4db94011d3	375	#define DSI_WRITE_LUT 0x2DU
sahilmgandhi	18:6a4db94011d3	376	#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
sahilmgandhi	18:6a4db94011d3	377	#define DSI_WRITE_MEMORY_START 0x2CU
sahilmgandhi	18:6a4db94011d3	378	/**
sahilmgandhi	18:6a4db94011d3	379	* @}
sahilmgandhi	18:6a4db94011d3	380	*/
sahilmgandhi	18:6a4db94011d3	381
sahilmgandhi	18:6a4db94011d3	382	/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
sahilmgandhi	18:6a4db94011d3	383	* @{
sahilmgandhi	18:6a4db94011d3	384	*/
sahilmgandhi	18:6a4db94011d3	385	#define DSI_VID_MODE_NB_PULSES 0U
sahilmgandhi	18:6a4db94011d3	386	#define DSI_VID_MODE_NB_EVENTS 1U
sahilmgandhi	18:6a4db94011d3	387	#define DSI_VID_MODE_BURST 2U
sahilmgandhi	18:6a4db94011d3	388	/**
sahilmgandhi	18:6a4db94011d3	389	* @}
sahilmgandhi	18:6a4db94011d3	390	*/
sahilmgandhi	18:6a4db94011d3	391
sahilmgandhi	18:6a4db94011d3	392	/** @defgroup DSI_Color_Mode DSI Color Mode
sahilmgandhi	18:6a4db94011d3	393	* @{
sahilmgandhi	18:6a4db94011d3	394	*/
sahilmgandhi	18:6a4db94011d3	395	#define DSI_COLOR_MODE_FULL ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	396	#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
sahilmgandhi	18:6a4db94011d3	397	/**
sahilmgandhi	18:6a4db94011d3	398	* @}
sahilmgandhi	18:6a4db94011d3	399	*/
sahilmgandhi	18:6a4db94011d3	400
sahilmgandhi	18:6a4db94011d3	401	/** @defgroup DSI_ShutDown DSI ShutDown
sahilmgandhi	18:6a4db94011d3	402	* @{
sahilmgandhi	18:6a4db94011d3	403	*/
sahilmgandhi	18:6a4db94011d3	404	#define DSI_DISPLAY_ON ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	405	#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
sahilmgandhi	18:6a4db94011d3	406	/**
sahilmgandhi	18:6a4db94011d3	407	* @}
sahilmgandhi	18:6a4db94011d3	408	*/
sahilmgandhi	18:6a4db94011d3	409
sahilmgandhi	18:6a4db94011d3	410	/** @defgroup DSI_LP_Command DSI LP Command
sahilmgandhi	18:6a4db94011d3	411	* @{
sahilmgandhi	18:6a4db94011d3	412	*/
sahilmgandhi	18:6a4db94011d3	413	#define DSI_LP_COMMAND_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	414	#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
sahilmgandhi	18:6a4db94011d3	415	/**
sahilmgandhi	18:6a4db94011d3	416	* @}
sahilmgandhi	18:6a4db94011d3	417	*/
sahilmgandhi	18:6a4db94011d3	418
sahilmgandhi	18:6a4db94011d3	419	/** @defgroup DSI_LP_HFP DSI LP HFP
sahilmgandhi	18:6a4db94011d3	420	* @{
sahilmgandhi	18:6a4db94011d3	421	*/
sahilmgandhi	18:6a4db94011d3	422	#define DSI_LP_HFP_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	423	#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
sahilmgandhi	18:6a4db94011d3	424	/**
sahilmgandhi	18:6a4db94011d3	425	* @}
sahilmgandhi	18:6a4db94011d3	426	*/
sahilmgandhi	18:6a4db94011d3	427
sahilmgandhi	18:6a4db94011d3	428	/** @defgroup DSI_LP_HBP DSI LP HBP
sahilmgandhi	18:6a4db94011d3	429	* @{
sahilmgandhi	18:6a4db94011d3	430	*/
sahilmgandhi	18:6a4db94011d3	431	#define DSI_LP_HBP_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	432	#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
sahilmgandhi	18:6a4db94011d3	433	/**
sahilmgandhi	18:6a4db94011d3	434	* @}
sahilmgandhi	18:6a4db94011d3	435	*/
sahilmgandhi	18:6a4db94011d3	436
sahilmgandhi	18:6a4db94011d3	437	/** @defgroup DSI_LP_VACT DSI LP VACT
sahilmgandhi	18:6a4db94011d3	438	* @{
sahilmgandhi	18:6a4db94011d3	439	*/
sahilmgandhi	18:6a4db94011d3	440	#define DSI_LP_VACT_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	441	#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
sahilmgandhi	18:6a4db94011d3	442	/**
sahilmgandhi	18:6a4db94011d3	443	* @}
sahilmgandhi	18:6a4db94011d3	444	*/
sahilmgandhi	18:6a4db94011d3	445
sahilmgandhi	18:6a4db94011d3	446	/** @defgroup DSI_LP_VFP DSI LP VFP
sahilmgandhi	18:6a4db94011d3	447	* @{
sahilmgandhi	18:6a4db94011d3	448	*/
sahilmgandhi	18:6a4db94011d3	449	#define DSI_LP_VFP_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	450	#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
sahilmgandhi	18:6a4db94011d3	451	/**
sahilmgandhi	18:6a4db94011d3	452	* @}
sahilmgandhi	18:6a4db94011d3	453	*/
sahilmgandhi	18:6a4db94011d3	454
sahilmgandhi	18:6a4db94011d3	455	/** @defgroup DSI_LP_VBP DSI LP VBP
sahilmgandhi	18:6a4db94011d3	456	* @{
sahilmgandhi	18:6a4db94011d3	457	*/
sahilmgandhi	18:6a4db94011d3	458	#define DSI_LP_VBP_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	459	#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
sahilmgandhi	18:6a4db94011d3	460	/**
sahilmgandhi	18:6a4db94011d3	461	* @}
sahilmgandhi	18:6a4db94011d3	462	*/
sahilmgandhi	18:6a4db94011d3	463
sahilmgandhi	18:6a4db94011d3	464	/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
sahilmgandhi	18:6a4db94011d3	465	* @{
sahilmgandhi	18:6a4db94011d3	466	*/
sahilmgandhi	18:6a4db94011d3	467	#define DSI_LP_VSYNC_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	468	#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
sahilmgandhi	18:6a4db94011d3	469	/**
sahilmgandhi	18:6a4db94011d3	470	* @}
sahilmgandhi	18:6a4db94011d3	471	*/
sahilmgandhi	18:6a4db94011d3	472
sahilmgandhi	18:6a4db94011d3	473	/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
sahilmgandhi	18:6a4db94011d3	474	* @{
sahilmgandhi	18:6a4db94011d3	475	*/
sahilmgandhi	18:6a4db94011d3	476	#define DSI_FBTAA_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	477	#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
sahilmgandhi	18:6a4db94011d3	478	/**
sahilmgandhi	18:6a4db94011d3	479	* @}
sahilmgandhi	18:6a4db94011d3	480	*/
sahilmgandhi	18:6a4db94011d3	481
sahilmgandhi	18:6a4db94011d3	482	/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
sahilmgandhi	18:6a4db94011d3	483	* @{
sahilmgandhi	18:6a4db94011d3	484	*/
sahilmgandhi	18:6a4db94011d3	485	#define DSI_TE_DSILINK ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	486	#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
sahilmgandhi	18:6a4db94011d3	487	/**
sahilmgandhi	18:6a4db94011d3	488	* @}
sahilmgandhi	18:6a4db94011d3	489	*/
sahilmgandhi	18:6a4db94011d3	490
sahilmgandhi	18:6a4db94011d3	491	/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
sahilmgandhi	18:6a4db94011d3	492	* @{
sahilmgandhi	18:6a4db94011d3	493	*/
sahilmgandhi	18:6a4db94011d3	494	#define DSI_TE_RISING_EDGE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	495	#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
sahilmgandhi	18:6a4db94011d3	496	/**
sahilmgandhi	18:6a4db94011d3	497	* @}
sahilmgandhi	18:6a4db94011d3	498	*/
sahilmgandhi	18:6a4db94011d3	499
sahilmgandhi	18:6a4db94011d3	500	/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
sahilmgandhi	18:6a4db94011d3	501	* @{
sahilmgandhi	18:6a4db94011d3	502	*/
sahilmgandhi	18:6a4db94011d3	503	#define DSI_VSYNC_FALLING ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	504	#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
sahilmgandhi	18:6a4db94011d3	505	/**
sahilmgandhi	18:6a4db94011d3	506	* @}
sahilmgandhi	18:6a4db94011d3	507	*/
sahilmgandhi	18:6a4db94011d3	508
sahilmgandhi	18:6a4db94011d3	509	/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
sahilmgandhi	18:6a4db94011d3	510	* @{
sahilmgandhi	18:6a4db94011d3	511	*/
sahilmgandhi	18:6a4db94011d3	512	#define DSI_AR_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	513	#define DSI_AR_ENABLE DSI_WCFGR_AR
sahilmgandhi	18:6a4db94011d3	514	/**
sahilmgandhi	18:6a4db94011d3	515	* @}
sahilmgandhi	18:6a4db94011d3	516	*/
sahilmgandhi	18:6a4db94011d3	517
sahilmgandhi	18:6a4db94011d3	518	/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
sahilmgandhi	18:6a4db94011d3	519	* @{
sahilmgandhi	18:6a4db94011d3	520	*/
sahilmgandhi	18:6a4db94011d3	521	#define DSI_TE_ACKNOWLEDGE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	522	#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
sahilmgandhi	18:6a4db94011d3	523	/**
sahilmgandhi	18:6a4db94011d3	524	* @}
sahilmgandhi	18:6a4db94011d3	525	*/
sahilmgandhi	18:6a4db94011d3	526
sahilmgandhi	18:6a4db94011d3	527	/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
sahilmgandhi	18:6a4db94011d3	528	* @{
sahilmgandhi	18:6a4db94011d3	529	*/
sahilmgandhi	18:6a4db94011d3	530	#define DSI_ACKNOWLEDGE_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	531	#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
sahilmgandhi	18:6a4db94011d3	532	/**
sahilmgandhi	18:6a4db94011d3	533	* @}
sahilmgandhi	18:6a4db94011d3	534	*/
sahilmgandhi	18:6a4db94011d3	535
sahilmgandhi	18:6a4db94011d3	536	/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
sahilmgandhi	18:6a4db94011d3	537	* @{
sahilmgandhi	18:6a4db94011d3	538	*/
sahilmgandhi	18:6a4db94011d3	539	#define DSI_LP_GSW0P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	540	#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
sahilmgandhi	18:6a4db94011d3	541	/**
sahilmgandhi	18:6a4db94011d3	542	* @}
sahilmgandhi	18:6a4db94011d3	543	*/
sahilmgandhi	18:6a4db94011d3	544
sahilmgandhi	18:6a4db94011d3	545	/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
sahilmgandhi	18:6a4db94011d3	546	* @{
sahilmgandhi	18:6a4db94011d3	547	*/
sahilmgandhi	18:6a4db94011d3	548	#define DSI_LP_GSW1P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	549	#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
sahilmgandhi	18:6a4db94011d3	550	/**
sahilmgandhi	18:6a4db94011d3	551	* @}
sahilmgandhi	18:6a4db94011d3	552	*/
sahilmgandhi	18:6a4db94011d3	553
sahilmgandhi	18:6a4db94011d3	554	/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
sahilmgandhi	18:6a4db94011d3	555	* @{
sahilmgandhi	18:6a4db94011d3	556	*/
sahilmgandhi	18:6a4db94011d3	557	#define DSI_LP_GSW2P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	558	#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
sahilmgandhi	18:6a4db94011d3	559	/**
sahilmgandhi	18:6a4db94011d3	560	* @}
sahilmgandhi	18:6a4db94011d3	561	*/
sahilmgandhi	18:6a4db94011d3	562
sahilmgandhi	18:6a4db94011d3	563	/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
sahilmgandhi	18:6a4db94011d3	564	* @{
sahilmgandhi	18:6a4db94011d3	565	*/
sahilmgandhi	18:6a4db94011d3	566	#define DSI_LP_GSR0P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	567	#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
sahilmgandhi	18:6a4db94011d3	568	/**
sahilmgandhi	18:6a4db94011d3	569	* @}
sahilmgandhi	18:6a4db94011d3	570	*/
sahilmgandhi	18:6a4db94011d3	571
sahilmgandhi	18:6a4db94011d3	572	/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
sahilmgandhi	18:6a4db94011d3	573	* @{
sahilmgandhi	18:6a4db94011d3	574	*/
sahilmgandhi	18:6a4db94011d3	575	#define DSI_LP_GSR1P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	576	#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
sahilmgandhi	18:6a4db94011d3	577	/**
sahilmgandhi	18:6a4db94011d3	578	* @}
sahilmgandhi	18:6a4db94011d3	579	*/
sahilmgandhi	18:6a4db94011d3	580
sahilmgandhi	18:6a4db94011d3	581	/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
sahilmgandhi	18:6a4db94011d3	582	* @{
sahilmgandhi	18:6a4db94011d3	583	*/
sahilmgandhi	18:6a4db94011d3	584	#define DSI_LP_GSR2P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	585	#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
sahilmgandhi	18:6a4db94011d3	586	/**
sahilmgandhi	18:6a4db94011d3	587	* @}
sahilmgandhi	18:6a4db94011d3	588	*/
sahilmgandhi	18:6a4db94011d3	589
sahilmgandhi	18:6a4db94011d3	590	/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
sahilmgandhi	18:6a4db94011d3	591	* @{
sahilmgandhi	18:6a4db94011d3	592	*/
sahilmgandhi	18:6a4db94011d3	593	#define DSI_LP_GLW_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	594	#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
sahilmgandhi	18:6a4db94011d3	595	/**
sahilmgandhi	18:6a4db94011d3	596	* @}
sahilmgandhi	18:6a4db94011d3	597	*/
sahilmgandhi	18:6a4db94011d3	598
sahilmgandhi	18:6a4db94011d3	599	/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
sahilmgandhi	18:6a4db94011d3	600	* @{
sahilmgandhi	18:6a4db94011d3	601	*/
sahilmgandhi	18:6a4db94011d3	602	#define DSI_LP_DSW0P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	603	#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
sahilmgandhi	18:6a4db94011d3	604	/**
sahilmgandhi	18:6a4db94011d3	605	* @}
sahilmgandhi	18:6a4db94011d3	606	*/
sahilmgandhi	18:6a4db94011d3	607
sahilmgandhi	18:6a4db94011d3	608	/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
sahilmgandhi	18:6a4db94011d3	609	* @{
sahilmgandhi	18:6a4db94011d3	610	*/
sahilmgandhi	18:6a4db94011d3	611	#define DSI_LP_DSW1P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	612	#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
sahilmgandhi	18:6a4db94011d3	613	/**
sahilmgandhi	18:6a4db94011d3	614	* @}
sahilmgandhi	18:6a4db94011d3	615	*/
sahilmgandhi	18:6a4db94011d3	616
sahilmgandhi	18:6a4db94011d3	617	/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
sahilmgandhi	18:6a4db94011d3	618	* @{
sahilmgandhi	18:6a4db94011d3	619	*/
sahilmgandhi	18:6a4db94011d3	620	#define DSI_LP_DSR0P_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	621	#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
sahilmgandhi	18:6a4db94011d3	622	/**
sahilmgandhi	18:6a4db94011d3	623	* @}
sahilmgandhi	18:6a4db94011d3	624	*/
sahilmgandhi	18:6a4db94011d3	625
sahilmgandhi	18:6a4db94011d3	626	/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
sahilmgandhi	18:6a4db94011d3	627	* @{
sahilmgandhi	18:6a4db94011d3	628	*/
sahilmgandhi	18:6a4db94011d3	629	#define DSI_LP_DLW_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	630	#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
sahilmgandhi	18:6a4db94011d3	631	/**
sahilmgandhi	18:6a4db94011d3	632	* @}
sahilmgandhi	18:6a4db94011d3	633	*/
sahilmgandhi	18:6a4db94011d3	634
sahilmgandhi	18:6a4db94011d3	635	/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
sahilmgandhi	18:6a4db94011d3	636	* @{
sahilmgandhi	18:6a4db94011d3	637	*/
sahilmgandhi	18:6a4db94011d3	638	#define DSI_LP_MRDP_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	639	#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
sahilmgandhi	18:6a4db94011d3	640	/**
sahilmgandhi	18:6a4db94011d3	641	* @}
sahilmgandhi	18:6a4db94011d3	642	*/
sahilmgandhi	18:6a4db94011d3	643
sahilmgandhi	18:6a4db94011d3	644	/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
sahilmgandhi	18:6a4db94011d3	645	* @{
sahilmgandhi	18:6a4db94011d3	646	*/
sahilmgandhi	18:6a4db94011d3	647	#define DSI_HS_PM_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	648	#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
sahilmgandhi	18:6a4db94011d3	649	/**
sahilmgandhi	18:6a4db94011d3	650	* @}
sahilmgandhi	18:6a4db94011d3	651	*/
sahilmgandhi	18:6a4db94011d3	652
sahilmgandhi	18:6a4db94011d3	653
sahilmgandhi	18:6a4db94011d3	654	/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
sahilmgandhi	18:6a4db94011d3	655	* @{
sahilmgandhi	18:6a4db94011d3	656	*/
sahilmgandhi	18:6a4db94011d3	657	#define DSI_AUTO_CLK_LANE_CTRL_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	658	#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
sahilmgandhi	18:6a4db94011d3	659	/**
sahilmgandhi	18:6a4db94011d3	660	* @}
sahilmgandhi	18:6a4db94011d3	661	*/
sahilmgandhi	18:6a4db94011d3	662
sahilmgandhi	18:6a4db94011d3	663	/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
sahilmgandhi	18:6a4db94011d3	664	* @{
sahilmgandhi	18:6a4db94011d3	665	*/
sahilmgandhi	18:6a4db94011d3	666	#define DSI_ONE_DATA_LANE 0U
sahilmgandhi	18:6a4db94011d3	667	#define DSI_TWO_DATA_LANES 1U
sahilmgandhi	18:6a4db94011d3	668	/**
sahilmgandhi	18:6a4db94011d3	669	* @}
sahilmgandhi	18:6a4db94011d3	670	*/
sahilmgandhi	18:6a4db94011d3	671
sahilmgandhi	18:6a4db94011d3	672	/** @defgroup DSI_FlowControl DSI Flow Control
sahilmgandhi	18:6a4db94011d3	673	* @{
sahilmgandhi	18:6a4db94011d3	674	*/
sahilmgandhi	18:6a4db94011d3	675	#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
sahilmgandhi	18:6a4db94011d3	676	#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
sahilmgandhi	18:6a4db94011d3	677	#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
sahilmgandhi	18:6a4db94011d3	678	#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
sahilmgandhi	18:6a4db94011d3	679	#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
sahilmgandhi	18:6a4db94011d3	680	#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX \| DSI_FLOW_CONTROL_ECC_RX \| \
sahilmgandhi	18:6a4db94011d3	681	DSI_FLOW_CONTROL_BTA \| DSI_FLOW_CONTROL_EOTP_RX \| \
sahilmgandhi	18:6a4db94011d3	682	DSI_FLOW_CONTROL_EOTP_TX)
sahilmgandhi	18:6a4db94011d3	683	/**
sahilmgandhi	18:6a4db94011d3	684	* @}
sahilmgandhi	18:6a4db94011d3	685	*/
sahilmgandhi	18:6a4db94011d3	686
sahilmgandhi	18:6a4db94011d3	687	/** @defgroup DSI_Color_Coding DSI Color Coding
sahilmgandhi	18:6a4db94011d3	688	* @{
sahilmgandhi	18:6a4db94011d3	689	*/
sahilmgandhi	18:6a4db94011d3	690	#define DSI_RGB565 ((uint32_t)0x00000000U) /!< The values 0x00000001U and 0x00000002U can also be used for the RGB565 color mode configuration /
sahilmgandhi	18:6a4db94011d3	691	#define DSI_RGB666 ((uint32_t)0x00000003U) /!< The value 0x00000004U can also be used for the RGB666 color mode configuration /
sahilmgandhi	18:6a4db94011d3	692	#define DSI_RGB888 ((uint32_t)0x00000005U)
sahilmgandhi	18:6a4db94011d3	693	/**
sahilmgandhi	18:6a4db94011d3	694	* @}
sahilmgandhi	18:6a4db94011d3	695	*/
sahilmgandhi	18:6a4db94011d3	696
sahilmgandhi	18:6a4db94011d3	697	/** @defgroup DSI_LooselyPacked DSI Loosely Packed
sahilmgandhi	18:6a4db94011d3	698	* @{
sahilmgandhi	18:6a4db94011d3	699	*/
sahilmgandhi	18:6a4db94011d3	700	#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
sahilmgandhi	18:6a4db94011d3	701	#define DSI_LOOSELY_PACKED_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	702	/**
sahilmgandhi	18:6a4db94011d3	703	* @}
sahilmgandhi	18:6a4db94011d3	704	*/
sahilmgandhi	18:6a4db94011d3	705
sahilmgandhi	18:6a4db94011d3	706	/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
sahilmgandhi	18:6a4db94011d3	707	* @{
sahilmgandhi	18:6a4db94011d3	708	*/
sahilmgandhi	18:6a4db94011d3	709	#define DSI_HSYNC_ACTIVE_HIGH ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	710	#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
sahilmgandhi	18:6a4db94011d3	711	/**
sahilmgandhi	18:6a4db94011d3	712	* @}
sahilmgandhi	18:6a4db94011d3	713	*/
sahilmgandhi	18:6a4db94011d3	714
sahilmgandhi	18:6a4db94011d3	715	/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
sahilmgandhi	18:6a4db94011d3	716	* @{
sahilmgandhi	18:6a4db94011d3	717	*/
sahilmgandhi	18:6a4db94011d3	718	#define DSI_VSYNC_ACTIVE_HIGH ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	719	#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
sahilmgandhi	18:6a4db94011d3	720	/**
sahilmgandhi	18:6a4db94011d3	721	* @}
sahilmgandhi	18:6a4db94011d3	722	*/
sahilmgandhi	18:6a4db94011d3	723
sahilmgandhi	18:6a4db94011d3	724	/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
sahilmgandhi	18:6a4db94011d3	725	* @{
sahilmgandhi	18:6a4db94011d3	726	*/
sahilmgandhi	18:6a4db94011d3	727	#define DSI_DATA_ENABLE_ACTIVE_HIGH ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	728	#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
sahilmgandhi	18:6a4db94011d3	729	/**
sahilmgandhi	18:6a4db94011d3	730	* @}
sahilmgandhi	18:6a4db94011d3	731	*/
sahilmgandhi	18:6a4db94011d3	732
sahilmgandhi	18:6a4db94011d3	733	/** @defgroup DSI_PLL_IDF DSI PLL IDF
sahilmgandhi	18:6a4db94011d3	734	* @{
sahilmgandhi	18:6a4db94011d3	735	*/
sahilmgandhi	18:6a4db94011d3	736	#define DSI_PLL_IN_DIV1 ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	737	#define DSI_PLL_IN_DIV2 ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	738	#define DSI_PLL_IN_DIV3 ((uint32_t)0x00000003U)
sahilmgandhi	18:6a4db94011d3	739	#define DSI_PLL_IN_DIV4 ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	740	#define DSI_PLL_IN_DIV5 ((uint32_t)0x00000005U)
sahilmgandhi	18:6a4db94011d3	741	#define DSI_PLL_IN_DIV6 ((uint32_t)0x00000006U)
sahilmgandhi	18:6a4db94011d3	742	#define DSI_PLL_IN_DIV7 ((uint32_t)0x00000007U)
sahilmgandhi	18:6a4db94011d3	743	/**
sahilmgandhi	18:6a4db94011d3	744	* @}
sahilmgandhi	18:6a4db94011d3	745	*/
sahilmgandhi	18:6a4db94011d3	746
sahilmgandhi	18:6a4db94011d3	747	/** @defgroup DSI_PLL_ODF DSI PLL ODF
sahilmgandhi	18:6a4db94011d3	748	* @{
sahilmgandhi	18:6a4db94011d3	749	*/
sahilmgandhi	18:6a4db94011d3	750	#define DSI_PLL_OUT_DIV1 ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	751	#define DSI_PLL_OUT_DIV2 ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	752	#define DSI_PLL_OUT_DIV4 ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	753	#define DSI_PLL_OUT_DIV8 ((uint32_t)0x00000003U)
sahilmgandhi	18:6a4db94011d3	754	/**
sahilmgandhi	18:6a4db94011d3	755	* @}
sahilmgandhi	18:6a4db94011d3	756	*/
sahilmgandhi	18:6a4db94011d3	757
sahilmgandhi	18:6a4db94011d3	758	/** @defgroup DSI_Flags DSI Flags
sahilmgandhi	18:6a4db94011d3	759	* @{
sahilmgandhi	18:6a4db94011d3	760	*/
sahilmgandhi	18:6a4db94011d3	761	#define DSI_FLAG_TE DSI_WISR_TEIF
sahilmgandhi	18:6a4db94011d3	762	#define DSI_FLAG_ER DSI_WISR_ERIF
sahilmgandhi	18:6a4db94011d3	763	#define DSI_FLAG_BUSY DSI_WISR_BUSY
sahilmgandhi	18:6a4db94011d3	764	#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
sahilmgandhi	18:6a4db94011d3	765	#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
sahilmgandhi	18:6a4db94011d3	766	#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
sahilmgandhi	18:6a4db94011d3	767	#define DSI_FLAG_RRS DSI_WISR_RRS
sahilmgandhi	18:6a4db94011d3	768	#define DSI_FLAG_RR DSI_WISR_RRIF
sahilmgandhi	18:6a4db94011d3	769	/**
sahilmgandhi	18:6a4db94011d3	770	* @}
sahilmgandhi	18:6a4db94011d3	771	*/
sahilmgandhi	18:6a4db94011d3	772
sahilmgandhi	18:6a4db94011d3	773	/** @defgroup DSI_Interrupts DSI Interrupts
sahilmgandhi	18:6a4db94011d3	774	* @{
sahilmgandhi	18:6a4db94011d3	775	*/
sahilmgandhi	18:6a4db94011d3	776	#define DSI_IT_TE DSI_WIER_TEIE
sahilmgandhi	18:6a4db94011d3	777	#define DSI_IT_ER DSI_WIER_ERIE
sahilmgandhi	18:6a4db94011d3	778	#define DSI_IT_PLLL DSI_WIER_PLLLIE
sahilmgandhi	18:6a4db94011d3	779	#define DSI_IT_PLLU DSI_WIER_PLLUIE
sahilmgandhi	18:6a4db94011d3	780	#define DSI_IT_RR DSI_WIER_RRIE
sahilmgandhi	18:6a4db94011d3	781	/**
sahilmgandhi	18:6a4db94011d3	782	* @}
sahilmgandhi	18:6a4db94011d3	783	*/
sahilmgandhi	18:6a4db94011d3	784
sahilmgandhi	18:6a4db94011d3	785	/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
sahilmgandhi	18:6a4db94011d3	786	* @{
sahilmgandhi	18:6a4db94011d3	787	*/
sahilmgandhi	18:6a4db94011d3	788	#define DSI_DCS_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000005U) /!< DCS short write, no parameters /
sahilmgandhi	18:6a4db94011d3	789	#define DSI_DCS_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000015U) /!< DCS short write, one parameter /
sahilmgandhi	18:6a4db94011d3	790	#define DSI_GEN_SHORT_PKT_WRITE_P0 ((uint32_t)0x00000003U) /!< Generic short write, no parameters /
sahilmgandhi	18:6a4db94011d3	791	#define DSI_GEN_SHORT_PKT_WRITE_P1 ((uint32_t)0x00000013U) /!< Generic short write, one parameter /
sahilmgandhi	18:6a4db94011d3	792	#define DSI_GEN_SHORT_PKT_WRITE_P2 ((uint32_t)0x00000023U) /!< Generic short write, two parameters /
sahilmgandhi	18:6a4db94011d3	793	/**
sahilmgandhi	18:6a4db94011d3	794	* @}
sahilmgandhi	18:6a4db94011d3	795	*/
sahilmgandhi	18:6a4db94011d3	796
sahilmgandhi	18:6a4db94011d3	797	/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
sahilmgandhi	18:6a4db94011d3	798	* @{
sahilmgandhi	18:6a4db94011d3	799	*/
sahilmgandhi	18:6a4db94011d3	800	#define DSI_DCS_LONG_PKT_WRITE ((uint32_t)0x00000039U) /!< DCS long write /
sahilmgandhi	18:6a4db94011d3	801	#define DSI_GEN_LONG_PKT_WRITE ((uint32_t)0x00000029U) /!< Generic long write /
sahilmgandhi	18:6a4db94011d3	802	/**
sahilmgandhi	18:6a4db94011d3	803	* @}
sahilmgandhi	18:6a4db94011d3	804	*/
sahilmgandhi	18:6a4db94011d3	805
sahilmgandhi	18:6a4db94011d3	806	/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
sahilmgandhi	18:6a4db94011d3	807	* @{
sahilmgandhi	18:6a4db94011d3	808	*/
sahilmgandhi	18:6a4db94011d3	809	#define DSI_DCS_SHORT_PKT_READ ((uint32_t)0x00000006U) /!< DCS short read /
sahilmgandhi	18:6a4db94011d3	810	#define DSI_GEN_SHORT_PKT_READ_P0 ((uint32_t)0x00000004U) /!< Generic short read, no parameters /
sahilmgandhi	18:6a4db94011d3	811	#define DSI_GEN_SHORT_PKT_READ_P1 ((uint32_t)0x00000014U) /!< Generic short read, one parameter /
sahilmgandhi	18:6a4db94011d3	812	#define DSI_GEN_SHORT_PKT_READ_P2 ((uint32_t)0x00000024U) /!< Generic short read, two parameters /
sahilmgandhi	18:6a4db94011d3	813	/**
sahilmgandhi	18:6a4db94011d3	814	* @}
sahilmgandhi	18:6a4db94011d3	815	*/
sahilmgandhi	18:6a4db94011d3	816
sahilmgandhi	18:6a4db94011d3	817	/** @defgroup DSI_Error_Data_Type DSI Error Data Type
sahilmgandhi	18:6a4db94011d3	818	* @{
sahilmgandhi	18:6a4db94011d3	819	*/
sahilmgandhi	18:6a4db94011d3	820	#define HAL_DSI_ERROR_NONE 0
sahilmgandhi	18:6a4db94011d3	821	#define HAL_DSI_ERROR_ACK ((uint32_t)0x00000001U) /!< acknowledge errors /
sahilmgandhi	18:6a4db94011d3	822	#define HAL_DSI_ERROR_PHY ((uint32_t)0x00000002U) /!< PHY related errors /
sahilmgandhi	18:6a4db94011d3	823	#define HAL_DSI_ERROR_TX ((uint32_t)0x00000004U) /!< transmission error /
sahilmgandhi	18:6a4db94011d3	824	#define HAL_DSI_ERROR_RX ((uint32_t)0x00000008U) /!< reception error /
sahilmgandhi	18:6a4db94011d3	825	#define HAL_DSI_ERROR_ECC ((uint32_t)0x00000010U) /!< ECC errors /
sahilmgandhi	18:6a4db94011d3	826	#define HAL_DSI_ERROR_CRC ((uint32_t)0x00000020U) /!< CRC error /
sahilmgandhi	18:6a4db94011d3	827	#define HAL_DSI_ERROR_PSE ((uint32_t)0x00000040U) /!< Packet Size error /
sahilmgandhi	18:6a4db94011d3	828	#define HAL_DSI_ERROR_EOT ((uint32_t)0x00000080U) /!< End Of Transmission error /
sahilmgandhi	18:6a4db94011d3	829	#define HAL_DSI_ERROR_OVF ((uint32_t)0x00000100U) /!< FIFO overflow error /
sahilmgandhi	18:6a4db94011d3	830	#define HAL_DSI_ERROR_GEN ((uint32_t)0x00000200U) /!< Generic FIFO related errors /
sahilmgandhi	18:6a4db94011d3	831	/**
sahilmgandhi	18:6a4db94011d3	832	* @}
sahilmgandhi	18:6a4db94011d3	833	*/
sahilmgandhi	18:6a4db94011d3	834
sahilmgandhi	18:6a4db94011d3	835	/** @defgroup DSI_Lane_Group DSI Lane Group
sahilmgandhi	18:6a4db94011d3	836	* @{
sahilmgandhi	18:6a4db94011d3	837	*/
sahilmgandhi	18:6a4db94011d3	838	#define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	839	#define DSI_DATA_LANES ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	840	/**
sahilmgandhi	18:6a4db94011d3	841	* @}
sahilmgandhi	18:6a4db94011d3	842	*/
sahilmgandhi	18:6a4db94011d3	843
sahilmgandhi	18:6a4db94011d3	844	/** @defgroup DSI_Communication_Delay DSI Communication Delay
sahilmgandhi	18:6a4db94011d3	845	* @{
sahilmgandhi	18:6a4db94011d3	846	*/
sahilmgandhi	18:6a4db94011d3	847	#define DSI_SLEW_RATE_HSTX ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	848	#define DSI_SLEW_RATE_LPTX ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	849	#define DSI_HS_DELAY ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	850	/**
sahilmgandhi	18:6a4db94011d3	851	* @}
sahilmgandhi	18:6a4db94011d3	852	*/
sahilmgandhi	18:6a4db94011d3	853
sahilmgandhi	18:6a4db94011d3	854	/** @defgroup DSI_CustomLane DSI CustomLane
sahilmgandhi	18:6a4db94011d3	855	* @{
sahilmgandhi	18:6a4db94011d3	856	*/
sahilmgandhi	18:6a4db94011d3	857	#define DSI_SWAP_LANE_PINS ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	858	#define DSI_INVERT_HS_SIGNAL ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	859	/**
sahilmgandhi	18:6a4db94011d3	860	* @}
sahilmgandhi	18:6a4db94011d3	861	*/
sahilmgandhi	18:6a4db94011d3	862
sahilmgandhi	18:6a4db94011d3	863	/** @defgroup DSI_Lane_Select DSI Lane Select
sahilmgandhi	18:6a4db94011d3	864	* @{
sahilmgandhi	18:6a4db94011d3	865	*/
sahilmgandhi	18:6a4db94011d3	866	#define DSI_CLOCK_LANE ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	867	#define DSI_DATA_LANE0 ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	868	#define DSI_DATA_LANE1 ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	869	/**
sahilmgandhi	18:6a4db94011d3	870	* @}
sahilmgandhi	18:6a4db94011d3	871	*/
sahilmgandhi	18:6a4db94011d3	872
sahilmgandhi	18:6a4db94011d3	873	/** @defgroup DSI_PHY_Timing DSI PHY Timing
sahilmgandhi	18:6a4db94011d3	874	* @{
sahilmgandhi	18:6a4db94011d3	875	*/
sahilmgandhi	18:6a4db94011d3	876	#define DSI_TCLK_POST ((uint32_t)0x00000000U)
sahilmgandhi	18:6a4db94011d3	877	#define DSI_TLPX_CLK ((uint32_t)0x00000001U)
sahilmgandhi	18:6a4db94011d3	878	#define DSI_THS_EXIT ((uint32_t)0x00000002U)
sahilmgandhi	18:6a4db94011d3	879	#define DSI_TLPX_DATA ((uint32_t)0x00000003U)
sahilmgandhi	18:6a4db94011d3	880	#define DSI_THS_ZERO ((uint32_t)0x00000004U)
sahilmgandhi	18:6a4db94011d3	881	#define DSI_THS_TRAIL ((uint32_t)0x00000005U)
sahilmgandhi	18:6a4db94011d3	882	#define DSI_THS_PREPARE ((uint32_t)0x00000006U)
sahilmgandhi	18:6a4db94011d3	883	#define DSI_TCLK_ZERO ((uint32_t)0x00000007U)
sahilmgandhi	18:6a4db94011d3	884	#define DSI_TCLK_PREPARE ((uint32_t)0x00000008U)
sahilmgandhi	18:6a4db94011d3	885	/**
sahilmgandhi	18:6a4db94011d3	886	* @}
sahilmgandhi	18:6a4db94011d3	887	*/
sahilmgandhi	18:6a4db94011d3	888
sahilmgandhi	18:6a4db94011d3	889	/* Exported macros -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	890	/**
sahilmgandhi	18:6a4db94011d3	891	* @brief Enables the DSI host.
sahilmgandhi	18:6a4db94011d3	892	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	893	* @retval None.
sahilmgandhi	18:6a4db94011d3	894	*/
sahilmgandhi	18:6a4db94011d3	895	#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= DSI_CR_EN)
sahilmgandhi	18:6a4db94011d3	896
sahilmgandhi	18:6a4db94011d3	897	/**
sahilmgandhi	18:6a4db94011d3	898	* @brief Disables the DSI host.
sahilmgandhi	18:6a4db94011d3	899	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	900	* @retval None.
sahilmgandhi	18:6a4db94011d3	901	*/
sahilmgandhi	18:6a4db94011d3	902	#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)
sahilmgandhi	18:6a4db94011d3	903
sahilmgandhi	18:6a4db94011d3	904	/**
sahilmgandhi	18:6a4db94011d3	905	* @brief Enables the DSI wrapper.
sahilmgandhi	18:6a4db94011d3	906	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	907	* @retval None.
sahilmgandhi	18:6a4db94011d3	908	*/
sahilmgandhi	18:6a4db94011d3	909	#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR \|= DSI_WCR_DSIEN)
sahilmgandhi	18:6a4db94011d3	910
sahilmgandhi	18:6a4db94011d3	911	/**
sahilmgandhi	18:6a4db94011d3	912	* @brief Disable the DSI wrapper.
sahilmgandhi	18:6a4db94011d3	913	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	914	* @retval None.
sahilmgandhi	18:6a4db94011d3	915	*/
sahilmgandhi	18:6a4db94011d3	916	#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)
sahilmgandhi	18:6a4db94011d3	917
sahilmgandhi	18:6a4db94011d3	918	/**
sahilmgandhi	18:6a4db94011d3	919	* @brief Enables the DSI PLL.
sahilmgandhi	18:6a4db94011d3	920	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	921	* @retval None.
sahilmgandhi	18:6a4db94011d3	922	*/
sahilmgandhi	18:6a4db94011d3	923	#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR \|= DSI_WRPCR_PLLEN)
sahilmgandhi	18:6a4db94011d3	924
sahilmgandhi	18:6a4db94011d3	925	/**
sahilmgandhi	18:6a4db94011d3	926	* @brief Disables the DSI PLL.
sahilmgandhi	18:6a4db94011d3	927	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	928	* @retval None.
sahilmgandhi	18:6a4db94011d3	929	*/
sahilmgandhi	18:6a4db94011d3	930	#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)
sahilmgandhi	18:6a4db94011d3	931
sahilmgandhi	18:6a4db94011d3	932	/**
sahilmgandhi	18:6a4db94011d3	933	* @brief Enables the DSI regulator.
sahilmgandhi	18:6a4db94011d3	934	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	935	* @retval None.
sahilmgandhi	18:6a4db94011d3	936	*/
sahilmgandhi	18:6a4db94011d3	937	#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR \|= DSI_WRPCR_REGEN)
sahilmgandhi	18:6a4db94011d3	938
sahilmgandhi	18:6a4db94011d3	939	/**
sahilmgandhi	18:6a4db94011d3	940	* @brief Disables the DSI regulator.
sahilmgandhi	18:6a4db94011d3	941	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	942	* @retval None.
sahilmgandhi	18:6a4db94011d3	943	*/
sahilmgandhi	18:6a4db94011d3	944	#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)
sahilmgandhi	18:6a4db94011d3	945
sahilmgandhi	18:6a4db94011d3	946	/**
sahilmgandhi	18:6a4db94011d3	947	* @brief Get the DSI pending flags.
sahilmgandhi	18:6a4db94011d3	948	* @param __HANDLE__: DSI handle.
sahilmgandhi	18:6a4db94011d3	949	* @param __FLAG__: Get the specified flag.
sahilmgandhi	18:6a4db94011d3	950	* This parameter can be any combination of the following values:
sahilmgandhi	18:6a4db94011d3	951	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
sahilmgandhi	18:6a4db94011d3	952	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
sahilmgandhi	18:6a4db94011d3	953	* @arg DSI_FLAG_BUSY : Busy Flag
sahilmgandhi	18:6a4db94011d3	954	* @arg DSI_FLAG_PLLLS: PLL Lock Status
sahilmgandhi	18:6a4db94011d3	955	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
sahilmgandhi	18:6a4db94011d3	956	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
sahilmgandhi	18:6a4db94011d3	957	* @arg DSI_FLAG_RRS : Regulator Ready Flag
sahilmgandhi	18:6a4db94011d3	958	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
sahilmgandhi	18:6a4db94011d3	959	* @retval The state of FLAG (SET or RESET).
sahilmgandhi	18:6a4db94011d3	960	*/
sahilmgandhi	18:6a4db94011d3	961	#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
sahilmgandhi	18:6a4db94011d3	962
sahilmgandhi	18:6a4db94011d3	963	/**
sahilmgandhi	18:6a4db94011d3	964	* @brief Clears the DSI pending flags.
sahilmgandhi	18:6a4db94011d3	965	* @param __HANDLE__: DSI handle.
sahilmgandhi	18:6a4db94011d3	966	* @param __FLAG__: specifies the flag to clear.
sahilmgandhi	18:6a4db94011d3	967	* This parameter can be any combination of the following values:
sahilmgandhi	18:6a4db94011d3	968	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
sahilmgandhi	18:6a4db94011d3	969	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
sahilmgandhi	18:6a4db94011d3	970	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
sahilmgandhi	18:6a4db94011d3	971	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
sahilmgandhi	18:6a4db94011d3	972	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
sahilmgandhi	18:6a4db94011d3	973	* @retval None
sahilmgandhi	18:6a4db94011d3	974	*/
sahilmgandhi	18:6a4db94011d3	975	#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
sahilmgandhi	18:6a4db94011d3	976
sahilmgandhi	18:6a4db94011d3	977	/**
sahilmgandhi	18:6a4db94011d3	978	* @brief Enables the specified DSI interrupts.
sahilmgandhi	18:6a4db94011d3	979	* @param __HANDLE__: DSI handle.
sahilmgandhi	18:6a4db94011d3	980	* @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled.
sahilmgandhi	18:6a4db94011d3	981	* This parameter can be any combination of the following values:
sahilmgandhi	18:6a4db94011d3	982	* @arg DSI_IT_TE : Tearing Effect Interrupt
sahilmgandhi	18:6a4db94011d3	983	* @arg DSI_IT_ER : End of Refresh Interrupt
sahilmgandhi	18:6a4db94011d3	984	* @arg DSI_IT_PLLL: PLL Lock Interrupt
sahilmgandhi	18:6a4db94011d3	985	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
sahilmgandhi	18:6a4db94011d3	986	* @arg DSI_IT_RR : Regulator Ready Interrupt
sahilmgandhi	18:6a4db94011d3	987	* @retval None
sahilmgandhi	18:6a4db94011d3	988	*/
sahilmgandhi	18:6a4db94011d3	989	#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER \|= (__INTERRUPT__))
sahilmgandhi	18:6a4db94011d3	990
sahilmgandhi	18:6a4db94011d3	991	/**
sahilmgandhi	18:6a4db94011d3	992	* @brief Disables the specified DSI interrupts.
sahilmgandhi	18:6a4db94011d3	993	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	994	* @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled.
sahilmgandhi	18:6a4db94011d3	995	* This parameter can be any combination of the following values:
sahilmgandhi	18:6a4db94011d3	996	* @arg DSI_IT_TE : Tearing Effect Interrupt
sahilmgandhi	18:6a4db94011d3	997	* @arg DSI_IT_ER : End of Refresh Interrupt
sahilmgandhi	18:6a4db94011d3	998	* @arg DSI_IT_PLLL: PLL Lock Interrupt
sahilmgandhi	18:6a4db94011d3	999	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
sahilmgandhi	18:6a4db94011d3	1000	* @arg DSI_IT_RR : Regulator Ready Interrupt
sahilmgandhi	18:6a4db94011d3	1001	* @retval None
sahilmgandhi	18:6a4db94011d3	1002	*/
sahilmgandhi	18:6a4db94011d3	1003	#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
sahilmgandhi	18:6a4db94011d3	1004
sahilmgandhi	18:6a4db94011d3	1005	/**
sahilmgandhi	18:6a4db94011d3	1006	* @brief Checks whether the specified DSI interrupt has occurred or not.
sahilmgandhi	18:6a4db94011d3	1007	* @param __HANDLE__: DSI handle
sahilmgandhi	18:6a4db94011d3	1008	* @param __INTERRUPT__: specifies the DSI interrupt source to check.
sahilmgandhi	18:6a4db94011d3	1009	* This parameter can be one of the following values:
sahilmgandhi	18:6a4db94011d3	1010	* @arg DSI_IT_TE : Tearing Effect Interrupt
sahilmgandhi	18:6a4db94011d3	1011	* @arg DSI_IT_ER : End of Refresh Interrupt
sahilmgandhi	18:6a4db94011d3	1012	* @arg DSI_IT_PLLL: PLL Lock Interrupt
sahilmgandhi	18:6a4db94011d3	1013	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
sahilmgandhi	18:6a4db94011d3	1014	* @arg DSI_IT_RR : Regulator Ready Interrupt
sahilmgandhi	18:6a4db94011d3	1015	* @retval The state of INTERRUPT (SET or RESET).
sahilmgandhi	18:6a4db94011d3	1016	*/
sahilmgandhi	18:6a4db94011d3	1017	#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WISR & (__INTERRUPT__))
sahilmgandhi	18:6a4db94011d3	1018
sahilmgandhi	18:6a4db94011d3	1019	/* Exported functions --------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1020	/** @defgroup DSI_Exported_Functions DSI Exported Functions
sahilmgandhi	18:6a4db94011d3	1021	* @{
sahilmgandhi	18:6a4db94011d3	1022	*/
sahilmgandhi	18:6a4db94011d3	1023	HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef hdsi, DSI_PLLInitTypeDef PLLInit);
sahilmgandhi	18:6a4db94011d3	1024	HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1025	void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1026	void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1027
sahilmgandhi	18:6a4db94011d3	1028	void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1029	void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1030	void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1031	void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1032
sahilmgandhi	18:6a4db94011d3	1033	HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
sahilmgandhi	18:6a4db94011d3	1034	HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef hdsi, DSI_VidCfgTypeDef VidCfg);
sahilmgandhi	18:6a4db94011d3	1035	HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef hdsi, DSI_CmdCfgTypeDef CmdCfg);
sahilmgandhi	18:6a4db94011d3	1036	HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef hdsi, DSI_LPCmdTypeDef LPCmd);
sahilmgandhi	18:6a4db94011d3	1037	HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
sahilmgandhi	18:6a4db94011d3	1038	HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef hdsi, DSI_PHY_TimerTypeDef PhyTimers);
sahilmgandhi	18:6a4db94011d3	1039	HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef hdsi, DSI_HOST_TimeoutTypeDef HostTimeouts);
sahilmgandhi	18:6a4db94011d3	1040	HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1041	HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1042	HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1043	HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
sahilmgandhi	18:6a4db94011d3	1044	HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
sahilmgandhi	18:6a4db94011d3	1045	HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
sahilmgandhi	18:6a4db94011d3	1046	uint32_t ChannelID,
sahilmgandhi	18:6a4db94011d3	1047	uint32_t Mode,
sahilmgandhi	18:6a4db94011d3	1048	uint32_t Param1,
sahilmgandhi	18:6a4db94011d3	1049	uint32_t Param2);
sahilmgandhi	18:6a4db94011d3	1050	HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
sahilmgandhi	18:6a4db94011d3	1051	uint32_t ChannelID,
sahilmgandhi	18:6a4db94011d3	1052	uint32_t Mode,
sahilmgandhi	18:6a4db94011d3	1053	uint32_t NbParams,
sahilmgandhi	18:6a4db94011d3	1054	uint32_t Param1,
sahilmgandhi	18:6a4db94011d3	1055	uint8_t* ParametersTable);
sahilmgandhi	18:6a4db94011d3	1056	HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
sahilmgandhi	18:6a4db94011d3	1057	uint32_t ChannelNbr,
sahilmgandhi	18:6a4db94011d3	1058	uint8_t* Array,
sahilmgandhi	18:6a4db94011d3	1059	uint32_t Size,
sahilmgandhi	18:6a4db94011d3	1060	uint32_t Mode,
sahilmgandhi	18:6a4db94011d3	1061	uint32_t DCSCmd,
sahilmgandhi	18:6a4db94011d3	1062	uint8_t* ParametersTable);
sahilmgandhi	18:6a4db94011d3	1063	HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1064	HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1065	HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1066	HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1067
sahilmgandhi	18:6a4db94011d3	1068	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
sahilmgandhi	18:6a4db94011d3	1069	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1070
sahilmgandhi	18:6a4db94011d3	1071	HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
sahilmgandhi	18:6a4db94011d3	1072	HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
sahilmgandhi	18:6a4db94011d3	1073	HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
sahilmgandhi	18:6a4db94011d3	1074	HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
sahilmgandhi	18:6a4db94011d3	1075	HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
sahilmgandhi	18:6a4db94011d3	1076	HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
sahilmgandhi	18:6a4db94011d3	1077	HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
sahilmgandhi	18:6a4db94011d3	1078	HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
sahilmgandhi	18:6a4db94011d3	1079	HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
sahilmgandhi	18:6a4db94011d3	1080	HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
sahilmgandhi	18:6a4db94011d3	1081
sahilmgandhi	18:6a4db94011d3	1082	uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1083	HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
sahilmgandhi	18:6a4db94011d3	1084	HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
sahilmgandhi	18:6a4db94011d3	1085	/**
sahilmgandhi	18:6a4db94011d3	1086	* @}
sahilmgandhi	18:6a4db94011d3	1087	*/
sahilmgandhi	18:6a4db94011d3	1088
sahilmgandhi	18:6a4db94011d3	1089	/* Private types -------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1090	/** @defgroup DSI_Private_Types DSI Private Types
sahilmgandhi	18:6a4db94011d3	1091	* @{
sahilmgandhi	18:6a4db94011d3	1092	*/
sahilmgandhi	18:6a4db94011d3	1093
sahilmgandhi	18:6a4db94011d3	1094	/**
sahilmgandhi	18:6a4db94011d3	1095	* @}
sahilmgandhi	18:6a4db94011d3	1096	*/
sahilmgandhi	18:6a4db94011d3	1097
sahilmgandhi	18:6a4db94011d3	1098	/* Private defines -----------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1099	/** @defgroup DSI_Private_Defines DSI Private Defines
sahilmgandhi	18:6a4db94011d3	1100	* @{
sahilmgandhi	18:6a4db94011d3	1101	*/
sahilmgandhi	18:6a4db94011d3	1102
sahilmgandhi	18:6a4db94011d3	1103	/**
sahilmgandhi	18:6a4db94011d3	1104	* @}
sahilmgandhi	18:6a4db94011d3	1105	*/
sahilmgandhi	18:6a4db94011d3	1106
sahilmgandhi	18:6a4db94011d3	1107	/* Private variables ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1108	/** @defgroup DSI_Private_Variables DSI Private Variables
sahilmgandhi	18:6a4db94011d3	1109	* @{
sahilmgandhi	18:6a4db94011d3	1110	*/
sahilmgandhi	18:6a4db94011d3	1111
sahilmgandhi	18:6a4db94011d3	1112	/**
sahilmgandhi	18:6a4db94011d3	1113	* @}
sahilmgandhi	18:6a4db94011d3	1114	*/
sahilmgandhi	18:6a4db94011d3	1115
sahilmgandhi	18:6a4db94011d3	1116	/* Private constants ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1117	/** @defgroup DSI_Private_Constants DSI Private Constants
sahilmgandhi	18:6a4db94011d3	1118	* @{
sahilmgandhi	18:6a4db94011d3	1119	*/
sahilmgandhi	18:6a4db94011d3	1120	#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037U) /!< Maximum return packet configuration /
sahilmgandhi	18:6a4db94011d3	1121	/**
sahilmgandhi	18:6a4db94011d3	1122	* @}
sahilmgandhi	18:6a4db94011d3	1123	*/
sahilmgandhi	18:6a4db94011d3	1124
sahilmgandhi	18:6a4db94011d3	1125	/* Private macros ------------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1126	/** @defgroup DSI_Private_Macros DSI Private Macros
sahilmgandhi	18:6a4db94011d3	1127	* @{
sahilmgandhi	18:6a4db94011d3	1128	*/
sahilmgandhi	18:6a4db94011d3	1129	#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
sahilmgandhi	18:6a4db94011d3	1130	#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) \|\| \
sahilmgandhi	18:6a4db94011d3	1131	((IDF) == DSI_PLL_IN_DIV2) \|\| \
sahilmgandhi	18:6a4db94011d3	1132	((IDF) == DSI_PLL_IN_DIV3) \|\| \
sahilmgandhi	18:6a4db94011d3	1133	((IDF) == DSI_PLL_IN_DIV4) \|\| \
sahilmgandhi	18:6a4db94011d3	1134	((IDF) == DSI_PLL_IN_DIV5) \|\| \
sahilmgandhi	18:6a4db94011d3	1135	((IDF) == DSI_PLL_IN_DIV6) \|\| \
sahilmgandhi	18:6a4db94011d3	1136	((IDF) == DSI_PLL_IN_DIV7))
sahilmgandhi	18:6a4db94011d3	1137	#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) \|\| \
sahilmgandhi	18:6a4db94011d3	1138	((ODF) == DSI_PLL_OUT_DIV2) \|\| \
sahilmgandhi	18:6a4db94011d3	1139	((ODF) == DSI_PLL_OUT_DIV4) \|\| \
sahilmgandhi	18:6a4db94011d3	1140	((ODF) == DSI_PLL_OUT_DIV8))
sahilmgandhi	18:6a4db94011d3	1141	#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) \|\| ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
sahilmgandhi	18:6a4db94011d3	1142	#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) \|\| ((NumberOfLanes) == DSI_TWO_DATA_LANES))
sahilmgandhi	18:6a4db94011d3	1143	#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) \| DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
sahilmgandhi	18:6a4db94011d3	1144	#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
sahilmgandhi	18:6a4db94011d3	1145	#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) \|\| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
sahilmgandhi	18:6a4db94011d3	1146	#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) \|\| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
sahilmgandhi	18:6a4db94011d3	1147	#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) \|\| ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
sahilmgandhi	18:6a4db94011d3	1148	#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) \|\| ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
sahilmgandhi	18:6a4db94011d3	1149	#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) \|\| \
sahilmgandhi	18:6a4db94011d3	1150	((VideoModeType) == DSI_VID_MODE_NB_EVENTS) \|\| \
sahilmgandhi	18:6a4db94011d3	1151	((VideoModeType) == DSI_VID_MODE_BURST))
sahilmgandhi	18:6a4db94011d3	1152	#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) \|\| ((ColorMode) == DSI_COLOR_MODE_EIGHT))
sahilmgandhi	18:6a4db94011d3	1153	#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) \|\| ((ShutDown) == DSI_DISPLAY_OFF))
sahilmgandhi	18:6a4db94011d3	1154	#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) \|\| ((LPCommand) == DSI_LP_COMMAND_ENABLE))
sahilmgandhi	18:6a4db94011d3	1155	#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) \|\| ((LPHFP) == DSI_LP_HFP_ENABLE))
sahilmgandhi	18:6a4db94011d3	1156	#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) \|\| ((LPHBP) == DSI_LP_HBP_ENABLE))
sahilmgandhi	18:6a4db94011d3	1157	#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) \|\| ((LPVActive) == DSI_LP_VACT_ENABLE))
sahilmgandhi	18:6a4db94011d3	1158	#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) \|\| ((LPVFP) == DSI_LP_VFP_ENABLE))
sahilmgandhi	18:6a4db94011d3	1159	#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) \|\| ((LPVBP) == DSI_LP_VBP_ENABLE))
sahilmgandhi	18:6a4db94011d3	1160	#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) \|\| ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
sahilmgandhi	18:6a4db94011d3	1161	#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) \|\| ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
sahilmgandhi	18:6a4db94011d3	1162	#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) \|\| ((TESource) == DSI_TE_EXTERNAL))
sahilmgandhi	18:6a4db94011d3	1163	#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) \|\| ((TEPolarity) == DSI_TE_FALLING_EDGE))
sahilmgandhi	18:6a4db94011d3	1164	#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) \|\| ((AutomaticRefresh) == DSI_AR_ENABLE))
sahilmgandhi	18:6a4db94011d3	1165	#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) \|\| ((VSPolarity) == DSI_VSYNC_RISING))
sahilmgandhi	18:6a4db94011d3	1166	#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) \|\| ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
sahilmgandhi	18:6a4db94011d3	1167	#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) \|\| ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
sahilmgandhi	18:6a4db94011d3	1168	#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) \|\| ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1169	#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) \|\| ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1170	#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) \|\| ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1171	#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) \|\| ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1172	#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) \|\| ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1173	#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) \|\| ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1174	#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) \|\| ((LP_GLW) == DSI_LP_GLW_ENABLE))
sahilmgandhi	18:6a4db94011d3	1175	#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) \|\| ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1176	#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) \|\| ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1177	#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) \|\| ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
sahilmgandhi	18:6a4db94011d3	1178	#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) \|\| ((LP_DLW) == DSI_LP_DLW_ENABLE))
sahilmgandhi	18:6a4db94011d3	1179	#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) \|\| ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
sahilmgandhi	18:6a4db94011d3	1180	#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) \|\| \
sahilmgandhi	18:6a4db94011d3	1181	((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) \|\| \
sahilmgandhi	18:6a4db94011d3	1182	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) \|\| \
sahilmgandhi	18:6a4db94011d3	1183	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) \|\| \
sahilmgandhi	18:6a4db94011d3	1184	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
sahilmgandhi	18:6a4db94011d3	1185	#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) \|\| \
sahilmgandhi	18:6a4db94011d3	1186	((MODE) == DSI_GEN_LONG_PKT_WRITE))
sahilmgandhi	18:6a4db94011d3	1187	#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) \|\| \
sahilmgandhi	18:6a4db94011d3	1188	((MODE) == DSI_GEN_SHORT_PKT_READ_P0) \|\| \
sahilmgandhi	18:6a4db94011d3	1189	((MODE) == DSI_GEN_SHORT_PKT_READ_P1) \|\| \
sahilmgandhi	18:6a4db94011d3	1190	((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
sahilmgandhi	18:6a4db94011d3	1191	#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) \|\| ((CommDelay) == DSI_SLEW_RATE_LPTX) \|\| ((CommDelay) == DSI_HS_DELAY))
sahilmgandhi	18:6a4db94011d3	1192	#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANES))
sahilmgandhi	18:6a4db94011d3	1193	#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) \|\| ((CustomLane) == DSI_INVERT_HS_SIGNAL))
sahilmgandhi	18:6a4db94011d3	1194	#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANE0) \|\| ((Lane) == DSI_DATA_LANE1))
sahilmgandhi	18:6a4db94011d3	1195	#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) \|\| \
sahilmgandhi	18:6a4db94011d3	1196	((Timing) == DSI_TLPX_CLK ) \|\| \
sahilmgandhi	18:6a4db94011d3	1197	((Timing) == DSI_THS_EXIT ) \|\| \
sahilmgandhi	18:6a4db94011d3	1198	((Timing) == DSI_TLPX_DATA ) \|\| \
sahilmgandhi	18:6a4db94011d3	1199	((Timing) == DSI_THS_ZERO ) \|\| \
sahilmgandhi	18:6a4db94011d3	1200	((Timing) == DSI_THS_TRAIL ) \|\| \
sahilmgandhi	18:6a4db94011d3	1201	((Timing) == DSI_THS_PREPARE ) \|\| \
sahilmgandhi	18:6a4db94011d3	1202	((Timing) == DSI_TCLK_ZERO ) \|\| \
sahilmgandhi	18:6a4db94011d3	1203	((Timing) == DSI_TCLK_PREPARE))
sahilmgandhi	18:6a4db94011d3	1204
sahilmgandhi	18:6a4db94011d3	1205	/**
sahilmgandhi	18:6a4db94011d3	1206	* @}
sahilmgandhi	18:6a4db94011d3	1207	*/
sahilmgandhi	18:6a4db94011d3	1208
sahilmgandhi	18:6a4db94011d3	1209	/* Private functions prototypes ----------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1210	/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
sahilmgandhi	18:6a4db94011d3	1211	* @{
sahilmgandhi	18:6a4db94011d3	1212	*/
sahilmgandhi	18:6a4db94011d3	1213
sahilmgandhi	18:6a4db94011d3	1214	/**
sahilmgandhi	18:6a4db94011d3	1215	* @}
sahilmgandhi	18:6a4db94011d3	1216	*/
sahilmgandhi	18:6a4db94011d3	1217
sahilmgandhi	18:6a4db94011d3	1218	/* Private functions ---------------------------------------------------------*/
sahilmgandhi	18:6a4db94011d3	1219	/** @defgroup DSI_Private_Functions DSI Private Functions
sahilmgandhi	18:6a4db94011d3	1220	* @{
sahilmgandhi	18:6a4db94011d3	1221	*/
sahilmgandhi	18:6a4db94011d3	1222
sahilmgandhi	18:6a4db94011d3	1223	/**
sahilmgandhi	18:6a4db94011d3	1224	* @}
sahilmgandhi	18:6a4db94011d3	1225	*/
sahilmgandhi	18:6a4db94011d3	1226
sahilmgandhi	18:6a4db94011d3	1227	/**
sahilmgandhi	18:6a4db94011d3	1228	* @}
sahilmgandhi	18:6a4db94011d3	1229	*/
sahilmgandhi	18:6a4db94011d3	1230
sahilmgandhi	18:6a4db94011d3	1231	/**
sahilmgandhi	18:6a4db94011d3	1232	* @}
sahilmgandhi	18:6a4db94011d3	1233	*/
sahilmgandhi	18:6a4db94011d3	1234	#endif /* STM32F469xx \|\| STM32F479xx */
sahilmgandhi	18:6a4db94011d3	1235
sahilmgandhi	18:6a4db94011d3	1236	#ifdef __cplusplus
sahilmgandhi	18:6a4db94011d3	1237	}
sahilmgandhi	18:6a4db94011d3	1238	#endif
sahilmgandhi	18:6a4db94011d3	1239
sahilmgandhi	18:6a4db94011d3	1240	#endif /* __STM32F4xx_HAL_DSI_H */
sahilmgandhi	18:6a4db94011d3	1241
sahilmgandhi	18:6a4db94011d3	1242	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	25 Apr 2017
Imports:	29
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	2
Followers:	5

The code in this repository is Apache licensed.

mbed-dev/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h@46:b156ef445742, 2017-06-03 (annotated)

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